1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* Microsemi Ocelot Switch driver 3 * Copyright (c) 2019 Microsemi Corporation 4 */ 5 6 #include <linux/iopoll.h> 7 #include <linux/proc_fs.h> 8 9 #include <soc/mscc/ocelot_vcap.h> 10 #include "ocelot_police.h" 11 #include "ocelot_vcap.h" 12 #include "ocelot_s2.h" 13 14 #define OCELOT_POLICER_DISCARD 0x17f 15 #define ENTRY_WIDTH 32 16 17 enum vcap_sel { 18 VCAP_SEL_ENTRY = 0x1, 19 VCAP_SEL_ACTION = 0x2, 20 VCAP_SEL_COUNTER = 0x4, 21 VCAP_SEL_ALL = 0x7, 22 }; 23 24 enum vcap_cmd { 25 VCAP_CMD_WRITE = 0, /* Copy from Cache to TCAM */ 26 VCAP_CMD_READ = 1, /* Copy from TCAM to Cache */ 27 VCAP_CMD_MOVE_UP = 2, /* Move <count> up */ 28 VCAP_CMD_MOVE_DOWN = 3, /* Move <count> down */ 29 VCAP_CMD_INITIALIZE = 4, /* Write all (from cache) */ 30 }; 31 32 #define VCAP_ENTRY_WIDTH 12 /* Max entry width (32bit words) */ 33 #define VCAP_COUNTER_WIDTH 4 /* Max counter width (32bit words) */ 34 35 struct vcap_data { 36 u32 entry[VCAP_ENTRY_WIDTH]; /* ENTRY_DAT */ 37 u32 mask[VCAP_ENTRY_WIDTH]; /* MASK_DAT */ 38 u32 action[VCAP_ENTRY_WIDTH]; /* ACTION_DAT */ 39 u32 counter[VCAP_COUNTER_WIDTH]; /* CNT_DAT */ 40 u32 tg; /* TG_DAT */ 41 u32 type; /* Action type */ 42 u32 tg_sw; /* Current type-group */ 43 u32 cnt; /* Current counter */ 44 u32 key_offset; /* Current entry offset */ 45 u32 action_offset; /* Current action offset */ 46 u32 counter_offset; /* Current counter offset */ 47 u32 tg_value; /* Current type-group value */ 48 u32 tg_mask; /* Current type-group mask */ 49 }; 50 51 static u32 vcap_s2_read_update_ctrl(struct ocelot *ocelot) 52 { 53 return ocelot_read(ocelot, S2_CORE_UPDATE_CTRL); 54 } 55 56 static void vcap_cmd(struct ocelot *ocelot, u16 ix, int cmd, int sel) 57 { 58 const struct vcap_props *vcap_is2 = &ocelot->vcap[VCAP_IS2]; 59 60 u32 value = (S2_CORE_UPDATE_CTRL_UPDATE_CMD(cmd) | 61 S2_CORE_UPDATE_CTRL_UPDATE_ADDR(ix) | 62 S2_CORE_UPDATE_CTRL_UPDATE_SHOT); 63 64 if ((sel & VCAP_SEL_ENTRY) && ix >= vcap_is2->entry_count) 65 return; 66 67 if (!(sel & VCAP_SEL_ENTRY)) 68 value |= S2_CORE_UPDATE_CTRL_UPDATE_ENTRY_DIS; 69 70 if (!(sel & VCAP_SEL_ACTION)) 71 value |= S2_CORE_UPDATE_CTRL_UPDATE_ACTION_DIS; 72 73 if (!(sel & VCAP_SEL_COUNTER)) 74 value |= S2_CORE_UPDATE_CTRL_UPDATE_CNT_DIS; 75 76 ocelot_write(ocelot, value, S2_CORE_UPDATE_CTRL); 77 readx_poll_timeout(vcap_s2_read_update_ctrl, ocelot, value, 78 (value & S2_CORE_UPDATE_CTRL_UPDATE_SHOT) == 0, 79 10, 100000); 80 } 81 82 /* Convert from 0-based row to VCAP entry row and run command */ 83 static void vcap_row_cmd(struct ocelot *ocelot, u32 row, int cmd, int sel) 84 { 85 const struct vcap_props *vcap_is2 = &ocelot->vcap[VCAP_IS2]; 86 87 vcap_cmd(ocelot, vcap_is2->entry_count - row - 1, cmd, sel); 88 } 89 90 static void vcap_entry2cache(struct ocelot *ocelot, struct vcap_data *data) 91 { 92 const struct vcap_props *vcap_is2 = &ocelot->vcap[VCAP_IS2]; 93 u32 entry_words, i; 94 95 entry_words = DIV_ROUND_UP(vcap_is2->entry_width, ENTRY_WIDTH); 96 97 for (i = 0; i < entry_words; i++) { 98 ocelot_write_rix(ocelot, data->entry[i], S2_CACHE_ENTRY_DAT, i); 99 ocelot_write_rix(ocelot, ~data->mask[i], S2_CACHE_MASK_DAT, i); 100 } 101 ocelot_write(ocelot, data->tg, S2_CACHE_TG_DAT); 102 } 103 104 static void vcap_cache2entry(struct ocelot *ocelot, struct vcap_data *data) 105 { 106 const struct vcap_props *vcap_is2 = &ocelot->vcap[VCAP_IS2]; 107 u32 entry_words, i; 108 109 entry_words = DIV_ROUND_UP(vcap_is2->entry_width, ENTRY_WIDTH); 110 111 for (i = 0; i < entry_words; i++) { 112 data->entry[i] = ocelot_read_rix(ocelot, S2_CACHE_ENTRY_DAT, i); 113 // Invert mask 114 data->mask[i] = ~ocelot_read_rix(ocelot, S2_CACHE_MASK_DAT, i); 115 } 116 data->tg = ocelot_read(ocelot, S2_CACHE_TG_DAT); 117 } 118 119 static void vcap_action2cache(struct ocelot *ocelot, struct vcap_data *data) 120 { 121 const struct vcap_props *vcap_is2 = &ocelot->vcap[VCAP_IS2]; 122 u32 action_words, mask; 123 int i, width; 124 125 /* Encode action type */ 126 width = vcap_is2->action_type_width; 127 if (width) { 128 mask = GENMASK(width, 0); 129 data->action[0] = ((data->action[0] & ~mask) | data->type); 130 } 131 132 action_words = DIV_ROUND_UP(vcap_is2->action_width, ENTRY_WIDTH); 133 134 for (i = 0; i < action_words; i++) 135 ocelot_write_rix(ocelot, data->action[i], S2_CACHE_ACTION_DAT, 136 i); 137 138 for (i = 0; i < vcap_is2->counter_words; i++) 139 ocelot_write_rix(ocelot, data->counter[i], S2_CACHE_CNT_DAT, i); 140 } 141 142 static void vcap_cache2action(struct ocelot *ocelot, struct vcap_data *data) 143 { 144 const struct vcap_props *vcap_is2 = &ocelot->vcap[VCAP_IS2]; 145 u32 action_words; 146 int i, width; 147 148 action_words = DIV_ROUND_UP(vcap_is2->action_width, ENTRY_WIDTH); 149 150 for (i = 0; i < action_words; i++) 151 data->action[i] = ocelot_read_rix(ocelot, S2_CACHE_ACTION_DAT, 152 i); 153 154 for (i = 0; i < vcap_is2->counter_words; i++) 155 data->counter[i] = ocelot_read_rix(ocelot, S2_CACHE_CNT_DAT, i); 156 157 /* Extract action type */ 158 width = vcap_is2->action_type_width; 159 data->type = (width ? (data->action[0] & GENMASK(width, 0)) : 0); 160 } 161 162 /* Calculate offsets for entry */ 163 static void is2_data_get(struct ocelot *ocelot, struct vcap_data *data, int ix) 164 { 165 const struct vcap_props *vcap_is2 = &ocelot->vcap[VCAP_IS2]; 166 int i, col, offset, count, cnt, base; 167 int width = vcap_is2->tg_width; 168 169 count = (data->tg_sw == VCAP_TG_HALF ? 2 : 4); 170 col = (ix % 2); 171 cnt = (vcap_is2->sw_count / count); 172 base = (vcap_is2->sw_count - col * cnt - cnt); 173 data->tg_value = 0; 174 data->tg_mask = 0; 175 for (i = 0; i < cnt; i++) { 176 offset = ((base + i) * width); 177 data->tg_value |= (data->tg_sw << offset); 178 data->tg_mask |= GENMASK(offset + width - 1, offset); 179 } 180 181 /* Calculate key/action/counter offsets */ 182 col = (count - col - 1); 183 data->key_offset = (base * vcap_is2->entry_width) / vcap_is2->sw_count; 184 data->counter_offset = (cnt * col * vcap_is2->counter_width); 185 i = data->type; 186 width = vcap_is2->action_table[i].width; 187 cnt = vcap_is2->action_table[i].count; 188 data->action_offset = 189 (((cnt * col * width) / count) + vcap_is2->action_type_width); 190 } 191 192 static void vcap_data_set(u32 *data, u32 offset, u32 len, u32 value) 193 { 194 u32 i, v, m; 195 196 for (i = 0; i < len; i++, offset++) { 197 v = data[offset / ENTRY_WIDTH]; 198 m = (1 << (offset % ENTRY_WIDTH)); 199 if (value & (1 << i)) 200 v |= m; 201 else 202 v &= ~m; 203 data[offset / ENTRY_WIDTH] = v; 204 } 205 } 206 207 static u32 vcap_data_get(u32 *data, u32 offset, u32 len) 208 { 209 u32 i, v, m, value = 0; 210 211 for (i = 0; i < len; i++, offset++) { 212 v = data[offset / ENTRY_WIDTH]; 213 m = (1 << (offset % ENTRY_WIDTH)); 214 if (v & m) 215 value |= (1 << i); 216 } 217 return value; 218 } 219 220 static void vcap_key_field_set(struct vcap_data *data, u32 offset, u32 width, 221 u32 value, u32 mask) 222 { 223 vcap_data_set(data->entry, offset + data->key_offset, width, value); 224 vcap_data_set(data->mask, offset + data->key_offset, width, mask); 225 } 226 227 static void vcap_key_set(struct ocelot *ocelot, struct vcap_data *data, 228 enum vcap_is2_half_key_field field, 229 u32 value, u32 mask) 230 { 231 u32 offset = ocelot->vcap_is2_keys[field].offset; 232 u32 length = ocelot->vcap_is2_keys[field].length; 233 234 vcap_key_field_set(data, offset, length, value, mask); 235 } 236 237 static void vcap_key_bytes_set(struct ocelot *ocelot, struct vcap_data *data, 238 enum vcap_is2_half_key_field field, 239 u8 *val, u8 *msk) 240 { 241 u32 offset = ocelot->vcap_is2_keys[field].offset; 242 u32 count = ocelot->vcap_is2_keys[field].length; 243 u32 i, j, n = 0, value = 0, mask = 0; 244 245 WARN_ON(count % 8); 246 247 /* Data wider than 32 bits are split up in chunks of maximum 32 bits. 248 * The 32 LSB of the data are written to the 32 MSB of the TCAM. 249 */ 250 offset += count; 251 count /= 8; 252 253 for (i = 0; i < count; i++) { 254 j = (count - i - 1); 255 value += (val[j] << n); 256 mask += (msk[j] << n); 257 n += 8; 258 if (n == ENTRY_WIDTH || (i + 1) == count) { 259 offset -= n; 260 vcap_key_field_set(data, offset, n, value, mask); 261 n = 0; 262 value = 0; 263 mask = 0; 264 } 265 } 266 } 267 268 static void vcap_key_l4_port_set(struct ocelot *ocelot, struct vcap_data *data, 269 enum vcap_is2_half_key_field field, 270 struct ocelot_vcap_udp_tcp *port) 271 { 272 u32 offset = ocelot->vcap_is2_keys[field].offset; 273 u32 length = ocelot->vcap_is2_keys[field].length; 274 275 WARN_ON(length != 16); 276 277 vcap_key_field_set(data, offset, length, port->value, port->mask); 278 } 279 280 static void vcap_key_bit_set(struct ocelot *ocelot, struct vcap_data *data, 281 enum vcap_is2_half_key_field field, 282 enum ocelot_vcap_bit val) 283 { 284 u32 offset = ocelot->vcap_is2_keys[field].offset; 285 u32 length = ocelot->vcap_is2_keys[field].length; 286 u32 value = (val == OCELOT_VCAP_BIT_1 ? 1 : 0); 287 u32 msk = (val == OCELOT_VCAP_BIT_ANY ? 0 : 1); 288 289 WARN_ON(length != 1); 290 291 vcap_key_field_set(data, offset, length, value, msk); 292 } 293 294 static void vcap_action_set(struct ocelot *ocelot, struct vcap_data *data, 295 enum vcap_is2_action_field field, u32 value) 296 { 297 int offset = ocelot->vcap_is2_actions[field].offset; 298 int length = ocelot->vcap_is2_actions[field].length; 299 300 vcap_data_set(data->action, offset + data->action_offset, length, 301 value); 302 } 303 304 static void is2_action_set(struct ocelot *ocelot, struct vcap_data *data, 305 struct ocelot_vcap_filter *filter) 306 { 307 switch (filter->action) { 308 case OCELOT_VCAP_ACTION_DROP: 309 vcap_action_set(ocelot, data, VCAP_IS2_ACT_PORT_MASK, 0); 310 vcap_action_set(ocelot, data, VCAP_IS2_ACT_MASK_MODE, 1); 311 vcap_action_set(ocelot, data, VCAP_IS2_ACT_POLICE_ENA, 1); 312 vcap_action_set(ocelot, data, VCAP_IS2_ACT_POLICE_IDX, 313 OCELOT_POLICER_DISCARD); 314 vcap_action_set(ocelot, data, VCAP_IS2_ACT_CPU_QU_NUM, 0); 315 vcap_action_set(ocelot, data, VCAP_IS2_ACT_CPU_COPY_ENA, 0); 316 break; 317 case OCELOT_VCAP_ACTION_TRAP: 318 vcap_action_set(ocelot, data, VCAP_IS2_ACT_PORT_MASK, 0); 319 vcap_action_set(ocelot, data, VCAP_IS2_ACT_MASK_MODE, 1); 320 vcap_action_set(ocelot, data, VCAP_IS2_ACT_POLICE_ENA, 0); 321 vcap_action_set(ocelot, data, VCAP_IS2_ACT_POLICE_IDX, 0); 322 vcap_action_set(ocelot, data, VCAP_IS2_ACT_CPU_QU_NUM, 0); 323 vcap_action_set(ocelot, data, VCAP_IS2_ACT_CPU_COPY_ENA, 1); 324 break; 325 case OCELOT_VCAP_ACTION_POLICE: 326 vcap_action_set(ocelot, data, VCAP_IS2_ACT_PORT_MASK, 0); 327 vcap_action_set(ocelot, data, VCAP_IS2_ACT_MASK_MODE, 0); 328 vcap_action_set(ocelot, data, VCAP_IS2_ACT_POLICE_ENA, 1); 329 vcap_action_set(ocelot, data, VCAP_IS2_ACT_POLICE_IDX, 330 filter->pol_ix); 331 vcap_action_set(ocelot, data, VCAP_IS2_ACT_CPU_QU_NUM, 0); 332 vcap_action_set(ocelot, data, VCAP_IS2_ACT_CPU_COPY_ENA, 0); 333 break; 334 } 335 } 336 337 static void is2_entry_set(struct ocelot *ocelot, int ix, 338 struct ocelot_vcap_filter *filter) 339 { 340 const struct vcap_props *vcap_is2 = &ocelot->vcap[VCAP_IS2]; 341 struct ocelot_vcap_key_vlan *tag = &filter->vlan; 342 u32 val, msk, type, type_mask = 0xf, i, count; 343 struct ocelot_vcap_u64 payload; 344 struct vcap_data data; 345 int row = (ix / 2); 346 347 memset(&payload, 0, sizeof(payload)); 348 memset(&data, 0, sizeof(data)); 349 350 /* Read row */ 351 vcap_row_cmd(ocelot, row, VCAP_CMD_READ, VCAP_SEL_ALL); 352 vcap_cache2entry(ocelot, &data); 353 vcap_cache2action(ocelot, &data); 354 355 data.tg_sw = VCAP_TG_HALF; 356 is2_data_get(ocelot, &data, ix); 357 data.tg = (data.tg & ~data.tg_mask); 358 if (filter->prio != 0) 359 data.tg |= data.tg_value; 360 361 data.type = IS2_ACTION_TYPE_NORMAL; 362 363 vcap_key_set(ocelot, &data, VCAP_IS2_HK_PAG, 0, 0); 364 vcap_key_set(ocelot, &data, VCAP_IS2_HK_IGR_PORT_MASK, 0, 365 ~filter->ingress_port_mask); 366 vcap_key_bit_set(ocelot, &data, VCAP_IS2_HK_FIRST, OCELOT_VCAP_BIT_1); 367 vcap_key_bit_set(ocelot, &data, VCAP_IS2_HK_HOST_MATCH, 368 OCELOT_VCAP_BIT_ANY); 369 vcap_key_bit_set(ocelot, &data, VCAP_IS2_HK_L2_MC, filter->dmac_mc); 370 vcap_key_bit_set(ocelot, &data, VCAP_IS2_HK_L2_BC, filter->dmac_bc); 371 vcap_key_bit_set(ocelot, &data, VCAP_IS2_HK_VLAN_TAGGED, tag->tagged); 372 vcap_key_set(ocelot, &data, VCAP_IS2_HK_VID, 373 tag->vid.value, tag->vid.mask); 374 vcap_key_set(ocelot, &data, VCAP_IS2_HK_PCP, 375 tag->pcp.value[0], tag->pcp.mask[0]); 376 vcap_key_bit_set(ocelot, &data, VCAP_IS2_HK_DEI, tag->dei); 377 378 switch (filter->key_type) { 379 case OCELOT_VCAP_KEY_ETYPE: { 380 struct ocelot_vcap_key_etype *etype = &filter->key.etype; 381 382 type = IS2_TYPE_ETYPE; 383 vcap_key_bytes_set(ocelot, &data, VCAP_IS2_HK_L2_DMAC, 384 etype->dmac.value, etype->dmac.mask); 385 vcap_key_bytes_set(ocelot, &data, VCAP_IS2_HK_L2_SMAC, 386 etype->smac.value, etype->smac.mask); 387 vcap_key_bytes_set(ocelot, &data, VCAP_IS2_HK_MAC_ETYPE_ETYPE, 388 etype->etype.value, etype->etype.mask); 389 /* Clear unused bits */ 390 vcap_key_set(ocelot, &data, VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0, 391 0, 0); 392 vcap_key_set(ocelot, &data, VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1, 393 0, 0); 394 vcap_key_set(ocelot, &data, VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2, 395 0, 0); 396 vcap_key_bytes_set(ocelot, &data, 397 VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0, 398 etype->data.value, etype->data.mask); 399 break; 400 } 401 case OCELOT_VCAP_KEY_LLC: { 402 struct ocelot_vcap_key_llc *llc = &filter->key.llc; 403 404 type = IS2_TYPE_LLC; 405 vcap_key_bytes_set(ocelot, &data, VCAP_IS2_HK_L2_DMAC, 406 llc->dmac.value, llc->dmac.mask); 407 vcap_key_bytes_set(ocelot, &data, VCAP_IS2_HK_L2_SMAC, 408 llc->smac.value, llc->smac.mask); 409 for (i = 0; i < 4; i++) { 410 payload.value[i] = llc->llc.value[i]; 411 payload.mask[i] = llc->llc.mask[i]; 412 } 413 vcap_key_bytes_set(ocelot, &data, VCAP_IS2_HK_MAC_LLC_L2_LLC, 414 payload.value, payload.mask); 415 break; 416 } 417 case OCELOT_VCAP_KEY_SNAP: { 418 struct ocelot_vcap_key_snap *snap = &filter->key.snap; 419 420 type = IS2_TYPE_SNAP; 421 vcap_key_bytes_set(ocelot, &data, VCAP_IS2_HK_L2_DMAC, 422 snap->dmac.value, snap->dmac.mask); 423 vcap_key_bytes_set(ocelot, &data, VCAP_IS2_HK_L2_SMAC, 424 snap->smac.value, snap->smac.mask); 425 vcap_key_bytes_set(ocelot, &data, VCAP_IS2_HK_MAC_SNAP_L2_SNAP, 426 filter->key.snap.snap.value, 427 filter->key.snap.snap.mask); 428 break; 429 } 430 case OCELOT_VCAP_KEY_ARP: { 431 struct ocelot_vcap_key_arp *arp = &filter->key.arp; 432 433 type = IS2_TYPE_ARP; 434 vcap_key_bytes_set(ocelot, &data, VCAP_IS2_HK_MAC_ARP_SMAC, 435 arp->smac.value, arp->smac.mask); 436 vcap_key_bit_set(ocelot, &data, 437 VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK, 438 arp->ethernet); 439 vcap_key_bit_set(ocelot, &data, 440 VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK, 441 arp->ip); 442 vcap_key_bit_set(ocelot, &data, 443 VCAP_IS2_HK_MAC_ARP_LEN_OK, 444 arp->length); 445 vcap_key_bit_set(ocelot, &data, 446 VCAP_IS2_HK_MAC_ARP_TARGET_MATCH, 447 arp->dmac_match); 448 vcap_key_bit_set(ocelot, &data, 449 VCAP_IS2_HK_MAC_ARP_SENDER_MATCH, 450 arp->smac_match); 451 vcap_key_bit_set(ocelot, &data, 452 VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN, 453 arp->unknown); 454 455 /* OPCODE is inverse, bit 0 is reply flag, bit 1 is RARP flag */ 456 val = ((arp->req == OCELOT_VCAP_BIT_0 ? 1 : 0) | 457 (arp->arp == OCELOT_VCAP_BIT_0 ? 2 : 0)); 458 msk = ((arp->req == OCELOT_VCAP_BIT_ANY ? 0 : 1) | 459 (arp->arp == OCELOT_VCAP_BIT_ANY ? 0 : 2)); 460 vcap_key_set(ocelot, &data, VCAP_IS2_HK_MAC_ARP_OPCODE, 461 val, msk); 462 vcap_key_bytes_set(ocelot, &data, 463 VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP, 464 arp->dip.value.addr, arp->dip.mask.addr); 465 vcap_key_bytes_set(ocelot, &data, 466 VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP, 467 arp->sip.value.addr, arp->sip.mask.addr); 468 vcap_key_set(ocelot, &data, VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP, 469 0, 0); 470 break; 471 } 472 case OCELOT_VCAP_KEY_IPV4: 473 case OCELOT_VCAP_KEY_IPV6: { 474 enum ocelot_vcap_bit sip_eq_dip, sport_eq_dport, seq_zero, tcp; 475 enum ocelot_vcap_bit ttl, fragment, options, tcp_ack, tcp_urg; 476 enum ocelot_vcap_bit tcp_fin, tcp_syn, tcp_rst, tcp_psh; 477 struct ocelot_vcap_key_ipv4 *ipv4 = NULL; 478 struct ocelot_vcap_key_ipv6 *ipv6 = NULL; 479 struct ocelot_vcap_udp_tcp *sport, *dport; 480 struct ocelot_vcap_ipv4 sip, dip; 481 struct ocelot_vcap_u8 proto, ds; 482 struct ocelot_vcap_u48 *ip_data; 483 484 if (filter->key_type == OCELOT_VCAP_KEY_IPV4) { 485 ipv4 = &filter->key.ipv4; 486 ttl = ipv4->ttl; 487 fragment = ipv4->fragment; 488 options = ipv4->options; 489 proto = ipv4->proto; 490 ds = ipv4->ds; 491 ip_data = &ipv4->data; 492 sip = ipv4->sip; 493 dip = ipv4->dip; 494 sport = &ipv4->sport; 495 dport = &ipv4->dport; 496 tcp_fin = ipv4->tcp_fin; 497 tcp_syn = ipv4->tcp_syn; 498 tcp_rst = ipv4->tcp_rst; 499 tcp_psh = ipv4->tcp_psh; 500 tcp_ack = ipv4->tcp_ack; 501 tcp_urg = ipv4->tcp_urg; 502 sip_eq_dip = ipv4->sip_eq_dip; 503 sport_eq_dport = ipv4->sport_eq_dport; 504 seq_zero = ipv4->seq_zero; 505 } else { 506 ipv6 = &filter->key.ipv6; 507 ttl = ipv6->ttl; 508 fragment = OCELOT_VCAP_BIT_ANY; 509 options = OCELOT_VCAP_BIT_ANY; 510 proto = ipv6->proto; 511 ds = ipv6->ds; 512 ip_data = &ipv6->data; 513 for (i = 0; i < 8; i++) { 514 val = ipv6->sip.value[i + 8]; 515 msk = ipv6->sip.mask[i + 8]; 516 if (i < 4) { 517 dip.value.addr[i] = val; 518 dip.mask.addr[i] = msk; 519 } else { 520 sip.value.addr[i - 4] = val; 521 sip.mask.addr[i - 4] = msk; 522 } 523 } 524 sport = &ipv6->sport; 525 dport = &ipv6->dport; 526 tcp_fin = ipv6->tcp_fin; 527 tcp_syn = ipv6->tcp_syn; 528 tcp_rst = ipv6->tcp_rst; 529 tcp_psh = ipv6->tcp_psh; 530 tcp_ack = ipv6->tcp_ack; 531 tcp_urg = ipv6->tcp_urg; 532 sip_eq_dip = ipv6->sip_eq_dip; 533 sport_eq_dport = ipv6->sport_eq_dport; 534 seq_zero = ipv6->seq_zero; 535 } 536 537 vcap_key_bit_set(ocelot, &data, VCAP_IS2_HK_IP4, 538 ipv4 ? OCELOT_VCAP_BIT_1 : OCELOT_VCAP_BIT_0); 539 vcap_key_bit_set(ocelot, &data, VCAP_IS2_HK_L3_FRAGMENT, 540 fragment); 541 vcap_key_set(ocelot, &data, VCAP_IS2_HK_L3_FRAG_OFS_GT0, 0, 0); 542 vcap_key_bit_set(ocelot, &data, VCAP_IS2_HK_L3_OPTIONS, 543 options); 544 vcap_key_bit_set(ocelot, &data, VCAP_IS2_HK_IP4_L3_TTL_GT0, 545 ttl); 546 vcap_key_bytes_set(ocelot, &data, VCAP_IS2_HK_L3_TOS, 547 ds.value, ds.mask); 548 vcap_key_bytes_set(ocelot, &data, VCAP_IS2_HK_L3_IP4_DIP, 549 dip.value.addr, dip.mask.addr); 550 vcap_key_bytes_set(ocelot, &data, VCAP_IS2_HK_L3_IP4_SIP, 551 sip.value.addr, sip.mask.addr); 552 vcap_key_bit_set(ocelot, &data, VCAP_IS2_HK_DIP_EQ_SIP, 553 sip_eq_dip); 554 val = proto.value[0]; 555 msk = proto.mask[0]; 556 type = IS2_TYPE_IP_UDP_TCP; 557 if (msk == 0xff && (val == 6 || val == 17)) { 558 /* UDP/TCP protocol match */ 559 tcp = (val == 6 ? 560 OCELOT_VCAP_BIT_1 : OCELOT_VCAP_BIT_0); 561 vcap_key_bit_set(ocelot, &data, VCAP_IS2_HK_TCP, tcp); 562 vcap_key_l4_port_set(ocelot, &data, 563 VCAP_IS2_HK_L4_DPORT, dport); 564 vcap_key_l4_port_set(ocelot, &data, 565 VCAP_IS2_HK_L4_SPORT, sport); 566 vcap_key_set(ocelot, &data, VCAP_IS2_HK_L4_RNG, 0, 0); 567 vcap_key_bit_set(ocelot, &data, 568 VCAP_IS2_HK_L4_SPORT_EQ_DPORT, 569 sport_eq_dport); 570 vcap_key_bit_set(ocelot, &data, 571 VCAP_IS2_HK_L4_SEQUENCE_EQ0, 572 seq_zero); 573 vcap_key_bit_set(ocelot, &data, VCAP_IS2_HK_L4_FIN, 574 tcp_fin); 575 vcap_key_bit_set(ocelot, &data, VCAP_IS2_HK_L4_SYN, 576 tcp_syn); 577 vcap_key_bit_set(ocelot, &data, VCAP_IS2_HK_L4_RST, 578 tcp_rst); 579 vcap_key_bit_set(ocelot, &data, VCAP_IS2_HK_L4_PSH, 580 tcp_psh); 581 vcap_key_bit_set(ocelot, &data, VCAP_IS2_HK_L4_ACK, 582 tcp_ack); 583 vcap_key_bit_set(ocelot, &data, VCAP_IS2_HK_L4_URG, 584 tcp_urg); 585 vcap_key_set(ocelot, &data, VCAP_IS2_HK_L4_1588_DOM, 586 0, 0); 587 vcap_key_set(ocelot, &data, VCAP_IS2_HK_L4_1588_VER, 588 0, 0); 589 } else { 590 if (msk == 0) { 591 /* Any IP protocol match */ 592 type_mask = IS2_TYPE_MASK_IP_ANY; 593 } else { 594 /* Non-UDP/TCP protocol match */ 595 type = IS2_TYPE_IP_OTHER; 596 for (i = 0; i < 6; i++) { 597 payload.value[i] = ip_data->value[i]; 598 payload.mask[i] = ip_data->mask[i]; 599 } 600 } 601 vcap_key_bytes_set(ocelot, &data, 602 VCAP_IS2_HK_IP4_L3_PROTO, 603 proto.value, proto.mask); 604 vcap_key_bytes_set(ocelot, &data, 605 VCAP_IS2_HK_L3_PAYLOAD, 606 payload.value, payload.mask); 607 } 608 break; 609 } 610 case OCELOT_VCAP_KEY_ANY: 611 default: 612 type = 0; 613 type_mask = 0; 614 count = vcap_is2->entry_width / 2; 615 /* Iterate over the non-common part of the key and 616 * clear entry data 617 */ 618 for (i = ocelot->vcap_is2_keys[VCAP_IS2_HK_L2_DMAC].offset; 619 i < count; i += ENTRY_WIDTH) { 620 vcap_key_field_set(&data, i, min(32u, count - i), 0, 0); 621 } 622 break; 623 } 624 625 vcap_key_set(ocelot, &data, VCAP_IS2_TYPE, type, type_mask); 626 is2_action_set(ocelot, &data, filter); 627 vcap_data_set(data.counter, data.counter_offset, 628 vcap_is2->counter_width, filter->stats.pkts); 629 630 /* Write row */ 631 vcap_entry2cache(ocelot, &data); 632 vcap_action2cache(ocelot, &data); 633 vcap_row_cmd(ocelot, row, VCAP_CMD_WRITE, VCAP_SEL_ALL); 634 } 635 636 static void is2_entry_get(struct ocelot *ocelot, struct ocelot_vcap_filter *filter, 637 int ix) 638 { 639 const struct vcap_props *vcap_is2 = &ocelot->vcap[VCAP_IS2]; 640 struct vcap_data data; 641 int row = (ix / 2); 642 u32 cnt; 643 644 vcap_row_cmd(ocelot, row, VCAP_CMD_READ, VCAP_SEL_COUNTER); 645 vcap_cache2action(ocelot, &data); 646 data.tg_sw = VCAP_TG_HALF; 647 is2_data_get(ocelot, &data, ix); 648 cnt = vcap_data_get(data.counter, data.counter_offset, 649 vcap_is2->counter_width); 650 651 filter->stats.pkts = cnt; 652 } 653 654 static int ocelot_vcap_policer_add(struct ocelot *ocelot, u32 pol_ix, 655 struct ocelot_policer *pol) 656 { 657 struct qos_policer_conf pp = { 0 }; 658 659 if (!pol) 660 return -EINVAL; 661 662 pp.mode = MSCC_QOS_RATE_MODE_DATA; 663 pp.pir = pol->rate; 664 pp.pbs = pol->burst; 665 666 return qos_policer_conf_set(ocelot, 0, pol_ix, &pp); 667 } 668 669 static void ocelot_vcap_policer_del(struct ocelot *ocelot, 670 struct ocelot_vcap_block *block, 671 u32 pol_ix) 672 { 673 struct ocelot_vcap_filter *filter; 674 struct qos_policer_conf pp = {0}; 675 int index = -1; 676 677 if (pol_ix < block->pol_lpr) 678 return; 679 680 list_for_each_entry(filter, &block->rules, list) { 681 index++; 682 if (filter->action == OCELOT_VCAP_ACTION_POLICE && 683 filter->pol_ix < pol_ix) { 684 filter->pol_ix += 1; 685 ocelot_vcap_policer_add(ocelot, filter->pol_ix, 686 &filter->pol); 687 is2_entry_set(ocelot, index, filter); 688 } 689 } 690 691 pp.mode = MSCC_QOS_RATE_MODE_DISABLED; 692 qos_policer_conf_set(ocelot, 0, pol_ix, &pp); 693 694 block->pol_lpr++; 695 } 696 697 static void ocelot_vcap_filter_add_to_block(struct ocelot *ocelot, 698 struct ocelot_vcap_block *block, 699 struct ocelot_vcap_filter *filter) 700 { 701 struct ocelot_vcap_filter *tmp; 702 struct list_head *pos, *n; 703 704 if (filter->action == OCELOT_VCAP_ACTION_POLICE) { 705 block->pol_lpr--; 706 filter->pol_ix = block->pol_lpr; 707 ocelot_vcap_policer_add(ocelot, filter->pol_ix, &filter->pol); 708 } 709 710 block->count++; 711 712 if (list_empty(&block->rules)) { 713 list_add(&filter->list, &block->rules); 714 return; 715 } 716 717 list_for_each_safe(pos, n, &block->rules) { 718 tmp = list_entry(pos, struct ocelot_vcap_filter, list); 719 if (filter->prio < tmp->prio) 720 break; 721 } 722 list_add(&filter->list, pos->prev); 723 } 724 725 static int ocelot_vcap_block_get_filter_index(struct ocelot_vcap_block *block, 726 struct ocelot_vcap_filter *filter) 727 { 728 struct ocelot_vcap_filter *tmp; 729 int index = -1; 730 731 list_for_each_entry(tmp, &block->rules, list) { 732 ++index; 733 if (filter->id == tmp->id) 734 break; 735 } 736 return index; 737 } 738 739 static struct ocelot_vcap_filter* 740 ocelot_vcap_block_find_filter(struct ocelot_vcap_block *block, 741 int index) 742 { 743 struct ocelot_vcap_filter *tmp; 744 int i = 0; 745 746 list_for_each_entry(tmp, &block->rules, list) { 747 if (i == index) 748 return tmp; 749 ++i; 750 } 751 752 return NULL; 753 } 754 755 /* If @on=false, then SNAP, ARP, IP and OAM frames will not match on keys based 756 * on destination and source MAC addresses, but only on higher-level protocol 757 * information. The only frame types to match on keys containing MAC addresses 758 * in this case are non-SNAP, non-ARP, non-IP and non-OAM frames. 759 * 760 * If @on=true, then the above frame types (SNAP, ARP, IP and OAM) will match 761 * on MAC_ETYPE keys such as destination and source MAC on this ingress port. 762 * However the setting has the side effect of making these frames not matching 763 * on any _other_ keys than MAC_ETYPE ones. 764 */ 765 static void ocelot_match_all_as_mac_etype(struct ocelot *ocelot, int port, 766 bool on) 767 { 768 u32 val = 0; 769 770 if (on) 771 val = ANA_PORT_VCAP_S2_CFG_S2_SNAP_DIS(3) | 772 ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS(3) | 773 ANA_PORT_VCAP_S2_CFG_S2_IP_TCPUDP_DIS(3) | 774 ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS(3) | 775 ANA_PORT_VCAP_S2_CFG_S2_OAM_DIS(3); 776 777 ocelot_rmw_gix(ocelot, val, 778 ANA_PORT_VCAP_S2_CFG_S2_SNAP_DIS_M | 779 ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS_M | 780 ANA_PORT_VCAP_S2_CFG_S2_IP_TCPUDP_DIS_M | 781 ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS_M | 782 ANA_PORT_VCAP_S2_CFG_S2_OAM_DIS_M, 783 ANA_PORT_VCAP_S2_CFG, port); 784 } 785 786 static bool 787 ocelot_vcap_is_problematic_mac_etype(struct ocelot_vcap_filter *filter) 788 { 789 u16 proto, mask; 790 791 if (filter->key_type != OCELOT_VCAP_KEY_ETYPE) 792 return false; 793 794 proto = ntohs(*(__be16 *)filter->key.etype.etype.value); 795 mask = ntohs(*(__be16 *)filter->key.etype.etype.mask); 796 797 /* ETH_P_ALL match, so all protocols below are included */ 798 if (mask == 0) 799 return true; 800 if (proto == ETH_P_ARP) 801 return true; 802 if (proto == ETH_P_IP) 803 return true; 804 if (proto == ETH_P_IPV6) 805 return true; 806 807 return false; 808 } 809 810 static bool 811 ocelot_vcap_is_problematic_non_mac_etype(struct ocelot_vcap_filter *filter) 812 { 813 if (filter->key_type == OCELOT_VCAP_KEY_SNAP) 814 return true; 815 if (filter->key_type == OCELOT_VCAP_KEY_ARP) 816 return true; 817 if (filter->key_type == OCELOT_VCAP_KEY_IPV4) 818 return true; 819 if (filter->key_type == OCELOT_VCAP_KEY_IPV6) 820 return true; 821 return false; 822 } 823 824 static bool 825 ocelot_exclusive_mac_etype_filter_rules(struct ocelot *ocelot, 826 struct ocelot_vcap_filter *filter) 827 { 828 struct ocelot_vcap_block *block = &ocelot->block; 829 struct ocelot_vcap_filter *tmp; 830 unsigned long port; 831 int i; 832 833 if (ocelot_vcap_is_problematic_mac_etype(filter)) { 834 /* Search for any non-MAC_ETYPE rules on the port */ 835 for (i = 0; i < block->count; i++) { 836 tmp = ocelot_vcap_block_find_filter(block, i); 837 if (tmp->ingress_port_mask & filter->ingress_port_mask && 838 ocelot_vcap_is_problematic_non_mac_etype(tmp)) 839 return false; 840 } 841 842 for_each_set_bit(port, &filter->ingress_port_mask, 843 ocelot->num_phys_ports) 844 ocelot_match_all_as_mac_etype(ocelot, port, true); 845 } else if (ocelot_vcap_is_problematic_non_mac_etype(filter)) { 846 /* Search for any MAC_ETYPE rules on the port */ 847 for (i = 0; i < block->count; i++) { 848 tmp = ocelot_vcap_block_find_filter(block, i); 849 if (tmp->ingress_port_mask & filter->ingress_port_mask && 850 ocelot_vcap_is_problematic_mac_etype(tmp)) 851 return false; 852 } 853 854 for_each_set_bit(port, &filter->ingress_port_mask, 855 ocelot->num_phys_ports) 856 ocelot_match_all_as_mac_etype(ocelot, port, false); 857 } 858 859 return true; 860 } 861 862 int ocelot_vcap_filter_add(struct ocelot *ocelot, 863 struct ocelot_vcap_filter *filter, 864 struct netlink_ext_ack *extack) 865 { 866 struct ocelot_vcap_block *block = &ocelot->block; 867 int i, index; 868 869 if (!ocelot_exclusive_mac_etype_filter_rules(ocelot, filter)) { 870 NL_SET_ERR_MSG_MOD(extack, 871 "Cannot mix MAC_ETYPE with non-MAC_ETYPE rules"); 872 return -EBUSY; 873 } 874 875 /* Add filter to the linked list */ 876 ocelot_vcap_filter_add_to_block(ocelot, block, filter); 877 878 /* Get the index of the inserted filter */ 879 index = ocelot_vcap_block_get_filter_index(block, filter); 880 881 /* Move down the rules to make place for the new filter */ 882 for (i = block->count - 1; i > index; i--) { 883 struct ocelot_vcap_filter *tmp; 884 885 tmp = ocelot_vcap_block_find_filter(block, i); 886 is2_entry_set(ocelot, i, tmp); 887 } 888 889 /* Now insert the new filter */ 890 is2_entry_set(ocelot, index, filter); 891 return 0; 892 } 893 894 static void ocelot_vcap_block_remove_filter(struct ocelot *ocelot, 895 struct ocelot_vcap_block *block, 896 struct ocelot_vcap_filter *filter) 897 { 898 struct ocelot_vcap_filter *tmp; 899 struct list_head *pos, *q; 900 901 list_for_each_safe(pos, q, &block->rules) { 902 tmp = list_entry(pos, struct ocelot_vcap_filter, list); 903 if (tmp->id == filter->id) { 904 if (tmp->action == OCELOT_VCAP_ACTION_POLICE) 905 ocelot_vcap_policer_del(ocelot, block, 906 tmp->pol_ix); 907 908 list_del(pos); 909 kfree(tmp); 910 } 911 } 912 913 block->count--; 914 } 915 916 int ocelot_vcap_filter_del(struct ocelot *ocelot, 917 struct ocelot_vcap_filter *filter) 918 { 919 struct ocelot_vcap_block *block = &ocelot->block; 920 struct ocelot_vcap_filter del_filter; 921 int i, index; 922 923 memset(&del_filter, 0, sizeof(del_filter)); 924 925 /* Gets index of the filter */ 926 index = ocelot_vcap_block_get_filter_index(block, filter); 927 928 /* Delete filter */ 929 ocelot_vcap_block_remove_filter(ocelot, block, filter); 930 931 /* Move up all the blocks over the deleted filter */ 932 for (i = index; i < block->count; i++) { 933 struct ocelot_vcap_filter *tmp; 934 935 tmp = ocelot_vcap_block_find_filter(block, i); 936 is2_entry_set(ocelot, i, tmp); 937 } 938 939 /* Now delete the last filter, because it is duplicated */ 940 is2_entry_set(ocelot, block->count, &del_filter); 941 942 return 0; 943 } 944 945 int ocelot_vcap_filter_stats_update(struct ocelot *ocelot, 946 struct ocelot_vcap_filter *filter) 947 { 948 struct ocelot_vcap_block *block = &ocelot->block; 949 struct ocelot_vcap_filter *tmp; 950 int index; 951 952 index = ocelot_vcap_block_get_filter_index(block, filter); 953 is2_entry_get(ocelot, filter, index); 954 955 /* After we get the result we need to clear the counters */ 956 tmp = ocelot_vcap_block_find_filter(block, index); 957 tmp->stats.pkts = 0; 958 is2_entry_set(ocelot, index, tmp); 959 960 return 0; 961 } 962 963 int ocelot_vcap_init(struct ocelot *ocelot) 964 { 965 const struct vcap_props *vcap_is2 = &ocelot->vcap[VCAP_IS2]; 966 struct ocelot_vcap_block *block = &ocelot->block; 967 struct vcap_data data; 968 969 memset(&data, 0, sizeof(data)); 970 971 vcap_entry2cache(ocelot, &data); 972 ocelot_write(ocelot, vcap_is2->entry_count, S2_CORE_MV_CFG); 973 vcap_cmd(ocelot, 0, VCAP_CMD_INITIALIZE, VCAP_SEL_ENTRY); 974 975 vcap_action2cache(ocelot, &data); 976 ocelot_write(ocelot, vcap_is2->action_count, S2_CORE_MV_CFG); 977 vcap_cmd(ocelot, 0, VCAP_CMD_INITIALIZE, 978 VCAP_SEL_ACTION | VCAP_SEL_COUNTER); 979 980 /* Create a policer that will drop the frames for the cpu. 981 * This policer will be used as action in the acl rules to drop 982 * frames. 983 */ 984 ocelot_write_gix(ocelot, 0x299, ANA_POL_MODE_CFG, 985 OCELOT_POLICER_DISCARD); 986 ocelot_write_gix(ocelot, 0x1, ANA_POL_PIR_CFG, 987 OCELOT_POLICER_DISCARD); 988 ocelot_write_gix(ocelot, 0x3fffff, ANA_POL_PIR_STATE, 989 OCELOT_POLICER_DISCARD); 990 ocelot_write_gix(ocelot, 0x0, ANA_POL_CIR_CFG, 991 OCELOT_POLICER_DISCARD); 992 ocelot_write_gix(ocelot, 0x3fffff, ANA_POL_CIR_STATE, 993 OCELOT_POLICER_DISCARD); 994 995 block->pol_lpr = OCELOT_POLICER_DISCARD - 1; 996 997 INIT_LIST_HEAD(&ocelot->block.rules); 998 999 return 0; 1000 } 1001