1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7 #include <linux/dsa/ocelot.h> 8 #include <linux/if_bridge.h> 9 #include <linux/ptp_classify.h> 10 #include <soc/mscc/ocelot_vcap.h> 11 #include "ocelot.h" 12 #include "ocelot_vcap.h" 13 14 #define TABLE_UPDATE_SLEEP_US 10 15 #define TABLE_UPDATE_TIMEOUT_US 100000 16 17 struct ocelot_mact_entry { 18 u8 mac[ETH_ALEN]; 19 u16 vid; 20 enum macaccess_entry_type type; 21 }; 22 23 /* Caller must hold &ocelot->mact_lock */ 24 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot) 25 { 26 return ocelot_read(ocelot, ANA_TABLES_MACACCESS); 27 } 28 29 /* Caller must hold &ocelot->mact_lock */ 30 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot) 31 { 32 u32 val; 33 34 return readx_poll_timeout(ocelot_mact_read_macaccess, 35 ocelot, val, 36 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) == 37 MACACCESS_CMD_IDLE, 38 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 39 } 40 41 /* Caller must hold &ocelot->mact_lock */ 42 static void ocelot_mact_select(struct ocelot *ocelot, 43 const unsigned char mac[ETH_ALEN], 44 unsigned int vid) 45 { 46 u32 macl = 0, mach = 0; 47 48 /* Set the MAC address to handle and the vlan associated in a format 49 * understood by the hardware. 50 */ 51 mach |= vid << 16; 52 mach |= mac[0] << 8; 53 mach |= mac[1] << 0; 54 macl |= mac[2] << 24; 55 macl |= mac[3] << 16; 56 macl |= mac[4] << 8; 57 macl |= mac[5] << 0; 58 59 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA); 60 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA); 61 62 } 63 64 static int __ocelot_mact_learn(struct ocelot *ocelot, int port, 65 const unsigned char mac[ETH_ALEN], 66 unsigned int vid, enum macaccess_entry_type type) 67 { 68 u32 cmd = ANA_TABLES_MACACCESS_VALID | 69 ANA_TABLES_MACACCESS_DEST_IDX(port) | 70 ANA_TABLES_MACACCESS_ENTRYTYPE(type) | 71 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN); 72 unsigned int mc_ports; 73 int err; 74 75 /* Set MAC_CPU_COPY if the CPU port is used by a multicast entry */ 76 if (type == ENTRYTYPE_MACv4) 77 mc_ports = (mac[1] << 8) | mac[2]; 78 else if (type == ENTRYTYPE_MACv6) 79 mc_ports = (mac[0] << 8) | mac[1]; 80 else 81 mc_ports = 0; 82 83 if (mc_ports & BIT(ocelot->num_phys_ports)) 84 cmd |= ANA_TABLES_MACACCESS_MAC_CPU_COPY; 85 86 ocelot_mact_select(ocelot, mac, vid); 87 88 /* Issue a write command */ 89 ocelot_write(ocelot, cmd, ANA_TABLES_MACACCESS); 90 91 err = ocelot_mact_wait_for_completion(ocelot); 92 93 return err; 94 } 95 96 int ocelot_mact_learn(struct ocelot *ocelot, int port, 97 const unsigned char mac[ETH_ALEN], 98 unsigned int vid, enum macaccess_entry_type type) 99 { 100 int ret; 101 102 mutex_lock(&ocelot->mact_lock); 103 ret = __ocelot_mact_learn(ocelot, port, mac, vid, type); 104 mutex_unlock(&ocelot->mact_lock); 105 106 return ret; 107 } 108 EXPORT_SYMBOL(ocelot_mact_learn); 109 110 int ocelot_mact_forget(struct ocelot *ocelot, 111 const unsigned char mac[ETH_ALEN], unsigned int vid) 112 { 113 int err; 114 115 mutex_lock(&ocelot->mact_lock); 116 117 ocelot_mact_select(ocelot, mac, vid); 118 119 /* Issue a forget command */ 120 ocelot_write(ocelot, 121 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET), 122 ANA_TABLES_MACACCESS); 123 124 err = ocelot_mact_wait_for_completion(ocelot); 125 126 mutex_unlock(&ocelot->mact_lock); 127 128 return err; 129 } 130 EXPORT_SYMBOL(ocelot_mact_forget); 131 132 int ocelot_mact_lookup(struct ocelot *ocelot, int *dst_idx, 133 const unsigned char mac[ETH_ALEN], 134 unsigned int vid, enum macaccess_entry_type *type) 135 { 136 int val; 137 138 mutex_lock(&ocelot->mact_lock); 139 140 ocelot_mact_select(ocelot, mac, vid); 141 142 /* Issue a read command with MACACCESS_VALID=1. */ 143 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID | 144 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 145 ANA_TABLES_MACACCESS); 146 147 if (ocelot_mact_wait_for_completion(ocelot)) { 148 mutex_unlock(&ocelot->mact_lock); 149 return -ETIMEDOUT; 150 } 151 152 /* Read back the entry flags */ 153 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 154 155 mutex_unlock(&ocelot->mact_lock); 156 157 if (!(val & ANA_TABLES_MACACCESS_VALID)) 158 return -ENOENT; 159 160 *dst_idx = ANA_TABLES_MACACCESS_DEST_IDX_X(val); 161 *type = ANA_TABLES_MACACCESS_ENTRYTYPE_X(val); 162 163 return 0; 164 } 165 EXPORT_SYMBOL(ocelot_mact_lookup); 166 167 int ocelot_mact_learn_streamdata(struct ocelot *ocelot, int dst_idx, 168 const unsigned char mac[ETH_ALEN], 169 unsigned int vid, 170 enum macaccess_entry_type type, 171 int sfid, int ssid) 172 { 173 int ret; 174 175 mutex_lock(&ocelot->mact_lock); 176 177 ocelot_write(ocelot, 178 (sfid < 0 ? 0 : ANA_TABLES_STREAMDATA_SFID_VALID) | 179 ANA_TABLES_STREAMDATA_SFID(sfid) | 180 (ssid < 0 ? 0 : ANA_TABLES_STREAMDATA_SSID_VALID) | 181 ANA_TABLES_STREAMDATA_SSID(ssid), 182 ANA_TABLES_STREAMDATA); 183 184 ret = __ocelot_mact_learn(ocelot, dst_idx, mac, vid, type); 185 186 mutex_unlock(&ocelot->mact_lock); 187 188 return ret; 189 } 190 EXPORT_SYMBOL(ocelot_mact_learn_streamdata); 191 192 static void ocelot_mact_init(struct ocelot *ocelot) 193 { 194 /* Configure the learning mode entries attributes: 195 * - Do not copy the frame to the CPU extraction queues. 196 * - Use the vlan and mac_cpoy for dmac lookup. 197 */ 198 ocelot_rmw(ocelot, 0, 199 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS 200 | ANA_AGENCTRL_LEARN_FWD_KILL 201 | ANA_AGENCTRL_LEARN_IGNORE_VLAN, 202 ANA_AGENCTRL); 203 204 /* Clear the MAC table. We are not concurrent with anyone, so 205 * holding &ocelot->mact_lock is pointless. 206 */ 207 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS); 208 } 209 210 static void ocelot_vcap_enable(struct ocelot *ocelot, int port) 211 { 212 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA | 213 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa), 214 ANA_PORT_VCAP_S2_CFG, port); 215 216 ocelot_write_gix(ocelot, ANA_PORT_VCAP_CFG_S1_ENA, 217 ANA_PORT_VCAP_CFG, port); 218 219 ocelot_rmw_gix(ocelot, REW_PORT_CFG_ES0_EN, 220 REW_PORT_CFG_ES0_EN, 221 REW_PORT_CFG, port); 222 } 223 224 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot) 225 { 226 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS); 227 } 228 229 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot) 230 { 231 u32 val; 232 233 return readx_poll_timeout(ocelot_vlant_read_vlanaccess, 234 ocelot, 235 val, 236 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) == 237 ANA_TABLES_VLANACCESS_CMD_IDLE, 238 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 239 } 240 241 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask) 242 { 243 /* Select the VID to configure */ 244 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid), 245 ANA_TABLES_VLANTIDX); 246 /* Set the vlan port members mask and issue a write command */ 247 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) | 248 ANA_TABLES_VLANACCESS_CMD_WRITE, 249 ANA_TABLES_VLANACCESS); 250 251 return ocelot_vlant_wait_for_completion(ocelot); 252 } 253 254 static int ocelot_port_num_untagged_vlans(struct ocelot *ocelot, int port) 255 { 256 struct ocelot_bridge_vlan *vlan; 257 int num_untagged = 0; 258 259 list_for_each_entry(vlan, &ocelot->vlans, list) { 260 if (!(vlan->portmask & BIT(port))) 261 continue; 262 263 if (vlan->untagged & BIT(port)) 264 num_untagged++; 265 } 266 267 return num_untagged; 268 } 269 270 static int ocelot_port_num_tagged_vlans(struct ocelot *ocelot, int port) 271 { 272 struct ocelot_bridge_vlan *vlan; 273 int num_tagged = 0; 274 275 list_for_each_entry(vlan, &ocelot->vlans, list) { 276 if (!(vlan->portmask & BIT(port))) 277 continue; 278 279 if (!(vlan->untagged & BIT(port))) 280 num_tagged++; 281 } 282 283 return num_tagged; 284 } 285 286 /* We use native VLAN when we have to mix egress-tagged VLANs with exactly 287 * _one_ egress-untagged VLAN (_the_ native VLAN) 288 */ 289 static bool ocelot_port_uses_native_vlan(struct ocelot *ocelot, int port) 290 { 291 return ocelot_port_num_tagged_vlans(ocelot, port) && 292 ocelot_port_num_untagged_vlans(ocelot, port) == 1; 293 } 294 295 static struct ocelot_bridge_vlan * 296 ocelot_port_find_native_vlan(struct ocelot *ocelot, int port) 297 { 298 struct ocelot_bridge_vlan *vlan; 299 300 list_for_each_entry(vlan, &ocelot->vlans, list) 301 if (vlan->portmask & BIT(port) && vlan->untagged & BIT(port)) 302 return vlan; 303 304 return NULL; 305 } 306 307 /* Keep in sync REW_TAG_CFG_TAG_CFG and, if applicable, 308 * REW_PORT_VLAN_CFG_PORT_VID, with the bridge VLAN table and VLAN awareness 309 * state of the port. 310 */ 311 static void ocelot_port_manage_port_tag(struct ocelot *ocelot, int port) 312 { 313 struct ocelot_port *ocelot_port = ocelot->ports[port]; 314 enum ocelot_port_tag_config tag_cfg; 315 bool uses_native_vlan = false; 316 317 if (ocelot_port->vlan_aware) { 318 uses_native_vlan = ocelot_port_uses_native_vlan(ocelot, port); 319 320 if (uses_native_vlan) 321 tag_cfg = OCELOT_PORT_TAG_NATIVE; 322 else if (ocelot_port_num_untagged_vlans(ocelot, port)) 323 tag_cfg = OCELOT_PORT_TAG_DISABLED; 324 else 325 tag_cfg = OCELOT_PORT_TAG_TRUNK; 326 } else { 327 tag_cfg = OCELOT_PORT_TAG_DISABLED; 328 } 329 330 ocelot_rmw_gix(ocelot, REW_TAG_CFG_TAG_CFG(tag_cfg), 331 REW_TAG_CFG_TAG_CFG_M, 332 REW_TAG_CFG, port); 333 334 if (uses_native_vlan) { 335 struct ocelot_bridge_vlan *native_vlan; 336 337 /* Not having a native VLAN is impossible, because 338 * ocelot_port_num_untagged_vlans has returned 1. 339 * So there is no use in checking for NULL here. 340 */ 341 native_vlan = ocelot_port_find_native_vlan(ocelot, port); 342 343 ocelot_rmw_gix(ocelot, 344 REW_PORT_VLAN_CFG_PORT_VID(native_vlan->vid), 345 REW_PORT_VLAN_CFG_PORT_VID_M, 346 REW_PORT_VLAN_CFG, port); 347 } 348 } 349 350 /* Default vlan to clasify for untagged frames (may be zero) */ 351 static void ocelot_port_set_pvid(struct ocelot *ocelot, int port, 352 const struct ocelot_bridge_vlan *pvid_vlan) 353 { 354 struct ocelot_port *ocelot_port = ocelot->ports[port]; 355 u16 pvid = OCELOT_VLAN_UNAWARE_PVID; 356 u32 val = 0; 357 358 ocelot_port->pvid_vlan = pvid_vlan; 359 360 if (ocelot_port->vlan_aware && pvid_vlan) 361 pvid = pvid_vlan->vid; 362 363 ocelot_rmw_gix(ocelot, 364 ANA_PORT_VLAN_CFG_VLAN_VID(pvid), 365 ANA_PORT_VLAN_CFG_VLAN_VID_M, 366 ANA_PORT_VLAN_CFG, port); 367 368 /* If there's no pvid, we should drop not only untagged traffic (which 369 * happens automatically), but also 802.1p traffic which gets 370 * classified to VLAN 0, but that is always in our RX filter, so it 371 * would get accepted were it not for this setting. 372 */ 373 if (!pvid_vlan && ocelot_port->vlan_aware) 374 val = ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 375 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA; 376 377 ocelot_rmw_gix(ocelot, val, 378 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 379 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, 380 ANA_PORT_DROP_CFG, port); 381 } 382 383 static struct ocelot_bridge_vlan *ocelot_bridge_vlan_find(struct ocelot *ocelot, 384 u16 vid) 385 { 386 struct ocelot_bridge_vlan *vlan; 387 388 list_for_each_entry(vlan, &ocelot->vlans, list) 389 if (vlan->vid == vid) 390 return vlan; 391 392 return NULL; 393 } 394 395 static int ocelot_vlan_member_add(struct ocelot *ocelot, int port, u16 vid, 396 bool untagged) 397 { 398 struct ocelot_bridge_vlan *vlan = ocelot_bridge_vlan_find(ocelot, vid); 399 unsigned long portmask; 400 int err; 401 402 if (vlan) { 403 portmask = vlan->portmask | BIT(port); 404 405 err = ocelot_vlant_set_mask(ocelot, vid, portmask); 406 if (err) 407 return err; 408 409 vlan->portmask = portmask; 410 /* Bridge VLANs can be overwritten with a different 411 * egress-tagging setting, so make sure to override an untagged 412 * with a tagged VID if that's going on. 413 */ 414 if (untagged) 415 vlan->untagged |= BIT(port); 416 else 417 vlan->untagged &= ~BIT(port); 418 419 return 0; 420 } 421 422 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL); 423 if (!vlan) 424 return -ENOMEM; 425 426 portmask = BIT(port); 427 428 err = ocelot_vlant_set_mask(ocelot, vid, portmask); 429 if (err) { 430 kfree(vlan); 431 return err; 432 } 433 434 vlan->vid = vid; 435 vlan->portmask = portmask; 436 if (untagged) 437 vlan->untagged = BIT(port); 438 INIT_LIST_HEAD(&vlan->list); 439 list_add_tail(&vlan->list, &ocelot->vlans); 440 441 return 0; 442 } 443 444 static int ocelot_vlan_member_del(struct ocelot *ocelot, int port, u16 vid) 445 { 446 struct ocelot_bridge_vlan *vlan = ocelot_bridge_vlan_find(ocelot, vid); 447 unsigned long portmask; 448 int err; 449 450 if (!vlan) 451 return 0; 452 453 portmask = vlan->portmask & ~BIT(port); 454 455 err = ocelot_vlant_set_mask(ocelot, vid, portmask); 456 if (err) 457 return err; 458 459 vlan->portmask = portmask; 460 if (vlan->portmask) 461 return 0; 462 463 list_del(&vlan->list); 464 kfree(vlan); 465 466 return 0; 467 } 468 469 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, 470 bool vlan_aware, struct netlink_ext_ack *extack) 471 { 472 struct ocelot_vcap_block *block = &ocelot->block[VCAP_IS1]; 473 struct ocelot_port *ocelot_port = ocelot->ports[port]; 474 struct ocelot_vcap_filter *filter; 475 u32 val; 476 477 list_for_each_entry(filter, &block->rules, list) { 478 if (filter->ingress_port_mask & BIT(port) && 479 filter->action.vid_replace_ena) { 480 NL_SET_ERR_MSG_MOD(extack, 481 "Cannot change VLAN state with vlan modify rules active"); 482 return -EBUSY; 483 } 484 } 485 486 ocelot_port->vlan_aware = vlan_aware; 487 488 if (vlan_aware) 489 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 490 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1); 491 else 492 val = 0; 493 ocelot_rmw_gix(ocelot, val, 494 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 495 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M, 496 ANA_PORT_VLAN_CFG, port); 497 498 ocelot_port_set_pvid(ocelot, port, ocelot_port->pvid_vlan); 499 ocelot_port_manage_port_tag(ocelot, port); 500 501 return 0; 502 } 503 EXPORT_SYMBOL(ocelot_port_vlan_filtering); 504 505 int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid, 506 bool untagged, struct netlink_ext_ack *extack) 507 { 508 if (untagged) { 509 /* We are adding an egress-tagged VLAN */ 510 if (ocelot_port_uses_native_vlan(ocelot, port)) { 511 NL_SET_ERR_MSG_MOD(extack, 512 "Port with egress-tagged VLANs cannot have more than one egress-untagged (native) VLAN"); 513 return -EBUSY; 514 } 515 } else { 516 /* We are adding an egress-tagged VLAN */ 517 if (ocelot_port_num_untagged_vlans(ocelot, port) > 1) { 518 NL_SET_ERR_MSG_MOD(extack, 519 "Port with more than one egress-untagged VLAN cannot have egress-tagged VLANs"); 520 return -EBUSY; 521 } 522 } 523 524 return 0; 525 } 526 EXPORT_SYMBOL(ocelot_vlan_prepare); 527 528 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid, 529 bool untagged) 530 { 531 int err; 532 533 err = ocelot_vlan_member_add(ocelot, port, vid, untagged); 534 if (err) 535 return err; 536 537 /* Default ingress vlan classification */ 538 if (pvid) 539 ocelot_port_set_pvid(ocelot, port, 540 ocelot_bridge_vlan_find(ocelot, vid)); 541 542 /* Untagged egress vlan clasification */ 543 ocelot_port_manage_port_tag(ocelot, port); 544 545 return 0; 546 } 547 EXPORT_SYMBOL(ocelot_vlan_add); 548 549 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid) 550 { 551 struct ocelot_port *ocelot_port = ocelot->ports[port]; 552 int err; 553 554 err = ocelot_vlan_member_del(ocelot, port, vid); 555 if (err) 556 return err; 557 558 /* Ingress */ 559 if (ocelot_port->pvid_vlan && ocelot_port->pvid_vlan->vid == vid) 560 ocelot_port_set_pvid(ocelot, port, NULL); 561 562 /* Egress */ 563 ocelot_port_manage_port_tag(ocelot, port); 564 565 return 0; 566 } 567 EXPORT_SYMBOL(ocelot_vlan_del); 568 569 static void ocelot_vlan_init(struct ocelot *ocelot) 570 { 571 unsigned long all_ports = GENMASK(ocelot->num_phys_ports - 1, 0); 572 u16 port, vid; 573 574 /* Clear VLAN table, by default all ports are members of all VLANs */ 575 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT, 576 ANA_TABLES_VLANACCESS); 577 ocelot_vlant_wait_for_completion(ocelot); 578 579 /* Configure the port VLAN memberships */ 580 for (vid = 1; vid < VLAN_N_VID; vid++) 581 ocelot_vlant_set_mask(ocelot, vid, 0); 582 583 /* Because VLAN filtering is enabled, we need VID 0 to get untagged 584 * traffic. It is added automatically if 8021q module is loaded, but 585 * we can't rely on it since module may be not loaded. 586 */ 587 ocelot_vlant_set_mask(ocelot, OCELOT_VLAN_UNAWARE_PVID, all_ports); 588 589 /* Set vlan ingress filter mask to all ports but the CPU port by 590 * default. 591 */ 592 ocelot_write(ocelot, all_ports, ANA_VLANMASK); 593 594 for (port = 0; port < ocelot->num_phys_ports; port++) { 595 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port); 596 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port); 597 } 598 } 599 600 static u32 ocelot_read_eq_avail(struct ocelot *ocelot, int port) 601 { 602 return ocelot_read_rix(ocelot, QSYS_SW_STATUS, port); 603 } 604 605 static int ocelot_port_flush(struct ocelot *ocelot, int port) 606 { 607 unsigned int pause_ena; 608 int err, val; 609 610 /* Disable dequeuing from the egress queues */ 611 ocelot_rmw_rix(ocelot, QSYS_PORT_MODE_DEQUEUE_DIS, 612 QSYS_PORT_MODE_DEQUEUE_DIS, 613 QSYS_PORT_MODE, port); 614 615 /* Disable flow control */ 616 ocelot_fields_read(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, &pause_ena); 617 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 0); 618 619 /* Disable priority flow control */ 620 ocelot_fields_write(ocelot, port, 621 QSYS_SWITCH_PORT_MODE_TX_PFC_ENA, 0); 622 623 /* Wait at least the time it takes to receive a frame of maximum length 624 * at the port. 625 * Worst-case delays for 10 kilobyte jumbo frames are: 626 * 8 ms on a 10M port 627 * 800 μs on a 100M port 628 * 80 μs on a 1G port 629 * 32 μs on a 2.5G port 630 */ 631 usleep_range(8000, 10000); 632 633 /* Disable half duplex backpressure. */ 634 ocelot_rmw_rix(ocelot, 0, SYS_FRONT_PORT_MODE_HDX_MODE, 635 SYS_FRONT_PORT_MODE, port); 636 637 /* Flush the queues associated with the port. */ 638 ocelot_rmw_gix(ocelot, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG_FLUSH_ENA, 639 REW_PORT_CFG, port); 640 641 /* Enable dequeuing from the egress queues. */ 642 ocelot_rmw_rix(ocelot, 0, QSYS_PORT_MODE_DEQUEUE_DIS, QSYS_PORT_MODE, 643 port); 644 645 /* Wait until flushing is complete. */ 646 err = read_poll_timeout(ocelot_read_eq_avail, val, !val, 647 100, 2000000, false, ocelot, port); 648 649 /* Clear flushing again. */ 650 ocelot_rmw_gix(ocelot, 0, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG, port); 651 652 /* Re-enable flow control */ 653 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, pause_ena); 654 655 return err; 656 } 657 658 void ocelot_phylink_mac_link_down(struct ocelot *ocelot, int port, 659 unsigned int link_an_mode, 660 phy_interface_t interface, 661 unsigned long quirks) 662 { 663 struct ocelot_port *ocelot_port = ocelot->ports[port]; 664 int err; 665 666 ocelot_port_rmwl(ocelot_port, 0, DEV_MAC_ENA_CFG_RX_ENA, 667 DEV_MAC_ENA_CFG); 668 669 ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0); 670 671 err = ocelot_port_flush(ocelot, port); 672 if (err) 673 dev_err(ocelot->dev, "failed to flush port %d: %d\n", 674 port, err); 675 676 /* Put the port in reset. */ 677 if (interface != PHY_INTERFACE_MODE_QSGMII || 678 !(quirks & OCELOT_QUIRK_QSGMII_PORTS_MUST_BE_UP)) 679 ocelot_port_rmwl(ocelot_port, 680 DEV_CLOCK_CFG_MAC_TX_RST | 681 DEV_CLOCK_CFG_MAC_RX_RST, 682 DEV_CLOCK_CFG_MAC_TX_RST | 683 DEV_CLOCK_CFG_MAC_RX_RST, 684 DEV_CLOCK_CFG); 685 } 686 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_down); 687 688 void ocelot_phylink_mac_link_up(struct ocelot *ocelot, int port, 689 struct phy_device *phydev, 690 unsigned int link_an_mode, 691 phy_interface_t interface, 692 int speed, int duplex, 693 bool tx_pause, bool rx_pause, 694 unsigned long quirks) 695 { 696 struct ocelot_port *ocelot_port = ocelot->ports[port]; 697 int mac_speed, mode = 0; 698 u32 mac_fc_cfg; 699 700 /* The MAC might be integrated in systems where the MAC speed is fixed 701 * and it's the PCS who is performing the rate adaptation, so we have 702 * to write "1000Mbps" into the LINK_SPEED field of DEV_CLOCK_CFG 703 * (which is also its default value). 704 */ 705 if ((quirks & OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION) || 706 speed == SPEED_1000) { 707 mac_speed = OCELOT_SPEED_1000; 708 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 709 } else if (speed == SPEED_2500) { 710 mac_speed = OCELOT_SPEED_2500; 711 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 712 } else if (speed == SPEED_100) { 713 mac_speed = OCELOT_SPEED_100; 714 } else { 715 mac_speed = OCELOT_SPEED_10; 716 } 717 718 if (duplex == DUPLEX_FULL) 719 mode |= DEV_MAC_MODE_CFG_FDX_ENA; 720 721 ocelot_port_writel(ocelot_port, mode, DEV_MAC_MODE_CFG); 722 723 /* Take port out of reset by clearing the MAC_TX_RST, MAC_RX_RST and 724 * PORT_RST bits in DEV_CLOCK_CFG. 725 */ 726 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(mac_speed), 727 DEV_CLOCK_CFG); 728 729 switch (speed) { 730 case SPEED_10: 731 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_10); 732 break; 733 case SPEED_100: 734 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_100); 735 break; 736 case SPEED_1000: 737 case SPEED_2500: 738 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_1000); 739 break; 740 default: 741 dev_err(ocelot->dev, "Unsupported speed on port %d: %d\n", 742 port, speed); 743 return; 744 } 745 746 /* Handle RX pause in all cases, with 2500base-X this is used for rate 747 * adaptation. 748 */ 749 mac_fc_cfg |= SYS_MAC_FC_CFG_RX_FC_ENA; 750 751 if (tx_pause) 752 mac_fc_cfg |= SYS_MAC_FC_CFG_TX_FC_ENA | 753 SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) | 754 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) | 755 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA; 756 757 /* Flow control. Link speed is only used here to evaluate the time 758 * specification in incoming pause frames. 759 */ 760 ocelot_write_rix(ocelot, mac_fc_cfg, SYS_MAC_FC_CFG, port); 761 762 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port); 763 764 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, tx_pause); 765 766 /* Undo the effects of ocelot_phylink_mac_link_down: 767 * enable MAC module 768 */ 769 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA | 770 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG); 771 772 /* Core: Enable port for frame transfer */ 773 ocelot_fields_write(ocelot, port, 774 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 775 } 776 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_up); 777 778 static int ocelot_port_add_txtstamp_skb(struct ocelot *ocelot, int port, 779 struct sk_buff *clone) 780 { 781 struct ocelot_port *ocelot_port = ocelot->ports[port]; 782 unsigned long flags; 783 784 spin_lock_irqsave(&ocelot->ts_id_lock, flags); 785 786 if (ocelot_port->ptp_skbs_in_flight == OCELOT_MAX_PTP_ID || 787 ocelot->ptp_skbs_in_flight == OCELOT_PTP_FIFO_SIZE) { 788 spin_unlock_irqrestore(&ocelot->ts_id_lock, flags); 789 return -EBUSY; 790 } 791 792 skb_shinfo(clone)->tx_flags |= SKBTX_IN_PROGRESS; 793 /* Store timestamp ID in OCELOT_SKB_CB(clone)->ts_id */ 794 OCELOT_SKB_CB(clone)->ts_id = ocelot_port->ts_id; 795 796 ocelot_port->ts_id++; 797 if (ocelot_port->ts_id == OCELOT_MAX_PTP_ID) 798 ocelot_port->ts_id = 0; 799 800 ocelot_port->ptp_skbs_in_flight++; 801 ocelot->ptp_skbs_in_flight++; 802 803 skb_queue_tail(&ocelot_port->tx_skbs, clone); 804 805 spin_unlock_irqrestore(&ocelot->ts_id_lock, flags); 806 807 return 0; 808 } 809 810 static bool ocelot_ptp_is_onestep_sync(struct sk_buff *skb, 811 unsigned int ptp_class) 812 { 813 struct ptp_header *hdr; 814 u8 msgtype, twostep; 815 816 hdr = ptp_parse_header(skb, ptp_class); 817 if (!hdr) 818 return false; 819 820 msgtype = ptp_get_msgtype(hdr, ptp_class); 821 twostep = hdr->flag_field[0] & 0x2; 822 823 if (msgtype == PTP_MSGTYPE_SYNC && twostep == 0) 824 return true; 825 826 return false; 827 } 828 829 int ocelot_port_txtstamp_request(struct ocelot *ocelot, int port, 830 struct sk_buff *skb, 831 struct sk_buff **clone) 832 { 833 struct ocelot_port *ocelot_port = ocelot->ports[port]; 834 u8 ptp_cmd = ocelot_port->ptp_cmd; 835 unsigned int ptp_class; 836 int err; 837 838 /* Don't do anything if PTP timestamping not enabled */ 839 if (!ptp_cmd) 840 return 0; 841 842 ptp_class = ptp_classify_raw(skb); 843 if (ptp_class == PTP_CLASS_NONE) 844 return -EINVAL; 845 846 /* Store ptp_cmd in OCELOT_SKB_CB(skb)->ptp_cmd */ 847 if (ptp_cmd == IFH_REW_OP_ORIGIN_PTP) { 848 if (ocelot_ptp_is_onestep_sync(skb, ptp_class)) { 849 OCELOT_SKB_CB(skb)->ptp_cmd = ptp_cmd; 850 return 0; 851 } 852 853 /* Fall back to two-step timestamping */ 854 ptp_cmd = IFH_REW_OP_TWO_STEP_PTP; 855 } 856 857 if (ptp_cmd == IFH_REW_OP_TWO_STEP_PTP) { 858 *clone = skb_clone_sk(skb); 859 if (!(*clone)) 860 return -ENOMEM; 861 862 err = ocelot_port_add_txtstamp_skb(ocelot, port, *clone); 863 if (err) 864 return err; 865 866 OCELOT_SKB_CB(skb)->ptp_cmd = ptp_cmd; 867 OCELOT_SKB_CB(*clone)->ptp_class = ptp_class; 868 } 869 870 return 0; 871 } 872 EXPORT_SYMBOL(ocelot_port_txtstamp_request); 873 874 static void ocelot_get_hwtimestamp(struct ocelot *ocelot, 875 struct timespec64 *ts) 876 { 877 unsigned long flags; 878 u32 val; 879 880 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); 881 882 /* Read current PTP time to get seconds */ 883 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 884 885 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 886 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE); 887 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 888 ts->tv_sec = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN); 889 890 /* Read packet HW timestamp from FIFO */ 891 val = ocelot_read(ocelot, SYS_PTP_TXSTAMP); 892 ts->tv_nsec = SYS_PTP_TXSTAMP_PTP_TXSTAMP(val); 893 894 /* Sec has incremented since the ts was registered */ 895 if ((ts->tv_sec & 0x1) != !!(val & SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC)) 896 ts->tv_sec--; 897 898 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 899 } 900 901 static bool ocelot_validate_ptp_skb(struct sk_buff *clone, u16 seqid) 902 { 903 struct ptp_header *hdr; 904 905 hdr = ptp_parse_header(clone, OCELOT_SKB_CB(clone)->ptp_class); 906 if (WARN_ON(!hdr)) 907 return false; 908 909 return seqid == ntohs(hdr->sequence_id); 910 } 911 912 void ocelot_get_txtstamp(struct ocelot *ocelot) 913 { 914 int budget = OCELOT_PTP_QUEUE_SZ; 915 916 while (budget--) { 917 struct sk_buff *skb, *skb_tmp, *skb_match = NULL; 918 struct skb_shared_hwtstamps shhwtstamps; 919 u32 val, id, seqid, txport; 920 struct ocelot_port *port; 921 struct timespec64 ts; 922 unsigned long flags; 923 924 val = ocelot_read(ocelot, SYS_PTP_STATUS); 925 926 /* Check if a timestamp can be retrieved */ 927 if (!(val & SYS_PTP_STATUS_PTP_MESS_VLD)) 928 break; 929 930 WARN_ON(val & SYS_PTP_STATUS_PTP_OVFL); 931 932 /* Retrieve the ts ID and Tx port */ 933 id = SYS_PTP_STATUS_PTP_MESS_ID_X(val); 934 txport = SYS_PTP_STATUS_PTP_MESS_TXPORT_X(val); 935 seqid = SYS_PTP_STATUS_PTP_MESS_SEQ_ID(val); 936 937 port = ocelot->ports[txport]; 938 939 spin_lock(&ocelot->ts_id_lock); 940 port->ptp_skbs_in_flight--; 941 ocelot->ptp_skbs_in_flight--; 942 spin_unlock(&ocelot->ts_id_lock); 943 944 /* Retrieve its associated skb */ 945 try_again: 946 spin_lock_irqsave(&port->tx_skbs.lock, flags); 947 948 skb_queue_walk_safe(&port->tx_skbs, skb, skb_tmp) { 949 if (OCELOT_SKB_CB(skb)->ts_id != id) 950 continue; 951 __skb_unlink(skb, &port->tx_skbs); 952 skb_match = skb; 953 break; 954 } 955 956 spin_unlock_irqrestore(&port->tx_skbs.lock, flags); 957 958 if (WARN_ON(!skb_match)) 959 continue; 960 961 if (!ocelot_validate_ptp_skb(skb_match, seqid)) { 962 dev_err_ratelimited(ocelot->dev, 963 "port %d received stale TX timestamp for seqid %d, discarding\n", 964 txport, seqid); 965 dev_kfree_skb_any(skb); 966 goto try_again; 967 } 968 969 /* Get the h/w timestamp */ 970 ocelot_get_hwtimestamp(ocelot, &ts); 971 972 /* Set the timestamp into the skb */ 973 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 974 shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec); 975 skb_complete_tx_timestamp(skb_match, &shhwtstamps); 976 977 /* Next ts */ 978 ocelot_write(ocelot, SYS_PTP_NXT_PTP_NXT, SYS_PTP_NXT); 979 } 980 } 981 EXPORT_SYMBOL(ocelot_get_txtstamp); 982 983 static int ocelot_rx_frame_word(struct ocelot *ocelot, u8 grp, bool ifh, 984 u32 *rval) 985 { 986 u32 bytes_valid, val; 987 988 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 989 if (val == XTR_NOT_READY) { 990 if (ifh) 991 return -EIO; 992 993 do { 994 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 995 } while (val == XTR_NOT_READY); 996 } 997 998 switch (val) { 999 case XTR_ABORT: 1000 return -EIO; 1001 case XTR_EOF_0: 1002 case XTR_EOF_1: 1003 case XTR_EOF_2: 1004 case XTR_EOF_3: 1005 case XTR_PRUNED: 1006 bytes_valid = XTR_VALID_BYTES(val); 1007 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1008 if (val == XTR_ESCAPE) 1009 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1010 else 1011 *rval = val; 1012 1013 return bytes_valid; 1014 case XTR_ESCAPE: 1015 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1016 1017 return 4; 1018 default: 1019 *rval = val; 1020 1021 return 4; 1022 } 1023 } 1024 1025 static int ocelot_xtr_poll_xfh(struct ocelot *ocelot, int grp, u32 *xfh) 1026 { 1027 int i, err = 0; 1028 1029 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) { 1030 err = ocelot_rx_frame_word(ocelot, grp, true, &xfh[i]); 1031 if (err != 4) 1032 return (err < 0) ? err : -EIO; 1033 } 1034 1035 return 0; 1036 } 1037 1038 int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **nskb) 1039 { 1040 struct skb_shared_hwtstamps *shhwtstamps; 1041 u64 tod_in_ns, full_ts_in_ns; 1042 u64 timestamp, src_port, len; 1043 u32 xfh[OCELOT_TAG_LEN / 4]; 1044 struct net_device *dev; 1045 struct timespec64 ts; 1046 struct sk_buff *skb; 1047 int sz, buf_len; 1048 u32 val, *buf; 1049 int err; 1050 1051 err = ocelot_xtr_poll_xfh(ocelot, grp, xfh); 1052 if (err) 1053 return err; 1054 1055 ocelot_xfh_get_src_port(xfh, &src_port); 1056 ocelot_xfh_get_len(xfh, &len); 1057 ocelot_xfh_get_rew_val(xfh, ×tamp); 1058 1059 if (WARN_ON(src_port >= ocelot->num_phys_ports)) 1060 return -EINVAL; 1061 1062 dev = ocelot->ops->port_to_netdev(ocelot, src_port); 1063 if (!dev) 1064 return -EINVAL; 1065 1066 skb = netdev_alloc_skb(dev, len); 1067 if (unlikely(!skb)) { 1068 netdev_err(dev, "Unable to allocate sk_buff\n"); 1069 return -ENOMEM; 1070 } 1071 1072 buf_len = len - ETH_FCS_LEN; 1073 buf = (u32 *)skb_put(skb, buf_len); 1074 1075 len = 0; 1076 do { 1077 sz = ocelot_rx_frame_word(ocelot, grp, false, &val); 1078 if (sz < 0) { 1079 err = sz; 1080 goto out_free_skb; 1081 } 1082 *buf++ = val; 1083 len += sz; 1084 } while (len < buf_len); 1085 1086 /* Read the FCS */ 1087 sz = ocelot_rx_frame_word(ocelot, grp, false, &val); 1088 if (sz < 0) { 1089 err = sz; 1090 goto out_free_skb; 1091 } 1092 1093 /* Update the statistics if part of the FCS was read before */ 1094 len -= ETH_FCS_LEN - sz; 1095 1096 if (unlikely(dev->features & NETIF_F_RXFCS)) { 1097 buf = (u32 *)skb_put(skb, ETH_FCS_LEN); 1098 *buf = val; 1099 } 1100 1101 if (ocelot->ptp) { 1102 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); 1103 1104 tod_in_ns = ktime_set(ts.tv_sec, ts.tv_nsec); 1105 if ((tod_in_ns & 0xffffffff) < timestamp) 1106 full_ts_in_ns = (((tod_in_ns >> 32) - 1) << 32) | 1107 timestamp; 1108 else 1109 full_ts_in_ns = (tod_in_ns & GENMASK_ULL(63, 32)) | 1110 timestamp; 1111 1112 shhwtstamps = skb_hwtstamps(skb); 1113 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps)); 1114 shhwtstamps->hwtstamp = full_ts_in_ns; 1115 } 1116 1117 /* Everything we see on an interface that is in the HW bridge 1118 * has already been forwarded. 1119 */ 1120 if (ocelot->ports[src_port]->bridge) 1121 skb->offload_fwd_mark = 1; 1122 1123 skb->protocol = eth_type_trans(skb, dev); 1124 1125 *nskb = skb; 1126 1127 return 0; 1128 1129 out_free_skb: 1130 kfree_skb(skb); 1131 return err; 1132 } 1133 EXPORT_SYMBOL(ocelot_xtr_poll_frame); 1134 1135 bool ocelot_can_inject(struct ocelot *ocelot, int grp) 1136 { 1137 u32 val = ocelot_read(ocelot, QS_INJ_STATUS); 1138 1139 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp)))) 1140 return false; 1141 if (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp))) 1142 return false; 1143 1144 return true; 1145 } 1146 EXPORT_SYMBOL(ocelot_can_inject); 1147 1148 void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp, 1149 u32 rew_op, struct sk_buff *skb) 1150 { 1151 u32 ifh[OCELOT_TAG_LEN / 4] = {0}; 1152 unsigned int i, count, last; 1153 1154 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 1155 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp); 1156 1157 ocelot_ifh_set_bypass(ifh, 1); 1158 ocelot_ifh_set_dest(ifh, BIT_ULL(port)); 1159 ocelot_ifh_set_tag_type(ifh, IFH_TAG_TYPE_C); 1160 ocelot_ifh_set_vlan_tci(ifh, skb_vlan_tag_get(skb)); 1161 ocelot_ifh_set_rew_op(ifh, rew_op); 1162 1163 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) 1164 ocelot_write_rix(ocelot, ifh[i], QS_INJ_WR, grp); 1165 1166 count = DIV_ROUND_UP(skb->len, 4); 1167 last = skb->len % 4; 1168 for (i = 0; i < count; i++) 1169 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp); 1170 1171 /* Add padding */ 1172 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) { 1173 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 1174 i++; 1175 } 1176 1177 /* Indicate EOF and valid bytes in last word */ 1178 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 1179 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) | 1180 QS_INJ_CTRL_EOF, 1181 QS_INJ_CTRL, grp); 1182 1183 /* Add dummy CRC */ 1184 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 1185 skb_tx_timestamp(skb); 1186 1187 skb->dev->stats.tx_packets++; 1188 skb->dev->stats.tx_bytes += skb->len; 1189 } 1190 EXPORT_SYMBOL(ocelot_port_inject_frame); 1191 1192 void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp) 1193 { 1194 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)) 1195 ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1196 } 1197 EXPORT_SYMBOL(ocelot_drain_cpu_queue); 1198 1199 int ocelot_fdb_add(struct ocelot *ocelot, int port, 1200 const unsigned char *addr, u16 vid) 1201 { 1202 int pgid = port; 1203 1204 if (port == ocelot->npi) 1205 pgid = PGID_CPU; 1206 1207 return ocelot_mact_learn(ocelot, pgid, addr, vid, ENTRYTYPE_LOCKED); 1208 } 1209 EXPORT_SYMBOL(ocelot_fdb_add); 1210 1211 int ocelot_fdb_del(struct ocelot *ocelot, int port, 1212 const unsigned char *addr, u16 vid) 1213 { 1214 return ocelot_mact_forget(ocelot, addr, vid); 1215 } 1216 EXPORT_SYMBOL(ocelot_fdb_del); 1217 1218 int ocelot_port_fdb_do_dump(const unsigned char *addr, u16 vid, 1219 bool is_static, void *data) 1220 { 1221 struct ocelot_dump_ctx *dump = data; 1222 u32 portid = NETLINK_CB(dump->cb->skb).portid; 1223 u32 seq = dump->cb->nlh->nlmsg_seq; 1224 struct nlmsghdr *nlh; 1225 struct ndmsg *ndm; 1226 1227 if (dump->idx < dump->cb->args[2]) 1228 goto skip; 1229 1230 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH, 1231 sizeof(*ndm), NLM_F_MULTI); 1232 if (!nlh) 1233 return -EMSGSIZE; 1234 1235 ndm = nlmsg_data(nlh); 1236 ndm->ndm_family = AF_BRIDGE; 1237 ndm->ndm_pad1 = 0; 1238 ndm->ndm_pad2 = 0; 1239 ndm->ndm_flags = NTF_SELF; 1240 ndm->ndm_type = 0; 1241 ndm->ndm_ifindex = dump->dev->ifindex; 1242 ndm->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE; 1243 1244 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, addr)) 1245 goto nla_put_failure; 1246 1247 if (vid && nla_put_u16(dump->skb, NDA_VLAN, vid)) 1248 goto nla_put_failure; 1249 1250 nlmsg_end(dump->skb, nlh); 1251 1252 skip: 1253 dump->idx++; 1254 return 0; 1255 1256 nla_put_failure: 1257 nlmsg_cancel(dump->skb, nlh); 1258 return -EMSGSIZE; 1259 } 1260 EXPORT_SYMBOL(ocelot_port_fdb_do_dump); 1261 1262 /* Caller must hold &ocelot->mact_lock */ 1263 static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col, 1264 struct ocelot_mact_entry *entry) 1265 { 1266 u32 val, dst, macl, mach; 1267 char mac[ETH_ALEN]; 1268 1269 /* Set row and column to read from */ 1270 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row); 1271 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col); 1272 1273 /* Issue a read command */ 1274 ocelot_write(ocelot, 1275 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 1276 ANA_TABLES_MACACCESS); 1277 1278 if (ocelot_mact_wait_for_completion(ocelot)) 1279 return -ETIMEDOUT; 1280 1281 /* Read the entry flags */ 1282 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 1283 if (!(val & ANA_TABLES_MACACCESS_VALID)) 1284 return -EINVAL; 1285 1286 /* If the entry read has another port configured as its destination, 1287 * do not report it. 1288 */ 1289 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3; 1290 if (dst != port) 1291 return -EINVAL; 1292 1293 /* Get the entry's MAC address and VLAN id */ 1294 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA); 1295 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA); 1296 1297 mac[0] = (mach >> 8) & 0xff; 1298 mac[1] = (mach >> 0) & 0xff; 1299 mac[2] = (macl >> 24) & 0xff; 1300 mac[3] = (macl >> 16) & 0xff; 1301 mac[4] = (macl >> 8) & 0xff; 1302 mac[5] = (macl >> 0) & 0xff; 1303 1304 entry->vid = (mach >> 16) & 0xfff; 1305 ether_addr_copy(entry->mac, mac); 1306 1307 return 0; 1308 } 1309 1310 int ocelot_fdb_dump(struct ocelot *ocelot, int port, 1311 dsa_fdb_dump_cb_t *cb, void *data) 1312 { 1313 int err = 0; 1314 int i, j; 1315 1316 /* We could take the lock just around ocelot_mact_read, but doing so 1317 * thousands of times in a row seems rather pointless and inefficient. 1318 */ 1319 mutex_lock(&ocelot->mact_lock); 1320 1321 /* Loop through all the mac tables entries. */ 1322 for (i = 0; i < ocelot->num_mact_rows; i++) { 1323 for (j = 0; j < 4; j++) { 1324 struct ocelot_mact_entry entry; 1325 bool is_static; 1326 1327 err = ocelot_mact_read(ocelot, port, i, j, &entry); 1328 /* If the entry is invalid (wrong port, invalid...), 1329 * skip it. 1330 */ 1331 if (err == -EINVAL) 1332 continue; 1333 else if (err) 1334 break; 1335 1336 is_static = (entry.type == ENTRYTYPE_LOCKED); 1337 1338 err = cb(entry.mac, entry.vid, is_static, data); 1339 if (err) 1340 break; 1341 } 1342 } 1343 1344 mutex_unlock(&ocelot->mact_lock); 1345 1346 return err; 1347 } 1348 EXPORT_SYMBOL(ocelot_fdb_dump); 1349 1350 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr) 1351 { 1352 return copy_to_user(ifr->ifr_data, &ocelot->hwtstamp_config, 1353 sizeof(ocelot->hwtstamp_config)) ? -EFAULT : 0; 1354 } 1355 EXPORT_SYMBOL(ocelot_hwstamp_get); 1356 1357 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr) 1358 { 1359 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1360 struct hwtstamp_config cfg; 1361 1362 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1363 return -EFAULT; 1364 1365 /* reserved for future extensions */ 1366 if (cfg.flags) 1367 return -EINVAL; 1368 1369 /* Tx type sanity check */ 1370 switch (cfg.tx_type) { 1371 case HWTSTAMP_TX_ON: 1372 ocelot_port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP; 1373 break; 1374 case HWTSTAMP_TX_ONESTEP_SYNC: 1375 /* IFH_REW_OP_ONE_STEP_PTP updates the correctional field, we 1376 * need to update the origin time. 1377 */ 1378 ocelot_port->ptp_cmd = IFH_REW_OP_ORIGIN_PTP; 1379 break; 1380 case HWTSTAMP_TX_OFF: 1381 ocelot_port->ptp_cmd = 0; 1382 break; 1383 default: 1384 return -ERANGE; 1385 } 1386 1387 mutex_lock(&ocelot->ptp_lock); 1388 1389 switch (cfg.rx_filter) { 1390 case HWTSTAMP_FILTER_NONE: 1391 break; 1392 case HWTSTAMP_FILTER_ALL: 1393 case HWTSTAMP_FILTER_SOME: 1394 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1395 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1396 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1397 case HWTSTAMP_FILTER_NTP_ALL: 1398 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1399 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1400 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1401 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1402 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1403 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1404 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1405 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1406 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1407 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 1408 break; 1409 default: 1410 mutex_unlock(&ocelot->ptp_lock); 1411 return -ERANGE; 1412 } 1413 1414 /* Commit back the result & save it */ 1415 memcpy(&ocelot->hwtstamp_config, &cfg, sizeof(cfg)); 1416 mutex_unlock(&ocelot->ptp_lock); 1417 1418 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1419 } 1420 EXPORT_SYMBOL(ocelot_hwstamp_set); 1421 1422 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data) 1423 { 1424 int i; 1425 1426 if (sset != ETH_SS_STATS) 1427 return; 1428 1429 for (i = 0; i < ocelot->num_stats; i++) 1430 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name, 1431 ETH_GSTRING_LEN); 1432 } 1433 EXPORT_SYMBOL(ocelot_get_strings); 1434 1435 static void ocelot_update_stats(struct ocelot *ocelot) 1436 { 1437 int i, j; 1438 1439 mutex_lock(&ocelot->stats_lock); 1440 1441 for (i = 0; i < ocelot->num_phys_ports; i++) { 1442 /* Configure the port to read the stats from */ 1443 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(i), SYS_STAT_CFG); 1444 1445 for (j = 0; j < ocelot->num_stats; j++) { 1446 u32 val; 1447 unsigned int idx = i * ocelot->num_stats + j; 1448 1449 val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS, 1450 ocelot->stats_layout[j].offset); 1451 1452 if (val < (ocelot->stats[idx] & U32_MAX)) 1453 ocelot->stats[idx] += (u64)1 << 32; 1454 1455 ocelot->stats[idx] = (ocelot->stats[idx] & 1456 ~(u64)U32_MAX) + val; 1457 } 1458 } 1459 1460 mutex_unlock(&ocelot->stats_lock); 1461 } 1462 1463 static void ocelot_check_stats_work(struct work_struct *work) 1464 { 1465 struct delayed_work *del_work = to_delayed_work(work); 1466 struct ocelot *ocelot = container_of(del_work, struct ocelot, 1467 stats_work); 1468 1469 ocelot_update_stats(ocelot); 1470 1471 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 1472 OCELOT_STATS_CHECK_DELAY); 1473 } 1474 1475 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data) 1476 { 1477 int i; 1478 1479 /* check and update now */ 1480 ocelot_update_stats(ocelot); 1481 1482 /* Copy all counters */ 1483 for (i = 0; i < ocelot->num_stats; i++) 1484 *data++ = ocelot->stats[port * ocelot->num_stats + i]; 1485 } 1486 EXPORT_SYMBOL(ocelot_get_ethtool_stats); 1487 1488 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset) 1489 { 1490 if (sset != ETH_SS_STATS) 1491 return -EOPNOTSUPP; 1492 1493 return ocelot->num_stats; 1494 } 1495 EXPORT_SYMBOL(ocelot_get_sset_count); 1496 1497 int ocelot_get_ts_info(struct ocelot *ocelot, int port, 1498 struct ethtool_ts_info *info) 1499 { 1500 info->phc_index = ocelot->ptp_clock ? 1501 ptp_clock_index(ocelot->ptp_clock) : -1; 1502 if (info->phc_index == -1) { 1503 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 1504 SOF_TIMESTAMPING_RX_SOFTWARE | 1505 SOF_TIMESTAMPING_SOFTWARE; 1506 return 0; 1507 } 1508 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 1509 SOF_TIMESTAMPING_RX_SOFTWARE | 1510 SOF_TIMESTAMPING_SOFTWARE | 1511 SOF_TIMESTAMPING_TX_HARDWARE | 1512 SOF_TIMESTAMPING_RX_HARDWARE | 1513 SOF_TIMESTAMPING_RAW_HARDWARE; 1514 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON) | 1515 BIT(HWTSTAMP_TX_ONESTEP_SYNC); 1516 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL); 1517 1518 return 0; 1519 } 1520 EXPORT_SYMBOL(ocelot_get_ts_info); 1521 1522 static u32 ocelot_get_bond_mask(struct ocelot *ocelot, struct net_device *bond, 1523 bool only_active_ports) 1524 { 1525 u32 mask = 0; 1526 int port; 1527 1528 for (port = 0; port < ocelot->num_phys_ports; port++) { 1529 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1530 1531 if (!ocelot_port) 1532 continue; 1533 1534 if (ocelot_port->bond == bond) { 1535 if (only_active_ports && !ocelot_port->lag_tx_active) 1536 continue; 1537 1538 mask |= BIT(port); 1539 } 1540 } 1541 1542 return mask; 1543 } 1544 1545 static u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot, int src_port, 1546 struct net_device *bridge) 1547 { 1548 struct ocelot_port *ocelot_port = ocelot->ports[src_port]; 1549 u32 mask = 0; 1550 int port; 1551 1552 if (!ocelot_port || ocelot_port->bridge != bridge || 1553 ocelot_port->stp_state != BR_STATE_FORWARDING) 1554 return 0; 1555 1556 for (port = 0; port < ocelot->num_phys_ports; port++) { 1557 ocelot_port = ocelot->ports[port]; 1558 1559 if (!ocelot_port) 1560 continue; 1561 1562 if (ocelot_port->stp_state == BR_STATE_FORWARDING && 1563 ocelot_port->bridge == bridge) 1564 mask |= BIT(port); 1565 } 1566 1567 return mask; 1568 } 1569 1570 static u32 ocelot_get_dsa_8021q_cpu_mask(struct ocelot *ocelot) 1571 { 1572 u32 mask = 0; 1573 int port; 1574 1575 for (port = 0; port < ocelot->num_phys_ports; port++) { 1576 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1577 1578 if (!ocelot_port) 1579 continue; 1580 1581 if (ocelot_port->is_dsa_8021q_cpu) 1582 mask |= BIT(port); 1583 } 1584 1585 return mask; 1586 } 1587 1588 void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot) 1589 { 1590 unsigned long cpu_fwd_mask; 1591 int port; 1592 1593 /* If a DSA tag_8021q CPU exists, it needs to be included in the 1594 * regular forwarding path of the front ports regardless of whether 1595 * those are bridged or standalone. 1596 * If DSA tag_8021q is not used, this returns 0, which is fine because 1597 * the hardware-based CPU port module can be a destination for packets 1598 * even if it isn't part of PGID_SRC. 1599 */ 1600 cpu_fwd_mask = ocelot_get_dsa_8021q_cpu_mask(ocelot); 1601 1602 /* Apply FWD mask. The loop is needed to add/remove the current port as 1603 * a source for the other ports. 1604 */ 1605 for (port = 0; port < ocelot->num_phys_ports; port++) { 1606 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1607 unsigned long mask; 1608 1609 if (!ocelot_port) { 1610 /* Unused ports can't send anywhere */ 1611 mask = 0; 1612 } else if (ocelot_port->is_dsa_8021q_cpu) { 1613 /* The DSA tag_8021q CPU ports need to be able to 1614 * forward packets to all other ports except for 1615 * themselves 1616 */ 1617 mask = GENMASK(ocelot->num_phys_ports - 1, 0); 1618 mask &= ~cpu_fwd_mask; 1619 } else if (ocelot_port->bridge) { 1620 struct net_device *bridge = ocelot_port->bridge; 1621 struct net_device *bond = ocelot_port->bond; 1622 1623 mask = ocelot_get_bridge_fwd_mask(ocelot, port, bridge); 1624 mask |= cpu_fwd_mask; 1625 mask &= ~BIT(port); 1626 if (bond) { 1627 mask &= ~ocelot_get_bond_mask(ocelot, bond, 1628 false); 1629 } 1630 } else { 1631 /* Standalone ports forward only to DSA tag_8021q CPU 1632 * ports (if those exist), or to the hardware CPU port 1633 * module otherwise. 1634 */ 1635 mask = cpu_fwd_mask; 1636 } 1637 1638 ocelot_write_rix(ocelot, mask, ANA_PGID_PGID, PGID_SRC + port); 1639 } 1640 } 1641 EXPORT_SYMBOL(ocelot_apply_bridge_fwd_mask); 1642 1643 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state) 1644 { 1645 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1646 u32 learn_ena = 0; 1647 1648 ocelot_port->stp_state = state; 1649 1650 if ((state == BR_STATE_LEARNING || state == BR_STATE_FORWARDING) && 1651 ocelot_port->learn_ena) 1652 learn_ena = ANA_PORT_PORT_CFG_LEARN_ENA; 1653 1654 ocelot_rmw_gix(ocelot, learn_ena, ANA_PORT_PORT_CFG_LEARN_ENA, 1655 ANA_PORT_PORT_CFG, port); 1656 1657 ocelot_apply_bridge_fwd_mask(ocelot); 1658 } 1659 EXPORT_SYMBOL(ocelot_bridge_stp_state_set); 1660 1661 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs) 1662 { 1663 unsigned int age_period = ANA_AUTOAGE_AGE_PERIOD(msecs / 2000); 1664 1665 /* Setting AGE_PERIOD to zero effectively disables automatic aging, 1666 * which is clearly not what our intention is. So avoid that. 1667 */ 1668 if (!age_period) 1669 age_period = 1; 1670 1671 ocelot_rmw(ocelot, age_period, ANA_AUTOAGE_AGE_PERIOD_M, ANA_AUTOAGE); 1672 } 1673 EXPORT_SYMBOL(ocelot_set_ageing_time); 1674 1675 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot, 1676 const unsigned char *addr, 1677 u16 vid) 1678 { 1679 struct ocelot_multicast *mc; 1680 1681 list_for_each_entry(mc, &ocelot->multicast, list) { 1682 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid) 1683 return mc; 1684 } 1685 1686 return NULL; 1687 } 1688 1689 static enum macaccess_entry_type ocelot_classify_mdb(const unsigned char *addr) 1690 { 1691 if (addr[0] == 0x01 && addr[1] == 0x00 && addr[2] == 0x5e) 1692 return ENTRYTYPE_MACv4; 1693 if (addr[0] == 0x33 && addr[1] == 0x33) 1694 return ENTRYTYPE_MACv6; 1695 return ENTRYTYPE_LOCKED; 1696 } 1697 1698 static struct ocelot_pgid *ocelot_pgid_alloc(struct ocelot *ocelot, int index, 1699 unsigned long ports) 1700 { 1701 struct ocelot_pgid *pgid; 1702 1703 pgid = kzalloc(sizeof(*pgid), GFP_KERNEL); 1704 if (!pgid) 1705 return ERR_PTR(-ENOMEM); 1706 1707 pgid->ports = ports; 1708 pgid->index = index; 1709 refcount_set(&pgid->refcount, 1); 1710 list_add_tail(&pgid->list, &ocelot->pgids); 1711 1712 return pgid; 1713 } 1714 1715 static void ocelot_pgid_free(struct ocelot *ocelot, struct ocelot_pgid *pgid) 1716 { 1717 if (!refcount_dec_and_test(&pgid->refcount)) 1718 return; 1719 1720 list_del(&pgid->list); 1721 kfree(pgid); 1722 } 1723 1724 static struct ocelot_pgid *ocelot_mdb_get_pgid(struct ocelot *ocelot, 1725 const struct ocelot_multicast *mc) 1726 { 1727 struct ocelot_pgid *pgid; 1728 int index; 1729 1730 /* According to VSC7514 datasheet 3.9.1.5 IPv4 Multicast Entries and 1731 * 3.9.1.6 IPv6 Multicast Entries, "Instead of a lookup in the 1732 * destination mask table (PGID), the destination set is programmed as 1733 * part of the entry MAC address.", and the DEST_IDX is set to 0. 1734 */ 1735 if (mc->entry_type == ENTRYTYPE_MACv4 || 1736 mc->entry_type == ENTRYTYPE_MACv6) 1737 return ocelot_pgid_alloc(ocelot, 0, mc->ports); 1738 1739 list_for_each_entry(pgid, &ocelot->pgids, list) { 1740 /* When searching for a nonreserved multicast PGID, ignore the 1741 * dummy PGID of zero that we have for MACv4/MACv6 entries 1742 */ 1743 if (pgid->index && pgid->ports == mc->ports) { 1744 refcount_inc(&pgid->refcount); 1745 return pgid; 1746 } 1747 } 1748 1749 /* Search for a free index in the nonreserved multicast PGID area */ 1750 for_each_nonreserved_multicast_dest_pgid(ocelot, index) { 1751 bool used = false; 1752 1753 list_for_each_entry(pgid, &ocelot->pgids, list) { 1754 if (pgid->index == index) { 1755 used = true; 1756 break; 1757 } 1758 } 1759 1760 if (!used) 1761 return ocelot_pgid_alloc(ocelot, index, mc->ports); 1762 } 1763 1764 return ERR_PTR(-ENOSPC); 1765 } 1766 1767 static void ocelot_encode_ports_to_mdb(unsigned char *addr, 1768 struct ocelot_multicast *mc) 1769 { 1770 ether_addr_copy(addr, mc->addr); 1771 1772 if (mc->entry_type == ENTRYTYPE_MACv4) { 1773 addr[0] = 0; 1774 addr[1] = mc->ports >> 8; 1775 addr[2] = mc->ports & 0xff; 1776 } else if (mc->entry_type == ENTRYTYPE_MACv6) { 1777 addr[0] = mc->ports >> 8; 1778 addr[1] = mc->ports & 0xff; 1779 } 1780 } 1781 1782 int ocelot_port_mdb_add(struct ocelot *ocelot, int port, 1783 const struct switchdev_obj_port_mdb *mdb) 1784 { 1785 unsigned char addr[ETH_ALEN]; 1786 struct ocelot_multicast *mc; 1787 struct ocelot_pgid *pgid; 1788 u16 vid = mdb->vid; 1789 1790 if (port == ocelot->npi) 1791 port = ocelot->num_phys_ports; 1792 1793 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1794 if (!mc) { 1795 /* New entry */ 1796 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL); 1797 if (!mc) 1798 return -ENOMEM; 1799 1800 mc->entry_type = ocelot_classify_mdb(mdb->addr); 1801 ether_addr_copy(mc->addr, mdb->addr); 1802 mc->vid = vid; 1803 1804 list_add_tail(&mc->list, &ocelot->multicast); 1805 } else { 1806 /* Existing entry. Clean up the current port mask from 1807 * hardware now, because we'll be modifying it. 1808 */ 1809 ocelot_pgid_free(ocelot, mc->pgid); 1810 ocelot_encode_ports_to_mdb(addr, mc); 1811 ocelot_mact_forget(ocelot, addr, vid); 1812 } 1813 1814 mc->ports |= BIT(port); 1815 1816 pgid = ocelot_mdb_get_pgid(ocelot, mc); 1817 if (IS_ERR(pgid)) { 1818 dev_err(ocelot->dev, 1819 "Cannot allocate PGID for mdb %pM vid %d\n", 1820 mc->addr, mc->vid); 1821 devm_kfree(ocelot->dev, mc); 1822 return PTR_ERR(pgid); 1823 } 1824 mc->pgid = pgid; 1825 1826 ocelot_encode_ports_to_mdb(addr, mc); 1827 1828 if (mc->entry_type != ENTRYTYPE_MACv4 && 1829 mc->entry_type != ENTRYTYPE_MACv6) 1830 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 1831 pgid->index); 1832 1833 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 1834 mc->entry_type); 1835 } 1836 EXPORT_SYMBOL(ocelot_port_mdb_add); 1837 1838 int ocelot_port_mdb_del(struct ocelot *ocelot, int port, 1839 const struct switchdev_obj_port_mdb *mdb) 1840 { 1841 unsigned char addr[ETH_ALEN]; 1842 struct ocelot_multicast *mc; 1843 struct ocelot_pgid *pgid; 1844 u16 vid = mdb->vid; 1845 1846 if (port == ocelot->npi) 1847 port = ocelot->num_phys_ports; 1848 1849 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1850 if (!mc) 1851 return -ENOENT; 1852 1853 ocelot_encode_ports_to_mdb(addr, mc); 1854 ocelot_mact_forget(ocelot, addr, vid); 1855 1856 ocelot_pgid_free(ocelot, mc->pgid); 1857 mc->ports &= ~BIT(port); 1858 if (!mc->ports) { 1859 list_del(&mc->list); 1860 devm_kfree(ocelot->dev, mc); 1861 return 0; 1862 } 1863 1864 /* We have a PGID with fewer ports now */ 1865 pgid = ocelot_mdb_get_pgid(ocelot, mc); 1866 if (IS_ERR(pgid)) 1867 return PTR_ERR(pgid); 1868 mc->pgid = pgid; 1869 1870 ocelot_encode_ports_to_mdb(addr, mc); 1871 1872 if (mc->entry_type != ENTRYTYPE_MACv4 && 1873 mc->entry_type != ENTRYTYPE_MACv6) 1874 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 1875 pgid->index); 1876 1877 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 1878 mc->entry_type); 1879 } 1880 EXPORT_SYMBOL(ocelot_port_mdb_del); 1881 1882 void ocelot_port_bridge_join(struct ocelot *ocelot, int port, 1883 struct net_device *bridge) 1884 { 1885 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1886 1887 ocelot_port->bridge = bridge; 1888 1889 ocelot_apply_bridge_fwd_mask(ocelot); 1890 } 1891 EXPORT_SYMBOL(ocelot_port_bridge_join); 1892 1893 void ocelot_port_bridge_leave(struct ocelot *ocelot, int port, 1894 struct net_device *bridge) 1895 { 1896 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1897 1898 ocelot_port->bridge = NULL; 1899 1900 ocelot_port_set_pvid(ocelot, port, NULL); 1901 ocelot_port_manage_port_tag(ocelot, port); 1902 ocelot_apply_bridge_fwd_mask(ocelot); 1903 } 1904 EXPORT_SYMBOL(ocelot_port_bridge_leave); 1905 1906 static void ocelot_set_aggr_pgids(struct ocelot *ocelot) 1907 { 1908 unsigned long visited = GENMASK(ocelot->num_phys_ports - 1, 0); 1909 int i, port, lag; 1910 1911 /* Reset destination and aggregation PGIDS */ 1912 for_each_unicast_dest_pgid(ocelot, port) 1913 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 1914 1915 for_each_aggr_pgid(ocelot, i) 1916 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 1917 ANA_PGID_PGID, i); 1918 1919 /* The visited ports bitmask holds the list of ports offloading any 1920 * bonding interface. Initially we mark all these ports as unvisited, 1921 * then every time we visit a port in this bitmask, we know that it is 1922 * the lowest numbered port, i.e. the one whose logical ID == physical 1923 * port ID == LAG ID. So we mark as visited all further ports in the 1924 * bitmask that are offloading the same bonding interface. This way, 1925 * we set up the aggregation PGIDs only once per bonding interface. 1926 */ 1927 for (port = 0; port < ocelot->num_phys_ports; port++) { 1928 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1929 1930 if (!ocelot_port || !ocelot_port->bond) 1931 continue; 1932 1933 visited &= ~BIT(port); 1934 } 1935 1936 /* Now, set PGIDs for each active LAG */ 1937 for (lag = 0; lag < ocelot->num_phys_ports; lag++) { 1938 struct net_device *bond = ocelot->ports[lag]->bond; 1939 int num_active_ports = 0; 1940 unsigned long bond_mask; 1941 u8 aggr_idx[16]; 1942 1943 if (!bond || (visited & BIT(lag))) 1944 continue; 1945 1946 bond_mask = ocelot_get_bond_mask(ocelot, bond, true); 1947 1948 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) { 1949 // Destination mask 1950 ocelot_write_rix(ocelot, bond_mask, 1951 ANA_PGID_PGID, port); 1952 aggr_idx[num_active_ports++] = port; 1953 } 1954 1955 for_each_aggr_pgid(ocelot, i) { 1956 u32 ac; 1957 1958 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i); 1959 ac &= ~bond_mask; 1960 /* Don't do division by zero if there was no active 1961 * port. Just make all aggregation codes zero. 1962 */ 1963 if (num_active_ports) 1964 ac |= BIT(aggr_idx[i % num_active_ports]); 1965 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i); 1966 } 1967 1968 /* Mark all ports in the same LAG as visited to avoid applying 1969 * the same config again. 1970 */ 1971 for (port = lag; port < ocelot->num_phys_ports; port++) { 1972 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1973 1974 if (!ocelot_port) 1975 continue; 1976 1977 if (ocelot_port->bond == bond) 1978 visited |= BIT(port); 1979 } 1980 } 1981 } 1982 1983 /* When offloading a bonding interface, the switch ports configured under the 1984 * same bond must have the same logical port ID, equal to the physical port ID 1985 * of the lowest numbered physical port in that bond. Otherwise, in standalone/ 1986 * bridged mode, each port has a logical port ID equal to its physical port ID. 1987 */ 1988 static void ocelot_setup_logical_port_ids(struct ocelot *ocelot) 1989 { 1990 int port; 1991 1992 for (port = 0; port < ocelot->num_phys_ports; port++) { 1993 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1994 struct net_device *bond; 1995 1996 if (!ocelot_port) 1997 continue; 1998 1999 bond = ocelot_port->bond; 2000 if (bond) { 2001 int lag = __ffs(ocelot_get_bond_mask(ocelot, bond, 2002 false)); 2003 2004 ocelot_rmw_gix(ocelot, 2005 ANA_PORT_PORT_CFG_PORTID_VAL(lag), 2006 ANA_PORT_PORT_CFG_PORTID_VAL_M, 2007 ANA_PORT_PORT_CFG, port); 2008 } else { 2009 ocelot_rmw_gix(ocelot, 2010 ANA_PORT_PORT_CFG_PORTID_VAL(port), 2011 ANA_PORT_PORT_CFG_PORTID_VAL_M, 2012 ANA_PORT_PORT_CFG, port); 2013 } 2014 } 2015 } 2016 2017 int ocelot_port_lag_join(struct ocelot *ocelot, int port, 2018 struct net_device *bond, 2019 struct netdev_lag_upper_info *info) 2020 { 2021 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) 2022 return -EOPNOTSUPP; 2023 2024 ocelot->ports[port]->bond = bond; 2025 2026 ocelot_setup_logical_port_ids(ocelot); 2027 ocelot_apply_bridge_fwd_mask(ocelot); 2028 ocelot_set_aggr_pgids(ocelot); 2029 2030 return 0; 2031 } 2032 EXPORT_SYMBOL(ocelot_port_lag_join); 2033 2034 void ocelot_port_lag_leave(struct ocelot *ocelot, int port, 2035 struct net_device *bond) 2036 { 2037 ocelot->ports[port]->bond = NULL; 2038 2039 ocelot_setup_logical_port_ids(ocelot); 2040 ocelot_apply_bridge_fwd_mask(ocelot); 2041 ocelot_set_aggr_pgids(ocelot); 2042 } 2043 EXPORT_SYMBOL(ocelot_port_lag_leave); 2044 2045 void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active) 2046 { 2047 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2048 2049 ocelot_port->lag_tx_active = lag_tx_active; 2050 2051 /* Rebalance the LAGs */ 2052 ocelot_set_aggr_pgids(ocelot); 2053 } 2054 EXPORT_SYMBOL(ocelot_port_lag_change); 2055 2056 /* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu. 2057 * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG. 2058 * In the special case that it's the NPI port that we're configuring, the 2059 * length of the tag and optional prefix needs to be accounted for privately, 2060 * in order to be able to sustain communication at the requested @sdu. 2061 */ 2062 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu) 2063 { 2064 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2065 int maxlen = sdu + ETH_HLEN + ETH_FCS_LEN; 2066 int pause_start, pause_stop; 2067 int atop, atop_tot; 2068 2069 if (port == ocelot->npi) { 2070 maxlen += OCELOT_TAG_LEN; 2071 2072 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT) 2073 maxlen += OCELOT_SHORT_PREFIX_LEN; 2074 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG) 2075 maxlen += OCELOT_LONG_PREFIX_LEN; 2076 } 2077 2078 ocelot_port_writel(ocelot_port, maxlen, DEV_MAC_MAXLEN_CFG); 2079 2080 /* Set Pause watermark hysteresis */ 2081 pause_start = 6 * maxlen / OCELOT_BUFFER_CELL_SZ; 2082 pause_stop = 4 * maxlen / OCELOT_BUFFER_CELL_SZ; 2083 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_START, 2084 pause_start); 2085 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_STOP, 2086 pause_stop); 2087 2088 /* Tail dropping watermarks */ 2089 atop_tot = (ocelot->packet_buffer_size - 9 * maxlen) / 2090 OCELOT_BUFFER_CELL_SZ; 2091 atop = (9 * maxlen) / OCELOT_BUFFER_CELL_SZ; 2092 ocelot_write_rix(ocelot, ocelot->ops->wm_enc(atop), SYS_ATOP, port); 2093 ocelot_write(ocelot, ocelot->ops->wm_enc(atop_tot), SYS_ATOP_TOT_CFG); 2094 } 2095 EXPORT_SYMBOL(ocelot_port_set_maxlen); 2096 2097 int ocelot_get_max_mtu(struct ocelot *ocelot, int port) 2098 { 2099 int max_mtu = 65535 - ETH_HLEN - ETH_FCS_LEN; 2100 2101 if (port == ocelot->npi) { 2102 max_mtu -= OCELOT_TAG_LEN; 2103 2104 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT) 2105 max_mtu -= OCELOT_SHORT_PREFIX_LEN; 2106 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG) 2107 max_mtu -= OCELOT_LONG_PREFIX_LEN; 2108 } 2109 2110 return max_mtu; 2111 } 2112 EXPORT_SYMBOL(ocelot_get_max_mtu); 2113 2114 static void ocelot_port_set_learning(struct ocelot *ocelot, int port, 2115 bool enabled) 2116 { 2117 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2118 u32 val = 0; 2119 2120 if (enabled) 2121 val = ANA_PORT_PORT_CFG_LEARN_ENA; 2122 2123 ocelot_rmw_gix(ocelot, val, ANA_PORT_PORT_CFG_LEARN_ENA, 2124 ANA_PORT_PORT_CFG, port); 2125 2126 ocelot_port->learn_ena = enabled; 2127 } 2128 2129 static void ocelot_port_set_ucast_flood(struct ocelot *ocelot, int port, 2130 bool enabled) 2131 { 2132 u32 val = 0; 2133 2134 if (enabled) 2135 val = BIT(port); 2136 2137 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_UC); 2138 } 2139 2140 static void ocelot_port_set_mcast_flood(struct ocelot *ocelot, int port, 2141 bool enabled) 2142 { 2143 u32 val = 0; 2144 2145 if (enabled) 2146 val = BIT(port); 2147 2148 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MC); 2149 } 2150 2151 static void ocelot_port_set_bcast_flood(struct ocelot *ocelot, int port, 2152 bool enabled) 2153 { 2154 u32 val = 0; 2155 2156 if (enabled) 2157 val = BIT(port); 2158 2159 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_BC); 2160 } 2161 2162 int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port, 2163 struct switchdev_brport_flags flags) 2164 { 2165 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 2166 BR_BCAST_FLOOD)) 2167 return -EINVAL; 2168 2169 return 0; 2170 } 2171 EXPORT_SYMBOL(ocelot_port_pre_bridge_flags); 2172 2173 void ocelot_port_bridge_flags(struct ocelot *ocelot, int port, 2174 struct switchdev_brport_flags flags) 2175 { 2176 if (flags.mask & BR_LEARNING) 2177 ocelot_port_set_learning(ocelot, port, 2178 !!(flags.val & BR_LEARNING)); 2179 2180 if (flags.mask & BR_FLOOD) 2181 ocelot_port_set_ucast_flood(ocelot, port, 2182 !!(flags.val & BR_FLOOD)); 2183 2184 if (flags.mask & BR_MCAST_FLOOD) 2185 ocelot_port_set_mcast_flood(ocelot, port, 2186 !!(flags.val & BR_MCAST_FLOOD)); 2187 2188 if (flags.mask & BR_BCAST_FLOOD) 2189 ocelot_port_set_bcast_flood(ocelot, port, 2190 !!(flags.val & BR_BCAST_FLOOD)); 2191 } 2192 EXPORT_SYMBOL(ocelot_port_bridge_flags); 2193 2194 void ocelot_init_port(struct ocelot *ocelot, int port) 2195 { 2196 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2197 2198 skb_queue_head_init(&ocelot_port->tx_skbs); 2199 2200 /* Basic L2 initialization */ 2201 2202 /* Set MAC IFG Gaps 2203 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0 2204 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5 2205 */ 2206 ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5), 2207 DEV_MAC_IFG_CFG); 2208 2209 /* Load seed (0) and set MAC HDX late collision */ 2210 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) | 2211 DEV_MAC_HDX_CFG_SEED_LOAD, 2212 DEV_MAC_HDX_CFG); 2213 mdelay(1); 2214 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67), 2215 DEV_MAC_HDX_CFG); 2216 2217 /* Set Max Length and maximum tags allowed */ 2218 ocelot_port_set_maxlen(ocelot, port, ETH_DATA_LEN); 2219 ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) | 2220 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA | 2221 DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA | 2222 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, 2223 DEV_MAC_TAGS_CFG); 2224 2225 /* Set SMAC of Pause frame (00:00:00:00:00:00) */ 2226 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG); 2227 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG); 2228 2229 /* Enable transmission of pause frames */ 2230 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1); 2231 2232 /* Drop frames with multicast source address */ 2233 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 2234 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 2235 ANA_PORT_DROP_CFG, port); 2236 2237 /* Set default VLAN and tag type to 8021Q. */ 2238 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q), 2239 REW_PORT_VLAN_CFG_PORT_TPID_M, 2240 REW_PORT_VLAN_CFG, port); 2241 2242 /* Disable source address learning for standalone mode */ 2243 ocelot_port_set_learning(ocelot, port, false); 2244 2245 /* Set the port's initial logical port ID value, enable receiving 2246 * frames on it, and configure the MAC address learning type to 2247 * automatic. 2248 */ 2249 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO | 2250 ANA_PORT_PORT_CFG_RECV_ENA | 2251 ANA_PORT_PORT_CFG_PORTID_VAL(port), 2252 ANA_PORT_PORT_CFG, port); 2253 2254 /* Enable vcap lookups */ 2255 ocelot_vcap_enable(ocelot, port); 2256 } 2257 EXPORT_SYMBOL(ocelot_init_port); 2258 2259 /* Configure and enable the CPU port module, which is a set of queues 2260 * accessible through register MMIO, frame DMA or Ethernet (in case 2261 * NPI mode is used). 2262 */ 2263 static void ocelot_cpu_port_init(struct ocelot *ocelot) 2264 { 2265 int cpu = ocelot->num_phys_ports; 2266 2267 /* The unicast destination PGID for the CPU port module is unused */ 2268 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu); 2269 /* Instead set up a multicast destination PGID for traffic copied to 2270 * the CPU. Whitelisted MAC addresses like the port netdevice MAC 2271 * addresses will be copied to the CPU via this PGID. 2272 */ 2273 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU); 2274 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA | 2275 ANA_PORT_PORT_CFG_PORTID_VAL(cpu), 2276 ANA_PORT_PORT_CFG, cpu); 2277 2278 /* Enable CPU port module */ 2279 ocelot_fields_write(ocelot, cpu, QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 2280 /* CPU port Injection/Extraction configuration */ 2281 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_XTR_HDR, 2282 OCELOT_TAG_PREFIX_NONE); 2283 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_INJ_HDR, 2284 OCELOT_TAG_PREFIX_NONE); 2285 2286 /* Configure the CPU port to be VLAN aware */ 2287 ocelot_write_gix(ocelot, 2288 ANA_PORT_VLAN_CFG_VLAN_VID(OCELOT_VLAN_UNAWARE_PVID) | 2289 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 2290 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1), 2291 ANA_PORT_VLAN_CFG, cpu); 2292 } 2293 2294 static void ocelot_detect_features(struct ocelot *ocelot) 2295 { 2296 int mmgt, eq_ctrl; 2297 2298 /* For Ocelot, Felix, Seville, Serval etc, SYS:MMGT:MMGT:FREECNT holds 2299 * the number of 240-byte free memory words (aka 4-cell chunks) and not 2300 * 192 bytes as the documentation incorrectly says. 2301 */ 2302 mmgt = ocelot_read(ocelot, SYS_MMGT); 2303 ocelot->packet_buffer_size = 240 * SYS_MMGT_FREECNT(mmgt); 2304 2305 eq_ctrl = ocelot_read(ocelot, QSYS_EQ_CTRL); 2306 ocelot->num_frame_refs = QSYS_MMGT_EQ_CTRL_FP_FREE_CNT(eq_ctrl); 2307 } 2308 2309 int ocelot_init(struct ocelot *ocelot) 2310 { 2311 char queue_name[32]; 2312 int i, ret; 2313 u32 port; 2314 2315 if (ocelot->ops->reset) { 2316 ret = ocelot->ops->reset(ocelot); 2317 if (ret) { 2318 dev_err(ocelot->dev, "Switch reset failed\n"); 2319 return ret; 2320 } 2321 } 2322 2323 ocelot->stats = devm_kcalloc(ocelot->dev, 2324 ocelot->num_phys_ports * ocelot->num_stats, 2325 sizeof(u64), GFP_KERNEL); 2326 if (!ocelot->stats) 2327 return -ENOMEM; 2328 2329 mutex_init(&ocelot->stats_lock); 2330 mutex_init(&ocelot->ptp_lock); 2331 mutex_init(&ocelot->mact_lock); 2332 spin_lock_init(&ocelot->ptp_clock_lock); 2333 spin_lock_init(&ocelot->ts_id_lock); 2334 snprintf(queue_name, sizeof(queue_name), "%s-stats", 2335 dev_name(ocelot->dev)); 2336 ocelot->stats_queue = create_singlethread_workqueue(queue_name); 2337 if (!ocelot->stats_queue) 2338 return -ENOMEM; 2339 2340 ocelot->owq = alloc_ordered_workqueue("ocelot-owq", 0); 2341 if (!ocelot->owq) { 2342 destroy_workqueue(ocelot->stats_queue); 2343 return -ENOMEM; 2344 } 2345 2346 INIT_LIST_HEAD(&ocelot->multicast); 2347 INIT_LIST_HEAD(&ocelot->pgids); 2348 INIT_LIST_HEAD(&ocelot->vlans); 2349 ocelot_detect_features(ocelot); 2350 ocelot_mact_init(ocelot); 2351 ocelot_vlan_init(ocelot); 2352 ocelot_vcap_init(ocelot); 2353 ocelot_cpu_port_init(ocelot); 2354 2355 if (ocelot->ops->psfp_init) 2356 ocelot->ops->psfp_init(ocelot); 2357 2358 for (port = 0; port < ocelot->num_phys_ports; port++) { 2359 /* Clear all counters (5 groups) */ 2360 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) | 2361 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f), 2362 SYS_STAT_CFG); 2363 } 2364 2365 /* Only use S-Tag */ 2366 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG); 2367 2368 /* Aggregation mode */ 2369 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA | 2370 ANA_AGGR_CFG_AC_DMAC_ENA | 2371 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA | 2372 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA | 2373 ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA | 2374 ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA, 2375 ANA_AGGR_CFG); 2376 2377 /* Set MAC age time to default value. The entry is aged after 2378 * 2*AGE_PERIOD 2379 */ 2380 ocelot_write(ocelot, 2381 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ), 2382 ANA_AUTOAGE); 2383 2384 /* Disable learning for frames discarded by VLAN ingress filtering */ 2385 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1); 2386 2387 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */ 2388 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA | 2389 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING); 2390 2391 /* Setup flooding PGIDs */ 2392 for (i = 0; i < ocelot->num_flooding_pgids; i++) 2393 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) | 2394 ANA_FLOODING_FLD_BROADCAST(PGID_BC) | 2395 ANA_FLOODING_FLD_UNICAST(PGID_UC), 2396 ANA_FLOODING, i); 2397 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) | 2398 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) | 2399 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) | 2400 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC), 2401 ANA_FLOODING_IPMC); 2402 2403 for (port = 0; port < ocelot->num_phys_ports; port++) { 2404 /* Transmit the frame to the local port. */ 2405 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 2406 /* Do not forward BPDU frames to the front ports. */ 2407 ocelot_write_gix(ocelot, 2408 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff), 2409 ANA_PORT_CPU_FWD_BPDU_CFG, 2410 port); 2411 /* Ensure bridging is disabled */ 2412 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port); 2413 } 2414 2415 for_each_nonreserved_multicast_dest_pgid(ocelot, i) { 2416 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0)); 2417 2418 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 2419 } 2420 2421 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_BLACKHOLE); 2422 2423 /* Allow broadcast and unknown L2 multicast to the CPU. */ 2424 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2425 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2426 ANA_PGID_PGID, PGID_MC); 2427 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2428 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2429 ANA_PGID_PGID, PGID_BC); 2430 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4); 2431 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6); 2432 2433 /* Allow manual injection via DEVCPU_QS registers, and byte swap these 2434 * registers endianness. 2435 */ 2436 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP | 2437 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0); 2438 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP | 2439 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0); 2440 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) | 2441 ANA_CPUQ_CFG_CPUQ_LRN(2) | 2442 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) | 2443 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) | 2444 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) | 2445 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) | 2446 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) | 2447 ANA_CPUQ_CFG_CPUQ_IGMP(6) | 2448 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG); 2449 for (i = 0; i < 16; i++) 2450 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) | 2451 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6), 2452 ANA_CPUQ_8021_CFG, i); 2453 2454 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats_work); 2455 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 2456 OCELOT_STATS_CHECK_DELAY); 2457 2458 return 0; 2459 } 2460 EXPORT_SYMBOL(ocelot_init); 2461 2462 void ocelot_deinit(struct ocelot *ocelot) 2463 { 2464 cancel_delayed_work(&ocelot->stats_work); 2465 destroy_workqueue(ocelot->stats_queue); 2466 destroy_workqueue(ocelot->owq); 2467 mutex_destroy(&ocelot->stats_lock); 2468 } 2469 EXPORT_SYMBOL(ocelot_deinit); 2470 2471 void ocelot_deinit_port(struct ocelot *ocelot, int port) 2472 { 2473 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2474 2475 skb_queue_purge(&ocelot_port->tx_skbs); 2476 } 2477 EXPORT_SYMBOL(ocelot_deinit_port); 2478 2479 MODULE_LICENSE("Dual MIT/GPL"); 2480