1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7 #include <linux/dsa/ocelot.h> 8 #include <linux/if_bridge.h> 9 #include <linux/ptp_classify.h> 10 #include <soc/mscc/ocelot_vcap.h> 11 #include "ocelot.h" 12 #include "ocelot_vcap.h" 13 14 #define TABLE_UPDATE_SLEEP_US 10 15 #define TABLE_UPDATE_TIMEOUT_US 100000 16 17 struct ocelot_mact_entry { 18 u8 mac[ETH_ALEN]; 19 u16 vid; 20 enum macaccess_entry_type type; 21 }; 22 23 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot) 24 { 25 return ocelot_read(ocelot, ANA_TABLES_MACACCESS); 26 } 27 28 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot) 29 { 30 u32 val; 31 32 return readx_poll_timeout(ocelot_mact_read_macaccess, 33 ocelot, val, 34 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) == 35 MACACCESS_CMD_IDLE, 36 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 37 } 38 39 static void ocelot_mact_select(struct ocelot *ocelot, 40 const unsigned char mac[ETH_ALEN], 41 unsigned int vid) 42 { 43 u32 macl = 0, mach = 0; 44 45 /* Set the MAC address to handle and the vlan associated in a format 46 * understood by the hardware. 47 */ 48 mach |= vid << 16; 49 mach |= mac[0] << 8; 50 mach |= mac[1] << 0; 51 macl |= mac[2] << 24; 52 macl |= mac[3] << 16; 53 macl |= mac[4] << 8; 54 macl |= mac[5] << 0; 55 56 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA); 57 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA); 58 59 } 60 61 int ocelot_mact_learn(struct ocelot *ocelot, int port, 62 const unsigned char mac[ETH_ALEN], 63 unsigned int vid, enum macaccess_entry_type type) 64 { 65 u32 cmd = ANA_TABLES_MACACCESS_VALID | 66 ANA_TABLES_MACACCESS_DEST_IDX(port) | 67 ANA_TABLES_MACACCESS_ENTRYTYPE(type) | 68 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN); 69 unsigned int mc_ports; 70 71 /* Set MAC_CPU_COPY if the CPU port is used by a multicast entry */ 72 if (type == ENTRYTYPE_MACv4) 73 mc_ports = (mac[1] << 8) | mac[2]; 74 else if (type == ENTRYTYPE_MACv6) 75 mc_ports = (mac[0] << 8) | mac[1]; 76 else 77 mc_ports = 0; 78 79 if (mc_ports & BIT(ocelot->num_phys_ports)) 80 cmd |= ANA_TABLES_MACACCESS_MAC_CPU_COPY; 81 82 ocelot_mact_select(ocelot, mac, vid); 83 84 /* Issue a write command */ 85 ocelot_write(ocelot, cmd, ANA_TABLES_MACACCESS); 86 87 return ocelot_mact_wait_for_completion(ocelot); 88 } 89 EXPORT_SYMBOL(ocelot_mact_learn); 90 91 int ocelot_mact_forget(struct ocelot *ocelot, 92 const unsigned char mac[ETH_ALEN], unsigned int vid) 93 { 94 ocelot_mact_select(ocelot, mac, vid); 95 96 /* Issue a forget command */ 97 ocelot_write(ocelot, 98 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET), 99 ANA_TABLES_MACACCESS); 100 101 return ocelot_mact_wait_for_completion(ocelot); 102 } 103 EXPORT_SYMBOL(ocelot_mact_forget); 104 105 static void ocelot_mact_init(struct ocelot *ocelot) 106 { 107 /* Configure the learning mode entries attributes: 108 * - Do not copy the frame to the CPU extraction queues. 109 * - Use the vlan and mac_cpoy for dmac lookup. 110 */ 111 ocelot_rmw(ocelot, 0, 112 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS 113 | ANA_AGENCTRL_LEARN_FWD_KILL 114 | ANA_AGENCTRL_LEARN_IGNORE_VLAN, 115 ANA_AGENCTRL); 116 117 /* Clear the MAC table */ 118 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS); 119 } 120 121 static void ocelot_vcap_enable(struct ocelot *ocelot, int port) 122 { 123 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA | 124 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa), 125 ANA_PORT_VCAP_S2_CFG, port); 126 127 ocelot_write_gix(ocelot, ANA_PORT_VCAP_CFG_S1_ENA, 128 ANA_PORT_VCAP_CFG, port); 129 130 ocelot_rmw_gix(ocelot, REW_PORT_CFG_ES0_EN, 131 REW_PORT_CFG_ES0_EN, 132 REW_PORT_CFG, port); 133 } 134 135 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot) 136 { 137 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS); 138 } 139 140 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot) 141 { 142 u32 val; 143 144 return readx_poll_timeout(ocelot_vlant_read_vlanaccess, 145 ocelot, 146 val, 147 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) == 148 ANA_TABLES_VLANACCESS_CMD_IDLE, 149 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 150 } 151 152 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask) 153 { 154 /* Select the VID to configure */ 155 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid), 156 ANA_TABLES_VLANTIDX); 157 /* Set the vlan port members mask and issue a write command */ 158 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) | 159 ANA_TABLES_VLANACCESS_CMD_WRITE, 160 ANA_TABLES_VLANACCESS); 161 162 return ocelot_vlant_wait_for_completion(ocelot); 163 } 164 165 static void ocelot_port_set_native_vlan(struct ocelot *ocelot, int port, 166 struct ocelot_vlan native_vlan) 167 { 168 struct ocelot_port *ocelot_port = ocelot->ports[port]; 169 u32 val = 0; 170 171 ocelot_port->native_vlan = native_vlan; 172 173 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_VID(native_vlan.vid), 174 REW_PORT_VLAN_CFG_PORT_VID_M, 175 REW_PORT_VLAN_CFG, port); 176 177 if (ocelot_port->vlan_aware) { 178 if (native_vlan.valid) 179 /* Tag all frames except when VID == DEFAULT_VLAN */ 180 val = REW_TAG_CFG_TAG_CFG(1); 181 else 182 /* Tag all frames */ 183 val = REW_TAG_CFG_TAG_CFG(3); 184 } else { 185 /* Port tagging disabled. */ 186 val = REW_TAG_CFG_TAG_CFG(0); 187 } 188 ocelot_rmw_gix(ocelot, val, 189 REW_TAG_CFG_TAG_CFG_M, 190 REW_TAG_CFG, port); 191 } 192 193 /* Default vlan to clasify for untagged frames (may be zero) */ 194 static void ocelot_port_set_pvid(struct ocelot *ocelot, int port, 195 struct ocelot_vlan pvid_vlan) 196 { 197 struct ocelot_port *ocelot_port = ocelot->ports[port]; 198 u32 val = 0; 199 200 ocelot_port->pvid_vlan = pvid_vlan; 201 202 if (!ocelot_port->vlan_aware) 203 pvid_vlan.vid = 0; 204 205 ocelot_rmw_gix(ocelot, 206 ANA_PORT_VLAN_CFG_VLAN_VID(pvid_vlan.vid), 207 ANA_PORT_VLAN_CFG_VLAN_VID_M, 208 ANA_PORT_VLAN_CFG, port); 209 210 /* If there's no pvid, we should drop not only untagged traffic (which 211 * happens automatically), but also 802.1p traffic which gets 212 * classified to VLAN 0, but that is always in our RX filter, so it 213 * would get accepted were it not for this setting. 214 */ 215 if (!pvid_vlan.valid && ocelot_port->vlan_aware) 216 val = ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 217 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA; 218 219 ocelot_rmw_gix(ocelot, val, 220 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 221 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, 222 ANA_PORT_DROP_CFG, port); 223 } 224 225 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, 226 bool vlan_aware) 227 { 228 struct ocelot_vcap_block *block = &ocelot->block[VCAP_IS1]; 229 struct ocelot_port *ocelot_port = ocelot->ports[port]; 230 struct ocelot_vcap_filter *filter; 231 u32 val; 232 233 list_for_each_entry(filter, &block->rules, list) { 234 if (filter->ingress_port_mask & BIT(port) && 235 filter->action.vid_replace_ena) { 236 dev_err(ocelot->dev, 237 "Cannot change VLAN state with vlan modify rules active\n"); 238 return -EBUSY; 239 } 240 } 241 242 ocelot_port->vlan_aware = vlan_aware; 243 244 if (vlan_aware) 245 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 246 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1); 247 else 248 val = 0; 249 ocelot_rmw_gix(ocelot, val, 250 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 251 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M, 252 ANA_PORT_VLAN_CFG, port); 253 254 ocelot_port_set_pvid(ocelot, port, ocelot_port->pvid_vlan); 255 ocelot_port_set_native_vlan(ocelot, port, ocelot_port->native_vlan); 256 257 return 0; 258 } 259 EXPORT_SYMBOL(ocelot_port_vlan_filtering); 260 261 int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid, 262 bool untagged) 263 { 264 struct ocelot_port *ocelot_port = ocelot->ports[port]; 265 266 /* Deny changing the native VLAN, but always permit deleting it */ 267 if (untagged && ocelot_port->native_vlan.vid != vid && 268 ocelot_port->native_vlan.valid) { 269 dev_err(ocelot->dev, 270 "Port already has a native VLAN: %d\n", 271 ocelot_port->native_vlan.vid); 272 return -EBUSY; 273 } 274 275 return 0; 276 } 277 EXPORT_SYMBOL(ocelot_vlan_prepare); 278 279 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid, 280 bool untagged) 281 { 282 int ret; 283 284 /* Make the port a member of the VLAN */ 285 ocelot->vlan_mask[vid] |= BIT(port); 286 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 287 if (ret) 288 return ret; 289 290 /* Default ingress vlan classification */ 291 if (pvid) { 292 struct ocelot_vlan pvid_vlan; 293 294 pvid_vlan.vid = vid; 295 pvid_vlan.valid = true; 296 ocelot_port_set_pvid(ocelot, port, pvid_vlan); 297 } 298 299 /* Untagged egress vlan clasification */ 300 if (untagged) { 301 struct ocelot_vlan native_vlan; 302 303 native_vlan.vid = vid; 304 native_vlan.valid = true; 305 ocelot_port_set_native_vlan(ocelot, port, native_vlan); 306 } 307 308 return 0; 309 } 310 EXPORT_SYMBOL(ocelot_vlan_add); 311 312 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid) 313 { 314 struct ocelot_port *ocelot_port = ocelot->ports[port]; 315 int ret; 316 317 /* Stop the port from being a member of the vlan */ 318 ocelot->vlan_mask[vid] &= ~BIT(port); 319 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 320 if (ret) 321 return ret; 322 323 /* Ingress */ 324 if (ocelot_port->pvid_vlan.vid == vid) { 325 struct ocelot_vlan pvid_vlan = {0}; 326 327 ocelot_port_set_pvid(ocelot, port, pvid_vlan); 328 } 329 330 /* Egress */ 331 if (ocelot_port->native_vlan.vid == vid) { 332 struct ocelot_vlan native_vlan = {0}; 333 334 ocelot_port_set_native_vlan(ocelot, port, native_vlan); 335 } 336 337 return 0; 338 } 339 EXPORT_SYMBOL(ocelot_vlan_del); 340 341 static void ocelot_vlan_init(struct ocelot *ocelot) 342 { 343 u16 port, vid; 344 345 /* Clear VLAN table, by default all ports are members of all VLANs */ 346 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT, 347 ANA_TABLES_VLANACCESS); 348 ocelot_vlant_wait_for_completion(ocelot); 349 350 /* Configure the port VLAN memberships */ 351 for (vid = 1; vid < VLAN_N_VID; vid++) { 352 ocelot->vlan_mask[vid] = 0; 353 ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 354 } 355 356 /* Because VLAN filtering is enabled, we need VID 0 to get untagged 357 * traffic. It is added automatically if 8021q module is loaded, but 358 * we can't rely on it since module may be not loaded. 359 */ 360 ocelot->vlan_mask[0] = GENMASK(ocelot->num_phys_ports - 1, 0); 361 ocelot_vlant_set_mask(ocelot, 0, ocelot->vlan_mask[0]); 362 363 /* Set vlan ingress filter mask to all ports but the CPU port by 364 * default. 365 */ 366 ocelot_write(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 367 ANA_VLANMASK); 368 369 for (port = 0; port < ocelot->num_phys_ports; port++) { 370 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port); 371 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port); 372 } 373 } 374 375 static u32 ocelot_read_eq_avail(struct ocelot *ocelot, int port) 376 { 377 return ocelot_read_rix(ocelot, QSYS_SW_STATUS, port); 378 } 379 380 static int ocelot_port_flush(struct ocelot *ocelot, int port) 381 { 382 unsigned int pause_ena; 383 int err, val; 384 385 /* Disable dequeuing from the egress queues */ 386 ocelot_rmw_rix(ocelot, QSYS_PORT_MODE_DEQUEUE_DIS, 387 QSYS_PORT_MODE_DEQUEUE_DIS, 388 QSYS_PORT_MODE, port); 389 390 /* Disable flow control */ 391 ocelot_fields_read(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, &pause_ena); 392 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 0); 393 394 /* Disable priority flow control */ 395 ocelot_fields_write(ocelot, port, 396 QSYS_SWITCH_PORT_MODE_TX_PFC_ENA, 0); 397 398 /* Wait at least the time it takes to receive a frame of maximum length 399 * at the port. 400 * Worst-case delays for 10 kilobyte jumbo frames are: 401 * 8 ms on a 10M port 402 * 800 μs on a 100M port 403 * 80 μs on a 1G port 404 * 32 μs on a 2.5G port 405 */ 406 usleep_range(8000, 10000); 407 408 /* Disable half duplex backpressure. */ 409 ocelot_rmw_rix(ocelot, 0, SYS_FRONT_PORT_MODE_HDX_MODE, 410 SYS_FRONT_PORT_MODE, port); 411 412 /* Flush the queues associated with the port. */ 413 ocelot_rmw_gix(ocelot, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG_FLUSH_ENA, 414 REW_PORT_CFG, port); 415 416 /* Enable dequeuing from the egress queues. */ 417 ocelot_rmw_rix(ocelot, 0, QSYS_PORT_MODE_DEQUEUE_DIS, QSYS_PORT_MODE, 418 port); 419 420 /* Wait until flushing is complete. */ 421 err = read_poll_timeout(ocelot_read_eq_avail, val, !val, 422 100, 2000000, false, ocelot, port); 423 424 /* Clear flushing again. */ 425 ocelot_rmw_gix(ocelot, 0, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG, port); 426 427 /* Re-enable flow control */ 428 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, pause_ena); 429 430 return err; 431 } 432 433 void ocelot_phylink_mac_link_down(struct ocelot *ocelot, int port, 434 unsigned int link_an_mode, 435 phy_interface_t interface, 436 unsigned long quirks) 437 { 438 struct ocelot_port *ocelot_port = ocelot->ports[port]; 439 int err; 440 441 ocelot_port_rmwl(ocelot_port, 0, DEV_MAC_ENA_CFG_RX_ENA, 442 DEV_MAC_ENA_CFG); 443 444 ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0); 445 446 err = ocelot_port_flush(ocelot, port); 447 if (err) 448 dev_err(ocelot->dev, "failed to flush port %d: %d\n", 449 port, err); 450 451 /* Put the port in reset. */ 452 if (interface != PHY_INTERFACE_MODE_QSGMII || 453 !(quirks & OCELOT_QUIRK_QSGMII_PORTS_MUST_BE_UP)) 454 ocelot_port_rmwl(ocelot_port, 455 DEV_CLOCK_CFG_MAC_TX_RST | 456 DEV_CLOCK_CFG_MAC_TX_RST, 457 DEV_CLOCK_CFG_MAC_TX_RST | 458 DEV_CLOCK_CFG_MAC_TX_RST, 459 DEV_CLOCK_CFG); 460 } 461 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_down); 462 463 void ocelot_phylink_mac_link_up(struct ocelot *ocelot, int port, 464 struct phy_device *phydev, 465 unsigned int link_an_mode, 466 phy_interface_t interface, 467 int speed, int duplex, 468 bool tx_pause, bool rx_pause, 469 unsigned long quirks) 470 { 471 struct ocelot_port *ocelot_port = ocelot->ports[port]; 472 int mac_speed, mode = 0; 473 u32 mac_fc_cfg; 474 475 /* The MAC might be integrated in systems where the MAC speed is fixed 476 * and it's the PCS who is performing the rate adaptation, so we have 477 * to write "1000Mbps" into the LINK_SPEED field of DEV_CLOCK_CFG 478 * (which is also its default value). 479 */ 480 if ((quirks & OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION) || 481 speed == SPEED_1000) { 482 mac_speed = OCELOT_SPEED_1000; 483 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 484 } else if (speed == SPEED_2500) { 485 mac_speed = OCELOT_SPEED_2500; 486 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 487 } else if (speed == SPEED_100) { 488 mac_speed = OCELOT_SPEED_100; 489 } else { 490 mac_speed = OCELOT_SPEED_10; 491 } 492 493 if (duplex == DUPLEX_FULL) 494 mode |= DEV_MAC_MODE_CFG_FDX_ENA; 495 496 ocelot_port_writel(ocelot_port, mode, DEV_MAC_MODE_CFG); 497 498 /* Take port out of reset by clearing the MAC_TX_RST, MAC_RX_RST and 499 * PORT_RST bits in DEV_CLOCK_CFG. 500 */ 501 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(mac_speed), 502 DEV_CLOCK_CFG); 503 504 switch (speed) { 505 case SPEED_10: 506 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_10); 507 break; 508 case SPEED_100: 509 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_100); 510 break; 511 case SPEED_1000: 512 case SPEED_2500: 513 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_1000); 514 break; 515 default: 516 dev_err(ocelot->dev, "Unsupported speed on port %d: %d\n", 517 port, speed); 518 return; 519 } 520 521 /* Handle RX pause in all cases, with 2500base-X this is used for rate 522 * adaptation. 523 */ 524 mac_fc_cfg |= SYS_MAC_FC_CFG_RX_FC_ENA; 525 526 if (tx_pause) 527 mac_fc_cfg |= SYS_MAC_FC_CFG_TX_FC_ENA | 528 SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) | 529 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) | 530 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA; 531 532 /* Flow control. Link speed is only used here to evaluate the time 533 * specification in incoming pause frames. 534 */ 535 ocelot_write_rix(ocelot, mac_fc_cfg, SYS_MAC_FC_CFG, port); 536 537 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port); 538 539 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, tx_pause); 540 541 /* Undo the effects of ocelot_phylink_mac_link_down: 542 * enable MAC module 543 */ 544 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA | 545 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG); 546 547 /* Take MAC, Port, Phy (intern) and PCS (SGMII/Serdes) clock out of 548 * reset 549 */ 550 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(speed), 551 DEV_CLOCK_CFG); 552 553 /* No PFC */ 554 ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed), 555 ANA_PFC_PFC_CFG, port); 556 557 /* Core: Enable port for frame transfer */ 558 ocelot_fields_write(ocelot, port, 559 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 560 } 561 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_up); 562 563 static void ocelot_port_add_txtstamp_skb(struct ocelot *ocelot, int port, 564 struct sk_buff *clone) 565 { 566 struct ocelot_port *ocelot_port = ocelot->ports[port]; 567 568 spin_lock(&ocelot_port->ts_id_lock); 569 570 skb_shinfo(clone)->tx_flags |= SKBTX_IN_PROGRESS; 571 /* Store timestamp ID in OCELOT_SKB_CB(clone)->ts_id */ 572 OCELOT_SKB_CB(clone)->ts_id = ocelot_port->ts_id; 573 ocelot_port->ts_id = (ocelot_port->ts_id + 1) % 4; 574 skb_queue_tail(&ocelot_port->tx_skbs, clone); 575 576 spin_unlock(&ocelot_port->ts_id_lock); 577 } 578 579 u32 ocelot_ptp_rew_op(struct sk_buff *skb) 580 { 581 struct sk_buff *clone = OCELOT_SKB_CB(skb)->clone; 582 u8 ptp_cmd = OCELOT_SKB_CB(skb)->ptp_cmd; 583 u32 rew_op = 0; 584 585 if (ptp_cmd == IFH_REW_OP_TWO_STEP_PTP && clone) { 586 rew_op = ptp_cmd; 587 rew_op |= OCELOT_SKB_CB(clone)->ts_id << 3; 588 } else if (ptp_cmd == IFH_REW_OP_ORIGIN_PTP) { 589 rew_op = ptp_cmd; 590 } 591 592 return rew_op; 593 } 594 EXPORT_SYMBOL(ocelot_ptp_rew_op); 595 596 static bool ocelot_ptp_is_onestep_sync(struct sk_buff *skb) 597 { 598 struct ptp_header *hdr; 599 unsigned int ptp_class; 600 u8 msgtype, twostep; 601 602 ptp_class = ptp_classify_raw(skb); 603 if (ptp_class == PTP_CLASS_NONE) 604 return false; 605 606 hdr = ptp_parse_header(skb, ptp_class); 607 if (!hdr) 608 return false; 609 610 msgtype = ptp_get_msgtype(hdr, ptp_class); 611 twostep = hdr->flag_field[0] & 0x2; 612 613 if (msgtype == PTP_MSGTYPE_SYNC && twostep == 0) 614 return true; 615 616 return false; 617 } 618 619 int ocelot_port_txtstamp_request(struct ocelot *ocelot, int port, 620 struct sk_buff *skb, 621 struct sk_buff **clone) 622 { 623 struct ocelot_port *ocelot_port = ocelot->ports[port]; 624 u8 ptp_cmd = ocelot_port->ptp_cmd; 625 626 /* Store ptp_cmd in OCELOT_SKB_CB(skb)->ptp_cmd */ 627 if (ptp_cmd == IFH_REW_OP_ORIGIN_PTP) { 628 if (ocelot_ptp_is_onestep_sync(skb)) { 629 OCELOT_SKB_CB(skb)->ptp_cmd = ptp_cmd; 630 return 0; 631 } 632 633 /* Fall back to two-step timestamping */ 634 ptp_cmd = IFH_REW_OP_TWO_STEP_PTP; 635 } 636 637 if (ptp_cmd == IFH_REW_OP_TWO_STEP_PTP) { 638 *clone = skb_clone_sk(skb); 639 if (!(*clone)) 640 return -ENOMEM; 641 642 ocelot_port_add_txtstamp_skb(ocelot, port, *clone); 643 OCELOT_SKB_CB(skb)->ptp_cmd = ptp_cmd; 644 } 645 646 return 0; 647 } 648 EXPORT_SYMBOL(ocelot_port_txtstamp_request); 649 650 static void ocelot_get_hwtimestamp(struct ocelot *ocelot, 651 struct timespec64 *ts) 652 { 653 unsigned long flags; 654 u32 val; 655 656 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); 657 658 /* Read current PTP time to get seconds */ 659 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 660 661 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 662 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE); 663 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 664 ts->tv_sec = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN); 665 666 /* Read packet HW timestamp from FIFO */ 667 val = ocelot_read(ocelot, SYS_PTP_TXSTAMP); 668 ts->tv_nsec = SYS_PTP_TXSTAMP_PTP_TXSTAMP(val); 669 670 /* Sec has incremented since the ts was registered */ 671 if ((ts->tv_sec & 0x1) != !!(val & SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC)) 672 ts->tv_sec--; 673 674 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 675 } 676 677 void ocelot_get_txtstamp(struct ocelot *ocelot) 678 { 679 int budget = OCELOT_PTP_QUEUE_SZ; 680 681 while (budget--) { 682 struct sk_buff *skb, *skb_tmp, *skb_match = NULL; 683 struct skb_shared_hwtstamps shhwtstamps; 684 struct ocelot_port *port; 685 struct timespec64 ts; 686 unsigned long flags; 687 u32 val, id, txport; 688 689 val = ocelot_read(ocelot, SYS_PTP_STATUS); 690 691 /* Check if a timestamp can be retrieved */ 692 if (!(val & SYS_PTP_STATUS_PTP_MESS_VLD)) 693 break; 694 695 WARN_ON(val & SYS_PTP_STATUS_PTP_OVFL); 696 697 /* Retrieve the ts ID and Tx port */ 698 id = SYS_PTP_STATUS_PTP_MESS_ID_X(val); 699 txport = SYS_PTP_STATUS_PTP_MESS_TXPORT_X(val); 700 701 /* Retrieve its associated skb */ 702 port = ocelot->ports[txport]; 703 704 spin_lock_irqsave(&port->tx_skbs.lock, flags); 705 706 skb_queue_walk_safe(&port->tx_skbs, skb, skb_tmp) { 707 if (OCELOT_SKB_CB(skb)->ts_id != id) 708 continue; 709 __skb_unlink(skb, &port->tx_skbs); 710 skb_match = skb; 711 break; 712 } 713 714 spin_unlock_irqrestore(&port->tx_skbs.lock, flags); 715 716 /* Get the h/w timestamp */ 717 ocelot_get_hwtimestamp(ocelot, &ts); 718 719 if (unlikely(!skb_match)) 720 continue; 721 722 /* Set the timestamp into the skb */ 723 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 724 shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec); 725 skb_complete_tx_timestamp(skb_match, &shhwtstamps); 726 727 /* Next ts */ 728 ocelot_write(ocelot, SYS_PTP_NXT_PTP_NXT, SYS_PTP_NXT); 729 } 730 } 731 EXPORT_SYMBOL(ocelot_get_txtstamp); 732 733 static int ocelot_rx_frame_word(struct ocelot *ocelot, u8 grp, bool ifh, 734 u32 *rval) 735 { 736 u32 bytes_valid, val; 737 738 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 739 if (val == XTR_NOT_READY) { 740 if (ifh) 741 return -EIO; 742 743 do { 744 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 745 } while (val == XTR_NOT_READY); 746 } 747 748 switch (val) { 749 case XTR_ABORT: 750 return -EIO; 751 case XTR_EOF_0: 752 case XTR_EOF_1: 753 case XTR_EOF_2: 754 case XTR_EOF_3: 755 case XTR_PRUNED: 756 bytes_valid = XTR_VALID_BYTES(val); 757 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 758 if (val == XTR_ESCAPE) 759 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 760 else 761 *rval = val; 762 763 return bytes_valid; 764 case XTR_ESCAPE: 765 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 766 767 return 4; 768 default: 769 *rval = val; 770 771 return 4; 772 } 773 } 774 775 static int ocelot_xtr_poll_xfh(struct ocelot *ocelot, int grp, u32 *xfh) 776 { 777 int i, err = 0; 778 779 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) { 780 err = ocelot_rx_frame_word(ocelot, grp, true, &xfh[i]); 781 if (err != 4) 782 return (err < 0) ? err : -EIO; 783 } 784 785 return 0; 786 } 787 788 int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **nskb) 789 { 790 struct skb_shared_hwtstamps *shhwtstamps; 791 u64 tod_in_ns, full_ts_in_ns; 792 u64 timestamp, src_port, len; 793 u32 xfh[OCELOT_TAG_LEN / 4]; 794 struct net_device *dev; 795 struct timespec64 ts; 796 struct sk_buff *skb; 797 int sz, buf_len; 798 u32 val, *buf; 799 int err; 800 801 err = ocelot_xtr_poll_xfh(ocelot, grp, xfh); 802 if (err) 803 return err; 804 805 ocelot_xfh_get_src_port(xfh, &src_port); 806 ocelot_xfh_get_len(xfh, &len); 807 ocelot_xfh_get_rew_val(xfh, ×tamp); 808 809 if (WARN_ON(src_port >= ocelot->num_phys_ports)) 810 return -EINVAL; 811 812 dev = ocelot->ops->port_to_netdev(ocelot, src_port); 813 if (!dev) 814 return -EINVAL; 815 816 skb = netdev_alloc_skb(dev, len); 817 if (unlikely(!skb)) { 818 netdev_err(dev, "Unable to allocate sk_buff\n"); 819 return -ENOMEM; 820 } 821 822 buf_len = len - ETH_FCS_LEN; 823 buf = (u32 *)skb_put(skb, buf_len); 824 825 len = 0; 826 do { 827 sz = ocelot_rx_frame_word(ocelot, grp, false, &val); 828 if (sz < 0) { 829 err = sz; 830 goto out_free_skb; 831 } 832 *buf++ = val; 833 len += sz; 834 } while (len < buf_len); 835 836 /* Read the FCS */ 837 sz = ocelot_rx_frame_word(ocelot, grp, false, &val); 838 if (sz < 0) { 839 err = sz; 840 goto out_free_skb; 841 } 842 843 /* Update the statistics if part of the FCS was read before */ 844 len -= ETH_FCS_LEN - sz; 845 846 if (unlikely(dev->features & NETIF_F_RXFCS)) { 847 buf = (u32 *)skb_put(skb, ETH_FCS_LEN); 848 *buf = val; 849 } 850 851 if (ocelot->ptp) { 852 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); 853 854 tod_in_ns = ktime_set(ts.tv_sec, ts.tv_nsec); 855 if ((tod_in_ns & 0xffffffff) < timestamp) 856 full_ts_in_ns = (((tod_in_ns >> 32) - 1) << 32) | 857 timestamp; 858 else 859 full_ts_in_ns = (tod_in_ns & GENMASK_ULL(63, 32)) | 860 timestamp; 861 862 shhwtstamps = skb_hwtstamps(skb); 863 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps)); 864 shhwtstamps->hwtstamp = full_ts_in_ns; 865 } 866 867 /* Everything we see on an interface that is in the HW bridge 868 * has already been forwarded. 869 */ 870 if (ocelot->ports[src_port]->bridge) 871 skb->offload_fwd_mark = 1; 872 873 skb->protocol = eth_type_trans(skb, dev); 874 875 *nskb = skb; 876 877 return 0; 878 879 out_free_skb: 880 kfree_skb(skb); 881 return err; 882 } 883 EXPORT_SYMBOL(ocelot_xtr_poll_frame); 884 885 bool ocelot_can_inject(struct ocelot *ocelot, int grp) 886 { 887 u32 val = ocelot_read(ocelot, QS_INJ_STATUS); 888 889 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp)))) 890 return false; 891 if (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp))) 892 return false; 893 894 return true; 895 } 896 EXPORT_SYMBOL(ocelot_can_inject); 897 898 void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp, 899 u32 rew_op, struct sk_buff *skb) 900 { 901 u32 ifh[OCELOT_TAG_LEN / 4] = {0}; 902 unsigned int i, count, last; 903 904 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 905 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp); 906 907 ocelot_ifh_set_bypass(ifh, 1); 908 ocelot_ifh_set_dest(ifh, BIT_ULL(port)); 909 ocelot_ifh_set_tag_type(ifh, IFH_TAG_TYPE_C); 910 ocelot_ifh_set_vid(ifh, skb_vlan_tag_get(skb)); 911 ocelot_ifh_set_rew_op(ifh, rew_op); 912 913 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) 914 ocelot_write_rix(ocelot, ifh[i], QS_INJ_WR, grp); 915 916 count = DIV_ROUND_UP(skb->len, 4); 917 last = skb->len % 4; 918 for (i = 0; i < count; i++) 919 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp); 920 921 /* Add padding */ 922 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) { 923 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 924 i++; 925 } 926 927 /* Indicate EOF and valid bytes in last word */ 928 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 929 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) | 930 QS_INJ_CTRL_EOF, 931 QS_INJ_CTRL, grp); 932 933 /* Add dummy CRC */ 934 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 935 skb_tx_timestamp(skb); 936 937 skb->dev->stats.tx_packets++; 938 skb->dev->stats.tx_bytes += skb->len; 939 } 940 EXPORT_SYMBOL(ocelot_port_inject_frame); 941 942 void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp) 943 { 944 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)) 945 ocelot_read_rix(ocelot, QS_XTR_RD, grp); 946 } 947 EXPORT_SYMBOL(ocelot_drain_cpu_queue); 948 949 int ocelot_fdb_add(struct ocelot *ocelot, int port, 950 const unsigned char *addr, u16 vid) 951 { 952 int pgid = port; 953 954 if (port == ocelot->npi) 955 pgid = PGID_CPU; 956 957 return ocelot_mact_learn(ocelot, pgid, addr, vid, ENTRYTYPE_LOCKED); 958 } 959 EXPORT_SYMBOL(ocelot_fdb_add); 960 961 int ocelot_fdb_del(struct ocelot *ocelot, int port, 962 const unsigned char *addr, u16 vid) 963 { 964 return ocelot_mact_forget(ocelot, addr, vid); 965 } 966 EXPORT_SYMBOL(ocelot_fdb_del); 967 968 int ocelot_port_fdb_do_dump(const unsigned char *addr, u16 vid, 969 bool is_static, void *data) 970 { 971 struct ocelot_dump_ctx *dump = data; 972 u32 portid = NETLINK_CB(dump->cb->skb).portid; 973 u32 seq = dump->cb->nlh->nlmsg_seq; 974 struct nlmsghdr *nlh; 975 struct ndmsg *ndm; 976 977 if (dump->idx < dump->cb->args[2]) 978 goto skip; 979 980 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH, 981 sizeof(*ndm), NLM_F_MULTI); 982 if (!nlh) 983 return -EMSGSIZE; 984 985 ndm = nlmsg_data(nlh); 986 ndm->ndm_family = AF_BRIDGE; 987 ndm->ndm_pad1 = 0; 988 ndm->ndm_pad2 = 0; 989 ndm->ndm_flags = NTF_SELF; 990 ndm->ndm_type = 0; 991 ndm->ndm_ifindex = dump->dev->ifindex; 992 ndm->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE; 993 994 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, addr)) 995 goto nla_put_failure; 996 997 if (vid && nla_put_u16(dump->skb, NDA_VLAN, vid)) 998 goto nla_put_failure; 999 1000 nlmsg_end(dump->skb, nlh); 1001 1002 skip: 1003 dump->idx++; 1004 return 0; 1005 1006 nla_put_failure: 1007 nlmsg_cancel(dump->skb, nlh); 1008 return -EMSGSIZE; 1009 } 1010 EXPORT_SYMBOL(ocelot_port_fdb_do_dump); 1011 1012 static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col, 1013 struct ocelot_mact_entry *entry) 1014 { 1015 u32 val, dst, macl, mach; 1016 char mac[ETH_ALEN]; 1017 1018 /* Set row and column to read from */ 1019 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row); 1020 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col); 1021 1022 /* Issue a read command */ 1023 ocelot_write(ocelot, 1024 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 1025 ANA_TABLES_MACACCESS); 1026 1027 if (ocelot_mact_wait_for_completion(ocelot)) 1028 return -ETIMEDOUT; 1029 1030 /* Read the entry flags */ 1031 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 1032 if (!(val & ANA_TABLES_MACACCESS_VALID)) 1033 return -EINVAL; 1034 1035 /* If the entry read has another port configured as its destination, 1036 * do not report it. 1037 */ 1038 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3; 1039 if (dst != port) 1040 return -EINVAL; 1041 1042 /* Get the entry's MAC address and VLAN id */ 1043 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA); 1044 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA); 1045 1046 mac[0] = (mach >> 8) & 0xff; 1047 mac[1] = (mach >> 0) & 0xff; 1048 mac[2] = (macl >> 24) & 0xff; 1049 mac[3] = (macl >> 16) & 0xff; 1050 mac[4] = (macl >> 8) & 0xff; 1051 mac[5] = (macl >> 0) & 0xff; 1052 1053 entry->vid = (mach >> 16) & 0xfff; 1054 ether_addr_copy(entry->mac, mac); 1055 1056 return 0; 1057 } 1058 1059 int ocelot_fdb_dump(struct ocelot *ocelot, int port, 1060 dsa_fdb_dump_cb_t *cb, void *data) 1061 { 1062 int i, j; 1063 1064 /* Loop through all the mac tables entries. */ 1065 for (i = 0; i < ocelot->num_mact_rows; i++) { 1066 for (j = 0; j < 4; j++) { 1067 struct ocelot_mact_entry entry; 1068 bool is_static; 1069 int ret; 1070 1071 ret = ocelot_mact_read(ocelot, port, i, j, &entry); 1072 /* If the entry is invalid (wrong port, invalid...), 1073 * skip it. 1074 */ 1075 if (ret == -EINVAL) 1076 continue; 1077 else if (ret) 1078 return ret; 1079 1080 is_static = (entry.type == ENTRYTYPE_LOCKED); 1081 1082 ret = cb(entry.mac, entry.vid, is_static, data); 1083 if (ret) 1084 return ret; 1085 } 1086 } 1087 1088 return 0; 1089 } 1090 EXPORT_SYMBOL(ocelot_fdb_dump); 1091 1092 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr) 1093 { 1094 return copy_to_user(ifr->ifr_data, &ocelot->hwtstamp_config, 1095 sizeof(ocelot->hwtstamp_config)) ? -EFAULT : 0; 1096 } 1097 EXPORT_SYMBOL(ocelot_hwstamp_get); 1098 1099 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr) 1100 { 1101 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1102 struct hwtstamp_config cfg; 1103 1104 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1105 return -EFAULT; 1106 1107 /* reserved for future extensions */ 1108 if (cfg.flags) 1109 return -EINVAL; 1110 1111 /* Tx type sanity check */ 1112 switch (cfg.tx_type) { 1113 case HWTSTAMP_TX_ON: 1114 ocelot_port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP; 1115 break; 1116 case HWTSTAMP_TX_ONESTEP_SYNC: 1117 /* IFH_REW_OP_ONE_STEP_PTP updates the correctional field, we 1118 * need to update the origin time. 1119 */ 1120 ocelot_port->ptp_cmd = IFH_REW_OP_ORIGIN_PTP; 1121 break; 1122 case HWTSTAMP_TX_OFF: 1123 ocelot_port->ptp_cmd = 0; 1124 break; 1125 default: 1126 return -ERANGE; 1127 } 1128 1129 mutex_lock(&ocelot->ptp_lock); 1130 1131 switch (cfg.rx_filter) { 1132 case HWTSTAMP_FILTER_NONE: 1133 break; 1134 case HWTSTAMP_FILTER_ALL: 1135 case HWTSTAMP_FILTER_SOME: 1136 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1137 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1138 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1139 case HWTSTAMP_FILTER_NTP_ALL: 1140 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1141 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1142 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1143 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1144 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1145 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1146 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1147 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1148 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1149 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 1150 break; 1151 default: 1152 mutex_unlock(&ocelot->ptp_lock); 1153 return -ERANGE; 1154 } 1155 1156 /* Commit back the result & save it */ 1157 memcpy(&ocelot->hwtstamp_config, &cfg, sizeof(cfg)); 1158 mutex_unlock(&ocelot->ptp_lock); 1159 1160 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1161 } 1162 EXPORT_SYMBOL(ocelot_hwstamp_set); 1163 1164 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data) 1165 { 1166 int i; 1167 1168 if (sset != ETH_SS_STATS) 1169 return; 1170 1171 for (i = 0; i < ocelot->num_stats; i++) 1172 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name, 1173 ETH_GSTRING_LEN); 1174 } 1175 EXPORT_SYMBOL(ocelot_get_strings); 1176 1177 static void ocelot_update_stats(struct ocelot *ocelot) 1178 { 1179 int i, j; 1180 1181 mutex_lock(&ocelot->stats_lock); 1182 1183 for (i = 0; i < ocelot->num_phys_ports; i++) { 1184 /* Configure the port to read the stats from */ 1185 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(i), SYS_STAT_CFG); 1186 1187 for (j = 0; j < ocelot->num_stats; j++) { 1188 u32 val; 1189 unsigned int idx = i * ocelot->num_stats + j; 1190 1191 val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS, 1192 ocelot->stats_layout[j].offset); 1193 1194 if (val < (ocelot->stats[idx] & U32_MAX)) 1195 ocelot->stats[idx] += (u64)1 << 32; 1196 1197 ocelot->stats[idx] = (ocelot->stats[idx] & 1198 ~(u64)U32_MAX) + val; 1199 } 1200 } 1201 1202 mutex_unlock(&ocelot->stats_lock); 1203 } 1204 1205 static void ocelot_check_stats_work(struct work_struct *work) 1206 { 1207 struct delayed_work *del_work = to_delayed_work(work); 1208 struct ocelot *ocelot = container_of(del_work, struct ocelot, 1209 stats_work); 1210 1211 ocelot_update_stats(ocelot); 1212 1213 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 1214 OCELOT_STATS_CHECK_DELAY); 1215 } 1216 1217 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data) 1218 { 1219 int i; 1220 1221 /* check and update now */ 1222 ocelot_update_stats(ocelot); 1223 1224 /* Copy all counters */ 1225 for (i = 0; i < ocelot->num_stats; i++) 1226 *data++ = ocelot->stats[port * ocelot->num_stats + i]; 1227 } 1228 EXPORT_SYMBOL(ocelot_get_ethtool_stats); 1229 1230 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset) 1231 { 1232 if (sset != ETH_SS_STATS) 1233 return -EOPNOTSUPP; 1234 1235 return ocelot->num_stats; 1236 } 1237 EXPORT_SYMBOL(ocelot_get_sset_count); 1238 1239 int ocelot_get_ts_info(struct ocelot *ocelot, int port, 1240 struct ethtool_ts_info *info) 1241 { 1242 info->phc_index = ocelot->ptp_clock ? 1243 ptp_clock_index(ocelot->ptp_clock) : -1; 1244 if (info->phc_index == -1) { 1245 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 1246 SOF_TIMESTAMPING_RX_SOFTWARE | 1247 SOF_TIMESTAMPING_SOFTWARE; 1248 return 0; 1249 } 1250 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 1251 SOF_TIMESTAMPING_RX_SOFTWARE | 1252 SOF_TIMESTAMPING_SOFTWARE | 1253 SOF_TIMESTAMPING_TX_HARDWARE | 1254 SOF_TIMESTAMPING_RX_HARDWARE | 1255 SOF_TIMESTAMPING_RAW_HARDWARE; 1256 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON) | 1257 BIT(HWTSTAMP_TX_ONESTEP_SYNC); 1258 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL); 1259 1260 return 0; 1261 } 1262 EXPORT_SYMBOL(ocelot_get_ts_info); 1263 1264 static u32 ocelot_get_bond_mask(struct ocelot *ocelot, struct net_device *bond, 1265 bool only_active_ports) 1266 { 1267 u32 mask = 0; 1268 int port; 1269 1270 for (port = 0; port < ocelot->num_phys_ports; port++) { 1271 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1272 1273 if (!ocelot_port) 1274 continue; 1275 1276 if (ocelot_port->bond == bond) { 1277 if (only_active_ports && !ocelot_port->lag_tx_active) 1278 continue; 1279 1280 mask |= BIT(port); 1281 } 1282 } 1283 1284 return mask; 1285 } 1286 1287 static u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot, 1288 struct net_device *bridge) 1289 { 1290 u32 mask = 0; 1291 int port; 1292 1293 for (port = 0; port < ocelot->num_phys_ports; port++) { 1294 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1295 1296 if (!ocelot_port) 1297 continue; 1298 1299 if (ocelot_port->stp_state == BR_STATE_FORWARDING && 1300 ocelot_port->bridge == bridge) 1301 mask |= BIT(port); 1302 } 1303 1304 return mask; 1305 } 1306 1307 static u32 ocelot_get_dsa_8021q_cpu_mask(struct ocelot *ocelot) 1308 { 1309 u32 mask = 0; 1310 int port; 1311 1312 for (port = 0; port < ocelot->num_phys_ports; port++) { 1313 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1314 1315 if (!ocelot_port) 1316 continue; 1317 1318 if (ocelot_port->is_dsa_8021q_cpu) 1319 mask |= BIT(port); 1320 } 1321 1322 return mask; 1323 } 1324 1325 void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot) 1326 { 1327 unsigned long cpu_fwd_mask; 1328 int port; 1329 1330 /* If a DSA tag_8021q CPU exists, it needs to be included in the 1331 * regular forwarding path of the front ports regardless of whether 1332 * those are bridged or standalone. 1333 * If DSA tag_8021q is not used, this returns 0, which is fine because 1334 * the hardware-based CPU port module can be a destination for packets 1335 * even if it isn't part of PGID_SRC. 1336 */ 1337 cpu_fwd_mask = ocelot_get_dsa_8021q_cpu_mask(ocelot); 1338 1339 /* Apply FWD mask. The loop is needed to add/remove the current port as 1340 * a source for the other ports. 1341 */ 1342 for (port = 0; port < ocelot->num_phys_ports; port++) { 1343 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1344 unsigned long mask; 1345 1346 if (!ocelot_port) { 1347 /* Unused ports can't send anywhere */ 1348 mask = 0; 1349 } else if (ocelot_port->is_dsa_8021q_cpu) { 1350 /* The DSA tag_8021q CPU ports need to be able to 1351 * forward packets to all other ports except for 1352 * themselves 1353 */ 1354 mask = GENMASK(ocelot->num_phys_ports - 1, 0); 1355 mask &= ~cpu_fwd_mask; 1356 } else if (ocelot_port->bridge) { 1357 struct net_device *bridge = ocelot_port->bridge; 1358 struct net_device *bond = ocelot_port->bond; 1359 1360 mask = ocelot_get_bridge_fwd_mask(ocelot, bridge); 1361 mask |= cpu_fwd_mask; 1362 mask &= ~BIT(port); 1363 if (bond) { 1364 mask &= ~ocelot_get_bond_mask(ocelot, bond, 1365 false); 1366 } 1367 } else { 1368 /* Standalone ports forward only to DSA tag_8021q CPU 1369 * ports (if those exist), or to the hardware CPU port 1370 * module otherwise. 1371 */ 1372 mask = cpu_fwd_mask; 1373 } 1374 1375 ocelot_write_rix(ocelot, mask, ANA_PGID_PGID, PGID_SRC + port); 1376 } 1377 } 1378 EXPORT_SYMBOL(ocelot_apply_bridge_fwd_mask); 1379 1380 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state) 1381 { 1382 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1383 u32 learn_ena = 0; 1384 1385 ocelot_port->stp_state = state; 1386 1387 if ((state == BR_STATE_LEARNING || state == BR_STATE_FORWARDING) && 1388 ocelot_port->learn_ena) 1389 learn_ena = ANA_PORT_PORT_CFG_LEARN_ENA; 1390 1391 ocelot_rmw_gix(ocelot, learn_ena, ANA_PORT_PORT_CFG_LEARN_ENA, 1392 ANA_PORT_PORT_CFG, port); 1393 1394 ocelot_apply_bridge_fwd_mask(ocelot); 1395 } 1396 EXPORT_SYMBOL(ocelot_bridge_stp_state_set); 1397 1398 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs) 1399 { 1400 unsigned int age_period = ANA_AUTOAGE_AGE_PERIOD(msecs / 2000); 1401 1402 /* Setting AGE_PERIOD to zero effectively disables automatic aging, 1403 * which is clearly not what our intention is. So avoid that. 1404 */ 1405 if (!age_period) 1406 age_period = 1; 1407 1408 ocelot_rmw(ocelot, age_period, ANA_AUTOAGE_AGE_PERIOD_M, ANA_AUTOAGE); 1409 } 1410 EXPORT_SYMBOL(ocelot_set_ageing_time); 1411 1412 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot, 1413 const unsigned char *addr, 1414 u16 vid) 1415 { 1416 struct ocelot_multicast *mc; 1417 1418 list_for_each_entry(mc, &ocelot->multicast, list) { 1419 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid) 1420 return mc; 1421 } 1422 1423 return NULL; 1424 } 1425 1426 static enum macaccess_entry_type ocelot_classify_mdb(const unsigned char *addr) 1427 { 1428 if (addr[0] == 0x01 && addr[1] == 0x00 && addr[2] == 0x5e) 1429 return ENTRYTYPE_MACv4; 1430 if (addr[0] == 0x33 && addr[1] == 0x33) 1431 return ENTRYTYPE_MACv6; 1432 return ENTRYTYPE_LOCKED; 1433 } 1434 1435 static struct ocelot_pgid *ocelot_pgid_alloc(struct ocelot *ocelot, int index, 1436 unsigned long ports) 1437 { 1438 struct ocelot_pgid *pgid; 1439 1440 pgid = kzalloc(sizeof(*pgid), GFP_KERNEL); 1441 if (!pgid) 1442 return ERR_PTR(-ENOMEM); 1443 1444 pgid->ports = ports; 1445 pgid->index = index; 1446 refcount_set(&pgid->refcount, 1); 1447 list_add_tail(&pgid->list, &ocelot->pgids); 1448 1449 return pgid; 1450 } 1451 1452 static void ocelot_pgid_free(struct ocelot *ocelot, struct ocelot_pgid *pgid) 1453 { 1454 if (!refcount_dec_and_test(&pgid->refcount)) 1455 return; 1456 1457 list_del(&pgid->list); 1458 kfree(pgid); 1459 } 1460 1461 static struct ocelot_pgid *ocelot_mdb_get_pgid(struct ocelot *ocelot, 1462 const struct ocelot_multicast *mc) 1463 { 1464 struct ocelot_pgid *pgid; 1465 int index; 1466 1467 /* According to VSC7514 datasheet 3.9.1.5 IPv4 Multicast Entries and 1468 * 3.9.1.6 IPv6 Multicast Entries, "Instead of a lookup in the 1469 * destination mask table (PGID), the destination set is programmed as 1470 * part of the entry MAC address.", and the DEST_IDX is set to 0. 1471 */ 1472 if (mc->entry_type == ENTRYTYPE_MACv4 || 1473 mc->entry_type == ENTRYTYPE_MACv6) 1474 return ocelot_pgid_alloc(ocelot, 0, mc->ports); 1475 1476 list_for_each_entry(pgid, &ocelot->pgids, list) { 1477 /* When searching for a nonreserved multicast PGID, ignore the 1478 * dummy PGID of zero that we have for MACv4/MACv6 entries 1479 */ 1480 if (pgid->index && pgid->ports == mc->ports) { 1481 refcount_inc(&pgid->refcount); 1482 return pgid; 1483 } 1484 } 1485 1486 /* Search for a free index in the nonreserved multicast PGID area */ 1487 for_each_nonreserved_multicast_dest_pgid(ocelot, index) { 1488 bool used = false; 1489 1490 list_for_each_entry(pgid, &ocelot->pgids, list) { 1491 if (pgid->index == index) { 1492 used = true; 1493 break; 1494 } 1495 } 1496 1497 if (!used) 1498 return ocelot_pgid_alloc(ocelot, index, mc->ports); 1499 } 1500 1501 return ERR_PTR(-ENOSPC); 1502 } 1503 1504 static void ocelot_encode_ports_to_mdb(unsigned char *addr, 1505 struct ocelot_multicast *mc) 1506 { 1507 ether_addr_copy(addr, mc->addr); 1508 1509 if (mc->entry_type == ENTRYTYPE_MACv4) { 1510 addr[0] = 0; 1511 addr[1] = mc->ports >> 8; 1512 addr[2] = mc->ports & 0xff; 1513 } else if (mc->entry_type == ENTRYTYPE_MACv6) { 1514 addr[0] = mc->ports >> 8; 1515 addr[1] = mc->ports & 0xff; 1516 } 1517 } 1518 1519 int ocelot_port_mdb_add(struct ocelot *ocelot, int port, 1520 const struct switchdev_obj_port_mdb *mdb) 1521 { 1522 unsigned char addr[ETH_ALEN]; 1523 struct ocelot_multicast *mc; 1524 struct ocelot_pgid *pgid; 1525 u16 vid = mdb->vid; 1526 1527 if (port == ocelot->npi) 1528 port = ocelot->num_phys_ports; 1529 1530 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1531 if (!mc) { 1532 /* New entry */ 1533 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL); 1534 if (!mc) 1535 return -ENOMEM; 1536 1537 mc->entry_type = ocelot_classify_mdb(mdb->addr); 1538 ether_addr_copy(mc->addr, mdb->addr); 1539 mc->vid = vid; 1540 1541 list_add_tail(&mc->list, &ocelot->multicast); 1542 } else { 1543 /* Existing entry. Clean up the current port mask from 1544 * hardware now, because we'll be modifying it. 1545 */ 1546 ocelot_pgid_free(ocelot, mc->pgid); 1547 ocelot_encode_ports_to_mdb(addr, mc); 1548 ocelot_mact_forget(ocelot, addr, vid); 1549 } 1550 1551 mc->ports |= BIT(port); 1552 1553 pgid = ocelot_mdb_get_pgid(ocelot, mc); 1554 if (IS_ERR(pgid)) { 1555 dev_err(ocelot->dev, 1556 "Cannot allocate PGID for mdb %pM vid %d\n", 1557 mc->addr, mc->vid); 1558 devm_kfree(ocelot->dev, mc); 1559 return PTR_ERR(pgid); 1560 } 1561 mc->pgid = pgid; 1562 1563 ocelot_encode_ports_to_mdb(addr, mc); 1564 1565 if (mc->entry_type != ENTRYTYPE_MACv4 && 1566 mc->entry_type != ENTRYTYPE_MACv6) 1567 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 1568 pgid->index); 1569 1570 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 1571 mc->entry_type); 1572 } 1573 EXPORT_SYMBOL(ocelot_port_mdb_add); 1574 1575 int ocelot_port_mdb_del(struct ocelot *ocelot, int port, 1576 const struct switchdev_obj_port_mdb *mdb) 1577 { 1578 unsigned char addr[ETH_ALEN]; 1579 struct ocelot_multicast *mc; 1580 struct ocelot_pgid *pgid; 1581 u16 vid = mdb->vid; 1582 1583 if (port == ocelot->npi) 1584 port = ocelot->num_phys_ports; 1585 1586 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1587 if (!mc) 1588 return -ENOENT; 1589 1590 ocelot_encode_ports_to_mdb(addr, mc); 1591 ocelot_mact_forget(ocelot, addr, vid); 1592 1593 ocelot_pgid_free(ocelot, mc->pgid); 1594 mc->ports &= ~BIT(port); 1595 if (!mc->ports) { 1596 list_del(&mc->list); 1597 devm_kfree(ocelot->dev, mc); 1598 return 0; 1599 } 1600 1601 /* We have a PGID with fewer ports now */ 1602 pgid = ocelot_mdb_get_pgid(ocelot, mc); 1603 if (IS_ERR(pgid)) 1604 return PTR_ERR(pgid); 1605 mc->pgid = pgid; 1606 1607 ocelot_encode_ports_to_mdb(addr, mc); 1608 1609 if (mc->entry_type != ENTRYTYPE_MACv4 && 1610 mc->entry_type != ENTRYTYPE_MACv6) 1611 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 1612 pgid->index); 1613 1614 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 1615 mc->entry_type); 1616 } 1617 EXPORT_SYMBOL(ocelot_port_mdb_del); 1618 1619 void ocelot_port_bridge_join(struct ocelot *ocelot, int port, 1620 struct net_device *bridge) 1621 { 1622 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1623 1624 ocelot_port->bridge = bridge; 1625 1626 ocelot_apply_bridge_fwd_mask(ocelot); 1627 } 1628 EXPORT_SYMBOL(ocelot_port_bridge_join); 1629 1630 void ocelot_port_bridge_leave(struct ocelot *ocelot, int port, 1631 struct net_device *bridge) 1632 { 1633 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1634 struct ocelot_vlan pvid = {0}, native_vlan = {0}; 1635 1636 ocelot_port->bridge = NULL; 1637 1638 ocelot_port_set_pvid(ocelot, port, pvid); 1639 ocelot_port_set_native_vlan(ocelot, port, native_vlan); 1640 ocelot_apply_bridge_fwd_mask(ocelot); 1641 } 1642 EXPORT_SYMBOL(ocelot_port_bridge_leave); 1643 1644 static void ocelot_set_aggr_pgids(struct ocelot *ocelot) 1645 { 1646 unsigned long visited = GENMASK(ocelot->num_phys_ports - 1, 0); 1647 int i, port, lag; 1648 1649 /* Reset destination and aggregation PGIDS */ 1650 for_each_unicast_dest_pgid(ocelot, port) 1651 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 1652 1653 for_each_aggr_pgid(ocelot, i) 1654 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 1655 ANA_PGID_PGID, i); 1656 1657 /* The visited ports bitmask holds the list of ports offloading any 1658 * bonding interface. Initially we mark all these ports as unvisited, 1659 * then every time we visit a port in this bitmask, we know that it is 1660 * the lowest numbered port, i.e. the one whose logical ID == physical 1661 * port ID == LAG ID. So we mark as visited all further ports in the 1662 * bitmask that are offloading the same bonding interface. This way, 1663 * we set up the aggregation PGIDs only once per bonding interface. 1664 */ 1665 for (port = 0; port < ocelot->num_phys_ports; port++) { 1666 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1667 1668 if (!ocelot_port || !ocelot_port->bond) 1669 continue; 1670 1671 visited &= ~BIT(port); 1672 } 1673 1674 /* Now, set PGIDs for each active LAG */ 1675 for (lag = 0; lag < ocelot->num_phys_ports; lag++) { 1676 struct net_device *bond = ocelot->ports[lag]->bond; 1677 int num_active_ports = 0; 1678 unsigned long bond_mask; 1679 u8 aggr_idx[16]; 1680 1681 if (!bond || (visited & BIT(lag))) 1682 continue; 1683 1684 bond_mask = ocelot_get_bond_mask(ocelot, bond, true); 1685 1686 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) { 1687 // Destination mask 1688 ocelot_write_rix(ocelot, bond_mask, 1689 ANA_PGID_PGID, port); 1690 aggr_idx[num_active_ports++] = port; 1691 } 1692 1693 for_each_aggr_pgid(ocelot, i) { 1694 u32 ac; 1695 1696 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i); 1697 ac &= ~bond_mask; 1698 /* Don't do division by zero if there was no active 1699 * port. Just make all aggregation codes zero. 1700 */ 1701 if (num_active_ports) 1702 ac |= BIT(aggr_idx[i % num_active_ports]); 1703 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i); 1704 } 1705 1706 /* Mark all ports in the same LAG as visited to avoid applying 1707 * the same config again. 1708 */ 1709 for (port = lag; port < ocelot->num_phys_ports; port++) { 1710 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1711 1712 if (!ocelot_port) 1713 continue; 1714 1715 if (ocelot_port->bond == bond) 1716 visited |= BIT(port); 1717 } 1718 } 1719 } 1720 1721 /* When offloading a bonding interface, the switch ports configured under the 1722 * same bond must have the same logical port ID, equal to the physical port ID 1723 * of the lowest numbered physical port in that bond. Otherwise, in standalone/ 1724 * bridged mode, each port has a logical port ID equal to its physical port ID. 1725 */ 1726 static void ocelot_setup_logical_port_ids(struct ocelot *ocelot) 1727 { 1728 int port; 1729 1730 for (port = 0; port < ocelot->num_phys_ports; port++) { 1731 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1732 struct net_device *bond; 1733 1734 if (!ocelot_port) 1735 continue; 1736 1737 bond = ocelot_port->bond; 1738 if (bond) { 1739 int lag = __ffs(ocelot_get_bond_mask(ocelot, bond, 1740 false)); 1741 1742 ocelot_rmw_gix(ocelot, 1743 ANA_PORT_PORT_CFG_PORTID_VAL(lag), 1744 ANA_PORT_PORT_CFG_PORTID_VAL_M, 1745 ANA_PORT_PORT_CFG, port); 1746 } else { 1747 ocelot_rmw_gix(ocelot, 1748 ANA_PORT_PORT_CFG_PORTID_VAL(port), 1749 ANA_PORT_PORT_CFG_PORTID_VAL_M, 1750 ANA_PORT_PORT_CFG, port); 1751 } 1752 } 1753 } 1754 1755 int ocelot_port_lag_join(struct ocelot *ocelot, int port, 1756 struct net_device *bond, 1757 struct netdev_lag_upper_info *info) 1758 { 1759 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) 1760 return -EOPNOTSUPP; 1761 1762 ocelot->ports[port]->bond = bond; 1763 1764 ocelot_setup_logical_port_ids(ocelot); 1765 ocelot_apply_bridge_fwd_mask(ocelot); 1766 ocelot_set_aggr_pgids(ocelot); 1767 1768 return 0; 1769 } 1770 EXPORT_SYMBOL(ocelot_port_lag_join); 1771 1772 void ocelot_port_lag_leave(struct ocelot *ocelot, int port, 1773 struct net_device *bond) 1774 { 1775 ocelot->ports[port]->bond = NULL; 1776 1777 ocelot_setup_logical_port_ids(ocelot); 1778 ocelot_apply_bridge_fwd_mask(ocelot); 1779 ocelot_set_aggr_pgids(ocelot); 1780 } 1781 EXPORT_SYMBOL(ocelot_port_lag_leave); 1782 1783 void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active) 1784 { 1785 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1786 1787 ocelot_port->lag_tx_active = lag_tx_active; 1788 1789 /* Rebalance the LAGs */ 1790 ocelot_set_aggr_pgids(ocelot); 1791 } 1792 EXPORT_SYMBOL(ocelot_port_lag_change); 1793 1794 /* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu. 1795 * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG. 1796 * In the special case that it's the NPI port that we're configuring, the 1797 * length of the tag and optional prefix needs to be accounted for privately, 1798 * in order to be able to sustain communication at the requested @sdu. 1799 */ 1800 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu) 1801 { 1802 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1803 int maxlen = sdu + ETH_HLEN + ETH_FCS_LEN; 1804 int pause_start, pause_stop; 1805 int atop, atop_tot; 1806 1807 if (port == ocelot->npi) { 1808 maxlen += OCELOT_TAG_LEN; 1809 1810 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT) 1811 maxlen += OCELOT_SHORT_PREFIX_LEN; 1812 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG) 1813 maxlen += OCELOT_LONG_PREFIX_LEN; 1814 } 1815 1816 ocelot_port_writel(ocelot_port, maxlen, DEV_MAC_MAXLEN_CFG); 1817 1818 /* Set Pause watermark hysteresis */ 1819 pause_start = 6 * maxlen / OCELOT_BUFFER_CELL_SZ; 1820 pause_stop = 4 * maxlen / OCELOT_BUFFER_CELL_SZ; 1821 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_START, 1822 pause_start); 1823 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_STOP, 1824 pause_stop); 1825 1826 /* Tail dropping watermarks */ 1827 atop_tot = (ocelot->packet_buffer_size - 9 * maxlen) / 1828 OCELOT_BUFFER_CELL_SZ; 1829 atop = (9 * maxlen) / OCELOT_BUFFER_CELL_SZ; 1830 ocelot_write_rix(ocelot, ocelot->ops->wm_enc(atop), SYS_ATOP, port); 1831 ocelot_write(ocelot, ocelot->ops->wm_enc(atop_tot), SYS_ATOP_TOT_CFG); 1832 } 1833 EXPORT_SYMBOL(ocelot_port_set_maxlen); 1834 1835 int ocelot_get_max_mtu(struct ocelot *ocelot, int port) 1836 { 1837 int max_mtu = 65535 - ETH_HLEN - ETH_FCS_LEN; 1838 1839 if (port == ocelot->npi) { 1840 max_mtu -= OCELOT_TAG_LEN; 1841 1842 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT) 1843 max_mtu -= OCELOT_SHORT_PREFIX_LEN; 1844 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG) 1845 max_mtu -= OCELOT_LONG_PREFIX_LEN; 1846 } 1847 1848 return max_mtu; 1849 } 1850 EXPORT_SYMBOL(ocelot_get_max_mtu); 1851 1852 static void ocelot_port_set_learning(struct ocelot *ocelot, int port, 1853 bool enabled) 1854 { 1855 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1856 u32 val = 0; 1857 1858 if (enabled) 1859 val = ANA_PORT_PORT_CFG_LEARN_ENA; 1860 1861 ocelot_rmw_gix(ocelot, val, ANA_PORT_PORT_CFG_LEARN_ENA, 1862 ANA_PORT_PORT_CFG, port); 1863 1864 ocelot_port->learn_ena = enabled; 1865 } 1866 1867 static void ocelot_port_set_ucast_flood(struct ocelot *ocelot, int port, 1868 bool enabled) 1869 { 1870 u32 val = 0; 1871 1872 if (enabled) 1873 val = BIT(port); 1874 1875 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_UC); 1876 } 1877 1878 static void ocelot_port_set_mcast_flood(struct ocelot *ocelot, int port, 1879 bool enabled) 1880 { 1881 u32 val = 0; 1882 1883 if (enabled) 1884 val = BIT(port); 1885 1886 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MC); 1887 } 1888 1889 static void ocelot_port_set_bcast_flood(struct ocelot *ocelot, int port, 1890 bool enabled) 1891 { 1892 u32 val = 0; 1893 1894 if (enabled) 1895 val = BIT(port); 1896 1897 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_BC); 1898 } 1899 1900 int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port, 1901 struct switchdev_brport_flags flags) 1902 { 1903 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 1904 BR_BCAST_FLOOD)) 1905 return -EINVAL; 1906 1907 return 0; 1908 } 1909 EXPORT_SYMBOL(ocelot_port_pre_bridge_flags); 1910 1911 void ocelot_port_bridge_flags(struct ocelot *ocelot, int port, 1912 struct switchdev_brport_flags flags) 1913 { 1914 if (flags.mask & BR_LEARNING) 1915 ocelot_port_set_learning(ocelot, port, 1916 !!(flags.val & BR_LEARNING)); 1917 1918 if (flags.mask & BR_FLOOD) 1919 ocelot_port_set_ucast_flood(ocelot, port, 1920 !!(flags.val & BR_FLOOD)); 1921 1922 if (flags.mask & BR_MCAST_FLOOD) 1923 ocelot_port_set_mcast_flood(ocelot, port, 1924 !!(flags.val & BR_MCAST_FLOOD)); 1925 1926 if (flags.mask & BR_BCAST_FLOOD) 1927 ocelot_port_set_bcast_flood(ocelot, port, 1928 !!(flags.val & BR_BCAST_FLOOD)); 1929 } 1930 EXPORT_SYMBOL(ocelot_port_bridge_flags); 1931 1932 void ocelot_init_port(struct ocelot *ocelot, int port) 1933 { 1934 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1935 1936 skb_queue_head_init(&ocelot_port->tx_skbs); 1937 spin_lock_init(&ocelot_port->ts_id_lock); 1938 1939 /* Basic L2 initialization */ 1940 1941 /* Set MAC IFG Gaps 1942 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0 1943 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5 1944 */ 1945 ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5), 1946 DEV_MAC_IFG_CFG); 1947 1948 /* Load seed (0) and set MAC HDX late collision */ 1949 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) | 1950 DEV_MAC_HDX_CFG_SEED_LOAD, 1951 DEV_MAC_HDX_CFG); 1952 mdelay(1); 1953 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67), 1954 DEV_MAC_HDX_CFG); 1955 1956 /* Set Max Length and maximum tags allowed */ 1957 ocelot_port_set_maxlen(ocelot, port, ETH_DATA_LEN); 1958 ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) | 1959 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA | 1960 DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA | 1961 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, 1962 DEV_MAC_TAGS_CFG); 1963 1964 /* Set SMAC of Pause frame (00:00:00:00:00:00) */ 1965 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG); 1966 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG); 1967 1968 /* Enable transmission of pause frames */ 1969 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1); 1970 1971 /* Drop frames with multicast source address */ 1972 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 1973 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 1974 ANA_PORT_DROP_CFG, port); 1975 1976 /* Set default VLAN and tag type to 8021Q. */ 1977 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q), 1978 REW_PORT_VLAN_CFG_PORT_TPID_M, 1979 REW_PORT_VLAN_CFG, port); 1980 1981 /* Disable source address learning for standalone mode */ 1982 ocelot_port_set_learning(ocelot, port, false); 1983 1984 /* Set the port's initial logical port ID value, enable receiving 1985 * frames on it, and configure the MAC address learning type to 1986 * automatic. 1987 */ 1988 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO | 1989 ANA_PORT_PORT_CFG_RECV_ENA | 1990 ANA_PORT_PORT_CFG_PORTID_VAL(port), 1991 ANA_PORT_PORT_CFG, port); 1992 1993 /* Enable vcap lookups */ 1994 ocelot_vcap_enable(ocelot, port); 1995 } 1996 EXPORT_SYMBOL(ocelot_init_port); 1997 1998 /* Configure and enable the CPU port module, which is a set of queues 1999 * accessible through register MMIO, frame DMA or Ethernet (in case 2000 * NPI mode is used). 2001 */ 2002 static void ocelot_cpu_port_init(struct ocelot *ocelot) 2003 { 2004 int cpu = ocelot->num_phys_ports; 2005 2006 /* The unicast destination PGID for the CPU port module is unused */ 2007 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu); 2008 /* Instead set up a multicast destination PGID for traffic copied to 2009 * the CPU. Whitelisted MAC addresses like the port netdevice MAC 2010 * addresses will be copied to the CPU via this PGID. 2011 */ 2012 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU); 2013 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA | 2014 ANA_PORT_PORT_CFG_PORTID_VAL(cpu), 2015 ANA_PORT_PORT_CFG, cpu); 2016 2017 /* Enable CPU port module */ 2018 ocelot_fields_write(ocelot, cpu, QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 2019 /* CPU port Injection/Extraction configuration */ 2020 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_XTR_HDR, 2021 OCELOT_TAG_PREFIX_NONE); 2022 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_INJ_HDR, 2023 OCELOT_TAG_PREFIX_NONE); 2024 2025 /* Configure the CPU port to be VLAN aware */ 2026 ocelot_write_gix(ocelot, ANA_PORT_VLAN_CFG_VLAN_VID(0) | 2027 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 2028 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1), 2029 ANA_PORT_VLAN_CFG, cpu); 2030 } 2031 2032 static void ocelot_detect_features(struct ocelot *ocelot) 2033 { 2034 int mmgt, eq_ctrl; 2035 2036 /* For Ocelot, Felix, Seville, Serval etc, SYS:MMGT:MMGT:FREECNT holds 2037 * the number of 240-byte free memory words (aka 4-cell chunks) and not 2038 * 192 bytes as the documentation incorrectly says. 2039 */ 2040 mmgt = ocelot_read(ocelot, SYS_MMGT); 2041 ocelot->packet_buffer_size = 240 * SYS_MMGT_FREECNT(mmgt); 2042 2043 eq_ctrl = ocelot_read(ocelot, QSYS_EQ_CTRL); 2044 ocelot->num_frame_refs = QSYS_MMGT_EQ_CTRL_FP_FREE_CNT(eq_ctrl); 2045 } 2046 2047 int ocelot_init(struct ocelot *ocelot) 2048 { 2049 char queue_name[32]; 2050 int i, ret; 2051 u32 port; 2052 2053 if (ocelot->ops->reset) { 2054 ret = ocelot->ops->reset(ocelot); 2055 if (ret) { 2056 dev_err(ocelot->dev, "Switch reset failed\n"); 2057 return ret; 2058 } 2059 } 2060 2061 ocelot->stats = devm_kcalloc(ocelot->dev, 2062 ocelot->num_phys_ports * ocelot->num_stats, 2063 sizeof(u64), GFP_KERNEL); 2064 if (!ocelot->stats) 2065 return -ENOMEM; 2066 2067 mutex_init(&ocelot->stats_lock); 2068 mutex_init(&ocelot->ptp_lock); 2069 spin_lock_init(&ocelot->ptp_clock_lock); 2070 snprintf(queue_name, sizeof(queue_name), "%s-stats", 2071 dev_name(ocelot->dev)); 2072 ocelot->stats_queue = create_singlethread_workqueue(queue_name); 2073 if (!ocelot->stats_queue) 2074 return -ENOMEM; 2075 2076 ocelot->owq = alloc_ordered_workqueue("ocelot-owq", 0); 2077 if (!ocelot->owq) { 2078 destroy_workqueue(ocelot->stats_queue); 2079 return -ENOMEM; 2080 } 2081 2082 INIT_LIST_HEAD(&ocelot->multicast); 2083 INIT_LIST_HEAD(&ocelot->pgids); 2084 ocelot_detect_features(ocelot); 2085 ocelot_mact_init(ocelot); 2086 ocelot_vlan_init(ocelot); 2087 ocelot_vcap_init(ocelot); 2088 ocelot_cpu_port_init(ocelot); 2089 2090 for (port = 0; port < ocelot->num_phys_ports; port++) { 2091 /* Clear all counters (5 groups) */ 2092 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) | 2093 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f), 2094 SYS_STAT_CFG); 2095 } 2096 2097 /* Only use S-Tag */ 2098 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG); 2099 2100 /* Aggregation mode */ 2101 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA | 2102 ANA_AGGR_CFG_AC_DMAC_ENA | 2103 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA | 2104 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA | 2105 ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA | 2106 ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA, 2107 ANA_AGGR_CFG); 2108 2109 /* Set MAC age time to default value. The entry is aged after 2110 * 2*AGE_PERIOD 2111 */ 2112 ocelot_write(ocelot, 2113 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ), 2114 ANA_AUTOAGE); 2115 2116 /* Disable learning for frames discarded by VLAN ingress filtering */ 2117 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1); 2118 2119 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */ 2120 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA | 2121 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING); 2122 2123 /* Setup flooding PGIDs */ 2124 for (i = 0; i < ocelot->num_flooding_pgids; i++) 2125 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) | 2126 ANA_FLOODING_FLD_BROADCAST(PGID_BC) | 2127 ANA_FLOODING_FLD_UNICAST(PGID_UC), 2128 ANA_FLOODING, i); 2129 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) | 2130 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) | 2131 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) | 2132 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC), 2133 ANA_FLOODING_IPMC); 2134 2135 for (port = 0; port < ocelot->num_phys_ports; port++) { 2136 /* Transmit the frame to the local port. */ 2137 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 2138 /* Do not forward BPDU frames to the front ports. */ 2139 ocelot_write_gix(ocelot, 2140 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff), 2141 ANA_PORT_CPU_FWD_BPDU_CFG, 2142 port); 2143 /* Ensure bridging is disabled */ 2144 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port); 2145 } 2146 2147 for_each_nonreserved_multicast_dest_pgid(ocelot, i) { 2148 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0)); 2149 2150 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 2151 } 2152 2153 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_BLACKHOLE); 2154 2155 /* Allow broadcast and unknown L2 multicast to the CPU. */ 2156 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2157 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2158 ANA_PGID_PGID, PGID_MC); 2159 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2160 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2161 ANA_PGID_PGID, PGID_BC); 2162 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4); 2163 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6); 2164 2165 /* Allow manual injection via DEVCPU_QS registers, and byte swap these 2166 * registers endianness. 2167 */ 2168 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP | 2169 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0); 2170 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP | 2171 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0); 2172 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) | 2173 ANA_CPUQ_CFG_CPUQ_LRN(2) | 2174 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) | 2175 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) | 2176 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) | 2177 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) | 2178 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) | 2179 ANA_CPUQ_CFG_CPUQ_IGMP(6) | 2180 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG); 2181 for (i = 0; i < 16; i++) 2182 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) | 2183 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6), 2184 ANA_CPUQ_8021_CFG, i); 2185 2186 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats_work); 2187 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 2188 OCELOT_STATS_CHECK_DELAY); 2189 2190 return 0; 2191 } 2192 EXPORT_SYMBOL(ocelot_init); 2193 2194 void ocelot_deinit(struct ocelot *ocelot) 2195 { 2196 cancel_delayed_work(&ocelot->stats_work); 2197 destroy_workqueue(ocelot->stats_queue); 2198 destroy_workqueue(ocelot->owq); 2199 mutex_destroy(&ocelot->stats_lock); 2200 } 2201 EXPORT_SYMBOL(ocelot_deinit); 2202 2203 void ocelot_deinit_port(struct ocelot *ocelot, int port) 2204 { 2205 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2206 2207 skb_queue_purge(&ocelot_port->tx_skbs); 2208 } 2209 EXPORT_SYMBOL(ocelot_deinit_port); 2210 2211 MODULE_LICENSE("Dual MIT/GPL"); 2212