1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7 #include <linux/dsa/ocelot.h> 8 #include <linux/if_bridge.h> 9 #include <soc/mscc/ocelot_vcap.h> 10 #include "ocelot.h" 11 #include "ocelot_vcap.h" 12 13 #define TABLE_UPDATE_SLEEP_US 10 14 #define TABLE_UPDATE_TIMEOUT_US 100000 15 #define OCELOT_RSV_VLAN_RANGE_START 4000 16 17 struct ocelot_mact_entry { 18 u8 mac[ETH_ALEN]; 19 u16 vid; 20 enum macaccess_entry_type type; 21 }; 22 23 /* Caller must hold &ocelot->mact_lock */ 24 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot) 25 { 26 return ocelot_read(ocelot, ANA_TABLES_MACACCESS); 27 } 28 29 /* Caller must hold &ocelot->mact_lock */ 30 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot) 31 { 32 u32 val; 33 34 return readx_poll_timeout(ocelot_mact_read_macaccess, 35 ocelot, val, 36 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) == 37 MACACCESS_CMD_IDLE, 38 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 39 } 40 41 /* Caller must hold &ocelot->mact_lock */ 42 static void ocelot_mact_select(struct ocelot *ocelot, 43 const unsigned char mac[ETH_ALEN], 44 unsigned int vid) 45 { 46 u32 macl = 0, mach = 0; 47 48 /* Set the MAC address to handle and the vlan associated in a format 49 * understood by the hardware. 50 */ 51 mach |= vid << 16; 52 mach |= mac[0] << 8; 53 mach |= mac[1] << 0; 54 macl |= mac[2] << 24; 55 macl |= mac[3] << 16; 56 macl |= mac[4] << 8; 57 macl |= mac[5] << 0; 58 59 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA); 60 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA); 61 62 } 63 64 static int __ocelot_mact_learn(struct ocelot *ocelot, int port, 65 const unsigned char mac[ETH_ALEN], 66 unsigned int vid, enum macaccess_entry_type type) 67 { 68 u32 cmd = ANA_TABLES_MACACCESS_VALID | 69 ANA_TABLES_MACACCESS_DEST_IDX(port) | 70 ANA_TABLES_MACACCESS_ENTRYTYPE(type) | 71 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN); 72 unsigned int mc_ports; 73 int err; 74 75 /* Set MAC_CPU_COPY if the CPU port is used by a multicast entry */ 76 if (type == ENTRYTYPE_MACv4) 77 mc_ports = (mac[1] << 8) | mac[2]; 78 else if (type == ENTRYTYPE_MACv6) 79 mc_ports = (mac[0] << 8) | mac[1]; 80 else 81 mc_ports = 0; 82 83 if (mc_ports & BIT(ocelot->num_phys_ports)) 84 cmd |= ANA_TABLES_MACACCESS_MAC_CPU_COPY; 85 86 ocelot_mact_select(ocelot, mac, vid); 87 88 /* Issue a write command */ 89 ocelot_write(ocelot, cmd, ANA_TABLES_MACACCESS); 90 91 err = ocelot_mact_wait_for_completion(ocelot); 92 93 return err; 94 } 95 96 int ocelot_mact_learn(struct ocelot *ocelot, int port, 97 const unsigned char mac[ETH_ALEN], 98 unsigned int vid, enum macaccess_entry_type type) 99 { 100 int ret; 101 102 mutex_lock(&ocelot->mact_lock); 103 ret = __ocelot_mact_learn(ocelot, port, mac, vid, type); 104 mutex_unlock(&ocelot->mact_lock); 105 106 return ret; 107 } 108 EXPORT_SYMBOL(ocelot_mact_learn); 109 110 int ocelot_mact_forget(struct ocelot *ocelot, 111 const unsigned char mac[ETH_ALEN], unsigned int vid) 112 { 113 int err; 114 115 mutex_lock(&ocelot->mact_lock); 116 117 ocelot_mact_select(ocelot, mac, vid); 118 119 /* Issue a forget command */ 120 ocelot_write(ocelot, 121 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET), 122 ANA_TABLES_MACACCESS); 123 124 err = ocelot_mact_wait_for_completion(ocelot); 125 126 mutex_unlock(&ocelot->mact_lock); 127 128 return err; 129 } 130 EXPORT_SYMBOL(ocelot_mact_forget); 131 132 int ocelot_mact_lookup(struct ocelot *ocelot, int *dst_idx, 133 const unsigned char mac[ETH_ALEN], 134 unsigned int vid, enum macaccess_entry_type *type) 135 { 136 int val; 137 138 mutex_lock(&ocelot->mact_lock); 139 140 ocelot_mact_select(ocelot, mac, vid); 141 142 /* Issue a read command with MACACCESS_VALID=1. */ 143 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID | 144 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 145 ANA_TABLES_MACACCESS); 146 147 if (ocelot_mact_wait_for_completion(ocelot)) { 148 mutex_unlock(&ocelot->mact_lock); 149 return -ETIMEDOUT; 150 } 151 152 /* Read back the entry flags */ 153 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 154 155 mutex_unlock(&ocelot->mact_lock); 156 157 if (!(val & ANA_TABLES_MACACCESS_VALID)) 158 return -ENOENT; 159 160 *dst_idx = ANA_TABLES_MACACCESS_DEST_IDX_X(val); 161 *type = ANA_TABLES_MACACCESS_ENTRYTYPE_X(val); 162 163 return 0; 164 } 165 EXPORT_SYMBOL(ocelot_mact_lookup); 166 167 int ocelot_mact_learn_streamdata(struct ocelot *ocelot, int dst_idx, 168 const unsigned char mac[ETH_ALEN], 169 unsigned int vid, 170 enum macaccess_entry_type type, 171 int sfid, int ssid) 172 { 173 int ret; 174 175 mutex_lock(&ocelot->mact_lock); 176 177 ocelot_write(ocelot, 178 (sfid < 0 ? 0 : ANA_TABLES_STREAMDATA_SFID_VALID) | 179 ANA_TABLES_STREAMDATA_SFID(sfid) | 180 (ssid < 0 ? 0 : ANA_TABLES_STREAMDATA_SSID_VALID) | 181 ANA_TABLES_STREAMDATA_SSID(ssid), 182 ANA_TABLES_STREAMDATA); 183 184 ret = __ocelot_mact_learn(ocelot, dst_idx, mac, vid, type); 185 186 mutex_unlock(&ocelot->mact_lock); 187 188 return ret; 189 } 190 EXPORT_SYMBOL(ocelot_mact_learn_streamdata); 191 192 static void ocelot_mact_init(struct ocelot *ocelot) 193 { 194 /* Configure the learning mode entries attributes: 195 * - Do not copy the frame to the CPU extraction queues. 196 * - Use the vlan and mac_cpoy for dmac lookup. 197 */ 198 ocelot_rmw(ocelot, 0, 199 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS 200 | ANA_AGENCTRL_LEARN_FWD_KILL 201 | ANA_AGENCTRL_LEARN_IGNORE_VLAN, 202 ANA_AGENCTRL); 203 204 /* Clear the MAC table. We are not concurrent with anyone, so 205 * holding &ocelot->mact_lock is pointless. 206 */ 207 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS); 208 } 209 210 static void ocelot_vcap_enable(struct ocelot *ocelot, int port) 211 { 212 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA | 213 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa), 214 ANA_PORT_VCAP_S2_CFG, port); 215 216 ocelot_write_gix(ocelot, ANA_PORT_VCAP_CFG_S1_ENA, 217 ANA_PORT_VCAP_CFG, port); 218 219 ocelot_rmw_gix(ocelot, REW_PORT_CFG_ES0_EN, 220 REW_PORT_CFG_ES0_EN, 221 REW_PORT_CFG, port); 222 } 223 224 static int ocelot_single_vlan_aware_bridge(struct ocelot *ocelot, 225 struct netlink_ext_ack *extack) 226 { 227 struct net_device *bridge = NULL; 228 int port; 229 230 for (port = 0; port < ocelot->num_phys_ports; port++) { 231 struct ocelot_port *ocelot_port = ocelot->ports[port]; 232 233 if (!ocelot_port || !ocelot_port->bridge || 234 !br_vlan_enabled(ocelot_port->bridge)) 235 continue; 236 237 if (!bridge) { 238 bridge = ocelot_port->bridge; 239 continue; 240 } 241 242 if (bridge == ocelot_port->bridge) 243 continue; 244 245 NL_SET_ERR_MSG_MOD(extack, 246 "Only one VLAN-aware bridge is supported"); 247 return -EBUSY; 248 } 249 250 return 0; 251 } 252 253 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot) 254 { 255 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS); 256 } 257 258 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot) 259 { 260 u32 val; 261 262 return readx_poll_timeout(ocelot_vlant_read_vlanaccess, 263 ocelot, 264 val, 265 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) == 266 ANA_TABLES_VLANACCESS_CMD_IDLE, 267 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 268 } 269 270 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask) 271 { 272 /* Select the VID to configure */ 273 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid), 274 ANA_TABLES_VLANTIDX); 275 /* Set the vlan port members mask and issue a write command */ 276 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) | 277 ANA_TABLES_VLANACCESS_CMD_WRITE, 278 ANA_TABLES_VLANACCESS); 279 280 return ocelot_vlant_wait_for_completion(ocelot); 281 } 282 283 static int ocelot_port_num_untagged_vlans(struct ocelot *ocelot, int port) 284 { 285 struct ocelot_bridge_vlan *vlan; 286 int num_untagged = 0; 287 288 list_for_each_entry(vlan, &ocelot->vlans, list) { 289 if (!(vlan->portmask & BIT(port))) 290 continue; 291 292 if (vlan->untagged & BIT(port)) 293 num_untagged++; 294 } 295 296 return num_untagged; 297 } 298 299 static int ocelot_port_num_tagged_vlans(struct ocelot *ocelot, int port) 300 { 301 struct ocelot_bridge_vlan *vlan; 302 int num_tagged = 0; 303 304 list_for_each_entry(vlan, &ocelot->vlans, list) { 305 if (!(vlan->portmask & BIT(port))) 306 continue; 307 308 if (!(vlan->untagged & BIT(port))) 309 num_tagged++; 310 } 311 312 return num_tagged; 313 } 314 315 /* We use native VLAN when we have to mix egress-tagged VLANs with exactly 316 * _one_ egress-untagged VLAN (_the_ native VLAN) 317 */ 318 static bool ocelot_port_uses_native_vlan(struct ocelot *ocelot, int port) 319 { 320 return ocelot_port_num_tagged_vlans(ocelot, port) && 321 ocelot_port_num_untagged_vlans(ocelot, port) == 1; 322 } 323 324 static struct ocelot_bridge_vlan * 325 ocelot_port_find_native_vlan(struct ocelot *ocelot, int port) 326 { 327 struct ocelot_bridge_vlan *vlan; 328 329 list_for_each_entry(vlan, &ocelot->vlans, list) 330 if (vlan->portmask & BIT(port) && vlan->untagged & BIT(port)) 331 return vlan; 332 333 return NULL; 334 } 335 336 /* Keep in sync REW_TAG_CFG_TAG_CFG and, if applicable, 337 * REW_PORT_VLAN_CFG_PORT_VID, with the bridge VLAN table and VLAN awareness 338 * state of the port. 339 */ 340 static void ocelot_port_manage_port_tag(struct ocelot *ocelot, int port) 341 { 342 struct ocelot_port *ocelot_port = ocelot->ports[port]; 343 enum ocelot_port_tag_config tag_cfg; 344 bool uses_native_vlan = false; 345 346 if (ocelot_port->vlan_aware) { 347 uses_native_vlan = ocelot_port_uses_native_vlan(ocelot, port); 348 349 if (uses_native_vlan) 350 tag_cfg = OCELOT_PORT_TAG_NATIVE; 351 else if (ocelot_port_num_untagged_vlans(ocelot, port)) 352 tag_cfg = OCELOT_PORT_TAG_DISABLED; 353 else 354 tag_cfg = OCELOT_PORT_TAG_TRUNK; 355 } else { 356 tag_cfg = OCELOT_PORT_TAG_DISABLED; 357 } 358 359 ocelot_rmw_gix(ocelot, REW_TAG_CFG_TAG_CFG(tag_cfg), 360 REW_TAG_CFG_TAG_CFG_M, 361 REW_TAG_CFG, port); 362 363 if (uses_native_vlan) { 364 struct ocelot_bridge_vlan *native_vlan; 365 366 /* Not having a native VLAN is impossible, because 367 * ocelot_port_num_untagged_vlans has returned 1. 368 * So there is no use in checking for NULL here. 369 */ 370 native_vlan = ocelot_port_find_native_vlan(ocelot, port); 371 372 ocelot_rmw_gix(ocelot, 373 REW_PORT_VLAN_CFG_PORT_VID(native_vlan->vid), 374 REW_PORT_VLAN_CFG_PORT_VID_M, 375 REW_PORT_VLAN_CFG, port); 376 } 377 } 378 379 int ocelot_bridge_num_find(struct ocelot *ocelot, 380 const struct net_device *bridge) 381 { 382 int port; 383 384 for (port = 0; port < ocelot->num_phys_ports; port++) { 385 struct ocelot_port *ocelot_port = ocelot->ports[port]; 386 387 if (ocelot_port && ocelot_port->bridge == bridge) 388 return ocelot_port->bridge_num; 389 } 390 391 return -1; 392 } 393 EXPORT_SYMBOL_GPL(ocelot_bridge_num_find); 394 395 static u16 ocelot_vlan_unaware_pvid(struct ocelot *ocelot, 396 const struct net_device *bridge) 397 { 398 int bridge_num; 399 400 /* Standalone ports use VID 0 */ 401 if (!bridge) 402 return 0; 403 404 bridge_num = ocelot_bridge_num_find(ocelot, bridge); 405 if (WARN_ON(bridge_num < 0)) 406 return 0; 407 408 /* VLAN-unaware bridges use a reserved VID going from 4095 downwards */ 409 return VLAN_N_VID - bridge_num - 1; 410 } 411 412 /* Default vlan to clasify for untagged frames (may be zero) */ 413 static void ocelot_port_set_pvid(struct ocelot *ocelot, int port, 414 const struct ocelot_bridge_vlan *pvid_vlan) 415 { 416 struct ocelot_port *ocelot_port = ocelot->ports[port]; 417 u16 pvid = ocelot_vlan_unaware_pvid(ocelot, ocelot_port->bridge); 418 u32 val = 0; 419 420 ocelot_port->pvid_vlan = pvid_vlan; 421 422 if (ocelot_port->vlan_aware && pvid_vlan) 423 pvid = pvid_vlan->vid; 424 425 ocelot_rmw_gix(ocelot, 426 ANA_PORT_VLAN_CFG_VLAN_VID(pvid), 427 ANA_PORT_VLAN_CFG_VLAN_VID_M, 428 ANA_PORT_VLAN_CFG, port); 429 430 /* If there's no pvid, we should drop not only untagged traffic (which 431 * happens automatically), but also 802.1p traffic which gets 432 * classified to VLAN 0, but that is always in our RX filter, so it 433 * would get accepted were it not for this setting. 434 */ 435 if (!pvid_vlan && ocelot_port->vlan_aware) 436 val = ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 437 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA; 438 439 ocelot_rmw_gix(ocelot, val, 440 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 441 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, 442 ANA_PORT_DROP_CFG, port); 443 } 444 445 static struct ocelot_bridge_vlan *ocelot_bridge_vlan_find(struct ocelot *ocelot, 446 u16 vid) 447 { 448 struct ocelot_bridge_vlan *vlan; 449 450 list_for_each_entry(vlan, &ocelot->vlans, list) 451 if (vlan->vid == vid) 452 return vlan; 453 454 return NULL; 455 } 456 457 static int ocelot_vlan_member_add(struct ocelot *ocelot, int port, u16 vid, 458 bool untagged) 459 { 460 struct ocelot_bridge_vlan *vlan = ocelot_bridge_vlan_find(ocelot, vid); 461 unsigned long portmask; 462 int err; 463 464 if (vlan) { 465 portmask = vlan->portmask | BIT(port); 466 467 err = ocelot_vlant_set_mask(ocelot, vid, portmask); 468 if (err) 469 return err; 470 471 vlan->portmask = portmask; 472 /* Bridge VLANs can be overwritten with a different 473 * egress-tagging setting, so make sure to override an untagged 474 * with a tagged VID if that's going on. 475 */ 476 if (untagged) 477 vlan->untagged |= BIT(port); 478 else 479 vlan->untagged &= ~BIT(port); 480 481 return 0; 482 } 483 484 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL); 485 if (!vlan) 486 return -ENOMEM; 487 488 portmask = BIT(port); 489 490 err = ocelot_vlant_set_mask(ocelot, vid, portmask); 491 if (err) { 492 kfree(vlan); 493 return err; 494 } 495 496 vlan->vid = vid; 497 vlan->portmask = portmask; 498 if (untagged) 499 vlan->untagged = BIT(port); 500 INIT_LIST_HEAD(&vlan->list); 501 list_add_tail(&vlan->list, &ocelot->vlans); 502 503 return 0; 504 } 505 506 static int ocelot_vlan_member_del(struct ocelot *ocelot, int port, u16 vid) 507 { 508 struct ocelot_bridge_vlan *vlan = ocelot_bridge_vlan_find(ocelot, vid); 509 unsigned long portmask; 510 int err; 511 512 if (!vlan) 513 return 0; 514 515 portmask = vlan->portmask & ~BIT(port); 516 517 err = ocelot_vlant_set_mask(ocelot, vid, portmask); 518 if (err) 519 return err; 520 521 vlan->portmask = portmask; 522 if (vlan->portmask) 523 return 0; 524 525 list_del(&vlan->list); 526 kfree(vlan); 527 528 return 0; 529 } 530 531 static int ocelot_add_vlan_unaware_pvid(struct ocelot *ocelot, int port, 532 const struct net_device *bridge) 533 { 534 u16 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 535 536 return ocelot_vlan_member_add(ocelot, port, vid, true); 537 } 538 539 static int ocelot_del_vlan_unaware_pvid(struct ocelot *ocelot, int port, 540 const struct net_device *bridge) 541 { 542 u16 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 543 544 return ocelot_vlan_member_del(ocelot, port, vid); 545 } 546 547 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, 548 bool vlan_aware, struct netlink_ext_ack *extack) 549 { 550 struct ocelot_vcap_block *block = &ocelot->block[VCAP_IS1]; 551 struct ocelot_port *ocelot_port = ocelot->ports[port]; 552 struct ocelot_vcap_filter *filter; 553 int err = 0; 554 u32 val; 555 556 list_for_each_entry(filter, &block->rules, list) { 557 if (filter->ingress_port_mask & BIT(port) && 558 filter->action.vid_replace_ena) { 559 NL_SET_ERR_MSG_MOD(extack, 560 "Cannot change VLAN state with vlan modify rules active"); 561 return -EBUSY; 562 } 563 } 564 565 err = ocelot_single_vlan_aware_bridge(ocelot, extack); 566 if (err) 567 return err; 568 569 if (vlan_aware) 570 err = ocelot_del_vlan_unaware_pvid(ocelot, port, 571 ocelot_port->bridge); 572 else if (ocelot_port->bridge) 573 err = ocelot_add_vlan_unaware_pvid(ocelot, port, 574 ocelot_port->bridge); 575 if (err) 576 return err; 577 578 ocelot_port->vlan_aware = vlan_aware; 579 580 if (vlan_aware) 581 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 582 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1); 583 else 584 val = 0; 585 ocelot_rmw_gix(ocelot, val, 586 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 587 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M, 588 ANA_PORT_VLAN_CFG, port); 589 590 ocelot_port_set_pvid(ocelot, port, ocelot_port->pvid_vlan); 591 ocelot_port_manage_port_tag(ocelot, port); 592 593 return 0; 594 } 595 EXPORT_SYMBOL(ocelot_port_vlan_filtering); 596 597 int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid, 598 bool untagged, struct netlink_ext_ack *extack) 599 { 600 if (untagged) { 601 /* We are adding an egress-tagged VLAN */ 602 if (ocelot_port_uses_native_vlan(ocelot, port)) { 603 NL_SET_ERR_MSG_MOD(extack, 604 "Port with egress-tagged VLANs cannot have more than one egress-untagged (native) VLAN"); 605 return -EBUSY; 606 } 607 } else { 608 /* We are adding an egress-tagged VLAN */ 609 if (ocelot_port_num_untagged_vlans(ocelot, port) > 1) { 610 NL_SET_ERR_MSG_MOD(extack, 611 "Port with more than one egress-untagged VLAN cannot have egress-tagged VLANs"); 612 return -EBUSY; 613 } 614 } 615 616 if (vid > OCELOT_RSV_VLAN_RANGE_START) { 617 NL_SET_ERR_MSG_MOD(extack, 618 "VLAN range 4000-4095 reserved for VLAN-unaware bridging"); 619 return -EBUSY; 620 } 621 622 return 0; 623 } 624 EXPORT_SYMBOL(ocelot_vlan_prepare); 625 626 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid, 627 bool untagged) 628 { 629 int err; 630 631 /* Ignore VID 0 added to our RX filter by the 8021q module, since 632 * that collides with OCELOT_STANDALONE_PVID and changes it from 633 * egress-untagged to egress-tagged. 634 */ 635 if (!vid) 636 return 0; 637 638 err = ocelot_vlan_member_add(ocelot, port, vid, untagged); 639 if (err) 640 return err; 641 642 /* Default ingress vlan classification */ 643 if (pvid) 644 ocelot_port_set_pvid(ocelot, port, 645 ocelot_bridge_vlan_find(ocelot, vid)); 646 647 /* Untagged egress vlan clasification */ 648 ocelot_port_manage_port_tag(ocelot, port); 649 650 return 0; 651 } 652 EXPORT_SYMBOL(ocelot_vlan_add); 653 654 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid) 655 { 656 struct ocelot_port *ocelot_port = ocelot->ports[port]; 657 bool del_pvid = false; 658 int err; 659 660 if (!vid) 661 return 0; 662 663 if (ocelot_port->pvid_vlan && ocelot_port->pvid_vlan->vid == vid) 664 del_pvid = true; 665 666 err = ocelot_vlan_member_del(ocelot, port, vid); 667 if (err) 668 return err; 669 670 /* Ingress */ 671 if (del_pvid) 672 ocelot_port_set_pvid(ocelot, port, NULL); 673 674 /* Egress */ 675 ocelot_port_manage_port_tag(ocelot, port); 676 677 return 0; 678 } 679 EXPORT_SYMBOL(ocelot_vlan_del); 680 681 static void ocelot_vlan_init(struct ocelot *ocelot) 682 { 683 unsigned long all_ports = GENMASK(ocelot->num_phys_ports - 1, 0); 684 u16 port, vid; 685 686 /* Clear VLAN table, by default all ports are members of all VLANs */ 687 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT, 688 ANA_TABLES_VLANACCESS); 689 ocelot_vlant_wait_for_completion(ocelot); 690 691 /* Configure the port VLAN memberships */ 692 for (vid = 1; vid < VLAN_N_VID; vid++) 693 ocelot_vlant_set_mask(ocelot, vid, 0); 694 695 /* We need VID 0 to get traffic on standalone ports. 696 * It is added automatically if the 8021q module is loaded, but we 697 * can't rely on that since it might not be. 698 */ 699 ocelot_vlant_set_mask(ocelot, OCELOT_STANDALONE_PVID, all_ports); 700 701 /* Set vlan ingress filter mask to all ports but the CPU port by 702 * default. 703 */ 704 ocelot_write(ocelot, all_ports, ANA_VLANMASK); 705 706 for (port = 0; port < ocelot->num_phys_ports; port++) { 707 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port); 708 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port); 709 } 710 } 711 712 static u32 ocelot_read_eq_avail(struct ocelot *ocelot, int port) 713 { 714 return ocelot_read_rix(ocelot, QSYS_SW_STATUS, port); 715 } 716 717 static int ocelot_port_flush(struct ocelot *ocelot, int port) 718 { 719 unsigned int pause_ena; 720 int err, val; 721 722 /* Disable dequeuing from the egress queues */ 723 ocelot_rmw_rix(ocelot, QSYS_PORT_MODE_DEQUEUE_DIS, 724 QSYS_PORT_MODE_DEQUEUE_DIS, 725 QSYS_PORT_MODE, port); 726 727 /* Disable flow control */ 728 ocelot_fields_read(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, &pause_ena); 729 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 0); 730 731 /* Disable priority flow control */ 732 ocelot_fields_write(ocelot, port, 733 QSYS_SWITCH_PORT_MODE_TX_PFC_ENA, 0); 734 735 /* Wait at least the time it takes to receive a frame of maximum length 736 * at the port. 737 * Worst-case delays for 10 kilobyte jumbo frames are: 738 * 8 ms on a 10M port 739 * 800 μs on a 100M port 740 * 80 μs on a 1G port 741 * 32 μs on a 2.5G port 742 */ 743 usleep_range(8000, 10000); 744 745 /* Disable half duplex backpressure. */ 746 ocelot_rmw_rix(ocelot, 0, SYS_FRONT_PORT_MODE_HDX_MODE, 747 SYS_FRONT_PORT_MODE, port); 748 749 /* Flush the queues associated with the port. */ 750 ocelot_rmw_gix(ocelot, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG_FLUSH_ENA, 751 REW_PORT_CFG, port); 752 753 /* Enable dequeuing from the egress queues. */ 754 ocelot_rmw_rix(ocelot, 0, QSYS_PORT_MODE_DEQUEUE_DIS, QSYS_PORT_MODE, 755 port); 756 757 /* Wait until flushing is complete. */ 758 err = read_poll_timeout(ocelot_read_eq_avail, val, !val, 759 100, 2000000, false, ocelot, port); 760 761 /* Clear flushing again. */ 762 ocelot_rmw_gix(ocelot, 0, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG, port); 763 764 /* Re-enable flow control */ 765 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, pause_ena); 766 767 return err; 768 } 769 770 void ocelot_phylink_mac_link_down(struct ocelot *ocelot, int port, 771 unsigned int link_an_mode, 772 phy_interface_t interface, 773 unsigned long quirks) 774 { 775 struct ocelot_port *ocelot_port = ocelot->ports[port]; 776 int err; 777 778 ocelot_port->speed = SPEED_UNKNOWN; 779 780 ocelot_port_rmwl(ocelot_port, 0, DEV_MAC_ENA_CFG_RX_ENA, 781 DEV_MAC_ENA_CFG); 782 783 if (ocelot->ops->cut_through_fwd) { 784 mutex_lock(&ocelot->fwd_domain_lock); 785 ocelot->ops->cut_through_fwd(ocelot); 786 mutex_unlock(&ocelot->fwd_domain_lock); 787 } 788 789 ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0); 790 791 err = ocelot_port_flush(ocelot, port); 792 if (err) 793 dev_err(ocelot->dev, "failed to flush port %d: %d\n", 794 port, err); 795 796 /* Put the port in reset. */ 797 if (interface != PHY_INTERFACE_MODE_QSGMII || 798 !(quirks & OCELOT_QUIRK_QSGMII_PORTS_MUST_BE_UP)) 799 ocelot_port_rmwl(ocelot_port, 800 DEV_CLOCK_CFG_MAC_TX_RST | 801 DEV_CLOCK_CFG_MAC_RX_RST, 802 DEV_CLOCK_CFG_MAC_TX_RST | 803 DEV_CLOCK_CFG_MAC_RX_RST, 804 DEV_CLOCK_CFG); 805 } 806 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_down); 807 808 void ocelot_phylink_mac_link_up(struct ocelot *ocelot, int port, 809 struct phy_device *phydev, 810 unsigned int link_an_mode, 811 phy_interface_t interface, 812 int speed, int duplex, 813 bool tx_pause, bool rx_pause, 814 unsigned long quirks) 815 { 816 struct ocelot_port *ocelot_port = ocelot->ports[port]; 817 int mac_speed, mode = 0; 818 u32 mac_fc_cfg; 819 820 ocelot_port->speed = speed; 821 822 /* The MAC might be integrated in systems where the MAC speed is fixed 823 * and it's the PCS who is performing the rate adaptation, so we have 824 * to write "1000Mbps" into the LINK_SPEED field of DEV_CLOCK_CFG 825 * (which is also its default value). 826 */ 827 if ((quirks & OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION) || 828 speed == SPEED_1000) { 829 mac_speed = OCELOT_SPEED_1000; 830 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 831 } else if (speed == SPEED_2500) { 832 mac_speed = OCELOT_SPEED_2500; 833 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 834 } else if (speed == SPEED_100) { 835 mac_speed = OCELOT_SPEED_100; 836 } else { 837 mac_speed = OCELOT_SPEED_10; 838 } 839 840 if (duplex == DUPLEX_FULL) 841 mode |= DEV_MAC_MODE_CFG_FDX_ENA; 842 843 ocelot_port_writel(ocelot_port, mode, DEV_MAC_MODE_CFG); 844 845 /* Take port out of reset by clearing the MAC_TX_RST, MAC_RX_RST and 846 * PORT_RST bits in DEV_CLOCK_CFG. 847 */ 848 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(mac_speed), 849 DEV_CLOCK_CFG); 850 851 switch (speed) { 852 case SPEED_10: 853 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_10); 854 break; 855 case SPEED_100: 856 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_100); 857 break; 858 case SPEED_1000: 859 case SPEED_2500: 860 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_1000); 861 break; 862 default: 863 dev_err(ocelot->dev, "Unsupported speed on port %d: %d\n", 864 port, speed); 865 return; 866 } 867 868 /* Handle RX pause in all cases, with 2500base-X this is used for rate 869 * adaptation. 870 */ 871 mac_fc_cfg |= SYS_MAC_FC_CFG_RX_FC_ENA; 872 873 if (tx_pause) 874 mac_fc_cfg |= SYS_MAC_FC_CFG_TX_FC_ENA | 875 SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) | 876 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) | 877 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA; 878 879 /* Flow control. Link speed is only used here to evaluate the time 880 * specification in incoming pause frames. 881 */ 882 ocelot_write_rix(ocelot, mac_fc_cfg, SYS_MAC_FC_CFG, port); 883 884 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port); 885 886 /* Don't attempt to send PAUSE frames on the NPI port, it's broken */ 887 if (port != ocelot->npi) 888 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 889 tx_pause); 890 891 /* Undo the effects of ocelot_phylink_mac_link_down: 892 * enable MAC module 893 */ 894 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA | 895 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG); 896 897 /* If the port supports cut-through forwarding, update the masks before 898 * enabling forwarding on the port. 899 */ 900 if (ocelot->ops->cut_through_fwd) { 901 mutex_lock(&ocelot->fwd_domain_lock); 902 ocelot->ops->cut_through_fwd(ocelot); 903 mutex_unlock(&ocelot->fwd_domain_lock); 904 } 905 906 /* Core: Enable port for frame transfer */ 907 ocelot_fields_write(ocelot, port, 908 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 909 } 910 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_up); 911 912 static int ocelot_rx_frame_word(struct ocelot *ocelot, u8 grp, bool ifh, 913 u32 *rval) 914 { 915 u32 bytes_valid, val; 916 917 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 918 if (val == XTR_NOT_READY) { 919 if (ifh) 920 return -EIO; 921 922 do { 923 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 924 } while (val == XTR_NOT_READY); 925 } 926 927 switch (val) { 928 case XTR_ABORT: 929 return -EIO; 930 case XTR_EOF_0: 931 case XTR_EOF_1: 932 case XTR_EOF_2: 933 case XTR_EOF_3: 934 case XTR_PRUNED: 935 bytes_valid = XTR_VALID_BYTES(val); 936 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 937 if (val == XTR_ESCAPE) 938 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 939 else 940 *rval = val; 941 942 return bytes_valid; 943 case XTR_ESCAPE: 944 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 945 946 return 4; 947 default: 948 *rval = val; 949 950 return 4; 951 } 952 } 953 954 static int ocelot_xtr_poll_xfh(struct ocelot *ocelot, int grp, u32 *xfh) 955 { 956 int i, err = 0; 957 958 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) { 959 err = ocelot_rx_frame_word(ocelot, grp, true, &xfh[i]); 960 if (err != 4) 961 return (err < 0) ? err : -EIO; 962 } 963 964 return 0; 965 } 966 967 void ocelot_ptp_rx_timestamp(struct ocelot *ocelot, struct sk_buff *skb, 968 u64 timestamp) 969 { 970 struct skb_shared_hwtstamps *shhwtstamps; 971 u64 tod_in_ns, full_ts_in_ns; 972 struct timespec64 ts; 973 974 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); 975 976 tod_in_ns = ktime_set(ts.tv_sec, ts.tv_nsec); 977 if ((tod_in_ns & 0xffffffff) < timestamp) 978 full_ts_in_ns = (((tod_in_ns >> 32) - 1) << 32) | 979 timestamp; 980 else 981 full_ts_in_ns = (tod_in_ns & GENMASK_ULL(63, 32)) | 982 timestamp; 983 984 shhwtstamps = skb_hwtstamps(skb); 985 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps)); 986 shhwtstamps->hwtstamp = full_ts_in_ns; 987 } 988 EXPORT_SYMBOL(ocelot_ptp_rx_timestamp); 989 990 int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **nskb) 991 { 992 u64 timestamp, src_port, len; 993 u32 xfh[OCELOT_TAG_LEN / 4]; 994 struct net_device *dev; 995 struct sk_buff *skb; 996 int sz, buf_len; 997 u32 val, *buf; 998 int err; 999 1000 err = ocelot_xtr_poll_xfh(ocelot, grp, xfh); 1001 if (err) 1002 return err; 1003 1004 ocelot_xfh_get_src_port(xfh, &src_port); 1005 ocelot_xfh_get_len(xfh, &len); 1006 ocelot_xfh_get_rew_val(xfh, ×tamp); 1007 1008 if (WARN_ON(src_port >= ocelot->num_phys_ports)) 1009 return -EINVAL; 1010 1011 dev = ocelot->ops->port_to_netdev(ocelot, src_port); 1012 if (!dev) 1013 return -EINVAL; 1014 1015 skb = netdev_alloc_skb(dev, len); 1016 if (unlikely(!skb)) { 1017 netdev_err(dev, "Unable to allocate sk_buff\n"); 1018 return -ENOMEM; 1019 } 1020 1021 buf_len = len - ETH_FCS_LEN; 1022 buf = (u32 *)skb_put(skb, buf_len); 1023 1024 len = 0; 1025 do { 1026 sz = ocelot_rx_frame_word(ocelot, grp, false, &val); 1027 if (sz < 0) { 1028 err = sz; 1029 goto out_free_skb; 1030 } 1031 *buf++ = val; 1032 len += sz; 1033 } while (len < buf_len); 1034 1035 /* Read the FCS */ 1036 sz = ocelot_rx_frame_word(ocelot, grp, false, &val); 1037 if (sz < 0) { 1038 err = sz; 1039 goto out_free_skb; 1040 } 1041 1042 /* Update the statistics if part of the FCS was read before */ 1043 len -= ETH_FCS_LEN - sz; 1044 1045 if (unlikely(dev->features & NETIF_F_RXFCS)) { 1046 buf = (u32 *)skb_put(skb, ETH_FCS_LEN); 1047 *buf = val; 1048 } 1049 1050 if (ocelot->ptp) 1051 ocelot_ptp_rx_timestamp(ocelot, skb, timestamp); 1052 1053 /* Everything we see on an interface that is in the HW bridge 1054 * has already been forwarded. 1055 */ 1056 if (ocelot->ports[src_port]->bridge) 1057 skb->offload_fwd_mark = 1; 1058 1059 skb->protocol = eth_type_trans(skb, dev); 1060 1061 *nskb = skb; 1062 1063 return 0; 1064 1065 out_free_skb: 1066 kfree_skb(skb); 1067 return err; 1068 } 1069 EXPORT_SYMBOL(ocelot_xtr_poll_frame); 1070 1071 bool ocelot_can_inject(struct ocelot *ocelot, int grp) 1072 { 1073 u32 val = ocelot_read(ocelot, QS_INJ_STATUS); 1074 1075 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp)))) 1076 return false; 1077 if (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp))) 1078 return false; 1079 1080 return true; 1081 } 1082 EXPORT_SYMBOL(ocelot_can_inject); 1083 1084 void ocelot_ifh_port_set(void *ifh, int port, u32 rew_op, u32 vlan_tag) 1085 { 1086 ocelot_ifh_set_bypass(ifh, 1); 1087 ocelot_ifh_set_dest(ifh, BIT_ULL(port)); 1088 ocelot_ifh_set_tag_type(ifh, IFH_TAG_TYPE_C); 1089 if (vlan_tag) 1090 ocelot_ifh_set_vlan_tci(ifh, vlan_tag); 1091 if (rew_op) 1092 ocelot_ifh_set_rew_op(ifh, rew_op); 1093 } 1094 EXPORT_SYMBOL(ocelot_ifh_port_set); 1095 1096 void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp, 1097 u32 rew_op, struct sk_buff *skb) 1098 { 1099 u32 ifh[OCELOT_TAG_LEN / 4] = {0}; 1100 unsigned int i, count, last; 1101 1102 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 1103 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp); 1104 1105 ocelot_ifh_port_set(ifh, port, rew_op, skb_vlan_tag_get(skb)); 1106 1107 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) 1108 ocelot_write_rix(ocelot, ifh[i], QS_INJ_WR, grp); 1109 1110 count = DIV_ROUND_UP(skb->len, 4); 1111 last = skb->len % 4; 1112 for (i = 0; i < count; i++) 1113 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp); 1114 1115 /* Add padding */ 1116 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) { 1117 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 1118 i++; 1119 } 1120 1121 /* Indicate EOF and valid bytes in last word */ 1122 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 1123 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) | 1124 QS_INJ_CTRL_EOF, 1125 QS_INJ_CTRL, grp); 1126 1127 /* Add dummy CRC */ 1128 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 1129 skb_tx_timestamp(skb); 1130 1131 skb->dev->stats.tx_packets++; 1132 skb->dev->stats.tx_bytes += skb->len; 1133 } 1134 EXPORT_SYMBOL(ocelot_port_inject_frame); 1135 1136 void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp) 1137 { 1138 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)) 1139 ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1140 } 1141 EXPORT_SYMBOL(ocelot_drain_cpu_queue); 1142 1143 int ocelot_fdb_add(struct ocelot *ocelot, int port, const unsigned char *addr, 1144 u16 vid, const struct net_device *bridge) 1145 { 1146 if (!vid) 1147 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 1148 1149 return ocelot_mact_learn(ocelot, port, addr, vid, ENTRYTYPE_LOCKED); 1150 } 1151 EXPORT_SYMBOL(ocelot_fdb_add); 1152 1153 int ocelot_fdb_del(struct ocelot *ocelot, int port, const unsigned char *addr, 1154 u16 vid, const struct net_device *bridge) 1155 { 1156 if (!vid) 1157 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 1158 1159 return ocelot_mact_forget(ocelot, addr, vid); 1160 } 1161 EXPORT_SYMBOL(ocelot_fdb_del); 1162 1163 /* Caller must hold &ocelot->mact_lock */ 1164 static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col, 1165 struct ocelot_mact_entry *entry) 1166 { 1167 u32 val, dst, macl, mach; 1168 char mac[ETH_ALEN]; 1169 1170 /* Set row and column to read from */ 1171 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row); 1172 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col); 1173 1174 /* Issue a read command */ 1175 ocelot_write(ocelot, 1176 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 1177 ANA_TABLES_MACACCESS); 1178 1179 if (ocelot_mact_wait_for_completion(ocelot)) 1180 return -ETIMEDOUT; 1181 1182 /* Read the entry flags */ 1183 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 1184 if (!(val & ANA_TABLES_MACACCESS_VALID)) 1185 return -EINVAL; 1186 1187 /* If the entry read has another port configured as its destination, 1188 * do not report it. 1189 */ 1190 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3; 1191 if (dst != port) 1192 return -EINVAL; 1193 1194 /* Get the entry's MAC address and VLAN id */ 1195 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA); 1196 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA); 1197 1198 mac[0] = (mach >> 8) & 0xff; 1199 mac[1] = (mach >> 0) & 0xff; 1200 mac[2] = (macl >> 24) & 0xff; 1201 mac[3] = (macl >> 16) & 0xff; 1202 mac[4] = (macl >> 8) & 0xff; 1203 mac[5] = (macl >> 0) & 0xff; 1204 1205 entry->vid = (mach >> 16) & 0xfff; 1206 ether_addr_copy(entry->mac, mac); 1207 1208 return 0; 1209 } 1210 1211 int ocelot_mact_flush(struct ocelot *ocelot, int port) 1212 { 1213 int err; 1214 1215 mutex_lock(&ocelot->mact_lock); 1216 1217 /* Program ageing filter for a single port */ 1218 ocelot_write(ocelot, ANA_ANAGEFIL_PID_EN | ANA_ANAGEFIL_PID_VAL(port), 1219 ANA_ANAGEFIL); 1220 1221 /* Flushing dynamic FDB entries requires two successive age scans */ 1222 ocelot_write(ocelot, 1223 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_AGE), 1224 ANA_TABLES_MACACCESS); 1225 1226 err = ocelot_mact_wait_for_completion(ocelot); 1227 if (err) { 1228 mutex_unlock(&ocelot->mact_lock); 1229 return err; 1230 } 1231 1232 /* And second... */ 1233 ocelot_write(ocelot, 1234 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_AGE), 1235 ANA_TABLES_MACACCESS); 1236 1237 err = ocelot_mact_wait_for_completion(ocelot); 1238 1239 /* Restore ageing filter */ 1240 ocelot_write(ocelot, 0, ANA_ANAGEFIL); 1241 1242 mutex_unlock(&ocelot->mact_lock); 1243 1244 return err; 1245 } 1246 EXPORT_SYMBOL_GPL(ocelot_mact_flush); 1247 1248 int ocelot_fdb_dump(struct ocelot *ocelot, int port, 1249 dsa_fdb_dump_cb_t *cb, void *data) 1250 { 1251 int err = 0; 1252 int i, j; 1253 1254 /* We could take the lock just around ocelot_mact_read, but doing so 1255 * thousands of times in a row seems rather pointless and inefficient. 1256 */ 1257 mutex_lock(&ocelot->mact_lock); 1258 1259 /* Loop through all the mac tables entries. */ 1260 for (i = 0; i < ocelot->num_mact_rows; i++) { 1261 for (j = 0; j < 4; j++) { 1262 struct ocelot_mact_entry entry; 1263 bool is_static; 1264 1265 err = ocelot_mact_read(ocelot, port, i, j, &entry); 1266 /* If the entry is invalid (wrong port, invalid...), 1267 * skip it. 1268 */ 1269 if (err == -EINVAL) 1270 continue; 1271 else if (err) 1272 break; 1273 1274 is_static = (entry.type == ENTRYTYPE_LOCKED); 1275 1276 /* Hide the reserved VLANs used for 1277 * VLAN-unaware bridging. 1278 */ 1279 if (entry.vid > OCELOT_RSV_VLAN_RANGE_START) 1280 entry.vid = 0; 1281 1282 err = cb(entry.mac, entry.vid, is_static, data); 1283 if (err) 1284 break; 1285 } 1286 } 1287 1288 mutex_unlock(&ocelot->mact_lock); 1289 1290 return err; 1291 } 1292 EXPORT_SYMBOL(ocelot_fdb_dump); 1293 1294 int ocelot_trap_add(struct ocelot *ocelot, int port, 1295 unsigned long cookie, bool take_ts, 1296 void (*populate)(struct ocelot_vcap_filter *f)) 1297 { 1298 struct ocelot_vcap_block *block_vcap_is2; 1299 struct ocelot_vcap_filter *trap; 1300 bool new = false; 1301 int err; 1302 1303 block_vcap_is2 = &ocelot->block[VCAP_IS2]; 1304 1305 trap = ocelot_vcap_block_find_filter_by_id(block_vcap_is2, cookie, 1306 false); 1307 if (!trap) { 1308 trap = kzalloc(sizeof(*trap), GFP_KERNEL); 1309 if (!trap) 1310 return -ENOMEM; 1311 1312 populate(trap); 1313 trap->prio = 1; 1314 trap->id.cookie = cookie; 1315 trap->id.tc_offload = false; 1316 trap->block_id = VCAP_IS2; 1317 trap->type = OCELOT_VCAP_FILTER_OFFLOAD; 1318 trap->lookup = 0; 1319 trap->action.cpu_copy_ena = true; 1320 trap->action.mask_mode = OCELOT_MASK_MODE_PERMIT_DENY; 1321 trap->action.port_mask = 0; 1322 trap->take_ts = take_ts; 1323 trap->is_trap = true; 1324 new = true; 1325 } 1326 1327 trap->ingress_port_mask |= BIT(port); 1328 1329 if (new) 1330 err = ocelot_vcap_filter_add(ocelot, trap, NULL); 1331 else 1332 err = ocelot_vcap_filter_replace(ocelot, trap); 1333 if (err) { 1334 trap->ingress_port_mask &= ~BIT(port); 1335 if (!trap->ingress_port_mask) 1336 kfree(trap); 1337 return err; 1338 } 1339 1340 return 0; 1341 } 1342 1343 int ocelot_trap_del(struct ocelot *ocelot, int port, unsigned long cookie) 1344 { 1345 struct ocelot_vcap_block *block_vcap_is2; 1346 struct ocelot_vcap_filter *trap; 1347 1348 block_vcap_is2 = &ocelot->block[VCAP_IS2]; 1349 1350 trap = ocelot_vcap_block_find_filter_by_id(block_vcap_is2, cookie, 1351 false); 1352 if (!trap) 1353 return 0; 1354 1355 trap->ingress_port_mask &= ~BIT(port); 1356 if (!trap->ingress_port_mask) 1357 return ocelot_vcap_filter_del(ocelot, trap); 1358 1359 return ocelot_vcap_filter_replace(ocelot, trap); 1360 } 1361 1362 static u32 ocelot_get_bond_mask(struct ocelot *ocelot, struct net_device *bond) 1363 { 1364 u32 mask = 0; 1365 int port; 1366 1367 lockdep_assert_held(&ocelot->fwd_domain_lock); 1368 1369 for (port = 0; port < ocelot->num_phys_ports; port++) { 1370 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1371 1372 if (!ocelot_port) 1373 continue; 1374 1375 if (ocelot_port->bond == bond) 1376 mask |= BIT(port); 1377 } 1378 1379 return mask; 1380 } 1381 1382 /* The logical port number of a LAG is equal to the lowest numbered physical 1383 * port ID present in that LAG. It may change if that port ever leaves the LAG. 1384 */ 1385 int ocelot_bond_get_id(struct ocelot *ocelot, struct net_device *bond) 1386 { 1387 int bond_mask = ocelot_get_bond_mask(ocelot, bond); 1388 1389 if (!bond_mask) 1390 return -ENOENT; 1391 1392 return __ffs(bond_mask); 1393 } 1394 EXPORT_SYMBOL_GPL(ocelot_bond_get_id); 1395 1396 /* Returns the mask of user ports assigned to this DSA tag_8021q CPU port. 1397 * Note that when CPU ports are in a LAG, the user ports are assigned to the 1398 * 'primary' CPU port, the one whose physical port number gives the logical 1399 * port number of the LAG. 1400 * 1401 * We leave PGID_SRC poorly configured for the 'secondary' CPU port in the LAG 1402 * (to which no user port is assigned), but it appears that forwarding from 1403 * this secondary CPU port looks at the PGID_SRC associated with the logical 1404 * port ID that it's assigned to, which *is* configured properly. 1405 */ 1406 static u32 ocelot_dsa_8021q_cpu_assigned_ports(struct ocelot *ocelot, 1407 struct ocelot_port *cpu) 1408 { 1409 u32 mask = 0; 1410 int port; 1411 1412 for (port = 0; port < ocelot->num_phys_ports; port++) { 1413 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1414 1415 if (!ocelot_port) 1416 continue; 1417 1418 if (ocelot_port->dsa_8021q_cpu == cpu) 1419 mask |= BIT(port); 1420 } 1421 1422 if (cpu->bond) 1423 mask &= ~ocelot_get_bond_mask(ocelot, cpu->bond); 1424 1425 return mask; 1426 } 1427 1428 /* Returns the DSA tag_8021q CPU port that the given port is assigned to, 1429 * or the bit mask of CPU ports if said CPU port is in a LAG. 1430 */ 1431 u32 ocelot_port_assigned_dsa_8021q_cpu_mask(struct ocelot *ocelot, int port) 1432 { 1433 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1434 struct ocelot_port *cpu_port = ocelot_port->dsa_8021q_cpu; 1435 1436 if (!cpu_port) 1437 return 0; 1438 1439 if (cpu_port->bond) 1440 return ocelot_get_bond_mask(ocelot, cpu_port->bond); 1441 1442 return BIT(cpu_port->index); 1443 } 1444 EXPORT_SYMBOL_GPL(ocelot_port_assigned_dsa_8021q_cpu_mask); 1445 1446 u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot, int src_port) 1447 { 1448 struct ocelot_port *ocelot_port = ocelot->ports[src_port]; 1449 const struct net_device *bridge; 1450 u32 mask = 0; 1451 int port; 1452 1453 if (!ocelot_port || ocelot_port->stp_state != BR_STATE_FORWARDING) 1454 return 0; 1455 1456 bridge = ocelot_port->bridge; 1457 if (!bridge) 1458 return 0; 1459 1460 for (port = 0; port < ocelot->num_phys_ports; port++) { 1461 ocelot_port = ocelot->ports[port]; 1462 1463 if (!ocelot_port) 1464 continue; 1465 1466 if (ocelot_port->stp_state == BR_STATE_FORWARDING && 1467 ocelot_port->bridge == bridge) 1468 mask |= BIT(port); 1469 } 1470 1471 return mask; 1472 } 1473 EXPORT_SYMBOL_GPL(ocelot_get_bridge_fwd_mask); 1474 1475 static void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot, bool joining) 1476 { 1477 int port; 1478 1479 lockdep_assert_held(&ocelot->fwd_domain_lock); 1480 1481 /* If cut-through forwarding is supported, update the masks before a 1482 * port joins the forwarding domain, to avoid potential underruns if it 1483 * has the highest speed from the new domain. 1484 */ 1485 if (joining && ocelot->ops->cut_through_fwd) 1486 ocelot->ops->cut_through_fwd(ocelot); 1487 1488 /* Apply FWD mask. The loop is needed to add/remove the current port as 1489 * a source for the other ports. 1490 */ 1491 for (port = 0; port < ocelot->num_phys_ports; port++) { 1492 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1493 unsigned long mask; 1494 1495 if (!ocelot_port) { 1496 /* Unused ports can't send anywhere */ 1497 mask = 0; 1498 } else if (ocelot_port->is_dsa_8021q_cpu) { 1499 /* The DSA tag_8021q CPU ports need to be able to 1500 * forward packets to all ports assigned to them. 1501 */ 1502 mask = ocelot_dsa_8021q_cpu_assigned_ports(ocelot, 1503 ocelot_port); 1504 } else if (ocelot_port->bridge) { 1505 struct net_device *bond = ocelot_port->bond; 1506 1507 mask = ocelot_get_bridge_fwd_mask(ocelot, port); 1508 mask &= ~BIT(port); 1509 1510 mask |= ocelot_port_assigned_dsa_8021q_cpu_mask(ocelot, 1511 port); 1512 1513 if (bond) 1514 mask &= ~ocelot_get_bond_mask(ocelot, bond); 1515 } else { 1516 /* Standalone ports forward only to DSA tag_8021q CPU 1517 * ports (if those exist), or to the hardware CPU port 1518 * module otherwise. 1519 */ 1520 mask = ocelot_port_assigned_dsa_8021q_cpu_mask(ocelot, 1521 port); 1522 } 1523 1524 ocelot_write_rix(ocelot, mask, ANA_PGID_PGID, PGID_SRC + port); 1525 } 1526 1527 /* If cut-through forwarding is supported and a port is leaving, there 1528 * is a chance that cut-through was disabled on the other ports due to 1529 * the port which is leaving (it has a higher link speed). We need to 1530 * update the cut-through masks of the remaining ports no earlier than 1531 * after the port has left, to prevent underruns from happening between 1532 * the cut-through update and the forwarding domain update. 1533 */ 1534 if (!joining && ocelot->ops->cut_through_fwd) 1535 ocelot->ops->cut_through_fwd(ocelot); 1536 } 1537 1538 /* Update PGID_CPU which is the destination port mask used for whitelisting 1539 * unicast addresses filtered towards the host. In the normal and NPI modes, 1540 * this points to the analyzer entry for the CPU port module, while in DSA 1541 * tag_8021q mode, it is a bit mask of all active CPU ports. 1542 * PGID_SRC will take care of forwarding a packet from one user port to 1543 * no more than a single CPU port. 1544 */ 1545 static void ocelot_update_pgid_cpu(struct ocelot *ocelot) 1546 { 1547 int pgid_cpu = 0; 1548 int port; 1549 1550 for (port = 0; port < ocelot->num_phys_ports; port++) { 1551 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1552 1553 if (!ocelot_port || !ocelot_port->is_dsa_8021q_cpu) 1554 continue; 1555 1556 pgid_cpu |= BIT(port); 1557 } 1558 1559 if (!pgid_cpu) 1560 pgid_cpu = BIT(ocelot->num_phys_ports); 1561 1562 ocelot_write_rix(ocelot, pgid_cpu, ANA_PGID_PGID, PGID_CPU); 1563 } 1564 1565 void ocelot_port_setup_dsa_8021q_cpu(struct ocelot *ocelot, int cpu) 1566 { 1567 struct ocelot_port *cpu_port = ocelot->ports[cpu]; 1568 u16 vid; 1569 1570 mutex_lock(&ocelot->fwd_domain_lock); 1571 1572 cpu_port->is_dsa_8021q_cpu = true; 1573 1574 for (vid = OCELOT_RSV_VLAN_RANGE_START; vid < VLAN_N_VID; vid++) 1575 ocelot_vlan_member_add(ocelot, cpu, vid, true); 1576 1577 ocelot_update_pgid_cpu(ocelot); 1578 1579 mutex_unlock(&ocelot->fwd_domain_lock); 1580 } 1581 EXPORT_SYMBOL_GPL(ocelot_port_setup_dsa_8021q_cpu); 1582 1583 void ocelot_port_teardown_dsa_8021q_cpu(struct ocelot *ocelot, int cpu) 1584 { 1585 struct ocelot_port *cpu_port = ocelot->ports[cpu]; 1586 u16 vid; 1587 1588 mutex_lock(&ocelot->fwd_domain_lock); 1589 1590 cpu_port->is_dsa_8021q_cpu = false; 1591 1592 for (vid = OCELOT_RSV_VLAN_RANGE_START; vid < VLAN_N_VID; vid++) 1593 ocelot_vlan_member_del(ocelot, cpu_port->index, vid); 1594 1595 ocelot_update_pgid_cpu(ocelot); 1596 1597 mutex_unlock(&ocelot->fwd_domain_lock); 1598 } 1599 EXPORT_SYMBOL_GPL(ocelot_port_teardown_dsa_8021q_cpu); 1600 1601 void ocelot_port_assign_dsa_8021q_cpu(struct ocelot *ocelot, int port, 1602 int cpu) 1603 { 1604 struct ocelot_port *cpu_port = ocelot->ports[cpu]; 1605 1606 mutex_lock(&ocelot->fwd_domain_lock); 1607 1608 ocelot->ports[port]->dsa_8021q_cpu = cpu_port; 1609 ocelot_apply_bridge_fwd_mask(ocelot, true); 1610 1611 mutex_unlock(&ocelot->fwd_domain_lock); 1612 } 1613 EXPORT_SYMBOL_GPL(ocelot_port_assign_dsa_8021q_cpu); 1614 1615 void ocelot_port_unassign_dsa_8021q_cpu(struct ocelot *ocelot, int port) 1616 { 1617 mutex_lock(&ocelot->fwd_domain_lock); 1618 1619 ocelot->ports[port]->dsa_8021q_cpu = NULL; 1620 ocelot_apply_bridge_fwd_mask(ocelot, true); 1621 1622 mutex_unlock(&ocelot->fwd_domain_lock); 1623 } 1624 EXPORT_SYMBOL_GPL(ocelot_port_unassign_dsa_8021q_cpu); 1625 1626 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state) 1627 { 1628 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1629 u32 learn_ena = 0; 1630 1631 mutex_lock(&ocelot->fwd_domain_lock); 1632 1633 ocelot_port->stp_state = state; 1634 1635 if ((state == BR_STATE_LEARNING || state == BR_STATE_FORWARDING) && 1636 ocelot_port->learn_ena) 1637 learn_ena = ANA_PORT_PORT_CFG_LEARN_ENA; 1638 1639 ocelot_rmw_gix(ocelot, learn_ena, ANA_PORT_PORT_CFG_LEARN_ENA, 1640 ANA_PORT_PORT_CFG, port); 1641 1642 ocelot_apply_bridge_fwd_mask(ocelot, state == BR_STATE_FORWARDING); 1643 1644 mutex_unlock(&ocelot->fwd_domain_lock); 1645 } 1646 EXPORT_SYMBOL(ocelot_bridge_stp_state_set); 1647 1648 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs) 1649 { 1650 unsigned int age_period = ANA_AUTOAGE_AGE_PERIOD(msecs / 2000); 1651 1652 /* Setting AGE_PERIOD to zero effectively disables automatic aging, 1653 * which is clearly not what our intention is. So avoid that. 1654 */ 1655 if (!age_period) 1656 age_period = 1; 1657 1658 ocelot_rmw(ocelot, age_period, ANA_AUTOAGE_AGE_PERIOD_M, ANA_AUTOAGE); 1659 } 1660 EXPORT_SYMBOL(ocelot_set_ageing_time); 1661 1662 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot, 1663 const unsigned char *addr, 1664 u16 vid) 1665 { 1666 struct ocelot_multicast *mc; 1667 1668 list_for_each_entry(mc, &ocelot->multicast, list) { 1669 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid) 1670 return mc; 1671 } 1672 1673 return NULL; 1674 } 1675 1676 static enum macaccess_entry_type ocelot_classify_mdb(const unsigned char *addr) 1677 { 1678 if (addr[0] == 0x01 && addr[1] == 0x00 && addr[2] == 0x5e) 1679 return ENTRYTYPE_MACv4; 1680 if (addr[0] == 0x33 && addr[1] == 0x33) 1681 return ENTRYTYPE_MACv6; 1682 return ENTRYTYPE_LOCKED; 1683 } 1684 1685 static struct ocelot_pgid *ocelot_pgid_alloc(struct ocelot *ocelot, int index, 1686 unsigned long ports) 1687 { 1688 struct ocelot_pgid *pgid; 1689 1690 pgid = kzalloc(sizeof(*pgid), GFP_KERNEL); 1691 if (!pgid) 1692 return ERR_PTR(-ENOMEM); 1693 1694 pgid->ports = ports; 1695 pgid->index = index; 1696 refcount_set(&pgid->refcount, 1); 1697 list_add_tail(&pgid->list, &ocelot->pgids); 1698 1699 return pgid; 1700 } 1701 1702 static void ocelot_pgid_free(struct ocelot *ocelot, struct ocelot_pgid *pgid) 1703 { 1704 if (!refcount_dec_and_test(&pgid->refcount)) 1705 return; 1706 1707 list_del(&pgid->list); 1708 kfree(pgid); 1709 } 1710 1711 static struct ocelot_pgid *ocelot_mdb_get_pgid(struct ocelot *ocelot, 1712 const struct ocelot_multicast *mc) 1713 { 1714 struct ocelot_pgid *pgid; 1715 int index; 1716 1717 /* According to VSC7514 datasheet 3.9.1.5 IPv4 Multicast Entries and 1718 * 3.9.1.6 IPv6 Multicast Entries, "Instead of a lookup in the 1719 * destination mask table (PGID), the destination set is programmed as 1720 * part of the entry MAC address.", and the DEST_IDX is set to 0. 1721 */ 1722 if (mc->entry_type == ENTRYTYPE_MACv4 || 1723 mc->entry_type == ENTRYTYPE_MACv6) 1724 return ocelot_pgid_alloc(ocelot, 0, mc->ports); 1725 1726 list_for_each_entry(pgid, &ocelot->pgids, list) { 1727 /* When searching for a nonreserved multicast PGID, ignore the 1728 * dummy PGID of zero that we have for MACv4/MACv6 entries 1729 */ 1730 if (pgid->index && pgid->ports == mc->ports) { 1731 refcount_inc(&pgid->refcount); 1732 return pgid; 1733 } 1734 } 1735 1736 /* Search for a free index in the nonreserved multicast PGID area */ 1737 for_each_nonreserved_multicast_dest_pgid(ocelot, index) { 1738 bool used = false; 1739 1740 list_for_each_entry(pgid, &ocelot->pgids, list) { 1741 if (pgid->index == index) { 1742 used = true; 1743 break; 1744 } 1745 } 1746 1747 if (!used) 1748 return ocelot_pgid_alloc(ocelot, index, mc->ports); 1749 } 1750 1751 return ERR_PTR(-ENOSPC); 1752 } 1753 1754 static void ocelot_encode_ports_to_mdb(unsigned char *addr, 1755 struct ocelot_multicast *mc) 1756 { 1757 ether_addr_copy(addr, mc->addr); 1758 1759 if (mc->entry_type == ENTRYTYPE_MACv4) { 1760 addr[0] = 0; 1761 addr[1] = mc->ports >> 8; 1762 addr[2] = mc->ports & 0xff; 1763 } else if (mc->entry_type == ENTRYTYPE_MACv6) { 1764 addr[0] = mc->ports >> 8; 1765 addr[1] = mc->ports & 0xff; 1766 } 1767 } 1768 1769 int ocelot_port_mdb_add(struct ocelot *ocelot, int port, 1770 const struct switchdev_obj_port_mdb *mdb, 1771 const struct net_device *bridge) 1772 { 1773 unsigned char addr[ETH_ALEN]; 1774 struct ocelot_multicast *mc; 1775 struct ocelot_pgid *pgid; 1776 u16 vid = mdb->vid; 1777 1778 if (!vid) 1779 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 1780 1781 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1782 if (!mc) { 1783 /* New entry */ 1784 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL); 1785 if (!mc) 1786 return -ENOMEM; 1787 1788 mc->entry_type = ocelot_classify_mdb(mdb->addr); 1789 ether_addr_copy(mc->addr, mdb->addr); 1790 mc->vid = vid; 1791 1792 list_add_tail(&mc->list, &ocelot->multicast); 1793 } else { 1794 /* Existing entry. Clean up the current port mask from 1795 * hardware now, because we'll be modifying it. 1796 */ 1797 ocelot_pgid_free(ocelot, mc->pgid); 1798 ocelot_encode_ports_to_mdb(addr, mc); 1799 ocelot_mact_forget(ocelot, addr, vid); 1800 } 1801 1802 mc->ports |= BIT(port); 1803 1804 pgid = ocelot_mdb_get_pgid(ocelot, mc); 1805 if (IS_ERR(pgid)) { 1806 dev_err(ocelot->dev, 1807 "Cannot allocate PGID for mdb %pM vid %d\n", 1808 mc->addr, mc->vid); 1809 devm_kfree(ocelot->dev, mc); 1810 return PTR_ERR(pgid); 1811 } 1812 mc->pgid = pgid; 1813 1814 ocelot_encode_ports_to_mdb(addr, mc); 1815 1816 if (mc->entry_type != ENTRYTYPE_MACv4 && 1817 mc->entry_type != ENTRYTYPE_MACv6) 1818 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 1819 pgid->index); 1820 1821 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 1822 mc->entry_type); 1823 } 1824 EXPORT_SYMBOL(ocelot_port_mdb_add); 1825 1826 int ocelot_port_mdb_del(struct ocelot *ocelot, int port, 1827 const struct switchdev_obj_port_mdb *mdb, 1828 const struct net_device *bridge) 1829 { 1830 unsigned char addr[ETH_ALEN]; 1831 struct ocelot_multicast *mc; 1832 struct ocelot_pgid *pgid; 1833 u16 vid = mdb->vid; 1834 1835 if (!vid) 1836 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 1837 1838 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1839 if (!mc) 1840 return -ENOENT; 1841 1842 ocelot_encode_ports_to_mdb(addr, mc); 1843 ocelot_mact_forget(ocelot, addr, vid); 1844 1845 ocelot_pgid_free(ocelot, mc->pgid); 1846 mc->ports &= ~BIT(port); 1847 if (!mc->ports) { 1848 list_del(&mc->list); 1849 devm_kfree(ocelot->dev, mc); 1850 return 0; 1851 } 1852 1853 /* We have a PGID with fewer ports now */ 1854 pgid = ocelot_mdb_get_pgid(ocelot, mc); 1855 if (IS_ERR(pgid)) 1856 return PTR_ERR(pgid); 1857 mc->pgid = pgid; 1858 1859 ocelot_encode_ports_to_mdb(addr, mc); 1860 1861 if (mc->entry_type != ENTRYTYPE_MACv4 && 1862 mc->entry_type != ENTRYTYPE_MACv6) 1863 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 1864 pgid->index); 1865 1866 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 1867 mc->entry_type); 1868 } 1869 EXPORT_SYMBOL(ocelot_port_mdb_del); 1870 1871 int ocelot_port_bridge_join(struct ocelot *ocelot, int port, 1872 struct net_device *bridge, int bridge_num, 1873 struct netlink_ext_ack *extack) 1874 { 1875 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1876 int err; 1877 1878 err = ocelot_single_vlan_aware_bridge(ocelot, extack); 1879 if (err) 1880 return err; 1881 1882 mutex_lock(&ocelot->fwd_domain_lock); 1883 1884 ocelot_port->bridge = bridge; 1885 ocelot_port->bridge_num = bridge_num; 1886 1887 ocelot_apply_bridge_fwd_mask(ocelot, true); 1888 1889 mutex_unlock(&ocelot->fwd_domain_lock); 1890 1891 if (br_vlan_enabled(bridge)) 1892 return 0; 1893 1894 return ocelot_add_vlan_unaware_pvid(ocelot, port, bridge); 1895 } 1896 EXPORT_SYMBOL(ocelot_port_bridge_join); 1897 1898 void ocelot_port_bridge_leave(struct ocelot *ocelot, int port, 1899 struct net_device *bridge) 1900 { 1901 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1902 1903 mutex_lock(&ocelot->fwd_domain_lock); 1904 1905 if (!br_vlan_enabled(bridge)) 1906 ocelot_del_vlan_unaware_pvid(ocelot, port, bridge); 1907 1908 ocelot_port->bridge = NULL; 1909 ocelot_port->bridge_num = -1; 1910 1911 ocelot_port_set_pvid(ocelot, port, NULL); 1912 ocelot_port_manage_port_tag(ocelot, port); 1913 ocelot_apply_bridge_fwd_mask(ocelot, false); 1914 1915 mutex_unlock(&ocelot->fwd_domain_lock); 1916 } 1917 EXPORT_SYMBOL(ocelot_port_bridge_leave); 1918 1919 static void ocelot_set_aggr_pgids(struct ocelot *ocelot) 1920 { 1921 unsigned long visited = GENMASK(ocelot->num_phys_ports - 1, 0); 1922 int i, port, lag; 1923 1924 /* Reset destination and aggregation PGIDS */ 1925 for_each_unicast_dest_pgid(ocelot, port) 1926 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 1927 1928 for_each_aggr_pgid(ocelot, i) 1929 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 1930 ANA_PGID_PGID, i); 1931 1932 /* The visited ports bitmask holds the list of ports offloading any 1933 * bonding interface. Initially we mark all these ports as unvisited, 1934 * then every time we visit a port in this bitmask, we know that it is 1935 * the lowest numbered port, i.e. the one whose logical ID == physical 1936 * port ID == LAG ID. So we mark as visited all further ports in the 1937 * bitmask that are offloading the same bonding interface. This way, 1938 * we set up the aggregation PGIDs only once per bonding interface. 1939 */ 1940 for (port = 0; port < ocelot->num_phys_ports; port++) { 1941 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1942 1943 if (!ocelot_port || !ocelot_port->bond) 1944 continue; 1945 1946 visited &= ~BIT(port); 1947 } 1948 1949 /* Now, set PGIDs for each active LAG */ 1950 for (lag = 0; lag < ocelot->num_phys_ports; lag++) { 1951 struct net_device *bond = ocelot->ports[lag]->bond; 1952 int num_active_ports = 0; 1953 unsigned long bond_mask; 1954 u8 aggr_idx[16]; 1955 1956 if (!bond || (visited & BIT(lag))) 1957 continue; 1958 1959 bond_mask = ocelot_get_bond_mask(ocelot, bond); 1960 1961 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) { 1962 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1963 1964 // Destination mask 1965 ocelot_write_rix(ocelot, bond_mask, 1966 ANA_PGID_PGID, port); 1967 1968 if (ocelot_port->lag_tx_active) 1969 aggr_idx[num_active_ports++] = port; 1970 } 1971 1972 for_each_aggr_pgid(ocelot, i) { 1973 u32 ac; 1974 1975 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i); 1976 ac &= ~bond_mask; 1977 /* Don't do division by zero if there was no active 1978 * port. Just make all aggregation codes zero. 1979 */ 1980 if (num_active_ports) 1981 ac |= BIT(aggr_idx[i % num_active_ports]); 1982 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i); 1983 } 1984 1985 /* Mark all ports in the same LAG as visited to avoid applying 1986 * the same config again. 1987 */ 1988 for (port = lag; port < ocelot->num_phys_ports; port++) { 1989 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1990 1991 if (!ocelot_port) 1992 continue; 1993 1994 if (ocelot_port->bond == bond) 1995 visited |= BIT(port); 1996 } 1997 } 1998 } 1999 2000 /* When offloading a bonding interface, the switch ports configured under the 2001 * same bond must have the same logical port ID, equal to the physical port ID 2002 * of the lowest numbered physical port in that bond. Otherwise, in standalone/ 2003 * bridged mode, each port has a logical port ID equal to its physical port ID. 2004 */ 2005 static void ocelot_setup_logical_port_ids(struct ocelot *ocelot) 2006 { 2007 int port; 2008 2009 for (port = 0; port < ocelot->num_phys_ports; port++) { 2010 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2011 struct net_device *bond; 2012 2013 if (!ocelot_port) 2014 continue; 2015 2016 bond = ocelot_port->bond; 2017 if (bond) { 2018 int lag = ocelot_bond_get_id(ocelot, bond); 2019 2020 ocelot_rmw_gix(ocelot, 2021 ANA_PORT_PORT_CFG_PORTID_VAL(lag), 2022 ANA_PORT_PORT_CFG_PORTID_VAL_M, 2023 ANA_PORT_PORT_CFG, port); 2024 } else { 2025 ocelot_rmw_gix(ocelot, 2026 ANA_PORT_PORT_CFG_PORTID_VAL(port), 2027 ANA_PORT_PORT_CFG_PORTID_VAL_M, 2028 ANA_PORT_PORT_CFG, port); 2029 } 2030 } 2031 } 2032 2033 static int ocelot_migrate_mc(struct ocelot *ocelot, struct ocelot_multicast *mc, 2034 unsigned long from_mask, unsigned long to_mask) 2035 { 2036 unsigned char addr[ETH_ALEN]; 2037 struct ocelot_pgid *pgid; 2038 u16 vid = mc->vid; 2039 2040 dev_dbg(ocelot->dev, 2041 "Migrating multicast %pM vid %d from port mask 0x%lx to 0x%lx\n", 2042 mc->addr, mc->vid, from_mask, to_mask); 2043 2044 /* First clean up the current port mask from hardware, because 2045 * we'll be modifying it. 2046 */ 2047 ocelot_pgid_free(ocelot, mc->pgid); 2048 ocelot_encode_ports_to_mdb(addr, mc); 2049 ocelot_mact_forget(ocelot, addr, vid); 2050 2051 mc->ports &= ~from_mask; 2052 mc->ports |= to_mask; 2053 2054 pgid = ocelot_mdb_get_pgid(ocelot, mc); 2055 if (IS_ERR(pgid)) { 2056 dev_err(ocelot->dev, 2057 "Cannot allocate PGID for mdb %pM vid %d\n", 2058 mc->addr, mc->vid); 2059 devm_kfree(ocelot->dev, mc); 2060 return PTR_ERR(pgid); 2061 } 2062 mc->pgid = pgid; 2063 2064 ocelot_encode_ports_to_mdb(addr, mc); 2065 2066 if (mc->entry_type != ENTRYTYPE_MACv4 && 2067 mc->entry_type != ENTRYTYPE_MACv6) 2068 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 2069 pgid->index); 2070 2071 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 2072 mc->entry_type); 2073 } 2074 2075 int ocelot_migrate_mdbs(struct ocelot *ocelot, unsigned long from_mask, 2076 unsigned long to_mask) 2077 { 2078 struct ocelot_multicast *mc; 2079 int err; 2080 2081 list_for_each_entry(mc, &ocelot->multicast, list) { 2082 if (!(mc->ports & from_mask)) 2083 continue; 2084 2085 err = ocelot_migrate_mc(ocelot, mc, from_mask, to_mask); 2086 if (err) 2087 return err; 2088 } 2089 2090 return 0; 2091 } 2092 EXPORT_SYMBOL_GPL(ocelot_migrate_mdbs); 2093 2094 /* Documentation for PORTID_VAL says: 2095 * Logical port number for front port. If port is not a member of a LLAG, 2096 * then PORTID must be set to the physical port number. 2097 * If port is a member of a LLAG, then PORTID must be set to the common 2098 * PORTID_VAL used for all member ports of the LLAG. 2099 * The value must not exceed the number of physical ports on the device. 2100 * 2101 * This means we have little choice but to migrate FDB entries pointing towards 2102 * a logical port when that changes. 2103 */ 2104 static void ocelot_migrate_lag_fdbs(struct ocelot *ocelot, 2105 struct net_device *bond, 2106 int lag) 2107 { 2108 struct ocelot_lag_fdb *fdb; 2109 int err; 2110 2111 lockdep_assert_held(&ocelot->fwd_domain_lock); 2112 2113 list_for_each_entry(fdb, &ocelot->lag_fdbs, list) { 2114 if (fdb->bond != bond) 2115 continue; 2116 2117 err = ocelot_mact_forget(ocelot, fdb->addr, fdb->vid); 2118 if (err) { 2119 dev_err(ocelot->dev, 2120 "failed to delete LAG %s FDB %pM vid %d: %pe\n", 2121 bond->name, fdb->addr, fdb->vid, ERR_PTR(err)); 2122 } 2123 2124 err = ocelot_mact_learn(ocelot, lag, fdb->addr, fdb->vid, 2125 ENTRYTYPE_LOCKED); 2126 if (err) { 2127 dev_err(ocelot->dev, 2128 "failed to migrate LAG %s FDB %pM vid %d: %pe\n", 2129 bond->name, fdb->addr, fdb->vid, ERR_PTR(err)); 2130 } 2131 } 2132 } 2133 2134 int ocelot_port_lag_join(struct ocelot *ocelot, int port, 2135 struct net_device *bond, 2136 struct netdev_lag_upper_info *info, 2137 struct netlink_ext_ack *extack) 2138 { 2139 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 2140 NL_SET_ERR_MSG_MOD(extack, 2141 "Can only offload LAG using hash TX type"); 2142 return -EOPNOTSUPP; 2143 } 2144 2145 mutex_lock(&ocelot->fwd_domain_lock); 2146 2147 ocelot->ports[port]->bond = bond; 2148 2149 ocelot_setup_logical_port_ids(ocelot); 2150 ocelot_apply_bridge_fwd_mask(ocelot, true); 2151 ocelot_set_aggr_pgids(ocelot); 2152 2153 mutex_unlock(&ocelot->fwd_domain_lock); 2154 2155 return 0; 2156 } 2157 EXPORT_SYMBOL(ocelot_port_lag_join); 2158 2159 void ocelot_port_lag_leave(struct ocelot *ocelot, int port, 2160 struct net_device *bond) 2161 { 2162 int old_lag_id, new_lag_id; 2163 2164 mutex_lock(&ocelot->fwd_domain_lock); 2165 2166 old_lag_id = ocelot_bond_get_id(ocelot, bond); 2167 2168 ocelot->ports[port]->bond = NULL; 2169 2170 ocelot_setup_logical_port_ids(ocelot); 2171 ocelot_apply_bridge_fwd_mask(ocelot, false); 2172 ocelot_set_aggr_pgids(ocelot); 2173 2174 new_lag_id = ocelot_bond_get_id(ocelot, bond); 2175 2176 if (new_lag_id >= 0 && old_lag_id != new_lag_id) 2177 ocelot_migrate_lag_fdbs(ocelot, bond, new_lag_id); 2178 2179 mutex_unlock(&ocelot->fwd_domain_lock); 2180 } 2181 EXPORT_SYMBOL(ocelot_port_lag_leave); 2182 2183 void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active) 2184 { 2185 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2186 2187 mutex_lock(&ocelot->fwd_domain_lock); 2188 2189 ocelot_port->lag_tx_active = lag_tx_active; 2190 2191 /* Rebalance the LAGs */ 2192 ocelot_set_aggr_pgids(ocelot); 2193 2194 mutex_unlock(&ocelot->fwd_domain_lock); 2195 } 2196 EXPORT_SYMBOL(ocelot_port_lag_change); 2197 2198 int ocelot_lag_fdb_add(struct ocelot *ocelot, struct net_device *bond, 2199 const unsigned char *addr, u16 vid, 2200 const struct net_device *bridge) 2201 { 2202 struct ocelot_lag_fdb *fdb; 2203 int lag, err; 2204 2205 fdb = kzalloc(sizeof(*fdb), GFP_KERNEL); 2206 if (!fdb) 2207 return -ENOMEM; 2208 2209 mutex_lock(&ocelot->fwd_domain_lock); 2210 2211 if (!vid) 2212 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 2213 2214 ether_addr_copy(fdb->addr, addr); 2215 fdb->vid = vid; 2216 fdb->bond = bond; 2217 2218 lag = ocelot_bond_get_id(ocelot, bond); 2219 2220 err = ocelot_mact_learn(ocelot, lag, addr, vid, ENTRYTYPE_LOCKED); 2221 if (err) { 2222 mutex_unlock(&ocelot->fwd_domain_lock); 2223 kfree(fdb); 2224 return err; 2225 } 2226 2227 list_add_tail(&fdb->list, &ocelot->lag_fdbs); 2228 mutex_unlock(&ocelot->fwd_domain_lock); 2229 2230 return 0; 2231 } 2232 EXPORT_SYMBOL_GPL(ocelot_lag_fdb_add); 2233 2234 int ocelot_lag_fdb_del(struct ocelot *ocelot, struct net_device *bond, 2235 const unsigned char *addr, u16 vid, 2236 const struct net_device *bridge) 2237 { 2238 struct ocelot_lag_fdb *fdb, *tmp; 2239 2240 mutex_lock(&ocelot->fwd_domain_lock); 2241 2242 if (!vid) 2243 vid = ocelot_vlan_unaware_pvid(ocelot, bridge); 2244 2245 list_for_each_entry_safe(fdb, tmp, &ocelot->lag_fdbs, list) { 2246 if (!ether_addr_equal(fdb->addr, addr) || fdb->vid != vid || 2247 fdb->bond != bond) 2248 continue; 2249 2250 ocelot_mact_forget(ocelot, addr, vid); 2251 list_del(&fdb->list); 2252 mutex_unlock(&ocelot->fwd_domain_lock); 2253 kfree(fdb); 2254 2255 return 0; 2256 } 2257 2258 mutex_unlock(&ocelot->fwd_domain_lock); 2259 2260 return -ENOENT; 2261 } 2262 EXPORT_SYMBOL_GPL(ocelot_lag_fdb_del); 2263 2264 /* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu. 2265 * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG. 2266 * In the special case that it's the NPI port that we're configuring, the 2267 * length of the tag and optional prefix needs to be accounted for privately, 2268 * in order to be able to sustain communication at the requested @sdu. 2269 */ 2270 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu) 2271 { 2272 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2273 int maxlen = sdu + ETH_HLEN + ETH_FCS_LEN; 2274 int pause_start, pause_stop; 2275 int atop, atop_tot; 2276 2277 if (port == ocelot->npi) { 2278 maxlen += OCELOT_TAG_LEN; 2279 2280 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT) 2281 maxlen += OCELOT_SHORT_PREFIX_LEN; 2282 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG) 2283 maxlen += OCELOT_LONG_PREFIX_LEN; 2284 } 2285 2286 ocelot_port_writel(ocelot_port, maxlen, DEV_MAC_MAXLEN_CFG); 2287 2288 /* Set Pause watermark hysteresis */ 2289 pause_start = 6 * maxlen / OCELOT_BUFFER_CELL_SZ; 2290 pause_stop = 4 * maxlen / OCELOT_BUFFER_CELL_SZ; 2291 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_START, 2292 pause_start); 2293 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_STOP, 2294 pause_stop); 2295 2296 /* Tail dropping watermarks */ 2297 atop_tot = (ocelot->packet_buffer_size - 9 * maxlen) / 2298 OCELOT_BUFFER_CELL_SZ; 2299 atop = (9 * maxlen) / OCELOT_BUFFER_CELL_SZ; 2300 ocelot_write_rix(ocelot, ocelot->ops->wm_enc(atop), SYS_ATOP, port); 2301 ocelot_write(ocelot, ocelot->ops->wm_enc(atop_tot), SYS_ATOP_TOT_CFG); 2302 } 2303 EXPORT_SYMBOL(ocelot_port_set_maxlen); 2304 2305 int ocelot_get_max_mtu(struct ocelot *ocelot, int port) 2306 { 2307 int max_mtu = 65535 - ETH_HLEN - ETH_FCS_LEN; 2308 2309 if (port == ocelot->npi) { 2310 max_mtu -= OCELOT_TAG_LEN; 2311 2312 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT) 2313 max_mtu -= OCELOT_SHORT_PREFIX_LEN; 2314 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG) 2315 max_mtu -= OCELOT_LONG_PREFIX_LEN; 2316 } 2317 2318 return max_mtu; 2319 } 2320 EXPORT_SYMBOL(ocelot_get_max_mtu); 2321 2322 static void ocelot_port_set_learning(struct ocelot *ocelot, int port, 2323 bool enabled) 2324 { 2325 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2326 u32 val = 0; 2327 2328 if (enabled) 2329 val = ANA_PORT_PORT_CFG_LEARN_ENA; 2330 2331 ocelot_rmw_gix(ocelot, val, ANA_PORT_PORT_CFG_LEARN_ENA, 2332 ANA_PORT_PORT_CFG, port); 2333 2334 ocelot_port->learn_ena = enabled; 2335 } 2336 2337 static void ocelot_port_set_ucast_flood(struct ocelot *ocelot, int port, 2338 bool enabled) 2339 { 2340 u32 val = 0; 2341 2342 if (enabled) 2343 val = BIT(port); 2344 2345 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_UC); 2346 } 2347 2348 static void ocelot_port_set_mcast_flood(struct ocelot *ocelot, int port, 2349 bool enabled) 2350 { 2351 u32 val = 0; 2352 2353 if (enabled) 2354 val = BIT(port); 2355 2356 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MC); 2357 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MCIPV4); 2358 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MCIPV6); 2359 } 2360 2361 static void ocelot_port_set_bcast_flood(struct ocelot *ocelot, int port, 2362 bool enabled) 2363 { 2364 u32 val = 0; 2365 2366 if (enabled) 2367 val = BIT(port); 2368 2369 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_BC); 2370 } 2371 2372 int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port, 2373 struct switchdev_brport_flags flags) 2374 { 2375 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 2376 BR_BCAST_FLOOD)) 2377 return -EINVAL; 2378 2379 return 0; 2380 } 2381 EXPORT_SYMBOL(ocelot_port_pre_bridge_flags); 2382 2383 void ocelot_port_bridge_flags(struct ocelot *ocelot, int port, 2384 struct switchdev_brport_flags flags) 2385 { 2386 if (flags.mask & BR_LEARNING) 2387 ocelot_port_set_learning(ocelot, port, 2388 !!(flags.val & BR_LEARNING)); 2389 2390 if (flags.mask & BR_FLOOD) 2391 ocelot_port_set_ucast_flood(ocelot, port, 2392 !!(flags.val & BR_FLOOD)); 2393 2394 if (flags.mask & BR_MCAST_FLOOD) 2395 ocelot_port_set_mcast_flood(ocelot, port, 2396 !!(flags.val & BR_MCAST_FLOOD)); 2397 2398 if (flags.mask & BR_BCAST_FLOOD) 2399 ocelot_port_set_bcast_flood(ocelot, port, 2400 !!(flags.val & BR_BCAST_FLOOD)); 2401 } 2402 EXPORT_SYMBOL(ocelot_port_bridge_flags); 2403 2404 int ocelot_port_get_default_prio(struct ocelot *ocelot, int port) 2405 { 2406 int val = ocelot_read_gix(ocelot, ANA_PORT_QOS_CFG, port); 2407 2408 return ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_X(val); 2409 } 2410 EXPORT_SYMBOL_GPL(ocelot_port_get_default_prio); 2411 2412 int ocelot_port_set_default_prio(struct ocelot *ocelot, int port, u8 prio) 2413 { 2414 if (prio >= OCELOT_NUM_TC) 2415 return -ERANGE; 2416 2417 ocelot_rmw_gix(ocelot, 2418 ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL(prio), 2419 ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_M, 2420 ANA_PORT_QOS_CFG, 2421 port); 2422 2423 return 0; 2424 } 2425 EXPORT_SYMBOL_GPL(ocelot_port_set_default_prio); 2426 2427 int ocelot_port_get_dscp_prio(struct ocelot *ocelot, int port, u8 dscp) 2428 { 2429 int qos_cfg = ocelot_read_gix(ocelot, ANA_PORT_QOS_CFG, port); 2430 int dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, dscp); 2431 2432 /* Return error if DSCP prioritization isn't enabled */ 2433 if (!(qos_cfg & ANA_PORT_QOS_CFG_QOS_DSCP_ENA)) 2434 return -EOPNOTSUPP; 2435 2436 if (qos_cfg & ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA) { 2437 dscp = ANA_DSCP_CFG_DSCP_TRANSLATE_VAL_X(dscp_cfg); 2438 /* Re-read ANA_DSCP_CFG for the translated DSCP */ 2439 dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, dscp); 2440 } 2441 2442 /* If the DSCP value is not trusted, the QoS classification falls back 2443 * to VLAN PCP or port-based default. 2444 */ 2445 if (!(dscp_cfg & ANA_DSCP_CFG_DSCP_TRUST_ENA)) 2446 return -EOPNOTSUPP; 2447 2448 return ANA_DSCP_CFG_QOS_DSCP_VAL_X(dscp_cfg); 2449 } 2450 EXPORT_SYMBOL_GPL(ocelot_port_get_dscp_prio); 2451 2452 int ocelot_port_add_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio) 2453 { 2454 int mask, val; 2455 2456 if (prio >= OCELOT_NUM_TC) 2457 return -ERANGE; 2458 2459 /* There is at least one app table priority (this one), so we need to 2460 * make sure DSCP prioritization is enabled on the port. 2461 * Also make sure DSCP translation is disabled 2462 * (dcbnl doesn't support it). 2463 */ 2464 mask = ANA_PORT_QOS_CFG_QOS_DSCP_ENA | 2465 ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA; 2466 2467 ocelot_rmw_gix(ocelot, ANA_PORT_QOS_CFG_QOS_DSCP_ENA, mask, 2468 ANA_PORT_QOS_CFG, port); 2469 2470 /* Trust this DSCP value and map it to the given QoS class */ 2471 val = ANA_DSCP_CFG_DSCP_TRUST_ENA | ANA_DSCP_CFG_QOS_DSCP_VAL(prio); 2472 2473 ocelot_write_rix(ocelot, val, ANA_DSCP_CFG, dscp); 2474 2475 return 0; 2476 } 2477 EXPORT_SYMBOL_GPL(ocelot_port_add_dscp_prio); 2478 2479 int ocelot_port_del_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio) 2480 { 2481 int dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, dscp); 2482 int mask, i; 2483 2484 /* During a "dcb app replace" command, the new app table entry will be 2485 * added first, then the old one will be deleted. But the hardware only 2486 * supports one QoS class per DSCP value (duh), so if we blindly delete 2487 * the app table entry for this DSCP value, we end up deleting the 2488 * entry with the new priority. Avoid that by checking whether user 2489 * space wants to delete the priority which is currently configured, or 2490 * something else which is no longer current. 2491 */ 2492 if (ANA_DSCP_CFG_QOS_DSCP_VAL_X(dscp_cfg) != prio) 2493 return 0; 2494 2495 /* Untrust this DSCP value */ 2496 ocelot_write_rix(ocelot, 0, ANA_DSCP_CFG, dscp); 2497 2498 for (i = 0; i < 64; i++) { 2499 int dscp_cfg = ocelot_read_rix(ocelot, ANA_DSCP_CFG, i); 2500 2501 /* There are still app table entries on the port, so we need to 2502 * keep DSCP enabled, nothing to do. 2503 */ 2504 if (dscp_cfg & ANA_DSCP_CFG_DSCP_TRUST_ENA) 2505 return 0; 2506 } 2507 2508 /* Disable DSCP QoS classification if there isn't any trusted 2509 * DSCP value left. 2510 */ 2511 mask = ANA_PORT_QOS_CFG_QOS_DSCP_ENA | 2512 ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA; 2513 2514 ocelot_rmw_gix(ocelot, 0, mask, ANA_PORT_QOS_CFG, port); 2515 2516 return 0; 2517 } 2518 EXPORT_SYMBOL_GPL(ocelot_port_del_dscp_prio); 2519 2520 struct ocelot_mirror *ocelot_mirror_get(struct ocelot *ocelot, int to, 2521 struct netlink_ext_ack *extack) 2522 { 2523 struct ocelot_mirror *m = ocelot->mirror; 2524 2525 if (m) { 2526 if (m->to != to) { 2527 NL_SET_ERR_MSG_MOD(extack, 2528 "Mirroring already configured towards different egress port"); 2529 return ERR_PTR(-EBUSY); 2530 } 2531 2532 refcount_inc(&m->refcount); 2533 return m; 2534 } 2535 2536 m = kzalloc(sizeof(*m), GFP_KERNEL); 2537 if (!m) 2538 return ERR_PTR(-ENOMEM); 2539 2540 m->to = to; 2541 refcount_set(&m->refcount, 1); 2542 ocelot->mirror = m; 2543 2544 /* Program the mirror port to hardware */ 2545 ocelot_write(ocelot, BIT(to), ANA_MIRRORPORTS); 2546 2547 return m; 2548 } 2549 2550 void ocelot_mirror_put(struct ocelot *ocelot) 2551 { 2552 struct ocelot_mirror *m = ocelot->mirror; 2553 2554 if (!refcount_dec_and_test(&m->refcount)) 2555 return; 2556 2557 ocelot_write(ocelot, 0, ANA_MIRRORPORTS); 2558 ocelot->mirror = NULL; 2559 kfree(m); 2560 } 2561 2562 int ocelot_port_mirror_add(struct ocelot *ocelot, int from, int to, 2563 bool ingress, struct netlink_ext_ack *extack) 2564 { 2565 struct ocelot_mirror *m = ocelot_mirror_get(ocelot, to, extack); 2566 2567 if (IS_ERR(m)) 2568 return PTR_ERR(m); 2569 2570 if (ingress) { 2571 ocelot_rmw_gix(ocelot, ANA_PORT_PORT_CFG_SRC_MIRROR_ENA, 2572 ANA_PORT_PORT_CFG_SRC_MIRROR_ENA, 2573 ANA_PORT_PORT_CFG, from); 2574 } else { 2575 ocelot_rmw(ocelot, BIT(from), BIT(from), 2576 ANA_EMIRRORPORTS); 2577 } 2578 2579 return 0; 2580 } 2581 EXPORT_SYMBOL_GPL(ocelot_port_mirror_add); 2582 2583 void ocelot_port_mirror_del(struct ocelot *ocelot, int from, bool ingress) 2584 { 2585 if (ingress) { 2586 ocelot_rmw_gix(ocelot, 0, ANA_PORT_PORT_CFG_SRC_MIRROR_ENA, 2587 ANA_PORT_PORT_CFG, from); 2588 } else { 2589 ocelot_rmw(ocelot, 0, BIT(from), ANA_EMIRRORPORTS); 2590 } 2591 2592 ocelot_mirror_put(ocelot); 2593 } 2594 EXPORT_SYMBOL_GPL(ocelot_port_mirror_del); 2595 2596 void ocelot_init_port(struct ocelot *ocelot, int port) 2597 { 2598 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2599 2600 skb_queue_head_init(&ocelot_port->tx_skbs); 2601 2602 /* Basic L2 initialization */ 2603 2604 /* Set MAC IFG Gaps 2605 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0 2606 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5 2607 */ 2608 ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5), 2609 DEV_MAC_IFG_CFG); 2610 2611 /* Load seed (0) and set MAC HDX late collision */ 2612 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) | 2613 DEV_MAC_HDX_CFG_SEED_LOAD, 2614 DEV_MAC_HDX_CFG); 2615 mdelay(1); 2616 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67), 2617 DEV_MAC_HDX_CFG); 2618 2619 /* Set Max Length and maximum tags allowed */ 2620 ocelot_port_set_maxlen(ocelot, port, ETH_DATA_LEN); 2621 ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) | 2622 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA | 2623 DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA | 2624 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, 2625 DEV_MAC_TAGS_CFG); 2626 2627 /* Set SMAC of Pause frame (00:00:00:00:00:00) */ 2628 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG); 2629 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG); 2630 2631 /* Enable transmission of pause frames */ 2632 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1); 2633 2634 /* Drop frames with multicast source address */ 2635 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 2636 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 2637 ANA_PORT_DROP_CFG, port); 2638 2639 /* Set default VLAN and tag type to 8021Q. */ 2640 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q), 2641 REW_PORT_VLAN_CFG_PORT_TPID_M, 2642 REW_PORT_VLAN_CFG, port); 2643 2644 /* Disable source address learning for standalone mode */ 2645 ocelot_port_set_learning(ocelot, port, false); 2646 2647 /* Set the port's initial logical port ID value, enable receiving 2648 * frames on it, and configure the MAC address learning type to 2649 * automatic. 2650 */ 2651 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO | 2652 ANA_PORT_PORT_CFG_RECV_ENA | 2653 ANA_PORT_PORT_CFG_PORTID_VAL(port), 2654 ANA_PORT_PORT_CFG, port); 2655 2656 /* Enable vcap lookups */ 2657 ocelot_vcap_enable(ocelot, port); 2658 } 2659 EXPORT_SYMBOL(ocelot_init_port); 2660 2661 /* Configure and enable the CPU port module, which is a set of queues 2662 * accessible through register MMIO, frame DMA or Ethernet (in case 2663 * NPI mode is used). 2664 */ 2665 static void ocelot_cpu_port_init(struct ocelot *ocelot) 2666 { 2667 int cpu = ocelot->num_phys_ports; 2668 2669 /* The unicast destination PGID for the CPU port module is unused */ 2670 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu); 2671 /* Instead set up a multicast destination PGID for traffic copied to 2672 * the CPU. Whitelisted MAC addresses like the port netdevice MAC 2673 * addresses will be copied to the CPU via this PGID. 2674 */ 2675 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU); 2676 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA | 2677 ANA_PORT_PORT_CFG_PORTID_VAL(cpu), 2678 ANA_PORT_PORT_CFG, cpu); 2679 2680 /* Enable CPU port module */ 2681 ocelot_fields_write(ocelot, cpu, QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 2682 /* CPU port Injection/Extraction configuration */ 2683 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_XTR_HDR, 2684 OCELOT_TAG_PREFIX_NONE); 2685 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_INJ_HDR, 2686 OCELOT_TAG_PREFIX_NONE); 2687 2688 /* Configure the CPU port to be VLAN aware */ 2689 ocelot_write_gix(ocelot, 2690 ANA_PORT_VLAN_CFG_VLAN_VID(OCELOT_STANDALONE_PVID) | 2691 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 2692 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1), 2693 ANA_PORT_VLAN_CFG, cpu); 2694 } 2695 2696 static void ocelot_detect_features(struct ocelot *ocelot) 2697 { 2698 int mmgt, eq_ctrl; 2699 2700 /* For Ocelot, Felix, Seville, Serval etc, SYS:MMGT:MMGT:FREECNT holds 2701 * the number of 240-byte free memory words (aka 4-cell chunks) and not 2702 * 192 bytes as the documentation incorrectly says. 2703 */ 2704 mmgt = ocelot_read(ocelot, SYS_MMGT); 2705 ocelot->packet_buffer_size = 240 * SYS_MMGT_FREECNT(mmgt); 2706 2707 eq_ctrl = ocelot_read(ocelot, QSYS_EQ_CTRL); 2708 ocelot->num_frame_refs = QSYS_MMGT_EQ_CTRL_FP_FREE_CNT(eq_ctrl); 2709 } 2710 2711 int ocelot_init(struct ocelot *ocelot) 2712 { 2713 int i, ret; 2714 u32 port; 2715 2716 if (ocelot->ops->reset) { 2717 ret = ocelot->ops->reset(ocelot); 2718 if (ret) { 2719 dev_err(ocelot->dev, "Switch reset failed\n"); 2720 return ret; 2721 } 2722 } 2723 2724 mutex_init(&ocelot->ptp_lock); 2725 mutex_init(&ocelot->mact_lock); 2726 mutex_init(&ocelot->fwd_domain_lock); 2727 mutex_init(&ocelot->tas_lock); 2728 spin_lock_init(&ocelot->ptp_clock_lock); 2729 spin_lock_init(&ocelot->ts_id_lock); 2730 2731 ocelot->owq = alloc_ordered_workqueue("ocelot-owq", 0); 2732 if (!ocelot->owq) 2733 return -ENOMEM; 2734 2735 ret = ocelot_stats_init(ocelot); 2736 if (ret) { 2737 destroy_workqueue(ocelot->owq); 2738 return ret; 2739 } 2740 2741 INIT_LIST_HEAD(&ocelot->multicast); 2742 INIT_LIST_HEAD(&ocelot->pgids); 2743 INIT_LIST_HEAD(&ocelot->vlans); 2744 INIT_LIST_HEAD(&ocelot->lag_fdbs); 2745 ocelot_detect_features(ocelot); 2746 ocelot_mact_init(ocelot); 2747 ocelot_vlan_init(ocelot); 2748 ocelot_vcap_init(ocelot); 2749 ocelot_cpu_port_init(ocelot); 2750 2751 if (ocelot->ops->psfp_init) 2752 ocelot->ops->psfp_init(ocelot); 2753 2754 for (port = 0; port < ocelot->num_phys_ports; port++) { 2755 /* Clear all counters (5 groups) */ 2756 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) | 2757 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f), 2758 SYS_STAT_CFG); 2759 } 2760 2761 /* Only use S-Tag */ 2762 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG); 2763 2764 /* Aggregation mode */ 2765 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA | 2766 ANA_AGGR_CFG_AC_DMAC_ENA | 2767 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA | 2768 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA | 2769 ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA | 2770 ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA, 2771 ANA_AGGR_CFG); 2772 2773 /* Set MAC age time to default value. The entry is aged after 2774 * 2*AGE_PERIOD 2775 */ 2776 ocelot_write(ocelot, 2777 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ), 2778 ANA_AUTOAGE); 2779 2780 /* Disable learning for frames discarded by VLAN ingress filtering */ 2781 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1); 2782 2783 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */ 2784 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA | 2785 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING); 2786 2787 /* Setup flooding PGIDs */ 2788 for (i = 0; i < ocelot->num_flooding_pgids; i++) 2789 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) | 2790 ANA_FLOODING_FLD_BROADCAST(PGID_BC) | 2791 ANA_FLOODING_FLD_UNICAST(PGID_UC), 2792 ANA_FLOODING, i); 2793 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) | 2794 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) | 2795 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) | 2796 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC), 2797 ANA_FLOODING_IPMC); 2798 2799 for (port = 0; port < ocelot->num_phys_ports; port++) { 2800 /* Transmit the frame to the local port. */ 2801 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 2802 /* Do not forward BPDU frames to the front ports. */ 2803 ocelot_write_gix(ocelot, 2804 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff), 2805 ANA_PORT_CPU_FWD_BPDU_CFG, 2806 port); 2807 /* Ensure bridging is disabled */ 2808 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port); 2809 } 2810 2811 for_each_nonreserved_multicast_dest_pgid(ocelot, i) { 2812 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0)); 2813 2814 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 2815 } 2816 2817 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_BLACKHOLE); 2818 2819 /* Allow broadcast and unknown L2 multicast to the CPU. */ 2820 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2821 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2822 ANA_PGID_PGID, PGID_MC); 2823 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2824 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2825 ANA_PGID_PGID, PGID_BC); 2826 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4); 2827 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6); 2828 2829 /* Allow manual injection via DEVCPU_QS registers, and byte swap these 2830 * registers endianness. 2831 */ 2832 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP | 2833 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0); 2834 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP | 2835 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0); 2836 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) | 2837 ANA_CPUQ_CFG_CPUQ_LRN(2) | 2838 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) | 2839 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) | 2840 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) | 2841 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) | 2842 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) | 2843 ANA_CPUQ_CFG_CPUQ_IGMP(6) | 2844 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG); 2845 for (i = 0; i < 16; i++) 2846 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) | 2847 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6), 2848 ANA_CPUQ_8021_CFG, i); 2849 2850 return 0; 2851 } 2852 EXPORT_SYMBOL(ocelot_init); 2853 2854 void ocelot_deinit(struct ocelot *ocelot) 2855 { 2856 ocelot_stats_deinit(ocelot); 2857 destroy_workqueue(ocelot->owq); 2858 } 2859 EXPORT_SYMBOL(ocelot_deinit); 2860 2861 void ocelot_deinit_port(struct ocelot *ocelot, int port) 2862 { 2863 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2864 2865 skb_queue_purge(&ocelot_port->tx_skbs); 2866 } 2867 EXPORT_SYMBOL(ocelot_deinit_port); 2868 2869 MODULE_LICENSE("Dual MIT/GPL"); 2870