1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7 #include <linux/dsa/ocelot.h> 8 #include <linux/if_bridge.h> 9 #include <soc/mscc/ocelot_vcap.h> 10 #include "ocelot.h" 11 #include "ocelot_vcap.h" 12 13 #define TABLE_UPDATE_SLEEP_US 10 14 #define TABLE_UPDATE_TIMEOUT_US 100000 15 16 struct ocelot_mact_entry { 17 u8 mac[ETH_ALEN]; 18 u16 vid; 19 enum macaccess_entry_type type; 20 }; 21 22 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot) 23 { 24 return ocelot_read(ocelot, ANA_TABLES_MACACCESS); 25 } 26 27 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot) 28 { 29 u32 val; 30 31 return readx_poll_timeout(ocelot_mact_read_macaccess, 32 ocelot, val, 33 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) == 34 MACACCESS_CMD_IDLE, 35 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 36 } 37 38 static void ocelot_mact_select(struct ocelot *ocelot, 39 const unsigned char mac[ETH_ALEN], 40 unsigned int vid) 41 { 42 u32 macl = 0, mach = 0; 43 44 /* Set the MAC address to handle and the vlan associated in a format 45 * understood by the hardware. 46 */ 47 mach |= vid << 16; 48 mach |= mac[0] << 8; 49 mach |= mac[1] << 0; 50 macl |= mac[2] << 24; 51 macl |= mac[3] << 16; 52 macl |= mac[4] << 8; 53 macl |= mac[5] << 0; 54 55 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA); 56 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA); 57 58 } 59 60 int ocelot_mact_learn(struct ocelot *ocelot, int port, 61 const unsigned char mac[ETH_ALEN], 62 unsigned int vid, enum macaccess_entry_type type) 63 { 64 u32 cmd = ANA_TABLES_MACACCESS_VALID | 65 ANA_TABLES_MACACCESS_DEST_IDX(port) | 66 ANA_TABLES_MACACCESS_ENTRYTYPE(type) | 67 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN); 68 unsigned int mc_ports; 69 70 /* Set MAC_CPU_COPY if the CPU port is used by a multicast entry */ 71 if (type == ENTRYTYPE_MACv4) 72 mc_ports = (mac[1] << 8) | mac[2]; 73 else if (type == ENTRYTYPE_MACv6) 74 mc_ports = (mac[0] << 8) | mac[1]; 75 else 76 mc_ports = 0; 77 78 if (mc_ports & BIT(ocelot->num_phys_ports)) 79 cmd |= ANA_TABLES_MACACCESS_MAC_CPU_COPY; 80 81 ocelot_mact_select(ocelot, mac, vid); 82 83 /* Issue a write command */ 84 ocelot_write(ocelot, cmd, ANA_TABLES_MACACCESS); 85 86 return ocelot_mact_wait_for_completion(ocelot); 87 } 88 EXPORT_SYMBOL(ocelot_mact_learn); 89 90 int ocelot_mact_forget(struct ocelot *ocelot, 91 const unsigned char mac[ETH_ALEN], unsigned int vid) 92 { 93 ocelot_mact_select(ocelot, mac, vid); 94 95 /* Issue a forget command */ 96 ocelot_write(ocelot, 97 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET), 98 ANA_TABLES_MACACCESS); 99 100 return ocelot_mact_wait_for_completion(ocelot); 101 } 102 EXPORT_SYMBOL(ocelot_mact_forget); 103 104 static void ocelot_mact_init(struct ocelot *ocelot) 105 { 106 /* Configure the learning mode entries attributes: 107 * - Do not copy the frame to the CPU extraction queues. 108 * - Use the vlan and mac_cpoy for dmac lookup. 109 */ 110 ocelot_rmw(ocelot, 0, 111 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS 112 | ANA_AGENCTRL_LEARN_FWD_KILL 113 | ANA_AGENCTRL_LEARN_IGNORE_VLAN, 114 ANA_AGENCTRL); 115 116 /* Clear the MAC table */ 117 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS); 118 } 119 120 static void ocelot_vcap_enable(struct ocelot *ocelot, int port) 121 { 122 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA | 123 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa), 124 ANA_PORT_VCAP_S2_CFG, port); 125 126 ocelot_write_gix(ocelot, ANA_PORT_VCAP_CFG_S1_ENA, 127 ANA_PORT_VCAP_CFG, port); 128 129 ocelot_rmw_gix(ocelot, REW_PORT_CFG_ES0_EN, 130 REW_PORT_CFG_ES0_EN, 131 REW_PORT_CFG, port); 132 } 133 134 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot) 135 { 136 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS); 137 } 138 139 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot) 140 { 141 u32 val; 142 143 return readx_poll_timeout(ocelot_vlant_read_vlanaccess, 144 ocelot, 145 val, 146 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) == 147 ANA_TABLES_VLANACCESS_CMD_IDLE, 148 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 149 } 150 151 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask) 152 { 153 /* Select the VID to configure */ 154 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid), 155 ANA_TABLES_VLANTIDX); 156 /* Set the vlan port members mask and issue a write command */ 157 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) | 158 ANA_TABLES_VLANACCESS_CMD_WRITE, 159 ANA_TABLES_VLANACCESS); 160 161 return ocelot_vlant_wait_for_completion(ocelot); 162 } 163 164 static void ocelot_port_set_native_vlan(struct ocelot *ocelot, int port, 165 struct ocelot_vlan native_vlan) 166 { 167 struct ocelot_port *ocelot_port = ocelot->ports[port]; 168 u32 val = 0; 169 170 ocelot_port->native_vlan = native_vlan; 171 172 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_VID(native_vlan.vid), 173 REW_PORT_VLAN_CFG_PORT_VID_M, 174 REW_PORT_VLAN_CFG, port); 175 176 if (ocelot_port->vlan_aware) { 177 if (native_vlan.valid) 178 /* Tag all frames except when VID == DEFAULT_VLAN */ 179 val = REW_TAG_CFG_TAG_CFG(1); 180 else 181 /* Tag all frames */ 182 val = REW_TAG_CFG_TAG_CFG(3); 183 } else { 184 /* Port tagging disabled. */ 185 val = REW_TAG_CFG_TAG_CFG(0); 186 } 187 ocelot_rmw_gix(ocelot, val, 188 REW_TAG_CFG_TAG_CFG_M, 189 REW_TAG_CFG, port); 190 } 191 192 /* Default vlan to clasify for untagged frames (may be zero) */ 193 static void ocelot_port_set_pvid(struct ocelot *ocelot, int port, 194 struct ocelot_vlan pvid_vlan) 195 { 196 struct ocelot_port *ocelot_port = ocelot->ports[port]; 197 u32 val = 0; 198 199 ocelot_port->pvid_vlan = pvid_vlan; 200 201 if (!ocelot_port->vlan_aware) 202 pvid_vlan.vid = 0; 203 204 ocelot_rmw_gix(ocelot, 205 ANA_PORT_VLAN_CFG_VLAN_VID(pvid_vlan.vid), 206 ANA_PORT_VLAN_CFG_VLAN_VID_M, 207 ANA_PORT_VLAN_CFG, port); 208 209 /* If there's no pvid, we should drop not only untagged traffic (which 210 * happens automatically), but also 802.1p traffic which gets 211 * classified to VLAN 0, but that is always in our RX filter, so it 212 * would get accepted were it not for this setting. 213 */ 214 if (!pvid_vlan.valid && ocelot_port->vlan_aware) 215 val = ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 216 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA; 217 218 ocelot_rmw_gix(ocelot, val, 219 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 220 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, 221 ANA_PORT_DROP_CFG, port); 222 } 223 224 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, 225 bool vlan_aware) 226 { 227 struct ocelot_vcap_block *block = &ocelot->block[VCAP_IS1]; 228 struct ocelot_port *ocelot_port = ocelot->ports[port]; 229 struct ocelot_vcap_filter *filter; 230 u32 val; 231 232 list_for_each_entry(filter, &block->rules, list) { 233 if (filter->ingress_port_mask & BIT(port) && 234 filter->action.vid_replace_ena) { 235 dev_err(ocelot->dev, 236 "Cannot change VLAN state with vlan modify rules active\n"); 237 return -EBUSY; 238 } 239 } 240 241 ocelot_port->vlan_aware = vlan_aware; 242 243 if (vlan_aware) 244 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 245 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1); 246 else 247 val = 0; 248 ocelot_rmw_gix(ocelot, val, 249 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 250 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M, 251 ANA_PORT_VLAN_CFG, port); 252 253 ocelot_port_set_pvid(ocelot, port, ocelot_port->pvid_vlan); 254 ocelot_port_set_native_vlan(ocelot, port, ocelot_port->native_vlan); 255 256 return 0; 257 } 258 EXPORT_SYMBOL(ocelot_port_vlan_filtering); 259 260 int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid, 261 bool untagged) 262 { 263 struct ocelot_port *ocelot_port = ocelot->ports[port]; 264 265 /* Deny changing the native VLAN, but always permit deleting it */ 266 if (untagged && ocelot_port->native_vlan.vid != vid && 267 ocelot_port->native_vlan.valid) { 268 dev_err(ocelot->dev, 269 "Port already has a native VLAN: %d\n", 270 ocelot_port->native_vlan.vid); 271 return -EBUSY; 272 } 273 274 return 0; 275 } 276 EXPORT_SYMBOL(ocelot_vlan_prepare); 277 278 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid, 279 bool untagged) 280 { 281 int ret; 282 283 /* Make the port a member of the VLAN */ 284 ocelot->vlan_mask[vid] |= BIT(port); 285 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 286 if (ret) 287 return ret; 288 289 /* Default ingress vlan classification */ 290 if (pvid) { 291 struct ocelot_vlan pvid_vlan; 292 293 pvid_vlan.vid = vid; 294 pvid_vlan.valid = true; 295 ocelot_port_set_pvid(ocelot, port, pvid_vlan); 296 } 297 298 /* Untagged egress vlan clasification */ 299 if (untagged) { 300 struct ocelot_vlan native_vlan; 301 302 native_vlan.vid = vid; 303 native_vlan.valid = true; 304 ocelot_port_set_native_vlan(ocelot, port, native_vlan); 305 } 306 307 return 0; 308 } 309 EXPORT_SYMBOL(ocelot_vlan_add); 310 311 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid) 312 { 313 struct ocelot_port *ocelot_port = ocelot->ports[port]; 314 int ret; 315 316 /* Stop the port from being a member of the vlan */ 317 ocelot->vlan_mask[vid] &= ~BIT(port); 318 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 319 if (ret) 320 return ret; 321 322 /* Ingress */ 323 if (ocelot_port->pvid_vlan.vid == vid) { 324 struct ocelot_vlan pvid_vlan = {0}; 325 326 ocelot_port_set_pvid(ocelot, port, pvid_vlan); 327 } 328 329 /* Egress */ 330 if (ocelot_port->native_vlan.vid == vid) { 331 struct ocelot_vlan native_vlan = {0}; 332 333 ocelot_port_set_native_vlan(ocelot, port, native_vlan); 334 } 335 336 return 0; 337 } 338 EXPORT_SYMBOL(ocelot_vlan_del); 339 340 static void ocelot_vlan_init(struct ocelot *ocelot) 341 { 342 u16 port, vid; 343 344 /* Clear VLAN table, by default all ports are members of all VLANs */ 345 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT, 346 ANA_TABLES_VLANACCESS); 347 ocelot_vlant_wait_for_completion(ocelot); 348 349 /* Configure the port VLAN memberships */ 350 for (vid = 1; vid < VLAN_N_VID; vid++) { 351 ocelot->vlan_mask[vid] = 0; 352 ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 353 } 354 355 /* Because VLAN filtering is enabled, we need VID 0 to get untagged 356 * traffic. It is added automatically if 8021q module is loaded, but 357 * we can't rely on it since module may be not loaded. 358 */ 359 ocelot->vlan_mask[0] = GENMASK(ocelot->num_phys_ports - 1, 0); 360 ocelot_vlant_set_mask(ocelot, 0, ocelot->vlan_mask[0]); 361 362 /* Set vlan ingress filter mask to all ports but the CPU port by 363 * default. 364 */ 365 ocelot_write(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 366 ANA_VLANMASK); 367 368 for (port = 0; port < ocelot->num_phys_ports; port++) { 369 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port); 370 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port); 371 } 372 } 373 374 static u32 ocelot_read_eq_avail(struct ocelot *ocelot, int port) 375 { 376 return ocelot_read_rix(ocelot, QSYS_SW_STATUS, port); 377 } 378 379 int ocelot_port_flush(struct ocelot *ocelot, int port) 380 { 381 int err, val; 382 383 /* Disable dequeuing from the egress queues */ 384 ocelot_rmw_rix(ocelot, QSYS_PORT_MODE_DEQUEUE_DIS, 385 QSYS_PORT_MODE_DEQUEUE_DIS, 386 QSYS_PORT_MODE, port); 387 388 /* Disable flow control */ 389 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 0); 390 391 /* Disable priority flow control */ 392 ocelot_fields_write(ocelot, port, 393 QSYS_SWITCH_PORT_MODE_TX_PFC_ENA, 0); 394 395 /* Wait at least the time it takes to receive a frame of maximum length 396 * at the port. 397 * Worst-case delays for 10 kilobyte jumbo frames are: 398 * 8 ms on a 10M port 399 * 800 μs on a 100M port 400 * 80 μs on a 1G port 401 * 32 μs on a 2.5G port 402 */ 403 usleep_range(8000, 10000); 404 405 /* Disable half duplex backpressure. */ 406 ocelot_rmw_rix(ocelot, 0, SYS_FRONT_PORT_MODE_HDX_MODE, 407 SYS_FRONT_PORT_MODE, port); 408 409 /* Flush the queues associated with the port. */ 410 ocelot_rmw_gix(ocelot, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG_FLUSH_ENA, 411 REW_PORT_CFG, port); 412 413 /* Enable dequeuing from the egress queues. */ 414 ocelot_rmw_rix(ocelot, 0, QSYS_PORT_MODE_DEQUEUE_DIS, QSYS_PORT_MODE, 415 port); 416 417 /* Wait until flushing is complete. */ 418 err = read_poll_timeout(ocelot_read_eq_avail, val, !val, 419 100, 2000000, false, ocelot, port); 420 421 /* Clear flushing again. */ 422 ocelot_rmw_gix(ocelot, 0, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG, port); 423 424 return err; 425 } 426 EXPORT_SYMBOL(ocelot_port_flush); 427 428 void ocelot_adjust_link(struct ocelot *ocelot, int port, 429 struct phy_device *phydev) 430 { 431 struct ocelot_port *ocelot_port = ocelot->ports[port]; 432 int speed, mode = 0; 433 434 switch (phydev->speed) { 435 case SPEED_10: 436 speed = OCELOT_SPEED_10; 437 break; 438 case SPEED_100: 439 speed = OCELOT_SPEED_100; 440 break; 441 case SPEED_1000: 442 speed = OCELOT_SPEED_1000; 443 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 444 break; 445 case SPEED_2500: 446 speed = OCELOT_SPEED_2500; 447 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 448 break; 449 default: 450 dev_err(ocelot->dev, "Unsupported PHY speed on port %d: %d\n", 451 port, phydev->speed); 452 return; 453 } 454 455 phy_print_status(phydev); 456 457 if (!phydev->link) 458 return; 459 460 /* Only full duplex supported for now */ 461 ocelot_port_writel(ocelot_port, DEV_MAC_MODE_CFG_FDX_ENA | 462 mode, DEV_MAC_MODE_CFG); 463 464 /* Disable HDX fast control */ 465 ocelot_port_writel(ocelot_port, DEV_PORT_MISC_HDX_FAST_DIS, 466 DEV_PORT_MISC); 467 468 /* SGMII only for now */ 469 ocelot_port_writel(ocelot_port, PCS1G_MODE_CFG_SGMII_MODE_ENA, 470 PCS1G_MODE_CFG); 471 ocelot_port_writel(ocelot_port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG); 472 473 /* Enable PCS */ 474 ocelot_port_writel(ocelot_port, PCS1G_CFG_PCS_ENA, PCS1G_CFG); 475 476 /* No aneg on SGMII */ 477 ocelot_port_writel(ocelot_port, 0, PCS1G_ANEG_CFG); 478 479 /* No loopback */ 480 ocelot_port_writel(ocelot_port, 0, PCS1G_LB_CFG); 481 482 /* Enable MAC module */ 483 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA | 484 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG); 485 486 /* Take MAC, Port, Phy (intern) and PCS (SGMII/Serdes) clock out of 487 * reset */ 488 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(speed), 489 DEV_CLOCK_CFG); 490 491 /* No PFC */ 492 ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed), 493 ANA_PFC_PFC_CFG, port); 494 495 /* Core: Enable port for frame transfer */ 496 ocelot_fields_write(ocelot, port, 497 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 498 499 /* Flow control */ 500 ocelot_write_rix(ocelot, SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) | 501 SYS_MAC_FC_CFG_RX_FC_ENA | SYS_MAC_FC_CFG_TX_FC_ENA | 502 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA | 503 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) | 504 SYS_MAC_FC_CFG_FC_LINK_SPEED(speed), 505 SYS_MAC_FC_CFG, port); 506 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port); 507 } 508 EXPORT_SYMBOL(ocelot_adjust_link); 509 510 void ocelot_port_enable(struct ocelot *ocelot, int port, 511 struct phy_device *phy) 512 { 513 /* Enable receiving frames on the port, and activate auto-learning of 514 * MAC addresses. 515 */ 516 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO | 517 ANA_PORT_PORT_CFG_RECV_ENA | 518 ANA_PORT_PORT_CFG_PORTID_VAL(port), 519 ANA_PORT_PORT_CFG, port); 520 } 521 EXPORT_SYMBOL(ocelot_port_enable); 522 523 void ocelot_port_disable(struct ocelot *ocelot, int port) 524 { 525 struct ocelot_port *ocelot_port = ocelot->ports[port]; 526 527 ocelot_port_writel(ocelot_port, 0, DEV_MAC_ENA_CFG); 528 ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0); 529 } 530 EXPORT_SYMBOL(ocelot_port_disable); 531 532 void ocelot_port_add_txtstamp_skb(struct ocelot *ocelot, int port, 533 struct sk_buff *clone) 534 { 535 struct ocelot_port *ocelot_port = ocelot->ports[port]; 536 537 spin_lock(&ocelot_port->ts_id_lock); 538 539 skb_shinfo(clone)->tx_flags |= SKBTX_IN_PROGRESS; 540 /* Store timestamp ID in cb[0] of sk_buff */ 541 clone->cb[0] = ocelot_port->ts_id; 542 ocelot_port->ts_id = (ocelot_port->ts_id + 1) % 4; 543 skb_queue_tail(&ocelot_port->tx_skbs, clone); 544 545 spin_unlock(&ocelot_port->ts_id_lock); 546 } 547 EXPORT_SYMBOL(ocelot_port_add_txtstamp_skb); 548 549 static void ocelot_get_hwtimestamp(struct ocelot *ocelot, 550 struct timespec64 *ts) 551 { 552 unsigned long flags; 553 u32 val; 554 555 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); 556 557 /* Read current PTP time to get seconds */ 558 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 559 560 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 561 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE); 562 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 563 ts->tv_sec = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN); 564 565 /* Read packet HW timestamp from FIFO */ 566 val = ocelot_read(ocelot, SYS_PTP_TXSTAMP); 567 ts->tv_nsec = SYS_PTP_TXSTAMP_PTP_TXSTAMP(val); 568 569 /* Sec has incremented since the ts was registered */ 570 if ((ts->tv_sec & 0x1) != !!(val & SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC)) 571 ts->tv_sec--; 572 573 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 574 } 575 576 void ocelot_get_txtstamp(struct ocelot *ocelot) 577 { 578 int budget = OCELOT_PTP_QUEUE_SZ; 579 580 while (budget--) { 581 struct sk_buff *skb, *skb_tmp, *skb_match = NULL; 582 struct skb_shared_hwtstamps shhwtstamps; 583 struct ocelot_port *port; 584 struct timespec64 ts; 585 unsigned long flags; 586 u32 val, id, txport; 587 588 val = ocelot_read(ocelot, SYS_PTP_STATUS); 589 590 /* Check if a timestamp can be retrieved */ 591 if (!(val & SYS_PTP_STATUS_PTP_MESS_VLD)) 592 break; 593 594 WARN_ON(val & SYS_PTP_STATUS_PTP_OVFL); 595 596 /* Retrieve the ts ID and Tx port */ 597 id = SYS_PTP_STATUS_PTP_MESS_ID_X(val); 598 txport = SYS_PTP_STATUS_PTP_MESS_TXPORT_X(val); 599 600 /* Retrieve its associated skb */ 601 port = ocelot->ports[txport]; 602 603 spin_lock_irqsave(&port->tx_skbs.lock, flags); 604 605 skb_queue_walk_safe(&port->tx_skbs, skb, skb_tmp) { 606 if (skb->cb[0] != id) 607 continue; 608 __skb_unlink(skb, &port->tx_skbs); 609 skb_match = skb; 610 break; 611 } 612 613 spin_unlock_irqrestore(&port->tx_skbs.lock, flags); 614 615 /* Get the h/w timestamp */ 616 ocelot_get_hwtimestamp(ocelot, &ts); 617 618 if (unlikely(!skb_match)) 619 continue; 620 621 /* Set the timestamp into the skb */ 622 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 623 shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec); 624 skb_complete_tx_timestamp(skb_match, &shhwtstamps); 625 626 /* Next ts */ 627 ocelot_write(ocelot, SYS_PTP_NXT_PTP_NXT, SYS_PTP_NXT); 628 } 629 } 630 EXPORT_SYMBOL(ocelot_get_txtstamp); 631 632 static int ocelot_rx_frame_word(struct ocelot *ocelot, u8 grp, bool ifh, 633 u32 *rval) 634 { 635 u32 bytes_valid, val; 636 637 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 638 if (val == XTR_NOT_READY) { 639 if (ifh) 640 return -EIO; 641 642 do { 643 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 644 } while (val == XTR_NOT_READY); 645 } 646 647 switch (val) { 648 case XTR_ABORT: 649 return -EIO; 650 case XTR_EOF_0: 651 case XTR_EOF_1: 652 case XTR_EOF_2: 653 case XTR_EOF_3: 654 case XTR_PRUNED: 655 bytes_valid = XTR_VALID_BYTES(val); 656 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 657 if (val == XTR_ESCAPE) 658 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 659 else 660 *rval = val; 661 662 return bytes_valid; 663 case XTR_ESCAPE: 664 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 665 666 return 4; 667 default: 668 *rval = val; 669 670 return 4; 671 } 672 } 673 674 static int ocelot_xtr_poll_xfh(struct ocelot *ocelot, int grp, u32 *xfh) 675 { 676 int i, err = 0; 677 678 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) { 679 err = ocelot_rx_frame_word(ocelot, grp, true, &xfh[i]); 680 if (err != 4) 681 return (err < 0) ? err : -EIO; 682 } 683 684 return 0; 685 } 686 687 int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **nskb) 688 { 689 struct skb_shared_hwtstamps *shhwtstamps; 690 u64 tod_in_ns, full_ts_in_ns; 691 u64 timestamp, src_port, len; 692 u32 xfh[OCELOT_TAG_LEN / 4]; 693 struct net_device *dev; 694 struct timespec64 ts; 695 struct sk_buff *skb; 696 int sz, buf_len; 697 u32 val, *buf; 698 int err; 699 700 err = ocelot_xtr_poll_xfh(ocelot, grp, xfh); 701 if (err) 702 return err; 703 704 ocelot_xfh_get_src_port(xfh, &src_port); 705 ocelot_xfh_get_len(xfh, &len); 706 ocelot_xfh_get_rew_val(xfh, ×tamp); 707 708 if (WARN_ON(src_port >= ocelot->num_phys_ports)) 709 return -EINVAL; 710 711 dev = ocelot->ops->port_to_netdev(ocelot, src_port); 712 if (!dev) 713 return -EINVAL; 714 715 skb = netdev_alloc_skb(dev, len); 716 if (unlikely(!skb)) { 717 netdev_err(dev, "Unable to allocate sk_buff\n"); 718 return -ENOMEM; 719 } 720 721 buf_len = len - ETH_FCS_LEN; 722 buf = (u32 *)skb_put(skb, buf_len); 723 724 len = 0; 725 do { 726 sz = ocelot_rx_frame_word(ocelot, grp, false, &val); 727 if (sz < 0) { 728 err = sz; 729 goto out_free_skb; 730 } 731 *buf++ = val; 732 len += sz; 733 } while (len < buf_len); 734 735 /* Read the FCS */ 736 sz = ocelot_rx_frame_word(ocelot, grp, false, &val); 737 if (sz < 0) { 738 err = sz; 739 goto out_free_skb; 740 } 741 742 /* Update the statistics if part of the FCS was read before */ 743 len -= ETH_FCS_LEN - sz; 744 745 if (unlikely(dev->features & NETIF_F_RXFCS)) { 746 buf = (u32 *)skb_put(skb, ETH_FCS_LEN); 747 *buf = val; 748 } 749 750 if (ocelot->ptp) { 751 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); 752 753 tod_in_ns = ktime_set(ts.tv_sec, ts.tv_nsec); 754 if ((tod_in_ns & 0xffffffff) < timestamp) 755 full_ts_in_ns = (((tod_in_ns >> 32) - 1) << 32) | 756 timestamp; 757 else 758 full_ts_in_ns = (tod_in_ns & GENMASK_ULL(63, 32)) | 759 timestamp; 760 761 shhwtstamps = skb_hwtstamps(skb); 762 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps)); 763 shhwtstamps->hwtstamp = full_ts_in_ns; 764 } 765 766 /* Everything we see on an interface that is in the HW bridge 767 * has already been forwarded. 768 */ 769 if (ocelot->ports[src_port]->bridge) 770 skb->offload_fwd_mark = 1; 771 772 skb->protocol = eth_type_trans(skb, dev); 773 774 *nskb = skb; 775 776 return 0; 777 778 out_free_skb: 779 kfree_skb(skb); 780 return err; 781 } 782 EXPORT_SYMBOL(ocelot_xtr_poll_frame); 783 784 bool ocelot_can_inject(struct ocelot *ocelot, int grp) 785 { 786 u32 val = ocelot_read(ocelot, QS_INJ_STATUS); 787 788 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp)))) 789 return false; 790 if (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp))) 791 return false; 792 793 return true; 794 } 795 EXPORT_SYMBOL(ocelot_can_inject); 796 797 void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp, 798 u32 rew_op, struct sk_buff *skb) 799 { 800 u32 ifh[OCELOT_TAG_LEN / 4] = {0}; 801 unsigned int i, count, last; 802 803 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 804 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp); 805 806 ocelot_ifh_set_bypass(ifh, 1); 807 ocelot_ifh_set_dest(ifh, BIT_ULL(port)); 808 ocelot_ifh_set_tag_type(ifh, IFH_TAG_TYPE_C); 809 ocelot_ifh_set_vid(ifh, skb_vlan_tag_get(skb)); 810 ocelot_ifh_set_rew_op(ifh, rew_op); 811 812 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) 813 ocelot_write_rix(ocelot, ifh[i], QS_INJ_WR, grp); 814 815 count = DIV_ROUND_UP(skb->len, 4); 816 last = skb->len % 4; 817 for (i = 0; i < count; i++) 818 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp); 819 820 /* Add padding */ 821 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) { 822 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 823 i++; 824 } 825 826 /* Indicate EOF and valid bytes in last word */ 827 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 828 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) | 829 QS_INJ_CTRL_EOF, 830 QS_INJ_CTRL, grp); 831 832 /* Add dummy CRC */ 833 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 834 skb_tx_timestamp(skb); 835 836 skb->dev->stats.tx_packets++; 837 skb->dev->stats.tx_bytes += skb->len; 838 } 839 EXPORT_SYMBOL(ocelot_port_inject_frame); 840 841 void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp) 842 { 843 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)) 844 ocelot_read_rix(ocelot, QS_XTR_RD, grp); 845 } 846 EXPORT_SYMBOL(ocelot_drain_cpu_queue); 847 848 int ocelot_fdb_add(struct ocelot *ocelot, int port, 849 const unsigned char *addr, u16 vid) 850 { 851 int pgid = port; 852 853 if (port == ocelot->npi) 854 pgid = PGID_CPU; 855 856 return ocelot_mact_learn(ocelot, pgid, addr, vid, ENTRYTYPE_LOCKED); 857 } 858 EXPORT_SYMBOL(ocelot_fdb_add); 859 860 int ocelot_fdb_del(struct ocelot *ocelot, int port, 861 const unsigned char *addr, u16 vid) 862 { 863 return ocelot_mact_forget(ocelot, addr, vid); 864 } 865 EXPORT_SYMBOL(ocelot_fdb_del); 866 867 int ocelot_port_fdb_do_dump(const unsigned char *addr, u16 vid, 868 bool is_static, void *data) 869 { 870 struct ocelot_dump_ctx *dump = data; 871 u32 portid = NETLINK_CB(dump->cb->skb).portid; 872 u32 seq = dump->cb->nlh->nlmsg_seq; 873 struct nlmsghdr *nlh; 874 struct ndmsg *ndm; 875 876 if (dump->idx < dump->cb->args[2]) 877 goto skip; 878 879 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH, 880 sizeof(*ndm), NLM_F_MULTI); 881 if (!nlh) 882 return -EMSGSIZE; 883 884 ndm = nlmsg_data(nlh); 885 ndm->ndm_family = AF_BRIDGE; 886 ndm->ndm_pad1 = 0; 887 ndm->ndm_pad2 = 0; 888 ndm->ndm_flags = NTF_SELF; 889 ndm->ndm_type = 0; 890 ndm->ndm_ifindex = dump->dev->ifindex; 891 ndm->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE; 892 893 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, addr)) 894 goto nla_put_failure; 895 896 if (vid && nla_put_u16(dump->skb, NDA_VLAN, vid)) 897 goto nla_put_failure; 898 899 nlmsg_end(dump->skb, nlh); 900 901 skip: 902 dump->idx++; 903 return 0; 904 905 nla_put_failure: 906 nlmsg_cancel(dump->skb, nlh); 907 return -EMSGSIZE; 908 } 909 EXPORT_SYMBOL(ocelot_port_fdb_do_dump); 910 911 static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col, 912 struct ocelot_mact_entry *entry) 913 { 914 u32 val, dst, macl, mach; 915 char mac[ETH_ALEN]; 916 917 /* Set row and column to read from */ 918 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row); 919 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col); 920 921 /* Issue a read command */ 922 ocelot_write(ocelot, 923 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 924 ANA_TABLES_MACACCESS); 925 926 if (ocelot_mact_wait_for_completion(ocelot)) 927 return -ETIMEDOUT; 928 929 /* Read the entry flags */ 930 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 931 if (!(val & ANA_TABLES_MACACCESS_VALID)) 932 return -EINVAL; 933 934 /* If the entry read has another port configured as its destination, 935 * do not report it. 936 */ 937 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3; 938 if (dst != port) 939 return -EINVAL; 940 941 /* Get the entry's MAC address and VLAN id */ 942 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA); 943 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA); 944 945 mac[0] = (mach >> 8) & 0xff; 946 mac[1] = (mach >> 0) & 0xff; 947 mac[2] = (macl >> 24) & 0xff; 948 mac[3] = (macl >> 16) & 0xff; 949 mac[4] = (macl >> 8) & 0xff; 950 mac[5] = (macl >> 0) & 0xff; 951 952 entry->vid = (mach >> 16) & 0xfff; 953 ether_addr_copy(entry->mac, mac); 954 955 return 0; 956 } 957 958 int ocelot_fdb_dump(struct ocelot *ocelot, int port, 959 dsa_fdb_dump_cb_t *cb, void *data) 960 { 961 int i, j; 962 963 /* Loop through all the mac tables entries. */ 964 for (i = 0; i < ocelot->num_mact_rows; i++) { 965 for (j = 0; j < 4; j++) { 966 struct ocelot_mact_entry entry; 967 bool is_static; 968 int ret; 969 970 ret = ocelot_mact_read(ocelot, port, i, j, &entry); 971 /* If the entry is invalid (wrong port, invalid...), 972 * skip it. 973 */ 974 if (ret == -EINVAL) 975 continue; 976 else if (ret) 977 return ret; 978 979 is_static = (entry.type == ENTRYTYPE_LOCKED); 980 981 ret = cb(entry.mac, entry.vid, is_static, data); 982 if (ret) 983 return ret; 984 } 985 } 986 987 return 0; 988 } 989 EXPORT_SYMBOL(ocelot_fdb_dump); 990 991 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr) 992 { 993 return copy_to_user(ifr->ifr_data, &ocelot->hwtstamp_config, 994 sizeof(ocelot->hwtstamp_config)) ? -EFAULT : 0; 995 } 996 EXPORT_SYMBOL(ocelot_hwstamp_get); 997 998 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr) 999 { 1000 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1001 struct hwtstamp_config cfg; 1002 1003 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1004 return -EFAULT; 1005 1006 /* reserved for future extensions */ 1007 if (cfg.flags) 1008 return -EINVAL; 1009 1010 /* Tx type sanity check */ 1011 switch (cfg.tx_type) { 1012 case HWTSTAMP_TX_ON: 1013 ocelot_port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP; 1014 break; 1015 case HWTSTAMP_TX_ONESTEP_SYNC: 1016 /* IFH_REW_OP_ONE_STEP_PTP updates the correctional field, we 1017 * need to update the origin time. 1018 */ 1019 ocelot_port->ptp_cmd = IFH_REW_OP_ORIGIN_PTP; 1020 break; 1021 case HWTSTAMP_TX_OFF: 1022 ocelot_port->ptp_cmd = 0; 1023 break; 1024 default: 1025 return -ERANGE; 1026 } 1027 1028 mutex_lock(&ocelot->ptp_lock); 1029 1030 switch (cfg.rx_filter) { 1031 case HWTSTAMP_FILTER_NONE: 1032 break; 1033 case HWTSTAMP_FILTER_ALL: 1034 case HWTSTAMP_FILTER_SOME: 1035 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1036 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1037 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1038 case HWTSTAMP_FILTER_NTP_ALL: 1039 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1040 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1041 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1042 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1043 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1044 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1045 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1046 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1047 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1048 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 1049 break; 1050 default: 1051 mutex_unlock(&ocelot->ptp_lock); 1052 return -ERANGE; 1053 } 1054 1055 /* Commit back the result & save it */ 1056 memcpy(&ocelot->hwtstamp_config, &cfg, sizeof(cfg)); 1057 mutex_unlock(&ocelot->ptp_lock); 1058 1059 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1060 } 1061 EXPORT_SYMBOL(ocelot_hwstamp_set); 1062 1063 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data) 1064 { 1065 int i; 1066 1067 if (sset != ETH_SS_STATS) 1068 return; 1069 1070 for (i = 0; i < ocelot->num_stats; i++) 1071 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name, 1072 ETH_GSTRING_LEN); 1073 } 1074 EXPORT_SYMBOL(ocelot_get_strings); 1075 1076 static void ocelot_update_stats(struct ocelot *ocelot) 1077 { 1078 int i, j; 1079 1080 mutex_lock(&ocelot->stats_lock); 1081 1082 for (i = 0; i < ocelot->num_phys_ports; i++) { 1083 /* Configure the port to read the stats from */ 1084 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(i), SYS_STAT_CFG); 1085 1086 for (j = 0; j < ocelot->num_stats; j++) { 1087 u32 val; 1088 unsigned int idx = i * ocelot->num_stats + j; 1089 1090 val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS, 1091 ocelot->stats_layout[j].offset); 1092 1093 if (val < (ocelot->stats[idx] & U32_MAX)) 1094 ocelot->stats[idx] += (u64)1 << 32; 1095 1096 ocelot->stats[idx] = (ocelot->stats[idx] & 1097 ~(u64)U32_MAX) + val; 1098 } 1099 } 1100 1101 mutex_unlock(&ocelot->stats_lock); 1102 } 1103 1104 static void ocelot_check_stats_work(struct work_struct *work) 1105 { 1106 struct delayed_work *del_work = to_delayed_work(work); 1107 struct ocelot *ocelot = container_of(del_work, struct ocelot, 1108 stats_work); 1109 1110 ocelot_update_stats(ocelot); 1111 1112 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 1113 OCELOT_STATS_CHECK_DELAY); 1114 } 1115 1116 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data) 1117 { 1118 int i; 1119 1120 /* check and update now */ 1121 ocelot_update_stats(ocelot); 1122 1123 /* Copy all counters */ 1124 for (i = 0; i < ocelot->num_stats; i++) 1125 *data++ = ocelot->stats[port * ocelot->num_stats + i]; 1126 } 1127 EXPORT_SYMBOL(ocelot_get_ethtool_stats); 1128 1129 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset) 1130 { 1131 if (sset != ETH_SS_STATS) 1132 return -EOPNOTSUPP; 1133 1134 return ocelot->num_stats; 1135 } 1136 EXPORT_SYMBOL(ocelot_get_sset_count); 1137 1138 int ocelot_get_ts_info(struct ocelot *ocelot, int port, 1139 struct ethtool_ts_info *info) 1140 { 1141 info->phc_index = ocelot->ptp_clock ? 1142 ptp_clock_index(ocelot->ptp_clock) : -1; 1143 if (info->phc_index == -1) { 1144 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 1145 SOF_TIMESTAMPING_RX_SOFTWARE | 1146 SOF_TIMESTAMPING_SOFTWARE; 1147 return 0; 1148 } 1149 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 1150 SOF_TIMESTAMPING_RX_SOFTWARE | 1151 SOF_TIMESTAMPING_SOFTWARE | 1152 SOF_TIMESTAMPING_TX_HARDWARE | 1153 SOF_TIMESTAMPING_RX_HARDWARE | 1154 SOF_TIMESTAMPING_RAW_HARDWARE; 1155 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON) | 1156 BIT(HWTSTAMP_TX_ONESTEP_SYNC); 1157 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL); 1158 1159 return 0; 1160 } 1161 EXPORT_SYMBOL(ocelot_get_ts_info); 1162 1163 static u32 ocelot_get_bond_mask(struct ocelot *ocelot, struct net_device *bond, 1164 bool only_active_ports) 1165 { 1166 u32 mask = 0; 1167 int port; 1168 1169 for (port = 0; port < ocelot->num_phys_ports; port++) { 1170 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1171 1172 if (!ocelot_port) 1173 continue; 1174 1175 if (ocelot_port->bond == bond) { 1176 if (only_active_ports && !ocelot_port->lag_tx_active) 1177 continue; 1178 1179 mask |= BIT(port); 1180 } 1181 } 1182 1183 return mask; 1184 } 1185 1186 static u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot, 1187 struct net_device *bridge) 1188 { 1189 u32 mask = 0; 1190 int port; 1191 1192 for (port = 0; port < ocelot->num_phys_ports; port++) { 1193 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1194 1195 if (!ocelot_port) 1196 continue; 1197 1198 if (ocelot_port->stp_state == BR_STATE_FORWARDING && 1199 ocelot_port->bridge == bridge) 1200 mask |= BIT(port); 1201 } 1202 1203 return mask; 1204 } 1205 1206 static u32 ocelot_get_dsa_8021q_cpu_mask(struct ocelot *ocelot) 1207 { 1208 u32 mask = 0; 1209 int port; 1210 1211 for (port = 0; port < ocelot->num_phys_ports; port++) { 1212 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1213 1214 if (!ocelot_port) 1215 continue; 1216 1217 if (ocelot_port->is_dsa_8021q_cpu) 1218 mask |= BIT(port); 1219 } 1220 1221 return mask; 1222 } 1223 1224 void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot) 1225 { 1226 unsigned long cpu_fwd_mask; 1227 int port; 1228 1229 /* If a DSA tag_8021q CPU exists, it needs to be included in the 1230 * regular forwarding path of the front ports regardless of whether 1231 * those are bridged or standalone. 1232 * If DSA tag_8021q is not used, this returns 0, which is fine because 1233 * the hardware-based CPU port module can be a destination for packets 1234 * even if it isn't part of PGID_SRC. 1235 */ 1236 cpu_fwd_mask = ocelot_get_dsa_8021q_cpu_mask(ocelot); 1237 1238 /* Apply FWD mask. The loop is needed to add/remove the current port as 1239 * a source for the other ports. 1240 */ 1241 for (port = 0; port < ocelot->num_phys_ports; port++) { 1242 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1243 unsigned long mask; 1244 1245 if (!ocelot_port) { 1246 /* Unused ports can't send anywhere */ 1247 mask = 0; 1248 } else if (ocelot_port->is_dsa_8021q_cpu) { 1249 /* The DSA tag_8021q CPU ports need to be able to 1250 * forward packets to all other ports except for 1251 * themselves 1252 */ 1253 mask = GENMASK(ocelot->num_phys_ports - 1, 0); 1254 mask &= ~cpu_fwd_mask; 1255 } else if (ocelot_port->bridge) { 1256 struct net_device *bridge = ocelot_port->bridge; 1257 struct net_device *bond = ocelot_port->bond; 1258 1259 mask = ocelot_get_bridge_fwd_mask(ocelot, bridge); 1260 mask &= ~BIT(port); 1261 if (bond) { 1262 mask &= ~ocelot_get_bond_mask(ocelot, bond, 1263 false); 1264 } 1265 } else { 1266 /* Standalone ports forward only to DSA tag_8021q CPU 1267 * ports (if those exist), or to the hardware CPU port 1268 * module otherwise. 1269 */ 1270 mask = cpu_fwd_mask; 1271 } 1272 1273 ocelot_write_rix(ocelot, mask, ANA_PGID_PGID, PGID_SRC + port); 1274 } 1275 } 1276 EXPORT_SYMBOL(ocelot_apply_bridge_fwd_mask); 1277 1278 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state) 1279 { 1280 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1281 u32 learn_ena = 0; 1282 1283 ocelot_port->stp_state = state; 1284 1285 if ((state == BR_STATE_LEARNING || state == BR_STATE_FORWARDING) && 1286 ocelot_port->learn_ena) 1287 learn_ena = ANA_PORT_PORT_CFG_LEARN_ENA; 1288 1289 ocelot_rmw_gix(ocelot, learn_ena, ANA_PORT_PORT_CFG_LEARN_ENA, 1290 ANA_PORT_PORT_CFG, port); 1291 1292 ocelot_apply_bridge_fwd_mask(ocelot); 1293 } 1294 EXPORT_SYMBOL(ocelot_bridge_stp_state_set); 1295 1296 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs) 1297 { 1298 unsigned int age_period = ANA_AUTOAGE_AGE_PERIOD(msecs / 2000); 1299 1300 /* Setting AGE_PERIOD to zero effectively disables automatic aging, 1301 * which is clearly not what our intention is. So avoid that. 1302 */ 1303 if (!age_period) 1304 age_period = 1; 1305 1306 ocelot_rmw(ocelot, age_period, ANA_AUTOAGE_AGE_PERIOD_M, ANA_AUTOAGE); 1307 } 1308 EXPORT_SYMBOL(ocelot_set_ageing_time); 1309 1310 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot, 1311 const unsigned char *addr, 1312 u16 vid) 1313 { 1314 struct ocelot_multicast *mc; 1315 1316 list_for_each_entry(mc, &ocelot->multicast, list) { 1317 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid) 1318 return mc; 1319 } 1320 1321 return NULL; 1322 } 1323 1324 static enum macaccess_entry_type ocelot_classify_mdb(const unsigned char *addr) 1325 { 1326 if (addr[0] == 0x01 && addr[1] == 0x00 && addr[2] == 0x5e) 1327 return ENTRYTYPE_MACv4; 1328 if (addr[0] == 0x33 && addr[1] == 0x33) 1329 return ENTRYTYPE_MACv6; 1330 return ENTRYTYPE_LOCKED; 1331 } 1332 1333 static struct ocelot_pgid *ocelot_pgid_alloc(struct ocelot *ocelot, int index, 1334 unsigned long ports) 1335 { 1336 struct ocelot_pgid *pgid; 1337 1338 pgid = kzalloc(sizeof(*pgid), GFP_KERNEL); 1339 if (!pgid) 1340 return ERR_PTR(-ENOMEM); 1341 1342 pgid->ports = ports; 1343 pgid->index = index; 1344 refcount_set(&pgid->refcount, 1); 1345 list_add_tail(&pgid->list, &ocelot->pgids); 1346 1347 return pgid; 1348 } 1349 1350 static void ocelot_pgid_free(struct ocelot *ocelot, struct ocelot_pgid *pgid) 1351 { 1352 if (!refcount_dec_and_test(&pgid->refcount)) 1353 return; 1354 1355 list_del(&pgid->list); 1356 kfree(pgid); 1357 } 1358 1359 static struct ocelot_pgid *ocelot_mdb_get_pgid(struct ocelot *ocelot, 1360 const struct ocelot_multicast *mc) 1361 { 1362 struct ocelot_pgid *pgid; 1363 int index; 1364 1365 /* According to VSC7514 datasheet 3.9.1.5 IPv4 Multicast Entries and 1366 * 3.9.1.6 IPv6 Multicast Entries, "Instead of a lookup in the 1367 * destination mask table (PGID), the destination set is programmed as 1368 * part of the entry MAC address.", and the DEST_IDX is set to 0. 1369 */ 1370 if (mc->entry_type == ENTRYTYPE_MACv4 || 1371 mc->entry_type == ENTRYTYPE_MACv6) 1372 return ocelot_pgid_alloc(ocelot, 0, mc->ports); 1373 1374 list_for_each_entry(pgid, &ocelot->pgids, list) { 1375 /* When searching for a nonreserved multicast PGID, ignore the 1376 * dummy PGID of zero that we have for MACv4/MACv6 entries 1377 */ 1378 if (pgid->index && pgid->ports == mc->ports) { 1379 refcount_inc(&pgid->refcount); 1380 return pgid; 1381 } 1382 } 1383 1384 /* Search for a free index in the nonreserved multicast PGID area */ 1385 for_each_nonreserved_multicast_dest_pgid(ocelot, index) { 1386 bool used = false; 1387 1388 list_for_each_entry(pgid, &ocelot->pgids, list) { 1389 if (pgid->index == index) { 1390 used = true; 1391 break; 1392 } 1393 } 1394 1395 if (!used) 1396 return ocelot_pgid_alloc(ocelot, index, mc->ports); 1397 } 1398 1399 return ERR_PTR(-ENOSPC); 1400 } 1401 1402 static void ocelot_encode_ports_to_mdb(unsigned char *addr, 1403 struct ocelot_multicast *mc) 1404 { 1405 ether_addr_copy(addr, mc->addr); 1406 1407 if (mc->entry_type == ENTRYTYPE_MACv4) { 1408 addr[0] = 0; 1409 addr[1] = mc->ports >> 8; 1410 addr[2] = mc->ports & 0xff; 1411 } else if (mc->entry_type == ENTRYTYPE_MACv6) { 1412 addr[0] = mc->ports >> 8; 1413 addr[1] = mc->ports & 0xff; 1414 } 1415 } 1416 1417 int ocelot_port_mdb_add(struct ocelot *ocelot, int port, 1418 const struct switchdev_obj_port_mdb *mdb) 1419 { 1420 unsigned char addr[ETH_ALEN]; 1421 struct ocelot_multicast *mc; 1422 struct ocelot_pgid *pgid; 1423 u16 vid = mdb->vid; 1424 1425 if (port == ocelot->npi) 1426 port = ocelot->num_phys_ports; 1427 1428 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1429 if (!mc) { 1430 /* New entry */ 1431 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL); 1432 if (!mc) 1433 return -ENOMEM; 1434 1435 mc->entry_type = ocelot_classify_mdb(mdb->addr); 1436 ether_addr_copy(mc->addr, mdb->addr); 1437 mc->vid = vid; 1438 1439 list_add_tail(&mc->list, &ocelot->multicast); 1440 } else { 1441 /* Existing entry. Clean up the current port mask from 1442 * hardware now, because we'll be modifying it. 1443 */ 1444 ocelot_pgid_free(ocelot, mc->pgid); 1445 ocelot_encode_ports_to_mdb(addr, mc); 1446 ocelot_mact_forget(ocelot, addr, vid); 1447 } 1448 1449 mc->ports |= BIT(port); 1450 1451 pgid = ocelot_mdb_get_pgid(ocelot, mc); 1452 if (IS_ERR(pgid)) { 1453 dev_err(ocelot->dev, 1454 "Cannot allocate PGID for mdb %pM vid %d\n", 1455 mc->addr, mc->vid); 1456 devm_kfree(ocelot->dev, mc); 1457 return PTR_ERR(pgid); 1458 } 1459 mc->pgid = pgid; 1460 1461 ocelot_encode_ports_to_mdb(addr, mc); 1462 1463 if (mc->entry_type != ENTRYTYPE_MACv4 && 1464 mc->entry_type != ENTRYTYPE_MACv6) 1465 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 1466 pgid->index); 1467 1468 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 1469 mc->entry_type); 1470 } 1471 EXPORT_SYMBOL(ocelot_port_mdb_add); 1472 1473 int ocelot_port_mdb_del(struct ocelot *ocelot, int port, 1474 const struct switchdev_obj_port_mdb *mdb) 1475 { 1476 unsigned char addr[ETH_ALEN]; 1477 struct ocelot_multicast *mc; 1478 struct ocelot_pgid *pgid; 1479 u16 vid = mdb->vid; 1480 1481 if (port == ocelot->npi) 1482 port = ocelot->num_phys_ports; 1483 1484 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1485 if (!mc) 1486 return -ENOENT; 1487 1488 ocelot_encode_ports_to_mdb(addr, mc); 1489 ocelot_mact_forget(ocelot, addr, vid); 1490 1491 ocelot_pgid_free(ocelot, mc->pgid); 1492 mc->ports &= ~BIT(port); 1493 if (!mc->ports) { 1494 list_del(&mc->list); 1495 devm_kfree(ocelot->dev, mc); 1496 return 0; 1497 } 1498 1499 /* We have a PGID with fewer ports now */ 1500 pgid = ocelot_mdb_get_pgid(ocelot, mc); 1501 if (IS_ERR(pgid)) 1502 return PTR_ERR(pgid); 1503 mc->pgid = pgid; 1504 1505 ocelot_encode_ports_to_mdb(addr, mc); 1506 1507 if (mc->entry_type != ENTRYTYPE_MACv4 && 1508 mc->entry_type != ENTRYTYPE_MACv6) 1509 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 1510 pgid->index); 1511 1512 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 1513 mc->entry_type); 1514 } 1515 EXPORT_SYMBOL(ocelot_port_mdb_del); 1516 1517 int ocelot_port_bridge_join(struct ocelot *ocelot, int port, 1518 struct net_device *bridge) 1519 { 1520 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1521 1522 ocelot_port->bridge = bridge; 1523 1524 return 0; 1525 } 1526 EXPORT_SYMBOL(ocelot_port_bridge_join); 1527 1528 int ocelot_port_bridge_leave(struct ocelot *ocelot, int port, 1529 struct net_device *bridge) 1530 { 1531 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1532 struct ocelot_vlan pvid = {0}, native_vlan = {0}; 1533 int ret; 1534 1535 ocelot_port->bridge = NULL; 1536 1537 ret = ocelot_port_vlan_filtering(ocelot, port, false); 1538 if (ret) 1539 return ret; 1540 1541 ocelot_port_set_pvid(ocelot, port, pvid); 1542 ocelot_port_set_native_vlan(ocelot, port, native_vlan); 1543 1544 return 0; 1545 } 1546 EXPORT_SYMBOL(ocelot_port_bridge_leave); 1547 1548 static void ocelot_set_aggr_pgids(struct ocelot *ocelot) 1549 { 1550 unsigned long visited = GENMASK(ocelot->num_phys_ports - 1, 0); 1551 int i, port, lag; 1552 1553 /* Reset destination and aggregation PGIDS */ 1554 for_each_unicast_dest_pgid(ocelot, port) 1555 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 1556 1557 for_each_aggr_pgid(ocelot, i) 1558 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 1559 ANA_PGID_PGID, i); 1560 1561 /* The visited ports bitmask holds the list of ports offloading any 1562 * bonding interface. Initially we mark all these ports as unvisited, 1563 * then every time we visit a port in this bitmask, we know that it is 1564 * the lowest numbered port, i.e. the one whose logical ID == physical 1565 * port ID == LAG ID. So we mark as visited all further ports in the 1566 * bitmask that are offloading the same bonding interface. This way, 1567 * we set up the aggregation PGIDs only once per bonding interface. 1568 */ 1569 for (port = 0; port < ocelot->num_phys_ports; port++) { 1570 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1571 1572 if (!ocelot_port || !ocelot_port->bond) 1573 continue; 1574 1575 visited &= ~BIT(port); 1576 } 1577 1578 /* Now, set PGIDs for each active LAG */ 1579 for (lag = 0; lag < ocelot->num_phys_ports; lag++) { 1580 struct net_device *bond = ocelot->ports[lag]->bond; 1581 int num_active_ports = 0; 1582 unsigned long bond_mask; 1583 u8 aggr_idx[16]; 1584 1585 if (!bond || (visited & BIT(lag))) 1586 continue; 1587 1588 bond_mask = ocelot_get_bond_mask(ocelot, bond, true); 1589 1590 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) { 1591 // Destination mask 1592 ocelot_write_rix(ocelot, bond_mask, 1593 ANA_PGID_PGID, port); 1594 aggr_idx[num_active_ports++] = port; 1595 } 1596 1597 for_each_aggr_pgid(ocelot, i) { 1598 u32 ac; 1599 1600 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i); 1601 ac &= ~bond_mask; 1602 /* Don't do division by zero if there was no active 1603 * port. Just make all aggregation codes zero. 1604 */ 1605 if (num_active_ports) 1606 ac |= BIT(aggr_idx[i % num_active_ports]); 1607 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i); 1608 } 1609 1610 /* Mark all ports in the same LAG as visited to avoid applying 1611 * the same config again. 1612 */ 1613 for (port = lag; port < ocelot->num_phys_ports; port++) { 1614 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1615 1616 if (!ocelot_port) 1617 continue; 1618 1619 if (ocelot_port->bond == bond) 1620 visited |= BIT(port); 1621 } 1622 } 1623 } 1624 1625 /* When offloading a bonding interface, the switch ports configured under the 1626 * same bond must have the same logical port ID, equal to the physical port ID 1627 * of the lowest numbered physical port in that bond. Otherwise, in standalone/ 1628 * bridged mode, each port has a logical port ID equal to its physical port ID. 1629 */ 1630 static void ocelot_setup_logical_port_ids(struct ocelot *ocelot) 1631 { 1632 int port; 1633 1634 for (port = 0; port < ocelot->num_phys_ports; port++) { 1635 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1636 struct net_device *bond; 1637 1638 if (!ocelot_port) 1639 continue; 1640 1641 bond = ocelot_port->bond; 1642 if (bond) { 1643 int lag = __ffs(ocelot_get_bond_mask(ocelot, bond, 1644 false)); 1645 1646 ocelot_rmw_gix(ocelot, 1647 ANA_PORT_PORT_CFG_PORTID_VAL(lag), 1648 ANA_PORT_PORT_CFG_PORTID_VAL_M, 1649 ANA_PORT_PORT_CFG, port); 1650 } else { 1651 ocelot_rmw_gix(ocelot, 1652 ANA_PORT_PORT_CFG_PORTID_VAL(port), 1653 ANA_PORT_PORT_CFG_PORTID_VAL_M, 1654 ANA_PORT_PORT_CFG, port); 1655 } 1656 } 1657 } 1658 1659 int ocelot_port_lag_join(struct ocelot *ocelot, int port, 1660 struct net_device *bond, 1661 struct netdev_lag_upper_info *info) 1662 { 1663 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) 1664 return -EOPNOTSUPP; 1665 1666 ocelot->ports[port]->bond = bond; 1667 1668 ocelot_setup_logical_port_ids(ocelot); 1669 ocelot_apply_bridge_fwd_mask(ocelot); 1670 ocelot_set_aggr_pgids(ocelot); 1671 1672 return 0; 1673 } 1674 EXPORT_SYMBOL(ocelot_port_lag_join); 1675 1676 void ocelot_port_lag_leave(struct ocelot *ocelot, int port, 1677 struct net_device *bond) 1678 { 1679 ocelot->ports[port]->bond = NULL; 1680 1681 ocelot_setup_logical_port_ids(ocelot); 1682 ocelot_apply_bridge_fwd_mask(ocelot); 1683 ocelot_set_aggr_pgids(ocelot); 1684 } 1685 EXPORT_SYMBOL(ocelot_port_lag_leave); 1686 1687 void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active) 1688 { 1689 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1690 1691 ocelot_port->lag_tx_active = lag_tx_active; 1692 1693 /* Rebalance the LAGs */ 1694 ocelot_set_aggr_pgids(ocelot); 1695 } 1696 EXPORT_SYMBOL(ocelot_port_lag_change); 1697 1698 /* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu. 1699 * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG. 1700 * In the special case that it's the NPI port that we're configuring, the 1701 * length of the tag and optional prefix needs to be accounted for privately, 1702 * in order to be able to sustain communication at the requested @sdu. 1703 */ 1704 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu) 1705 { 1706 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1707 int maxlen = sdu + ETH_HLEN + ETH_FCS_LEN; 1708 int pause_start, pause_stop; 1709 int atop, atop_tot; 1710 1711 if (port == ocelot->npi) { 1712 maxlen += OCELOT_TAG_LEN; 1713 1714 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT) 1715 maxlen += OCELOT_SHORT_PREFIX_LEN; 1716 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG) 1717 maxlen += OCELOT_LONG_PREFIX_LEN; 1718 } 1719 1720 ocelot_port_writel(ocelot_port, maxlen, DEV_MAC_MAXLEN_CFG); 1721 1722 /* Set Pause watermark hysteresis */ 1723 pause_start = 6 * maxlen / OCELOT_BUFFER_CELL_SZ; 1724 pause_stop = 4 * maxlen / OCELOT_BUFFER_CELL_SZ; 1725 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_START, 1726 pause_start); 1727 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_STOP, 1728 pause_stop); 1729 1730 /* Tail dropping watermarks */ 1731 atop_tot = (ocelot->packet_buffer_size - 9 * maxlen) / 1732 OCELOT_BUFFER_CELL_SZ; 1733 atop = (9 * maxlen) / OCELOT_BUFFER_CELL_SZ; 1734 ocelot_write_rix(ocelot, ocelot->ops->wm_enc(atop), SYS_ATOP, port); 1735 ocelot_write(ocelot, ocelot->ops->wm_enc(atop_tot), SYS_ATOP_TOT_CFG); 1736 } 1737 EXPORT_SYMBOL(ocelot_port_set_maxlen); 1738 1739 int ocelot_get_max_mtu(struct ocelot *ocelot, int port) 1740 { 1741 int max_mtu = 65535 - ETH_HLEN - ETH_FCS_LEN; 1742 1743 if (port == ocelot->npi) { 1744 max_mtu -= OCELOT_TAG_LEN; 1745 1746 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT) 1747 max_mtu -= OCELOT_SHORT_PREFIX_LEN; 1748 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG) 1749 max_mtu -= OCELOT_LONG_PREFIX_LEN; 1750 } 1751 1752 return max_mtu; 1753 } 1754 EXPORT_SYMBOL(ocelot_get_max_mtu); 1755 1756 static void ocelot_port_set_learning(struct ocelot *ocelot, int port, 1757 bool enabled) 1758 { 1759 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1760 u32 val = 0; 1761 1762 if (enabled) 1763 val = ANA_PORT_PORT_CFG_LEARN_ENA; 1764 1765 ocelot_rmw_gix(ocelot, val, ANA_PORT_PORT_CFG_LEARN_ENA, 1766 ANA_PORT_PORT_CFG, port); 1767 1768 ocelot_port->learn_ena = enabled; 1769 } 1770 1771 static void ocelot_port_set_ucast_flood(struct ocelot *ocelot, int port, 1772 bool enabled) 1773 { 1774 u32 val = 0; 1775 1776 if (enabled) 1777 val = BIT(port); 1778 1779 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_UC); 1780 } 1781 1782 static void ocelot_port_set_mcast_flood(struct ocelot *ocelot, int port, 1783 bool enabled) 1784 { 1785 u32 val = 0; 1786 1787 if (enabled) 1788 val = BIT(port); 1789 1790 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MC); 1791 } 1792 1793 static void ocelot_port_set_bcast_flood(struct ocelot *ocelot, int port, 1794 bool enabled) 1795 { 1796 u32 val = 0; 1797 1798 if (enabled) 1799 val = BIT(port); 1800 1801 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_BC); 1802 } 1803 1804 int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port, 1805 struct switchdev_brport_flags flags) 1806 { 1807 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 1808 BR_BCAST_FLOOD)) 1809 return -EINVAL; 1810 1811 return 0; 1812 } 1813 EXPORT_SYMBOL(ocelot_port_pre_bridge_flags); 1814 1815 void ocelot_port_bridge_flags(struct ocelot *ocelot, int port, 1816 struct switchdev_brport_flags flags) 1817 { 1818 if (flags.mask & BR_LEARNING) 1819 ocelot_port_set_learning(ocelot, port, 1820 !!(flags.val & BR_LEARNING)); 1821 1822 if (flags.mask & BR_FLOOD) 1823 ocelot_port_set_ucast_flood(ocelot, port, 1824 !!(flags.val & BR_FLOOD)); 1825 1826 if (flags.mask & BR_MCAST_FLOOD) 1827 ocelot_port_set_mcast_flood(ocelot, port, 1828 !!(flags.val & BR_MCAST_FLOOD)); 1829 1830 if (flags.mask & BR_BCAST_FLOOD) 1831 ocelot_port_set_bcast_flood(ocelot, port, 1832 !!(flags.val & BR_BCAST_FLOOD)); 1833 } 1834 EXPORT_SYMBOL(ocelot_port_bridge_flags); 1835 1836 void ocelot_init_port(struct ocelot *ocelot, int port) 1837 { 1838 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1839 1840 skb_queue_head_init(&ocelot_port->tx_skbs); 1841 spin_lock_init(&ocelot_port->ts_id_lock); 1842 1843 /* Basic L2 initialization */ 1844 1845 /* Set MAC IFG Gaps 1846 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0 1847 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5 1848 */ 1849 ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5), 1850 DEV_MAC_IFG_CFG); 1851 1852 /* Load seed (0) and set MAC HDX late collision */ 1853 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) | 1854 DEV_MAC_HDX_CFG_SEED_LOAD, 1855 DEV_MAC_HDX_CFG); 1856 mdelay(1); 1857 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67), 1858 DEV_MAC_HDX_CFG); 1859 1860 /* Set Max Length and maximum tags allowed */ 1861 ocelot_port_set_maxlen(ocelot, port, ETH_DATA_LEN); 1862 ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) | 1863 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA | 1864 DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA | 1865 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, 1866 DEV_MAC_TAGS_CFG); 1867 1868 /* Set SMAC of Pause frame (00:00:00:00:00:00) */ 1869 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG); 1870 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG); 1871 1872 /* Enable transmission of pause frames */ 1873 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1); 1874 1875 /* Drop frames with multicast source address */ 1876 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 1877 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 1878 ANA_PORT_DROP_CFG, port); 1879 1880 /* Set default VLAN and tag type to 8021Q. */ 1881 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q), 1882 REW_PORT_VLAN_CFG_PORT_TPID_M, 1883 REW_PORT_VLAN_CFG, port); 1884 1885 /* Disable source address learning for standalone mode */ 1886 ocelot_port_set_learning(ocelot, port, false); 1887 1888 /* Enable vcap lookups */ 1889 ocelot_vcap_enable(ocelot, port); 1890 } 1891 EXPORT_SYMBOL(ocelot_init_port); 1892 1893 /* Configure and enable the CPU port module, which is a set of queues 1894 * accessible through register MMIO, frame DMA or Ethernet (in case 1895 * NPI mode is used). 1896 */ 1897 static void ocelot_cpu_port_init(struct ocelot *ocelot) 1898 { 1899 int cpu = ocelot->num_phys_ports; 1900 1901 /* The unicast destination PGID for the CPU port module is unused */ 1902 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu); 1903 /* Instead set up a multicast destination PGID for traffic copied to 1904 * the CPU. Whitelisted MAC addresses like the port netdevice MAC 1905 * addresses will be copied to the CPU via this PGID. 1906 */ 1907 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU); 1908 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA | 1909 ANA_PORT_PORT_CFG_PORTID_VAL(cpu), 1910 ANA_PORT_PORT_CFG, cpu); 1911 1912 /* Enable CPU port module */ 1913 ocelot_fields_write(ocelot, cpu, QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 1914 /* CPU port Injection/Extraction configuration */ 1915 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_XTR_HDR, 1916 OCELOT_TAG_PREFIX_NONE); 1917 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_INJ_HDR, 1918 OCELOT_TAG_PREFIX_NONE); 1919 1920 /* Configure the CPU port to be VLAN aware */ 1921 ocelot_write_gix(ocelot, ANA_PORT_VLAN_CFG_VLAN_VID(0) | 1922 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 1923 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1), 1924 ANA_PORT_VLAN_CFG, cpu); 1925 } 1926 1927 static void ocelot_detect_features(struct ocelot *ocelot) 1928 { 1929 int mmgt, eq_ctrl; 1930 1931 /* For Ocelot, Felix, Seville, Serval etc, SYS:MMGT:MMGT:FREECNT holds 1932 * the number of 240-byte free memory words (aka 4-cell chunks) and not 1933 * 192 bytes as the documentation incorrectly says. 1934 */ 1935 mmgt = ocelot_read(ocelot, SYS_MMGT); 1936 ocelot->packet_buffer_size = 240 * SYS_MMGT_FREECNT(mmgt); 1937 1938 eq_ctrl = ocelot_read(ocelot, QSYS_EQ_CTRL); 1939 ocelot->num_frame_refs = QSYS_MMGT_EQ_CTRL_FP_FREE_CNT(eq_ctrl); 1940 } 1941 1942 int ocelot_init(struct ocelot *ocelot) 1943 { 1944 char queue_name[32]; 1945 int i, ret; 1946 u32 port; 1947 1948 if (ocelot->ops->reset) { 1949 ret = ocelot->ops->reset(ocelot); 1950 if (ret) { 1951 dev_err(ocelot->dev, "Switch reset failed\n"); 1952 return ret; 1953 } 1954 } 1955 1956 ocelot->stats = devm_kcalloc(ocelot->dev, 1957 ocelot->num_phys_ports * ocelot->num_stats, 1958 sizeof(u64), GFP_KERNEL); 1959 if (!ocelot->stats) 1960 return -ENOMEM; 1961 1962 mutex_init(&ocelot->stats_lock); 1963 mutex_init(&ocelot->ptp_lock); 1964 spin_lock_init(&ocelot->ptp_clock_lock); 1965 snprintf(queue_name, sizeof(queue_name), "%s-stats", 1966 dev_name(ocelot->dev)); 1967 ocelot->stats_queue = create_singlethread_workqueue(queue_name); 1968 if (!ocelot->stats_queue) 1969 return -ENOMEM; 1970 1971 ocelot->owq = alloc_ordered_workqueue("ocelot-owq", 0); 1972 if (!ocelot->owq) { 1973 destroy_workqueue(ocelot->stats_queue); 1974 return -ENOMEM; 1975 } 1976 1977 INIT_LIST_HEAD(&ocelot->multicast); 1978 INIT_LIST_HEAD(&ocelot->pgids); 1979 ocelot_detect_features(ocelot); 1980 ocelot_mact_init(ocelot); 1981 ocelot_vlan_init(ocelot); 1982 ocelot_vcap_init(ocelot); 1983 ocelot_cpu_port_init(ocelot); 1984 1985 for (port = 0; port < ocelot->num_phys_ports; port++) { 1986 /* Clear all counters (5 groups) */ 1987 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) | 1988 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f), 1989 SYS_STAT_CFG); 1990 } 1991 1992 /* Only use S-Tag */ 1993 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG); 1994 1995 /* Aggregation mode */ 1996 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA | 1997 ANA_AGGR_CFG_AC_DMAC_ENA | 1998 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA | 1999 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA | 2000 ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA | 2001 ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA, 2002 ANA_AGGR_CFG); 2003 2004 /* Set MAC age time to default value. The entry is aged after 2005 * 2*AGE_PERIOD 2006 */ 2007 ocelot_write(ocelot, 2008 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ), 2009 ANA_AUTOAGE); 2010 2011 /* Disable learning for frames discarded by VLAN ingress filtering */ 2012 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1); 2013 2014 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */ 2015 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA | 2016 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING); 2017 2018 /* Setup flooding PGIDs */ 2019 for (i = 0; i < ocelot->num_flooding_pgids; i++) 2020 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) | 2021 ANA_FLOODING_FLD_BROADCAST(PGID_BC) | 2022 ANA_FLOODING_FLD_UNICAST(PGID_UC), 2023 ANA_FLOODING, i); 2024 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) | 2025 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) | 2026 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) | 2027 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC), 2028 ANA_FLOODING_IPMC); 2029 2030 for (port = 0; port < ocelot->num_phys_ports; port++) { 2031 /* Transmit the frame to the local port. */ 2032 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 2033 /* Do not forward BPDU frames to the front ports. */ 2034 ocelot_write_gix(ocelot, 2035 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff), 2036 ANA_PORT_CPU_FWD_BPDU_CFG, 2037 port); 2038 /* Ensure bridging is disabled */ 2039 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port); 2040 } 2041 2042 for_each_nonreserved_multicast_dest_pgid(ocelot, i) { 2043 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0)); 2044 2045 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 2046 } 2047 2048 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_BLACKHOLE); 2049 2050 /* Allow broadcast and unknown L2 multicast to the CPU. */ 2051 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2052 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2053 ANA_PGID_PGID, PGID_MC); 2054 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2055 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2056 ANA_PGID_PGID, PGID_BC); 2057 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4); 2058 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6); 2059 2060 /* Allow manual injection via DEVCPU_QS registers, and byte swap these 2061 * registers endianness. 2062 */ 2063 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP | 2064 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0); 2065 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP | 2066 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0); 2067 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) | 2068 ANA_CPUQ_CFG_CPUQ_LRN(2) | 2069 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) | 2070 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) | 2071 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) | 2072 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) | 2073 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) | 2074 ANA_CPUQ_CFG_CPUQ_IGMP(6) | 2075 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG); 2076 for (i = 0; i < 16; i++) 2077 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) | 2078 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6), 2079 ANA_CPUQ_8021_CFG, i); 2080 2081 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats_work); 2082 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 2083 OCELOT_STATS_CHECK_DELAY); 2084 2085 return 0; 2086 } 2087 EXPORT_SYMBOL(ocelot_init); 2088 2089 void ocelot_deinit(struct ocelot *ocelot) 2090 { 2091 cancel_delayed_work(&ocelot->stats_work); 2092 destroy_workqueue(ocelot->stats_queue); 2093 destroy_workqueue(ocelot->owq); 2094 mutex_destroy(&ocelot->stats_lock); 2095 } 2096 EXPORT_SYMBOL(ocelot_deinit); 2097 2098 void ocelot_deinit_port(struct ocelot *ocelot, int port) 2099 { 2100 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2101 2102 skb_queue_purge(&ocelot_port->tx_skbs); 2103 } 2104 EXPORT_SYMBOL(ocelot_deinit_port); 2105 2106 MODULE_LICENSE("Dual MIT/GPL"); 2107