1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7 #include <linux/if_bridge.h> 8 #include "ocelot.h" 9 #include "ocelot_vcap.h" 10 11 #define TABLE_UPDATE_SLEEP_US 10 12 #define TABLE_UPDATE_TIMEOUT_US 100000 13 14 struct ocelot_mact_entry { 15 u8 mac[ETH_ALEN]; 16 u16 vid; 17 enum macaccess_entry_type type; 18 }; 19 20 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot) 21 { 22 return ocelot_read(ocelot, ANA_TABLES_MACACCESS); 23 } 24 25 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot) 26 { 27 u32 val; 28 29 return readx_poll_timeout(ocelot_mact_read_macaccess, 30 ocelot, val, 31 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) == 32 MACACCESS_CMD_IDLE, 33 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 34 } 35 36 static void ocelot_mact_select(struct ocelot *ocelot, 37 const unsigned char mac[ETH_ALEN], 38 unsigned int vid) 39 { 40 u32 macl = 0, mach = 0; 41 42 /* Set the MAC address to handle and the vlan associated in a format 43 * understood by the hardware. 44 */ 45 mach |= vid << 16; 46 mach |= mac[0] << 8; 47 mach |= mac[1] << 0; 48 macl |= mac[2] << 24; 49 macl |= mac[3] << 16; 50 macl |= mac[4] << 8; 51 macl |= mac[5] << 0; 52 53 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA); 54 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA); 55 56 } 57 58 int ocelot_mact_learn(struct ocelot *ocelot, int port, 59 const unsigned char mac[ETH_ALEN], 60 unsigned int vid, enum macaccess_entry_type type) 61 { 62 ocelot_mact_select(ocelot, mac, vid); 63 64 /* Issue a write command */ 65 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID | 66 ANA_TABLES_MACACCESS_DEST_IDX(port) | 67 ANA_TABLES_MACACCESS_ENTRYTYPE(type) | 68 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN), 69 ANA_TABLES_MACACCESS); 70 71 return ocelot_mact_wait_for_completion(ocelot); 72 } 73 EXPORT_SYMBOL(ocelot_mact_learn); 74 75 int ocelot_mact_forget(struct ocelot *ocelot, 76 const unsigned char mac[ETH_ALEN], unsigned int vid) 77 { 78 ocelot_mact_select(ocelot, mac, vid); 79 80 /* Issue a forget command */ 81 ocelot_write(ocelot, 82 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET), 83 ANA_TABLES_MACACCESS); 84 85 return ocelot_mact_wait_for_completion(ocelot); 86 } 87 EXPORT_SYMBOL(ocelot_mact_forget); 88 89 static void ocelot_mact_init(struct ocelot *ocelot) 90 { 91 /* Configure the learning mode entries attributes: 92 * - Do not copy the frame to the CPU extraction queues. 93 * - Use the vlan and mac_cpoy for dmac lookup. 94 */ 95 ocelot_rmw(ocelot, 0, 96 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS 97 | ANA_AGENCTRL_LEARN_FWD_KILL 98 | ANA_AGENCTRL_LEARN_IGNORE_VLAN, 99 ANA_AGENCTRL); 100 101 /* Clear the MAC table */ 102 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS); 103 } 104 105 static void ocelot_vcap_enable(struct ocelot *ocelot, int port) 106 { 107 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA | 108 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa), 109 ANA_PORT_VCAP_S2_CFG, port); 110 } 111 112 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot) 113 { 114 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS); 115 } 116 117 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot) 118 { 119 u32 val; 120 121 return readx_poll_timeout(ocelot_vlant_read_vlanaccess, 122 ocelot, 123 val, 124 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) == 125 ANA_TABLES_VLANACCESS_CMD_IDLE, 126 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 127 } 128 129 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask) 130 { 131 /* Select the VID to configure */ 132 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid), 133 ANA_TABLES_VLANTIDX); 134 /* Set the vlan port members mask and issue a write command */ 135 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) | 136 ANA_TABLES_VLANACCESS_CMD_WRITE, 137 ANA_TABLES_VLANACCESS); 138 139 return ocelot_vlant_wait_for_completion(ocelot); 140 } 141 142 static int ocelot_port_set_native_vlan(struct ocelot *ocelot, int port, 143 u16 vid) 144 { 145 struct ocelot_port *ocelot_port = ocelot->ports[port]; 146 u32 val = 0; 147 148 if (ocelot_port->vid != vid) { 149 /* Always permit deleting the native VLAN (vid = 0) */ 150 if (ocelot_port->vid && vid) { 151 dev_err(ocelot->dev, 152 "Port already has a native VLAN: %d\n", 153 ocelot_port->vid); 154 return -EBUSY; 155 } 156 ocelot_port->vid = vid; 157 } 158 159 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_VID(vid), 160 REW_PORT_VLAN_CFG_PORT_VID_M, 161 REW_PORT_VLAN_CFG, port); 162 163 if (ocelot_port->vlan_aware && !ocelot_port->vid) 164 /* If port is vlan-aware and tagged, drop untagged and priority 165 * tagged frames. 166 */ 167 val = ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA | 168 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 169 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA; 170 ocelot_rmw_gix(ocelot, val, 171 ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA | 172 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 173 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, 174 ANA_PORT_DROP_CFG, port); 175 176 if (ocelot_port->vlan_aware) { 177 if (ocelot_port->vid) 178 /* Tag all frames except when VID == DEFAULT_VLAN */ 179 val = REW_TAG_CFG_TAG_CFG(1); 180 else 181 /* Tag all frames */ 182 val = REW_TAG_CFG_TAG_CFG(3); 183 } else { 184 /* Port tagging disabled. */ 185 val = REW_TAG_CFG_TAG_CFG(0); 186 } 187 ocelot_rmw_gix(ocelot, val, 188 REW_TAG_CFG_TAG_CFG_M, 189 REW_TAG_CFG, port); 190 191 return 0; 192 } 193 194 void ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, 195 bool vlan_aware) 196 { 197 struct ocelot_port *ocelot_port = ocelot->ports[port]; 198 u32 val; 199 200 ocelot_port->vlan_aware = vlan_aware; 201 202 if (vlan_aware) 203 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 204 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1); 205 else 206 val = 0; 207 ocelot_rmw_gix(ocelot, val, 208 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 209 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M, 210 ANA_PORT_VLAN_CFG, port); 211 212 ocelot_port_set_native_vlan(ocelot, port, ocelot_port->vid); 213 } 214 EXPORT_SYMBOL(ocelot_port_vlan_filtering); 215 216 /* Default vlan to clasify for untagged frames (may be zero) */ 217 static void ocelot_port_set_pvid(struct ocelot *ocelot, int port, u16 pvid) 218 { 219 struct ocelot_port *ocelot_port = ocelot->ports[port]; 220 221 ocelot_rmw_gix(ocelot, 222 ANA_PORT_VLAN_CFG_VLAN_VID(pvid), 223 ANA_PORT_VLAN_CFG_VLAN_VID_M, 224 ANA_PORT_VLAN_CFG, port); 225 226 ocelot_port->pvid = pvid; 227 } 228 229 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid, 230 bool untagged) 231 { 232 int ret; 233 234 /* Make the port a member of the VLAN */ 235 ocelot->vlan_mask[vid] |= BIT(port); 236 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 237 if (ret) 238 return ret; 239 240 /* Default ingress vlan classification */ 241 if (pvid) 242 ocelot_port_set_pvid(ocelot, port, vid); 243 244 /* Untagged egress vlan clasification */ 245 if (untagged) { 246 ret = ocelot_port_set_native_vlan(ocelot, port, vid); 247 if (ret) 248 return ret; 249 } 250 251 return 0; 252 } 253 EXPORT_SYMBOL(ocelot_vlan_add); 254 255 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid) 256 { 257 struct ocelot_port *ocelot_port = ocelot->ports[port]; 258 int ret; 259 260 /* Stop the port from being a member of the vlan */ 261 ocelot->vlan_mask[vid] &= ~BIT(port); 262 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 263 if (ret) 264 return ret; 265 266 /* Ingress */ 267 if (ocelot_port->pvid == vid) 268 ocelot_port_set_pvid(ocelot, port, 0); 269 270 /* Egress */ 271 if (ocelot_port->vid == vid) 272 ocelot_port_set_native_vlan(ocelot, port, 0); 273 274 return 0; 275 } 276 EXPORT_SYMBOL(ocelot_vlan_del); 277 278 static void ocelot_vlan_init(struct ocelot *ocelot) 279 { 280 u16 port, vid; 281 282 /* Clear VLAN table, by default all ports are members of all VLANs */ 283 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT, 284 ANA_TABLES_VLANACCESS); 285 ocelot_vlant_wait_for_completion(ocelot); 286 287 /* Configure the port VLAN memberships */ 288 for (vid = 1; vid < VLAN_N_VID; vid++) { 289 ocelot->vlan_mask[vid] = 0; 290 ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 291 } 292 293 /* Because VLAN filtering is enabled, we need VID 0 to get untagged 294 * traffic. It is added automatically if 8021q module is loaded, but 295 * we can't rely on it since module may be not loaded. 296 */ 297 ocelot->vlan_mask[0] = GENMASK(ocelot->num_phys_ports - 1, 0); 298 ocelot_vlant_set_mask(ocelot, 0, ocelot->vlan_mask[0]); 299 300 /* Set vlan ingress filter mask to all ports but the CPU port by 301 * default. 302 */ 303 ocelot_write(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 304 ANA_VLANMASK); 305 306 for (port = 0; port < ocelot->num_phys_ports; port++) { 307 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port); 308 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port); 309 } 310 } 311 312 /* Watermark encode 313 * Bit 8: Unit; 0:1, 1:16 314 * Bit 7-0: Value to be multiplied with unit 315 */ 316 static u16 ocelot_wm_enc(u16 value) 317 { 318 if (value >= BIT(8)) 319 return BIT(8) | (value / 16); 320 321 return value; 322 } 323 324 void ocelot_adjust_link(struct ocelot *ocelot, int port, 325 struct phy_device *phydev) 326 { 327 struct ocelot_port *ocelot_port = ocelot->ports[port]; 328 int speed, mode = 0; 329 330 switch (phydev->speed) { 331 case SPEED_10: 332 speed = OCELOT_SPEED_10; 333 break; 334 case SPEED_100: 335 speed = OCELOT_SPEED_100; 336 break; 337 case SPEED_1000: 338 speed = OCELOT_SPEED_1000; 339 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 340 break; 341 case SPEED_2500: 342 speed = OCELOT_SPEED_2500; 343 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 344 break; 345 default: 346 dev_err(ocelot->dev, "Unsupported PHY speed on port %d: %d\n", 347 port, phydev->speed); 348 return; 349 } 350 351 phy_print_status(phydev); 352 353 if (!phydev->link) 354 return; 355 356 /* Only full duplex supported for now */ 357 ocelot_port_writel(ocelot_port, DEV_MAC_MODE_CFG_FDX_ENA | 358 mode, DEV_MAC_MODE_CFG); 359 360 /* Disable HDX fast control */ 361 ocelot_port_writel(ocelot_port, DEV_PORT_MISC_HDX_FAST_DIS, 362 DEV_PORT_MISC); 363 364 /* SGMII only for now */ 365 ocelot_port_writel(ocelot_port, PCS1G_MODE_CFG_SGMII_MODE_ENA, 366 PCS1G_MODE_CFG); 367 ocelot_port_writel(ocelot_port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG); 368 369 /* Enable PCS */ 370 ocelot_port_writel(ocelot_port, PCS1G_CFG_PCS_ENA, PCS1G_CFG); 371 372 /* No aneg on SGMII */ 373 ocelot_port_writel(ocelot_port, 0, PCS1G_ANEG_CFG); 374 375 /* No loopback */ 376 ocelot_port_writel(ocelot_port, 0, PCS1G_LB_CFG); 377 378 /* Enable MAC module */ 379 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA | 380 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG); 381 382 /* Take MAC, Port, Phy (intern) and PCS (SGMII/Serdes) clock out of 383 * reset */ 384 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(speed), 385 DEV_CLOCK_CFG); 386 387 /* No PFC */ 388 ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed), 389 ANA_PFC_PFC_CFG, port); 390 391 /* Core: Enable port for frame transfer */ 392 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE | 393 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) | 394 QSYS_SWITCH_PORT_MODE_PORT_ENA, 395 QSYS_SWITCH_PORT_MODE, port); 396 397 /* Flow control */ 398 ocelot_write_rix(ocelot, SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) | 399 SYS_MAC_FC_CFG_RX_FC_ENA | SYS_MAC_FC_CFG_TX_FC_ENA | 400 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA | 401 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) | 402 SYS_MAC_FC_CFG_FC_LINK_SPEED(speed), 403 SYS_MAC_FC_CFG, port); 404 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port); 405 } 406 EXPORT_SYMBOL(ocelot_adjust_link); 407 408 void ocelot_port_enable(struct ocelot *ocelot, int port, 409 struct phy_device *phy) 410 { 411 /* Enable receiving frames on the port, and activate auto-learning of 412 * MAC addresses. 413 */ 414 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO | 415 ANA_PORT_PORT_CFG_RECV_ENA | 416 ANA_PORT_PORT_CFG_PORTID_VAL(port), 417 ANA_PORT_PORT_CFG, port); 418 } 419 EXPORT_SYMBOL(ocelot_port_enable); 420 421 void ocelot_port_disable(struct ocelot *ocelot, int port) 422 { 423 struct ocelot_port *ocelot_port = ocelot->ports[port]; 424 425 ocelot_port_writel(ocelot_port, 0, DEV_MAC_ENA_CFG); 426 ocelot_rmw_rix(ocelot, 0, QSYS_SWITCH_PORT_MODE_PORT_ENA, 427 QSYS_SWITCH_PORT_MODE, port); 428 } 429 EXPORT_SYMBOL(ocelot_port_disable); 430 431 int ocelot_port_add_txtstamp_skb(struct ocelot_port *ocelot_port, 432 struct sk_buff *skb) 433 { 434 struct skb_shared_info *shinfo = skb_shinfo(skb); 435 struct ocelot *ocelot = ocelot_port->ocelot; 436 437 if (ocelot->ptp && shinfo->tx_flags & SKBTX_HW_TSTAMP && 438 ocelot_port->ptp_cmd == IFH_REW_OP_TWO_STEP_PTP) { 439 shinfo->tx_flags |= SKBTX_IN_PROGRESS; 440 /* Store timestamp ID in cb[0] of sk_buff */ 441 skb->cb[0] = ocelot_port->ts_id % 4; 442 skb_queue_tail(&ocelot_port->tx_skbs, skb); 443 return 0; 444 } 445 return -ENODATA; 446 } 447 EXPORT_SYMBOL(ocelot_port_add_txtstamp_skb); 448 449 static void ocelot_get_hwtimestamp(struct ocelot *ocelot, 450 struct timespec64 *ts) 451 { 452 unsigned long flags; 453 u32 val; 454 455 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); 456 457 /* Read current PTP time to get seconds */ 458 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 459 460 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 461 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE); 462 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 463 ts->tv_sec = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN); 464 465 /* Read packet HW timestamp from FIFO */ 466 val = ocelot_read(ocelot, SYS_PTP_TXSTAMP); 467 ts->tv_nsec = SYS_PTP_TXSTAMP_PTP_TXSTAMP(val); 468 469 /* Sec has incremented since the ts was registered */ 470 if ((ts->tv_sec & 0x1) != !!(val & SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC)) 471 ts->tv_sec--; 472 473 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 474 } 475 476 void ocelot_get_txtstamp(struct ocelot *ocelot) 477 { 478 int budget = OCELOT_PTP_QUEUE_SZ; 479 480 while (budget--) { 481 struct sk_buff *skb, *skb_tmp, *skb_match = NULL; 482 struct skb_shared_hwtstamps shhwtstamps; 483 struct ocelot_port *port; 484 struct timespec64 ts; 485 unsigned long flags; 486 u32 val, id, txport; 487 488 val = ocelot_read(ocelot, SYS_PTP_STATUS); 489 490 /* Check if a timestamp can be retrieved */ 491 if (!(val & SYS_PTP_STATUS_PTP_MESS_VLD)) 492 break; 493 494 WARN_ON(val & SYS_PTP_STATUS_PTP_OVFL); 495 496 /* Retrieve the ts ID and Tx port */ 497 id = SYS_PTP_STATUS_PTP_MESS_ID_X(val); 498 txport = SYS_PTP_STATUS_PTP_MESS_TXPORT_X(val); 499 500 /* Retrieve its associated skb */ 501 port = ocelot->ports[txport]; 502 503 spin_lock_irqsave(&port->tx_skbs.lock, flags); 504 505 skb_queue_walk_safe(&port->tx_skbs, skb, skb_tmp) { 506 if (skb->cb[0] != id) 507 continue; 508 __skb_unlink(skb, &port->tx_skbs); 509 skb_match = skb; 510 break; 511 } 512 513 spin_unlock_irqrestore(&port->tx_skbs.lock, flags); 514 515 /* Next ts */ 516 ocelot_write(ocelot, SYS_PTP_NXT_PTP_NXT, SYS_PTP_NXT); 517 518 if (unlikely(!skb_match)) 519 continue; 520 521 /* Get the h/w timestamp */ 522 ocelot_get_hwtimestamp(ocelot, &ts); 523 524 /* Set the timestamp into the skb */ 525 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 526 shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec); 527 skb_tstamp_tx(skb_match, &shhwtstamps); 528 529 dev_kfree_skb_any(skb_match); 530 } 531 } 532 EXPORT_SYMBOL(ocelot_get_txtstamp); 533 534 int ocelot_fdb_add(struct ocelot *ocelot, int port, 535 const unsigned char *addr, u16 vid) 536 { 537 struct ocelot_port *ocelot_port = ocelot->ports[port]; 538 int pgid = port; 539 540 if (port == ocelot->npi) 541 pgid = PGID_CPU; 542 543 if (!vid) { 544 if (!ocelot_port->vlan_aware) 545 /* If the bridge is not VLAN aware and no VID was 546 * provided, set it to pvid to ensure the MAC entry 547 * matches incoming untagged packets 548 */ 549 vid = ocelot_port->pvid; 550 else 551 /* If the bridge is VLAN aware a VID must be provided as 552 * otherwise the learnt entry wouldn't match any frame. 553 */ 554 return -EINVAL; 555 } 556 557 return ocelot_mact_learn(ocelot, pgid, addr, vid, ENTRYTYPE_LOCKED); 558 } 559 EXPORT_SYMBOL(ocelot_fdb_add); 560 561 int ocelot_fdb_del(struct ocelot *ocelot, int port, 562 const unsigned char *addr, u16 vid) 563 { 564 return ocelot_mact_forget(ocelot, addr, vid); 565 } 566 EXPORT_SYMBOL(ocelot_fdb_del); 567 568 int ocelot_port_fdb_do_dump(const unsigned char *addr, u16 vid, 569 bool is_static, void *data) 570 { 571 struct ocelot_dump_ctx *dump = data; 572 u32 portid = NETLINK_CB(dump->cb->skb).portid; 573 u32 seq = dump->cb->nlh->nlmsg_seq; 574 struct nlmsghdr *nlh; 575 struct ndmsg *ndm; 576 577 if (dump->idx < dump->cb->args[2]) 578 goto skip; 579 580 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH, 581 sizeof(*ndm), NLM_F_MULTI); 582 if (!nlh) 583 return -EMSGSIZE; 584 585 ndm = nlmsg_data(nlh); 586 ndm->ndm_family = AF_BRIDGE; 587 ndm->ndm_pad1 = 0; 588 ndm->ndm_pad2 = 0; 589 ndm->ndm_flags = NTF_SELF; 590 ndm->ndm_type = 0; 591 ndm->ndm_ifindex = dump->dev->ifindex; 592 ndm->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE; 593 594 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, addr)) 595 goto nla_put_failure; 596 597 if (vid && nla_put_u16(dump->skb, NDA_VLAN, vid)) 598 goto nla_put_failure; 599 600 nlmsg_end(dump->skb, nlh); 601 602 skip: 603 dump->idx++; 604 return 0; 605 606 nla_put_failure: 607 nlmsg_cancel(dump->skb, nlh); 608 return -EMSGSIZE; 609 } 610 EXPORT_SYMBOL(ocelot_port_fdb_do_dump); 611 612 static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col, 613 struct ocelot_mact_entry *entry) 614 { 615 u32 val, dst, macl, mach; 616 char mac[ETH_ALEN]; 617 618 /* Set row and column to read from */ 619 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row); 620 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col); 621 622 /* Issue a read command */ 623 ocelot_write(ocelot, 624 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 625 ANA_TABLES_MACACCESS); 626 627 if (ocelot_mact_wait_for_completion(ocelot)) 628 return -ETIMEDOUT; 629 630 /* Read the entry flags */ 631 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 632 if (!(val & ANA_TABLES_MACACCESS_VALID)) 633 return -EINVAL; 634 635 /* If the entry read has another port configured as its destination, 636 * do not report it. 637 */ 638 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3; 639 if (dst != port) 640 return -EINVAL; 641 642 /* Get the entry's MAC address and VLAN id */ 643 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA); 644 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA); 645 646 mac[0] = (mach >> 8) & 0xff; 647 mac[1] = (mach >> 0) & 0xff; 648 mac[2] = (macl >> 24) & 0xff; 649 mac[3] = (macl >> 16) & 0xff; 650 mac[4] = (macl >> 8) & 0xff; 651 mac[5] = (macl >> 0) & 0xff; 652 653 entry->vid = (mach >> 16) & 0xfff; 654 ether_addr_copy(entry->mac, mac); 655 656 return 0; 657 } 658 659 int ocelot_fdb_dump(struct ocelot *ocelot, int port, 660 dsa_fdb_dump_cb_t *cb, void *data) 661 { 662 int i, j; 663 664 /* Loop through all the mac tables entries. */ 665 for (i = 0; i < ocelot->num_mact_rows; i++) { 666 for (j = 0; j < 4; j++) { 667 struct ocelot_mact_entry entry; 668 bool is_static; 669 int ret; 670 671 ret = ocelot_mact_read(ocelot, port, i, j, &entry); 672 /* If the entry is invalid (wrong port, invalid...), 673 * skip it. 674 */ 675 if (ret == -EINVAL) 676 continue; 677 else if (ret) 678 return ret; 679 680 is_static = (entry.type == ENTRYTYPE_LOCKED); 681 682 ret = cb(entry.mac, entry.vid, is_static, data); 683 if (ret) 684 return ret; 685 } 686 } 687 688 return 0; 689 } 690 EXPORT_SYMBOL(ocelot_fdb_dump); 691 692 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr) 693 { 694 return copy_to_user(ifr->ifr_data, &ocelot->hwtstamp_config, 695 sizeof(ocelot->hwtstamp_config)) ? -EFAULT : 0; 696 } 697 EXPORT_SYMBOL(ocelot_hwstamp_get); 698 699 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr) 700 { 701 struct ocelot_port *ocelot_port = ocelot->ports[port]; 702 struct hwtstamp_config cfg; 703 704 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 705 return -EFAULT; 706 707 /* reserved for future extensions */ 708 if (cfg.flags) 709 return -EINVAL; 710 711 /* Tx type sanity check */ 712 switch (cfg.tx_type) { 713 case HWTSTAMP_TX_ON: 714 ocelot_port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP; 715 break; 716 case HWTSTAMP_TX_ONESTEP_SYNC: 717 /* IFH_REW_OP_ONE_STEP_PTP updates the correctional field, we 718 * need to update the origin time. 719 */ 720 ocelot_port->ptp_cmd = IFH_REW_OP_ORIGIN_PTP; 721 break; 722 case HWTSTAMP_TX_OFF: 723 ocelot_port->ptp_cmd = 0; 724 break; 725 default: 726 return -ERANGE; 727 } 728 729 mutex_lock(&ocelot->ptp_lock); 730 731 switch (cfg.rx_filter) { 732 case HWTSTAMP_FILTER_NONE: 733 break; 734 case HWTSTAMP_FILTER_ALL: 735 case HWTSTAMP_FILTER_SOME: 736 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 737 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 738 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 739 case HWTSTAMP_FILTER_NTP_ALL: 740 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 741 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 742 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 743 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 744 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 745 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 746 case HWTSTAMP_FILTER_PTP_V2_EVENT: 747 case HWTSTAMP_FILTER_PTP_V2_SYNC: 748 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 749 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 750 break; 751 default: 752 mutex_unlock(&ocelot->ptp_lock); 753 return -ERANGE; 754 } 755 756 /* Commit back the result & save it */ 757 memcpy(&ocelot->hwtstamp_config, &cfg, sizeof(cfg)); 758 mutex_unlock(&ocelot->ptp_lock); 759 760 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 761 } 762 EXPORT_SYMBOL(ocelot_hwstamp_set); 763 764 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data) 765 { 766 int i; 767 768 if (sset != ETH_SS_STATS) 769 return; 770 771 for (i = 0; i < ocelot->num_stats; i++) 772 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name, 773 ETH_GSTRING_LEN); 774 } 775 EXPORT_SYMBOL(ocelot_get_strings); 776 777 static void ocelot_update_stats(struct ocelot *ocelot) 778 { 779 int i, j; 780 781 mutex_lock(&ocelot->stats_lock); 782 783 for (i = 0; i < ocelot->num_phys_ports; i++) { 784 /* Configure the port to read the stats from */ 785 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(i), SYS_STAT_CFG); 786 787 for (j = 0; j < ocelot->num_stats; j++) { 788 u32 val; 789 unsigned int idx = i * ocelot->num_stats + j; 790 791 val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS, 792 ocelot->stats_layout[j].offset); 793 794 if (val < (ocelot->stats[idx] & U32_MAX)) 795 ocelot->stats[idx] += (u64)1 << 32; 796 797 ocelot->stats[idx] = (ocelot->stats[idx] & 798 ~(u64)U32_MAX) + val; 799 } 800 } 801 802 mutex_unlock(&ocelot->stats_lock); 803 } 804 805 static void ocelot_check_stats_work(struct work_struct *work) 806 { 807 struct delayed_work *del_work = to_delayed_work(work); 808 struct ocelot *ocelot = container_of(del_work, struct ocelot, 809 stats_work); 810 811 ocelot_update_stats(ocelot); 812 813 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 814 OCELOT_STATS_CHECK_DELAY); 815 } 816 817 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data) 818 { 819 int i; 820 821 /* check and update now */ 822 ocelot_update_stats(ocelot); 823 824 /* Copy all counters */ 825 for (i = 0; i < ocelot->num_stats; i++) 826 *data++ = ocelot->stats[port * ocelot->num_stats + i]; 827 } 828 EXPORT_SYMBOL(ocelot_get_ethtool_stats); 829 830 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset) 831 { 832 if (sset != ETH_SS_STATS) 833 return -EOPNOTSUPP; 834 835 return ocelot->num_stats; 836 } 837 EXPORT_SYMBOL(ocelot_get_sset_count); 838 839 int ocelot_get_ts_info(struct ocelot *ocelot, int port, 840 struct ethtool_ts_info *info) 841 { 842 info->phc_index = ocelot->ptp_clock ? 843 ptp_clock_index(ocelot->ptp_clock) : -1; 844 if (info->phc_index == -1) { 845 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 846 SOF_TIMESTAMPING_RX_SOFTWARE | 847 SOF_TIMESTAMPING_SOFTWARE; 848 return 0; 849 } 850 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 851 SOF_TIMESTAMPING_RX_SOFTWARE | 852 SOF_TIMESTAMPING_SOFTWARE | 853 SOF_TIMESTAMPING_TX_HARDWARE | 854 SOF_TIMESTAMPING_RX_HARDWARE | 855 SOF_TIMESTAMPING_RAW_HARDWARE; 856 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON) | 857 BIT(HWTSTAMP_TX_ONESTEP_SYNC); 858 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL); 859 860 return 0; 861 } 862 EXPORT_SYMBOL(ocelot_get_ts_info); 863 864 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state) 865 { 866 u32 port_cfg; 867 int p, i; 868 869 if (!(BIT(port) & ocelot->bridge_mask)) 870 return; 871 872 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, port); 873 874 switch (state) { 875 case BR_STATE_FORWARDING: 876 ocelot->bridge_fwd_mask |= BIT(port); 877 /* Fallthrough */ 878 case BR_STATE_LEARNING: 879 port_cfg |= ANA_PORT_PORT_CFG_LEARN_ENA; 880 break; 881 882 default: 883 port_cfg &= ~ANA_PORT_PORT_CFG_LEARN_ENA; 884 ocelot->bridge_fwd_mask &= ~BIT(port); 885 break; 886 } 887 888 ocelot_write_gix(ocelot, port_cfg, ANA_PORT_PORT_CFG, port); 889 890 /* Apply FWD mask. The loop is needed to add/remove the current port as 891 * a source for the other ports. 892 */ 893 for (p = 0; p < ocelot->num_phys_ports; p++) { 894 if (ocelot->bridge_fwd_mask & BIT(p)) { 895 unsigned long mask = ocelot->bridge_fwd_mask & ~BIT(p); 896 897 for (i = 0; i < ocelot->num_phys_ports; i++) { 898 unsigned long bond_mask = ocelot->lags[i]; 899 900 if (!bond_mask) 901 continue; 902 903 if (bond_mask & BIT(p)) { 904 mask &= ~bond_mask; 905 break; 906 } 907 } 908 909 ocelot_write_rix(ocelot, mask, 910 ANA_PGID_PGID, PGID_SRC + p); 911 } else { 912 ocelot_write_rix(ocelot, 0, 913 ANA_PGID_PGID, PGID_SRC + p); 914 } 915 } 916 } 917 EXPORT_SYMBOL(ocelot_bridge_stp_state_set); 918 919 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs) 920 { 921 unsigned int age_period = ANA_AUTOAGE_AGE_PERIOD(msecs / 2000); 922 923 /* Setting AGE_PERIOD to zero effectively disables automatic aging, 924 * which is clearly not what our intention is. So avoid that. 925 */ 926 if (!age_period) 927 age_period = 1; 928 929 ocelot_rmw(ocelot, age_period, ANA_AUTOAGE_AGE_PERIOD_M, ANA_AUTOAGE); 930 } 931 EXPORT_SYMBOL(ocelot_set_ageing_time); 932 933 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot, 934 const unsigned char *addr, 935 u16 vid) 936 { 937 struct ocelot_multicast *mc; 938 939 list_for_each_entry(mc, &ocelot->multicast, list) { 940 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid) 941 return mc; 942 } 943 944 return NULL; 945 } 946 947 static enum macaccess_entry_type ocelot_classify_mdb(const unsigned char *addr) 948 { 949 if (addr[0] == 0x01 && addr[1] == 0x00 && addr[2] == 0x5e) 950 return ENTRYTYPE_MACv4; 951 if (addr[0] == 0x33 && addr[1] == 0x33) 952 return ENTRYTYPE_MACv6; 953 return ENTRYTYPE_NORMAL; 954 } 955 956 static int ocelot_mdb_get_pgid(struct ocelot *ocelot, 957 enum macaccess_entry_type entry_type) 958 { 959 int pgid; 960 961 /* According to VSC7514 datasheet 3.9.1.5 IPv4 Multicast Entries and 962 * 3.9.1.6 IPv6 Multicast Entries, "Instead of a lookup in the 963 * destination mask table (PGID), the destination set is programmed as 964 * part of the entry MAC address.", and the DEST_IDX is set to 0. 965 */ 966 if (entry_type == ENTRYTYPE_MACv4 || 967 entry_type == ENTRYTYPE_MACv6) 968 return 0; 969 970 for_each_nonreserved_multicast_dest_pgid(ocelot, pgid) { 971 struct ocelot_multicast *mc; 972 bool used = false; 973 974 list_for_each_entry(mc, &ocelot->multicast, list) { 975 if (mc->pgid == pgid) { 976 used = true; 977 break; 978 } 979 } 980 981 if (!used) 982 return pgid; 983 } 984 985 return -1; 986 } 987 988 static void ocelot_encode_ports_to_mdb(unsigned char *addr, 989 struct ocelot_multicast *mc, 990 enum macaccess_entry_type entry_type) 991 { 992 memcpy(addr, mc->addr, ETH_ALEN); 993 994 if (entry_type == ENTRYTYPE_MACv4) { 995 addr[0] = 0; 996 addr[1] = mc->ports >> 8; 997 addr[2] = mc->ports & 0xff; 998 } else if (entry_type == ENTRYTYPE_MACv6) { 999 addr[0] = mc->ports >> 8; 1000 addr[1] = mc->ports & 0xff; 1001 } 1002 } 1003 1004 int ocelot_port_mdb_add(struct ocelot *ocelot, int port, 1005 const struct switchdev_obj_port_mdb *mdb) 1006 { 1007 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1008 enum macaccess_entry_type entry_type; 1009 unsigned char addr[ETH_ALEN]; 1010 struct ocelot_multicast *mc; 1011 u16 vid = mdb->vid; 1012 bool new = false; 1013 1014 if (port == ocelot->npi) 1015 port = ocelot->num_phys_ports; 1016 1017 if (!vid) 1018 vid = ocelot_port->pvid; 1019 1020 entry_type = ocelot_classify_mdb(mdb->addr); 1021 1022 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1023 if (!mc) { 1024 int pgid = ocelot_mdb_get_pgid(ocelot, entry_type); 1025 1026 if (pgid < 0) { 1027 dev_err(ocelot->dev, 1028 "No more PGIDs available for mdb %pM vid %d\n", 1029 mdb->addr, vid); 1030 return -ENOSPC; 1031 } 1032 1033 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL); 1034 if (!mc) 1035 return -ENOMEM; 1036 1037 memcpy(mc->addr, mdb->addr, ETH_ALEN); 1038 mc->vid = vid; 1039 mc->pgid = pgid; 1040 1041 list_add_tail(&mc->list, &ocelot->multicast); 1042 new = true; 1043 } 1044 1045 if (!new) { 1046 ocelot_encode_ports_to_mdb(addr, mc, entry_type); 1047 ocelot_mact_forget(ocelot, addr, vid); 1048 } 1049 1050 mc->ports |= BIT(port); 1051 ocelot_encode_ports_to_mdb(addr, mc, entry_type); 1052 1053 return ocelot_mact_learn(ocelot, mc->pgid, addr, vid, entry_type); 1054 } 1055 EXPORT_SYMBOL(ocelot_port_mdb_add); 1056 1057 int ocelot_port_mdb_del(struct ocelot *ocelot, int port, 1058 const struct switchdev_obj_port_mdb *mdb) 1059 { 1060 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1061 enum macaccess_entry_type entry_type; 1062 unsigned char addr[ETH_ALEN]; 1063 struct ocelot_multicast *mc; 1064 u16 vid = mdb->vid; 1065 1066 if (port == ocelot->npi) 1067 port = ocelot->num_phys_ports; 1068 1069 if (!vid) 1070 vid = ocelot_port->pvid; 1071 1072 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1073 if (!mc) 1074 return -ENOENT; 1075 1076 entry_type = ocelot_classify_mdb(mdb->addr); 1077 1078 ocelot_encode_ports_to_mdb(addr, mc, entry_type); 1079 ocelot_mact_forget(ocelot, addr, vid); 1080 1081 mc->ports &= ~BIT(port); 1082 if (!mc->ports) { 1083 list_del(&mc->list); 1084 devm_kfree(ocelot->dev, mc); 1085 return 0; 1086 } 1087 1088 ocelot_encode_ports_to_mdb(addr, mc, entry_type); 1089 1090 return ocelot_mact_learn(ocelot, mc->pgid, addr, vid, entry_type); 1091 } 1092 EXPORT_SYMBOL(ocelot_port_mdb_del); 1093 1094 int ocelot_port_bridge_join(struct ocelot *ocelot, int port, 1095 struct net_device *bridge) 1096 { 1097 if (!ocelot->bridge_mask) { 1098 ocelot->hw_bridge_dev = bridge; 1099 } else { 1100 if (ocelot->hw_bridge_dev != bridge) 1101 /* This is adding the port to a second bridge, this is 1102 * unsupported */ 1103 return -ENODEV; 1104 } 1105 1106 ocelot->bridge_mask |= BIT(port); 1107 1108 return 0; 1109 } 1110 EXPORT_SYMBOL(ocelot_port_bridge_join); 1111 1112 int ocelot_port_bridge_leave(struct ocelot *ocelot, int port, 1113 struct net_device *bridge) 1114 { 1115 ocelot->bridge_mask &= ~BIT(port); 1116 1117 if (!ocelot->bridge_mask) 1118 ocelot->hw_bridge_dev = NULL; 1119 1120 ocelot_port_vlan_filtering(ocelot, port, 0); 1121 ocelot_port_set_pvid(ocelot, port, 0); 1122 return ocelot_port_set_native_vlan(ocelot, port, 0); 1123 } 1124 EXPORT_SYMBOL(ocelot_port_bridge_leave); 1125 1126 static void ocelot_set_aggr_pgids(struct ocelot *ocelot) 1127 { 1128 int i, port, lag; 1129 1130 /* Reset destination and aggregation PGIDS */ 1131 for_each_unicast_dest_pgid(ocelot, port) 1132 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 1133 1134 for_each_aggr_pgid(ocelot, i) 1135 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 1136 ANA_PGID_PGID, i); 1137 1138 /* Now, set PGIDs for each LAG */ 1139 for (lag = 0; lag < ocelot->num_phys_ports; lag++) { 1140 unsigned long bond_mask; 1141 int aggr_count = 0; 1142 u8 aggr_idx[16]; 1143 1144 bond_mask = ocelot->lags[lag]; 1145 if (!bond_mask) 1146 continue; 1147 1148 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) { 1149 // Destination mask 1150 ocelot_write_rix(ocelot, bond_mask, 1151 ANA_PGID_PGID, port); 1152 aggr_idx[aggr_count] = port; 1153 aggr_count++; 1154 } 1155 1156 for_each_aggr_pgid(ocelot, i) { 1157 u32 ac; 1158 1159 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i); 1160 ac &= ~bond_mask; 1161 ac |= BIT(aggr_idx[i % aggr_count]); 1162 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i); 1163 } 1164 } 1165 } 1166 1167 static void ocelot_setup_lag(struct ocelot *ocelot, int lag) 1168 { 1169 unsigned long bond_mask = ocelot->lags[lag]; 1170 unsigned int p; 1171 1172 for_each_set_bit(p, &bond_mask, ocelot->num_phys_ports) { 1173 u32 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, p); 1174 1175 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M; 1176 1177 /* Use lag port as logical port for port i */ 1178 ocelot_write_gix(ocelot, port_cfg | 1179 ANA_PORT_PORT_CFG_PORTID_VAL(lag), 1180 ANA_PORT_PORT_CFG, p); 1181 } 1182 } 1183 1184 int ocelot_port_lag_join(struct ocelot *ocelot, int port, 1185 struct net_device *bond) 1186 { 1187 struct net_device *ndev; 1188 u32 bond_mask = 0; 1189 int lag, lp; 1190 1191 rcu_read_lock(); 1192 for_each_netdev_in_bond_rcu(bond, ndev) { 1193 struct ocelot_port_private *priv = netdev_priv(ndev); 1194 1195 bond_mask |= BIT(priv->chip_port); 1196 } 1197 rcu_read_unlock(); 1198 1199 lp = __ffs(bond_mask); 1200 1201 /* If the new port is the lowest one, use it as the logical port from 1202 * now on 1203 */ 1204 if (port == lp) { 1205 lag = port; 1206 ocelot->lags[port] = bond_mask; 1207 bond_mask &= ~BIT(port); 1208 if (bond_mask) { 1209 lp = __ffs(bond_mask); 1210 ocelot->lags[lp] = 0; 1211 } 1212 } else { 1213 lag = lp; 1214 ocelot->lags[lp] |= BIT(port); 1215 } 1216 1217 ocelot_setup_lag(ocelot, lag); 1218 ocelot_set_aggr_pgids(ocelot); 1219 1220 return 0; 1221 } 1222 EXPORT_SYMBOL(ocelot_port_lag_join); 1223 1224 void ocelot_port_lag_leave(struct ocelot *ocelot, int port, 1225 struct net_device *bond) 1226 { 1227 u32 port_cfg; 1228 int i; 1229 1230 /* Remove port from any lag */ 1231 for (i = 0; i < ocelot->num_phys_ports; i++) 1232 ocelot->lags[i] &= ~BIT(port); 1233 1234 /* if it was the logical port of the lag, move the lag config to the 1235 * next port 1236 */ 1237 if (ocelot->lags[port]) { 1238 int n = __ffs(ocelot->lags[port]); 1239 1240 ocelot->lags[n] = ocelot->lags[port]; 1241 ocelot->lags[port] = 0; 1242 1243 ocelot_setup_lag(ocelot, n); 1244 } 1245 1246 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, port); 1247 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M; 1248 ocelot_write_gix(ocelot, port_cfg | ANA_PORT_PORT_CFG_PORTID_VAL(port), 1249 ANA_PORT_PORT_CFG, port); 1250 1251 ocelot_set_aggr_pgids(ocelot); 1252 } 1253 EXPORT_SYMBOL(ocelot_port_lag_leave); 1254 1255 /* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu. 1256 * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG. 1257 * In the special case that it's the NPI port that we're configuring, the 1258 * length of the tag and optional prefix needs to be accounted for privately, 1259 * in order to be able to sustain communication at the requested @sdu. 1260 */ 1261 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu) 1262 { 1263 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1264 int maxlen = sdu + ETH_HLEN + ETH_FCS_LEN; 1265 int atop_wm; 1266 1267 if (port == ocelot->npi) { 1268 maxlen += OCELOT_TAG_LEN; 1269 1270 if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_SHORT) 1271 maxlen += OCELOT_SHORT_PREFIX_LEN; 1272 else if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_LONG) 1273 maxlen += OCELOT_LONG_PREFIX_LEN; 1274 } 1275 1276 ocelot_port_writel(ocelot_port, maxlen, DEV_MAC_MAXLEN_CFG); 1277 1278 /* Set Pause WM hysteresis 1279 * 152 = 6 * maxlen / OCELOT_BUFFER_CELL_SZ 1280 * 101 = 4 * maxlen / OCELOT_BUFFER_CELL_SZ 1281 */ 1282 ocelot_write_rix(ocelot, SYS_PAUSE_CFG_PAUSE_ENA | 1283 SYS_PAUSE_CFG_PAUSE_STOP(101) | 1284 SYS_PAUSE_CFG_PAUSE_START(152), SYS_PAUSE_CFG, port); 1285 1286 /* Tail dropping watermark */ 1287 atop_wm = (ocelot->shared_queue_sz - 9 * maxlen) / 1288 OCELOT_BUFFER_CELL_SZ; 1289 ocelot_write_rix(ocelot, ocelot_wm_enc(9 * maxlen), 1290 SYS_ATOP, port); 1291 ocelot_write(ocelot, ocelot_wm_enc(atop_wm), SYS_ATOP_TOT_CFG); 1292 } 1293 EXPORT_SYMBOL(ocelot_port_set_maxlen); 1294 1295 int ocelot_get_max_mtu(struct ocelot *ocelot, int port) 1296 { 1297 int max_mtu = 65535 - ETH_HLEN - ETH_FCS_LEN; 1298 1299 if (port == ocelot->npi) { 1300 max_mtu -= OCELOT_TAG_LEN; 1301 1302 if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_SHORT) 1303 max_mtu -= OCELOT_SHORT_PREFIX_LEN; 1304 else if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_LONG) 1305 max_mtu -= OCELOT_LONG_PREFIX_LEN; 1306 } 1307 1308 return max_mtu; 1309 } 1310 EXPORT_SYMBOL(ocelot_get_max_mtu); 1311 1312 void ocelot_init_port(struct ocelot *ocelot, int port) 1313 { 1314 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1315 1316 skb_queue_head_init(&ocelot_port->tx_skbs); 1317 1318 /* Basic L2 initialization */ 1319 1320 /* Set MAC IFG Gaps 1321 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0 1322 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5 1323 */ 1324 ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5), 1325 DEV_MAC_IFG_CFG); 1326 1327 /* Load seed (0) and set MAC HDX late collision */ 1328 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) | 1329 DEV_MAC_HDX_CFG_SEED_LOAD, 1330 DEV_MAC_HDX_CFG); 1331 mdelay(1); 1332 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67), 1333 DEV_MAC_HDX_CFG); 1334 1335 /* Set Max Length and maximum tags allowed */ 1336 ocelot_port_set_maxlen(ocelot, port, ETH_DATA_LEN); 1337 ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) | 1338 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA | 1339 DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA | 1340 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, 1341 DEV_MAC_TAGS_CFG); 1342 1343 /* Set SMAC of Pause frame (00:00:00:00:00:00) */ 1344 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG); 1345 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG); 1346 1347 /* Drop frames with multicast source address */ 1348 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 1349 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 1350 ANA_PORT_DROP_CFG, port); 1351 1352 /* Set default VLAN and tag type to 8021Q. */ 1353 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q), 1354 REW_PORT_VLAN_CFG_PORT_TPID_M, 1355 REW_PORT_VLAN_CFG, port); 1356 1357 /* Enable vcap lookups */ 1358 ocelot_vcap_enable(ocelot, port); 1359 } 1360 EXPORT_SYMBOL(ocelot_init_port); 1361 1362 /* Configure and enable the CPU port module, which is a set of queues. 1363 * If @npi contains a valid port index, the CPU port module is connected 1364 * to the Node Processor Interface (NPI). This is the mode through which 1365 * frames can be injected from and extracted to an external CPU, 1366 * over Ethernet. 1367 */ 1368 void ocelot_configure_cpu(struct ocelot *ocelot, int npi, 1369 enum ocelot_tag_prefix injection, 1370 enum ocelot_tag_prefix extraction) 1371 { 1372 int cpu = ocelot->num_phys_ports; 1373 1374 ocelot->npi = npi; 1375 ocelot->inj_prefix = injection; 1376 ocelot->xtr_prefix = extraction; 1377 1378 /* The unicast destination PGID for the CPU port module is unused */ 1379 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu); 1380 /* Instead set up a multicast destination PGID for traffic copied to 1381 * the CPU. Whitelisted MAC addresses like the port netdevice MAC 1382 * addresses will be copied to the CPU via this PGID. 1383 */ 1384 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU); 1385 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA | 1386 ANA_PORT_PORT_CFG_PORTID_VAL(cpu), 1387 ANA_PORT_PORT_CFG, cpu); 1388 1389 if (npi >= 0 && npi < ocelot->num_phys_ports) { 1390 ocelot_write(ocelot, QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M | 1391 QSYS_EXT_CPU_CFG_EXT_CPU_PORT(npi), 1392 QSYS_EXT_CPU_CFG); 1393 1394 /* Enable NPI port */ 1395 ocelot_write_rix(ocelot, 1396 QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE | 1397 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) | 1398 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1399 QSYS_SWITCH_PORT_MODE, npi); 1400 /* NPI port Injection/Extraction configuration */ 1401 ocelot_write_rix(ocelot, 1402 SYS_PORT_MODE_INCL_XTR_HDR(extraction) | 1403 SYS_PORT_MODE_INCL_INJ_HDR(injection), 1404 SYS_PORT_MODE, npi); 1405 } 1406 1407 /* Enable CPU port module */ 1408 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE | 1409 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) | 1410 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1411 QSYS_SWITCH_PORT_MODE, cpu); 1412 /* CPU port Injection/Extraction configuration */ 1413 ocelot_write_rix(ocelot, SYS_PORT_MODE_INCL_XTR_HDR(extraction) | 1414 SYS_PORT_MODE_INCL_INJ_HDR(injection), 1415 SYS_PORT_MODE, cpu); 1416 1417 /* Configure the CPU port to be VLAN aware */ 1418 ocelot_write_gix(ocelot, ANA_PORT_VLAN_CFG_VLAN_VID(0) | 1419 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 1420 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1), 1421 ANA_PORT_VLAN_CFG, cpu); 1422 } 1423 EXPORT_SYMBOL(ocelot_configure_cpu); 1424 1425 int ocelot_init(struct ocelot *ocelot) 1426 { 1427 char queue_name[32]; 1428 int i, ret; 1429 u32 port; 1430 1431 if (ocelot->ops->reset) { 1432 ret = ocelot->ops->reset(ocelot); 1433 if (ret) { 1434 dev_err(ocelot->dev, "Switch reset failed\n"); 1435 return ret; 1436 } 1437 } 1438 1439 ocelot->lags = devm_kcalloc(ocelot->dev, ocelot->num_phys_ports, 1440 sizeof(u32), GFP_KERNEL); 1441 if (!ocelot->lags) 1442 return -ENOMEM; 1443 1444 ocelot->stats = devm_kcalloc(ocelot->dev, 1445 ocelot->num_phys_ports * ocelot->num_stats, 1446 sizeof(u64), GFP_KERNEL); 1447 if (!ocelot->stats) 1448 return -ENOMEM; 1449 1450 mutex_init(&ocelot->stats_lock); 1451 mutex_init(&ocelot->ptp_lock); 1452 spin_lock_init(&ocelot->ptp_clock_lock); 1453 snprintf(queue_name, sizeof(queue_name), "%s-stats", 1454 dev_name(ocelot->dev)); 1455 ocelot->stats_queue = create_singlethread_workqueue(queue_name); 1456 if (!ocelot->stats_queue) 1457 return -ENOMEM; 1458 1459 INIT_LIST_HEAD(&ocelot->multicast); 1460 ocelot_mact_init(ocelot); 1461 ocelot_vlan_init(ocelot); 1462 ocelot_vcap_init(ocelot); 1463 1464 for (port = 0; port < ocelot->num_phys_ports; port++) { 1465 /* Clear all counters (5 groups) */ 1466 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) | 1467 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f), 1468 SYS_STAT_CFG); 1469 } 1470 1471 /* Only use S-Tag */ 1472 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG); 1473 1474 /* Aggregation mode */ 1475 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA | 1476 ANA_AGGR_CFG_AC_DMAC_ENA | 1477 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA | 1478 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, ANA_AGGR_CFG); 1479 1480 /* Set MAC age time to default value. The entry is aged after 1481 * 2*AGE_PERIOD 1482 */ 1483 ocelot_write(ocelot, 1484 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ), 1485 ANA_AUTOAGE); 1486 1487 /* Disable learning for frames discarded by VLAN ingress filtering */ 1488 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1); 1489 1490 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */ 1491 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA | 1492 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING); 1493 1494 /* Setup flooding PGIDs */ 1495 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) | 1496 ANA_FLOODING_FLD_BROADCAST(PGID_MC) | 1497 ANA_FLOODING_FLD_UNICAST(PGID_UC), 1498 ANA_FLOODING, 0); 1499 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) | 1500 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) | 1501 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) | 1502 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC), 1503 ANA_FLOODING_IPMC); 1504 1505 for (port = 0; port < ocelot->num_phys_ports; port++) { 1506 /* Transmit the frame to the local port. */ 1507 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 1508 /* Do not forward BPDU frames to the front ports. */ 1509 ocelot_write_gix(ocelot, 1510 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff), 1511 ANA_PORT_CPU_FWD_BPDU_CFG, 1512 port); 1513 /* Ensure bridging is disabled */ 1514 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port); 1515 } 1516 1517 /* Allow broadcast MAC frames. */ 1518 for_each_nonreserved_multicast_dest_pgid(ocelot, i) { 1519 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0)); 1520 1521 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 1522 } 1523 ocelot_write_rix(ocelot, 1524 ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports, 0)), 1525 ANA_PGID_PGID, PGID_MC); 1526 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4); 1527 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6); 1528 1529 /* Allow manual injection via DEVCPU_QS registers, and byte swap these 1530 * registers endianness. 1531 */ 1532 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP | 1533 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0); 1534 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP | 1535 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0); 1536 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) | 1537 ANA_CPUQ_CFG_CPUQ_LRN(2) | 1538 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) | 1539 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) | 1540 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) | 1541 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) | 1542 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) | 1543 ANA_CPUQ_CFG_CPUQ_IGMP(6) | 1544 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG); 1545 for (i = 0; i < 16; i++) 1546 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) | 1547 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6), 1548 ANA_CPUQ_8021_CFG, i); 1549 1550 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats_work); 1551 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 1552 OCELOT_STATS_CHECK_DELAY); 1553 1554 return 0; 1555 } 1556 EXPORT_SYMBOL(ocelot_init); 1557 1558 void ocelot_deinit(struct ocelot *ocelot) 1559 { 1560 struct ocelot_port *port; 1561 int i; 1562 1563 cancel_delayed_work(&ocelot->stats_work); 1564 destroy_workqueue(ocelot->stats_queue); 1565 mutex_destroy(&ocelot->stats_lock); 1566 1567 for (i = 0; i < ocelot->num_phys_ports; i++) { 1568 port = ocelot->ports[i]; 1569 skb_queue_purge(&port->tx_skbs); 1570 } 1571 } 1572 EXPORT_SYMBOL(ocelot_deinit); 1573 1574 MODULE_LICENSE("Dual MIT/GPL"); 1575