1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7 #include <linux/if_bridge.h> 8 #include <soc/mscc/ocelot_vcap.h> 9 #include "ocelot.h" 10 #include "ocelot_vcap.h" 11 12 #define TABLE_UPDATE_SLEEP_US 10 13 #define TABLE_UPDATE_TIMEOUT_US 100000 14 15 struct ocelot_mact_entry { 16 u8 mac[ETH_ALEN]; 17 u16 vid; 18 enum macaccess_entry_type type; 19 }; 20 21 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot) 22 { 23 return ocelot_read(ocelot, ANA_TABLES_MACACCESS); 24 } 25 26 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot) 27 { 28 u32 val; 29 30 return readx_poll_timeout(ocelot_mact_read_macaccess, 31 ocelot, val, 32 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) == 33 MACACCESS_CMD_IDLE, 34 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 35 } 36 37 static void ocelot_mact_select(struct ocelot *ocelot, 38 const unsigned char mac[ETH_ALEN], 39 unsigned int vid) 40 { 41 u32 macl = 0, mach = 0; 42 43 /* Set the MAC address to handle and the vlan associated in a format 44 * understood by the hardware. 45 */ 46 mach |= vid << 16; 47 mach |= mac[0] << 8; 48 mach |= mac[1] << 0; 49 macl |= mac[2] << 24; 50 macl |= mac[3] << 16; 51 macl |= mac[4] << 8; 52 macl |= mac[5] << 0; 53 54 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA); 55 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA); 56 57 } 58 59 int ocelot_mact_learn(struct ocelot *ocelot, int port, 60 const unsigned char mac[ETH_ALEN], 61 unsigned int vid, enum macaccess_entry_type type) 62 { 63 ocelot_mact_select(ocelot, mac, vid); 64 65 /* Issue a write command */ 66 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID | 67 ANA_TABLES_MACACCESS_DEST_IDX(port) | 68 ANA_TABLES_MACACCESS_ENTRYTYPE(type) | 69 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN), 70 ANA_TABLES_MACACCESS); 71 72 return ocelot_mact_wait_for_completion(ocelot); 73 } 74 EXPORT_SYMBOL(ocelot_mact_learn); 75 76 int ocelot_mact_forget(struct ocelot *ocelot, 77 const unsigned char mac[ETH_ALEN], unsigned int vid) 78 { 79 ocelot_mact_select(ocelot, mac, vid); 80 81 /* Issue a forget command */ 82 ocelot_write(ocelot, 83 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET), 84 ANA_TABLES_MACACCESS); 85 86 return ocelot_mact_wait_for_completion(ocelot); 87 } 88 EXPORT_SYMBOL(ocelot_mact_forget); 89 90 static void ocelot_mact_init(struct ocelot *ocelot) 91 { 92 /* Configure the learning mode entries attributes: 93 * - Do not copy the frame to the CPU extraction queues. 94 * - Use the vlan and mac_cpoy for dmac lookup. 95 */ 96 ocelot_rmw(ocelot, 0, 97 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS 98 | ANA_AGENCTRL_LEARN_FWD_KILL 99 | ANA_AGENCTRL_LEARN_IGNORE_VLAN, 100 ANA_AGENCTRL); 101 102 /* Clear the MAC table */ 103 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS); 104 } 105 106 static void ocelot_vcap_enable(struct ocelot *ocelot, int port) 107 { 108 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA | 109 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa), 110 ANA_PORT_VCAP_S2_CFG, port); 111 112 ocelot_write_gix(ocelot, ANA_PORT_VCAP_CFG_S1_ENA, 113 ANA_PORT_VCAP_CFG, port); 114 115 ocelot_rmw_gix(ocelot, REW_PORT_CFG_ES0_EN, 116 REW_PORT_CFG_ES0_EN, 117 REW_PORT_CFG, port); 118 } 119 120 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot) 121 { 122 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS); 123 } 124 125 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot) 126 { 127 u32 val; 128 129 return readx_poll_timeout(ocelot_vlant_read_vlanaccess, 130 ocelot, 131 val, 132 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) == 133 ANA_TABLES_VLANACCESS_CMD_IDLE, 134 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 135 } 136 137 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask) 138 { 139 /* Select the VID to configure */ 140 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid), 141 ANA_TABLES_VLANTIDX); 142 /* Set the vlan port members mask and issue a write command */ 143 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) | 144 ANA_TABLES_VLANACCESS_CMD_WRITE, 145 ANA_TABLES_VLANACCESS); 146 147 return ocelot_vlant_wait_for_completion(ocelot); 148 } 149 150 static void ocelot_port_set_native_vlan(struct ocelot *ocelot, int port, 151 struct ocelot_vlan native_vlan) 152 { 153 struct ocelot_port *ocelot_port = ocelot->ports[port]; 154 u32 val = 0; 155 156 ocelot_port->native_vlan = native_vlan; 157 158 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_VID(native_vlan.vid), 159 REW_PORT_VLAN_CFG_PORT_VID_M, 160 REW_PORT_VLAN_CFG, port); 161 162 if (ocelot_port->vlan_aware) { 163 if (native_vlan.valid) 164 /* Tag all frames except when VID == DEFAULT_VLAN */ 165 val = REW_TAG_CFG_TAG_CFG(1); 166 else 167 /* Tag all frames */ 168 val = REW_TAG_CFG_TAG_CFG(3); 169 } else { 170 /* Port tagging disabled. */ 171 val = REW_TAG_CFG_TAG_CFG(0); 172 } 173 ocelot_rmw_gix(ocelot, val, 174 REW_TAG_CFG_TAG_CFG_M, 175 REW_TAG_CFG, port); 176 } 177 178 /* Default vlan to clasify for untagged frames (may be zero) */ 179 static void ocelot_port_set_pvid(struct ocelot *ocelot, int port, 180 struct ocelot_vlan pvid_vlan) 181 { 182 struct ocelot_port *ocelot_port = ocelot->ports[port]; 183 u32 val = 0; 184 185 ocelot_port->pvid_vlan = pvid_vlan; 186 187 if (!ocelot_port->vlan_aware) 188 pvid_vlan.vid = 0; 189 190 ocelot_rmw_gix(ocelot, 191 ANA_PORT_VLAN_CFG_VLAN_VID(pvid_vlan.vid), 192 ANA_PORT_VLAN_CFG_VLAN_VID_M, 193 ANA_PORT_VLAN_CFG, port); 194 195 /* If there's no pvid, we should drop not only untagged traffic (which 196 * happens automatically), but also 802.1p traffic which gets 197 * classified to VLAN 0, but that is always in our RX filter, so it 198 * would get accepted were it not for this setting. 199 */ 200 if (!pvid_vlan.valid && ocelot_port->vlan_aware) 201 val = ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 202 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA; 203 204 ocelot_rmw_gix(ocelot, val, 205 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 206 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, 207 ANA_PORT_DROP_CFG, port); 208 } 209 210 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, 211 bool vlan_aware, struct switchdev_trans *trans) 212 { 213 struct ocelot_port *ocelot_port = ocelot->ports[port]; 214 u32 val; 215 216 if (switchdev_trans_ph_prepare(trans)) { 217 struct ocelot_vcap_block *block = &ocelot->block[VCAP_IS1]; 218 struct ocelot_vcap_filter *filter; 219 220 list_for_each_entry(filter, &block->rules, list) { 221 if (filter->ingress_port_mask & BIT(port) && 222 filter->action.vid_replace_ena) { 223 dev_err(ocelot->dev, 224 "Cannot change VLAN state with vlan modify rules active\n"); 225 return -EBUSY; 226 } 227 } 228 229 return 0; 230 } 231 232 ocelot_port->vlan_aware = vlan_aware; 233 234 if (vlan_aware) 235 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 236 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1); 237 else 238 val = 0; 239 ocelot_rmw_gix(ocelot, val, 240 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 241 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M, 242 ANA_PORT_VLAN_CFG, port); 243 244 ocelot_port_set_pvid(ocelot, port, ocelot_port->pvid_vlan); 245 ocelot_port_set_native_vlan(ocelot, port, ocelot_port->native_vlan); 246 247 return 0; 248 } 249 EXPORT_SYMBOL(ocelot_port_vlan_filtering); 250 251 int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid, 252 bool untagged) 253 { 254 struct ocelot_port *ocelot_port = ocelot->ports[port]; 255 256 /* Deny changing the native VLAN, but always permit deleting it */ 257 if (untagged && ocelot_port->native_vlan.vid != vid && 258 ocelot_port->native_vlan.valid) { 259 dev_err(ocelot->dev, 260 "Port already has a native VLAN: %d\n", 261 ocelot_port->native_vlan.vid); 262 return -EBUSY; 263 } 264 265 return 0; 266 } 267 EXPORT_SYMBOL(ocelot_vlan_prepare); 268 269 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid, 270 bool untagged) 271 { 272 int ret; 273 274 /* Make the port a member of the VLAN */ 275 ocelot->vlan_mask[vid] |= BIT(port); 276 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 277 if (ret) 278 return ret; 279 280 /* Default ingress vlan classification */ 281 if (pvid) { 282 struct ocelot_vlan pvid_vlan; 283 284 pvid_vlan.vid = vid; 285 pvid_vlan.valid = true; 286 ocelot_port_set_pvid(ocelot, port, pvid_vlan); 287 } 288 289 /* Untagged egress vlan clasification */ 290 if (untagged) { 291 struct ocelot_vlan native_vlan; 292 293 native_vlan.vid = vid; 294 native_vlan.valid = true; 295 ocelot_port_set_native_vlan(ocelot, port, native_vlan); 296 } 297 298 return 0; 299 } 300 EXPORT_SYMBOL(ocelot_vlan_add); 301 302 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid) 303 { 304 struct ocelot_port *ocelot_port = ocelot->ports[port]; 305 int ret; 306 307 /* Stop the port from being a member of the vlan */ 308 ocelot->vlan_mask[vid] &= ~BIT(port); 309 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 310 if (ret) 311 return ret; 312 313 /* Ingress */ 314 if (ocelot_port->pvid_vlan.vid == vid) { 315 struct ocelot_vlan pvid_vlan = {0}; 316 317 ocelot_port_set_pvid(ocelot, port, pvid_vlan); 318 } 319 320 /* Egress */ 321 if (ocelot_port->native_vlan.vid == vid) { 322 struct ocelot_vlan native_vlan = {0}; 323 324 ocelot_port_set_native_vlan(ocelot, port, native_vlan); 325 } 326 327 return 0; 328 } 329 EXPORT_SYMBOL(ocelot_vlan_del); 330 331 static void ocelot_vlan_init(struct ocelot *ocelot) 332 { 333 u16 port, vid; 334 335 /* Clear VLAN table, by default all ports are members of all VLANs */ 336 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT, 337 ANA_TABLES_VLANACCESS); 338 ocelot_vlant_wait_for_completion(ocelot); 339 340 /* Configure the port VLAN memberships */ 341 for (vid = 1; vid < VLAN_N_VID; vid++) { 342 ocelot->vlan_mask[vid] = 0; 343 ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 344 } 345 346 /* Because VLAN filtering is enabled, we need VID 0 to get untagged 347 * traffic. It is added automatically if 8021q module is loaded, but 348 * we can't rely on it since module may be not loaded. 349 */ 350 ocelot->vlan_mask[0] = GENMASK(ocelot->num_phys_ports - 1, 0); 351 ocelot_vlant_set_mask(ocelot, 0, ocelot->vlan_mask[0]); 352 353 /* Set vlan ingress filter mask to all ports but the CPU port by 354 * default. 355 */ 356 ocelot_write(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 357 ANA_VLANMASK); 358 359 for (port = 0; port < ocelot->num_phys_ports; port++) { 360 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port); 361 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port); 362 } 363 } 364 365 void ocelot_adjust_link(struct ocelot *ocelot, int port, 366 struct phy_device *phydev) 367 { 368 struct ocelot_port *ocelot_port = ocelot->ports[port]; 369 int speed, mode = 0; 370 371 switch (phydev->speed) { 372 case SPEED_10: 373 speed = OCELOT_SPEED_10; 374 break; 375 case SPEED_100: 376 speed = OCELOT_SPEED_100; 377 break; 378 case SPEED_1000: 379 speed = OCELOT_SPEED_1000; 380 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 381 break; 382 case SPEED_2500: 383 speed = OCELOT_SPEED_2500; 384 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 385 break; 386 default: 387 dev_err(ocelot->dev, "Unsupported PHY speed on port %d: %d\n", 388 port, phydev->speed); 389 return; 390 } 391 392 phy_print_status(phydev); 393 394 if (!phydev->link) 395 return; 396 397 /* Only full duplex supported for now */ 398 ocelot_port_writel(ocelot_port, DEV_MAC_MODE_CFG_FDX_ENA | 399 mode, DEV_MAC_MODE_CFG); 400 401 /* Disable HDX fast control */ 402 ocelot_port_writel(ocelot_port, DEV_PORT_MISC_HDX_FAST_DIS, 403 DEV_PORT_MISC); 404 405 /* SGMII only for now */ 406 ocelot_port_writel(ocelot_port, PCS1G_MODE_CFG_SGMII_MODE_ENA, 407 PCS1G_MODE_CFG); 408 ocelot_port_writel(ocelot_port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG); 409 410 /* Enable PCS */ 411 ocelot_port_writel(ocelot_port, PCS1G_CFG_PCS_ENA, PCS1G_CFG); 412 413 /* No aneg on SGMII */ 414 ocelot_port_writel(ocelot_port, 0, PCS1G_ANEG_CFG); 415 416 /* No loopback */ 417 ocelot_port_writel(ocelot_port, 0, PCS1G_LB_CFG); 418 419 /* Enable MAC module */ 420 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA | 421 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG); 422 423 /* Take MAC, Port, Phy (intern) and PCS (SGMII/Serdes) clock out of 424 * reset */ 425 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(speed), 426 DEV_CLOCK_CFG); 427 428 /* No PFC */ 429 ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed), 430 ANA_PFC_PFC_CFG, port); 431 432 /* Core: Enable port for frame transfer */ 433 ocelot_fields_write(ocelot, port, 434 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 435 436 /* Flow control */ 437 ocelot_write_rix(ocelot, SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) | 438 SYS_MAC_FC_CFG_RX_FC_ENA | SYS_MAC_FC_CFG_TX_FC_ENA | 439 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA | 440 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) | 441 SYS_MAC_FC_CFG_FC_LINK_SPEED(speed), 442 SYS_MAC_FC_CFG, port); 443 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port); 444 } 445 EXPORT_SYMBOL(ocelot_adjust_link); 446 447 void ocelot_port_enable(struct ocelot *ocelot, int port, 448 struct phy_device *phy) 449 { 450 /* Enable receiving frames on the port, and activate auto-learning of 451 * MAC addresses. 452 */ 453 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO | 454 ANA_PORT_PORT_CFG_RECV_ENA | 455 ANA_PORT_PORT_CFG_PORTID_VAL(port), 456 ANA_PORT_PORT_CFG, port); 457 } 458 EXPORT_SYMBOL(ocelot_port_enable); 459 460 void ocelot_port_disable(struct ocelot *ocelot, int port) 461 { 462 struct ocelot_port *ocelot_port = ocelot->ports[port]; 463 464 ocelot_port_writel(ocelot_port, 0, DEV_MAC_ENA_CFG); 465 ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0); 466 } 467 EXPORT_SYMBOL(ocelot_port_disable); 468 469 void ocelot_port_add_txtstamp_skb(struct ocelot *ocelot, int port, 470 struct sk_buff *clone) 471 { 472 struct ocelot_port *ocelot_port = ocelot->ports[port]; 473 474 spin_lock(&ocelot_port->ts_id_lock); 475 476 skb_shinfo(clone)->tx_flags |= SKBTX_IN_PROGRESS; 477 /* Store timestamp ID in cb[0] of sk_buff */ 478 clone->cb[0] = ocelot_port->ts_id; 479 ocelot_port->ts_id = (ocelot_port->ts_id + 1) % 4; 480 skb_queue_tail(&ocelot_port->tx_skbs, clone); 481 482 spin_unlock(&ocelot_port->ts_id_lock); 483 } 484 EXPORT_SYMBOL(ocelot_port_add_txtstamp_skb); 485 486 static void ocelot_get_hwtimestamp(struct ocelot *ocelot, 487 struct timespec64 *ts) 488 { 489 unsigned long flags; 490 u32 val; 491 492 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); 493 494 /* Read current PTP time to get seconds */ 495 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 496 497 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 498 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE); 499 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 500 ts->tv_sec = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN); 501 502 /* Read packet HW timestamp from FIFO */ 503 val = ocelot_read(ocelot, SYS_PTP_TXSTAMP); 504 ts->tv_nsec = SYS_PTP_TXSTAMP_PTP_TXSTAMP(val); 505 506 /* Sec has incremented since the ts was registered */ 507 if ((ts->tv_sec & 0x1) != !!(val & SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC)) 508 ts->tv_sec--; 509 510 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 511 } 512 513 void ocelot_get_txtstamp(struct ocelot *ocelot) 514 { 515 int budget = OCELOT_PTP_QUEUE_SZ; 516 517 while (budget--) { 518 struct sk_buff *skb, *skb_tmp, *skb_match = NULL; 519 struct skb_shared_hwtstamps shhwtstamps; 520 struct ocelot_port *port; 521 struct timespec64 ts; 522 unsigned long flags; 523 u32 val, id, txport; 524 525 val = ocelot_read(ocelot, SYS_PTP_STATUS); 526 527 /* Check if a timestamp can be retrieved */ 528 if (!(val & SYS_PTP_STATUS_PTP_MESS_VLD)) 529 break; 530 531 WARN_ON(val & SYS_PTP_STATUS_PTP_OVFL); 532 533 /* Retrieve the ts ID and Tx port */ 534 id = SYS_PTP_STATUS_PTP_MESS_ID_X(val); 535 txport = SYS_PTP_STATUS_PTP_MESS_TXPORT_X(val); 536 537 /* Retrieve its associated skb */ 538 port = ocelot->ports[txport]; 539 540 spin_lock_irqsave(&port->tx_skbs.lock, flags); 541 542 skb_queue_walk_safe(&port->tx_skbs, skb, skb_tmp) { 543 if (skb->cb[0] != id) 544 continue; 545 __skb_unlink(skb, &port->tx_skbs); 546 skb_match = skb; 547 break; 548 } 549 550 spin_unlock_irqrestore(&port->tx_skbs.lock, flags); 551 552 /* Get the h/w timestamp */ 553 ocelot_get_hwtimestamp(ocelot, &ts); 554 555 if (unlikely(!skb_match)) 556 continue; 557 558 /* Set the timestamp into the skb */ 559 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 560 shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec); 561 skb_complete_tx_timestamp(skb_match, &shhwtstamps); 562 563 /* Next ts */ 564 ocelot_write(ocelot, SYS_PTP_NXT_PTP_NXT, SYS_PTP_NXT); 565 } 566 } 567 EXPORT_SYMBOL(ocelot_get_txtstamp); 568 569 int ocelot_fdb_add(struct ocelot *ocelot, int port, 570 const unsigned char *addr, u16 vid) 571 { 572 int pgid = port; 573 574 if (port == ocelot->npi) 575 pgid = PGID_CPU; 576 577 return ocelot_mact_learn(ocelot, pgid, addr, vid, ENTRYTYPE_LOCKED); 578 } 579 EXPORT_SYMBOL(ocelot_fdb_add); 580 581 int ocelot_fdb_del(struct ocelot *ocelot, int port, 582 const unsigned char *addr, u16 vid) 583 { 584 return ocelot_mact_forget(ocelot, addr, vid); 585 } 586 EXPORT_SYMBOL(ocelot_fdb_del); 587 588 int ocelot_port_fdb_do_dump(const unsigned char *addr, u16 vid, 589 bool is_static, void *data) 590 { 591 struct ocelot_dump_ctx *dump = data; 592 u32 portid = NETLINK_CB(dump->cb->skb).portid; 593 u32 seq = dump->cb->nlh->nlmsg_seq; 594 struct nlmsghdr *nlh; 595 struct ndmsg *ndm; 596 597 if (dump->idx < dump->cb->args[2]) 598 goto skip; 599 600 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH, 601 sizeof(*ndm), NLM_F_MULTI); 602 if (!nlh) 603 return -EMSGSIZE; 604 605 ndm = nlmsg_data(nlh); 606 ndm->ndm_family = AF_BRIDGE; 607 ndm->ndm_pad1 = 0; 608 ndm->ndm_pad2 = 0; 609 ndm->ndm_flags = NTF_SELF; 610 ndm->ndm_type = 0; 611 ndm->ndm_ifindex = dump->dev->ifindex; 612 ndm->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE; 613 614 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, addr)) 615 goto nla_put_failure; 616 617 if (vid && nla_put_u16(dump->skb, NDA_VLAN, vid)) 618 goto nla_put_failure; 619 620 nlmsg_end(dump->skb, nlh); 621 622 skip: 623 dump->idx++; 624 return 0; 625 626 nla_put_failure: 627 nlmsg_cancel(dump->skb, nlh); 628 return -EMSGSIZE; 629 } 630 EXPORT_SYMBOL(ocelot_port_fdb_do_dump); 631 632 static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col, 633 struct ocelot_mact_entry *entry) 634 { 635 u32 val, dst, macl, mach; 636 char mac[ETH_ALEN]; 637 638 /* Set row and column to read from */ 639 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row); 640 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col); 641 642 /* Issue a read command */ 643 ocelot_write(ocelot, 644 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 645 ANA_TABLES_MACACCESS); 646 647 if (ocelot_mact_wait_for_completion(ocelot)) 648 return -ETIMEDOUT; 649 650 /* Read the entry flags */ 651 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 652 if (!(val & ANA_TABLES_MACACCESS_VALID)) 653 return -EINVAL; 654 655 /* If the entry read has another port configured as its destination, 656 * do not report it. 657 */ 658 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3; 659 if (dst != port) 660 return -EINVAL; 661 662 /* Get the entry's MAC address and VLAN id */ 663 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA); 664 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA); 665 666 mac[0] = (mach >> 8) & 0xff; 667 mac[1] = (mach >> 0) & 0xff; 668 mac[2] = (macl >> 24) & 0xff; 669 mac[3] = (macl >> 16) & 0xff; 670 mac[4] = (macl >> 8) & 0xff; 671 mac[5] = (macl >> 0) & 0xff; 672 673 entry->vid = (mach >> 16) & 0xfff; 674 ether_addr_copy(entry->mac, mac); 675 676 return 0; 677 } 678 679 int ocelot_fdb_dump(struct ocelot *ocelot, int port, 680 dsa_fdb_dump_cb_t *cb, void *data) 681 { 682 int i, j; 683 684 /* Loop through all the mac tables entries. */ 685 for (i = 0; i < ocelot->num_mact_rows; i++) { 686 for (j = 0; j < 4; j++) { 687 struct ocelot_mact_entry entry; 688 bool is_static; 689 int ret; 690 691 ret = ocelot_mact_read(ocelot, port, i, j, &entry); 692 /* If the entry is invalid (wrong port, invalid...), 693 * skip it. 694 */ 695 if (ret == -EINVAL) 696 continue; 697 else if (ret) 698 return ret; 699 700 is_static = (entry.type == ENTRYTYPE_LOCKED); 701 702 ret = cb(entry.mac, entry.vid, is_static, data); 703 if (ret) 704 return ret; 705 } 706 } 707 708 return 0; 709 } 710 EXPORT_SYMBOL(ocelot_fdb_dump); 711 712 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr) 713 { 714 return copy_to_user(ifr->ifr_data, &ocelot->hwtstamp_config, 715 sizeof(ocelot->hwtstamp_config)) ? -EFAULT : 0; 716 } 717 EXPORT_SYMBOL(ocelot_hwstamp_get); 718 719 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr) 720 { 721 struct ocelot_port *ocelot_port = ocelot->ports[port]; 722 struct hwtstamp_config cfg; 723 724 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 725 return -EFAULT; 726 727 /* reserved for future extensions */ 728 if (cfg.flags) 729 return -EINVAL; 730 731 /* Tx type sanity check */ 732 switch (cfg.tx_type) { 733 case HWTSTAMP_TX_ON: 734 ocelot_port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP; 735 break; 736 case HWTSTAMP_TX_ONESTEP_SYNC: 737 /* IFH_REW_OP_ONE_STEP_PTP updates the correctional field, we 738 * need to update the origin time. 739 */ 740 ocelot_port->ptp_cmd = IFH_REW_OP_ORIGIN_PTP; 741 break; 742 case HWTSTAMP_TX_OFF: 743 ocelot_port->ptp_cmd = 0; 744 break; 745 default: 746 return -ERANGE; 747 } 748 749 mutex_lock(&ocelot->ptp_lock); 750 751 switch (cfg.rx_filter) { 752 case HWTSTAMP_FILTER_NONE: 753 break; 754 case HWTSTAMP_FILTER_ALL: 755 case HWTSTAMP_FILTER_SOME: 756 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 757 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 758 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 759 case HWTSTAMP_FILTER_NTP_ALL: 760 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 761 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 762 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 763 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 764 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 765 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 766 case HWTSTAMP_FILTER_PTP_V2_EVENT: 767 case HWTSTAMP_FILTER_PTP_V2_SYNC: 768 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 769 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 770 break; 771 default: 772 mutex_unlock(&ocelot->ptp_lock); 773 return -ERANGE; 774 } 775 776 /* Commit back the result & save it */ 777 memcpy(&ocelot->hwtstamp_config, &cfg, sizeof(cfg)); 778 mutex_unlock(&ocelot->ptp_lock); 779 780 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 781 } 782 EXPORT_SYMBOL(ocelot_hwstamp_set); 783 784 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data) 785 { 786 int i; 787 788 if (sset != ETH_SS_STATS) 789 return; 790 791 for (i = 0; i < ocelot->num_stats; i++) 792 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name, 793 ETH_GSTRING_LEN); 794 } 795 EXPORT_SYMBOL(ocelot_get_strings); 796 797 static void ocelot_update_stats(struct ocelot *ocelot) 798 { 799 int i, j; 800 801 mutex_lock(&ocelot->stats_lock); 802 803 for (i = 0; i < ocelot->num_phys_ports; i++) { 804 /* Configure the port to read the stats from */ 805 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(i), SYS_STAT_CFG); 806 807 for (j = 0; j < ocelot->num_stats; j++) { 808 u32 val; 809 unsigned int idx = i * ocelot->num_stats + j; 810 811 val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS, 812 ocelot->stats_layout[j].offset); 813 814 if (val < (ocelot->stats[idx] & U32_MAX)) 815 ocelot->stats[idx] += (u64)1 << 32; 816 817 ocelot->stats[idx] = (ocelot->stats[idx] & 818 ~(u64)U32_MAX) + val; 819 } 820 } 821 822 mutex_unlock(&ocelot->stats_lock); 823 } 824 825 static void ocelot_check_stats_work(struct work_struct *work) 826 { 827 struct delayed_work *del_work = to_delayed_work(work); 828 struct ocelot *ocelot = container_of(del_work, struct ocelot, 829 stats_work); 830 831 ocelot_update_stats(ocelot); 832 833 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 834 OCELOT_STATS_CHECK_DELAY); 835 } 836 837 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data) 838 { 839 int i; 840 841 /* check and update now */ 842 ocelot_update_stats(ocelot); 843 844 /* Copy all counters */ 845 for (i = 0; i < ocelot->num_stats; i++) 846 *data++ = ocelot->stats[port * ocelot->num_stats + i]; 847 } 848 EXPORT_SYMBOL(ocelot_get_ethtool_stats); 849 850 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset) 851 { 852 if (sset != ETH_SS_STATS) 853 return -EOPNOTSUPP; 854 855 return ocelot->num_stats; 856 } 857 EXPORT_SYMBOL(ocelot_get_sset_count); 858 859 int ocelot_get_ts_info(struct ocelot *ocelot, int port, 860 struct ethtool_ts_info *info) 861 { 862 info->phc_index = ocelot->ptp_clock ? 863 ptp_clock_index(ocelot->ptp_clock) : -1; 864 if (info->phc_index == -1) { 865 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 866 SOF_TIMESTAMPING_RX_SOFTWARE | 867 SOF_TIMESTAMPING_SOFTWARE; 868 return 0; 869 } 870 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 871 SOF_TIMESTAMPING_RX_SOFTWARE | 872 SOF_TIMESTAMPING_SOFTWARE | 873 SOF_TIMESTAMPING_TX_HARDWARE | 874 SOF_TIMESTAMPING_RX_HARDWARE | 875 SOF_TIMESTAMPING_RAW_HARDWARE; 876 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON) | 877 BIT(HWTSTAMP_TX_ONESTEP_SYNC); 878 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL); 879 880 return 0; 881 } 882 EXPORT_SYMBOL(ocelot_get_ts_info); 883 884 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state) 885 { 886 u32 port_cfg; 887 int p, i; 888 889 if (!(BIT(port) & ocelot->bridge_mask)) 890 return; 891 892 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, port); 893 894 switch (state) { 895 case BR_STATE_FORWARDING: 896 ocelot->bridge_fwd_mask |= BIT(port); 897 fallthrough; 898 case BR_STATE_LEARNING: 899 port_cfg |= ANA_PORT_PORT_CFG_LEARN_ENA; 900 break; 901 902 default: 903 port_cfg &= ~ANA_PORT_PORT_CFG_LEARN_ENA; 904 ocelot->bridge_fwd_mask &= ~BIT(port); 905 break; 906 } 907 908 ocelot_write_gix(ocelot, port_cfg, ANA_PORT_PORT_CFG, port); 909 910 /* Apply FWD mask. The loop is needed to add/remove the current port as 911 * a source for the other ports. 912 */ 913 for (p = 0; p < ocelot->num_phys_ports; p++) { 914 if (ocelot->bridge_fwd_mask & BIT(p)) { 915 unsigned long mask = ocelot->bridge_fwd_mask & ~BIT(p); 916 917 for (i = 0; i < ocelot->num_phys_ports; i++) { 918 unsigned long bond_mask = ocelot->lags[i]; 919 920 if (!bond_mask) 921 continue; 922 923 if (bond_mask & BIT(p)) { 924 mask &= ~bond_mask; 925 break; 926 } 927 } 928 929 ocelot_write_rix(ocelot, mask, 930 ANA_PGID_PGID, PGID_SRC + p); 931 } else { 932 ocelot_write_rix(ocelot, 0, 933 ANA_PGID_PGID, PGID_SRC + p); 934 } 935 } 936 } 937 EXPORT_SYMBOL(ocelot_bridge_stp_state_set); 938 939 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs) 940 { 941 unsigned int age_period = ANA_AUTOAGE_AGE_PERIOD(msecs / 2000); 942 943 /* Setting AGE_PERIOD to zero effectively disables automatic aging, 944 * which is clearly not what our intention is. So avoid that. 945 */ 946 if (!age_period) 947 age_period = 1; 948 949 ocelot_rmw(ocelot, age_period, ANA_AUTOAGE_AGE_PERIOD_M, ANA_AUTOAGE); 950 } 951 EXPORT_SYMBOL(ocelot_set_ageing_time); 952 953 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot, 954 const unsigned char *addr, 955 u16 vid) 956 { 957 struct ocelot_multicast *mc; 958 959 list_for_each_entry(mc, &ocelot->multicast, list) { 960 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid) 961 return mc; 962 } 963 964 return NULL; 965 } 966 967 static enum macaccess_entry_type ocelot_classify_mdb(const unsigned char *addr) 968 { 969 if (addr[0] == 0x01 && addr[1] == 0x00 && addr[2] == 0x5e) 970 return ENTRYTYPE_MACv4; 971 if (addr[0] == 0x33 && addr[1] == 0x33) 972 return ENTRYTYPE_MACv6; 973 return ENTRYTYPE_LOCKED; 974 } 975 976 static struct ocelot_pgid *ocelot_pgid_alloc(struct ocelot *ocelot, int index, 977 unsigned long ports) 978 { 979 struct ocelot_pgid *pgid; 980 981 pgid = kzalloc(sizeof(*pgid), GFP_KERNEL); 982 if (!pgid) 983 return ERR_PTR(-ENOMEM); 984 985 pgid->ports = ports; 986 pgid->index = index; 987 refcount_set(&pgid->refcount, 1); 988 list_add_tail(&pgid->list, &ocelot->pgids); 989 990 return pgid; 991 } 992 993 static void ocelot_pgid_free(struct ocelot *ocelot, struct ocelot_pgid *pgid) 994 { 995 if (!refcount_dec_and_test(&pgid->refcount)) 996 return; 997 998 list_del(&pgid->list); 999 kfree(pgid); 1000 } 1001 1002 static struct ocelot_pgid *ocelot_mdb_get_pgid(struct ocelot *ocelot, 1003 const struct ocelot_multicast *mc) 1004 { 1005 struct ocelot_pgid *pgid; 1006 int index; 1007 1008 /* According to VSC7514 datasheet 3.9.1.5 IPv4 Multicast Entries and 1009 * 3.9.1.6 IPv6 Multicast Entries, "Instead of a lookup in the 1010 * destination mask table (PGID), the destination set is programmed as 1011 * part of the entry MAC address.", and the DEST_IDX is set to 0. 1012 */ 1013 if (mc->entry_type == ENTRYTYPE_MACv4 || 1014 mc->entry_type == ENTRYTYPE_MACv6) 1015 return ocelot_pgid_alloc(ocelot, 0, mc->ports); 1016 1017 list_for_each_entry(pgid, &ocelot->pgids, list) { 1018 /* When searching for a nonreserved multicast PGID, ignore the 1019 * dummy PGID of zero that we have for MACv4/MACv6 entries 1020 */ 1021 if (pgid->index && pgid->ports == mc->ports) { 1022 refcount_inc(&pgid->refcount); 1023 return pgid; 1024 } 1025 } 1026 1027 /* Search for a free index in the nonreserved multicast PGID area */ 1028 for_each_nonreserved_multicast_dest_pgid(ocelot, index) { 1029 bool used = false; 1030 1031 list_for_each_entry(pgid, &ocelot->pgids, list) { 1032 if (pgid->index == index) { 1033 used = true; 1034 break; 1035 } 1036 } 1037 1038 if (!used) 1039 return ocelot_pgid_alloc(ocelot, index, mc->ports); 1040 } 1041 1042 return ERR_PTR(-ENOSPC); 1043 } 1044 1045 static void ocelot_encode_ports_to_mdb(unsigned char *addr, 1046 struct ocelot_multicast *mc) 1047 { 1048 ether_addr_copy(addr, mc->addr); 1049 1050 if (mc->entry_type == ENTRYTYPE_MACv4) { 1051 addr[0] = 0; 1052 addr[1] = mc->ports >> 8; 1053 addr[2] = mc->ports & 0xff; 1054 } else if (mc->entry_type == ENTRYTYPE_MACv6) { 1055 addr[0] = mc->ports >> 8; 1056 addr[1] = mc->ports & 0xff; 1057 } 1058 } 1059 1060 int ocelot_port_mdb_add(struct ocelot *ocelot, int port, 1061 const struct switchdev_obj_port_mdb *mdb) 1062 { 1063 unsigned char addr[ETH_ALEN]; 1064 struct ocelot_multicast *mc; 1065 struct ocelot_pgid *pgid; 1066 u16 vid = mdb->vid; 1067 1068 if (port == ocelot->npi) 1069 port = ocelot->num_phys_ports; 1070 1071 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1072 if (!mc) { 1073 /* New entry */ 1074 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL); 1075 if (!mc) 1076 return -ENOMEM; 1077 1078 mc->entry_type = ocelot_classify_mdb(mdb->addr); 1079 ether_addr_copy(mc->addr, mdb->addr); 1080 mc->vid = vid; 1081 1082 list_add_tail(&mc->list, &ocelot->multicast); 1083 } else { 1084 /* Existing entry. Clean up the current port mask from 1085 * hardware now, because we'll be modifying it. 1086 */ 1087 ocelot_pgid_free(ocelot, mc->pgid); 1088 ocelot_encode_ports_to_mdb(addr, mc); 1089 ocelot_mact_forget(ocelot, addr, vid); 1090 } 1091 1092 mc->ports |= BIT(port); 1093 1094 pgid = ocelot_mdb_get_pgid(ocelot, mc); 1095 if (IS_ERR(pgid)) { 1096 dev_err(ocelot->dev, 1097 "Cannot allocate PGID for mdb %pM vid %d\n", 1098 mc->addr, mc->vid); 1099 devm_kfree(ocelot->dev, mc); 1100 return PTR_ERR(pgid); 1101 } 1102 mc->pgid = pgid; 1103 1104 ocelot_encode_ports_to_mdb(addr, mc); 1105 1106 if (mc->entry_type != ENTRYTYPE_MACv4 && 1107 mc->entry_type != ENTRYTYPE_MACv6) 1108 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 1109 pgid->index); 1110 1111 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 1112 mc->entry_type); 1113 } 1114 EXPORT_SYMBOL(ocelot_port_mdb_add); 1115 1116 int ocelot_port_mdb_del(struct ocelot *ocelot, int port, 1117 const struct switchdev_obj_port_mdb *mdb) 1118 { 1119 unsigned char addr[ETH_ALEN]; 1120 struct ocelot_multicast *mc; 1121 struct ocelot_pgid *pgid; 1122 u16 vid = mdb->vid; 1123 1124 if (port == ocelot->npi) 1125 port = ocelot->num_phys_ports; 1126 1127 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1128 if (!mc) 1129 return -ENOENT; 1130 1131 ocelot_encode_ports_to_mdb(addr, mc); 1132 ocelot_mact_forget(ocelot, addr, vid); 1133 1134 ocelot_pgid_free(ocelot, mc->pgid); 1135 mc->ports &= ~BIT(port); 1136 if (!mc->ports) { 1137 list_del(&mc->list); 1138 devm_kfree(ocelot->dev, mc); 1139 return 0; 1140 } 1141 1142 /* We have a PGID with fewer ports now */ 1143 pgid = ocelot_mdb_get_pgid(ocelot, mc); 1144 if (IS_ERR(pgid)) 1145 return PTR_ERR(pgid); 1146 mc->pgid = pgid; 1147 1148 ocelot_encode_ports_to_mdb(addr, mc); 1149 1150 if (mc->entry_type != ENTRYTYPE_MACv4 && 1151 mc->entry_type != ENTRYTYPE_MACv6) 1152 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 1153 pgid->index); 1154 1155 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 1156 mc->entry_type); 1157 } 1158 EXPORT_SYMBOL(ocelot_port_mdb_del); 1159 1160 int ocelot_port_bridge_join(struct ocelot *ocelot, int port, 1161 struct net_device *bridge) 1162 { 1163 if (!ocelot->bridge_mask) { 1164 ocelot->hw_bridge_dev = bridge; 1165 } else { 1166 if (ocelot->hw_bridge_dev != bridge) 1167 /* This is adding the port to a second bridge, this is 1168 * unsupported */ 1169 return -ENODEV; 1170 } 1171 1172 ocelot->bridge_mask |= BIT(port); 1173 1174 return 0; 1175 } 1176 EXPORT_SYMBOL(ocelot_port_bridge_join); 1177 1178 int ocelot_port_bridge_leave(struct ocelot *ocelot, int port, 1179 struct net_device *bridge) 1180 { 1181 struct ocelot_vlan pvid = {0}, native_vlan = {0}; 1182 struct switchdev_trans trans; 1183 int ret; 1184 1185 ocelot->bridge_mask &= ~BIT(port); 1186 1187 if (!ocelot->bridge_mask) 1188 ocelot->hw_bridge_dev = NULL; 1189 1190 trans.ph_prepare = true; 1191 ret = ocelot_port_vlan_filtering(ocelot, port, false, &trans); 1192 if (ret) 1193 return ret; 1194 1195 trans.ph_prepare = false; 1196 ret = ocelot_port_vlan_filtering(ocelot, port, false, &trans); 1197 if (ret) 1198 return ret; 1199 1200 ocelot_port_set_pvid(ocelot, port, pvid); 1201 ocelot_port_set_native_vlan(ocelot, port, native_vlan); 1202 1203 return 0; 1204 } 1205 EXPORT_SYMBOL(ocelot_port_bridge_leave); 1206 1207 static void ocelot_set_aggr_pgids(struct ocelot *ocelot) 1208 { 1209 int i, port, lag; 1210 1211 /* Reset destination and aggregation PGIDS */ 1212 for_each_unicast_dest_pgid(ocelot, port) 1213 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 1214 1215 for_each_aggr_pgid(ocelot, i) 1216 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 1217 ANA_PGID_PGID, i); 1218 1219 /* Now, set PGIDs for each LAG */ 1220 for (lag = 0; lag < ocelot->num_phys_ports; lag++) { 1221 unsigned long bond_mask; 1222 int aggr_count = 0; 1223 u8 aggr_idx[16]; 1224 1225 bond_mask = ocelot->lags[lag]; 1226 if (!bond_mask) 1227 continue; 1228 1229 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) { 1230 // Destination mask 1231 ocelot_write_rix(ocelot, bond_mask, 1232 ANA_PGID_PGID, port); 1233 aggr_idx[aggr_count] = port; 1234 aggr_count++; 1235 } 1236 1237 for_each_aggr_pgid(ocelot, i) { 1238 u32 ac; 1239 1240 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i); 1241 ac &= ~bond_mask; 1242 ac |= BIT(aggr_idx[i % aggr_count]); 1243 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i); 1244 } 1245 } 1246 } 1247 1248 static void ocelot_setup_lag(struct ocelot *ocelot, int lag) 1249 { 1250 unsigned long bond_mask = ocelot->lags[lag]; 1251 unsigned int p; 1252 1253 for_each_set_bit(p, &bond_mask, ocelot->num_phys_ports) { 1254 u32 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, p); 1255 1256 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M; 1257 1258 /* Use lag port as logical port for port i */ 1259 ocelot_write_gix(ocelot, port_cfg | 1260 ANA_PORT_PORT_CFG_PORTID_VAL(lag), 1261 ANA_PORT_PORT_CFG, p); 1262 } 1263 } 1264 1265 int ocelot_port_lag_join(struct ocelot *ocelot, int port, 1266 struct net_device *bond) 1267 { 1268 struct net_device *ndev; 1269 u32 bond_mask = 0; 1270 int lag, lp; 1271 1272 rcu_read_lock(); 1273 for_each_netdev_in_bond_rcu(bond, ndev) { 1274 struct ocelot_port_private *priv = netdev_priv(ndev); 1275 1276 bond_mask |= BIT(priv->chip_port); 1277 } 1278 rcu_read_unlock(); 1279 1280 lp = __ffs(bond_mask); 1281 1282 /* If the new port is the lowest one, use it as the logical port from 1283 * now on 1284 */ 1285 if (port == lp) { 1286 lag = port; 1287 ocelot->lags[port] = bond_mask; 1288 bond_mask &= ~BIT(port); 1289 if (bond_mask) { 1290 lp = __ffs(bond_mask); 1291 ocelot->lags[lp] = 0; 1292 } 1293 } else { 1294 lag = lp; 1295 ocelot->lags[lp] |= BIT(port); 1296 } 1297 1298 ocelot_setup_lag(ocelot, lag); 1299 ocelot_set_aggr_pgids(ocelot); 1300 1301 return 0; 1302 } 1303 EXPORT_SYMBOL(ocelot_port_lag_join); 1304 1305 void ocelot_port_lag_leave(struct ocelot *ocelot, int port, 1306 struct net_device *bond) 1307 { 1308 u32 port_cfg; 1309 int i; 1310 1311 /* Remove port from any lag */ 1312 for (i = 0; i < ocelot->num_phys_ports; i++) 1313 ocelot->lags[i] &= ~BIT(port); 1314 1315 /* if it was the logical port of the lag, move the lag config to the 1316 * next port 1317 */ 1318 if (ocelot->lags[port]) { 1319 int n = __ffs(ocelot->lags[port]); 1320 1321 ocelot->lags[n] = ocelot->lags[port]; 1322 ocelot->lags[port] = 0; 1323 1324 ocelot_setup_lag(ocelot, n); 1325 } 1326 1327 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, port); 1328 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M; 1329 ocelot_write_gix(ocelot, port_cfg | ANA_PORT_PORT_CFG_PORTID_VAL(port), 1330 ANA_PORT_PORT_CFG, port); 1331 1332 ocelot_set_aggr_pgids(ocelot); 1333 } 1334 EXPORT_SYMBOL(ocelot_port_lag_leave); 1335 1336 /* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu. 1337 * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG. 1338 * In the special case that it's the NPI port that we're configuring, the 1339 * length of the tag and optional prefix needs to be accounted for privately, 1340 * in order to be able to sustain communication at the requested @sdu. 1341 */ 1342 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu) 1343 { 1344 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1345 int maxlen = sdu + ETH_HLEN + ETH_FCS_LEN; 1346 int pause_start, pause_stop; 1347 int atop, atop_tot; 1348 1349 if (port == ocelot->npi) { 1350 maxlen += OCELOT_TAG_LEN; 1351 1352 if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_SHORT) 1353 maxlen += OCELOT_SHORT_PREFIX_LEN; 1354 else if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_LONG) 1355 maxlen += OCELOT_LONG_PREFIX_LEN; 1356 } 1357 1358 ocelot_port_writel(ocelot_port, maxlen, DEV_MAC_MAXLEN_CFG); 1359 1360 /* Set Pause watermark hysteresis */ 1361 pause_start = 6 * maxlen / OCELOT_BUFFER_CELL_SZ; 1362 pause_stop = 4 * maxlen / OCELOT_BUFFER_CELL_SZ; 1363 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_START, 1364 pause_start); 1365 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_STOP, 1366 pause_stop); 1367 1368 /* Tail dropping watermarks */ 1369 atop_tot = (ocelot->shared_queue_sz - 9 * maxlen) / 1370 OCELOT_BUFFER_CELL_SZ; 1371 atop = (9 * maxlen) / OCELOT_BUFFER_CELL_SZ; 1372 ocelot_write_rix(ocelot, ocelot->ops->wm_enc(atop), SYS_ATOP, port); 1373 ocelot_write(ocelot, ocelot->ops->wm_enc(atop_tot), SYS_ATOP_TOT_CFG); 1374 } 1375 EXPORT_SYMBOL(ocelot_port_set_maxlen); 1376 1377 int ocelot_get_max_mtu(struct ocelot *ocelot, int port) 1378 { 1379 int max_mtu = 65535 - ETH_HLEN - ETH_FCS_LEN; 1380 1381 if (port == ocelot->npi) { 1382 max_mtu -= OCELOT_TAG_LEN; 1383 1384 if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_SHORT) 1385 max_mtu -= OCELOT_SHORT_PREFIX_LEN; 1386 else if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_LONG) 1387 max_mtu -= OCELOT_LONG_PREFIX_LEN; 1388 } 1389 1390 return max_mtu; 1391 } 1392 EXPORT_SYMBOL(ocelot_get_max_mtu); 1393 1394 void ocelot_init_port(struct ocelot *ocelot, int port) 1395 { 1396 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1397 1398 skb_queue_head_init(&ocelot_port->tx_skbs); 1399 spin_lock_init(&ocelot_port->ts_id_lock); 1400 1401 /* Basic L2 initialization */ 1402 1403 /* Set MAC IFG Gaps 1404 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0 1405 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5 1406 */ 1407 ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5), 1408 DEV_MAC_IFG_CFG); 1409 1410 /* Load seed (0) and set MAC HDX late collision */ 1411 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) | 1412 DEV_MAC_HDX_CFG_SEED_LOAD, 1413 DEV_MAC_HDX_CFG); 1414 mdelay(1); 1415 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67), 1416 DEV_MAC_HDX_CFG); 1417 1418 /* Set Max Length and maximum tags allowed */ 1419 ocelot_port_set_maxlen(ocelot, port, ETH_DATA_LEN); 1420 ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) | 1421 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA | 1422 DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA | 1423 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, 1424 DEV_MAC_TAGS_CFG); 1425 1426 /* Set SMAC of Pause frame (00:00:00:00:00:00) */ 1427 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG); 1428 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG); 1429 1430 /* Enable transmission of pause frames */ 1431 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1); 1432 1433 /* Drop frames with multicast source address */ 1434 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 1435 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 1436 ANA_PORT_DROP_CFG, port); 1437 1438 /* Set default VLAN and tag type to 8021Q. */ 1439 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q), 1440 REW_PORT_VLAN_CFG_PORT_TPID_M, 1441 REW_PORT_VLAN_CFG, port); 1442 1443 /* Enable vcap lookups */ 1444 ocelot_vcap_enable(ocelot, port); 1445 } 1446 EXPORT_SYMBOL(ocelot_init_port); 1447 1448 /* Configure and enable the CPU port module, which is a set of queues 1449 * accessible through register MMIO, frame DMA or Ethernet (in case 1450 * NPI mode is used). 1451 */ 1452 static void ocelot_cpu_port_init(struct ocelot *ocelot) 1453 { 1454 int cpu = ocelot->num_phys_ports; 1455 1456 /* The unicast destination PGID for the CPU port module is unused */ 1457 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu); 1458 /* Instead set up a multicast destination PGID for traffic copied to 1459 * the CPU. Whitelisted MAC addresses like the port netdevice MAC 1460 * addresses will be copied to the CPU via this PGID. 1461 */ 1462 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU); 1463 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA | 1464 ANA_PORT_PORT_CFG_PORTID_VAL(cpu), 1465 ANA_PORT_PORT_CFG, cpu); 1466 1467 /* Enable CPU port module */ 1468 ocelot_fields_write(ocelot, cpu, QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 1469 /* CPU port Injection/Extraction configuration */ 1470 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_XTR_HDR, 1471 ocelot->xtr_prefix); 1472 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_INJ_HDR, 1473 ocelot->inj_prefix); 1474 1475 /* Configure the CPU port to be VLAN aware */ 1476 ocelot_write_gix(ocelot, ANA_PORT_VLAN_CFG_VLAN_VID(0) | 1477 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 1478 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1), 1479 ANA_PORT_VLAN_CFG, cpu); 1480 } 1481 1482 int ocelot_init(struct ocelot *ocelot) 1483 { 1484 char queue_name[32]; 1485 int i, ret; 1486 u32 port; 1487 1488 if (ocelot->ops->reset) { 1489 ret = ocelot->ops->reset(ocelot); 1490 if (ret) { 1491 dev_err(ocelot->dev, "Switch reset failed\n"); 1492 return ret; 1493 } 1494 } 1495 1496 ocelot->lags = devm_kcalloc(ocelot->dev, ocelot->num_phys_ports, 1497 sizeof(u32), GFP_KERNEL); 1498 if (!ocelot->lags) 1499 return -ENOMEM; 1500 1501 ocelot->stats = devm_kcalloc(ocelot->dev, 1502 ocelot->num_phys_ports * ocelot->num_stats, 1503 sizeof(u64), GFP_KERNEL); 1504 if (!ocelot->stats) 1505 return -ENOMEM; 1506 1507 mutex_init(&ocelot->stats_lock); 1508 mutex_init(&ocelot->ptp_lock); 1509 spin_lock_init(&ocelot->ptp_clock_lock); 1510 snprintf(queue_name, sizeof(queue_name), "%s-stats", 1511 dev_name(ocelot->dev)); 1512 ocelot->stats_queue = create_singlethread_workqueue(queue_name); 1513 if (!ocelot->stats_queue) 1514 return -ENOMEM; 1515 1516 ocelot->owq = alloc_ordered_workqueue("ocelot-owq", 0); 1517 if (!ocelot->owq) { 1518 destroy_workqueue(ocelot->stats_queue); 1519 return -ENOMEM; 1520 } 1521 1522 INIT_LIST_HEAD(&ocelot->multicast); 1523 INIT_LIST_HEAD(&ocelot->pgids); 1524 ocelot_mact_init(ocelot); 1525 ocelot_vlan_init(ocelot); 1526 ocelot_vcap_init(ocelot); 1527 ocelot_cpu_port_init(ocelot); 1528 1529 for (port = 0; port < ocelot->num_phys_ports; port++) { 1530 /* Clear all counters (5 groups) */ 1531 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) | 1532 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f), 1533 SYS_STAT_CFG); 1534 } 1535 1536 /* Only use S-Tag */ 1537 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG); 1538 1539 /* Aggregation mode */ 1540 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA | 1541 ANA_AGGR_CFG_AC_DMAC_ENA | 1542 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA | 1543 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, ANA_AGGR_CFG); 1544 1545 /* Set MAC age time to default value. The entry is aged after 1546 * 2*AGE_PERIOD 1547 */ 1548 ocelot_write(ocelot, 1549 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ), 1550 ANA_AUTOAGE); 1551 1552 /* Disable learning for frames discarded by VLAN ingress filtering */ 1553 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1); 1554 1555 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */ 1556 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA | 1557 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING); 1558 1559 /* Setup flooding PGIDs */ 1560 for (i = 0; i < ocelot->num_flooding_pgids; i++) 1561 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) | 1562 ANA_FLOODING_FLD_BROADCAST(PGID_MC) | 1563 ANA_FLOODING_FLD_UNICAST(PGID_UC), 1564 ANA_FLOODING, i); 1565 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) | 1566 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) | 1567 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) | 1568 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC), 1569 ANA_FLOODING_IPMC); 1570 1571 for (port = 0; port < ocelot->num_phys_ports; port++) { 1572 /* Transmit the frame to the local port. */ 1573 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 1574 /* Do not forward BPDU frames to the front ports. */ 1575 ocelot_write_gix(ocelot, 1576 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff), 1577 ANA_PORT_CPU_FWD_BPDU_CFG, 1578 port); 1579 /* Ensure bridging is disabled */ 1580 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port); 1581 } 1582 1583 /* Allow broadcast MAC frames. */ 1584 for_each_nonreserved_multicast_dest_pgid(ocelot, i) { 1585 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0)); 1586 1587 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 1588 } 1589 ocelot_write_rix(ocelot, 1590 ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports, 0)), 1591 ANA_PGID_PGID, PGID_MC); 1592 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4); 1593 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6); 1594 1595 /* Allow manual injection via DEVCPU_QS registers, and byte swap these 1596 * registers endianness. 1597 */ 1598 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP | 1599 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0); 1600 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP | 1601 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0); 1602 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) | 1603 ANA_CPUQ_CFG_CPUQ_LRN(2) | 1604 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) | 1605 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) | 1606 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) | 1607 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) | 1608 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) | 1609 ANA_CPUQ_CFG_CPUQ_IGMP(6) | 1610 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG); 1611 for (i = 0; i < 16; i++) 1612 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) | 1613 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6), 1614 ANA_CPUQ_8021_CFG, i); 1615 1616 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats_work); 1617 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 1618 OCELOT_STATS_CHECK_DELAY); 1619 1620 return 0; 1621 } 1622 EXPORT_SYMBOL(ocelot_init); 1623 1624 void ocelot_deinit(struct ocelot *ocelot) 1625 { 1626 cancel_delayed_work(&ocelot->stats_work); 1627 destroy_workqueue(ocelot->stats_queue); 1628 destroy_workqueue(ocelot->owq); 1629 mutex_destroy(&ocelot->stats_lock); 1630 } 1631 EXPORT_SYMBOL(ocelot_deinit); 1632 1633 void ocelot_deinit_port(struct ocelot *ocelot, int port) 1634 { 1635 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1636 1637 skb_queue_purge(&ocelot_port->tx_skbs); 1638 } 1639 EXPORT_SYMBOL(ocelot_deinit_port); 1640 1641 MODULE_LICENSE("Dual MIT/GPL"); 1642