1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7 #include <linux/dsa/ocelot.h> 8 #include <linux/if_bridge.h> 9 #include <linux/ptp_classify.h> 10 #include <soc/mscc/ocelot_vcap.h> 11 #include "ocelot.h" 12 #include "ocelot_vcap.h" 13 14 #define TABLE_UPDATE_SLEEP_US 10 15 #define TABLE_UPDATE_TIMEOUT_US 100000 16 17 struct ocelot_mact_entry { 18 u8 mac[ETH_ALEN]; 19 u16 vid; 20 enum macaccess_entry_type type; 21 }; 22 23 /* Caller must hold &ocelot->mact_lock */ 24 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot) 25 { 26 return ocelot_read(ocelot, ANA_TABLES_MACACCESS); 27 } 28 29 /* Caller must hold &ocelot->mact_lock */ 30 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot) 31 { 32 u32 val; 33 34 return readx_poll_timeout(ocelot_mact_read_macaccess, 35 ocelot, val, 36 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) == 37 MACACCESS_CMD_IDLE, 38 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 39 } 40 41 /* Caller must hold &ocelot->mact_lock */ 42 static void ocelot_mact_select(struct ocelot *ocelot, 43 const unsigned char mac[ETH_ALEN], 44 unsigned int vid) 45 { 46 u32 macl = 0, mach = 0; 47 48 /* Set the MAC address to handle and the vlan associated in a format 49 * understood by the hardware. 50 */ 51 mach |= vid << 16; 52 mach |= mac[0] << 8; 53 mach |= mac[1] << 0; 54 macl |= mac[2] << 24; 55 macl |= mac[3] << 16; 56 macl |= mac[4] << 8; 57 macl |= mac[5] << 0; 58 59 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA); 60 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA); 61 62 } 63 64 static int __ocelot_mact_learn(struct ocelot *ocelot, int port, 65 const unsigned char mac[ETH_ALEN], 66 unsigned int vid, enum macaccess_entry_type type) 67 { 68 u32 cmd = ANA_TABLES_MACACCESS_VALID | 69 ANA_TABLES_MACACCESS_DEST_IDX(port) | 70 ANA_TABLES_MACACCESS_ENTRYTYPE(type) | 71 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN); 72 unsigned int mc_ports; 73 int err; 74 75 /* Set MAC_CPU_COPY if the CPU port is used by a multicast entry */ 76 if (type == ENTRYTYPE_MACv4) 77 mc_ports = (mac[1] << 8) | mac[2]; 78 else if (type == ENTRYTYPE_MACv6) 79 mc_ports = (mac[0] << 8) | mac[1]; 80 else 81 mc_ports = 0; 82 83 if (mc_ports & BIT(ocelot->num_phys_ports)) 84 cmd |= ANA_TABLES_MACACCESS_MAC_CPU_COPY; 85 86 ocelot_mact_select(ocelot, mac, vid); 87 88 /* Issue a write command */ 89 ocelot_write(ocelot, cmd, ANA_TABLES_MACACCESS); 90 91 err = ocelot_mact_wait_for_completion(ocelot); 92 93 return err; 94 } 95 96 int ocelot_mact_learn(struct ocelot *ocelot, int port, 97 const unsigned char mac[ETH_ALEN], 98 unsigned int vid, enum macaccess_entry_type type) 99 { 100 int ret; 101 102 mutex_lock(&ocelot->mact_lock); 103 ret = __ocelot_mact_learn(ocelot, port, mac, vid, type); 104 mutex_unlock(&ocelot->mact_lock); 105 106 return ret; 107 } 108 EXPORT_SYMBOL(ocelot_mact_learn); 109 110 int ocelot_mact_forget(struct ocelot *ocelot, 111 const unsigned char mac[ETH_ALEN], unsigned int vid) 112 { 113 int err; 114 115 mutex_lock(&ocelot->mact_lock); 116 117 ocelot_mact_select(ocelot, mac, vid); 118 119 /* Issue a forget command */ 120 ocelot_write(ocelot, 121 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET), 122 ANA_TABLES_MACACCESS); 123 124 err = ocelot_mact_wait_for_completion(ocelot); 125 126 mutex_unlock(&ocelot->mact_lock); 127 128 return err; 129 } 130 EXPORT_SYMBOL(ocelot_mact_forget); 131 132 int ocelot_mact_lookup(struct ocelot *ocelot, int *dst_idx, 133 const unsigned char mac[ETH_ALEN], 134 unsigned int vid, enum macaccess_entry_type *type) 135 { 136 int val; 137 138 mutex_lock(&ocelot->mact_lock); 139 140 ocelot_mact_select(ocelot, mac, vid); 141 142 /* Issue a read command with MACACCESS_VALID=1. */ 143 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID | 144 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 145 ANA_TABLES_MACACCESS); 146 147 if (ocelot_mact_wait_for_completion(ocelot)) { 148 mutex_unlock(&ocelot->mact_lock); 149 return -ETIMEDOUT; 150 } 151 152 /* Read back the entry flags */ 153 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 154 155 mutex_unlock(&ocelot->mact_lock); 156 157 if (!(val & ANA_TABLES_MACACCESS_VALID)) 158 return -ENOENT; 159 160 *dst_idx = ANA_TABLES_MACACCESS_DEST_IDX_X(val); 161 *type = ANA_TABLES_MACACCESS_ENTRYTYPE_X(val); 162 163 return 0; 164 } 165 EXPORT_SYMBOL(ocelot_mact_lookup); 166 167 int ocelot_mact_learn_streamdata(struct ocelot *ocelot, int dst_idx, 168 const unsigned char mac[ETH_ALEN], 169 unsigned int vid, 170 enum macaccess_entry_type type, 171 int sfid, int ssid) 172 { 173 int ret; 174 175 mutex_lock(&ocelot->mact_lock); 176 177 ocelot_write(ocelot, 178 (sfid < 0 ? 0 : ANA_TABLES_STREAMDATA_SFID_VALID) | 179 ANA_TABLES_STREAMDATA_SFID(sfid) | 180 (ssid < 0 ? 0 : ANA_TABLES_STREAMDATA_SSID_VALID) | 181 ANA_TABLES_STREAMDATA_SSID(ssid), 182 ANA_TABLES_STREAMDATA); 183 184 ret = __ocelot_mact_learn(ocelot, dst_idx, mac, vid, type); 185 186 mutex_unlock(&ocelot->mact_lock); 187 188 return ret; 189 } 190 EXPORT_SYMBOL(ocelot_mact_learn_streamdata); 191 192 static void ocelot_mact_init(struct ocelot *ocelot) 193 { 194 /* Configure the learning mode entries attributes: 195 * - Do not copy the frame to the CPU extraction queues. 196 * - Use the vlan and mac_cpoy for dmac lookup. 197 */ 198 ocelot_rmw(ocelot, 0, 199 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS 200 | ANA_AGENCTRL_LEARN_FWD_KILL 201 | ANA_AGENCTRL_LEARN_IGNORE_VLAN, 202 ANA_AGENCTRL); 203 204 /* Clear the MAC table. We are not concurrent with anyone, so 205 * holding &ocelot->mact_lock is pointless. 206 */ 207 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS); 208 } 209 210 static void ocelot_vcap_enable(struct ocelot *ocelot, int port) 211 { 212 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA | 213 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa), 214 ANA_PORT_VCAP_S2_CFG, port); 215 216 ocelot_write_gix(ocelot, ANA_PORT_VCAP_CFG_S1_ENA, 217 ANA_PORT_VCAP_CFG, port); 218 219 ocelot_rmw_gix(ocelot, REW_PORT_CFG_ES0_EN, 220 REW_PORT_CFG_ES0_EN, 221 REW_PORT_CFG, port); 222 } 223 224 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot) 225 { 226 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS); 227 } 228 229 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot) 230 { 231 u32 val; 232 233 return readx_poll_timeout(ocelot_vlant_read_vlanaccess, 234 ocelot, 235 val, 236 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) == 237 ANA_TABLES_VLANACCESS_CMD_IDLE, 238 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 239 } 240 241 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask) 242 { 243 /* Select the VID to configure */ 244 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid), 245 ANA_TABLES_VLANTIDX); 246 /* Set the vlan port members mask and issue a write command */ 247 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) | 248 ANA_TABLES_VLANACCESS_CMD_WRITE, 249 ANA_TABLES_VLANACCESS); 250 251 return ocelot_vlant_wait_for_completion(ocelot); 252 } 253 254 static int ocelot_port_num_untagged_vlans(struct ocelot *ocelot, int port) 255 { 256 struct ocelot_bridge_vlan *vlan; 257 int num_untagged = 0; 258 259 list_for_each_entry(vlan, &ocelot->vlans, list) { 260 if (!(vlan->portmask & BIT(port))) 261 continue; 262 263 if (vlan->untagged & BIT(port)) 264 num_untagged++; 265 } 266 267 return num_untagged; 268 } 269 270 static int ocelot_port_num_tagged_vlans(struct ocelot *ocelot, int port) 271 { 272 struct ocelot_bridge_vlan *vlan; 273 int num_tagged = 0; 274 275 list_for_each_entry(vlan, &ocelot->vlans, list) { 276 if (!(vlan->portmask & BIT(port))) 277 continue; 278 279 if (!(vlan->untagged & BIT(port))) 280 num_tagged++; 281 } 282 283 return num_tagged; 284 } 285 286 /* We use native VLAN when we have to mix egress-tagged VLANs with exactly 287 * _one_ egress-untagged VLAN (_the_ native VLAN) 288 */ 289 static bool ocelot_port_uses_native_vlan(struct ocelot *ocelot, int port) 290 { 291 return ocelot_port_num_tagged_vlans(ocelot, port) && 292 ocelot_port_num_untagged_vlans(ocelot, port) == 1; 293 } 294 295 static struct ocelot_bridge_vlan * 296 ocelot_port_find_native_vlan(struct ocelot *ocelot, int port) 297 { 298 struct ocelot_bridge_vlan *vlan; 299 300 list_for_each_entry(vlan, &ocelot->vlans, list) 301 if (vlan->portmask & BIT(port) && vlan->untagged & BIT(port)) 302 return vlan; 303 304 return NULL; 305 } 306 307 /* Keep in sync REW_TAG_CFG_TAG_CFG and, if applicable, 308 * REW_PORT_VLAN_CFG_PORT_VID, with the bridge VLAN table and VLAN awareness 309 * state of the port. 310 */ 311 static void ocelot_port_manage_port_tag(struct ocelot *ocelot, int port) 312 { 313 struct ocelot_port *ocelot_port = ocelot->ports[port]; 314 enum ocelot_port_tag_config tag_cfg; 315 bool uses_native_vlan = false; 316 317 if (ocelot_port->vlan_aware) { 318 uses_native_vlan = ocelot_port_uses_native_vlan(ocelot, port); 319 320 if (uses_native_vlan) 321 tag_cfg = OCELOT_PORT_TAG_NATIVE; 322 else if (ocelot_port_num_untagged_vlans(ocelot, port)) 323 tag_cfg = OCELOT_PORT_TAG_DISABLED; 324 else 325 tag_cfg = OCELOT_PORT_TAG_TRUNK; 326 } else { 327 tag_cfg = OCELOT_PORT_TAG_DISABLED; 328 } 329 330 ocelot_rmw_gix(ocelot, REW_TAG_CFG_TAG_CFG(tag_cfg), 331 REW_TAG_CFG_TAG_CFG_M, 332 REW_TAG_CFG, port); 333 334 if (uses_native_vlan) { 335 struct ocelot_bridge_vlan *native_vlan; 336 337 /* Not having a native VLAN is impossible, because 338 * ocelot_port_num_untagged_vlans has returned 1. 339 * So there is no use in checking for NULL here. 340 */ 341 native_vlan = ocelot_port_find_native_vlan(ocelot, port); 342 343 ocelot_rmw_gix(ocelot, 344 REW_PORT_VLAN_CFG_PORT_VID(native_vlan->vid), 345 REW_PORT_VLAN_CFG_PORT_VID_M, 346 REW_PORT_VLAN_CFG, port); 347 } 348 } 349 350 /* Default vlan to clasify for untagged frames (may be zero) */ 351 static void ocelot_port_set_pvid(struct ocelot *ocelot, int port, 352 const struct ocelot_bridge_vlan *pvid_vlan) 353 { 354 struct ocelot_port *ocelot_port = ocelot->ports[port]; 355 u16 pvid = OCELOT_VLAN_UNAWARE_PVID; 356 u32 val = 0; 357 358 ocelot_port->pvid_vlan = pvid_vlan; 359 360 if (ocelot_port->vlan_aware && pvid_vlan) 361 pvid = pvid_vlan->vid; 362 363 ocelot_rmw_gix(ocelot, 364 ANA_PORT_VLAN_CFG_VLAN_VID(pvid), 365 ANA_PORT_VLAN_CFG_VLAN_VID_M, 366 ANA_PORT_VLAN_CFG, port); 367 368 /* If there's no pvid, we should drop not only untagged traffic (which 369 * happens automatically), but also 802.1p traffic which gets 370 * classified to VLAN 0, but that is always in our RX filter, so it 371 * would get accepted were it not for this setting. 372 */ 373 if (!pvid_vlan && ocelot_port->vlan_aware) 374 val = ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 375 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA; 376 377 ocelot_rmw_gix(ocelot, val, 378 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 379 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, 380 ANA_PORT_DROP_CFG, port); 381 } 382 383 static struct ocelot_bridge_vlan *ocelot_bridge_vlan_find(struct ocelot *ocelot, 384 u16 vid) 385 { 386 struct ocelot_bridge_vlan *vlan; 387 388 list_for_each_entry(vlan, &ocelot->vlans, list) 389 if (vlan->vid == vid) 390 return vlan; 391 392 return NULL; 393 } 394 395 static int ocelot_vlan_member_add(struct ocelot *ocelot, int port, u16 vid, 396 bool untagged) 397 { 398 struct ocelot_bridge_vlan *vlan = ocelot_bridge_vlan_find(ocelot, vid); 399 unsigned long portmask; 400 int err; 401 402 if (vlan) { 403 portmask = vlan->portmask | BIT(port); 404 405 err = ocelot_vlant_set_mask(ocelot, vid, portmask); 406 if (err) 407 return err; 408 409 vlan->portmask = portmask; 410 /* Bridge VLANs can be overwritten with a different 411 * egress-tagging setting, so make sure to override an untagged 412 * with a tagged VID if that's going on. 413 */ 414 if (untagged) 415 vlan->untagged |= BIT(port); 416 else 417 vlan->untagged &= ~BIT(port); 418 419 return 0; 420 } 421 422 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL); 423 if (!vlan) 424 return -ENOMEM; 425 426 portmask = BIT(port); 427 428 err = ocelot_vlant_set_mask(ocelot, vid, portmask); 429 if (err) { 430 kfree(vlan); 431 return err; 432 } 433 434 vlan->vid = vid; 435 vlan->portmask = portmask; 436 if (untagged) 437 vlan->untagged = BIT(port); 438 INIT_LIST_HEAD(&vlan->list); 439 list_add_tail(&vlan->list, &ocelot->vlans); 440 441 return 0; 442 } 443 444 static int ocelot_vlan_member_del(struct ocelot *ocelot, int port, u16 vid) 445 { 446 struct ocelot_bridge_vlan *vlan = ocelot_bridge_vlan_find(ocelot, vid); 447 unsigned long portmask; 448 int err; 449 450 if (!vlan) 451 return 0; 452 453 portmask = vlan->portmask & ~BIT(port); 454 455 err = ocelot_vlant_set_mask(ocelot, vid, portmask); 456 if (err) 457 return err; 458 459 vlan->portmask = portmask; 460 if (vlan->portmask) 461 return 0; 462 463 list_del(&vlan->list); 464 kfree(vlan); 465 466 return 0; 467 } 468 469 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, 470 bool vlan_aware, struct netlink_ext_ack *extack) 471 { 472 struct ocelot_vcap_block *block = &ocelot->block[VCAP_IS1]; 473 struct ocelot_port *ocelot_port = ocelot->ports[port]; 474 struct ocelot_vcap_filter *filter; 475 u32 val; 476 477 list_for_each_entry(filter, &block->rules, list) { 478 if (filter->ingress_port_mask & BIT(port) && 479 filter->action.vid_replace_ena) { 480 NL_SET_ERR_MSG_MOD(extack, 481 "Cannot change VLAN state with vlan modify rules active"); 482 return -EBUSY; 483 } 484 } 485 486 ocelot_port->vlan_aware = vlan_aware; 487 488 if (vlan_aware) 489 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 490 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1); 491 else 492 val = 0; 493 ocelot_rmw_gix(ocelot, val, 494 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 495 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M, 496 ANA_PORT_VLAN_CFG, port); 497 498 ocelot_port_set_pvid(ocelot, port, ocelot_port->pvid_vlan); 499 ocelot_port_manage_port_tag(ocelot, port); 500 501 return 0; 502 } 503 EXPORT_SYMBOL(ocelot_port_vlan_filtering); 504 505 int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid, 506 bool untagged, struct netlink_ext_ack *extack) 507 { 508 if (untagged) { 509 /* We are adding an egress-tagged VLAN */ 510 if (ocelot_port_uses_native_vlan(ocelot, port)) { 511 NL_SET_ERR_MSG_MOD(extack, 512 "Port with egress-tagged VLANs cannot have more than one egress-untagged (native) VLAN"); 513 return -EBUSY; 514 } 515 } else { 516 /* We are adding an egress-tagged VLAN */ 517 if (ocelot_port_num_untagged_vlans(ocelot, port) > 1) { 518 NL_SET_ERR_MSG_MOD(extack, 519 "Port with more than one egress-untagged VLAN cannot have egress-tagged VLANs"); 520 return -EBUSY; 521 } 522 } 523 524 return 0; 525 } 526 EXPORT_SYMBOL(ocelot_vlan_prepare); 527 528 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid, 529 bool untagged) 530 { 531 int err; 532 533 err = ocelot_vlan_member_add(ocelot, port, vid, untagged); 534 if (err) 535 return err; 536 537 /* Default ingress vlan classification */ 538 if (pvid) 539 ocelot_port_set_pvid(ocelot, port, 540 ocelot_bridge_vlan_find(ocelot, vid)); 541 542 /* Untagged egress vlan clasification */ 543 ocelot_port_manage_port_tag(ocelot, port); 544 545 return 0; 546 } 547 EXPORT_SYMBOL(ocelot_vlan_add); 548 549 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid) 550 { 551 struct ocelot_port *ocelot_port = ocelot->ports[port]; 552 int err; 553 554 err = ocelot_vlan_member_del(ocelot, port, vid); 555 if (err) 556 return err; 557 558 /* Ingress */ 559 if (ocelot_port->pvid_vlan && ocelot_port->pvid_vlan->vid == vid) 560 ocelot_port_set_pvid(ocelot, port, NULL); 561 562 /* Egress */ 563 ocelot_port_manage_port_tag(ocelot, port); 564 565 return 0; 566 } 567 EXPORT_SYMBOL(ocelot_vlan_del); 568 569 static void ocelot_vlan_init(struct ocelot *ocelot) 570 { 571 unsigned long all_ports = GENMASK(ocelot->num_phys_ports - 1, 0); 572 u16 port, vid; 573 574 /* Clear VLAN table, by default all ports are members of all VLANs */ 575 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT, 576 ANA_TABLES_VLANACCESS); 577 ocelot_vlant_wait_for_completion(ocelot); 578 579 /* Configure the port VLAN memberships */ 580 for (vid = 1; vid < VLAN_N_VID; vid++) 581 ocelot_vlant_set_mask(ocelot, vid, 0); 582 583 /* Because VLAN filtering is enabled, we need VID 0 to get untagged 584 * traffic. It is added automatically if 8021q module is loaded, but 585 * we can't rely on it since module may be not loaded. 586 */ 587 ocelot_vlant_set_mask(ocelot, OCELOT_VLAN_UNAWARE_PVID, all_ports); 588 589 /* Set vlan ingress filter mask to all ports but the CPU port by 590 * default. 591 */ 592 ocelot_write(ocelot, all_ports, ANA_VLANMASK); 593 594 for (port = 0; port < ocelot->num_phys_ports; port++) { 595 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port); 596 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port); 597 } 598 } 599 600 static u32 ocelot_read_eq_avail(struct ocelot *ocelot, int port) 601 { 602 return ocelot_read_rix(ocelot, QSYS_SW_STATUS, port); 603 } 604 605 static int ocelot_port_flush(struct ocelot *ocelot, int port) 606 { 607 unsigned int pause_ena; 608 int err, val; 609 610 /* Disable dequeuing from the egress queues */ 611 ocelot_rmw_rix(ocelot, QSYS_PORT_MODE_DEQUEUE_DIS, 612 QSYS_PORT_MODE_DEQUEUE_DIS, 613 QSYS_PORT_MODE, port); 614 615 /* Disable flow control */ 616 ocelot_fields_read(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, &pause_ena); 617 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 0); 618 619 /* Disable priority flow control */ 620 ocelot_fields_write(ocelot, port, 621 QSYS_SWITCH_PORT_MODE_TX_PFC_ENA, 0); 622 623 /* Wait at least the time it takes to receive a frame of maximum length 624 * at the port. 625 * Worst-case delays for 10 kilobyte jumbo frames are: 626 * 8 ms on a 10M port 627 * 800 μs on a 100M port 628 * 80 μs on a 1G port 629 * 32 μs on a 2.5G port 630 */ 631 usleep_range(8000, 10000); 632 633 /* Disable half duplex backpressure. */ 634 ocelot_rmw_rix(ocelot, 0, SYS_FRONT_PORT_MODE_HDX_MODE, 635 SYS_FRONT_PORT_MODE, port); 636 637 /* Flush the queues associated with the port. */ 638 ocelot_rmw_gix(ocelot, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG_FLUSH_ENA, 639 REW_PORT_CFG, port); 640 641 /* Enable dequeuing from the egress queues. */ 642 ocelot_rmw_rix(ocelot, 0, QSYS_PORT_MODE_DEQUEUE_DIS, QSYS_PORT_MODE, 643 port); 644 645 /* Wait until flushing is complete. */ 646 err = read_poll_timeout(ocelot_read_eq_avail, val, !val, 647 100, 2000000, false, ocelot, port); 648 649 /* Clear flushing again. */ 650 ocelot_rmw_gix(ocelot, 0, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG, port); 651 652 /* Re-enable flow control */ 653 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, pause_ena); 654 655 return err; 656 } 657 658 void ocelot_phylink_mac_link_down(struct ocelot *ocelot, int port, 659 unsigned int link_an_mode, 660 phy_interface_t interface, 661 unsigned long quirks) 662 { 663 struct ocelot_port *ocelot_port = ocelot->ports[port]; 664 int err; 665 666 ocelot_port->speed = SPEED_UNKNOWN; 667 668 ocelot_port_rmwl(ocelot_port, 0, DEV_MAC_ENA_CFG_RX_ENA, 669 DEV_MAC_ENA_CFG); 670 671 if (ocelot->ops->cut_through_fwd) { 672 mutex_lock(&ocelot->fwd_domain_lock); 673 ocelot->ops->cut_through_fwd(ocelot); 674 mutex_unlock(&ocelot->fwd_domain_lock); 675 } 676 677 ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0); 678 679 err = ocelot_port_flush(ocelot, port); 680 if (err) 681 dev_err(ocelot->dev, "failed to flush port %d: %d\n", 682 port, err); 683 684 /* Put the port in reset. */ 685 if (interface != PHY_INTERFACE_MODE_QSGMII || 686 !(quirks & OCELOT_QUIRK_QSGMII_PORTS_MUST_BE_UP)) 687 ocelot_port_rmwl(ocelot_port, 688 DEV_CLOCK_CFG_MAC_TX_RST | 689 DEV_CLOCK_CFG_MAC_RX_RST, 690 DEV_CLOCK_CFG_MAC_TX_RST | 691 DEV_CLOCK_CFG_MAC_RX_RST, 692 DEV_CLOCK_CFG); 693 } 694 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_down); 695 696 void ocelot_phylink_mac_link_up(struct ocelot *ocelot, int port, 697 struct phy_device *phydev, 698 unsigned int link_an_mode, 699 phy_interface_t interface, 700 int speed, int duplex, 701 bool tx_pause, bool rx_pause, 702 unsigned long quirks) 703 { 704 struct ocelot_port *ocelot_port = ocelot->ports[port]; 705 int mac_speed, mode = 0; 706 u32 mac_fc_cfg; 707 708 ocelot_port->speed = speed; 709 710 /* The MAC might be integrated in systems where the MAC speed is fixed 711 * and it's the PCS who is performing the rate adaptation, so we have 712 * to write "1000Mbps" into the LINK_SPEED field of DEV_CLOCK_CFG 713 * (which is also its default value). 714 */ 715 if ((quirks & OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION) || 716 speed == SPEED_1000) { 717 mac_speed = OCELOT_SPEED_1000; 718 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 719 } else if (speed == SPEED_2500) { 720 mac_speed = OCELOT_SPEED_2500; 721 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 722 } else if (speed == SPEED_100) { 723 mac_speed = OCELOT_SPEED_100; 724 } else { 725 mac_speed = OCELOT_SPEED_10; 726 } 727 728 if (duplex == DUPLEX_FULL) 729 mode |= DEV_MAC_MODE_CFG_FDX_ENA; 730 731 ocelot_port_writel(ocelot_port, mode, DEV_MAC_MODE_CFG); 732 733 /* Take port out of reset by clearing the MAC_TX_RST, MAC_RX_RST and 734 * PORT_RST bits in DEV_CLOCK_CFG. 735 */ 736 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(mac_speed), 737 DEV_CLOCK_CFG); 738 739 switch (speed) { 740 case SPEED_10: 741 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_10); 742 break; 743 case SPEED_100: 744 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_100); 745 break; 746 case SPEED_1000: 747 case SPEED_2500: 748 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_1000); 749 break; 750 default: 751 dev_err(ocelot->dev, "Unsupported speed on port %d: %d\n", 752 port, speed); 753 return; 754 } 755 756 /* Handle RX pause in all cases, with 2500base-X this is used for rate 757 * adaptation. 758 */ 759 mac_fc_cfg |= SYS_MAC_FC_CFG_RX_FC_ENA; 760 761 if (tx_pause) 762 mac_fc_cfg |= SYS_MAC_FC_CFG_TX_FC_ENA | 763 SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) | 764 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) | 765 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA; 766 767 /* Flow control. Link speed is only used here to evaluate the time 768 * specification in incoming pause frames. 769 */ 770 ocelot_write_rix(ocelot, mac_fc_cfg, SYS_MAC_FC_CFG, port); 771 772 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port); 773 774 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, tx_pause); 775 776 /* Undo the effects of ocelot_phylink_mac_link_down: 777 * enable MAC module 778 */ 779 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA | 780 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG); 781 782 /* If the port supports cut-through forwarding, update the masks before 783 * enabling forwarding on the port. 784 */ 785 if (ocelot->ops->cut_through_fwd) { 786 mutex_lock(&ocelot->fwd_domain_lock); 787 ocelot->ops->cut_through_fwd(ocelot); 788 mutex_unlock(&ocelot->fwd_domain_lock); 789 } 790 791 /* Core: Enable port for frame transfer */ 792 ocelot_fields_write(ocelot, port, 793 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 794 } 795 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_up); 796 797 static int ocelot_port_add_txtstamp_skb(struct ocelot *ocelot, int port, 798 struct sk_buff *clone) 799 { 800 struct ocelot_port *ocelot_port = ocelot->ports[port]; 801 unsigned long flags; 802 803 spin_lock_irqsave(&ocelot->ts_id_lock, flags); 804 805 if (ocelot_port->ptp_skbs_in_flight == OCELOT_MAX_PTP_ID || 806 ocelot->ptp_skbs_in_flight == OCELOT_PTP_FIFO_SIZE) { 807 spin_unlock_irqrestore(&ocelot->ts_id_lock, flags); 808 return -EBUSY; 809 } 810 811 skb_shinfo(clone)->tx_flags |= SKBTX_IN_PROGRESS; 812 /* Store timestamp ID in OCELOT_SKB_CB(clone)->ts_id */ 813 OCELOT_SKB_CB(clone)->ts_id = ocelot_port->ts_id; 814 815 ocelot_port->ts_id++; 816 if (ocelot_port->ts_id == OCELOT_MAX_PTP_ID) 817 ocelot_port->ts_id = 0; 818 819 ocelot_port->ptp_skbs_in_flight++; 820 ocelot->ptp_skbs_in_flight++; 821 822 skb_queue_tail(&ocelot_port->tx_skbs, clone); 823 824 spin_unlock_irqrestore(&ocelot->ts_id_lock, flags); 825 826 return 0; 827 } 828 829 static bool ocelot_ptp_is_onestep_sync(struct sk_buff *skb, 830 unsigned int ptp_class) 831 { 832 struct ptp_header *hdr; 833 u8 msgtype, twostep; 834 835 hdr = ptp_parse_header(skb, ptp_class); 836 if (!hdr) 837 return false; 838 839 msgtype = ptp_get_msgtype(hdr, ptp_class); 840 twostep = hdr->flag_field[0] & 0x2; 841 842 if (msgtype == PTP_MSGTYPE_SYNC && twostep == 0) 843 return true; 844 845 return false; 846 } 847 848 int ocelot_port_txtstamp_request(struct ocelot *ocelot, int port, 849 struct sk_buff *skb, 850 struct sk_buff **clone) 851 { 852 struct ocelot_port *ocelot_port = ocelot->ports[port]; 853 u8 ptp_cmd = ocelot_port->ptp_cmd; 854 unsigned int ptp_class; 855 int err; 856 857 /* Don't do anything if PTP timestamping not enabled */ 858 if (!ptp_cmd) 859 return 0; 860 861 ptp_class = ptp_classify_raw(skb); 862 if (ptp_class == PTP_CLASS_NONE) 863 return -EINVAL; 864 865 /* Store ptp_cmd in OCELOT_SKB_CB(skb)->ptp_cmd */ 866 if (ptp_cmd == IFH_REW_OP_ORIGIN_PTP) { 867 if (ocelot_ptp_is_onestep_sync(skb, ptp_class)) { 868 OCELOT_SKB_CB(skb)->ptp_cmd = ptp_cmd; 869 return 0; 870 } 871 872 /* Fall back to two-step timestamping */ 873 ptp_cmd = IFH_REW_OP_TWO_STEP_PTP; 874 } 875 876 if (ptp_cmd == IFH_REW_OP_TWO_STEP_PTP) { 877 *clone = skb_clone_sk(skb); 878 if (!(*clone)) 879 return -ENOMEM; 880 881 err = ocelot_port_add_txtstamp_skb(ocelot, port, *clone); 882 if (err) 883 return err; 884 885 OCELOT_SKB_CB(skb)->ptp_cmd = ptp_cmd; 886 OCELOT_SKB_CB(*clone)->ptp_class = ptp_class; 887 } 888 889 return 0; 890 } 891 EXPORT_SYMBOL(ocelot_port_txtstamp_request); 892 893 static void ocelot_get_hwtimestamp(struct ocelot *ocelot, 894 struct timespec64 *ts) 895 { 896 unsigned long flags; 897 u32 val; 898 899 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); 900 901 /* Read current PTP time to get seconds */ 902 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 903 904 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 905 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE); 906 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 907 ts->tv_sec = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN); 908 909 /* Read packet HW timestamp from FIFO */ 910 val = ocelot_read(ocelot, SYS_PTP_TXSTAMP); 911 ts->tv_nsec = SYS_PTP_TXSTAMP_PTP_TXSTAMP(val); 912 913 /* Sec has incremented since the ts was registered */ 914 if ((ts->tv_sec & 0x1) != !!(val & SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC)) 915 ts->tv_sec--; 916 917 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 918 } 919 920 static bool ocelot_validate_ptp_skb(struct sk_buff *clone, u16 seqid) 921 { 922 struct ptp_header *hdr; 923 924 hdr = ptp_parse_header(clone, OCELOT_SKB_CB(clone)->ptp_class); 925 if (WARN_ON(!hdr)) 926 return false; 927 928 return seqid == ntohs(hdr->sequence_id); 929 } 930 931 void ocelot_get_txtstamp(struct ocelot *ocelot) 932 { 933 int budget = OCELOT_PTP_QUEUE_SZ; 934 935 while (budget--) { 936 struct sk_buff *skb, *skb_tmp, *skb_match = NULL; 937 struct skb_shared_hwtstamps shhwtstamps; 938 u32 val, id, seqid, txport; 939 struct ocelot_port *port; 940 struct timespec64 ts; 941 unsigned long flags; 942 943 val = ocelot_read(ocelot, SYS_PTP_STATUS); 944 945 /* Check if a timestamp can be retrieved */ 946 if (!(val & SYS_PTP_STATUS_PTP_MESS_VLD)) 947 break; 948 949 WARN_ON(val & SYS_PTP_STATUS_PTP_OVFL); 950 951 /* Retrieve the ts ID and Tx port */ 952 id = SYS_PTP_STATUS_PTP_MESS_ID_X(val); 953 txport = SYS_PTP_STATUS_PTP_MESS_TXPORT_X(val); 954 seqid = SYS_PTP_STATUS_PTP_MESS_SEQ_ID(val); 955 956 port = ocelot->ports[txport]; 957 958 spin_lock(&ocelot->ts_id_lock); 959 port->ptp_skbs_in_flight--; 960 ocelot->ptp_skbs_in_flight--; 961 spin_unlock(&ocelot->ts_id_lock); 962 963 /* Retrieve its associated skb */ 964 try_again: 965 spin_lock_irqsave(&port->tx_skbs.lock, flags); 966 967 skb_queue_walk_safe(&port->tx_skbs, skb, skb_tmp) { 968 if (OCELOT_SKB_CB(skb)->ts_id != id) 969 continue; 970 __skb_unlink(skb, &port->tx_skbs); 971 skb_match = skb; 972 break; 973 } 974 975 spin_unlock_irqrestore(&port->tx_skbs.lock, flags); 976 977 if (WARN_ON(!skb_match)) 978 continue; 979 980 if (!ocelot_validate_ptp_skb(skb_match, seqid)) { 981 dev_err_ratelimited(ocelot->dev, 982 "port %d received stale TX timestamp for seqid %d, discarding\n", 983 txport, seqid); 984 dev_kfree_skb_any(skb); 985 goto try_again; 986 } 987 988 /* Get the h/w timestamp */ 989 ocelot_get_hwtimestamp(ocelot, &ts); 990 991 /* Set the timestamp into the skb */ 992 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 993 shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec); 994 skb_complete_tx_timestamp(skb_match, &shhwtstamps); 995 996 /* Next ts */ 997 ocelot_write(ocelot, SYS_PTP_NXT_PTP_NXT, SYS_PTP_NXT); 998 } 999 } 1000 EXPORT_SYMBOL(ocelot_get_txtstamp); 1001 1002 static int ocelot_rx_frame_word(struct ocelot *ocelot, u8 grp, bool ifh, 1003 u32 *rval) 1004 { 1005 u32 bytes_valid, val; 1006 1007 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1008 if (val == XTR_NOT_READY) { 1009 if (ifh) 1010 return -EIO; 1011 1012 do { 1013 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1014 } while (val == XTR_NOT_READY); 1015 } 1016 1017 switch (val) { 1018 case XTR_ABORT: 1019 return -EIO; 1020 case XTR_EOF_0: 1021 case XTR_EOF_1: 1022 case XTR_EOF_2: 1023 case XTR_EOF_3: 1024 case XTR_PRUNED: 1025 bytes_valid = XTR_VALID_BYTES(val); 1026 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1027 if (val == XTR_ESCAPE) 1028 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1029 else 1030 *rval = val; 1031 1032 return bytes_valid; 1033 case XTR_ESCAPE: 1034 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1035 1036 return 4; 1037 default: 1038 *rval = val; 1039 1040 return 4; 1041 } 1042 } 1043 1044 static int ocelot_xtr_poll_xfh(struct ocelot *ocelot, int grp, u32 *xfh) 1045 { 1046 int i, err = 0; 1047 1048 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) { 1049 err = ocelot_rx_frame_word(ocelot, grp, true, &xfh[i]); 1050 if (err != 4) 1051 return (err < 0) ? err : -EIO; 1052 } 1053 1054 return 0; 1055 } 1056 1057 int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **nskb) 1058 { 1059 struct skb_shared_hwtstamps *shhwtstamps; 1060 u64 tod_in_ns, full_ts_in_ns; 1061 u64 timestamp, src_port, len; 1062 u32 xfh[OCELOT_TAG_LEN / 4]; 1063 struct net_device *dev; 1064 struct timespec64 ts; 1065 struct sk_buff *skb; 1066 int sz, buf_len; 1067 u32 val, *buf; 1068 int err; 1069 1070 err = ocelot_xtr_poll_xfh(ocelot, grp, xfh); 1071 if (err) 1072 return err; 1073 1074 ocelot_xfh_get_src_port(xfh, &src_port); 1075 ocelot_xfh_get_len(xfh, &len); 1076 ocelot_xfh_get_rew_val(xfh, ×tamp); 1077 1078 if (WARN_ON(src_port >= ocelot->num_phys_ports)) 1079 return -EINVAL; 1080 1081 dev = ocelot->ops->port_to_netdev(ocelot, src_port); 1082 if (!dev) 1083 return -EINVAL; 1084 1085 skb = netdev_alloc_skb(dev, len); 1086 if (unlikely(!skb)) { 1087 netdev_err(dev, "Unable to allocate sk_buff\n"); 1088 return -ENOMEM; 1089 } 1090 1091 buf_len = len - ETH_FCS_LEN; 1092 buf = (u32 *)skb_put(skb, buf_len); 1093 1094 len = 0; 1095 do { 1096 sz = ocelot_rx_frame_word(ocelot, grp, false, &val); 1097 if (sz < 0) { 1098 err = sz; 1099 goto out_free_skb; 1100 } 1101 *buf++ = val; 1102 len += sz; 1103 } while (len < buf_len); 1104 1105 /* Read the FCS */ 1106 sz = ocelot_rx_frame_word(ocelot, grp, false, &val); 1107 if (sz < 0) { 1108 err = sz; 1109 goto out_free_skb; 1110 } 1111 1112 /* Update the statistics if part of the FCS was read before */ 1113 len -= ETH_FCS_LEN - sz; 1114 1115 if (unlikely(dev->features & NETIF_F_RXFCS)) { 1116 buf = (u32 *)skb_put(skb, ETH_FCS_LEN); 1117 *buf = val; 1118 } 1119 1120 if (ocelot->ptp) { 1121 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); 1122 1123 tod_in_ns = ktime_set(ts.tv_sec, ts.tv_nsec); 1124 if ((tod_in_ns & 0xffffffff) < timestamp) 1125 full_ts_in_ns = (((tod_in_ns >> 32) - 1) << 32) | 1126 timestamp; 1127 else 1128 full_ts_in_ns = (tod_in_ns & GENMASK_ULL(63, 32)) | 1129 timestamp; 1130 1131 shhwtstamps = skb_hwtstamps(skb); 1132 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps)); 1133 shhwtstamps->hwtstamp = full_ts_in_ns; 1134 } 1135 1136 /* Everything we see on an interface that is in the HW bridge 1137 * has already been forwarded. 1138 */ 1139 if (ocelot->ports[src_port]->bridge) 1140 skb->offload_fwd_mark = 1; 1141 1142 skb->protocol = eth_type_trans(skb, dev); 1143 1144 *nskb = skb; 1145 1146 return 0; 1147 1148 out_free_skb: 1149 kfree_skb(skb); 1150 return err; 1151 } 1152 EXPORT_SYMBOL(ocelot_xtr_poll_frame); 1153 1154 bool ocelot_can_inject(struct ocelot *ocelot, int grp) 1155 { 1156 u32 val = ocelot_read(ocelot, QS_INJ_STATUS); 1157 1158 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp)))) 1159 return false; 1160 if (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp))) 1161 return false; 1162 1163 return true; 1164 } 1165 EXPORT_SYMBOL(ocelot_can_inject); 1166 1167 void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp, 1168 u32 rew_op, struct sk_buff *skb) 1169 { 1170 u32 ifh[OCELOT_TAG_LEN / 4] = {0}; 1171 unsigned int i, count, last; 1172 1173 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 1174 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp); 1175 1176 ocelot_ifh_set_bypass(ifh, 1); 1177 ocelot_ifh_set_dest(ifh, BIT_ULL(port)); 1178 ocelot_ifh_set_tag_type(ifh, IFH_TAG_TYPE_C); 1179 ocelot_ifh_set_vlan_tci(ifh, skb_vlan_tag_get(skb)); 1180 ocelot_ifh_set_rew_op(ifh, rew_op); 1181 1182 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) 1183 ocelot_write_rix(ocelot, ifh[i], QS_INJ_WR, grp); 1184 1185 count = DIV_ROUND_UP(skb->len, 4); 1186 last = skb->len % 4; 1187 for (i = 0; i < count; i++) 1188 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp); 1189 1190 /* Add padding */ 1191 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) { 1192 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 1193 i++; 1194 } 1195 1196 /* Indicate EOF and valid bytes in last word */ 1197 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 1198 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) | 1199 QS_INJ_CTRL_EOF, 1200 QS_INJ_CTRL, grp); 1201 1202 /* Add dummy CRC */ 1203 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 1204 skb_tx_timestamp(skb); 1205 1206 skb->dev->stats.tx_packets++; 1207 skb->dev->stats.tx_bytes += skb->len; 1208 } 1209 EXPORT_SYMBOL(ocelot_port_inject_frame); 1210 1211 void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp) 1212 { 1213 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)) 1214 ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1215 } 1216 EXPORT_SYMBOL(ocelot_drain_cpu_queue); 1217 1218 int ocelot_fdb_add(struct ocelot *ocelot, int port, 1219 const unsigned char *addr, u16 vid) 1220 { 1221 int pgid = port; 1222 1223 if (port == ocelot->npi) 1224 pgid = PGID_CPU; 1225 1226 return ocelot_mact_learn(ocelot, pgid, addr, vid, ENTRYTYPE_LOCKED); 1227 } 1228 EXPORT_SYMBOL(ocelot_fdb_add); 1229 1230 int ocelot_fdb_del(struct ocelot *ocelot, int port, 1231 const unsigned char *addr, u16 vid) 1232 { 1233 return ocelot_mact_forget(ocelot, addr, vid); 1234 } 1235 EXPORT_SYMBOL(ocelot_fdb_del); 1236 1237 int ocelot_port_fdb_do_dump(const unsigned char *addr, u16 vid, 1238 bool is_static, void *data) 1239 { 1240 struct ocelot_dump_ctx *dump = data; 1241 u32 portid = NETLINK_CB(dump->cb->skb).portid; 1242 u32 seq = dump->cb->nlh->nlmsg_seq; 1243 struct nlmsghdr *nlh; 1244 struct ndmsg *ndm; 1245 1246 if (dump->idx < dump->cb->args[2]) 1247 goto skip; 1248 1249 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH, 1250 sizeof(*ndm), NLM_F_MULTI); 1251 if (!nlh) 1252 return -EMSGSIZE; 1253 1254 ndm = nlmsg_data(nlh); 1255 ndm->ndm_family = AF_BRIDGE; 1256 ndm->ndm_pad1 = 0; 1257 ndm->ndm_pad2 = 0; 1258 ndm->ndm_flags = NTF_SELF; 1259 ndm->ndm_type = 0; 1260 ndm->ndm_ifindex = dump->dev->ifindex; 1261 ndm->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE; 1262 1263 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, addr)) 1264 goto nla_put_failure; 1265 1266 if (vid && nla_put_u16(dump->skb, NDA_VLAN, vid)) 1267 goto nla_put_failure; 1268 1269 nlmsg_end(dump->skb, nlh); 1270 1271 skip: 1272 dump->idx++; 1273 return 0; 1274 1275 nla_put_failure: 1276 nlmsg_cancel(dump->skb, nlh); 1277 return -EMSGSIZE; 1278 } 1279 EXPORT_SYMBOL(ocelot_port_fdb_do_dump); 1280 1281 /* Caller must hold &ocelot->mact_lock */ 1282 static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col, 1283 struct ocelot_mact_entry *entry) 1284 { 1285 u32 val, dst, macl, mach; 1286 char mac[ETH_ALEN]; 1287 1288 /* Set row and column to read from */ 1289 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row); 1290 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col); 1291 1292 /* Issue a read command */ 1293 ocelot_write(ocelot, 1294 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 1295 ANA_TABLES_MACACCESS); 1296 1297 if (ocelot_mact_wait_for_completion(ocelot)) 1298 return -ETIMEDOUT; 1299 1300 /* Read the entry flags */ 1301 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 1302 if (!(val & ANA_TABLES_MACACCESS_VALID)) 1303 return -EINVAL; 1304 1305 /* If the entry read has another port configured as its destination, 1306 * do not report it. 1307 */ 1308 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3; 1309 if (dst != port) 1310 return -EINVAL; 1311 1312 /* Get the entry's MAC address and VLAN id */ 1313 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA); 1314 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA); 1315 1316 mac[0] = (mach >> 8) & 0xff; 1317 mac[1] = (mach >> 0) & 0xff; 1318 mac[2] = (macl >> 24) & 0xff; 1319 mac[3] = (macl >> 16) & 0xff; 1320 mac[4] = (macl >> 8) & 0xff; 1321 mac[5] = (macl >> 0) & 0xff; 1322 1323 entry->vid = (mach >> 16) & 0xfff; 1324 ether_addr_copy(entry->mac, mac); 1325 1326 return 0; 1327 } 1328 1329 int ocelot_fdb_dump(struct ocelot *ocelot, int port, 1330 dsa_fdb_dump_cb_t *cb, void *data) 1331 { 1332 int err = 0; 1333 int i, j; 1334 1335 /* We could take the lock just around ocelot_mact_read, but doing so 1336 * thousands of times in a row seems rather pointless and inefficient. 1337 */ 1338 mutex_lock(&ocelot->mact_lock); 1339 1340 /* Loop through all the mac tables entries. */ 1341 for (i = 0; i < ocelot->num_mact_rows; i++) { 1342 for (j = 0; j < 4; j++) { 1343 struct ocelot_mact_entry entry; 1344 bool is_static; 1345 1346 err = ocelot_mact_read(ocelot, port, i, j, &entry); 1347 /* If the entry is invalid (wrong port, invalid...), 1348 * skip it. 1349 */ 1350 if (err == -EINVAL) 1351 continue; 1352 else if (err) 1353 break; 1354 1355 is_static = (entry.type == ENTRYTYPE_LOCKED); 1356 1357 err = cb(entry.mac, entry.vid, is_static, data); 1358 if (err) 1359 break; 1360 } 1361 } 1362 1363 mutex_unlock(&ocelot->mact_lock); 1364 1365 return err; 1366 } 1367 EXPORT_SYMBOL(ocelot_fdb_dump); 1368 1369 static void ocelot_populate_l2_ptp_trap_key(struct ocelot_vcap_filter *trap) 1370 { 1371 trap->key_type = OCELOT_VCAP_KEY_ETYPE; 1372 *(__be16 *)trap->key.etype.etype.value = htons(ETH_P_1588); 1373 *(__be16 *)trap->key.etype.etype.mask = htons(0xffff); 1374 } 1375 1376 static void 1377 ocelot_populate_ipv4_ptp_event_trap_key(struct ocelot_vcap_filter *trap) 1378 { 1379 trap->key_type = OCELOT_VCAP_KEY_IPV4; 1380 trap->key.ipv4.dport.value = PTP_EV_PORT; 1381 trap->key.ipv4.dport.mask = 0xffff; 1382 } 1383 1384 static void 1385 ocelot_populate_ipv6_ptp_event_trap_key(struct ocelot_vcap_filter *trap) 1386 { 1387 trap->key_type = OCELOT_VCAP_KEY_IPV6; 1388 trap->key.ipv6.dport.value = PTP_EV_PORT; 1389 trap->key.ipv6.dport.mask = 0xffff; 1390 } 1391 1392 static void 1393 ocelot_populate_ipv4_ptp_general_trap_key(struct ocelot_vcap_filter *trap) 1394 { 1395 trap->key_type = OCELOT_VCAP_KEY_IPV4; 1396 trap->key.ipv4.dport.value = PTP_GEN_PORT; 1397 trap->key.ipv4.dport.mask = 0xffff; 1398 } 1399 1400 static void 1401 ocelot_populate_ipv6_ptp_general_trap_key(struct ocelot_vcap_filter *trap) 1402 { 1403 trap->key_type = OCELOT_VCAP_KEY_IPV6; 1404 trap->key.ipv6.dport.value = PTP_GEN_PORT; 1405 trap->key.ipv6.dport.mask = 0xffff; 1406 } 1407 1408 static int ocelot_trap_add(struct ocelot *ocelot, int port, 1409 unsigned long cookie, 1410 void (*populate)(struct ocelot_vcap_filter *f)) 1411 { 1412 struct ocelot_vcap_block *block_vcap_is2; 1413 struct ocelot_vcap_filter *trap; 1414 bool new = false; 1415 int err; 1416 1417 block_vcap_is2 = &ocelot->block[VCAP_IS2]; 1418 1419 trap = ocelot_vcap_block_find_filter_by_id(block_vcap_is2, cookie, 1420 false); 1421 if (!trap) { 1422 trap = kzalloc(sizeof(*trap), GFP_KERNEL); 1423 if (!trap) 1424 return -ENOMEM; 1425 1426 populate(trap); 1427 trap->prio = 1; 1428 trap->id.cookie = cookie; 1429 trap->id.tc_offload = false; 1430 trap->block_id = VCAP_IS2; 1431 trap->type = OCELOT_VCAP_FILTER_OFFLOAD; 1432 trap->lookup = 0; 1433 trap->action.cpu_copy_ena = true; 1434 trap->action.mask_mode = OCELOT_MASK_MODE_PERMIT_DENY; 1435 trap->action.port_mask = 0; 1436 new = true; 1437 } 1438 1439 trap->ingress_port_mask |= BIT(port); 1440 1441 if (new) 1442 err = ocelot_vcap_filter_add(ocelot, trap, NULL); 1443 else 1444 err = ocelot_vcap_filter_replace(ocelot, trap); 1445 if (err) { 1446 trap->ingress_port_mask &= ~BIT(port); 1447 if (!trap->ingress_port_mask) 1448 kfree(trap); 1449 return err; 1450 } 1451 1452 return 0; 1453 } 1454 1455 static int ocelot_trap_del(struct ocelot *ocelot, int port, 1456 unsigned long cookie) 1457 { 1458 struct ocelot_vcap_block *block_vcap_is2; 1459 struct ocelot_vcap_filter *trap; 1460 1461 block_vcap_is2 = &ocelot->block[VCAP_IS2]; 1462 1463 trap = ocelot_vcap_block_find_filter_by_id(block_vcap_is2, cookie, 1464 false); 1465 if (!trap) 1466 return 0; 1467 1468 trap->ingress_port_mask &= ~BIT(port); 1469 if (!trap->ingress_port_mask) 1470 return ocelot_vcap_filter_del(ocelot, trap); 1471 1472 return ocelot_vcap_filter_replace(ocelot, trap); 1473 } 1474 1475 static int ocelot_l2_ptp_trap_add(struct ocelot *ocelot, int port) 1476 { 1477 unsigned long l2_cookie = ocelot->num_phys_ports + 1; 1478 1479 return ocelot_trap_add(ocelot, port, l2_cookie, 1480 ocelot_populate_l2_ptp_trap_key); 1481 } 1482 1483 static int ocelot_l2_ptp_trap_del(struct ocelot *ocelot, int port) 1484 { 1485 unsigned long l2_cookie = ocelot->num_phys_ports + 1; 1486 1487 return ocelot_trap_del(ocelot, port, l2_cookie); 1488 } 1489 1490 static int ocelot_ipv4_ptp_trap_add(struct ocelot *ocelot, int port) 1491 { 1492 unsigned long ipv4_gen_cookie = ocelot->num_phys_ports + 2; 1493 unsigned long ipv4_ev_cookie = ocelot->num_phys_ports + 3; 1494 int err; 1495 1496 err = ocelot_trap_add(ocelot, port, ipv4_ev_cookie, 1497 ocelot_populate_ipv4_ptp_event_trap_key); 1498 if (err) 1499 return err; 1500 1501 err = ocelot_trap_add(ocelot, port, ipv4_gen_cookie, 1502 ocelot_populate_ipv4_ptp_general_trap_key); 1503 if (err) 1504 ocelot_trap_del(ocelot, port, ipv4_ev_cookie); 1505 1506 return err; 1507 } 1508 1509 static int ocelot_ipv4_ptp_trap_del(struct ocelot *ocelot, int port) 1510 { 1511 unsigned long ipv4_gen_cookie = ocelot->num_phys_ports + 2; 1512 unsigned long ipv4_ev_cookie = ocelot->num_phys_ports + 3; 1513 int err; 1514 1515 err = ocelot_trap_del(ocelot, port, ipv4_ev_cookie); 1516 err |= ocelot_trap_del(ocelot, port, ipv4_gen_cookie); 1517 return err; 1518 } 1519 1520 static int ocelot_ipv6_ptp_trap_add(struct ocelot *ocelot, int port) 1521 { 1522 unsigned long ipv6_gen_cookie = ocelot->num_phys_ports + 4; 1523 unsigned long ipv6_ev_cookie = ocelot->num_phys_ports + 5; 1524 int err; 1525 1526 err = ocelot_trap_add(ocelot, port, ipv6_ev_cookie, 1527 ocelot_populate_ipv6_ptp_event_trap_key); 1528 if (err) 1529 return err; 1530 1531 err = ocelot_trap_add(ocelot, port, ipv6_gen_cookie, 1532 ocelot_populate_ipv6_ptp_general_trap_key); 1533 if (err) 1534 ocelot_trap_del(ocelot, port, ipv6_ev_cookie); 1535 1536 return err; 1537 } 1538 1539 static int ocelot_ipv6_ptp_trap_del(struct ocelot *ocelot, int port) 1540 { 1541 unsigned long ipv6_gen_cookie = ocelot->num_phys_ports + 4; 1542 unsigned long ipv6_ev_cookie = ocelot->num_phys_ports + 5; 1543 int err; 1544 1545 err = ocelot_trap_del(ocelot, port, ipv6_ev_cookie); 1546 err |= ocelot_trap_del(ocelot, port, ipv6_gen_cookie); 1547 return err; 1548 } 1549 1550 static int ocelot_setup_ptp_traps(struct ocelot *ocelot, int port, 1551 bool l2, bool l4) 1552 { 1553 int err; 1554 1555 if (l2) 1556 err = ocelot_l2_ptp_trap_add(ocelot, port); 1557 else 1558 err = ocelot_l2_ptp_trap_del(ocelot, port); 1559 if (err) 1560 return err; 1561 1562 if (l4) { 1563 err = ocelot_ipv4_ptp_trap_add(ocelot, port); 1564 if (err) 1565 goto err_ipv4; 1566 1567 err = ocelot_ipv6_ptp_trap_add(ocelot, port); 1568 if (err) 1569 goto err_ipv6; 1570 } else { 1571 err = ocelot_ipv4_ptp_trap_del(ocelot, port); 1572 1573 err |= ocelot_ipv6_ptp_trap_del(ocelot, port); 1574 } 1575 if (err) 1576 return err; 1577 1578 return 0; 1579 1580 err_ipv6: 1581 ocelot_ipv4_ptp_trap_del(ocelot, port); 1582 err_ipv4: 1583 if (l2) 1584 ocelot_l2_ptp_trap_del(ocelot, port); 1585 return err; 1586 } 1587 1588 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr) 1589 { 1590 return copy_to_user(ifr->ifr_data, &ocelot->hwtstamp_config, 1591 sizeof(ocelot->hwtstamp_config)) ? -EFAULT : 0; 1592 } 1593 EXPORT_SYMBOL(ocelot_hwstamp_get); 1594 1595 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr) 1596 { 1597 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1598 bool l2 = false, l4 = false; 1599 struct hwtstamp_config cfg; 1600 int err; 1601 1602 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1603 return -EFAULT; 1604 1605 /* reserved for future extensions */ 1606 if (cfg.flags) 1607 return -EINVAL; 1608 1609 /* Tx type sanity check */ 1610 switch (cfg.tx_type) { 1611 case HWTSTAMP_TX_ON: 1612 ocelot_port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP; 1613 break; 1614 case HWTSTAMP_TX_ONESTEP_SYNC: 1615 /* IFH_REW_OP_ONE_STEP_PTP updates the correctional field, we 1616 * need to update the origin time. 1617 */ 1618 ocelot_port->ptp_cmd = IFH_REW_OP_ORIGIN_PTP; 1619 break; 1620 case HWTSTAMP_TX_OFF: 1621 ocelot_port->ptp_cmd = 0; 1622 break; 1623 default: 1624 return -ERANGE; 1625 } 1626 1627 mutex_lock(&ocelot->ptp_lock); 1628 1629 switch (cfg.rx_filter) { 1630 case HWTSTAMP_FILTER_NONE: 1631 break; 1632 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1633 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1634 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1635 l4 = true; 1636 break; 1637 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1638 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1639 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1640 l2 = true; 1641 break; 1642 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1643 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1644 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1645 l2 = true; 1646 l4 = true; 1647 break; 1648 default: 1649 mutex_unlock(&ocelot->ptp_lock); 1650 return -ERANGE; 1651 } 1652 1653 err = ocelot_setup_ptp_traps(ocelot, port, l2, l4); 1654 if (err) { 1655 mutex_unlock(&ocelot->ptp_lock); 1656 return err; 1657 } 1658 1659 if (l2 && l4) 1660 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 1661 else if (l2) 1662 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 1663 else if (l4) 1664 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 1665 else 1666 cfg.rx_filter = HWTSTAMP_FILTER_NONE; 1667 1668 /* Commit back the result & save it */ 1669 memcpy(&ocelot->hwtstamp_config, &cfg, sizeof(cfg)); 1670 mutex_unlock(&ocelot->ptp_lock); 1671 1672 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1673 } 1674 EXPORT_SYMBOL(ocelot_hwstamp_set); 1675 1676 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data) 1677 { 1678 int i; 1679 1680 if (sset != ETH_SS_STATS) 1681 return; 1682 1683 for (i = 0; i < ocelot->num_stats; i++) 1684 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name, 1685 ETH_GSTRING_LEN); 1686 } 1687 EXPORT_SYMBOL(ocelot_get_strings); 1688 1689 static void ocelot_update_stats(struct ocelot *ocelot) 1690 { 1691 int i, j; 1692 1693 mutex_lock(&ocelot->stats_lock); 1694 1695 for (i = 0; i < ocelot->num_phys_ports; i++) { 1696 /* Configure the port to read the stats from */ 1697 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(i), SYS_STAT_CFG); 1698 1699 for (j = 0; j < ocelot->num_stats; j++) { 1700 u32 val; 1701 unsigned int idx = i * ocelot->num_stats + j; 1702 1703 val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS, 1704 ocelot->stats_layout[j].offset); 1705 1706 if (val < (ocelot->stats[idx] & U32_MAX)) 1707 ocelot->stats[idx] += (u64)1 << 32; 1708 1709 ocelot->stats[idx] = (ocelot->stats[idx] & 1710 ~(u64)U32_MAX) + val; 1711 } 1712 } 1713 1714 mutex_unlock(&ocelot->stats_lock); 1715 } 1716 1717 static void ocelot_check_stats_work(struct work_struct *work) 1718 { 1719 struct delayed_work *del_work = to_delayed_work(work); 1720 struct ocelot *ocelot = container_of(del_work, struct ocelot, 1721 stats_work); 1722 1723 ocelot_update_stats(ocelot); 1724 1725 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 1726 OCELOT_STATS_CHECK_DELAY); 1727 } 1728 1729 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data) 1730 { 1731 int i; 1732 1733 /* check and update now */ 1734 ocelot_update_stats(ocelot); 1735 1736 /* Copy all counters */ 1737 for (i = 0; i < ocelot->num_stats; i++) 1738 *data++ = ocelot->stats[port * ocelot->num_stats + i]; 1739 } 1740 EXPORT_SYMBOL(ocelot_get_ethtool_stats); 1741 1742 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset) 1743 { 1744 if (sset != ETH_SS_STATS) 1745 return -EOPNOTSUPP; 1746 1747 return ocelot->num_stats; 1748 } 1749 EXPORT_SYMBOL(ocelot_get_sset_count); 1750 1751 int ocelot_get_ts_info(struct ocelot *ocelot, int port, 1752 struct ethtool_ts_info *info) 1753 { 1754 info->phc_index = ocelot->ptp_clock ? 1755 ptp_clock_index(ocelot->ptp_clock) : -1; 1756 if (info->phc_index == -1) { 1757 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 1758 SOF_TIMESTAMPING_RX_SOFTWARE | 1759 SOF_TIMESTAMPING_SOFTWARE; 1760 return 0; 1761 } 1762 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 1763 SOF_TIMESTAMPING_RX_SOFTWARE | 1764 SOF_TIMESTAMPING_SOFTWARE | 1765 SOF_TIMESTAMPING_TX_HARDWARE | 1766 SOF_TIMESTAMPING_RX_HARDWARE | 1767 SOF_TIMESTAMPING_RAW_HARDWARE; 1768 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON) | 1769 BIT(HWTSTAMP_TX_ONESTEP_SYNC); 1770 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | 1771 BIT(HWTSTAMP_FILTER_PTP_V2_EVENT) | 1772 BIT(HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1773 BIT(HWTSTAMP_FILTER_PTP_V2_L4_EVENT); 1774 1775 return 0; 1776 } 1777 EXPORT_SYMBOL(ocelot_get_ts_info); 1778 1779 static u32 ocelot_get_bond_mask(struct ocelot *ocelot, struct net_device *bond, 1780 bool only_active_ports) 1781 { 1782 u32 mask = 0; 1783 int port; 1784 1785 for (port = 0; port < ocelot->num_phys_ports; port++) { 1786 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1787 1788 if (!ocelot_port) 1789 continue; 1790 1791 if (ocelot_port->bond == bond) { 1792 if (only_active_ports && !ocelot_port->lag_tx_active) 1793 continue; 1794 1795 mask |= BIT(port); 1796 } 1797 } 1798 1799 return mask; 1800 } 1801 1802 u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot, int src_port) 1803 { 1804 struct ocelot_port *ocelot_port = ocelot->ports[src_port]; 1805 const struct net_device *bridge; 1806 u32 mask = 0; 1807 int port; 1808 1809 if (!ocelot_port || ocelot_port->stp_state != BR_STATE_FORWARDING) 1810 return 0; 1811 1812 bridge = ocelot_port->bridge; 1813 if (!bridge) 1814 return 0; 1815 1816 for (port = 0; port < ocelot->num_phys_ports; port++) { 1817 ocelot_port = ocelot->ports[port]; 1818 1819 if (!ocelot_port) 1820 continue; 1821 1822 if (ocelot_port->stp_state == BR_STATE_FORWARDING && 1823 ocelot_port->bridge == bridge) 1824 mask |= BIT(port); 1825 } 1826 1827 return mask; 1828 } 1829 EXPORT_SYMBOL_GPL(ocelot_get_bridge_fwd_mask); 1830 1831 u32 ocelot_get_dsa_8021q_cpu_mask(struct ocelot *ocelot) 1832 { 1833 u32 mask = 0; 1834 int port; 1835 1836 for (port = 0; port < ocelot->num_phys_ports; port++) { 1837 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1838 1839 if (!ocelot_port) 1840 continue; 1841 1842 if (ocelot_port->is_dsa_8021q_cpu) 1843 mask |= BIT(port); 1844 } 1845 1846 return mask; 1847 } 1848 EXPORT_SYMBOL_GPL(ocelot_get_dsa_8021q_cpu_mask); 1849 1850 void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot, bool joining) 1851 { 1852 unsigned long cpu_fwd_mask; 1853 int port; 1854 1855 lockdep_assert_held(&ocelot->fwd_domain_lock); 1856 1857 /* If cut-through forwarding is supported, update the masks before a 1858 * port joins the forwarding domain, to avoid potential underruns if it 1859 * has the highest speed from the new domain. 1860 */ 1861 if (joining && ocelot->ops->cut_through_fwd) 1862 ocelot->ops->cut_through_fwd(ocelot); 1863 1864 /* If a DSA tag_8021q CPU exists, it needs to be included in the 1865 * regular forwarding path of the front ports regardless of whether 1866 * those are bridged or standalone. 1867 * If DSA tag_8021q is not used, this returns 0, which is fine because 1868 * the hardware-based CPU port module can be a destination for packets 1869 * even if it isn't part of PGID_SRC. 1870 */ 1871 cpu_fwd_mask = ocelot_get_dsa_8021q_cpu_mask(ocelot); 1872 1873 /* Apply FWD mask. The loop is needed to add/remove the current port as 1874 * a source for the other ports. 1875 */ 1876 for (port = 0; port < ocelot->num_phys_ports; port++) { 1877 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1878 unsigned long mask; 1879 1880 if (!ocelot_port) { 1881 /* Unused ports can't send anywhere */ 1882 mask = 0; 1883 } else if (ocelot_port->is_dsa_8021q_cpu) { 1884 /* The DSA tag_8021q CPU ports need to be able to 1885 * forward packets to all other ports except for 1886 * themselves 1887 */ 1888 mask = GENMASK(ocelot->num_phys_ports - 1, 0); 1889 mask &= ~cpu_fwd_mask; 1890 } else if (ocelot_port->bridge) { 1891 struct net_device *bond = ocelot_port->bond; 1892 1893 mask = ocelot_get_bridge_fwd_mask(ocelot, port); 1894 mask |= cpu_fwd_mask; 1895 mask &= ~BIT(port); 1896 if (bond) { 1897 mask &= ~ocelot_get_bond_mask(ocelot, bond, 1898 false); 1899 } 1900 } else { 1901 /* Standalone ports forward only to DSA tag_8021q CPU 1902 * ports (if those exist), or to the hardware CPU port 1903 * module otherwise. 1904 */ 1905 mask = cpu_fwd_mask; 1906 } 1907 1908 ocelot_write_rix(ocelot, mask, ANA_PGID_PGID, PGID_SRC + port); 1909 } 1910 1911 /* If cut-through forwarding is supported and a port is leaving, there 1912 * is a chance that cut-through was disabled on the other ports due to 1913 * the port which is leaving (it has a higher link speed). We need to 1914 * update the cut-through masks of the remaining ports no earlier than 1915 * after the port has left, to prevent underruns from happening between 1916 * the cut-through update and the forwarding domain update. 1917 */ 1918 if (!joining && ocelot->ops->cut_through_fwd) 1919 ocelot->ops->cut_through_fwd(ocelot); 1920 } 1921 EXPORT_SYMBOL(ocelot_apply_bridge_fwd_mask); 1922 1923 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state) 1924 { 1925 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1926 u32 learn_ena = 0; 1927 1928 mutex_lock(&ocelot->fwd_domain_lock); 1929 1930 ocelot_port->stp_state = state; 1931 1932 if ((state == BR_STATE_LEARNING || state == BR_STATE_FORWARDING) && 1933 ocelot_port->learn_ena) 1934 learn_ena = ANA_PORT_PORT_CFG_LEARN_ENA; 1935 1936 ocelot_rmw_gix(ocelot, learn_ena, ANA_PORT_PORT_CFG_LEARN_ENA, 1937 ANA_PORT_PORT_CFG, port); 1938 1939 ocelot_apply_bridge_fwd_mask(ocelot, state == BR_STATE_FORWARDING); 1940 1941 mutex_unlock(&ocelot->fwd_domain_lock); 1942 } 1943 EXPORT_SYMBOL(ocelot_bridge_stp_state_set); 1944 1945 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs) 1946 { 1947 unsigned int age_period = ANA_AUTOAGE_AGE_PERIOD(msecs / 2000); 1948 1949 /* Setting AGE_PERIOD to zero effectively disables automatic aging, 1950 * which is clearly not what our intention is. So avoid that. 1951 */ 1952 if (!age_period) 1953 age_period = 1; 1954 1955 ocelot_rmw(ocelot, age_period, ANA_AUTOAGE_AGE_PERIOD_M, ANA_AUTOAGE); 1956 } 1957 EXPORT_SYMBOL(ocelot_set_ageing_time); 1958 1959 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot, 1960 const unsigned char *addr, 1961 u16 vid) 1962 { 1963 struct ocelot_multicast *mc; 1964 1965 list_for_each_entry(mc, &ocelot->multicast, list) { 1966 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid) 1967 return mc; 1968 } 1969 1970 return NULL; 1971 } 1972 1973 static enum macaccess_entry_type ocelot_classify_mdb(const unsigned char *addr) 1974 { 1975 if (addr[0] == 0x01 && addr[1] == 0x00 && addr[2] == 0x5e) 1976 return ENTRYTYPE_MACv4; 1977 if (addr[0] == 0x33 && addr[1] == 0x33) 1978 return ENTRYTYPE_MACv6; 1979 return ENTRYTYPE_LOCKED; 1980 } 1981 1982 static struct ocelot_pgid *ocelot_pgid_alloc(struct ocelot *ocelot, int index, 1983 unsigned long ports) 1984 { 1985 struct ocelot_pgid *pgid; 1986 1987 pgid = kzalloc(sizeof(*pgid), GFP_KERNEL); 1988 if (!pgid) 1989 return ERR_PTR(-ENOMEM); 1990 1991 pgid->ports = ports; 1992 pgid->index = index; 1993 refcount_set(&pgid->refcount, 1); 1994 list_add_tail(&pgid->list, &ocelot->pgids); 1995 1996 return pgid; 1997 } 1998 1999 static void ocelot_pgid_free(struct ocelot *ocelot, struct ocelot_pgid *pgid) 2000 { 2001 if (!refcount_dec_and_test(&pgid->refcount)) 2002 return; 2003 2004 list_del(&pgid->list); 2005 kfree(pgid); 2006 } 2007 2008 static struct ocelot_pgid *ocelot_mdb_get_pgid(struct ocelot *ocelot, 2009 const struct ocelot_multicast *mc) 2010 { 2011 struct ocelot_pgid *pgid; 2012 int index; 2013 2014 /* According to VSC7514 datasheet 3.9.1.5 IPv4 Multicast Entries and 2015 * 3.9.1.6 IPv6 Multicast Entries, "Instead of a lookup in the 2016 * destination mask table (PGID), the destination set is programmed as 2017 * part of the entry MAC address.", and the DEST_IDX is set to 0. 2018 */ 2019 if (mc->entry_type == ENTRYTYPE_MACv4 || 2020 mc->entry_type == ENTRYTYPE_MACv6) 2021 return ocelot_pgid_alloc(ocelot, 0, mc->ports); 2022 2023 list_for_each_entry(pgid, &ocelot->pgids, list) { 2024 /* When searching for a nonreserved multicast PGID, ignore the 2025 * dummy PGID of zero that we have for MACv4/MACv6 entries 2026 */ 2027 if (pgid->index && pgid->ports == mc->ports) { 2028 refcount_inc(&pgid->refcount); 2029 return pgid; 2030 } 2031 } 2032 2033 /* Search for a free index in the nonreserved multicast PGID area */ 2034 for_each_nonreserved_multicast_dest_pgid(ocelot, index) { 2035 bool used = false; 2036 2037 list_for_each_entry(pgid, &ocelot->pgids, list) { 2038 if (pgid->index == index) { 2039 used = true; 2040 break; 2041 } 2042 } 2043 2044 if (!used) 2045 return ocelot_pgid_alloc(ocelot, index, mc->ports); 2046 } 2047 2048 return ERR_PTR(-ENOSPC); 2049 } 2050 2051 static void ocelot_encode_ports_to_mdb(unsigned char *addr, 2052 struct ocelot_multicast *mc) 2053 { 2054 ether_addr_copy(addr, mc->addr); 2055 2056 if (mc->entry_type == ENTRYTYPE_MACv4) { 2057 addr[0] = 0; 2058 addr[1] = mc->ports >> 8; 2059 addr[2] = mc->ports & 0xff; 2060 } else if (mc->entry_type == ENTRYTYPE_MACv6) { 2061 addr[0] = mc->ports >> 8; 2062 addr[1] = mc->ports & 0xff; 2063 } 2064 } 2065 2066 int ocelot_port_mdb_add(struct ocelot *ocelot, int port, 2067 const struct switchdev_obj_port_mdb *mdb) 2068 { 2069 unsigned char addr[ETH_ALEN]; 2070 struct ocelot_multicast *mc; 2071 struct ocelot_pgid *pgid; 2072 u16 vid = mdb->vid; 2073 2074 if (port == ocelot->npi) 2075 port = ocelot->num_phys_ports; 2076 2077 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 2078 if (!mc) { 2079 /* New entry */ 2080 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL); 2081 if (!mc) 2082 return -ENOMEM; 2083 2084 mc->entry_type = ocelot_classify_mdb(mdb->addr); 2085 ether_addr_copy(mc->addr, mdb->addr); 2086 mc->vid = vid; 2087 2088 list_add_tail(&mc->list, &ocelot->multicast); 2089 } else { 2090 /* Existing entry. Clean up the current port mask from 2091 * hardware now, because we'll be modifying it. 2092 */ 2093 ocelot_pgid_free(ocelot, mc->pgid); 2094 ocelot_encode_ports_to_mdb(addr, mc); 2095 ocelot_mact_forget(ocelot, addr, vid); 2096 } 2097 2098 mc->ports |= BIT(port); 2099 2100 pgid = ocelot_mdb_get_pgid(ocelot, mc); 2101 if (IS_ERR(pgid)) { 2102 dev_err(ocelot->dev, 2103 "Cannot allocate PGID for mdb %pM vid %d\n", 2104 mc->addr, mc->vid); 2105 devm_kfree(ocelot->dev, mc); 2106 return PTR_ERR(pgid); 2107 } 2108 mc->pgid = pgid; 2109 2110 ocelot_encode_ports_to_mdb(addr, mc); 2111 2112 if (mc->entry_type != ENTRYTYPE_MACv4 && 2113 mc->entry_type != ENTRYTYPE_MACv6) 2114 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 2115 pgid->index); 2116 2117 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 2118 mc->entry_type); 2119 } 2120 EXPORT_SYMBOL(ocelot_port_mdb_add); 2121 2122 int ocelot_port_mdb_del(struct ocelot *ocelot, int port, 2123 const struct switchdev_obj_port_mdb *mdb) 2124 { 2125 unsigned char addr[ETH_ALEN]; 2126 struct ocelot_multicast *mc; 2127 struct ocelot_pgid *pgid; 2128 u16 vid = mdb->vid; 2129 2130 if (port == ocelot->npi) 2131 port = ocelot->num_phys_ports; 2132 2133 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 2134 if (!mc) 2135 return -ENOENT; 2136 2137 ocelot_encode_ports_to_mdb(addr, mc); 2138 ocelot_mact_forget(ocelot, addr, vid); 2139 2140 ocelot_pgid_free(ocelot, mc->pgid); 2141 mc->ports &= ~BIT(port); 2142 if (!mc->ports) { 2143 list_del(&mc->list); 2144 devm_kfree(ocelot->dev, mc); 2145 return 0; 2146 } 2147 2148 /* We have a PGID with fewer ports now */ 2149 pgid = ocelot_mdb_get_pgid(ocelot, mc); 2150 if (IS_ERR(pgid)) 2151 return PTR_ERR(pgid); 2152 mc->pgid = pgid; 2153 2154 ocelot_encode_ports_to_mdb(addr, mc); 2155 2156 if (mc->entry_type != ENTRYTYPE_MACv4 && 2157 mc->entry_type != ENTRYTYPE_MACv6) 2158 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 2159 pgid->index); 2160 2161 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 2162 mc->entry_type); 2163 } 2164 EXPORT_SYMBOL(ocelot_port_mdb_del); 2165 2166 void ocelot_port_bridge_join(struct ocelot *ocelot, int port, 2167 struct net_device *bridge) 2168 { 2169 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2170 2171 mutex_lock(&ocelot->fwd_domain_lock); 2172 2173 ocelot_port->bridge = bridge; 2174 2175 ocelot_apply_bridge_fwd_mask(ocelot, true); 2176 2177 mutex_unlock(&ocelot->fwd_domain_lock); 2178 } 2179 EXPORT_SYMBOL(ocelot_port_bridge_join); 2180 2181 void ocelot_port_bridge_leave(struct ocelot *ocelot, int port, 2182 struct net_device *bridge) 2183 { 2184 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2185 2186 mutex_lock(&ocelot->fwd_domain_lock); 2187 2188 ocelot_port->bridge = NULL; 2189 2190 ocelot_port_set_pvid(ocelot, port, NULL); 2191 ocelot_port_manage_port_tag(ocelot, port); 2192 ocelot_apply_bridge_fwd_mask(ocelot, false); 2193 2194 mutex_unlock(&ocelot->fwd_domain_lock); 2195 } 2196 EXPORT_SYMBOL(ocelot_port_bridge_leave); 2197 2198 static void ocelot_set_aggr_pgids(struct ocelot *ocelot) 2199 { 2200 unsigned long visited = GENMASK(ocelot->num_phys_ports - 1, 0); 2201 int i, port, lag; 2202 2203 /* Reset destination and aggregation PGIDS */ 2204 for_each_unicast_dest_pgid(ocelot, port) 2205 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 2206 2207 for_each_aggr_pgid(ocelot, i) 2208 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 2209 ANA_PGID_PGID, i); 2210 2211 /* The visited ports bitmask holds the list of ports offloading any 2212 * bonding interface. Initially we mark all these ports as unvisited, 2213 * then every time we visit a port in this bitmask, we know that it is 2214 * the lowest numbered port, i.e. the one whose logical ID == physical 2215 * port ID == LAG ID. So we mark as visited all further ports in the 2216 * bitmask that are offloading the same bonding interface. This way, 2217 * we set up the aggregation PGIDs only once per bonding interface. 2218 */ 2219 for (port = 0; port < ocelot->num_phys_ports; port++) { 2220 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2221 2222 if (!ocelot_port || !ocelot_port->bond) 2223 continue; 2224 2225 visited &= ~BIT(port); 2226 } 2227 2228 /* Now, set PGIDs for each active LAG */ 2229 for (lag = 0; lag < ocelot->num_phys_ports; lag++) { 2230 struct net_device *bond = ocelot->ports[lag]->bond; 2231 int num_active_ports = 0; 2232 unsigned long bond_mask; 2233 u8 aggr_idx[16]; 2234 2235 if (!bond || (visited & BIT(lag))) 2236 continue; 2237 2238 bond_mask = ocelot_get_bond_mask(ocelot, bond, true); 2239 2240 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) { 2241 // Destination mask 2242 ocelot_write_rix(ocelot, bond_mask, 2243 ANA_PGID_PGID, port); 2244 aggr_idx[num_active_ports++] = port; 2245 } 2246 2247 for_each_aggr_pgid(ocelot, i) { 2248 u32 ac; 2249 2250 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i); 2251 ac &= ~bond_mask; 2252 /* Don't do division by zero if there was no active 2253 * port. Just make all aggregation codes zero. 2254 */ 2255 if (num_active_ports) 2256 ac |= BIT(aggr_idx[i % num_active_ports]); 2257 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i); 2258 } 2259 2260 /* Mark all ports in the same LAG as visited to avoid applying 2261 * the same config again. 2262 */ 2263 for (port = lag; port < ocelot->num_phys_ports; port++) { 2264 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2265 2266 if (!ocelot_port) 2267 continue; 2268 2269 if (ocelot_port->bond == bond) 2270 visited |= BIT(port); 2271 } 2272 } 2273 } 2274 2275 /* When offloading a bonding interface, the switch ports configured under the 2276 * same bond must have the same logical port ID, equal to the physical port ID 2277 * of the lowest numbered physical port in that bond. Otherwise, in standalone/ 2278 * bridged mode, each port has a logical port ID equal to its physical port ID. 2279 */ 2280 static void ocelot_setup_logical_port_ids(struct ocelot *ocelot) 2281 { 2282 int port; 2283 2284 for (port = 0; port < ocelot->num_phys_ports; port++) { 2285 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2286 struct net_device *bond; 2287 2288 if (!ocelot_port) 2289 continue; 2290 2291 bond = ocelot_port->bond; 2292 if (bond) { 2293 int lag = __ffs(ocelot_get_bond_mask(ocelot, bond, 2294 false)); 2295 2296 ocelot_rmw_gix(ocelot, 2297 ANA_PORT_PORT_CFG_PORTID_VAL(lag), 2298 ANA_PORT_PORT_CFG_PORTID_VAL_M, 2299 ANA_PORT_PORT_CFG, port); 2300 } else { 2301 ocelot_rmw_gix(ocelot, 2302 ANA_PORT_PORT_CFG_PORTID_VAL(port), 2303 ANA_PORT_PORT_CFG_PORTID_VAL_M, 2304 ANA_PORT_PORT_CFG, port); 2305 } 2306 } 2307 } 2308 2309 int ocelot_port_lag_join(struct ocelot *ocelot, int port, 2310 struct net_device *bond, 2311 struct netdev_lag_upper_info *info) 2312 { 2313 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) 2314 return -EOPNOTSUPP; 2315 2316 mutex_lock(&ocelot->fwd_domain_lock); 2317 2318 ocelot->ports[port]->bond = bond; 2319 2320 ocelot_setup_logical_port_ids(ocelot); 2321 ocelot_apply_bridge_fwd_mask(ocelot, true); 2322 ocelot_set_aggr_pgids(ocelot); 2323 2324 mutex_unlock(&ocelot->fwd_domain_lock); 2325 2326 return 0; 2327 } 2328 EXPORT_SYMBOL(ocelot_port_lag_join); 2329 2330 void ocelot_port_lag_leave(struct ocelot *ocelot, int port, 2331 struct net_device *bond) 2332 { 2333 mutex_lock(&ocelot->fwd_domain_lock); 2334 2335 ocelot->ports[port]->bond = NULL; 2336 2337 ocelot_setup_logical_port_ids(ocelot); 2338 ocelot_apply_bridge_fwd_mask(ocelot, false); 2339 ocelot_set_aggr_pgids(ocelot); 2340 2341 mutex_unlock(&ocelot->fwd_domain_lock); 2342 } 2343 EXPORT_SYMBOL(ocelot_port_lag_leave); 2344 2345 void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active) 2346 { 2347 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2348 2349 ocelot_port->lag_tx_active = lag_tx_active; 2350 2351 /* Rebalance the LAGs */ 2352 ocelot_set_aggr_pgids(ocelot); 2353 } 2354 EXPORT_SYMBOL(ocelot_port_lag_change); 2355 2356 /* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu. 2357 * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG. 2358 * In the special case that it's the NPI port that we're configuring, the 2359 * length of the tag and optional prefix needs to be accounted for privately, 2360 * in order to be able to sustain communication at the requested @sdu. 2361 */ 2362 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu) 2363 { 2364 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2365 int maxlen = sdu + ETH_HLEN + ETH_FCS_LEN; 2366 int pause_start, pause_stop; 2367 int atop, atop_tot; 2368 2369 if (port == ocelot->npi) { 2370 maxlen += OCELOT_TAG_LEN; 2371 2372 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT) 2373 maxlen += OCELOT_SHORT_PREFIX_LEN; 2374 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG) 2375 maxlen += OCELOT_LONG_PREFIX_LEN; 2376 } 2377 2378 ocelot_port_writel(ocelot_port, maxlen, DEV_MAC_MAXLEN_CFG); 2379 2380 /* Set Pause watermark hysteresis */ 2381 pause_start = 6 * maxlen / OCELOT_BUFFER_CELL_SZ; 2382 pause_stop = 4 * maxlen / OCELOT_BUFFER_CELL_SZ; 2383 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_START, 2384 pause_start); 2385 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_STOP, 2386 pause_stop); 2387 2388 /* Tail dropping watermarks */ 2389 atop_tot = (ocelot->packet_buffer_size - 9 * maxlen) / 2390 OCELOT_BUFFER_CELL_SZ; 2391 atop = (9 * maxlen) / OCELOT_BUFFER_CELL_SZ; 2392 ocelot_write_rix(ocelot, ocelot->ops->wm_enc(atop), SYS_ATOP, port); 2393 ocelot_write(ocelot, ocelot->ops->wm_enc(atop_tot), SYS_ATOP_TOT_CFG); 2394 } 2395 EXPORT_SYMBOL(ocelot_port_set_maxlen); 2396 2397 int ocelot_get_max_mtu(struct ocelot *ocelot, int port) 2398 { 2399 int max_mtu = 65535 - ETH_HLEN - ETH_FCS_LEN; 2400 2401 if (port == ocelot->npi) { 2402 max_mtu -= OCELOT_TAG_LEN; 2403 2404 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT) 2405 max_mtu -= OCELOT_SHORT_PREFIX_LEN; 2406 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG) 2407 max_mtu -= OCELOT_LONG_PREFIX_LEN; 2408 } 2409 2410 return max_mtu; 2411 } 2412 EXPORT_SYMBOL(ocelot_get_max_mtu); 2413 2414 static void ocelot_port_set_learning(struct ocelot *ocelot, int port, 2415 bool enabled) 2416 { 2417 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2418 u32 val = 0; 2419 2420 if (enabled) 2421 val = ANA_PORT_PORT_CFG_LEARN_ENA; 2422 2423 ocelot_rmw_gix(ocelot, val, ANA_PORT_PORT_CFG_LEARN_ENA, 2424 ANA_PORT_PORT_CFG, port); 2425 2426 ocelot_port->learn_ena = enabled; 2427 } 2428 2429 static void ocelot_port_set_ucast_flood(struct ocelot *ocelot, int port, 2430 bool enabled) 2431 { 2432 u32 val = 0; 2433 2434 if (enabled) 2435 val = BIT(port); 2436 2437 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_UC); 2438 } 2439 2440 static void ocelot_port_set_mcast_flood(struct ocelot *ocelot, int port, 2441 bool enabled) 2442 { 2443 u32 val = 0; 2444 2445 if (enabled) 2446 val = BIT(port); 2447 2448 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MC); 2449 } 2450 2451 static void ocelot_port_set_bcast_flood(struct ocelot *ocelot, int port, 2452 bool enabled) 2453 { 2454 u32 val = 0; 2455 2456 if (enabled) 2457 val = BIT(port); 2458 2459 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_BC); 2460 } 2461 2462 int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port, 2463 struct switchdev_brport_flags flags) 2464 { 2465 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 2466 BR_BCAST_FLOOD)) 2467 return -EINVAL; 2468 2469 return 0; 2470 } 2471 EXPORT_SYMBOL(ocelot_port_pre_bridge_flags); 2472 2473 void ocelot_port_bridge_flags(struct ocelot *ocelot, int port, 2474 struct switchdev_brport_flags flags) 2475 { 2476 if (flags.mask & BR_LEARNING) 2477 ocelot_port_set_learning(ocelot, port, 2478 !!(flags.val & BR_LEARNING)); 2479 2480 if (flags.mask & BR_FLOOD) 2481 ocelot_port_set_ucast_flood(ocelot, port, 2482 !!(flags.val & BR_FLOOD)); 2483 2484 if (flags.mask & BR_MCAST_FLOOD) 2485 ocelot_port_set_mcast_flood(ocelot, port, 2486 !!(flags.val & BR_MCAST_FLOOD)); 2487 2488 if (flags.mask & BR_BCAST_FLOOD) 2489 ocelot_port_set_bcast_flood(ocelot, port, 2490 !!(flags.val & BR_BCAST_FLOOD)); 2491 } 2492 EXPORT_SYMBOL(ocelot_port_bridge_flags); 2493 2494 void ocelot_init_port(struct ocelot *ocelot, int port) 2495 { 2496 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2497 2498 skb_queue_head_init(&ocelot_port->tx_skbs); 2499 2500 /* Basic L2 initialization */ 2501 2502 /* Set MAC IFG Gaps 2503 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0 2504 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5 2505 */ 2506 ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5), 2507 DEV_MAC_IFG_CFG); 2508 2509 /* Load seed (0) and set MAC HDX late collision */ 2510 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) | 2511 DEV_MAC_HDX_CFG_SEED_LOAD, 2512 DEV_MAC_HDX_CFG); 2513 mdelay(1); 2514 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67), 2515 DEV_MAC_HDX_CFG); 2516 2517 /* Set Max Length and maximum tags allowed */ 2518 ocelot_port_set_maxlen(ocelot, port, ETH_DATA_LEN); 2519 ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) | 2520 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA | 2521 DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA | 2522 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, 2523 DEV_MAC_TAGS_CFG); 2524 2525 /* Set SMAC of Pause frame (00:00:00:00:00:00) */ 2526 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG); 2527 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG); 2528 2529 /* Enable transmission of pause frames */ 2530 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1); 2531 2532 /* Drop frames with multicast source address */ 2533 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 2534 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 2535 ANA_PORT_DROP_CFG, port); 2536 2537 /* Set default VLAN and tag type to 8021Q. */ 2538 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q), 2539 REW_PORT_VLAN_CFG_PORT_TPID_M, 2540 REW_PORT_VLAN_CFG, port); 2541 2542 /* Disable source address learning for standalone mode */ 2543 ocelot_port_set_learning(ocelot, port, false); 2544 2545 /* Set the port's initial logical port ID value, enable receiving 2546 * frames on it, and configure the MAC address learning type to 2547 * automatic. 2548 */ 2549 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO | 2550 ANA_PORT_PORT_CFG_RECV_ENA | 2551 ANA_PORT_PORT_CFG_PORTID_VAL(port), 2552 ANA_PORT_PORT_CFG, port); 2553 2554 /* Enable vcap lookups */ 2555 ocelot_vcap_enable(ocelot, port); 2556 } 2557 EXPORT_SYMBOL(ocelot_init_port); 2558 2559 /* Configure and enable the CPU port module, which is a set of queues 2560 * accessible through register MMIO, frame DMA or Ethernet (in case 2561 * NPI mode is used). 2562 */ 2563 static void ocelot_cpu_port_init(struct ocelot *ocelot) 2564 { 2565 int cpu = ocelot->num_phys_ports; 2566 2567 /* The unicast destination PGID for the CPU port module is unused */ 2568 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu); 2569 /* Instead set up a multicast destination PGID for traffic copied to 2570 * the CPU. Whitelisted MAC addresses like the port netdevice MAC 2571 * addresses will be copied to the CPU via this PGID. 2572 */ 2573 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU); 2574 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA | 2575 ANA_PORT_PORT_CFG_PORTID_VAL(cpu), 2576 ANA_PORT_PORT_CFG, cpu); 2577 2578 /* Enable CPU port module */ 2579 ocelot_fields_write(ocelot, cpu, QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 2580 /* CPU port Injection/Extraction configuration */ 2581 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_XTR_HDR, 2582 OCELOT_TAG_PREFIX_NONE); 2583 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_INJ_HDR, 2584 OCELOT_TAG_PREFIX_NONE); 2585 2586 /* Configure the CPU port to be VLAN aware */ 2587 ocelot_write_gix(ocelot, 2588 ANA_PORT_VLAN_CFG_VLAN_VID(OCELOT_VLAN_UNAWARE_PVID) | 2589 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 2590 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1), 2591 ANA_PORT_VLAN_CFG, cpu); 2592 } 2593 2594 static void ocelot_detect_features(struct ocelot *ocelot) 2595 { 2596 int mmgt, eq_ctrl; 2597 2598 /* For Ocelot, Felix, Seville, Serval etc, SYS:MMGT:MMGT:FREECNT holds 2599 * the number of 240-byte free memory words (aka 4-cell chunks) and not 2600 * 192 bytes as the documentation incorrectly says. 2601 */ 2602 mmgt = ocelot_read(ocelot, SYS_MMGT); 2603 ocelot->packet_buffer_size = 240 * SYS_MMGT_FREECNT(mmgt); 2604 2605 eq_ctrl = ocelot_read(ocelot, QSYS_EQ_CTRL); 2606 ocelot->num_frame_refs = QSYS_MMGT_EQ_CTRL_FP_FREE_CNT(eq_ctrl); 2607 } 2608 2609 int ocelot_init(struct ocelot *ocelot) 2610 { 2611 char queue_name[32]; 2612 int i, ret; 2613 u32 port; 2614 2615 if (ocelot->ops->reset) { 2616 ret = ocelot->ops->reset(ocelot); 2617 if (ret) { 2618 dev_err(ocelot->dev, "Switch reset failed\n"); 2619 return ret; 2620 } 2621 } 2622 2623 ocelot->stats = devm_kcalloc(ocelot->dev, 2624 ocelot->num_phys_ports * ocelot->num_stats, 2625 sizeof(u64), GFP_KERNEL); 2626 if (!ocelot->stats) 2627 return -ENOMEM; 2628 2629 mutex_init(&ocelot->stats_lock); 2630 mutex_init(&ocelot->ptp_lock); 2631 mutex_init(&ocelot->mact_lock); 2632 mutex_init(&ocelot->fwd_domain_lock); 2633 spin_lock_init(&ocelot->ptp_clock_lock); 2634 spin_lock_init(&ocelot->ts_id_lock); 2635 snprintf(queue_name, sizeof(queue_name), "%s-stats", 2636 dev_name(ocelot->dev)); 2637 ocelot->stats_queue = create_singlethread_workqueue(queue_name); 2638 if (!ocelot->stats_queue) 2639 return -ENOMEM; 2640 2641 ocelot->owq = alloc_ordered_workqueue("ocelot-owq", 0); 2642 if (!ocelot->owq) { 2643 destroy_workqueue(ocelot->stats_queue); 2644 return -ENOMEM; 2645 } 2646 2647 INIT_LIST_HEAD(&ocelot->multicast); 2648 INIT_LIST_HEAD(&ocelot->pgids); 2649 INIT_LIST_HEAD(&ocelot->vlans); 2650 ocelot_detect_features(ocelot); 2651 ocelot_mact_init(ocelot); 2652 ocelot_vlan_init(ocelot); 2653 ocelot_vcap_init(ocelot); 2654 ocelot_cpu_port_init(ocelot); 2655 2656 if (ocelot->ops->psfp_init) 2657 ocelot->ops->psfp_init(ocelot); 2658 2659 for (port = 0; port < ocelot->num_phys_ports; port++) { 2660 /* Clear all counters (5 groups) */ 2661 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) | 2662 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f), 2663 SYS_STAT_CFG); 2664 } 2665 2666 /* Only use S-Tag */ 2667 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG); 2668 2669 /* Aggregation mode */ 2670 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA | 2671 ANA_AGGR_CFG_AC_DMAC_ENA | 2672 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA | 2673 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA | 2674 ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA | 2675 ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA, 2676 ANA_AGGR_CFG); 2677 2678 /* Set MAC age time to default value. The entry is aged after 2679 * 2*AGE_PERIOD 2680 */ 2681 ocelot_write(ocelot, 2682 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ), 2683 ANA_AUTOAGE); 2684 2685 /* Disable learning for frames discarded by VLAN ingress filtering */ 2686 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1); 2687 2688 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */ 2689 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA | 2690 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING); 2691 2692 /* Setup flooding PGIDs */ 2693 for (i = 0; i < ocelot->num_flooding_pgids; i++) 2694 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) | 2695 ANA_FLOODING_FLD_BROADCAST(PGID_BC) | 2696 ANA_FLOODING_FLD_UNICAST(PGID_UC), 2697 ANA_FLOODING, i); 2698 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) | 2699 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) | 2700 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) | 2701 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC), 2702 ANA_FLOODING_IPMC); 2703 2704 for (port = 0; port < ocelot->num_phys_ports; port++) { 2705 /* Transmit the frame to the local port. */ 2706 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 2707 /* Do not forward BPDU frames to the front ports. */ 2708 ocelot_write_gix(ocelot, 2709 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff), 2710 ANA_PORT_CPU_FWD_BPDU_CFG, 2711 port); 2712 /* Ensure bridging is disabled */ 2713 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port); 2714 } 2715 2716 for_each_nonreserved_multicast_dest_pgid(ocelot, i) { 2717 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0)); 2718 2719 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 2720 } 2721 2722 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_BLACKHOLE); 2723 2724 /* Allow broadcast and unknown L2 multicast to the CPU. */ 2725 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2726 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2727 ANA_PGID_PGID, PGID_MC); 2728 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2729 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2730 ANA_PGID_PGID, PGID_BC); 2731 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4); 2732 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6); 2733 2734 /* Allow manual injection via DEVCPU_QS registers, and byte swap these 2735 * registers endianness. 2736 */ 2737 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP | 2738 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0); 2739 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP | 2740 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0); 2741 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) | 2742 ANA_CPUQ_CFG_CPUQ_LRN(2) | 2743 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) | 2744 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) | 2745 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) | 2746 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) | 2747 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) | 2748 ANA_CPUQ_CFG_CPUQ_IGMP(6) | 2749 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG); 2750 for (i = 0; i < 16; i++) 2751 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) | 2752 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6), 2753 ANA_CPUQ_8021_CFG, i); 2754 2755 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats_work); 2756 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 2757 OCELOT_STATS_CHECK_DELAY); 2758 2759 return 0; 2760 } 2761 EXPORT_SYMBOL(ocelot_init); 2762 2763 void ocelot_deinit(struct ocelot *ocelot) 2764 { 2765 cancel_delayed_work(&ocelot->stats_work); 2766 destroy_workqueue(ocelot->stats_queue); 2767 destroy_workqueue(ocelot->owq); 2768 mutex_destroy(&ocelot->stats_lock); 2769 } 2770 EXPORT_SYMBOL(ocelot_deinit); 2771 2772 void ocelot_deinit_port(struct ocelot *ocelot, int port) 2773 { 2774 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2775 2776 skb_queue_purge(&ocelot_port->tx_skbs); 2777 } 2778 EXPORT_SYMBOL(ocelot_deinit_port); 2779 2780 MODULE_LICENSE("Dual MIT/GPL"); 2781