1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7 #include <linux/dsa/ocelot.h> 8 #include <linux/if_bridge.h> 9 #include <linux/ptp_classify.h> 10 #include <soc/mscc/ocelot_vcap.h> 11 #include "ocelot.h" 12 #include "ocelot_vcap.h" 13 14 #define TABLE_UPDATE_SLEEP_US 10 15 #define TABLE_UPDATE_TIMEOUT_US 100000 16 17 struct ocelot_mact_entry { 18 u8 mac[ETH_ALEN]; 19 u16 vid; 20 enum macaccess_entry_type type; 21 }; 22 23 /* Caller must hold &ocelot->mact_lock */ 24 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot) 25 { 26 return ocelot_read(ocelot, ANA_TABLES_MACACCESS); 27 } 28 29 /* Caller must hold &ocelot->mact_lock */ 30 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot) 31 { 32 u32 val; 33 34 return readx_poll_timeout(ocelot_mact_read_macaccess, 35 ocelot, val, 36 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) == 37 MACACCESS_CMD_IDLE, 38 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 39 } 40 41 /* Caller must hold &ocelot->mact_lock */ 42 static void ocelot_mact_select(struct ocelot *ocelot, 43 const unsigned char mac[ETH_ALEN], 44 unsigned int vid) 45 { 46 u32 macl = 0, mach = 0; 47 48 /* Set the MAC address to handle and the vlan associated in a format 49 * understood by the hardware. 50 */ 51 mach |= vid << 16; 52 mach |= mac[0] << 8; 53 mach |= mac[1] << 0; 54 macl |= mac[2] << 24; 55 macl |= mac[3] << 16; 56 macl |= mac[4] << 8; 57 macl |= mac[5] << 0; 58 59 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA); 60 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA); 61 62 } 63 64 static int __ocelot_mact_learn(struct ocelot *ocelot, int port, 65 const unsigned char mac[ETH_ALEN], 66 unsigned int vid, enum macaccess_entry_type type) 67 { 68 u32 cmd = ANA_TABLES_MACACCESS_VALID | 69 ANA_TABLES_MACACCESS_DEST_IDX(port) | 70 ANA_TABLES_MACACCESS_ENTRYTYPE(type) | 71 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN); 72 unsigned int mc_ports; 73 int err; 74 75 /* Set MAC_CPU_COPY if the CPU port is used by a multicast entry */ 76 if (type == ENTRYTYPE_MACv4) 77 mc_ports = (mac[1] << 8) | mac[2]; 78 else if (type == ENTRYTYPE_MACv6) 79 mc_ports = (mac[0] << 8) | mac[1]; 80 else 81 mc_ports = 0; 82 83 if (mc_ports & BIT(ocelot->num_phys_ports)) 84 cmd |= ANA_TABLES_MACACCESS_MAC_CPU_COPY; 85 86 ocelot_mact_select(ocelot, mac, vid); 87 88 /* Issue a write command */ 89 ocelot_write(ocelot, cmd, ANA_TABLES_MACACCESS); 90 91 err = ocelot_mact_wait_for_completion(ocelot); 92 93 return err; 94 } 95 96 int ocelot_mact_learn(struct ocelot *ocelot, int port, 97 const unsigned char mac[ETH_ALEN], 98 unsigned int vid, enum macaccess_entry_type type) 99 { 100 int ret; 101 102 mutex_lock(&ocelot->mact_lock); 103 ret = __ocelot_mact_learn(ocelot, port, mac, vid, type); 104 mutex_unlock(&ocelot->mact_lock); 105 106 return ret; 107 } 108 EXPORT_SYMBOL(ocelot_mact_learn); 109 110 int ocelot_mact_forget(struct ocelot *ocelot, 111 const unsigned char mac[ETH_ALEN], unsigned int vid) 112 { 113 int err; 114 115 mutex_lock(&ocelot->mact_lock); 116 117 ocelot_mact_select(ocelot, mac, vid); 118 119 /* Issue a forget command */ 120 ocelot_write(ocelot, 121 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET), 122 ANA_TABLES_MACACCESS); 123 124 err = ocelot_mact_wait_for_completion(ocelot); 125 126 mutex_unlock(&ocelot->mact_lock); 127 128 return err; 129 } 130 EXPORT_SYMBOL(ocelot_mact_forget); 131 132 int ocelot_mact_lookup(struct ocelot *ocelot, int *dst_idx, 133 const unsigned char mac[ETH_ALEN], 134 unsigned int vid, enum macaccess_entry_type *type) 135 { 136 int val; 137 138 mutex_lock(&ocelot->mact_lock); 139 140 ocelot_mact_select(ocelot, mac, vid); 141 142 /* Issue a read command with MACACCESS_VALID=1. */ 143 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID | 144 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 145 ANA_TABLES_MACACCESS); 146 147 if (ocelot_mact_wait_for_completion(ocelot)) { 148 mutex_unlock(&ocelot->mact_lock); 149 return -ETIMEDOUT; 150 } 151 152 /* Read back the entry flags */ 153 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 154 155 mutex_unlock(&ocelot->mact_lock); 156 157 if (!(val & ANA_TABLES_MACACCESS_VALID)) 158 return -ENOENT; 159 160 *dst_idx = ANA_TABLES_MACACCESS_DEST_IDX_X(val); 161 *type = ANA_TABLES_MACACCESS_ENTRYTYPE_X(val); 162 163 return 0; 164 } 165 EXPORT_SYMBOL(ocelot_mact_lookup); 166 167 int ocelot_mact_learn_streamdata(struct ocelot *ocelot, int dst_idx, 168 const unsigned char mac[ETH_ALEN], 169 unsigned int vid, 170 enum macaccess_entry_type type, 171 int sfid, int ssid) 172 { 173 int ret; 174 175 mutex_lock(&ocelot->mact_lock); 176 177 ocelot_write(ocelot, 178 (sfid < 0 ? 0 : ANA_TABLES_STREAMDATA_SFID_VALID) | 179 ANA_TABLES_STREAMDATA_SFID(sfid) | 180 (ssid < 0 ? 0 : ANA_TABLES_STREAMDATA_SSID_VALID) | 181 ANA_TABLES_STREAMDATA_SSID(ssid), 182 ANA_TABLES_STREAMDATA); 183 184 ret = __ocelot_mact_learn(ocelot, dst_idx, mac, vid, type); 185 186 mutex_unlock(&ocelot->mact_lock); 187 188 return ret; 189 } 190 EXPORT_SYMBOL(ocelot_mact_learn_streamdata); 191 192 static void ocelot_mact_init(struct ocelot *ocelot) 193 { 194 /* Configure the learning mode entries attributes: 195 * - Do not copy the frame to the CPU extraction queues. 196 * - Use the vlan and mac_cpoy for dmac lookup. 197 */ 198 ocelot_rmw(ocelot, 0, 199 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS 200 | ANA_AGENCTRL_LEARN_FWD_KILL 201 | ANA_AGENCTRL_LEARN_IGNORE_VLAN, 202 ANA_AGENCTRL); 203 204 /* Clear the MAC table. We are not concurrent with anyone, so 205 * holding &ocelot->mact_lock is pointless. 206 */ 207 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS); 208 } 209 210 static void ocelot_vcap_enable(struct ocelot *ocelot, int port) 211 { 212 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA | 213 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa), 214 ANA_PORT_VCAP_S2_CFG, port); 215 216 ocelot_write_gix(ocelot, ANA_PORT_VCAP_CFG_S1_ENA, 217 ANA_PORT_VCAP_CFG, port); 218 219 ocelot_rmw_gix(ocelot, REW_PORT_CFG_ES0_EN, 220 REW_PORT_CFG_ES0_EN, 221 REW_PORT_CFG, port); 222 } 223 224 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot) 225 { 226 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS); 227 } 228 229 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot) 230 { 231 u32 val; 232 233 return readx_poll_timeout(ocelot_vlant_read_vlanaccess, 234 ocelot, 235 val, 236 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) == 237 ANA_TABLES_VLANACCESS_CMD_IDLE, 238 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 239 } 240 241 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask) 242 { 243 /* Select the VID to configure */ 244 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid), 245 ANA_TABLES_VLANTIDX); 246 /* Set the vlan port members mask and issue a write command */ 247 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) | 248 ANA_TABLES_VLANACCESS_CMD_WRITE, 249 ANA_TABLES_VLANACCESS); 250 251 return ocelot_vlant_wait_for_completion(ocelot); 252 } 253 254 static int ocelot_port_num_untagged_vlans(struct ocelot *ocelot, int port) 255 { 256 struct ocelot_bridge_vlan *vlan; 257 int num_untagged = 0; 258 259 list_for_each_entry(vlan, &ocelot->vlans, list) { 260 if (!(vlan->portmask & BIT(port))) 261 continue; 262 263 if (vlan->untagged & BIT(port)) 264 num_untagged++; 265 } 266 267 return num_untagged; 268 } 269 270 static int ocelot_port_num_tagged_vlans(struct ocelot *ocelot, int port) 271 { 272 struct ocelot_bridge_vlan *vlan; 273 int num_tagged = 0; 274 275 list_for_each_entry(vlan, &ocelot->vlans, list) { 276 if (!(vlan->portmask & BIT(port))) 277 continue; 278 279 if (!(vlan->untagged & BIT(port))) 280 num_tagged++; 281 } 282 283 return num_tagged; 284 } 285 286 /* We use native VLAN when we have to mix egress-tagged VLANs with exactly 287 * _one_ egress-untagged VLAN (_the_ native VLAN) 288 */ 289 static bool ocelot_port_uses_native_vlan(struct ocelot *ocelot, int port) 290 { 291 return ocelot_port_num_tagged_vlans(ocelot, port) && 292 ocelot_port_num_untagged_vlans(ocelot, port) == 1; 293 } 294 295 static struct ocelot_bridge_vlan * 296 ocelot_port_find_native_vlan(struct ocelot *ocelot, int port) 297 { 298 struct ocelot_bridge_vlan *vlan; 299 300 list_for_each_entry(vlan, &ocelot->vlans, list) 301 if (vlan->portmask & BIT(port) && vlan->untagged & BIT(port)) 302 return vlan; 303 304 return NULL; 305 } 306 307 /* Keep in sync REW_TAG_CFG_TAG_CFG and, if applicable, 308 * REW_PORT_VLAN_CFG_PORT_VID, with the bridge VLAN table and VLAN awareness 309 * state of the port. 310 */ 311 static void ocelot_port_manage_port_tag(struct ocelot *ocelot, int port) 312 { 313 struct ocelot_port *ocelot_port = ocelot->ports[port]; 314 enum ocelot_port_tag_config tag_cfg; 315 bool uses_native_vlan = false; 316 317 if (ocelot_port->vlan_aware) { 318 uses_native_vlan = ocelot_port_uses_native_vlan(ocelot, port); 319 320 if (uses_native_vlan) 321 tag_cfg = OCELOT_PORT_TAG_NATIVE; 322 else if (ocelot_port_num_untagged_vlans(ocelot, port)) 323 tag_cfg = OCELOT_PORT_TAG_DISABLED; 324 else 325 tag_cfg = OCELOT_PORT_TAG_TRUNK; 326 } else { 327 tag_cfg = OCELOT_PORT_TAG_DISABLED; 328 } 329 330 ocelot_rmw_gix(ocelot, REW_TAG_CFG_TAG_CFG(tag_cfg), 331 REW_TAG_CFG_TAG_CFG_M, 332 REW_TAG_CFG, port); 333 334 if (uses_native_vlan) { 335 struct ocelot_bridge_vlan *native_vlan; 336 337 /* Not having a native VLAN is impossible, because 338 * ocelot_port_num_untagged_vlans has returned 1. 339 * So there is no use in checking for NULL here. 340 */ 341 native_vlan = ocelot_port_find_native_vlan(ocelot, port); 342 343 ocelot_rmw_gix(ocelot, 344 REW_PORT_VLAN_CFG_PORT_VID(native_vlan->vid), 345 REW_PORT_VLAN_CFG_PORT_VID_M, 346 REW_PORT_VLAN_CFG, port); 347 } 348 } 349 350 /* Default vlan to clasify for untagged frames (may be zero) */ 351 static void ocelot_port_set_pvid(struct ocelot *ocelot, int port, 352 const struct ocelot_bridge_vlan *pvid_vlan) 353 { 354 struct ocelot_port *ocelot_port = ocelot->ports[port]; 355 u16 pvid = OCELOT_VLAN_UNAWARE_PVID; 356 u32 val = 0; 357 358 ocelot_port->pvid_vlan = pvid_vlan; 359 360 if (ocelot_port->vlan_aware && pvid_vlan) 361 pvid = pvid_vlan->vid; 362 363 ocelot_rmw_gix(ocelot, 364 ANA_PORT_VLAN_CFG_VLAN_VID(pvid), 365 ANA_PORT_VLAN_CFG_VLAN_VID_M, 366 ANA_PORT_VLAN_CFG, port); 367 368 /* If there's no pvid, we should drop not only untagged traffic (which 369 * happens automatically), but also 802.1p traffic which gets 370 * classified to VLAN 0, but that is always in our RX filter, so it 371 * would get accepted were it not for this setting. 372 */ 373 if (!pvid_vlan && ocelot_port->vlan_aware) 374 val = ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 375 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA; 376 377 ocelot_rmw_gix(ocelot, val, 378 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 379 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, 380 ANA_PORT_DROP_CFG, port); 381 } 382 383 static struct ocelot_bridge_vlan *ocelot_bridge_vlan_find(struct ocelot *ocelot, 384 u16 vid) 385 { 386 struct ocelot_bridge_vlan *vlan; 387 388 list_for_each_entry(vlan, &ocelot->vlans, list) 389 if (vlan->vid == vid) 390 return vlan; 391 392 return NULL; 393 } 394 395 static int ocelot_vlan_member_add(struct ocelot *ocelot, int port, u16 vid, 396 bool untagged) 397 { 398 struct ocelot_bridge_vlan *vlan = ocelot_bridge_vlan_find(ocelot, vid); 399 unsigned long portmask; 400 int err; 401 402 if (vlan) { 403 portmask = vlan->portmask | BIT(port); 404 405 err = ocelot_vlant_set_mask(ocelot, vid, portmask); 406 if (err) 407 return err; 408 409 vlan->portmask = portmask; 410 /* Bridge VLANs can be overwritten with a different 411 * egress-tagging setting, so make sure to override an untagged 412 * with a tagged VID if that's going on. 413 */ 414 if (untagged) 415 vlan->untagged |= BIT(port); 416 else 417 vlan->untagged &= ~BIT(port); 418 419 return 0; 420 } 421 422 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL); 423 if (!vlan) 424 return -ENOMEM; 425 426 portmask = BIT(port); 427 428 err = ocelot_vlant_set_mask(ocelot, vid, portmask); 429 if (err) { 430 kfree(vlan); 431 return err; 432 } 433 434 vlan->vid = vid; 435 vlan->portmask = portmask; 436 if (untagged) 437 vlan->untagged = BIT(port); 438 INIT_LIST_HEAD(&vlan->list); 439 list_add_tail(&vlan->list, &ocelot->vlans); 440 441 return 0; 442 } 443 444 static int ocelot_vlan_member_del(struct ocelot *ocelot, int port, u16 vid) 445 { 446 struct ocelot_bridge_vlan *vlan = ocelot_bridge_vlan_find(ocelot, vid); 447 unsigned long portmask; 448 int err; 449 450 if (!vlan) 451 return 0; 452 453 portmask = vlan->portmask & ~BIT(port); 454 455 err = ocelot_vlant_set_mask(ocelot, vid, portmask); 456 if (err) 457 return err; 458 459 vlan->portmask = portmask; 460 if (vlan->portmask) 461 return 0; 462 463 list_del(&vlan->list); 464 kfree(vlan); 465 466 return 0; 467 } 468 469 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, 470 bool vlan_aware, struct netlink_ext_ack *extack) 471 { 472 struct ocelot_vcap_block *block = &ocelot->block[VCAP_IS1]; 473 struct ocelot_port *ocelot_port = ocelot->ports[port]; 474 struct ocelot_vcap_filter *filter; 475 u32 val; 476 477 list_for_each_entry(filter, &block->rules, list) { 478 if (filter->ingress_port_mask & BIT(port) && 479 filter->action.vid_replace_ena) { 480 NL_SET_ERR_MSG_MOD(extack, 481 "Cannot change VLAN state with vlan modify rules active"); 482 return -EBUSY; 483 } 484 } 485 486 ocelot_port->vlan_aware = vlan_aware; 487 488 if (vlan_aware) 489 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 490 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1); 491 else 492 val = 0; 493 ocelot_rmw_gix(ocelot, val, 494 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 495 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M, 496 ANA_PORT_VLAN_CFG, port); 497 498 ocelot_port_set_pvid(ocelot, port, ocelot_port->pvid_vlan); 499 ocelot_port_manage_port_tag(ocelot, port); 500 501 return 0; 502 } 503 EXPORT_SYMBOL(ocelot_port_vlan_filtering); 504 505 int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid, 506 bool untagged, struct netlink_ext_ack *extack) 507 { 508 if (untagged) { 509 /* We are adding an egress-tagged VLAN */ 510 if (ocelot_port_uses_native_vlan(ocelot, port)) { 511 NL_SET_ERR_MSG_MOD(extack, 512 "Port with egress-tagged VLANs cannot have more than one egress-untagged (native) VLAN"); 513 return -EBUSY; 514 } 515 } else { 516 /* We are adding an egress-tagged VLAN */ 517 if (ocelot_port_num_untagged_vlans(ocelot, port) > 1) { 518 NL_SET_ERR_MSG_MOD(extack, 519 "Port with more than one egress-untagged VLAN cannot have egress-tagged VLANs"); 520 return -EBUSY; 521 } 522 } 523 524 return 0; 525 } 526 EXPORT_SYMBOL(ocelot_vlan_prepare); 527 528 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid, 529 bool untagged) 530 { 531 int err; 532 533 err = ocelot_vlan_member_add(ocelot, port, vid, untagged); 534 if (err) 535 return err; 536 537 /* Default ingress vlan classification */ 538 if (pvid) 539 ocelot_port_set_pvid(ocelot, port, 540 ocelot_bridge_vlan_find(ocelot, vid)); 541 542 /* Untagged egress vlan clasification */ 543 ocelot_port_manage_port_tag(ocelot, port); 544 545 return 0; 546 } 547 EXPORT_SYMBOL(ocelot_vlan_add); 548 549 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid) 550 { 551 struct ocelot_port *ocelot_port = ocelot->ports[port]; 552 bool del_pvid = false; 553 int err; 554 555 if (ocelot_port->pvid_vlan && ocelot_port->pvid_vlan->vid == vid) 556 del_pvid = true; 557 558 err = ocelot_vlan_member_del(ocelot, port, vid); 559 if (err) 560 return err; 561 562 /* Ingress */ 563 if (del_pvid) 564 ocelot_port_set_pvid(ocelot, port, NULL); 565 566 /* Egress */ 567 ocelot_port_manage_port_tag(ocelot, port); 568 569 return 0; 570 } 571 EXPORT_SYMBOL(ocelot_vlan_del); 572 573 static void ocelot_vlan_init(struct ocelot *ocelot) 574 { 575 unsigned long all_ports = GENMASK(ocelot->num_phys_ports - 1, 0); 576 u16 port, vid; 577 578 /* Clear VLAN table, by default all ports are members of all VLANs */ 579 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT, 580 ANA_TABLES_VLANACCESS); 581 ocelot_vlant_wait_for_completion(ocelot); 582 583 /* Configure the port VLAN memberships */ 584 for (vid = 1; vid < VLAN_N_VID; vid++) 585 ocelot_vlant_set_mask(ocelot, vid, 0); 586 587 /* Because VLAN filtering is enabled, we need VID 0 to get untagged 588 * traffic. It is added automatically if 8021q module is loaded, but 589 * we can't rely on it since module may be not loaded. 590 */ 591 ocelot_vlant_set_mask(ocelot, OCELOT_VLAN_UNAWARE_PVID, all_ports); 592 593 /* Set vlan ingress filter mask to all ports but the CPU port by 594 * default. 595 */ 596 ocelot_write(ocelot, all_ports, ANA_VLANMASK); 597 598 for (port = 0; port < ocelot->num_phys_ports; port++) { 599 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port); 600 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port); 601 } 602 } 603 604 static u32 ocelot_read_eq_avail(struct ocelot *ocelot, int port) 605 { 606 return ocelot_read_rix(ocelot, QSYS_SW_STATUS, port); 607 } 608 609 static int ocelot_port_flush(struct ocelot *ocelot, int port) 610 { 611 unsigned int pause_ena; 612 int err, val; 613 614 /* Disable dequeuing from the egress queues */ 615 ocelot_rmw_rix(ocelot, QSYS_PORT_MODE_DEQUEUE_DIS, 616 QSYS_PORT_MODE_DEQUEUE_DIS, 617 QSYS_PORT_MODE, port); 618 619 /* Disable flow control */ 620 ocelot_fields_read(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, &pause_ena); 621 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 0); 622 623 /* Disable priority flow control */ 624 ocelot_fields_write(ocelot, port, 625 QSYS_SWITCH_PORT_MODE_TX_PFC_ENA, 0); 626 627 /* Wait at least the time it takes to receive a frame of maximum length 628 * at the port. 629 * Worst-case delays for 10 kilobyte jumbo frames are: 630 * 8 ms on a 10M port 631 * 800 μs on a 100M port 632 * 80 μs on a 1G port 633 * 32 μs on a 2.5G port 634 */ 635 usleep_range(8000, 10000); 636 637 /* Disable half duplex backpressure. */ 638 ocelot_rmw_rix(ocelot, 0, SYS_FRONT_PORT_MODE_HDX_MODE, 639 SYS_FRONT_PORT_MODE, port); 640 641 /* Flush the queues associated with the port. */ 642 ocelot_rmw_gix(ocelot, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG_FLUSH_ENA, 643 REW_PORT_CFG, port); 644 645 /* Enable dequeuing from the egress queues. */ 646 ocelot_rmw_rix(ocelot, 0, QSYS_PORT_MODE_DEQUEUE_DIS, QSYS_PORT_MODE, 647 port); 648 649 /* Wait until flushing is complete. */ 650 err = read_poll_timeout(ocelot_read_eq_avail, val, !val, 651 100, 2000000, false, ocelot, port); 652 653 /* Clear flushing again. */ 654 ocelot_rmw_gix(ocelot, 0, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG, port); 655 656 /* Re-enable flow control */ 657 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, pause_ena); 658 659 return err; 660 } 661 662 void ocelot_phylink_mac_link_down(struct ocelot *ocelot, int port, 663 unsigned int link_an_mode, 664 phy_interface_t interface, 665 unsigned long quirks) 666 { 667 struct ocelot_port *ocelot_port = ocelot->ports[port]; 668 int err; 669 670 ocelot_port->speed = SPEED_UNKNOWN; 671 672 ocelot_port_rmwl(ocelot_port, 0, DEV_MAC_ENA_CFG_RX_ENA, 673 DEV_MAC_ENA_CFG); 674 675 if (ocelot->ops->cut_through_fwd) { 676 mutex_lock(&ocelot->fwd_domain_lock); 677 ocelot->ops->cut_through_fwd(ocelot); 678 mutex_unlock(&ocelot->fwd_domain_lock); 679 } 680 681 ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0); 682 683 err = ocelot_port_flush(ocelot, port); 684 if (err) 685 dev_err(ocelot->dev, "failed to flush port %d: %d\n", 686 port, err); 687 688 /* Put the port in reset. */ 689 if (interface != PHY_INTERFACE_MODE_QSGMII || 690 !(quirks & OCELOT_QUIRK_QSGMII_PORTS_MUST_BE_UP)) 691 ocelot_port_rmwl(ocelot_port, 692 DEV_CLOCK_CFG_MAC_TX_RST | 693 DEV_CLOCK_CFG_MAC_RX_RST, 694 DEV_CLOCK_CFG_MAC_TX_RST | 695 DEV_CLOCK_CFG_MAC_RX_RST, 696 DEV_CLOCK_CFG); 697 } 698 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_down); 699 700 void ocelot_phylink_mac_link_up(struct ocelot *ocelot, int port, 701 struct phy_device *phydev, 702 unsigned int link_an_mode, 703 phy_interface_t interface, 704 int speed, int duplex, 705 bool tx_pause, bool rx_pause, 706 unsigned long quirks) 707 { 708 struct ocelot_port *ocelot_port = ocelot->ports[port]; 709 int mac_speed, mode = 0; 710 u32 mac_fc_cfg; 711 712 ocelot_port->speed = speed; 713 714 /* The MAC might be integrated in systems where the MAC speed is fixed 715 * and it's the PCS who is performing the rate adaptation, so we have 716 * to write "1000Mbps" into the LINK_SPEED field of DEV_CLOCK_CFG 717 * (which is also its default value). 718 */ 719 if ((quirks & OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION) || 720 speed == SPEED_1000) { 721 mac_speed = OCELOT_SPEED_1000; 722 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 723 } else if (speed == SPEED_2500) { 724 mac_speed = OCELOT_SPEED_2500; 725 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 726 } else if (speed == SPEED_100) { 727 mac_speed = OCELOT_SPEED_100; 728 } else { 729 mac_speed = OCELOT_SPEED_10; 730 } 731 732 if (duplex == DUPLEX_FULL) 733 mode |= DEV_MAC_MODE_CFG_FDX_ENA; 734 735 ocelot_port_writel(ocelot_port, mode, DEV_MAC_MODE_CFG); 736 737 /* Take port out of reset by clearing the MAC_TX_RST, MAC_RX_RST and 738 * PORT_RST bits in DEV_CLOCK_CFG. 739 */ 740 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(mac_speed), 741 DEV_CLOCK_CFG); 742 743 switch (speed) { 744 case SPEED_10: 745 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_10); 746 break; 747 case SPEED_100: 748 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_100); 749 break; 750 case SPEED_1000: 751 case SPEED_2500: 752 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_1000); 753 break; 754 default: 755 dev_err(ocelot->dev, "Unsupported speed on port %d: %d\n", 756 port, speed); 757 return; 758 } 759 760 /* Handle RX pause in all cases, with 2500base-X this is used for rate 761 * adaptation. 762 */ 763 mac_fc_cfg |= SYS_MAC_FC_CFG_RX_FC_ENA; 764 765 if (tx_pause) 766 mac_fc_cfg |= SYS_MAC_FC_CFG_TX_FC_ENA | 767 SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) | 768 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) | 769 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA; 770 771 /* Flow control. Link speed is only used here to evaluate the time 772 * specification in incoming pause frames. 773 */ 774 ocelot_write_rix(ocelot, mac_fc_cfg, SYS_MAC_FC_CFG, port); 775 776 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port); 777 778 /* Don't attempt to send PAUSE frames on the NPI port, it's broken */ 779 if (port != ocelot->npi) 780 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 781 tx_pause); 782 783 /* Undo the effects of ocelot_phylink_mac_link_down: 784 * enable MAC module 785 */ 786 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA | 787 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG); 788 789 /* If the port supports cut-through forwarding, update the masks before 790 * enabling forwarding on the port. 791 */ 792 if (ocelot->ops->cut_through_fwd) { 793 mutex_lock(&ocelot->fwd_domain_lock); 794 ocelot->ops->cut_through_fwd(ocelot); 795 mutex_unlock(&ocelot->fwd_domain_lock); 796 } 797 798 /* Core: Enable port for frame transfer */ 799 ocelot_fields_write(ocelot, port, 800 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 801 } 802 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_up); 803 804 static int ocelot_port_add_txtstamp_skb(struct ocelot *ocelot, int port, 805 struct sk_buff *clone) 806 { 807 struct ocelot_port *ocelot_port = ocelot->ports[port]; 808 unsigned long flags; 809 810 spin_lock_irqsave(&ocelot->ts_id_lock, flags); 811 812 if (ocelot_port->ptp_skbs_in_flight == OCELOT_MAX_PTP_ID || 813 ocelot->ptp_skbs_in_flight == OCELOT_PTP_FIFO_SIZE) { 814 spin_unlock_irqrestore(&ocelot->ts_id_lock, flags); 815 return -EBUSY; 816 } 817 818 skb_shinfo(clone)->tx_flags |= SKBTX_IN_PROGRESS; 819 /* Store timestamp ID in OCELOT_SKB_CB(clone)->ts_id */ 820 OCELOT_SKB_CB(clone)->ts_id = ocelot_port->ts_id; 821 822 ocelot_port->ts_id++; 823 if (ocelot_port->ts_id == OCELOT_MAX_PTP_ID) 824 ocelot_port->ts_id = 0; 825 826 ocelot_port->ptp_skbs_in_flight++; 827 ocelot->ptp_skbs_in_flight++; 828 829 skb_queue_tail(&ocelot_port->tx_skbs, clone); 830 831 spin_unlock_irqrestore(&ocelot->ts_id_lock, flags); 832 833 return 0; 834 } 835 836 static bool ocelot_ptp_is_onestep_sync(struct sk_buff *skb, 837 unsigned int ptp_class) 838 { 839 struct ptp_header *hdr; 840 u8 msgtype, twostep; 841 842 hdr = ptp_parse_header(skb, ptp_class); 843 if (!hdr) 844 return false; 845 846 msgtype = ptp_get_msgtype(hdr, ptp_class); 847 twostep = hdr->flag_field[0] & 0x2; 848 849 if (msgtype == PTP_MSGTYPE_SYNC && twostep == 0) 850 return true; 851 852 return false; 853 } 854 855 int ocelot_port_txtstamp_request(struct ocelot *ocelot, int port, 856 struct sk_buff *skb, 857 struct sk_buff **clone) 858 { 859 struct ocelot_port *ocelot_port = ocelot->ports[port]; 860 u8 ptp_cmd = ocelot_port->ptp_cmd; 861 unsigned int ptp_class; 862 int err; 863 864 /* Don't do anything if PTP timestamping not enabled */ 865 if (!ptp_cmd) 866 return 0; 867 868 ptp_class = ptp_classify_raw(skb); 869 if (ptp_class == PTP_CLASS_NONE) 870 return -EINVAL; 871 872 /* Store ptp_cmd in OCELOT_SKB_CB(skb)->ptp_cmd */ 873 if (ptp_cmd == IFH_REW_OP_ORIGIN_PTP) { 874 if (ocelot_ptp_is_onestep_sync(skb, ptp_class)) { 875 OCELOT_SKB_CB(skb)->ptp_cmd = ptp_cmd; 876 return 0; 877 } 878 879 /* Fall back to two-step timestamping */ 880 ptp_cmd = IFH_REW_OP_TWO_STEP_PTP; 881 } 882 883 if (ptp_cmd == IFH_REW_OP_TWO_STEP_PTP) { 884 *clone = skb_clone_sk(skb); 885 if (!(*clone)) 886 return -ENOMEM; 887 888 err = ocelot_port_add_txtstamp_skb(ocelot, port, *clone); 889 if (err) 890 return err; 891 892 OCELOT_SKB_CB(skb)->ptp_cmd = ptp_cmd; 893 OCELOT_SKB_CB(*clone)->ptp_class = ptp_class; 894 } 895 896 return 0; 897 } 898 EXPORT_SYMBOL(ocelot_port_txtstamp_request); 899 900 static void ocelot_get_hwtimestamp(struct ocelot *ocelot, 901 struct timespec64 *ts) 902 { 903 unsigned long flags; 904 u32 val; 905 906 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); 907 908 /* Read current PTP time to get seconds */ 909 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 910 911 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 912 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE); 913 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 914 ts->tv_sec = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN); 915 916 /* Read packet HW timestamp from FIFO */ 917 val = ocelot_read(ocelot, SYS_PTP_TXSTAMP); 918 ts->tv_nsec = SYS_PTP_TXSTAMP_PTP_TXSTAMP(val); 919 920 /* Sec has incremented since the ts was registered */ 921 if ((ts->tv_sec & 0x1) != !!(val & SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC)) 922 ts->tv_sec--; 923 924 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 925 } 926 927 static bool ocelot_validate_ptp_skb(struct sk_buff *clone, u16 seqid) 928 { 929 struct ptp_header *hdr; 930 931 hdr = ptp_parse_header(clone, OCELOT_SKB_CB(clone)->ptp_class); 932 if (WARN_ON(!hdr)) 933 return false; 934 935 return seqid == ntohs(hdr->sequence_id); 936 } 937 938 void ocelot_get_txtstamp(struct ocelot *ocelot) 939 { 940 int budget = OCELOT_PTP_QUEUE_SZ; 941 942 while (budget--) { 943 struct sk_buff *skb, *skb_tmp, *skb_match = NULL; 944 struct skb_shared_hwtstamps shhwtstamps; 945 u32 val, id, seqid, txport; 946 struct ocelot_port *port; 947 struct timespec64 ts; 948 unsigned long flags; 949 950 val = ocelot_read(ocelot, SYS_PTP_STATUS); 951 952 /* Check if a timestamp can be retrieved */ 953 if (!(val & SYS_PTP_STATUS_PTP_MESS_VLD)) 954 break; 955 956 WARN_ON(val & SYS_PTP_STATUS_PTP_OVFL); 957 958 /* Retrieve the ts ID and Tx port */ 959 id = SYS_PTP_STATUS_PTP_MESS_ID_X(val); 960 txport = SYS_PTP_STATUS_PTP_MESS_TXPORT_X(val); 961 seqid = SYS_PTP_STATUS_PTP_MESS_SEQ_ID(val); 962 963 port = ocelot->ports[txport]; 964 965 spin_lock(&ocelot->ts_id_lock); 966 port->ptp_skbs_in_flight--; 967 ocelot->ptp_skbs_in_flight--; 968 spin_unlock(&ocelot->ts_id_lock); 969 970 /* Retrieve its associated skb */ 971 try_again: 972 spin_lock_irqsave(&port->tx_skbs.lock, flags); 973 974 skb_queue_walk_safe(&port->tx_skbs, skb, skb_tmp) { 975 if (OCELOT_SKB_CB(skb)->ts_id != id) 976 continue; 977 __skb_unlink(skb, &port->tx_skbs); 978 skb_match = skb; 979 break; 980 } 981 982 spin_unlock_irqrestore(&port->tx_skbs.lock, flags); 983 984 if (WARN_ON(!skb_match)) 985 continue; 986 987 if (!ocelot_validate_ptp_skb(skb_match, seqid)) { 988 dev_err_ratelimited(ocelot->dev, 989 "port %d received stale TX timestamp for seqid %d, discarding\n", 990 txport, seqid); 991 dev_kfree_skb_any(skb); 992 goto try_again; 993 } 994 995 /* Get the h/w timestamp */ 996 ocelot_get_hwtimestamp(ocelot, &ts); 997 998 /* Set the timestamp into the skb */ 999 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 1000 shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec); 1001 skb_complete_tx_timestamp(skb_match, &shhwtstamps); 1002 1003 /* Next ts */ 1004 ocelot_write(ocelot, SYS_PTP_NXT_PTP_NXT, SYS_PTP_NXT); 1005 } 1006 } 1007 EXPORT_SYMBOL(ocelot_get_txtstamp); 1008 1009 static int ocelot_rx_frame_word(struct ocelot *ocelot, u8 grp, bool ifh, 1010 u32 *rval) 1011 { 1012 u32 bytes_valid, val; 1013 1014 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1015 if (val == XTR_NOT_READY) { 1016 if (ifh) 1017 return -EIO; 1018 1019 do { 1020 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1021 } while (val == XTR_NOT_READY); 1022 } 1023 1024 switch (val) { 1025 case XTR_ABORT: 1026 return -EIO; 1027 case XTR_EOF_0: 1028 case XTR_EOF_1: 1029 case XTR_EOF_2: 1030 case XTR_EOF_3: 1031 case XTR_PRUNED: 1032 bytes_valid = XTR_VALID_BYTES(val); 1033 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1034 if (val == XTR_ESCAPE) 1035 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1036 else 1037 *rval = val; 1038 1039 return bytes_valid; 1040 case XTR_ESCAPE: 1041 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1042 1043 return 4; 1044 default: 1045 *rval = val; 1046 1047 return 4; 1048 } 1049 } 1050 1051 static int ocelot_xtr_poll_xfh(struct ocelot *ocelot, int grp, u32 *xfh) 1052 { 1053 int i, err = 0; 1054 1055 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) { 1056 err = ocelot_rx_frame_word(ocelot, grp, true, &xfh[i]); 1057 if (err != 4) 1058 return (err < 0) ? err : -EIO; 1059 } 1060 1061 return 0; 1062 } 1063 1064 void ocelot_ptp_rx_timestamp(struct ocelot *ocelot, struct sk_buff *skb, 1065 u64 timestamp) 1066 { 1067 struct skb_shared_hwtstamps *shhwtstamps; 1068 u64 tod_in_ns, full_ts_in_ns; 1069 struct timespec64 ts; 1070 1071 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); 1072 1073 tod_in_ns = ktime_set(ts.tv_sec, ts.tv_nsec); 1074 if ((tod_in_ns & 0xffffffff) < timestamp) 1075 full_ts_in_ns = (((tod_in_ns >> 32) - 1) << 32) | 1076 timestamp; 1077 else 1078 full_ts_in_ns = (tod_in_ns & GENMASK_ULL(63, 32)) | 1079 timestamp; 1080 1081 shhwtstamps = skb_hwtstamps(skb); 1082 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps)); 1083 shhwtstamps->hwtstamp = full_ts_in_ns; 1084 } 1085 EXPORT_SYMBOL(ocelot_ptp_rx_timestamp); 1086 1087 int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **nskb) 1088 { 1089 u64 timestamp, src_port, len; 1090 u32 xfh[OCELOT_TAG_LEN / 4]; 1091 struct net_device *dev; 1092 struct sk_buff *skb; 1093 int sz, buf_len; 1094 u32 val, *buf; 1095 int err; 1096 1097 err = ocelot_xtr_poll_xfh(ocelot, grp, xfh); 1098 if (err) 1099 return err; 1100 1101 ocelot_xfh_get_src_port(xfh, &src_port); 1102 ocelot_xfh_get_len(xfh, &len); 1103 ocelot_xfh_get_rew_val(xfh, ×tamp); 1104 1105 if (WARN_ON(src_port >= ocelot->num_phys_ports)) 1106 return -EINVAL; 1107 1108 dev = ocelot->ops->port_to_netdev(ocelot, src_port); 1109 if (!dev) 1110 return -EINVAL; 1111 1112 skb = netdev_alloc_skb(dev, len); 1113 if (unlikely(!skb)) { 1114 netdev_err(dev, "Unable to allocate sk_buff\n"); 1115 return -ENOMEM; 1116 } 1117 1118 buf_len = len - ETH_FCS_LEN; 1119 buf = (u32 *)skb_put(skb, buf_len); 1120 1121 len = 0; 1122 do { 1123 sz = ocelot_rx_frame_word(ocelot, grp, false, &val); 1124 if (sz < 0) { 1125 err = sz; 1126 goto out_free_skb; 1127 } 1128 *buf++ = val; 1129 len += sz; 1130 } while (len < buf_len); 1131 1132 /* Read the FCS */ 1133 sz = ocelot_rx_frame_word(ocelot, grp, false, &val); 1134 if (sz < 0) { 1135 err = sz; 1136 goto out_free_skb; 1137 } 1138 1139 /* Update the statistics if part of the FCS was read before */ 1140 len -= ETH_FCS_LEN - sz; 1141 1142 if (unlikely(dev->features & NETIF_F_RXFCS)) { 1143 buf = (u32 *)skb_put(skb, ETH_FCS_LEN); 1144 *buf = val; 1145 } 1146 1147 if (ocelot->ptp) 1148 ocelot_ptp_rx_timestamp(ocelot, skb, timestamp); 1149 1150 /* Everything we see on an interface that is in the HW bridge 1151 * has already been forwarded. 1152 */ 1153 if (ocelot->ports[src_port]->bridge) 1154 skb->offload_fwd_mark = 1; 1155 1156 skb->protocol = eth_type_trans(skb, dev); 1157 1158 *nskb = skb; 1159 1160 return 0; 1161 1162 out_free_skb: 1163 kfree_skb(skb); 1164 return err; 1165 } 1166 EXPORT_SYMBOL(ocelot_xtr_poll_frame); 1167 1168 bool ocelot_can_inject(struct ocelot *ocelot, int grp) 1169 { 1170 u32 val = ocelot_read(ocelot, QS_INJ_STATUS); 1171 1172 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp)))) 1173 return false; 1174 if (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp))) 1175 return false; 1176 1177 return true; 1178 } 1179 EXPORT_SYMBOL(ocelot_can_inject); 1180 1181 void ocelot_ifh_port_set(void *ifh, int port, u32 rew_op, u32 vlan_tag) 1182 { 1183 ocelot_ifh_set_bypass(ifh, 1); 1184 ocelot_ifh_set_dest(ifh, BIT_ULL(port)); 1185 ocelot_ifh_set_tag_type(ifh, IFH_TAG_TYPE_C); 1186 if (vlan_tag) 1187 ocelot_ifh_set_vlan_tci(ifh, vlan_tag); 1188 if (rew_op) 1189 ocelot_ifh_set_rew_op(ifh, rew_op); 1190 } 1191 EXPORT_SYMBOL(ocelot_ifh_port_set); 1192 1193 void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp, 1194 u32 rew_op, struct sk_buff *skb) 1195 { 1196 u32 ifh[OCELOT_TAG_LEN / 4] = {0}; 1197 unsigned int i, count, last; 1198 1199 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 1200 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp); 1201 1202 ocelot_ifh_port_set(ifh, port, rew_op, skb_vlan_tag_get(skb)); 1203 1204 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) 1205 ocelot_write_rix(ocelot, ifh[i], QS_INJ_WR, grp); 1206 1207 count = DIV_ROUND_UP(skb->len, 4); 1208 last = skb->len % 4; 1209 for (i = 0; i < count; i++) 1210 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp); 1211 1212 /* Add padding */ 1213 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) { 1214 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 1215 i++; 1216 } 1217 1218 /* Indicate EOF and valid bytes in last word */ 1219 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 1220 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) | 1221 QS_INJ_CTRL_EOF, 1222 QS_INJ_CTRL, grp); 1223 1224 /* Add dummy CRC */ 1225 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 1226 skb_tx_timestamp(skb); 1227 1228 skb->dev->stats.tx_packets++; 1229 skb->dev->stats.tx_bytes += skb->len; 1230 } 1231 EXPORT_SYMBOL(ocelot_port_inject_frame); 1232 1233 void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp) 1234 { 1235 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)) 1236 ocelot_read_rix(ocelot, QS_XTR_RD, grp); 1237 } 1238 EXPORT_SYMBOL(ocelot_drain_cpu_queue); 1239 1240 int ocelot_fdb_add(struct ocelot *ocelot, int port, 1241 const unsigned char *addr, u16 vid) 1242 { 1243 int pgid = port; 1244 1245 if (port == ocelot->npi) 1246 pgid = PGID_CPU; 1247 1248 return ocelot_mact_learn(ocelot, pgid, addr, vid, ENTRYTYPE_LOCKED); 1249 } 1250 EXPORT_SYMBOL(ocelot_fdb_add); 1251 1252 int ocelot_fdb_del(struct ocelot *ocelot, int port, 1253 const unsigned char *addr, u16 vid) 1254 { 1255 return ocelot_mact_forget(ocelot, addr, vid); 1256 } 1257 EXPORT_SYMBOL(ocelot_fdb_del); 1258 1259 int ocelot_port_fdb_do_dump(const unsigned char *addr, u16 vid, 1260 bool is_static, void *data) 1261 { 1262 struct ocelot_dump_ctx *dump = data; 1263 u32 portid = NETLINK_CB(dump->cb->skb).portid; 1264 u32 seq = dump->cb->nlh->nlmsg_seq; 1265 struct nlmsghdr *nlh; 1266 struct ndmsg *ndm; 1267 1268 if (dump->idx < dump->cb->args[2]) 1269 goto skip; 1270 1271 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH, 1272 sizeof(*ndm), NLM_F_MULTI); 1273 if (!nlh) 1274 return -EMSGSIZE; 1275 1276 ndm = nlmsg_data(nlh); 1277 ndm->ndm_family = AF_BRIDGE; 1278 ndm->ndm_pad1 = 0; 1279 ndm->ndm_pad2 = 0; 1280 ndm->ndm_flags = NTF_SELF; 1281 ndm->ndm_type = 0; 1282 ndm->ndm_ifindex = dump->dev->ifindex; 1283 ndm->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE; 1284 1285 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, addr)) 1286 goto nla_put_failure; 1287 1288 if (vid && nla_put_u16(dump->skb, NDA_VLAN, vid)) 1289 goto nla_put_failure; 1290 1291 nlmsg_end(dump->skb, nlh); 1292 1293 skip: 1294 dump->idx++; 1295 return 0; 1296 1297 nla_put_failure: 1298 nlmsg_cancel(dump->skb, nlh); 1299 return -EMSGSIZE; 1300 } 1301 EXPORT_SYMBOL(ocelot_port_fdb_do_dump); 1302 1303 /* Caller must hold &ocelot->mact_lock */ 1304 static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col, 1305 struct ocelot_mact_entry *entry) 1306 { 1307 u32 val, dst, macl, mach; 1308 char mac[ETH_ALEN]; 1309 1310 /* Set row and column to read from */ 1311 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row); 1312 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col); 1313 1314 /* Issue a read command */ 1315 ocelot_write(ocelot, 1316 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 1317 ANA_TABLES_MACACCESS); 1318 1319 if (ocelot_mact_wait_for_completion(ocelot)) 1320 return -ETIMEDOUT; 1321 1322 /* Read the entry flags */ 1323 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 1324 if (!(val & ANA_TABLES_MACACCESS_VALID)) 1325 return -EINVAL; 1326 1327 /* If the entry read has another port configured as its destination, 1328 * do not report it. 1329 */ 1330 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3; 1331 if (dst != port) 1332 return -EINVAL; 1333 1334 /* Get the entry's MAC address and VLAN id */ 1335 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA); 1336 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA); 1337 1338 mac[0] = (mach >> 8) & 0xff; 1339 mac[1] = (mach >> 0) & 0xff; 1340 mac[2] = (macl >> 24) & 0xff; 1341 mac[3] = (macl >> 16) & 0xff; 1342 mac[4] = (macl >> 8) & 0xff; 1343 mac[5] = (macl >> 0) & 0xff; 1344 1345 entry->vid = (mach >> 16) & 0xfff; 1346 ether_addr_copy(entry->mac, mac); 1347 1348 return 0; 1349 } 1350 1351 int ocelot_mact_flush(struct ocelot *ocelot, int port) 1352 { 1353 int err; 1354 1355 mutex_lock(&ocelot->mact_lock); 1356 1357 /* Program ageing filter for a single port */ 1358 ocelot_write(ocelot, ANA_ANAGEFIL_PID_EN | ANA_ANAGEFIL_PID_VAL(port), 1359 ANA_ANAGEFIL); 1360 1361 /* Flushing dynamic FDB entries requires two successive age scans */ 1362 ocelot_write(ocelot, 1363 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_AGE), 1364 ANA_TABLES_MACACCESS); 1365 1366 err = ocelot_mact_wait_for_completion(ocelot); 1367 if (err) { 1368 mutex_unlock(&ocelot->mact_lock); 1369 return err; 1370 } 1371 1372 /* And second... */ 1373 ocelot_write(ocelot, 1374 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_AGE), 1375 ANA_TABLES_MACACCESS); 1376 1377 err = ocelot_mact_wait_for_completion(ocelot); 1378 1379 /* Restore ageing filter */ 1380 ocelot_write(ocelot, 0, ANA_ANAGEFIL); 1381 1382 mutex_unlock(&ocelot->mact_lock); 1383 1384 return err; 1385 } 1386 EXPORT_SYMBOL_GPL(ocelot_mact_flush); 1387 1388 int ocelot_fdb_dump(struct ocelot *ocelot, int port, 1389 dsa_fdb_dump_cb_t *cb, void *data) 1390 { 1391 int err = 0; 1392 int i, j; 1393 1394 /* We could take the lock just around ocelot_mact_read, but doing so 1395 * thousands of times in a row seems rather pointless and inefficient. 1396 */ 1397 mutex_lock(&ocelot->mact_lock); 1398 1399 /* Loop through all the mac tables entries. */ 1400 for (i = 0; i < ocelot->num_mact_rows; i++) { 1401 for (j = 0; j < 4; j++) { 1402 struct ocelot_mact_entry entry; 1403 bool is_static; 1404 1405 err = ocelot_mact_read(ocelot, port, i, j, &entry); 1406 /* If the entry is invalid (wrong port, invalid...), 1407 * skip it. 1408 */ 1409 if (err == -EINVAL) 1410 continue; 1411 else if (err) 1412 break; 1413 1414 is_static = (entry.type == ENTRYTYPE_LOCKED); 1415 1416 err = cb(entry.mac, entry.vid, is_static, data); 1417 if (err) 1418 break; 1419 } 1420 } 1421 1422 mutex_unlock(&ocelot->mact_lock); 1423 1424 return err; 1425 } 1426 EXPORT_SYMBOL(ocelot_fdb_dump); 1427 1428 static void ocelot_populate_l2_ptp_trap_key(struct ocelot_vcap_filter *trap) 1429 { 1430 trap->key_type = OCELOT_VCAP_KEY_ETYPE; 1431 *(__be16 *)trap->key.etype.etype.value = htons(ETH_P_1588); 1432 *(__be16 *)trap->key.etype.etype.mask = htons(0xffff); 1433 } 1434 1435 static void 1436 ocelot_populate_ipv4_ptp_event_trap_key(struct ocelot_vcap_filter *trap) 1437 { 1438 trap->key_type = OCELOT_VCAP_KEY_IPV4; 1439 trap->key.ipv4.proto.value[0] = IPPROTO_UDP; 1440 trap->key.ipv4.proto.mask[0] = 0xff; 1441 trap->key.ipv4.dport.value = PTP_EV_PORT; 1442 trap->key.ipv4.dport.mask = 0xffff; 1443 } 1444 1445 static void 1446 ocelot_populate_ipv6_ptp_event_trap_key(struct ocelot_vcap_filter *trap) 1447 { 1448 trap->key_type = OCELOT_VCAP_KEY_IPV6; 1449 trap->key.ipv4.proto.value[0] = IPPROTO_UDP; 1450 trap->key.ipv4.proto.mask[0] = 0xff; 1451 trap->key.ipv6.dport.value = PTP_EV_PORT; 1452 trap->key.ipv6.dport.mask = 0xffff; 1453 } 1454 1455 static void 1456 ocelot_populate_ipv4_ptp_general_trap_key(struct ocelot_vcap_filter *trap) 1457 { 1458 trap->key_type = OCELOT_VCAP_KEY_IPV4; 1459 trap->key.ipv4.proto.value[0] = IPPROTO_UDP; 1460 trap->key.ipv4.proto.mask[0] = 0xff; 1461 trap->key.ipv4.dport.value = PTP_GEN_PORT; 1462 trap->key.ipv4.dport.mask = 0xffff; 1463 } 1464 1465 static void 1466 ocelot_populate_ipv6_ptp_general_trap_key(struct ocelot_vcap_filter *trap) 1467 { 1468 trap->key_type = OCELOT_VCAP_KEY_IPV6; 1469 trap->key.ipv4.proto.value[0] = IPPROTO_UDP; 1470 trap->key.ipv4.proto.mask[0] = 0xff; 1471 trap->key.ipv6.dport.value = PTP_GEN_PORT; 1472 trap->key.ipv6.dport.mask = 0xffff; 1473 } 1474 1475 int ocelot_trap_add(struct ocelot *ocelot, int port, 1476 unsigned long cookie, bool take_ts, 1477 void (*populate)(struct ocelot_vcap_filter *f)) 1478 { 1479 struct ocelot_vcap_block *block_vcap_is2; 1480 struct ocelot_vcap_filter *trap; 1481 bool new = false; 1482 int err; 1483 1484 block_vcap_is2 = &ocelot->block[VCAP_IS2]; 1485 1486 trap = ocelot_vcap_block_find_filter_by_id(block_vcap_is2, cookie, 1487 false); 1488 if (!trap) { 1489 trap = kzalloc(sizeof(*trap), GFP_KERNEL); 1490 if (!trap) 1491 return -ENOMEM; 1492 1493 populate(trap); 1494 trap->prio = 1; 1495 trap->id.cookie = cookie; 1496 trap->id.tc_offload = false; 1497 trap->block_id = VCAP_IS2; 1498 trap->type = OCELOT_VCAP_FILTER_OFFLOAD; 1499 trap->lookup = 0; 1500 trap->action.cpu_copy_ena = true; 1501 trap->action.mask_mode = OCELOT_MASK_MODE_PERMIT_DENY; 1502 trap->action.port_mask = 0; 1503 trap->take_ts = take_ts; 1504 list_add_tail(&trap->trap_list, &ocelot->traps); 1505 new = true; 1506 } 1507 1508 trap->ingress_port_mask |= BIT(port); 1509 1510 if (new) 1511 err = ocelot_vcap_filter_add(ocelot, trap, NULL); 1512 else 1513 err = ocelot_vcap_filter_replace(ocelot, trap); 1514 if (err) { 1515 trap->ingress_port_mask &= ~BIT(port); 1516 if (!trap->ingress_port_mask) { 1517 list_del(&trap->trap_list); 1518 kfree(trap); 1519 } 1520 return err; 1521 } 1522 1523 return 0; 1524 } 1525 1526 int ocelot_trap_del(struct ocelot *ocelot, int port, unsigned long cookie) 1527 { 1528 struct ocelot_vcap_block *block_vcap_is2; 1529 struct ocelot_vcap_filter *trap; 1530 1531 block_vcap_is2 = &ocelot->block[VCAP_IS2]; 1532 1533 trap = ocelot_vcap_block_find_filter_by_id(block_vcap_is2, cookie, 1534 false); 1535 if (!trap) 1536 return 0; 1537 1538 trap->ingress_port_mask &= ~BIT(port); 1539 if (!trap->ingress_port_mask) { 1540 list_del(&trap->trap_list); 1541 1542 return ocelot_vcap_filter_del(ocelot, trap); 1543 } 1544 1545 return ocelot_vcap_filter_replace(ocelot, trap); 1546 } 1547 1548 static int ocelot_l2_ptp_trap_add(struct ocelot *ocelot, int port) 1549 { 1550 unsigned long l2_cookie = OCELOT_VCAP_IS2_L2_PTP_TRAP(ocelot); 1551 1552 return ocelot_trap_add(ocelot, port, l2_cookie, true, 1553 ocelot_populate_l2_ptp_trap_key); 1554 } 1555 1556 static int ocelot_l2_ptp_trap_del(struct ocelot *ocelot, int port) 1557 { 1558 unsigned long l2_cookie = OCELOT_VCAP_IS2_L2_PTP_TRAP(ocelot); 1559 1560 return ocelot_trap_del(ocelot, port, l2_cookie); 1561 } 1562 1563 static int ocelot_ipv4_ptp_trap_add(struct ocelot *ocelot, int port) 1564 { 1565 unsigned long ipv4_gen_cookie = OCELOT_VCAP_IS2_IPV4_GEN_PTP_TRAP(ocelot); 1566 unsigned long ipv4_ev_cookie = OCELOT_VCAP_IS2_IPV4_EV_PTP_TRAP(ocelot); 1567 int err; 1568 1569 err = ocelot_trap_add(ocelot, port, ipv4_ev_cookie, true, 1570 ocelot_populate_ipv4_ptp_event_trap_key); 1571 if (err) 1572 return err; 1573 1574 err = ocelot_trap_add(ocelot, port, ipv4_gen_cookie, false, 1575 ocelot_populate_ipv4_ptp_general_trap_key); 1576 if (err) 1577 ocelot_trap_del(ocelot, port, ipv4_ev_cookie); 1578 1579 return err; 1580 } 1581 1582 static int ocelot_ipv4_ptp_trap_del(struct ocelot *ocelot, int port) 1583 { 1584 unsigned long ipv4_gen_cookie = OCELOT_VCAP_IS2_IPV4_GEN_PTP_TRAP(ocelot); 1585 unsigned long ipv4_ev_cookie = OCELOT_VCAP_IS2_IPV4_EV_PTP_TRAP(ocelot); 1586 int err; 1587 1588 err = ocelot_trap_del(ocelot, port, ipv4_ev_cookie); 1589 err |= ocelot_trap_del(ocelot, port, ipv4_gen_cookie); 1590 return err; 1591 } 1592 1593 static int ocelot_ipv6_ptp_trap_add(struct ocelot *ocelot, int port) 1594 { 1595 unsigned long ipv6_gen_cookie = OCELOT_VCAP_IS2_IPV6_GEN_PTP_TRAP(ocelot); 1596 unsigned long ipv6_ev_cookie = OCELOT_VCAP_IS2_IPV6_EV_PTP_TRAP(ocelot); 1597 int err; 1598 1599 err = ocelot_trap_add(ocelot, port, ipv6_ev_cookie, true, 1600 ocelot_populate_ipv6_ptp_event_trap_key); 1601 if (err) 1602 return err; 1603 1604 err = ocelot_trap_add(ocelot, port, ipv6_gen_cookie, false, 1605 ocelot_populate_ipv6_ptp_general_trap_key); 1606 if (err) 1607 ocelot_trap_del(ocelot, port, ipv6_ev_cookie); 1608 1609 return err; 1610 } 1611 1612 static int ocelot_ipv6_ptp_trap_del(struct ocelot *ocelot, int port) 1613 { 1614 unsigned long ipv6_gen_cookie = OCELOT_VCAP_IS2_IPV6_GEN_PTP_TRAP(ocelot); 1615 unsigned long ipv6_ev_cookie = OCELOT_VCAP_IS2_IPV6_EV_PTP_TRAP(ocelot); 1616 int err; 1617 1618 err = ocelot_trap_del(ocelot, port, ipv6_ev_cookie); 1619 err |= ocelot_trap_del(ocelot, port, ipv6_gen_cookie); 1620 return err; 1621 } 1622 1623 static int ocelot_setup_ptp_traps(struct ocelot *ocelot, int port, 1624 bool l2, bool l4) 1625 { 1626 int err; 1627 1628 if (l2) 1629 err = ocelot_l2_ptp_trap_add(ocelot, port); 1630 else 1631 err = ocelot_l2_ptp_trap_del(ocelot, port); 1632 if (err) 1633 return err; 1634 1635 if (l4) { 1636 err = ocelot_ipv4_ptp_trap_add(ocelot, port); 1637 if (err) 1638 goto err_ipv4; 1639 1640 err = ocelot_ipv6_ptp_trap_add(ocelot, port); 1641 if (err) 1642 goto err_ipv6; 1643 } else { 1644 err = ocelot_ipv4_ptp_trap_del(ocelot, port); 1645 1646 err |= ocelot_ipv6_ptp_trap_del(ocelot, port); 1647 } 1648 if (err) 1649 return err; 1650 1651 return 0; 1652 1653 err_ipv6: 1654 ocelot_ipv4_ptp_trap_del(ocelot, port); 1655 err_ipv4: 1656 if (l2) 1657 ocelot_l2_ptp_trap_del(ocelot, port); 1658 return err; 1659 } 1660 1661 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr) 1662 { 1663 return copy_to_user(ifr->ifr_data, &ocelot->hwtstamp_config, 1664 sizeof(ocelot->hwtstamp_config)) ? -EFAULT : 0; 1665 } 1666 EXPORT_SYMBOL(ocelot_hwstamp_get); 1667 1668 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr) 1669 { 1670 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1671 bool l2 = false, l4 = false; 1672 struct hwtstamp_config cfg; 1673 int err; 1674 1675 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1676 return -EFAULT; 1677 1678 /* Tx type sanity check */ 1679 switch (cfg.tx_type) { 1680 case HWTSTAMP_TX_ON: 1681 ocelot_port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP; 1682 break; 1683 case HWTSTAMP_TX_ONESTEP_SYNC: 1684 /* IFH_REW_OP_ONE_STEP_PTP updates the correctional field, we 1685 * need to update the origin time. 1686 */ 1687 ocelot_port->ptp_cmd = IFH_REW_OP_ORIGIN_PTP; 1688 break; 1689 case HWTSTAMP_TX_OFF: 1690 ocelot_port->ptp_cmd = 0; 1691 break; 1692 default: 1693 return -ERANGE; 1694 } 1695 1696 mutex_lock(&ocelot->ptp_lock); 1697 1698 switch (cfg.rx_filter) { 1699 case HWTSTAMP_FILTER_NONE: 1700 break; 1701 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1702 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1703 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1704 l4 = true; 1705 break; 1706 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1707 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1708 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1709 l2 = true; 1710 break; 1711 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1712 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1713 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1714 l2 = true; 1715 l4 = true; 1716 break; 1717 default: 1718 mutex_unlock(&ocelot->ptp_lock); 1719 return -ERANGE; 1720 } 1721 1722 err = ocelot_setup_ptp_traps(ocelot, port, l2, l4); 1723 if (err) { 1724 mutex_unlock(&ocelot->ptp_lock); 1725 return err; 1726 } 1727 1728 if (l2 && l4) 1729 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 1730 else if (l2) 1731 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 1732 else if (l4) 1733 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 1734 else 1735 cfg.rx_filter = HWTSTAMP_FILTER_NONE; 1736 1737 /* Commit back the result & save it */ 1738 memcpy(&ocelot->hwtstamp_config, &cfg, sizeof(cfg)); 1739 mutex_unlock(&ocelot->ptp_lock); 1740 1741 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1742 } 1743 EXPORT_SYMBOL(ocelot_hwstamp_set); 1744 1745 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data) 1746 { 1747 int i; 1748 1749 if (sset != ETH_SS_STATS) 1750 return; 1751 1752 for (i = 0; i < ocelot->num_stats; i++) 1753 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name, 1754 ETH_GSTRING_LEN); 1755 } 1756 EXPORT_SYMBOL(ocelot_get_strings); 1757 1758 /* Caller must hold &ocelot->stats_lock */ 1759 static int ocelot_port_update_stats(struct ocelot *ocelot, int port) 1760 { 1761 unsigned int idx = port * ocelot->num_stats; 1762 struct ocelot_stats_region *region; 1763 int err, j; 1764 1765 /* Configure the port to read the stats from */ 1766 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port), SYS_STAT_CFG); 1767 1768 list_for_each_entry(region, &ocelot->stats_regions, node) { 1769 err = ocelot_bulk_read_rix(ocelot, SYS_COUNT_RX_OCTETS, 1770 region->offset, region->buf, 1771 region->count); 1772 if (err) 1773 return err; 1774 1775 for (j = 0; j < region->count; j++) { 1776 u64 *stat = &ocelot->stats[idx + j]; 1777 u64 val = region->buf[j]; 1778 1779 if (val < (*stat & U32_MAX)) 1780 *stat += (u64)1 << 32; 1781 1782 *stat = (*stat & ~(u64)U32_MAX) + val; 1783 } 1784 1785 idx += region->count; 1786 } 1787 1788 return err; 1789 } 1790 1791 static void ocelot_check_stats_work(struct work_struct *work) 1792 { 1793 struct delayed_work *del_work = to_delayed_work(work); 1794 struct ocelot *ocelot = container_of(del_work, struct ocelot, 1795 stats_work); 1796 int i, err; 1797 1798 mutex_lock(&ocelot->stats_lock); 1799 for (i = 0; i < ocelot->num_phys_ports; i++) { 1800 err = ocelot_port_update_stats(ocelot, i); 1801 if (err) 1802 break; 1803 } 1804 mutex_unlock(&ocelot->stats_lock); 1805 1806 if (err) 1807 dev_err(ocelot->dev, "Error %d updating ethtool stats\n", err); 1808 1809 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 1810 OCELOT_STATS_CHECK_DELAY); 1811 } 1812 1813 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data) 1814 { 1815 int i, err; 1816 1817 mutex_lock(&ocelot->stats_lock); 1818 1819 /* check and update now */ 1820 err = ocelot_port_update_stats(ocelot, port); 1821 1822 /* Copy all counters */ 1823 for (i = 0; i < ocelot->num_stats; i++) 1824 *data++ = ocelot->stats[port * ocelot->num_stats + i]; 1825 1826 mutex_unlock(&ocelot->stats_lock); 1827 1828 if (err) 1829 dev_err(ocelot->dev, "Error %d updating ethtool stats\n", err); 1830 } 1831 EXPORT_SYMBOL(ocelot_get_ethtool_stats); 1832 1833 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset) 1834 { 1835 if (sset != ETH_SS_STATS) 1836 return -EOPNOTSUPP; 1837 1838 return ocelot->num_stats; 1839 } 1840 EXPORT_SYMBOL(ocelot_get_sset_count); 1841 1842 static int ocelot_prepare_stats_regions(struct ocelot *ocelot) 1843 { 1844 struct ocelot_stats_region *region = NULL; 1845 unsigned int last; 1846 int i; 1847 1848 INIT_LIST_HEAD(&ocelot->stats_regions); 1849 1850 for (i = 0; i < ocelot->num_stats; i++) { 1851 if (region && ocelot->stats_layout[i].offset == last + 1) { 1852 region->count++; 1853 } else { 1854 region = devm_kzalloc(ocelot->dev, sizeof(*region), 1855 GFP_KERNEL); 1856 if (!region) 1857 return -ENOMEM; 1858 1859 region->offset = ocelot->stats_layout[i].offset; 1860 region->count = 1; 1861 list_add_tail(®ion->node, &ocelot->stats_regions); 1862 } 1863 1864 last = ocelot->stats_layout[i].offset; 1865 } 1866 1867 list_for_each_entry(region, &ocelot->stats_regions, node) { 1868 region->buf = devm_kcalloc(ocelot->dev, region->count, 1869 sizeof(*region->buf), GFP_KERNEL); 1870 if (!region->buf) 1871 return -ENOMEM; 1872 } 1873 1874 return 0; 1875 } 1876 1877 int ocelot_get_ts_info(struct ocelot *ocelot, int port, 1878 struct ethtool_ts_info *info) 1879 { 1880 info->phc_index = ocelot->ptp_clock ? 1881 ptp_clock_index(ocelot->ptp_clock) : -1; 1882 if (info->phc_index == -1) { 1883 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 1884 SOF_TIMESTAMPING_RX_SOFTWARE | 1885 SOF_TIMESTAMPING_SOFTWARE; 1886 return 0; 1887 } 1888 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 1889 SOF_TIMESTAMPING_RX_SOFTWARE | 1890 SOF_TIMESTAMPING_SOFTWARE | 1891 SOF_TIMESTAMPING_TX_HARDWARE | 1892 SOF_TIMESTAMPING_RX_HARDWARE | 1893 SOF_TIMESTAMPING_RAW_HARDWARE; 1894 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON) | 1895 BIT(HWTSTAMP_TX_ONESTEP_SYNC); 1896 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | 1897 BIT(HWTSTAMP_FILTER_PTP_V2_EVENT) | 1898 BIT(HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1899 BIT(HWTSTAMP_FILTER_PTP_V2_L4_EVENT); 1900 1901 return 0; 1902 } 1903 EXPORT_SYMBOL(ocelot_get_ts_info); 1904 1905 static u32 ocelot_get_bond_mask(struct ocelot *ocelot, struct net_device *bond) 1906 { 1907 u32 mask = 0; 1908 int port; 1909 1910 lockdep_assert_held(&ocelot->fwd_domain_lock); 1911 1912 for (port = 0; port < ocelot->num_phys_ports; port++) { 1913 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1914 1915 if (!ocelot_port) 1916 continue; 1917 1918 if (ocelot_port->bond == bond) 1919 mask |= BIT(port); 1920 } 1921 1922 return mask; 1923 } 1924 1925 /* The logical port number of a LAG is equal to the lowest numbered physical 1926 * port ID present in that LAG. It may change if that port ever leaves the LAG. 1927 */ 1928 static int ocelot_bond_get_id(struct ocelot *ocelot, struct net_device *bond) 1929 { 1930 int bond_mask = ocelot_get_bond_mask(ocelot, bond); 1931 1932 if (!bond_mask) 1933 return -ENOENT; 1934 1935 return __ffs(bond_mask); 1936 } 1937 1938 u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot, int src_port) 1939 { 1940 struct ocelot_port *ocelot_port = ocelot->ports[src_port]; 1941 const struct net_device *bridge; 1942 u32 mask = 0; 1943 int port; 1944 1945 if (!ocelot_port || ocelot_port->stp_state != BR_STATE_FORWARDING) 1946 return 0; 1947 1948 bridge = ocelot_port->bridge; 1949 if (!bridge) 1950 return 0; 1951 1952 for (port = 0; port < ocelot->num_phys_ports; port++) { 1953 ocelot_port = ocelot->ports[port]; 1954 1955 if (!ocelot_port) 1956 continue; 1957 1958 if (ocelot_port->stp_state == BR_STATE_FORWARDING && 1959 ocelot_port->bridge == bridge) 1960 mask |= BIT(port); 1961 } 1962 1963 return mask; 1964 } 1965 EXPORT_SYMBOL_GPL(ocelot_get_bridge_fwd_mask); 1966 1967 u32 ocelot_get_dsa_8021q_cpu_mask(struct ocelot *ocelot) 1968 { 1969 u32 mask = 0; 1970 int port; 1971 1972 for (port = 0; port < ocelot->num_phys_ports; port++) { 1973 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1974 1975 if (!ocelot_port) 1976 continue; 1977 1978 if (ocelot_port->is_dsa_8021q_cpu) 1979 mask |= BIT(port); 1980 } 1981 1982 return mask; 1983 } 1984 EXPORT_SYMBOL_GPL(ocelot_get_dsa_8021q_cpu_mask); 1985 1986 void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot, bool joining) 1987 { 1988 unsigned long cpu_fwd_mask; 1989 int port; 1990 1991 lockdep_assert_held(&ocelot->fwd_domain_lock); 1992 1993 /* If cut-through forwarding is supported, update the masks before a 1994 * port joins the forwarding domain, to avoid potential underruns if it 1995 * has the highest speed from the new domain. 1996 */ 1997 if (joining && ocelot->ops->cut_through_fwd) 1998 ocelot->ops->cut_through_fwd(ocelot); 1999 2000 /* If a DSA tag_8021q CPU exists, it needs to be included in the 2001 * regular forwarding path of the front ports regardless of whether 2002 * those are bridged or standalone. 2003 * If DSA tag_8021q is not used, this returns 0, which is fine because 2004 * the hardware-based CPU port module can be a destination for packets 2005 * even if it isn't part of PGID_SRC. 2006 */ 2007 cpu_fwd_mask = ocelot_get_dsa_8021q_cpu_mask(ocelot); 2008 2009 /* Apply FWD mask. The loop is needed to add/remove the current port as 2010 * a source for the other ports. 2011 */ 2012 for (port = 0; port < ocelot->num_phys_ports; port++) { 2013 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2014 unsigned long mask; 2015 2016 if (!ocelot_port) { 2017 /* Unused ports can't send anywhere */ 2018 mask = 0; 2019 } else if (ocelot_port->is_dsa_8021q_cpu) { 2020 /* The DSA tag_8021q CPU ports need to be able to 2021 * forward packets to all other ports except for 2022 * themselves 2023 */ 2024 mask = GENMASK(ocelot->num_phys_ports - 1, 0); 2025 mask &= ~cpu_fwd_mask; 2026 } else if (ocelot_port->bridge) { 2027 struct net_device *bond = ocelot_port->bond; 2028 2029 mask = ocelot_get_bridge_fwd_mask(ocelot, port); 2030 mask |= cpu_fwd_mask; 2031 mask &= ~BIT(port); 2032 if (bond) 2033 mask &= ~ocelot_get_bond_mask(ocelot, bond); 2034 } else { 2035 /* Standalone ports forward only to DSA tag_8021q CPU 2036 * ports (if those exist), or to the hardware CPU port 2037 * module otherwise. 2038 */ 2039 mask = cpu_fwd_mask; 2040 } 2041 2042 ocelot_write_rix(ocelot, mask, ANA_PGID_PGID, PGID_SRC + port); 2043 } 2044 2045 /* If cut-through forwarding is supported and a port is leaving, there 2046 * is a chance that cut-through was disabled on the other ports due to 2047 * the port which is leaving (it has a higher link speed). We need to 2048 * update the cut-through masks of the remaining ports no earlier than 2049 * after the port has left, to prevent underruns from happening between 2050 * the cut-through update and the forwarding domain update. 2051 */ 2052 if (!joining && ocelot->ops->cut_through_fwd) 2053 ocelot->ops->cut_through_fwd(ocelot); 2054 } 2055 EXPORT_SYMBOL(ocelot_apply_bridge_fwd_mask); 2056 2057 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state) 2058 { 2059 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2060 u32 learn_ena = 0; 2061 2062 mutex_lock(&ocelot->fwd_domain_lock); 2063 2064 ocelot_port->stp_state = state; 2065 2066 if ((state == BR_STATE_LEARNING || state == BR_STATE_FORWARDING) && 2067 ocelot_port->learn_ena) 2068 learn_ena = ANA_PORT_PORT_CFG_LEARN_ENA; 2069 2070 ocelot_rmw_gix(ocelot, learn_ena, ANA_PORT_PORT_CFG_LEARN_ENA, 2071 ANA_PORT_PORT_CFG, port); 2072 2073 ocelot_apply_bridge_fwd_mask(ocelot, state == BR_STATE_FORWARDING); 2074 2075 mutex_unlock(&ocelot->fwd_domain_lock); 2076 } 2077 EXPORT_SYMBOL(ocelot_bridge_stp_state_set); 2078 2079 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs) 2080 { 2081 unsigned int age_period = ANA_AUTOAGE_AGE_PERIOD(msecs / 2000); 2082 2083 /* Setting AGE_PERIOD to zero effectively disables automatic aging, 2084 * which is clearly not what our intention is. So avoid that. 2085 */ 2086 if (!age_period) 2087 age_period = 1; 2088 2089 ocelot_rmw(ocelot, age_period, ANA_AUTOAGE_AGE_PERIOD_M, ANA_AUTOAGE); 2090 } 2091 EXPORT_SYMBOL(ocelot_set_ageing_time); 2092 2093 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot, 2094 const unsigned char *addr, 2095 u16 vid) 2096 { 2097 struct ocelot_multicast *mc; 2098 2099 list_for_each_entry(mc, &ocelot->multicast, list) { 2100 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid) 2101 return mc; 2102 } 2103 2104 return NULL; 2105 } 2106 2107 static enum macaccess_entry_type ocelot_classify_mdb(const unsigned char *addr) 2108 { 2109 if (addr[0] == 0x01 && addr[1] == 0x00 && addr[2] == 0x5e) 2110 return ENTRYTYPE_MACv4; 2111 if (addr[0] == 0x33 && addr[1] == 0x33) 2112 return ENTRYTYPE_MACv6; 2113 return ENTRYTYPE_LOCKED; 2114 } 2115 2116 static struct ocelot_pgid *ocelot_pgid_alloc(struct ocelot *ocelot, int index, 2117 unsigned long ports) 2118 { 2119 struct ocelot_pgid *pgid; 2120 2121 pgid = kzalloc(sizeof(*pgid), GFP_KERNEL); 2122 if (!pgid) 2123 return ERR_PTR(-ENOMEM); 2124 2125 pgid->ports = ports; 2126 pgid->index = index; 2127 refcount_set(&pgid->refcount, 1); 2128 list_add_tail(&pgid->list, &ocelot->pgids); 2129 2130 return pgid; 2131 } 2132 2133 static void ocelot_pgid_free(struct ocelot *ocelot, struct ocelot_pgid *pgid) 2134 { 2135 if (!refcount_dec_and_test(&pgid->refcount)) 2136 return; 2137 2138 list_del(&pgid->list); 2139 kfree(pgid); 2140 } 2141 2142 static struct ocelot_pgid *ocelot_mdb_get_pgid(struct ocelot *ocelot, 2143 const struct ocelot_multicast *mc) 2144 { 2145 struct ocelot_pgid *pgid; 2146 int index; 2147 2148 /* According to VSC7514 datasheet 3.9.1.5 IPv4 Multicast Entries and 2149 * 3.9.1.6 IPv6 Multicast Entries, "Instead of a lookup in the 2150 * destination mask table (PGID), the destination set is programmed as 2151 * part of the entry MAC address.", and the DEST_IDX is set to 0. 2152 */ 2153 if (mc->entry_type == ENTRYTYPE_MACv4 || 2154 mc->entry_type == ENTRYTYPE_MACv6) 2155 return ocelot_pgid_alloc(ocelot, 0, mc->ports); 2156 2157 list_for_each_entry(pgid, &ocelot->pgids, list) { 2158 /* When searching for a nonreserved multicast PGID, ignore the 2159 * dummy PGID of zero that we have for MACv4/MACv6 entries 2160 */ 2161 if (pgid->index && pgid->ports == mc->ports) { 2162 refcount_inc(&pgid->refcount); 2163 return pgid; 2164 } 2165 } 2166 2167 /* Search for a free index in the nonreserved multicast PGID area */ 2168 for_each_nonreserved_multicast_dest_pgid(ocelot, index) { 2169 bool used = false; 2170 2171 list_for_each_entry(pgid, &ocelot->pgids, list) { 2172 if (pgid->index == index) { 2173 used = true; 2174 break; 2175 } 2176 } 2177 2178 if (!used) 2179 return ocelot_pgid_alloc(ocelot, index, mc->ports); 2180 } 2181 2182 return ERR_PTR(-ENOSPC); 2183 } 2184 2185 static void ocelot_encode_ports_to_mdb(unsigned char *addr, 2186 struct ocelot_multicast *mc) 2187 { 2188 ether_addr_copy(addr, mc->addr); 2189 2190 if (mc->entry_type == ENTRYTYPE_MACv4) { 2191 addr[0] = 0; 2192 addr[1] = mc->ports >> 8; 2193 addr[2] = mc->ports & 0xff; 2194 } else if (mc->entry_type == ENTRYTYPE_MACv6) { 2195 addr[0] = mc->ports >> 8; 2196 addr[1] = mc->ports & 0xff; 2197 } 2198 } 2199 2200 int ocelot_port_mdb_add(struct ocelot *ocelot, int port, 2201 const struct switchdev_obj_port_mdb *mdb) 2202 { 2203 unsigned char addr[ETH_ALEN]; 2204 struct ocelot_multicast *mc; 2205 struct ocelot_pgid *pgid; 2206 u16 vid = mdb->vid; 2207 2208 if (port == ocelot->npi) 2209 port = ocelot->num_phys_ports; 2210 2211 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 2212 if (!mc) { 2213 /* New entry */ 2214 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL); 2215 if (!mc) 2216 return -ENOMEM; 2217 2218 mc->entry_type = ocelot_classify_mdb(mdb->addr); 2219 ether_addr_copy(mc->addr, mdb->addr); 2220 mc->vid = vid; 2221 2222 list_add_tail(&mc->list, &ocelot->multicast); 2223 } else { 2224 /* Existing entry. Clean up the current port mask from 2225 * hardware now, because we'll be modifying it. 2226 */ 2227 ocelot_pgid_free(ocelot, mc->pgid); 2228 ocelot_encode_ports_to_mdb(addr, mc); 2229 ocelot_mact_forget(ocelot, addr, vid); 2230 } 2231 2232 mc->ports |= BIT(port); 2233 2234 pgid = ocelot_mdb_get_pgid(ocelot, mc); 2235 if (IS_ERR(pgid)) { 2236 dev_err(ocelot->dev, 2237 "Cannot allocate PGID for mdb %pM vid %d\n", 2238 mc->addr, mc->vid); 2239 devm_kfree(ocelot->dev, mc); 2240 return PTR_ERR(pgid); 2241 } 2242 mc->pgid = pgid; 2243 2244 ocelot_encode_ports_to_mdb(addr, mc); 2245 2246 if (mc->entry_type != ENTRYTYPE_MACv4 && 2247 mc->entry_type != ENTRYTYPE_MACv6) 2248 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 2249 pgid->index); 2250 2251 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 2252 mc->entry_type); 2253 } 2254 EXPORT_SYMBOL(ocelot_port_mdb_add); 2255 2256 int ocelot_port_mdb_del(struct ocelot *ocelot, int port, 2257 const struct switchdev_obj_port_mdb *mdb) 2258 { 2259 unsigned char addr[ETH_ALEN]; 2260 struct ocelot_multicast *mc; 2261 struct ocelot_pgid *pgid; 2262 u16 vid = mdb->vid; 2263 2264 if (port == ocelot->npi) 2265 port = ocelot->num_phys_ports; 2266 2267 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 2268 if (!mc) 2269 return -ENOENT; 2270 2271 ocelot_encode_ports_to_mdb(addr, mc); 2272 ocelot_mact_forget(ocelot, addr, vid); 2273 2274 ocelot_pgid_free(ocelot, mc->pgid); 2275 mc->ports &= ~BIT(port); 2276 if (!mc->ports) { 2277 list_del(&mc->list); 2278 devm_kfree(ocelot->dev, mc); 2279 return 0; 2280 } 2281 2282 /* We have a PGID with fewer ports now */ 2283 pgid = ocelot_mdb_get_pgid(ocelot, mc); 2284 if (IS_ERR(pgid)) 2285 return PTR_ERR(pgid); 2286 mc->pgid = pgid; 2287 2288 ocelot_encode_ports_to_mdb(addr, mc); 2289 2290 if (mc->entry_type != ENTRYTYPE_MACv4 && 2291 mc->entry_type != ENTRYTYPE_MACv6) 2292 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID, 2293 pgid->index); 2294 2295 return ocelot_mact_learn(ocelot, pgid->index, addr, vid, 2296 mc->entry_type); 2297 } 2298 EXPORT_SYMBOL(ocelot_port_mdb_del); 2299 2300 void ocelot_port_bridge_join(struct ocelot *ocelot, int port, 2301 struct net_device *bridge) 2302 { 2303 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2304 2305 mutex_lock(&ocelot->fwd_domain_lock); 2306 2307 ocelot_port->bridge = bridge; 2308 2309 ocelot_apply_bridge_fwd_mask(ocelot, true); 2310 2311 mutex_unlock(&ocelot->fwd_domain_lock); 2312 } 2313 EXPORT_SYMBOL(ocelot_port_bridge_join); 2314 2315 void ocelot_port_bridge_leave(struct ocelot *ocelot, int port, 2316 struct net_device *bridge) 2317 { 2318 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2319 2320 mutex_lock(&ocelot->fwd_domain_lock); 2321 2322 ocelot_port->bridge = NULL; 2323 2324 ocelot_port_set_pvid(ocelot, port, NULL); 2325 ocelot_port_manage_port_tag(ocelot, port); 2326 ocelot_apply_bridge_fwd_mask(ocelot, false); 2327 2328 mutex_unlock(&ocelot->fwd_domain_lock); 2329 } 2330 EXPORT_SYMBOL(ocelot_port_bridge_leave); 2331 2332 static void ocelot_set_aggr_pgids(struct ocelot *ocelot) 2333 { 2334 unsigned long visited = GENMASK(ocelot->num_phys_ports - 1, 0); 2335 int i, port, lag; 2336 2337 /* Reset destination and aggregation PGIDS */ 2338 for_each_unicast_dest_pgid(ocelot, port) 2339 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 2340 2341 for_each_aggr_pgid(ocelot, i) 2342 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 2343 ANA_PGID_PGID, i); 2344 2345 /* The visited ports bitmask holds the list of ports offloading any 2346 * bonding interface. Initially we mark all these ports as unvisited, 2347 * then every time we visit a port in this bitmask, we know that it is 2348 * the lowest numbered port, i.e. the one whose logical ID == physical 2349 * port ID == LAG ID. So we mark as visited all further ports in the 2350 * bitmask that are offloading the same bonding interface. This way, 2351 * we set up the aggregation PGIDs only once per bonding interface. 2352 */ 2353 for (port = 0; port < ocelot->num_phys_ports; port++) { 2354 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2355 2356 if (!ocelot_port || !ocelot_port->bond) 2357 continue; 2358 2359 visited &= ~BIT(port); 2360 } 2361 2362 /* Now, set PGIDs for each active LAG */ 2363 for (lag = 0; lag < ocelot->num_phys_ports; lag++) { 2364 struct net_device *bond = ocelot->ports[lag]->bond; 2365 int num_active_ports = 0; 2366 unsigned long bond_mask; 2367 u8 aggr_idx[16]; 2368 2369 if (!bond || (visited & BIT(lag))) 2370 continue; 2371 2372 bond_mask = ocelot_get_bond_mask(ocelot, bond); 2373 2374 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) { 2375 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2376 2377 // Destination mask 2378 ocelot_write_rix(ocelot, bond_mask, 2379 ANA_PGID_PGID, port); 2380 2381 if (ocelot_port->lag_tx_active) 2382 aggr_idx[num_active_ports++] = port; 2383 } 2384 2385 for_each_aggr_pgid(ocelot, i) { 2386 u32 ac; 2387 2388 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i); 2389 ac &= ~bond_mask; 2390 /* Don't do division by zero if there was no active 2391 * port. Just make all aggregation codes zero. 2392 */ 2393 if (num_active_ports) 2394 ac |= BIT(aggr_idx[i % num_active_ports]); 2395 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i); 2396 } 2397 2398 /* Mark all ports in the same LAG as visited to avoid applying 2399 * the same config again. 2400 */ 2401 for (port = lag; port < ocelot->num_phys_ports; port++) { 2402 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2403 2404 if (!ocelot_port) 2405 continue; 2406 2407 if (ocelot_port->bond == bond) 2408 visited |= BIT(port); 2409 } 2410 } 2411 } 2412 2413 /* When offloading a bonding interface, the switch ports configured under the 2414 * same bond must have the same logical port ID, equal to the physical port ID 2415 * of the lowest numbered physical port in that bond. Otherwise, in standalone/ 2416 * bridged mode, each port has a logical port ID equal to its physical port ID. 2417 */ 2418 static void ocelot_setup_logical_port_ids(struct ocelot *ocelot) 2419 { 2420 int port; 2421 2422 for (port = 0; port < ocelot->num_phys_ports; port++) { 2423 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2424 struct net_device *bond; 2425 2426 if (!ocelot_port) 2427 continue; 2428 2429 bond = ocelot_port->bond; 2430 if (bond) { 2431 int lag = ocelot_bond_get_id(ocelot, bond); 2432 2433 ocelot_rmw_gix(ocelot, 2434 ANA_PORT_PORT_CFG_PORTID_VAL(lag), 2435 ANA_PORT_PORT_CFG_PORTID_VAL_M, 2436 ANA_PORT_PORT_CFG, port); 2437 } else { 2438 ocelot_rmw_gix(ocelot, 2439 ANA_PORT_PORT_CFG_PORTID_VAL(port), 2440 ANA_PORT_PORT_CFG_PORTID_VAL_M, 2441 ANA_PORT_PORT_CFG, port); 2442 } 2443 } 2444 } 2445 2446 /* Documentation for PORTID_VAL says: 2447 * Logical port number for front port. If port is not a member of a LLAG, 2448 * then PORTID must be set to the physical port number. 2449 * If port is a member of a LLAG, then PORTID must be set to the common 2450 * PORTID_VAL used for all member ports of the LLAG. 2451 * The value must not exceed the number of physical ports on the device. 2452 * 2453 * This means we have little choice but to migrate FDB entries pointing towards 2454 * a logical port when that changes. 2455 */ 2456 static void ocelot_migrate_lag_fdbs(struct ocelot *ocelot, 2457 struct net_device *bond, 2458 int lag) 2459 { 2460 struct ocelot_lag_fdb *fdb; 2461 int err; 2462 2463 lockdep_assert_held(&ocelot->fwd_domain_lock); 2464 2465 list_for_each_entry(fdb, &ocelot->lag_fdbs, list) { 2466 if (fdb->bond != bond) 2467 continue; 2468 2469 err = ocelot_mact_forget(ocelot, fdb->addr, fdb->vid); 2470 if (err) { 2471 dev_err(ocelot->dev, 2472 "failed to delete LAG %s FDB %pM vid %d: %pe\n", 2473 bond->name, fdb->addr, fdb->vid, ERR_PTR(err)); 2474 } 2475 2476 err = ocelot_mact_learn(ocelot, lag, fdb->addr, fdb->vid, 2477 ENTRYTYPE_LOCKED); 2478 if (err) { 2479 dev_err(ocelot->dev, 2480 "failed to migrate LAG %s FDB %pM vid %d: %pe\n", 2481 bond->name, fdb->addr, fdb->vid, ERR_PTR(err)); 2482 } 2483 } 2484 } 2485 2486 int ocelot_port_lag_join(struct ocelot *ocelot, int port, 2487 struct net_device *bond, 2488 struct netdev_lag_upper_info *info) 2489 { 2490 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) 2491 return -EOPNOTSUPP; 2492 2493 mutex_lock(&ocelot->fwd_domain_lock); 2494 2495 ocelot->ports[port]->bond = bond; 2496 2497 ocelot_setup_logical_port_ids(ocelot); 2498 ocelot_apply_bridge_fwd_mask(ocelot, true); 2499 ocelot_set_aggr_pgids(ocelot); 2500 2501 mutex_unlock(&ocelot->fwd_domain_lock); 2502 2503 return 0; 2504 } 2505 EXPORT_SYMBOL(ocelot_port_lag_join); 2506 2507 void ocelot_port_lag_leave(struct ocelot *ocelot, int port, 2508 struct net_device *bond) 2509 { 2510 int old_lag_id, new_lag_id; 2511 2512 mutex_lock(&ocelot->fwd_domain_lock); 2513 2514 old_lag_id = ocelot_bond_get_id(ocelot, bond); 2515 2516 ocelot->ports[port]->bond = NULL; 2517 2518 ocelot_setup_logical_port_ids(ocelot); 2519 ocelot_apply_bridge_fwd_mask(ocelot, false); 2520 ocelot_set_aggr_pgids(ocelot); 2521 2522 new_lag_id = ocelot_bond_get_id(ocelot, bond); 2523 2524 if (new_lag_id >= 0 && old_lag_id != new_lag_id) 2525 ocelot_migrate_lag_fdbs(ocelot, bond, new_lag_id); 2526 2527 mutex_unlock(&ocelot->fwd_domain_lock); 2528 } 2529 EXPORT_SYMBOL(ocelot_port_lag_leave); 2530 2531 void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active) 2532 { 2533 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2534 2535 mutex_lock(&ocelot->fwd_domain_lock); 2536 2537 ocelot_port->lag_tx_active = lag_tx_active; 2538 2539 /* Rebalance the LAGs */ 2540 ocelot_set_aggr_pgids(ocelot); 2541 2542 mutex_unlock(&ocelot->fwd_domain_lock); 2543 } 2544 EXPORT_SYMBOL(ocelot_port_lag_change); 2545 2546 int ocelot_lag_fdb_add(struct ocelot *ocelot, struct net_device *bond, 2547 const unsigned char *addr, u16 vid) 2548 { 2549 struct ocelot_lag_fdb *fdb; 2550 int lag, err; 2551 2552 fdb = kzalloc(sizeof(*fdb), GFP_KERNEL); 2553 if (!fdb) 2554 return -ENOMEM; 2555 2556 ether_addr_copy(fdb->addr, addr); 2557 fdb->vid = vid; 2558 fdb->bond = bond; 2559 2560 mutex_lock(&ocelot->fwd_domain_lock); 2561 lag = ocelot_bond_get_id(ocelot, bond); 2562 2563 err = ocelot_mact_learn(ocelot, lag, addr, vid, ENTRYTYPE_LOCKED); 2564 if (err) { 2565 mutex_unlock(&ocelot->fwd_domain_lock); 2566 kfree(fdb); 2567 return err; 2568 } 2569 2570 list_add_tail(&fdb->list, &ocelot->lag_fdbs); 2571 mutex_unlock(&ocelot->fwd_domain_lock); 2572 2573 return 0; 2574 } 2575 EXPORT_SYMBOL_GPL(ocelot_lag_fdb_add); 2576 2577 int ocelot_lag_fdb_del(struct ocelot *ocelot, struct net_device *bond, 2578 const unsigned char *addr, u16 vid) 2579 { 2580 struct ocelot_lag_fdb *fdb, *tmp; 2581 2582 mutex_lock(&ocelot->fwd_domain_lock); 2583 2584 list_for_each_entry_safe(fdb, tmp, &ocelot->lag_fdbs, list) { 2585 if (!ether_addr_equal(fdb->addr, addr) || fdb->vid != vid || 2586 fdb->bond != bond) 2587 continue; 2588 2589 ocelot_mact_forget(ocelot, addr, vid); 2590 list_del(&fdb->list); 2591 mutex_unlock(&ocelot->fwd_domain_lock); 2592 kfree(fdb); 2593 2594 return 0; 2595 } 2596 2597 mutex_unlock(&ocelot->fwd_domain_lock); 2598 2599 return -ENOENT; 2600 } 2601 EXPORT_SYMBOL_GPL(ocelot_lag_fdb_del); 2602 2603 /* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu. 2604 * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG. 2605 * In the special case that it's the NPI port that we're configuring, the 2606 * length of the tag and optional prefix needs to be accounted for privately, 2607 * in order to be able to sustain communication at the requested @sdu. 2608 */ 2609 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu) 2610 { 2611 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2612 int maxlen = sdu + ETH_HLEN + ETH_FCS_LEN; 2613 int pause_start, pause_stop; 2614 int atop, atop_tot; 2615 2616 if (port == ocelot->npi) { 2617 maxlen += OCELOT_TAG_LEN; 2618 2619 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT) 2620 maxlen += OCELOT_SHORT_PREFIX_LEN; 2621 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG) 2622 maxlen += OCELOT_LONG_PREFIX_LEN; 2623 } 2624 2625 ocelot_port_writel(ocelot_port, maxlen, DEV_MAC_MAXLEN_CFG); 2626 2627 /* Set Pause watermark hysteresis */ 2628 pause_start = 6 * maxlen / OCELOT_BUFFER_CELL_SZ; 2629 pause_stop = 4 * maxlen / OCELOT_BUFFER_CELL_SZ; 2630 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_START, 2631 pause_start); 2632 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_STOP, 2633 pause_stop); 2634 2635 /* Tail dropping watermarks */ 2636 atop_tot = (ocelot->packet_buffer_size - 9 * maxlen) / 2637 OCELOT_BUFFER_CELL_SZ; 2638 atop = (9 * maxlen) / OCELOT_BUFFER_CELL_SZ; 2639 ocelot_write_rix(ocelot, ocelot->ops->wm_enc(atop), SYS_ATOP, port); 2640 ocelot_write(ocelot, ocelot->ops->wm_enc(atop_tot), SYS_ATOP_TOT_CFG); 2641 } 2642 EXPORT_SYMBOL(ocelot_port_set_maxlen); 2643 2644 int ocelot_get_max_mtu(struct ocelot *ocelot, int port) 2645 { 2646 int max_mtu = 65535 - ETH_HLEN - ETH_FCS_LEN; 2647 2648 if (port == ocelot->npi) { 2649 max_mtu -= OCELOT_TAG_LEN; 2650 2651 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT) 2652 max_mtu -= OCELOT_SHORT_PREFIX_LEN; 2653 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG) 2654 max_mtu -= OCELOT_LONG_PREFIX_LEN; 2655 } 2656 2657 return max_mtu; 2658 } 2659 EXPORT_SYMBOL(ocelot_get_max_mtu); 2660 2661 static void ocelot_port_set_learning(struct ocelot *ocelot, int port, 2662 bool enabled) 2663 { 2664 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2665 u32 val = 0; 2666 2667 if (enabled) 2668 val = ANA_PORT_PORT_CFG_LEARN_ENA; 2669 2670 ocelot_rmw_gix(ocelot, val, ANA_PORT_PORT_CFG_LEARN_ENA, 2671 ANA_PORT_PORT_CFG, port); 2672 2673 ocelot_port->learn_ena = enabled; 2674 } 2675 2676 static void ocelot_port_set_ucast_flood(struct ocelot *ocelot, int port, 2677 bool enabled) 2678 { 2679 u32 val = 0; 2680 2681 if (enabled) 2682 val = BIT(port); 2683 2684 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_UC); 2685 } 2686 2687 static void ocelot_port_set_mcast_flood(struct ocelot *ocelot, int port, 2688 bool enabled) 2689 { 2690 u32 val = 0; 2691 2692 if (enabled) 2693 val = BIT(port); 2694 2695 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MC); 2696 } 2697 2698 static void ocelot_port_set_bcast_flood(struct ocelot *ocelot, int port, 2699 bool enabled) 2700 { 2701 u32 val = 0; 2702 2703 if (enabled) 2704 val = BIT(port); 2705 2706 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_BC); 2707 } 2708 2709 int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port, 2710 struct switchdev_brport_flags flags) 2711 { 2712 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 2713 BR_BCAST_FLOOD)) 2714 return -EINVAL; 2715 2716 return 0; 2717 } 2718 EXPORT_SYMBOL(ocelot_port_pre_bridge_flags); 2719 2720 void ocelot_port_bridge_flags(struct ocelot *ocelot, int port, 2721 struct switchdev_brport_flags flags) 2722 { 2723 if (flags.mask & BR_LEARNING) 2724 ocelot_port_set_learning(ocelot, port, 2725 !!(flags.val & BR_LEARNING)); 2726 2727 if (flags.mask & BR_FLOOD) 2728 ocelot_port_set_ucast_flood(ocelot, port, 2729 !!(flags.val & BR_FLOOD)); 2730 2731 if (flags.mask & BR_MCAST_FLOOD) 2732 ocelot_port_set_mcast_flood(ocelot, port, 2733 !!(flags.val & BR_MCAST_FLOOD)); 2734 2735 if (flags.mask & BR_BCAST_FLOOD) 2736 ocelot_port_set_bcast_flood(ocelot, port, 2737 !!(flags.val & BR_BCAST_FLOOD)); 2738 } 2739 EXPORT_SYMBOL(ocelot_port_bridge_flags); 2740 2741 void ocelot_init_port(struct ocelot *ocelot, int port) 2742 { 2743 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2744 2745 skb_queue_head_init(&ocelot_port->tx_skbs); 2746 2747 /* Basic L2 initialization */ 2748 2749 /* Set MAC IFG Gaps 2750 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0 2751 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5 2752 */ 2753 ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5), 2754 DEV_MAC_IFG_CFG); 2755 2756 /* Load seed (0) and set MAC HDX late collision */ 2757 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) | 2758 DEV_MAC_HDX_CFG_SEED_LOAD, 2759 DEV_MAC_HDX_CFG); 2760 mdelay(1); 2761 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67), 2762 DEV_MAC_HDX_CFG); 2763 2764 /* Set Max Length and maximum tags allowed */ 2765 ocelot_port_set_maxlen(ocelot, port, ETH_DATA_LEN); 2766 ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) | 2767 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA | 2768 DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA | 2769 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, 2770 DEV_MAC_TAGS_CFG); 2771 2772 /* Set SMAC of Pause frame (00:00:00:00:00:00) */ 2773 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG); 2774 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG); 2775 2776 /* Enable transmission of pause frames */ 2777 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1); 2778 2779 /* Drop frames with multicast source address */ 2780 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 2781 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 2782 ANA_PORT_DROP_CFG, port); 2783 2784 /* Set default VLAN and tag type to 8021Q. */ 2785 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q), 2786 REW_PORT_VLAN_CFG_PORT_TPID_M, 2787 REW_PORT_VLAN_CFG, port); 2788 2789 /* Disable source address learning for standalone mode */ 2790 ocelot_port_set_learning(ocelot, port, false); 2791 2792 /* Set the port's initial logical port ID value, enable receiving 2793 * frames on it, and configure the MAC address learning type to 2794 * automatic. 2795 */ 2796 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO | 2797 ANA_PORT_PORT_CFG_RECV_ENA | 2798 ANA_PORT_PORT_CFG_PORTID_VAL(port), 2799 ANA_PORT_PORT_CFG, port); 2800 2801 /* Enable vcap lookups */ 2802 ocelot_vcap_enable(ocelot, port); 2803 } 2804 EXPORT_SYMBOL(ocelot_init_port); 2805 2806 /* Configure and enable the CPU port module, which is a set of queues 2807 * accessible through register MMIO, frame DMA or Ethernet (in case 2808 * NPI mode is used). 2809 */ 2810 static void ocelot_cpu_port_init(struct ocelot *ocelot) 2811 { 2812 int cpu = ocelot->num_phys_ports; 2813 2814 /* The unicast destination PGID for the CPU port module is unused */ 2815 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu); 2816 /* Instead set up a multicast destination PGID for traffic copied to 2817 * the CPU. Whitelisted MAC addresses like the port netdevice MAC 2818 * addresses will be copied to the CPU via this PGID. 2819 */ 2820 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU); 2821 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA | 2822 ANA_PORT_PORT_CFG_PORTID_VAL(cpu), 2823 ANA_PORT_PORT_CFG, cpu); 2824 2825 /* Enable CPU port module */ 2826 ocelot_fields_write(ocelot, cpu, QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 2827 /* CPU port Injection/Extraction configuration */ 2828 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_XTR_HDR, 2829 OCELOT_TAG_PREFIX_NONE); 2830 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_INJ_HDR, 2831 OCELOT_TAG_PREFIX_NONE); 2832 2833 /* Configure the CPU port to be VLAN aware */ 2834 ocelot_write_gix(ocelot, 2835 ANA_PORT_VLAN_CFG_VLAN_VID(OCELOT_VLAN_UNAWARE_PVID) | 2836 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 2837 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1), 2838 ANA_PORT_VLAN_CFG, cpu); 2839 } 2840 2841 static void ocelot_detect_features(struct ocelot *ocelot) 2842 { 2843 int mmgt, eq_ctrl; 2844 2845 /* For Ocelot, Felix, Seville, Serval etc, SYS:MMGT:MMGT:FREECNT holds 2846 * the number of 240-byte free memory words (aka 4-cell chunks) and not 2847 * 192 bytes as the documentation incorrectly says. 2848 */ 2849 mmgt = ocelot_read(ocelot, SYS_MMGT); 2850 ocelot->packet_buffer_size = 240 * SYS_MMGT_FREECNT(mmgt); 2851 2852 eq_ctrl = ocelot_read(ocelot, QSYS_EQ_CTRL); 2853 ocelot->num_frame_refs = QSYS_MMGT_EQ_CTRL_FP_FREE_CNT(eq_ctrl); 2854 } 2855 2856 int ocelot_init(struct ocelot *ocelot) 2857 { 2858 char queue_name[32]; 2859 int i, ret; 2860 u32 port; 2861 2862 if (ocelot->ops->reset) { 2863 ret = ocelot->ops->reset(ocelot); 2864 if (ret) { 2865 dev_err(ocelot->dev, "Switch reset failed\n"); 2866 return ret; 2867 } 2868 } 2869 2870 ocelot->stats = devm_kcalloc(ocelot->dev, 2871 ocelot->num_phys_ports * ocelot->num_stats, 2872 sizeof(u64), GFP_KERNEL); 2873 if (!ocelot->stats) 2874 return -ENOMEM; 2875 2876 mutex_init(&ocelot->stats_lock); 2877 mutex_init(&ocelot->ptp_lock); 2878 mutex_init(&ocelot->mact_lock); 2879 mutex_init(&ocelot->fwd_domain_lock); 2880 spin_lock_init(&ocelot->ptp_clock_lock); 2881 spin_lock_init(&ocelot->ts_id_lock); 2882 snprintf(queue_name, sizeof(queue_name), "%s-stats", 2883 dev_name(ocelot->dev)); 2884 ocelot->stats_queue = create_singlethread_workqueue(queue_name); 2885 if (!ocelot->stats_queue) 2886 return -ENOMEM; 2887 2888 ocelot->owq = alloc_ordered_workqueue("ocelot-owq", 0); 2889 if (!ocelot->owq) { 2890 destroy_workqueue(ocelot->stats_queue); 2891 return -ENOMEM; 2892 } 2893 2894 INIT_LIST_HEAD(&ocelot->multicast); 2895 INIT_LIST_HEAD(&ocelot->pgids); 2896 INIT_LIST_HEAD(&ocelot->vlans); 2897 INIT_LIST_HEAD(&ocelot->lag_fdbs); 2898 ocelot_detect_features(ocelot); 2899 ocelot_mact_init(ocelot); 2900 ocelot_vlan_init(ocelot); 2901 ocelot_vcap_init(ocelot); 2902 ocelot_cpu_port_init(ocelot); 2903 2904 if (ocelot->ops->psfp_init) 2905 ocelot->ops->psfp_init(ocelot); 2906 2907 for (port = 0; port < ocelot->num_phys_ports; port++) { 2908 /* Clear all counters (5 groups) */ 2909 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) | 2910 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f), 2911 SYS_STAT_CFG); 2912 } 2913 2914 /* Only use S-Tag */ 2915 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG); 2916 2917 /* Aggregation mode */ 2918 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA | 2919 ANA_AGGR_CFG_AC_DMAC_ENA | 2920 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA | 2921 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA | 2922 ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA | 2923 ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA, 2924 ANA_AGGR_CFG); 2925 2926 /* Set MAC age time to default value. The entry is aged after 2927 * 2*AGE_PERIOD 2928 */ 2929 ocelot_write(ocelot, 2930 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ), 2931 ANA_AUTOAGE); 2932 2933 /* Disable learning for frames discarded by VLAN ingress filtering */ 2934 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1); 2935 2936 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */ 2937 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA | 2938 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING); 2939 2940 /* Setup flooding PGIDs */ 2941 for (i = 0; i < ocelot->num_flooding_pgids; i++) 2942 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) | 2943 ANA_FLOODING_FLD_BROADCAST(PGID_BC) | 2944 ANA_FLOODING_FLD_UNICAST(PGID_UC), 2945 ANA_FLOODING, i); 2946 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) | 2947 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) | 2948 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) | 2949 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC), 2950 ANA_FLOODING_IPMC); 2951 2952 for (port = 0; port < ocelot->num_phys_ports; port++) { 2953 /* Transmit the frame to the local port. */ 2954 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 2955 /* Do not forward BPDU frames to the front ports. */ 2956 ocelot_write_gix(ocelot, 2957 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff), 2958 ANA_PORT_CPU_FWD_BPDU_CFG, 2959 port); 2960 /* Ensure bridging is disabled */ 2961 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port); 2962 } 2963 2964 for_each_nonreserved_multicast_dest_pgid(ocelot, i) { 2965 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0)); 2966 2967 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 2968 } 2969 2970 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_BLACKHOLE); 2971 2972 /* Allow broadcast and unknown L2 multicast to the CPU. */ 2973 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2974 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2975 ANA_PGID_PGID, PGID_MC); 2976 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2977 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)), 2978 ANA_PGID_PGID, PGID_BC); 2979 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4); 2980 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6); 2981 2982 /* Allow manual injection via DEVCPU_QS registers, and byte swap these 2983 * registers endianness. 2984 */ 2985 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP | 2986 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0); 2987 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP | 2988 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0); 2989 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) | 2990 ANA_CPUQ_CFG_CPUQ_LRN(2) | 2991 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) | 2992 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) | 2993 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) | 2994 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) | 2995 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) | 2996 ANA_CPUQ_CFG_CPUQ_IGMP(6) | 2997 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG); 2998 for (i = 0; i < 16; i++) 2999 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) | 3000 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6), 3001 ANA_CPUQ_8021_CFG, i); 3002 3003 ret = ocelot_prepare_stats_regions(ocelot); 3004 if (ret) { 3005 destroy_workqueue(ocelot->stats_queue); 3006 destroy_workqueue(ocelot->owq); 3007 return ret; 3008 } 3009 3010 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats_work); 3011 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 3012 OCELOT_STATS_CHECK_DELAY); 3013 3014 return 0; 3015 } 3016 EXPORT_SYMBOL(ocelot_init); 3017 3018 void ocelot_deinit(struct ocelot *ocelot) 3019 { 3020 cancel_delayed_work(&ocelot->stats_work); 3021 destroy_workqueue(ocelot->stats_queue); 3022 destroy_workqueue(ocelot->owq); 3023 mutex_destroy(&ocelot->stats_lock); 3024 } 3025 EXPORT_SYMBOL(ocelot_deinit); 3026 3027 void ocelot_deinit_port(struct ocelot *ocelot, int port) 3028 { 3029 struct ocelot_port *ocelot_port = ocelot->ports[port]; 3030 3031 skb_queue_purge(&ocelot_port->tx_skbs); 3032 } 3033 EXPORT_SYMBOL(ocelot_deinit_port); 3034 3035 MODULE_LICENSE("Dual MIT/GPL"); 3036