1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright (c) 2021, Microsoft Corporation. */ 3 4 #include <linux/debugfs.h> 5 #include <linux/module.h> 6 #include <linux/pci.h> 7 #include <linux/utsname.h> 8 #include <linux/version.h> 9 10 #include <net/mana/mana.h> 11 12 struct dentry *mana_debugfs_root; 13 14 static u32 mana_gd_r32(struct gdma_context *g, u64 offset) 15 { 16 return readl(g->bar0_va + offset); 17 } 18 19 static u64 mana_gd_r64(struct gdma_context *g, u64 offset) 20 { 21 return readq(g->bar0_va + offset); 22 } 23 24 static void mana_gd_init_pf_regs(struct pci_dev *pdev) 25 { 26 struct gdma_context *gc = pci_get_drvdata(pdev); 27 void __iomem *sriov_base_va; 28 u64 sriov_base_off; 29 30 gc->db_page_size = mana_gd_r32(gc, GDMA_PF_REG_DB_PAGE_SIZE) & 0xFFFF; 31 gc->db_page_base = gc->bar0_va + 32 mana_gd_r64(gc, GDMA_PF_REG_DB_PAGE_OFF); 33 34 sriov_base_off = mana_gd_r64(gc, GDMA_SRIOV_REG_CFG_BASE_OFF); 35 36 sriov_base_va = gc->bar0_va + sriov_base_off; 37 gc->shm_base = sriov_base_va + 38 mana_gd_r64(gc, sriov_base_off + GDMA_PF_REG_SHM_OFF); 39 } 40 41 static void mana_gd_init_vf_regs(struct pci_dev *pdev) 42 { 43 struct gdma_context *gc = pci_get_drvdata(pdev); 44 45 gc->db_page_size = mana_gd_r32(gc, GDMA_REG_DB_PAGE_SIZE) & 0xFFFF; 46 47 gc->db_page_base = gc->bar0_va + 48 mana_gd_r64(gc, GDMA_REG_DB_PAGE_OFFSET); 49 50 gc->phys_db_page_base = gc->bar0_pa + 51 mana_gd_r64(gc, GDMA_REG_DB_PAGE_OFFSET); 52 53 gc->shm_base = gc->bar0_va + mana_gd_r64(gc, GDMA_REG_SHM_OFFSET); 54 } 55 56 static void mana_gd_init_registers(struct pci_dev *pdev) 57 { 58 struct gdma_context *gc = pci_get_drvdata(pdev); 59 60 if (gc->is_pf) 61 mana_gd_init_pf_regs(pdev); 62 else 63 mana_gd_init_vf_regs(pdev); 64 } 65 66 static int mana_gd_query_max_resources(struct pci_dev *pdev) 67 { 68 struct gdma_context *gc = pci_get_drvdata(pdev); 69 struct gdma_query_max_resources_resp resp = {}; 70 struct gdma_general_req req = {}; 71 int err; 72 73 mana_gd_init_req_hdr(&req.hdr, GDMA_QUERY_MAX_RESOURCES, 74 sizeof(req), sizeof(resp)); 75 76 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 77 if (err || resp.hdr.status) { 78 dev_err(gc->dev, "Failed to query resource info: %d, 0x%x\n", 79 err, resp.hdr.status); 80 return err ? err : -EPROTO; 81 } 82 83 if (gc->num_msix_usable > resp.max_msix) 84 gc->num_msix_usable = resp.max_msix; 85 86 if (gc->num_msix_usable <= 1) 87 return -ENOSPC; 88 89 gc->max_num_queues = num_online_cpus(); 90 if (gc->max_num_queues > MANA_MAX_NUM_QUEUES) 91 gc->max_num_queues = MANA_MAX_NUM_QUEUES; 92 93 if (gc->max_num_queues > resp.max_eq) 94 gc->max_num_queues = resp.max_eq; 95 96 if (gc->max_num_queues > resp.max_cq) 97 gc->max_num_queues = resp.max_cq; 98 99 if (gc->max_num_queues > resp.max_sq) 100 gc->max_num_queues = resp.max_sq; 101 102 if (gc->max_num_queues > resp.max_rq) 103 gc->max_num_queues = resp.max_rq; 104 105 /* The Hardware Channel (HWC) used 1 MSI-X */ 106 if (gc->max_num_queues > gc->num_msix_usable - 1) 107 gc->max_num_queues = gc->num_msix_usable - 1; 108 109 return 0; 110 } 111 112 static int mana_gd_query_hwc_timeout(struct pci_dev *pdev, u32 *timeout_val) 113 { 114 struct gdma_context *gc = pci_get_drvdata(pdev); 115 struct gdma_query_hwc_timeout_resp resp = {}; 116 struct gdma_query_hwc_timeout_req req = {}; 117 int err; 118 119 mana_gd_init_req_hdr(&req.hdr, GDMA_QUERY_HWC_TIMEOUT, 120 sizeof(req), sizeof(resp)); 121 req.timeout_ms = *timeout_val; 122 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 123 if (err || resp.hdr.status) 124 return err ? err : -EPROTO; 125 126 *timeout_val = resp.timeout_ms; 127 128 return 0; 129 } 130 131 static int mana_gd_detect_devices(struct pci_dev *pdev) 132 { 133 struct gdma_context *gc = pci_get_drvdata(pdev); 134 struct gdma_list_devices_resp resp = {}; 135 struct gdma_general_req req = {}; 136 struct gdma_dev_id dev; 137 int found_dev = 0; 138 u16 dev_type; 139 int err; 140 u32 i; 141 142 mana_gd_init_req_hdr(&req.hdr, GDMA_LIST_DEVICES, sizeof(req), 143 sizeof(resp)); 144 145 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 146 if (err || resp.hdr.status) { 147 dev_err(gc->dev, "Failed to detect devices: %d, 0x%x\n", err, 148 resp.hdr.status); 149 return err ? err : -EPROTO; 150 } 151 152 for (i = 0; i < GDMA_DEV_LIST_SIZE && 153 found_dev < resp.num_of_devs; i++) { 154 dev = resp.devs[i]; 155 dev_type = dev.type; 156 157 /* Skip empty devices */ 158 if (dev.as_uint32 == 0) 159 continue; 160 161 found_dev++; 162 163 /* HWC is already detected in mana_hwc_create_channel(). */ 164 if (dev_type == GDMA_DEVICE_HWC) 165 continue; 166 167 if (dev_type == GDMA_DEVICE_MANA) { 168 gc->mana.gdma_context = gc; 169 gc->mana.dev_id = dev; 170 } else if (dev_type == GDMA_DEVICE_MANA_IB) { 171 gc->mana_ib.dev_id = dev; 172 gc->mana_ib.gdma_context = gc; 173 } 174 } 175 176 return gc->mana.dev_id.type == 0 ? -ENODEV : 0; 177 } 178 179 int mana_gd_send_request(struct gdma_context *gc, u32 req_len, const void *req, 180 u32 resp_len, void *resp) 181 { 182 struct hw_channel_context *hwc = gc->hwc.driver_data; 183 184 return mana_hwc_send_request(hwc, req_len, req, resp_len, resp); 185 } 186 EXPORT_SYMBOL_NS(mana_gd_send_request, "NET_MANA"); 187 188 int mana_gd_alloc_memory(struct gdma_context *gc, unsigned int length, 189 struct gdma_mem_info *gmi) 190 { 191 dma_addr_t dma_handle; 192 void *buf; 193 194 if (length < MANA_PAGE_SIZE || !is_power_of_2(length)) 195 return -EINVAL; 196 197 gmi->dev = gc->dev; 198 buf = dma_alloc_coherent(gmi->dev, length, &dma_handle, GFP_KERNEL); 199 if (!buf) 200 return -ENOMEM; 201 202 gmi->dma_handle = dma_handle; 203 gmi->virt_addr = buf; 204 gmi->length = length; 205 206 return 0; 207 } 208 209 void mana_gd_free_memory(struct gdma_mem_info *gmi) 210 { 211 dma_free_coherent(gmi->dev, gmi->length, gmi->virt_addr, 212 gmi->dma_handle); 213 } 214 215 static int mana_gd_create_hw_eq(struct gdma_context *gc, 216 struct gdma_queue *queue) 217 { 218 struct gdma_create_queue_resp resp = {}; 219 struct gdma_create_queue_req req = {}; 220 int err; 221 222 if (queue->type != GDMA_EQ) 223 return -EINVAL; 224 225 mana_gd_init_req_hdr(&req.hdr, GDMA_CREATE_QUEUE, 226 sizeof(req), sizeof(resp)); 227 228 req.hdr.dev_id = queue->gdma_dev->dev_id; 229 req.type = queue->type; 230 req.pdid = queue->gdma_dev->pdid; 231 req.doolbell_id = queue->gdma_dev->doorbell; 232 req.gdma_region = queue->mem_info.dma_region_handle; 233 req.queue_size = queue->queue_size; 234 req.log2_throttle_limit = queue->eq.log2_throttle_limit; 235 req.eq_pci_msix_index = queue->eq.msix_index; 236 237 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 238 if (err || resp.hdr.status) { 239 dev_err(gc->dev, "Failed to create queue: %d, 0x%x\n", err, 240 resp.hdr.status); 241 return err ? err : -EPROTO; 242 } 243 244 queue->id = resp.queue_index; 245 queue->eq.disable_needed = true; 246 queue->mem_info.dma_region_handle = GDMA_INVALID_DMA_REGION; 247 return 0; 248 } 249 250 static int mana_gd_disable_queue(struct gdma_queue *queue) 251 { 252 struct gdma_context *gc = queue->gdma_dev->gdma_context; 253 struct gdma_disable_queue_req req = {}; 254 struct gdma_general_resp resp = {}; 255 int err; 256 257 WARN_ON(queue->type != GDMA_EQ); 258 259 mana_gd_init_req_hdr(&req.hdr, GDMA_DISABLE_QUEUE, 260 sizeof(req), sizeof(resp)); 261 262 req.hdr.dev_id = queue->gdma_dev->dev_id; 263 req.type = queue->type; 264 req.queue_index = queue->id; 265 req.alloc_res_id_on_creation = 1; 266 267 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 268 if (err || resp.hdr.status) { 269 dev_err(gc->dev, "Failed to disable queue: %d, 0x%x\n", err, 270 resp.hdr.status); 271 return err ? err : -EPROTO; 272 } 273 274 return 0; 275 } 276 277 #define DOORBELL_OFFSET_SQ 0x0 278 #define DOORBELL_OFFSET_RQ 0x400 279 #define DOORBELL_OFFSET_CQ 0x800 280 #define DOORBELL_OFFSET_EQ 0xFF8 281 282 static void mana_gd_ring_doorbell(struct gdma_context *gc, u32 db_index, 283 enum gdma_queue_type q_type, u32 qid, 284 u32 tail_ptr, u8 num_req) 285 { 286 void __iomem *addr = gc->db_page_base + gc->db_page_size * db_index; 287 union gdma_doorbell_entry e = {}; 288 289 switch (q_type) { 290 case GDMA_EQ: 291 e.eq.id = qid; 292 e.eq.tail_ptr = tail_ptr; 293 e.eq.arm = num_req; 294 295 addr += DOORBELL_OFFSET_EQ; 296 break; 297 298 case GDMA_CQ: 299 e.cq.id = qid; 300 e.cq.tail_ptr = tail_ptr; 301 e.cq.arm = num_req; 302 303 addr += DOORBELL_OFFSET_CQ; 304 break; 305 306 case GDMA_RQ: 307 e.rq.id = qid; 308 e.rq.tail_ptr = tail_ptr; 309 e.rq.wqe_cnt = num_req; 310 311 addr += DOORBELL_OFFSET_RQ; 312 break; 313 314 case GDMA_SQ: 315 e.sq.id = qid; 316 e.sq.tail_ptr = tail_ptr; 317 318 addr += DOORBELL_OFFSET_SQ; 319 break; 320 321 default: 322 WARN_ON(1); 323 return; 324 } 325 326 /* Ensure all writes are done before ring doorbell */ 327 wmb(); 328 329 writeq(e.as_uint64, addr); 330 } 331 332 void mana_gd_wq_ring_doorbell(struct gdma_context *gc, struct gdma_queue *queue) 333 { 334 /* Hardware Spec specifies that software client should set 0 for 335 * wqe_cnt for Receive Queues. This value is not used in Send Queues. 336 */ 337 mana_gd_ring_doorbell(gc, queue->gdma_dev->doorbell, queue->type, 338 queue->id, queue->head * GDMA_WQE_BU_SIZE, 0); 339 } 340 341 void mana_gd_ring_cq(struct gdma_queue *cq, u8 arm_bit) 342 { 343 struct gdma_context *gc = cq->gdma_dev->gdma_context; 344 345 u32 num_cqe = cq->queue_size / GDMA_CQE_SIZE; 346 347 u32 head = cq->head % (num_cqe << GDMA_CQE_OWNER_BITS); 348 349 mana_gd_ring_doorbell(gc, cq->gdma_dev->doorbell, cq->type, cq->id, 350 head, arm_bit); 351 } 352 353 static void mana_gd_process_eqe(struct gdma_queue *eq) 354 { 355 u32 head = eq->head % (eq->queue_size / GDMA_EQE_SIZE); 356 struct gdma_context *gc = eq->gdma_dev->gdma_context; 357 struct gdma_eqe *eq_eqe_ptr = eq->queue_mem_ptr; 358 union gdma_eqe_info eqe_info; 359 enum gdma_eqe_type type; 360 struct gdma_event event; 361 struct gdma_queue *cq; 362 struct gdma_eqe *eqe; 363 u32 cq_id; 364 365 eqe = &eq_eqe_ptr[head]; 366 eqe_info.as_uint32 = eqe->eqe_info; 367 type = eqe_info.type; 368 369 switch (type) { 370 case GDMA_EQE_COMPLETION: 371 cq_id = eqe->details[0] & 0xFFFFFF; 372 if (WARN_ON_ONCE(cq_id >= gc->max_num_cqs)) 373 break; 374 375 cq = gc->cq_table[cq_id]; 376 if (WARN_ON_ONCE(!cq || cq->type != GDMA_CQ || cq->id != cq_id)) 377 break; 378 379 if (cq->cq.callback) 380 cq->cq.callback(cq->cq.context, cq); 381 382 break; 383 384 case GDMA_EQE_TEST_EVENT: 385 gc->test_event_eq_id = eq->id; 386 complete(&gc->eq_test_event); 387 break; 388 389 case GDMA_EQE_HWC_INIT_EQ_ID_DB: 390 case GDMA_EQE_HWC_INIT_DATA: 391 case GDMA_EQE_HWC_INIT_DONE: 392 case GDMA_EQE_RNIC_QP_FATAL: 393 if (!eq->eq.callback) 394 break; 395 396 event.type = type; 397 memcpy(&event.details, &eqe->details, GDMA_EVENT_DATA_SIZE); 398 eq->eq.callback(eq->eq.context, eq, &event); 399 break; 400 401 default: 402 break; 403 } 404 } 405 406 static void mana_gd_process_eq_events(void *arg) 407 { 408 u32 owner_bits, new_bits, old_bits; 409 union gdma_eqe_info eqe_info; 410 struct gdma_eqe *eq_eqe_ptr; 411 struct gdma_queue *eq = arg; 412 struct gdma_context *gc; 413 struct gdma_eqe *eqe; 414 u32 head, num_eqe; 415 int i; 416 417 gc = eq->gdma_dev->gdma_context; 418 419 num_eqe = eq->queue_size / GDMA_EQE_SIZE; 420 eq_eqe_ptr = eq->queue_mem_ptr; 421 422 /* Process up to 5 EQEs at a time, and update the HW head. */ 423 for (i = 0; i < 5; i++) { 424 eqe = &eq_eqe_ptr[eq->head % num_eqe]; 425 eqe_info.as_uint32 = eqe->eqe_info; 426 owner_bits = eqe_info.owner_bits; 427 428 old_bits = (eq->head / num_eqe - 1) & GDMA_EQE_OWNER_MASK; 429 /* No more entries */ 430 if (owner_bits == old_bits) { 431 /* return here without ringing the doorbell */ 432 if (i == 0) 433 return; 434 break; 435 } 436 437 new_bits = (eq->head / num_eqe) & GDMA_EQE_OWNER_MASK; 438 if (owner_bits != new_bits) { 439 dev_err(gc->dev, "EQ %d: overflow detected\n", eq->id); 440 break; 441 } 442 443 /* Per GDMA spec, rmb is necessary after checking owner_bits, before 444 * reading eqe. 445 */ 446 rmb(); 447 448 mana_gd_process_eqe(eq); 449 450 eq->head++; 451 } 452 453 head = eq->head % (num_eqe << GDMA_EQE_OWNER_BITS); 454 455 mana_gd_ring_doorbell(gc, eq->gdma_dev->doorbell, eq->type, eq->id, 456 head, SET_ARM_BIT); 457 } 458 459 static int mana_gd_register_irq(struct gdma_queue *queue, 460 const struct gdma_queue_spec *spec) 461 { 462 struct gdma_dev *gd = queue->gdma_dev; 463 struct gdma_irq_context *gic; 464 struct gdma_context *gc; 465 unsigned int msi_index; 466 unsigned long flags; 467 struct device *dev; 468 int err = 0; 469 470 gc = gd->gdma_context; 471 dev = gc->dev; 472 msi_index = spec->eq.msix_index; 473 474 if (msi_index >= gc->num_msix_usable) { 475 err = -ENOSPC; 476 dev_err(dev, "Register IRQ err:%d, msi:%u nMSI:%u", 477 err, msi_index, gc->num_msix_usable); 478 479 return err; 480 } 481 482 queue->eq.msix_index = msi_index; 483 gic = &gc->irq_contexts[msi_index]; 484 485 spin_lock_irqsave(&gic->lock, flags); 486 list_add_rcu(&queue->entry, &gic->eq_list); 487 spin_unlock_irqrestore(&gic->lock, flags); 488 489 return 0; 490 } 491 492 static void mana_gd_deregiser_irq(struct gdma_queue *queue) 493 { 494 struct gdma_dev *gd = queue->gdma_dev; 495 struct gdma_irq_context *gic; 496 struct gdma_context *gc; 497 unsigned int msix_index; 498 unsigned long flags; 499 struct gdma_queue *eq; 500 501 gc = gd->gdma_context; 502 503 /* At most num_online_cpus() + 1 interrupts are used. */ 504 msix_index = queue->eq.msix_index; 505 if (WARN_ON(msix_index >= gc->num_msix_usable)) 506 return; 507 508 gic = &gc->irq_contexts[msix_index]; 509 spin_lock_irqsave(&gic->lock, flags); 510 list_for_each_entry_rcu(eq, &gic->eq_list, entry) { 511 if (queue == eq) { 512 list_del_rcu(&eq->entry); 513 break; 514 } 515 } 516 spin_unlock_irqrestore(&gic->lock, flags); 517 518 queue->eq.msix_index = INVALID_PCI_MSIX_INDEX; 519 synchronize_rcu(); 520 } 521 522 int mana_gd_test_eq(struct gdma_context *gc, struct gdma_queue *eq) 523 { 524 struct gdma_generate_test_event_req req = {}; 525 struct gdma_general_resp resp = {}; 526 struct device *dev = gc->dev; 527 int err; 528 529 mutex_lock(&gc->eq_test_event_mutex); 530 531 init_completion(&gc->eq_test_event); 532 gc->test_event_eq_id = INVALID_QUEUE_ID; 533 534 mana_gd_init_req_hdr(&req.hdr, GDMA_GENERATE_TEST_EQE, 535 sizeof(req), sizeof(resp)); 536 537 req.hdr.dev_id = eq->gdma_dev->dev_id; 538 req.queue_index = eq->id; 539 540 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 541 if (err) { 542 dev_err(dev, "test_eq failed: %d\n", err); 543 goto out; 544 } 545 546 err = -EPROTO; 547 548 if (resp.hdr.status) { 549 dev_err(dev, "test_eq failed: 0x%x\n", resp.hdr.status); 550 goto out; 551 } 552 553 if (!wait_for_completion_timeout(&gc->eq_test_event, 30 * HZ)) { 554 dev_err(dev, "test_eq timed out on queue %d\n", eq->id); 555 goto out; 556 } 557 558 if (eq->id != gc->test_event_eq_id) { 559 dev_err(dev, "test_eq got an event on wrong queue %d (%d)\n", 560 gc->test_event_eq_id, eq->id); 561 goto out; 562 } 563 564 err = 0; 565 out: 566 mutex_unlock(&gc->eq_test_event_mutex); 567 return err; 568 } 569 570 static void mana_gd_destroy_eq(struct gdma_context *gc, bool flush_evenets, 571 struct gdma_queue *queue) 572 { 573 int err; 574 575 if (flush_evenets) { 576 err = mana_gd_test_eq(gc, queue); 577 if (err) 578 dev_warn(gc->dev, "Failed to flush EQ: %d\n", err); 579 } 580 581 mana_gd_deregiser_irq(queue); 582 583 if (queue->eq.disable_needed) 584 mana_gd_disable_queue(queue); 585 } 586 587 static int mana_gd_create_eq(struct gdma_dev *gd, 588 const struct gdma_queue_spec *spec, 589 bool create_hwq, struct gdma_queue *queue) 590 { 591 struct gdma_context *gc = gd->gdma_context; 592 struct device *dev = gc->dev; 593 u32 log2_num_entries; 594 int err; 595 596 queue->eq.msix_index = INVALID_PCI_MSIX_INDEX; 597 queue->id = INVALID_QUEUE_ID; 598 599 log2_num_entries = ilog2(queue->queue_size / GDMA_EQE_SIZE); 600 601 if (spec->eq.log2_throttle_limit > log2_num_entries) { 602 dev_err(dev, "EQ throttling limit (%lu) > maximum EQE (%u)\n", 603 spec->eq.log2_throttle_limit, log2_num_entries); 604 return -EINVAL; 605 } 606 607 err = mana_gd_register_irq(queue, spec); 608 if (err) { 609 dev_err(dev, "Failed to register irq: %d\n", err); 610 return err; 611 } 612 613 queue->eq.callback = spec->eq.callback; 614 queue->eq.context = spec->eq.context; 615 queue->head |= INITIALIZED_OWNER_BIT(log2_num_entries); 616 queue->eq.log2_throttle_limit = spec->eq.log2_throttle_limit ?: 1; 617 618 if (create_hwq) { 619 err = mana_gd_create_hw_eq(gc, queue); 620 if (err) 621 goto out; 622 623 err = mana_gd_test_eq(gc, queue); 624 if (err) 625 goto out; 626 } 627 628 return 0; 629 out: 630 dev_err(dev, "Failed to create EQ: %d\n", err); 631 mana_gd_destroy_eq(gc, false, queue); 632 return err; 633 } 634 635 static void mana_gd_create_cq(const struct gdma_queue_spec *spec, 636 struct gdma_queue *queue) 637 { 638 u32 log2_num_entries = ilog2(spec->queue_size / GDMA_CQE_SIZE); 639 640 queue->head |= INITIALIZED_OWNER_BIT(log2_num_entries); 641 queue->cq.parent = spec->cq.parent_eq; 642 queue->cq.context = spec->cq.context; 643 queue->cq.callback = spec->cq.callback; 644 } 645 646 static void mana_gd_destroy_cq(struct gdma_context *gc, 647 struct gdma_queue *queue) 648 { 649 u32 id = queue->id; 650 651 if (id >= gc->max_num_cqs) 652 return; 653 654 if (!gc->cq_table[id]) 655 return; 656 657 gc->cq_table[id] = NULL; 658 } 659 660 int mana_gd_create_hwc_queue(struct gdma_dev *gd, 661 const struct gdma_queue_spec *spec, 662 struct gdma_queue **queue_ptr) 663 { 664 struct gdma_context *gc = gd->gdma_context; 665 struct gdma_mem_info *gmi; 666 struct gdma_queue *queue; 667 int err; 668 669 queue = kzalloc(sizeof(*queue), GFP_KERNEL); 670 if (!queue) 671 return -ENOMEM; 672 673 gmi = &queue->mem_info; 674 err = mana_gd_alloc_memory(gc, spec->queue_size, gmi); 675 if (err) 676 goto free_q; 677 678 queue->head = 0; 679 queue->tail = 0; 680 queue->queue_mem_ptr = gmi->virt_addr; 681 queue->queue_size = spec->queue_size; 682 queue->monitor_avl_buf = spec->monitor_avl_buf; 683 queue->type = spec->type; 684 queue->gdma_dev = gd; 685 686 if (spec->type == GDMA_EQ) 687 err = mana_gd_create_eq(gd, spec, false, queue); 688 else if (spec->type == GDMA_CQ) 689 mana_gd_create_cq(spec, queue); 690 691 if (err) 692 goto out; 693 694 *queue_ptr = queue; 695 return 0; 696 out: 697 mana_gd_free_memory(gmi); 698 free_q: 699 kfree(queue); 700 return err; 701 } 702 703 int mana_gd_destroy_dma_region(struct gdma_context *gc, u64 dma_region_handle) 704 { 705 struct gdma_destroy_dma_region_req req = {}; 706 struct gdma_general_resp resp = {}; 707 int err; 708 709 if (dma_region_handle == GDMA_INVALID_DMA_REGION) 710 return 0; 711 712 mana_gd_init_req_hdr(&req.hdr, GDMA_DESTROY_DMA_REGION, sizeof(req), 713 sizeof(resp)); 714 req.dma_region_handle = dma_region_handle; 715 716 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 717 if (err || resp.hdr.status) { 718 dev_err(gc->dev, "Failed to destroy DMA region: %d, 0x%x\n", 719 err, resp.hdr.status); 720 return -EPROTO; 721 } 722 723 return 0; 724 } 725 EXPORT_SYMBOL_NS(mana_gd_destroy_dma_region, "NET_MANA"); 726 727 static int mana_gd_create_dma_region(struct gdma_dev *gd, 728 struct gdma_mem_info *gmi) 729 { 730 unsigned int num_page = gmi->length / MANA_PAGE_SIZE; 731 struct gdma_create_dma_region_req *req = NULL; 732 struct gdma_create_dma_region_resp resp = {}; 733 struct gdma_context *gc = gd->gdma_context; 734 struct hw_channel_context *hwc; 735 u32 length = gmi->length; 736 size_t req_msg_size; 737 int err; 738 int i; 739 740 if (length < MANA_PAGE_SIZE || !is_power_of_2(length)) 741 return -EINVAL; 742 743 if (!MANA_PAGE_ALIGNED(gmi->virt_addr)) 744 return -EINVAL; 745 746 hwc = gc->hwc.driver_data; 747 req_msg_size = struct_size(req, page_addr_list, num_page); 748 if (req_msg_size > hwc->max_req_msg_size) 749 return -EINVAL; 750 751 req = kzalloc(req_msg_size, GFP_KERNEL); 752 if (!req) 753 return -ENOMEM; 754 755 mana_gd_init_req_hdr(&req->hdr, GDMA_CREATE_DMA_REGION, 756 req_msg_size, sizeof(resp)); 757 req->length = length; 758 req->offset_in_page = 0; 759 req->gdma_page_type = GDMA_PAGE_TYPE_4K; 760 req->page_count = num_page; 761 req->page_addr_list_len = num_page; 762 763 for (i = 0; i < num_page; i++) 764 req->page_addr_list[i] = gmi->dma_handle + i * MANA_PAGE_SIZE; 765 766 err = mana_gd_send_request(gc, req_msg_size, req, sizeof(resp), &resp); 767 if (err) 768 goto out; 769 770 if (resp.hdr.status || 771 resp.dma_region_handle == GDMA_INVALID_DMA_REGION) { 772 dev_err(gc->dev, "Failed to create DMA region: 0x%x\n", 773 resp.hdr.status); 774 err = -EPROTO; 775 goto out; 776 } 777 778 gmi->dma_region_handle = resp.dma_region_handle; 779 out: 780 kfree(req); 781 return err; 782 } 783 784 int mana_gd_create_mana_eq(struct gdma_dev *gd, 785 const struct gdma_queue_spec *spec, 786 struct gdma_queue **queue_ptr) 787 { 788 struct gdma_context *gc = gd->gdma_context; 789 struct gdma_mem_info *gmi; 790 struct gdma_queue *queue; 791 int err; 792 793 if (spec->type != GDMA_EQ) 794 return -EINVAL; 795 796 queue = kzalloc(sizeof(*queue), GFP_KERNEL); 797 if (!queue) 798 return -ENOMEM; 799 800 gmi = &queue->mem_info; 801 err = mana_gd_alloc_memory(gc, spec->queue_size, gmi); 802 if (err) 803 goto free_q; 804 805 err = mana_gd_create_dma_region(gd, gmi); 806 if (err) 807 goto out; 808 809 queue->head = 0; 810 queue->tail = 0; 811 queue->queue_mem_ptr = gmi->virt_addr; 812 queue->queue_size = spec->queue_size; 813 queue->monitor_avl_buf = spec->monitor_avl_buf; 814 queue->type = spec->type; 815 queue->gdma_dev = gd; 816 817 err = mana_gd_create_eq(gd, spec, true, queue); 818 if (err) 819 goto out; 820 821 *queue_ptr = queue; 822 return 0; 823 out: 824 mana_gd_free_memory(gmi); 825 free_q: 826 kfree(queue); 827 return err; 828 } 829 EXPORT_SYMBOL_NS(mana_gd_create_mana_eq, "NET_MANA"); 830 831 int mana_gd_create_mana_wq_cq(struct gdma_dev *gd, 832 const struct gdma_queue_spec *spec, 833 struct gdma_queue **queue_ptr) 834 { 835 struct gdma_context *gc = gd->gdma_context; 836 struct gdma_mem_info *gmi; 837 struct gdma_queue *queue; 838 int err; 839 840 if (spec->type != GDMA_CQ && spec->type != GDMA_SQ && 841 spec->type != GDMA_RQ) 842 return -EINVAL; 843 844 queue = kzalloc(sizeof(*queue), GFP_KERNEL); 845 if (!queue) 846 return -ENOMEM; 847 848 gmi = &queue->mem_info; 849 err = mana_gd_alloc_memory(gc, spec->queue_size, gmi); 850 if (err) 851 goto free_q; 852 853 err = mana_gd_create_dma_region(gd, gmi); 854 if (err) 855 goto out; 856 857 queue->head = 0; 858 queue->tail = 0; 859 queue->queue_mem_ptr = gmi->virt_addr; 860 queue->queue_size = spec->queue_size; 861 queue->monitor_avl_buf = spec->monitor_avl_buf; 862 queue->type = spec->type; 863 queue->gdma_dev = gd; 864 865 if (spec->type == GDMA_CQ) 866 mana_gd_create_cq(spec, queue); 867 868 *queue_ptr = queue; 869 return 0; 870 out: 871 mana_gd_free_memory(gmi); 872 free_q: 873 kfree(queue); 874 return err; 875 } 876 877 void mana_gd_destroy_queue(struct gdma_context *gc, struct gdma_queue *queue) 878 { 879 struct gdma_mem_info *gmi = &queue->mem_info; 880 881 switch (queue->type) { 882 case GDMA_EQ: 883 mana_gd_destroy_eq(gc, queue->eq.disable_needed, queue); 884 break; 885 886 case GDMA_CQ: 887 mana_gd_destroy_cq(gc, queue); 888 break; 889 890 case GDMA_RQ: 891 break; 892 893 case GDMA_SQ: 894 break; 895 896 default: 897 dev_err(gc->dev, "Can't destroy unknown queue: type=%d\n", 898 queue->type); 899 return; 900 } 901 902 mana_gd_destroy_dma_region(gc, gmi->dma_region_handle); 903 mana_gd_free_memory(gmi); 904 kfree(queue); 905 } 906 EXPORT_SYMBOL_NS(mana_gd_destroy_queue, "NET_MANA"); 907 908 int mana_gd_verify_vf_version(struct pci_dev *pdev) 909 { 910 struct gdma_context *gc = pci_get_drvdata(pdev); 911 struct gdma_verify_ver_resp resp = {}; 912 struct gdma_verify_ver_req req = {}; 913 struct hw_channel_context *hwc; 914 int err; 915 916 hwc = gc->hwc.driver_data; 917 mana_gd_init_req_hdr(&req.hdr, GDMA_VERIFY_VF_DRIVER_VERSION, 918 sizeof(req), sizeof(resp)); 919 920 req.protocol_ver_min = GDMA_PROTOCOL_FIRST; 921 req.protocol_ver_max = GDMA_PROTOCOL_LAST; 922 923 req.gd_drv_cap_flags1 = GDMA_DRV_CAP_FLAGS1; 924 req.gd_drv_cap_flags2 = GDMA_DRV_CAP_FLAGS2; 925 req.gd_drv_cap_flags3 = GDMA_DRV_CAP_FLAGS3; 926 req.gd_drv_cap_flags4 = GDMA_DRV_CAP_FLAGS4; 927 928 req.drv_ver = 0; /* Unused*/ 929 req.os_type = 0x10; /* Linux */ 930 req.os_ver_major = LINUX_VERSION_MAJOR; 931 req.os_ver_minor = LINUX_VERSION_PATCHLEVEL; 932 req.os_ver_build = LINUX_VERSION_SUBLEVEL; 933 strscpy(req.os_ver_str1, utsname()->sysname, sizeof(req.os_ver_str1)); 934 strscpy(req.os_ver_str2, utsname()->release, sizeof(req.os_ver_str2)); 935 strscpy(req.os_ver_str3, utsname()->version, sizeof(req.os_ver_str3)); 936 937 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 938 if (err || resp.hdr.status) { 939 dev_err(gc->dev, "VfVerifyVersionOutput: %d, status=0x%x\n", 940 err, resp.hdr.status); 941 return err ? err : -EPROTO; 942 } 943 if (resp.pf_cap_flags1 & GDMA_DRV_CAP_FLAG_1_HWC_TIMEOUT_RECONFIG) { 944 err = mana_gd_query_hwc_timeout(pdev, &hwc->hwc_timeout); 945 if (err) { 946 dev_err(gc->dev, "Failed to set the hwc timeout %d\n", err); 947 return err; 948 } 949 dev_dbg(gc->dev, "set the hwc timeout to %u\n", hwc->hwc_timeout); 950 } 951 return 0; 952 } 953 954 int mana_gd_register_device(struct gdma_dev *gd) 955 { 956 struct gdma_context *gc = gd->gdma_context; 957 struct gdma_register_device_resp resp = {}; 958 struct gdma_general_req req = {}; 959 int err; 960 961 gd->pdid = INVALID_PDID; 962 gd->doorbell = INVALID_DOORBELL; 963 gd->gpa_mkey = INVALID_MEM_KEY; 964 965 mana_gd_init_req_hdr(&req.hdr, GDMA_REGISTER_DEVICE, sizeof(req), 966 sizeof(resp)); 967 968 req.hdr.dev_id = gd->dev_id; 969 970 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 971 if (err || resp.hdr.status) { 972 dev_err(gc->dev, "gdma_register_device_resp failed: %d, 0x%x\n", 973 err, resp.hdr.status); 974 return err ? err : -EPROTO; 975 } 976 977 gd->pdid = resp.pdid; 978 gd->gpa_mkey = resp.gpa_mkey; 979 gd->doorbell = resp.db_id; 980 981 return 0; 982 } 983 EXPORT_SYMBOL_NS(mana_gd_register_device, "NET_MANA"); 984 985 int mana_gd_deregister_device(struct gdma_dev *gd) 986 { 987 struct gdma_context *gc = gd->gdma_context; 988 struct gdma_general_resp resp = {}; 989 struct gdma_general_req req = {}; 990 int err; 991 992 if (gd->pdid == INVALID_PDID) 993 return -EINVAL; 994 995 mana_gd_init_req_hdr(&req.hdr, GDMA_DEREGISTER_DEVICE, sizeof(req), 996 sizeof(resp)); 997 998 req.hdr.dev_id = gd->dev_id; 999 1000 err = mana_gd_send_request(gc, sizeof(req), &req, sizeof(resp), &resp); 1001 if (err || resp.hdr.status) { 1002 dev_err(gc->dev, "Failed to deregister device: %d, 0x%x\n", 1003 err, resp.hdr.status); 1004 if (!err) 1005 err = -EPROTO; 1006 } 1007 1008 gd->pdid = INVALID_PDID; 1009 gd->doorbell = INVALID_DOORBELL; 1010 gd->gpa_mkey = INVALID_MEM_KEY; 1011 1012 return err; 1013 } 1014 EXPORT_SYMBOL_NS(mana_gd_deregister_device, "NET_MANA"); 1015 1016 u32 mana_gd_wq_avail_space(struct gdma_queue *wq) 1017 { 1018 u32 used_space = (wq->head - wq->tail) * GDMA_WQE_BU_SIZE; 1019 u32 wq_size = wq->queue_size; 1020 1021 WARN_ON_ONCE(used_space > wq_size); 1022 1023 return wq_size - used_space; 1024 } 1025 1026 u8 *mana_gd_get_wqe_ptr(const struct gdma_queue *wq, u32 wqe_offset) 1027 { 1028 u32 offset = (wqe_offset * GDMA_WQE_BU_SIZE) & (wq->queue_size - 1); 1029 1030 WARN_ON_ONCE((offset + GDMA_WQE_BU_SIZE) > wq->queue_size); 1031 1032 return wq->queue_mem_ptr + offset; 1033 } 1034 1035 static u32 mana_gd_write_client_oob(const struct gdma_wqe_request *wqe_req, 1036 enum gdma_queue_type q_type, 1037 u32 client_oob_size, u32 sgl_data_size, 1038 u8 *wqe_ptr) 1039 { 1040 bool oob_in_sgl = !!(wqe_req->flags & GDMA_WR_OOB_IN_SGL); 1041 bool pad_data = !!(wqe_req->flags & GDMA_WR_PAD_BY_SGE0); 1042 struct gdma_wqe *header = (struct gdma_wqe *)wqe_ptr; 1043 u8 *ptr; 1044 1045 memset(header, 0, sizeof(struct gdma_wqe)); 1046 header->num_sge = wqe_req->num_sge; 1047 header->inline_oob_size_div4 = client_oob_size / sizeof(u32); 1048 1049 if (oob_in_sgl) { 1050 WARN_ON_ONCE(!pad_data || wqe_req->num_sge < 2); 1051 1052 header->client_oob_in_sgl = 1; 1053 1054 if (pad_data) 1055 header->last_vbytes = wqe_req->sgl[0].size; 1056 } 1057 1058 if (q_type == GDMA_SQ) 1059 header->client_data_unit = wqe_req->client_data_unit; 1060 1061 /* The size of gdma_wqe + client_oob_size must be less than or equal 1062 * to one Basic Unit (i.e. 32 bytes), so the pointer can't go beyond 1063 * the queue memory buffer boundary. 1064 */ 1065 ptr = wqe_ptr + sizeof(header); 1066 1067 if (wqe_req->inline_oob_data && wqe_req->inline_oob_size > 0) { 1068 memcpy(ptr, wqe_req->inline_oob_data, wqe_req->inline_oob_size); 1069 1070 if (client_oob_size > wqe_req->inline_oob_size) 1071 memset(ptr + wqe_req->inline_oob_size, 0, 1072 client_oob_size - wqe_req->inline_oob_size); 1073 } 1074 1075 return sizeof(header) + client_oob_size; 1076 } 1077 1078 static void mana_gd_write_sgl(struct gdma_queue *wq, u8 *wqe_ptr, 1079 const struct gdma_wqe_request *wqe_req) 1080 { 1081 u32 sgl_size = sizeof(struct gdma_sge) * wqe_req->num_sge; 1082 const u8 *address = (u8 *)wqe_req->sgl; 1083 u8 *base_ptr, *end_ptr; 1084 u32 size_to_end; 1085 1086 base_ptr = wq->queue_mem_ptr; 1087 end_ptr = base_ptr + wq->queue_size; 1088 size_to_end = (u32)(end_ptr - wqe_ptr); 1089 1090 if (size_to_end < sgl_size) { 1091 memcpy(wqe_ptr, address, size_to_end); 1092 1093 wqe_ptr = base_ptr; 1094 address += size_to_end; 1095 sgl_size -= size_to_end; 1096 } 1097 1098 memcpy(wqe_ptr, address, sgl_size); 1099 } 1100 1101 int mana_gd_post_work_request(struct gdma_queue *wq, 1102 const struct gdma_wqe_request *wqe_req, 1103 struct gdma_posted_wqe_info *wqe_info) 1104 { 1105 u32 client_oob_size = wqe_req->inline_oob_size; 1106 struct gdma_context *gc; 1107 u32 sgl_data_size; 1108 u32 max_wqe_size; 1109 u32 wqe_size; 1110 u8 *wqe_ptr; 1111 1112 if (wqe_req->num_sge == 0) 1113 return -EINVAL; 1114 1115 if (wq->type == GDMA_RQ) { 1116 if (client_oob_size != 0) 1117 return -EINVAL; 1118 1119 client_oob_size = INLINE_OOB_SMALL_SIZE; 1120 1121 max_wqe_size = GDMA_MAX_RQE_SIZE; 1122 } else { 1123 if (client_oob_size != INLINE_OOB_SMALL_SIZE && 1124 client_oob_size != INLINE_OOB_LARGE_SIZE) 1125 return -EINVAL; 1126 1127 max_wqe_size = GDMA_MAX_SQE_SIZE; 1128 } 1129 1130 sgl_data_size = sizeof(struct gdma_sge) * wqe_req->num_sge; 1131 wqe_size = ALIGN(sizeof(struct gdma_wqe) + client_oob_size + 1132 sgl_data_size, GDMA_WQE_BU_SIZE); 1133 if (wqe_size > max_wqe_size) 1134 return -EINVAL; 1135 1136 if (wq->monitor_avl_buf && wqe_size > mana_gd_wq_avail_space(wq)) { 1137 gc = wq->gdma_dev->gdma_context; 1138 dev_err(gc->dev, "unsuccessful flow control!\n"); 1139 return -ENOSPC; 1140 } 1141 1142 if (wqe_info) 1143 wqe_info->wqe_size_in_bu = wqe_size / GDMA_WQE_BU_SIZE; 1144 1145 wqe_ptr = mana_gd_get_wqe_ptr(wq, wq->head); 1146 wqe_ptr += mana_gd_write_client_oob(wqe_req, wq->type, client_oob_size, 1147 sgl_data_size, wqe_ptr); 1148 if (wqe_ptr >= (u8 *)wq->queue_mem_ptr + wq->queue_size) 1149 wqe_ptr -= wq->queue_size; 1150 1151 mana_gd_write_sgl(wq, wqe_ptr, wqe_req); 1152 1153 wq->head += wqe_size / GDMA_WQE_BU_SIZE; 1154 1155 return 0; 1156 } 1157 1158 int mana_gd_post_and_ring(struct gdma_queue *queue, 1159 const struct gdma_wqe_request *wqe_req, 1160 struct gdma_posted_wqe_info *wqe_info) 1161 { 1162 struct gdma_context *gc = queue->gdma_dev->gdma_context; 1163 int err; 1164 1165 err = mana_gd_post_work_request(queue, wqe_req, wqe_info); 1166 if (err) 1167 return err; 1168 1169 mana_gd_wq_ring_doorbell(gc, queue); 1170 1171 return 0; 1172 } 1173 1174 static int mana_gd_read_cqe(struct gdma_queue *cq, struct gdma_comp *comp) 1175 { 1176 unsigned int num_cqe = cq->queue_size / sizeof(struct gdma_cqe); 1177 struct gdma_cqe *cq_cqe = cq->queue_mem_ptr; 1178 u32 owner_bits, new_bits, old_bits; 1179 struct gdma_cqe *cqe; 1180 1181 cqe = &cq_cqe[cq->head % num_cqe]; 1182 owner_bits = cqe->cqe_info.owner_bits; 1183 1184 old_bits = (cq->head / num_cqe - 1) & GDMA_CQE_OWNER_MASK; 1185 /* Return 0 if no more entries. */ 1186 if (owner_bits == old_bits) 1187 return 0; 1188 1189 new_bits = (cq->head / num_cqe) & GDMA_CQE_OWNER_MASK; 1190 /* Return -1 if overflow detected. */ 1191 if (WARN_ON_ONCE(owner_bits != new_bits)) 1192 return -1; 1193 1194 /* Per GDMA spec, rmb is necessary after checking owner_bits, before 1195 * reading completion info 1196 */ 1197 rmb(); 1198 1199 comp->wq_num = cqe->cqe_info.wq_num; 1200 comp->is_sq = cqe->cqe_info.is_sq; 1201 memcpy(comp->cqe_data, cqe->cqe_data, GDMA_COMP_DATA_SIZE); 1202 1203 return 1; 1204 } 1205 1206 int mana_gd_poll_cq(struct gdma_queue *cq, struct gdma_comp *comp, int num_cqe) 1207 { 1208 int cqe_idx; 1209 int ret; 1210 1211 for (cqe_idx = 0; cqe_idx < num_cqe; cqe_idx++) { 1212 ret = mana_gd_read_cqe(cq, &comp[cqe_idx]); 1213 1214 if (ret < 0) { 1215 cq->head -= cqe_idx; 1216 return ret; 1217 } 1218 1219 if (ret == 0) 1220 break; 1221 1222 cq->head++; 1223 } 1224 1225 return cqe_idx; 1226 } 1227 1228 static irqreturn_t mana_gd_intr(int irq, void *arg) 1229 { 1230 struct gdma_irq_context *gic = arg; 1231 struct list_head *eq_list = &gic->eq_list; 1232 struct gdma_queue *eq; 1233 1234 rcu_read_lock(); 1235 list_for_each_entry_rcu(eq, eq_list, entry) { 1236 gic->handler(eq); 1237 } 1238 rcu_read_unlock(); 1239 1240 return IRQ_HANDLED; 1241 } 1242 1243 int mana_gd_alloc_res_map(u32 res_avail, struct gdma_resource *r) 1244 { 1245 r->map = bitmap_zalloc(res_avail, GFP_KERNEL); 1246 if (!r->map) 1247 return -ENOMEM; 1248 1249 r->size = res_avail; 1250 spin_lock_init(&r->lock); 1251 1252 return 0; 1253 } 1254 1255 void mana_gd_free_res_map(struct gdma_resource *r) 1256 { 1257 bitmap_free(r->map); 1258 r->map = NULL; 1259 r->size = 0; 1260 } 1261 1262 static int irq_setup(unsigned int *irqs, unsigned int len, int node) 1263 { 1264 const struct cpumask *next, *prev = cpu_none_mask; 1265 cpumask_var_t cpus __free(free_cpumask_var); 1266 int cpu, weight; 1267 1268 if (!alloc_cpumask_var(&cpus, GFP_KERNEL)) 1269 return -ENOMEM; 1270 1271 rcu_read_lock(); 1272 for_each_numa_hop_mask(next, node) { 1273 weight = cpumask_weight_andnot(next, prev); 1274 while (weight > 0) { 1275 cpumask_andnot(cpus, next, prev); 1276 for_each_cpu(cpu, cpus) { 1277 if (len-- == 0) 1278 goto done; 1279 irq_set_affinity_and_hint(*irqs++, topology_sibling_cpumask(cpu)); 1280 cpumask_andnot(cpus, cpus, topology_sibling_cpumask(cpu)); 1281 --weight; 1282 } 1283 } 1284 prev = next; 1285 } 1286 done: 1287 rcu_read_unlock(); 1288 return 0; 1289 } 1290 1291 static int mana_gd_setup_irqs(struct pci_dev *pdev) 1292 { 1293 struct gdma_context *gc = pci_get_drvdata(pdev); 1294 unsigned int max_queues_per_port; 1295 struct gdma_irq_context *gic; 1296 unsigned int max_irqs, cpu; 1297 int start_irq_index = 1; 1298 int nvec, *irqs, irq; 1299 int err, i = 0, j; 1300 1301 cpus_read_lock(); 1302 max_queues_per_port = num_online_cpus(); 1303 if (max_queues_per_port > MANA_MAX_NUM_QUEUES) 1304 max_queues_per_port = MANA_MAX_NUM_QUEUES; 1305 1306 /* Need 1 interrupt for the Hardware communication Channel (HWC) */ 1307 max_irqs = max_queues_per_port + 1; 1308 1309 nvec = pci_alloc_irq_vectors(pdev, 2, max_irqs, PCI_IRQ_MSIX); 1310 if (nvec < 0) { 1311 cpus_read_unlock(); 1312 return nvec; 1313 } 1314 if (nvec <= num_online_cpus()) 1315 start_irq_index = 0; 1316 1317 irqs = kmalloc_array((nvec - start_irq_index), sizeof(int), GFP_KERNEL); 1318 if (!irqs) { 1319 err = -ENOMEM; 1320 goto free_irq_vector; 1321 } 1322 1323 gc->irq_contexts = kcalloc(nvec, sizeof(struct gdma_irq_context), 1324 GFP_KERNEL); 1325 if (!gc->irq_contexts) { 1326 err = -ENOMEM; 1327 goto free_irq_array; 1328 } 1329 1330 for (i = 0; i < nvec; i++) { 1331 gic = &gc->irq_contexts[i]; 1332 gic->handler = mana_gd_process_eq_events; 1333 INIT_LIST_HEAD(&gic->eq_list); 1334 spin_lock_init(&gic->lock); 1335 1336 if (!i) 1337 snprintf(gic->name, MANA_IRQ_NAME_SZ, "mana_hwc@pci:%s", 1338 pci_name(pdev)); 1339 else 1340 snprintf(gic->name, MANA_IRQ_NAME_SZ, "mana_q%d@pci:%s", 1341 i - 1, pci_name(pdev)); 1342 1343 irq = pci_irq_vector(pdev, i); 1344 if (irq < 0) { 1345 err = irq; 1346 goto free_irq; 1347 } 1348 1349 if (!i) { 1350 err = request_irq(irq, mana_gd_intr, 0, gic->name, gic); 1351 if (err) 1352 goto free_irq; 1353 1354 /* If number of IRQ is one extra than number of online CPUs, 1355 * then we need to assign IRQ0 (hwc irq) and IRQ1 to 1356 * same CPU. 1357 * Else we will use different CPUs for IRQ0 and IRQ1. 1358 * Also we are using cpumask_local_spread instead of 1359 * cpumask_first for the node, because the node can be 1360 * mem only. 1361 */ 1362 if (start_irq_index) { 1363 cpu = cpumask_local_spread(i, gc->numa_node); 1364 irq_set_affinity_and_hint(irq, cpumask_of(cpu)); 1365 } else { 1366 irqs[start_irq_index] = irq; 1367 } 1368 } else { 1369 irqs[i - start_irq_index] = irq; 1370 err = request_irq(irqs[i - start_irq_index], mana_gd_intr, 0, 1371 gic->name, gic); 1372 if (err) 1373 goto free_irq; 1374 } 1375 } 1376 1377 err = irq_setup(irqs, (nvec - start_irq_index), gc->numa_node); 1378 if (err) 1379 goto free_irq; 1380 1381 gc->max_num_msix = nvec; 1382 gc->num_msix_usable = nvec; 1383 cpus_read_unlock(); 1384 kfree(irqs); 1385 return 0; 1386 1387 free_irq: 1388 for (j = i - 1; j >= 0; j--) { 1389 irq = pci_irq_vector(pdev, j); 1390 gic = &gc->irq_contexts[j]; 1391 1392 irq_update_affinity_hint(irq, NULL); 1393 free_irq(irq, gic); 1394 } 1395 1396 kfree(gc->irq_contexts); 1397 gc->irq_contexts = NULL; 1398 free_irq_array: 1399 kfree(irqs); 1400 free_irq_vector: 1401 cpus_read_unlock(); 1402 pci_free_irq_vectors(pdev); 1403 return err; 1404 } 1405 1406 static void mana_gd_remove_irqs(struct pci_dev *pdev) 1407 { 1408 struct gdma_context *gc = pci_get_drvdata(pdev); 1409 struct gdma_irq_context *gic; 1410 int irq, i; 1411 1412 if (gc->max_num_msix < 1) 1413 return; 1414 1415 for (i = 0; i < gc->max_num_msix; i++) { 1416 irq = pci_irq_vector(pdev, i); 1417 if (irq < 0) 1418 continue; 1419 1420 gic = &gc->irq_contexts[i]; 1421 1422 /* Need to clear the hint before free_irq */ 1423 irq_update_affinity_hint(irq, NULL); 1424 free_irq(irq, gic); 1425 } 1426 1427 pci_free_irq_vectors(pdev); 1428 1429 gc->max_num_msix = 0; 1430 gc->num_msix_usable = 0; 1431 kfree(gc->irq_contexts); 1432 gc->irq_contexts = NULL; 1433 } 1434 1435 static int mana_gd_setup(struct pci_dev *pdev) 1436 { 1437 struct gdma_context *gc = pci_get_drvdata(pdev); 1438 int err; 1439 1440 mana_gd_init_registers(pdev); 1441 mana_smc_init(&gc->shm_channel, gc->dev, gc->shm_base); 1442 1443 err = mana_gd_setup_irqs(pdev); 1444 if (err) 1445 return err; 1446 1447 err = mana_hwc_create_channel(gc); 1448 if (err) 1449 goto remove_irq; 1450 1451 err = mana_gd_verify_vf_version(pdev); 1452 if (err) 1453 goto destroy_hwc; 1454 1455 err = mana_gd_query_max_resources(pdev); 1456 if (err) 1457 goto destroy_hwc; 1458 1459 err = mana_gd_detect_devices(pdev); 1460 if (err) 1461 goto destroy_hwc; 1462 1463 return 0; 1464 1465 destroy_hwc: 1466 mana_hwc_destroy_channel(gc); 1467 remove_irq: 1468 mana_gd_remove_irqs(pdev); 1469 return err; 1470 } 1471 1472 static void mana_gd_cleanup(struct pci_dev *pdev) 1473 { 1474 struct gdma_context *gc = pci_get_drvdata(pdev); 1475 1476 mana_hwc_destroy_channel(gc); 1477 1478 mana_gd_remove_irqs(pdev); 1479 } 1480 1481 static bool mana_is_pf(unsigned short dev_id) 1482 { 1483 return dev_id == MANA_PF_DEVICE_ID; 1484 } 1485 1486 static int mana_gd_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1487 { 1488 struct gdma_context *gc; 1489 void __iomem *bar0_va; 1490 int bar = 0; 1491 int err; 1492 1493 /* Each port has 2 CQs, each CQ has at most 1 EQE at a time */ 1494 BUILD_BUG_ON(2 * MAX_PORTS_IN_MANA_DEV * GDMA_EQE_SIZE > EQ_SIZE); 1495 1496 err = pci_enable_device(pdev); 1497 if (err) 1498 return -ENXIO; 1499 1500 pci_set_master(pdev); 1501 1502 err = pci_request_regions(pdev, "mana"); 1503 if (err) 1504 goto disable_dev; 1505 1506 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 1507 if (err) 1508 goto release_region; 1509 1510 dma_set_max_seg_size(&pdev->dev, UINT_MAX); 1511 1512 err = -ENOMEM; 1513 gc = vzalloc(sizeof(*gc)); 1514 if (!gc) 1515 goto release_region; 1516 1517 mutex_init(&gc->eq_test_event_mutex); 1518 pci_set_drvdata(pdev, gc); 1519 gc->bar0_pa = pci_resource_start(pdev, 0); 1520 1521 bar0_va = pci_iomap(pdev, bar, 0); 1522 if (!bar0_va) 1523 goto free_gc; 1524 1525 gc->numa_node = dev_to_node(&pdev->dev); 1526 gc->is_pf = mana_is_pf(pdev->device); 1527 gc->bar0_va = bar0_va; 1528 gc->dev = &pdev->dev; 1529 1530 if (gc->is_pf) 1531 gc->mana_pci_debugfs = debugfs_create_dir("0", mana_debugfs_root); 1532 else 1533 gc->mana_pci_debugfs = debugfs_create_dir(pci_slot_name(pdev->slot), 1534 mana_debugfs_root); 1535 1536 err = mana_gd_setup(pdev); 1537 if (err) 1538 goto unmap_bar; 1539 1540 err = mana_probe(&gc->mana, false); 1541 if (err) 1542 goto cleanup_gd; 1543 1544 return 0; 1545 1546 cleanup_gd: 1547 mana_gd_cleanup(pdev); 1548 unmap_bar: 1549 /* 1550 * at this point we know that the other debugfs child dir/files 1551 * are either not yet created or are already cleaned up. 1552 * The pci debugfs folder clean-up now, will only be cleaning up 1553 * adapter-MTU file and apc->mana_pci_debugfs folder. 1554 */ 1555 debugfs_remove_recursive(gc->mana_pci_debugfs); 1556 gc->mana_pci_debugfs = NULL; 1557 pci_iounmap(pdev, bar0_va); 1558 free_gc: 1559 pci_set_drvdata(pdev, NULL); 1560 vfree(gc); 1561 release_region: 1562 pci_release_regions(pdev); 1563 disable_dev: 1564 pci_disable_device(pdev); 1565 dev_err(&pdev->dev, "gdma probe failed: err = %d\n", err); 1566 return err; 1567 } 1568 1569 static void mana_gd_remove(struct pci_dev *pdev) 1570 { 1571 struct gdma_context *gc = pci_get_drvdata(pdev); 1572 1573 mana_remove(&gc->mana, false); 1574 1575 mana_gd_cleanup(pdev); 1576 1577 debugfs_remove_recursive(gc->mana_pci_debugfs); 1578 1579 gc->mana_pci_debugfs = NULL; 1580 1581 pci_iounmap(pdev, gc->bar0_va); 1582 1583 vfree(gc); 1584 1585 pci_release_regions(pdev); 1586 pci_disable_device(pdev); 1587 } 1588 1589 /* The 'state' parameter is not used. */ 1590 static int mana_gd_suspend(struct pci_dev *pdev, pm_message_t state) 1591 { 1592 struct gdma_context *gc = pci_get_drvdata(pdev); 1593 1594 mana_remove(&gc->mana, true); 1595 1596 mana_gd_cleanup(pdev); 1597 1598 return 0; 1599 } 1600 1601 /* In case the NIC hardware stops working, the suspend and resume callbacks will 1602 * fail -- if this happens, it's safer to just report an error than try to undo 1603 * what has been done. 1604 */ 1605 static int mana_gd_resume(struct pci_dev *pdev) 1606 { 1607 struct gdma_context *gc = pci_get_drvdata(pdev); 1608 int err; 1609 1610 err = mana_gd_setup(pdev); 1611 if (err) 1612 return err; 1613 1614 err = mana_probe(&gc->mana, true); 1615 if (err) 1616 return err; 1617 1618 return 0; 1619 } 1620 1621 /* Quiesce the device for kexec. This is also called upon reboot/shutdown. */ 1622 static void mana_gd_shutdown(struct pci_dev *pdev) 1623 { 1624 struct gdma_context *gc = pci_get_drvdata(pdev); 1625 1626 dev_info(&pdev->dev, "Shutdown was called\n"); 1627 1628 mana_remove(&gc->mana, true); 1629 1630 mana_gd_cleanup(pdev); 1631 1632 debugfs_remove_recursive(gc->mana_pci_debugfs); 1633 1634 gc->mana_pci_debugfs = NULL; 1635 1636 pci_disable_device(pdev); 1637 } 1638 1639 static const struct pci_device_id mana_id_table[] = { 1640 { PCI_DEVICE(PCI_VENDOR_ID_MICROSOFT, MANA_PF_DEVICE_ID) }, 1641 { PCI_DEVICE(PCI_VENDOR_ID_MICROSOFT, MANA_VF_DEVICE_ID) }, 1642 { } 1643 }; 1644 1645 static struct pci_driver mana_driver = { 1646 .name = "mana", 1647 .id_table = mana_id_table, 1648 .probe = mana_gd_probe, 1649 .remove = mana_gd_remove, 1650 .suspend = mana_gd_suspend, 1651 .resume = mana_gd_resume, 1652 .shutdown = mana_gd_shutdown, 1653 }; 1654 1655 static int __init mana_driver_init(void) 1656 { 1657 int err; 1658 1659 mana_debugfs_root = debugfs_create_dir("mana", NULL); 1660 1661 err = pci_register_driver(&mana_driver); 1662 if (err) { 1663 debugfs_remove(mana_debugfs_root); 1664 mana_debugfs_root = NULL; 1665 } 1666 1667 return err; 1668 } 1669 1670 static void __exit mana_driver_exit(void) 1671 { 1672 pci_unregister_driver(&mana_driver); 1673 1674 debugfs_remove(mana_debugfs_root); 1675 1676 mana_debugfs_root = NULL; 1677 } 1678 1679 module_init(mana_driver_init); 1680 module_exit(mana_driver_exit); 1681 1682 MODULE_DEVICE_TABLE(pci, mana_id_table); 1683 1684 MODULE_LICENSE("Dual BSD/GPL"); 1685 MODULE_DESCRIPTION("Microsoft Azure Network Adapter driver"); 1686