1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Microchip Sparx5 Switch driver 3 * 4 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. 5 */ 6 7 #include "sparx5_main_regs.h" 8 #include "sparx5_main.h" 9 #include "sparx5_port.h" 10 #include "sparx5_tc.h" 11 12 /* The IFH bit position of the first VSTAX bit. This is because the 13 * VSTAX bit positions in Data sheet is starting from zero. 14 */ 15 #define VSTAX 73 16 17 #define ifh_encode_bitfield(ifh, value, pos, _width) \ 18 ({ \ 19 u32 width = (_width); \ 20 \ 21 /* Max width is 5 bytes - 40 bits. In worst case this will 22 * spread over 6 bytes - 48 bits 23 */ \ 24 compiletime_assert(width <= 40, \ 25 "Unsupported width, must be <= 40"); \ 26 __ifh_encode_bitfield((ifh), (value), (pos), width); \ 27 }) 28 29 static void __ifh_encode_bitfield(void *ifh, u64 value, u32 pos, u32 width) 30 { 31 u8 *ifh_hdr = ifh; 32 /* Calculate the Start IFH byte position of this IFH bit position */ 33 u32 byte = (35 - (pos / 8)); 34 /* Calculate the Start bit position in the Start IFH byte */ 35 u32 bit = (pos % 8); 36 u64 encode = GENMASK_ULL(bit + width - 1, bit) & (value << bit); 37 38 /* The b0-b7 goes into the start IFH byte */ 39 if (encode & 0xFF) 40 ifh_hdr[byte] |= (u8)((encode & 0xFF)); 41 /* The b8-b15 goes into the next IFH byte */ 42 if (encode & 0xFF00) 43 ifh_hdr[byte - 1] |= (u8)((encode & 0xFF00) >> 8); 44 /* The b16-b23 goes into the next IFH byte */ 45 if (encode & 0xFF0000) 46 ifh_hdr[byte - 2] |= (u8)((encode & 0xFF0000) >> 16); 47 /* The b24-b31 goes into the next IFH byte */ 48 if (encode & 0xFF000000) 49 ifh_hdr[byte - 3] |= (u8)((encode & 0xFF000000) >> 24); 50 /* The b32-b39 goes into the next IFH byte */ 51 if (encode & 0xFF00000000) 52 ifh_hdr[byte - 4] |= (u8)((encode & 0xFF00000000) >> 32); 53 /* The b40-b47 goes into the next IFH byte */ 54 if (encode & 0xFF0000000000) 55 ifh_hdr[byte - 5] |= (u8)((encode & 0xFF0000000000) >> 40); 56 } 57 58 void sparx5_set_port_ifh(struct sparx5 *sparx5, void *ifh_hdr, u16 portno) 59 { 60 /* VSTAX.RSV = 1. MSBit must be 1 */ 61 ifh_encode_bitfield(ifh_hdr, 1, VSTAX + 79, 1); 62 /* VSTAX.INGR_DROP_MODE = Enable. Don't make head-of-line blocking */ 63 ifh_encode_bitfield(ifh_hdr, 1, VSTAX + 55, 1); 64 /* MISC.CPU_MASK/DPORT = Destination port */ 65 ifh_encode_bitfield(ifh_hdr, portno, 29, 8); 66 /* MISC.PIPELINE_PT */ 67 ifh_encode_bitfield(ifh_hdr, 16, 37, 5); 68 /* MISC.PIPELINE_ACT */ 69 ifh_encode_bitfield(ifh_hdr, 1, 42, 3); 70 /* FWD.SRC_PORT = CPU */ 71 ifh_encode_bitfield(ifh_hdr, sparx5_get_pgid(sparx5, SPX5_PORT_CPU_0), 72 46, 7); 73 /* FWD.SFLOW_ID (disable SFlow sampling) */ 74 ifh_encode_bitfield(ifh_hdr, 124, 57, 7); 75 /* FWD.UPDATE_FCS = Enable. Enforce update of FCS. */ 76 ifh_encode_bitfield(ifh_hdr, 1, 67, 1); 77 } 78 79 void sparx5_set_port_ifh_rew_op(void *ifh_hdr, u32 rew_op) 80 { 81 ifh_encode_bitfield(ifh_hdr, rew_op, VSTAX + 32, 10); 82 } 83 84 void sparx5_set_port_ifh_pdu_type(void *ifh_hdr, u32 pdu_type) 85 { 86 ifh_encode_bitfield(ifh_hdr, pdu_type, 191, 4); 87 } 88 89 void sparx5_set_port_ifh_pdu_w16_offset(void *ifh_hdr, u32 pdu_w16_offset) 90 { 91 ifh_encode_bitfield(ifh_hdr, pdu_w16_offset, 195, 6); 92 } 93 94 void sparx5_set_port_ifh_timestamp(void *ifh_hdr, u64 timestamp) 95 { 96 ifh_encode_bitfield(ifh_hdr, timestamp, 232, 40); 97 } 98 99 static int sparx5_port_open(struct net_device *ndev) 100 { 101 struct sparx5_port *port = netdev_priv(ndev); 102 int err = 0; 103 104 sparx5_port_enable(port, true); 105 err = phylink_of_phy_connect(port->phylink, port->of_node, 0); 106 if (err) { 107 netdev_err(ndev, "Could not attach to PHY\n"); 108 goto err_connect; 109 } 110 111 phylink_start(port->phylink); 112 113 if (!ndev->phydev) { 114 /* power up serdes */ 115 port->conf.power_down = false; 116 if (port->conf.serdes_reset) 117 err = sparx5_serdes_set(port->sparx5, port, &port->conf); 118 else 119 err = phy_power_on(port->serdes); 120 if (err) { 121 netdev_err(ndev, "%s failed\n", __func__); 122 goto out_power; 123 } 124 } 125 126 return 0; 127 128 out_power: 129 phylink_stop(port->phylink); 130 phylink_disconnect_phy(port->phylink); 131 err_connect: 132 sparx5_port_enable(port, false); 133 134 return err; 135 } 136 137 static int sparx5_port_stop(struct net_device *ndev) 138 { 139 struct sparx5_port *port = netdev_priv(ndev); 140 int err = 0; 141 142 sparx5_port_enable(port, false); 143 phylink_stop(port->phylink); 144 phylink_disconnect_phy(port->phylink); 145 146 if (!ndev->phydev) { 147 /* power down serdes */ 148 port->conf.power_down = true; 149 if (port->conf.serdes_reset) 150 err = sparx5_serdes_set(port->sparx5, port, &port->conf); 151 else 152 err = phy_power_off(port->serdes); 153 if (err) 154 netdev_err(ndev, "%s failed\n", __func__); 155 } 156 return 0; 157 } 158 159 static void sparx5_set_rx_mode(struct net_device *dev) 160 { 161 struct sparx5_port *port = netdev_priv(dev); 162 struct sparx5 *sparx5 = port->sparx5; 163 164 if (!test_bit(port->portno, sparx5->bridge_mask)) 165 __dev_mc_sync(dev, sparx5_mc_sync, sparx5_mc_unsync); 166 } 167 168 static int sparx5_port_get_phys_port_name(struct net_device *dev, 169 char *buf, size_t len) 170 { 171 struct sparx5_port *port = netdev_priv(dev); 172 int ret; 173 174 ret = snprintf(buf, len, "p%d", port->portno); 175 if (ret >= len) 176 return -EINVAL; 177 178 return 0; 179 } 180 181 static int sparx5_set_mac_address(struct net_device *dev, void *p) 182 { 183 struct sparx5_port *port = netdev_priv(dev); 184 struct sparx5 *sparx5 = port->sparx5; 185 const struct sockaddr *addr = p; 186 187 if (!is_valid_ether_addr(addr->sa_data)) 188 return -EADDRNOTAVAIL; 189 190 /* Remove current */ 191 sparx5_mact_forget(sparx5, dev->dev_addr, port->pvid); 192 193 /* Add new */ 194 sparx5_mact_learn(sparx5, sparx5_get_pgid(sparx5, PGID_CPU), 195 addr->sa_data, port->pvid); 196 197 /* Record the address */ 198 eth_hw_addr_set(dev, addr->sa_data); 199 200 return 0; 201 } 202 203 static int sparx5_get_port_parent_id(struct net_device *dev, 204 struct netdev_phys_item_id *ppid) 205 { 206 struct sparx5_port *sparx5_port = netdev_priv(dev); 207 struct sparx5 *sparx5 = sparx5_port->sparx5; 208 209 ppid->id_len = sizeof(sparx5->base_mac); 210 memcpy(&ppid->id, &sparx5->base_mac, ppid->id_len); 211 212 return 0; 213 } 214 215 static int sparx5_port_hwtstamp_get(struct net_device *dev, 216 struct kernel_hwtstamp_config *cfg) 217 { 218 struct sparx5_port *sparx5_port = netdev_priv(dev); 219 struct sparx5 *sparx5 = sparx5_port->sparx5; 220 221 if (!sparx5->ptp) 222 return -EOPNOTSUPP; 223 224 sparx5_ptp_hwtstamp_get(sparx5_port, cfg); 225 226 return 0; 227 } 228 229 static int sparx5_port_hwtstamp_set(struct net_device *dev, 230 struct kernel_hwtstamp_config *cfg, 231 struct netlink_ext_ack *extack) 232 { 233 struct sparx5_port *sparx5_port = netdev_priv(dev); 234 struct sparx5 *sparx5 = sparx5_port->sparx5; 235 236 if (!sparx5->ptp) 237 return -EOPNOTSUPP; 238 239 return sparx5_ptp_hwtstamp_set(sparx5_port, cfg, extack); 240 } 241 242 static const struct net_device_ops sparx5_port_netdev_ops = { 243 .ndo_open = sparx5_port_open, 244 .ndo_stop = sparx5_port_stop, 245 .ndo_start_xmit = sparx5_port_xmit_impl, 246 .ndo_set_rx_mode = sparx5_set_rx_mode, 247 .ndo_get_phys_port_name = sparx5_port_get_phys_port_name, 248 .ndo_set_mac_address = sparx5_set_mac_address, 249 .ndo_validate_addr = eth_validate_addr, 250 .ndo_get_stats64 = sparx5_get_stats64, 251 .ndo_get_port_parent_id = sparx5_get_port_parent_id, 252 .ndo_eth_ioctl = phy_do_ioctl, 253 .ndo_setup_tc = sparx5_port_setup_tc, 254 .ndo_hwtstamp_get = sparx5_port_hwtstamp_get, 255 .ndo_hwtstamp_set = sparx5_port_hwtstamp_set, 256 }; 257 258 bool sparx5_netdevice_check(const struct net_device *dev) 259 { 260 return dev && (dev->netdev_ops == &sparx5_port_netdev_ops); 261 } 262 263 struct net_device *sparx5_create_netdev(struct sparx5 *sparx5, u32 portno) 264 { 265 struct sparx5_port *spx5_port; 266 struct net_device *ndev; 267 268 ndev = devm_alloc_etherdev_mqs(sparx5->dev, sizeof(struct sparx5_port), 269 SPX5_PRIOS, 1); 270 if (!ndev) 271 return ERR_PTR(-ENOMEM); 272 273 ndev->hw_features |= NETIF_F_HW_TC; 274 ndev->features |= NETIF_F_HW_TC; 275 276 SET_NETDEV_DEV(ndev, sparx5->dev); 277 spx5_port = netdev_priv(ndev); 278 spx5_port->ndev = ndev; 279 spx5_port->sparx5 = sparx5; 280 spx5_port->portno = portno; 281 282 ndev->netdev_ops = &sparx5_port_netdev_ops; 283 ndev->ethtool_ops = &sparx5_ethtool_ops; 284 285 eth_hw_addr_gen(ndev, sparx5->base_mac, portno + 1); 286 287 return ndev; 288 } 289 290 int sparx5_register_netdevs(struct sparx5 *sparx5) 291 { 292 int portno; 293 int err; 294 295 for (portno = 0; portno < sparx5->data->consts->n_ports; portno++) 296 if (sparx5->ports[portno]) { 297 err = register_netdev(sparx5->ports[portno]->ndev); 298 if (err) { 299 dev_err(sparx5->dev, 300 "port: %02u: netdev registration failed\n", 301 portno); 302 return err; 303 } 304 sparx5_port_inj_timer_setup(sparx5->ports[portno]); 305 } 306 return 0; 307 } 308 309 void sparx5_destroy_netdevs(struct sparx5 *sparx5) 310 { 311 struct sparx5_port *port; 312 int portno; 313 314 for (portno = 0; portno < sparx5->data->consts->n_ports; portno++) { 315 port = sparx5->ports[portno]; 316 if (port && port->phylink) { 317 /* Disconnect the phy */ 318 rtnl_lock(); 319 sparx5_port_stop(port->ndev); 320 phylink_disconnect_phy(port->phylink); 321 rtnl_unlock(); 322 phylink_destroy(port->phylink); 323 port->phylink = NULL; 324 } 325 } 326 } 327 328 void sparx5_unregister_netdevs(struct sparx5 *sparx5) 329 { 330 int portno; 331 332 for (portno = 0; portno < sparx5->data->consts->n_ports; portno++) 333 if (sparx5->ports[portno]) 334 unregister_netdev(sparx5->ports[portno]->ndev); 335 } 336