1 /* SPDX-License-Identifier: GPL-2.0+ 2 * Microchip Sparx5 Switch driver 3 * 4 * Copyright (c) 2024 Microchip Technology Inc. 5 */ 6 7 /* This file is autogenerated by cml-utils 2024-10-04 10:40:40 +0200. 8 * Commit ID: 9d07b8d19363f3cd3590ddb3f7a2e2768e16524b 9 */ 10 11 #ifndef _SPARX5_MAIN_REGS_H_ 12 #define _SPARX5_MAIN_REGS_H_ 13 14 #include <linux/bitfield.h> 15 #include <linux/types.h> 16 #include <linux/bug.h> 17 18 #include "sparx5_regs.h" 19 20 enum sparx5_target { 21 TARGET_ANA_AC = 1, 22 TARGET_ANA_ACL = 2, 23 TARGET_ANA_AC_POL = 4, 24 TARGET_ANA_AC_SDLB = 5, 25 TARGET_ANA_CL = 6, 26 TARGET_ANA_L2 = 7, 27 TARGET_ANA_L3 = 8, 28 TARGET_ASM = 9, 29 TARGET_CLKGEN = 11, 30 TARGET_CPU = 12, 31 TARGET_DEV10G = 17, 32 TARGET_DEV25G = 29, 33 TARGET_DEV2G5 = 37, 34 TARGET_DEV5G = 102, 35 TARGET_DSM = 115, 36 TARGET_EACL = 116, 37 TARGET_FDMA = 117, 38 TARGET_GCB = 118, 39 TARGET_HSCH = 119, 40 TARGET_LRN = 122, 41 TARGET_PCEP = 129, 42 TARGET_PCS10G_BR = 132, 43 TARGET_PCS25G_BR = 144, 44 TARGET_PCS5G_BR = 160, 45 TARGET_PORT_CONF = 173, 46 TARGET_PTP = 174, 47 TARGET_QFWD = 175, 48 TARGET_QRES = 176, 49 TARGET_QS = 177, 50 TARGET_QSYS = 178, 51 TARGET_REW = 179, 52 TARGET_VCAP_ES0 = 323, 53 TARGET_VCAP_ES2 = 324, 54 TARGET_VCAP_SUPER = 326, 55 TARGET_VOP = 327, 56 TARGET_XQS = 331, 57 NUM_TARGETS = 517 58 }; 59 60 /* sparx5_main.c 61 * 62 * This is used by the register macros to access chip differences (if any) in: 63 * target size, register address, register count, group address, group count, 64 * group size, field position and field size. 65 */ 66 extern const struct sparx5_regs *regs; 67 68 /* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */ 69 #define spx5_field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) 70 #define spx5_field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) 71 72 #define __REG(...) __VA_ARGS__ 73 74 /* ANA_AC:RAM_CTRL:RAM_INIT */ 75 #define ANA_AC_RAM_INIT \ 76 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_RAM_CTRL], 0, 1, 4, 0,\ 77 0, 1, 4) 78 79 #define ANA_AC_RAM_INIT_RAM_INIT BIT(1) 80 #define ANA_AC_RAM_INIT_RAM_INIT_SET(x)\ 81 FIELD_PREP(ANA_AC_RAM_INIT_RAM_INIT, x) 82 #define ANA_AC_RAM_INIT_RAM_INIT_GET(x)\ 83 FIELD_GET(ANA_AC_RAM_INIT_RAM_INIT, x) 84 85 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK BIT(0) 86 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_SET(x)\ 87 FIELD_PREP(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x) 88 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 89 FIELD_GET(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x) 90 91 /* ANA_AC:PS_COMMON:OWN_UPSID */ 92 #define ANA_AC_OWN_UPSID(r) \ 93 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_PS_COMMON], 0, 1, 352,\ 94 52, r, regs->rcnt[RC_ANA_AC_OWN_UPSID], 4) 95 96 #define ANA_AC_OWN_UPSID_OWN_UPSID GENMASK(4, 0) 97 #define ANA_AC_OWN_UPSID_OWN_UPSID_SET(x)\ 98 FIELD_PREP(ANA_AC_OWN_UPSID_OWN_UPSID, x) 99 #define ANA_AC_OWN_UPSID_OWN_UPSID_GET(x)\ 100 FIELD_GET(ANA_AC_OWN_UPSID_OWN_UPSID, x) 101 102 /* ANA_AC:MIRROR_PROBE:PROBE_CFG */ 103 #define ANA_AC_PROBE_CFG(g) \ 104 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_MIRROR_PROBE], g, 3, \ 105 32, 0, 0, 1, 4) 106 107 #define ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD GENMASK(31, 27) 108 #define ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD_SET(x)\ 109 FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD, x) 110 #define ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD_GET(x)\ 111 FIELD_GET(ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD, x) 112 113 #define ANA_AC_PROBE_CFG_PROBE_CPU_SET GENMASK(26, 19) 114 #define ANA_AC_PROBE_CFG_PROBE_CPU_SET_SET(x)\ 115 FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_CPU_SET, x) 116 #define ANA_AC_PROBE_CFG_PROBE_CPU_SET_GET(x)\ 117 FIELD_GET(ANA_AC_PROBE_CFG_PROBE_CPU_SET, x) 118 119 #define ANA_AC_PROBE_CFG_PROBE_VID GENMASK(18, 6) 120 #define ANA_AC_PROBE_CFG_PROBE_VID_SET(x)\ 121 FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_VID, x) 122 #define ANA_AC_PROBE_CFG_PROBE_VID_GET(x)\ 123 FIELD_GET(ANA_AC_PROBE_CFG_PROBE_VID, x) 124 125 #define ANA_AC_PROBE_CFG_PROBE_VLAN_MODE GENMASK(5, 4) 126 #define ANA_AC_PROBE_CFG_PROBE_VLAN_MODE_SET(x)\ 127 FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_VLAN_MODE, x) 128 #define ANA_AC_PROBE_CFG_PROBE_VLAN_MODE_GET(x)\ 129 FIELD_GET(ANA_AC_PROBE_CFG_PROBE_VLAN_MODE, x) 130 131 #define ANA_AC_PROBE_CFG_PROBE_MAC_MODE GENMASK(3, 2) 132 #define ANA_AC_PROBE_CFG_PROBE_MAC_MODE_SET(x)\ 133 FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_MAC_MODE, x) 134 #define ANA_AC_PROBE_CFG_PROBE_MAC_MODE_GET(x)\ 135 FIELD_GET(ANA_AC_PROBE_CFG_PROBE_MAC_MODE, x) 136 137 #define ANA_AC_PROBE_CFG_PROBE_DIRECTION GENMASK(1, 0) 138 #define ANA_AC_PROBE_CFG_PROBE_DIRECTION_SET(x)\ 139 FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_DIRECTION, x) 140 #define ANA_AC_PROBE_CFG_PROBE_DIRECTION_GET(x)\ 141 FIELD_GET(ANA_AC_PROBE_CFG_PROBE_DIRECTION, x) 142 143 /* ANA_AC:MIRROR_PROBE:PROBE_PORT_CFG */ 144 #define ANA_AC_PROBE_PORT_CFG(g) \ 145 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_MIRROR_PROBE], g, 3, \ 146 32, 8, 0, 1, 4) 147 148 /* SPARX5 ONLY */ 149 /* ANA_AC:MIRROR_PROBE:PROBE_PORT_CFG1 */ 150 #define ANA_AC_PROBE_PORT_CFG1(g) \ 151 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_MIRROR_PROBE], g, 3, \ 152 32, 12, 0, 1, 4) 153 154 /* SPARX5 ONLY */ 155 /* ANA_AC:MIRROR_PROBE:PROBE_PORT_CFG2 */ 156 #define ANA_AC_PROBE_PORT_CFG2(g) \ 157 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_MIRROR_PROBE], g, 3, \ 158 32, 16, 0, 1, 4) 159 160 #define ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2 BIT(0) 161 #define ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2_SET(x)\ 162 FIELD_PREP(ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2, x) 163 #define ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2_GET(x)\ 164 FIELD_GET(ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2, x) 165 166 /* ANA_AC:SRC:SRC_CFG */ 167 #define ANA_AC_SRC_CFG(g) \ 168 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SRC], g, \ 169 regs->gcnt[GC_ANA_AC_SRC], regs->gsize[GW_ANA_AC_SRC], 0, 0, 1, 4) 170 171 /* SPARX5 ONLY */ 172 /* ANA_AC:SRC:SRC_CFG1 */ 173 #define ANA_AC_SRC_CFG1(g) \ 174 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SRC], g, \ 175 regs->gcnt[GC_ANA_AC_SRC], regs->gsize[GW_ANA_AC_SRC], 4, 0, 1, 4) 176 177 /* SPARX5 ONLY */ 178 /* ANA_AC:SRC:SRC_CFG2 */ 179 #define ANA_AC_SRC_CFG2(g) \ 180 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SRC], g, \ 181 regs->gcnt[GC_ANA_AC_SRC], regs->gsize[GW_ANA_AC_SRC], 8, 0, 1, 4) 182 183 #define ANA_AC_SRC_CFG2_PORT_MASK2 BIT(0) 184 #define ANA_AC_SRC_CFG2_PORT_MASK2_SET(x)\ 185 FIELD_PREP(ANA_AC_SRC_CFG2_PORT_MASK2, x) 186 #define ANA_AC_SRC_CFG2_PORT_MASK2_GET(x)\ 187 FIELD_GET(ANA_AC_SRC_CFG2_PORT_MASK2, x) 188 189 /* ANA_AC:PGID:PGID_CFG */ 190 #define ANA_AC_PGID_CFG(g) \ 191 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_PGID], g, \ 192 regs->gcnt[GC_ANA_AC_PGID], 16, 0, 0, 1, 4) 193 194 /* SPARX5 ONLY */ 195 /* ANA_AC:PGID:PGID_CFG1 */ 196 #define ANA_AC_PGID_CFG1(g) \ 197 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_PGID], g, \ 198 regs->gcnt[GC_ANA_AC_PGID], 16, 4, 0, 1, 4) 199 200 /* SPARX5 ONLY */ 201 /* ANA_AC:PGID:PGID_CFG2 */ 202 #define ANA_AC_PGID_CFG2(g) \ 203 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_PGID], g, \ 204 regs->gcnt[GC_ANA_AC_PGID], 16, 8, 0, 1, 4) 205 206 #define ANA_AC_PGID_CFG2_PORT_MASK2 BIT(0) 207 #define ANA_AC_PGID_CFG2_PORT_MASK2_SET(x)\ 208 FIELD_PREP(ANA_AC_PGID_CFG2_PORT_MASK2, x) 209 #define ANA_AC_PGID_CFG2_PORT_MASK2_GET(x)\ 210 FIELD_GET(ANA_AC_PGID_CFG2_PORT_MASK2, x) 211 212 /* ANA_AC:PGID:PGID_MISC_CFG */ 213 #define ANA_AC_PGID_MISC_CFG(g) \ 214 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_PGID], g, \ 215 regs->gcnt[GC_ANA_AC_PGID], 16, 12, 0, 1, 4) 216 217 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU GENMASK(6, 4) 218 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU_SET(x)\ 219 FIELD_PREP(ANA_AC_PGID_MISC_CFG_PGID_CPU_QU, x) 220 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU_GET(x)\ 221 FIELD_GET(ANA_AC_PGID_MISC_CFG_PGID_CPU_QU, x) 222 223 #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA BIT(1) 224 #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA_SET(x)\ 225 FIELD_PREP(ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA, x) 226 #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA_GET(x)\ 227 FIELD_GET(ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA, x) 228 229 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA BIT(0) 230 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(x)\ 231 FIELD_PREP(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA, x) 232 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_GET(x)\ 233 FIELD_GET(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA, x) 234 235 /* ANA_AC:TSN_SF:TSN_SF */ 236 #define ANA_AC_TSN_SF \ 237 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_TSN_SF], 0, 1, 4, 0, \ 238 0, 1, 4) 239 240 #define ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY BIT(9) 241 #define ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY_SET(x)\ 242 FIELD_PREP(ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY, x) 243 #define ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY_GET(x)\ 244 FIELD_GET(ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY, x) 245 246 #define ANA_AC_TSN_SF_PORT_NUM\ 247 GENMASK(regs->fsize[FW_ANA_AC_TSN_SF_PORT_NUM] + 0 - 1, 0) 248 #define ANA_AC_TSN_SF_PORT_NUM_SET(x)\ 249 spx5_field_prep(ANA_AC_TSN_SF_PORT_NUM, x) 250 #define ANA_AC_TSN_SF_PORT_NUM_GET(x)\ 251 spx5_field_get(ANA_AC_TSN_SF_PORT_NUM, x) 252 253 /* ANA_AC:TSN_SF_CFG:TSN_SF_CFG */ 254 #define ANA_AC_TSN_SF_CFG(g) \ 255 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_TSN_SF_CFG], g, \ 256 regs->gcnt[GC_ANA_AC_TSN_SF_CFG], 4, 0, 0, 1, 4) 257 258 #define ANA_AC_TSN_SF_CFG_TSN_SGID\ 259 GENMASK(regs->fsize[FW_ANA_AC_TSN_SF_CFG_TSN_SGID] + 16 - 1, 16) 260 #define ANA_AC_TSN_SF_CFG_TSN_SGID_SET(x)\ 261 spx5_field_prep(ANA_AC_TSN_SF_CFG_TSN_SGID, x) 262 #define ANA_AC_TSN_SF_CFG_TSN_SGID_GET(x)\ 263 spx5_field_get(ANA_AC_TSN_SF_CFG_TSN_SGID, x) 264 265 #define ANA_AC_TSN_SF_CFG_TSN_MAX_SDU GENMASK(15, 2) 266 #define ANA_AC_TSN_SF_CFG_TSN_MAX_SDU_SET(x)\ 267 FIELD_PREP(ANA_AC_TSN_SF_CFG_TSN_MAX_SDU, x) 268 #define ANA_AC_TSN_SF_CFG_TSN_MAX_SDU_GET(x)\ 269 FIELD_GET(ANA_AC_TSN_SF_CFG_TSN_MAX_SDU, x) 270 271 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA BIT(1) 272 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA_SET(x)\ 273 FIELD_PREP(ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA, x) 274 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA_GET(x)\ 275 FIELD_GET(ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA, x) 276 277 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE BIT(0) 278 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE_SET(x)\ 279 FIELD_PREP(ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE, x) 280 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE_GET(x)\ 281 FIELD_GET(ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE, x) 282 283 /* ANA_AC:TSN_SF_STATUS:TSN_SF_STATUS */ 284 #define ANA_AC_TSN_SF_STATUS \ 285 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_TSN_SF_STATUS], 0, 1, \ 286 16, 0, 0, 1, 4) 287 288 #define ANA_AC_TSN_SF_STATUS_FRM_LEN GENMASK(25, 12) 289 #define ANA_AC_TSN_SF_STATUS_FRM_LEN_SET(x)\ 290 FIELD_PREP(ANA_AC_TSN_SF_STATUS_FRM_LEN, x) 291 #define ANA_AC_TSN_SF_STATUS_FRM_LEN_GET(x)\ 292 FIELD_GET(ANA_AC_TSN_SF_STATUS_FRM_LEN, x) 293 294 #define ANA_AC_TSN_SF_STATUS_DLB_DROP BIT(11) 295 #define ANA_AC_TSN_SF_STATUS_DLB_DROP_SET(x)\ 296 FIELD_PREP(ANA_AC_TSN_SF_STATUS_DLB_DROP, x) 297 #define ANA_AC_TSN_SF_STATUS_DLB_DROP_GET(x)\ 298 FIELD_GET(ANA_AC_TSN_SF_STATUS_DLB_DROP, x) 299 300 #define ANA_AC_TSN_SF_STATUS_TSN_SFID\ 301 GENMASK(regs->fsize[FW_ANA_AC_TSN_SF_STATUS_TSN_SFID] + 1 - 1, 1) 302 #define ANA_AC_TSN_SF_STATUS_TSN_SFID_SET(x)\ 303 spx5_field_prep(ANA_AC_TSN_SF_STATUS_TSN_SFID, x) 304 #define ANA_AC_TSN_SF_STATUS_TSN_SFID_GET(x)\ 305 spx5_field_get(ANA_AC_TSN_SF_STATUS_TSN_SFID, x) 306 307 #define ANA_AC_TSN_SF_STATUS_TSTAMP_VLD BIT(0) 308 #define ANA_AC_TSN_SF_STATUS_TSTAMP_VLD_SET(x)\ 309 FIELD_PREP(ANA_AC_TSN_SF_STATUS_TSTAMP_VLD, x) 310 #define ANA_AC_TSN_SF_STATUS_TSTAMP_VLD_GET(x)\ 311 FIELD_GET(ANA_AC_TSN_SF_STATUS_TSTAMP_VLD, x) 312 313 /* ANA_AC:SG_ACCESS:SG_ACCESS_CTRL */ 314 #define ANA_AC_SG_ACCESS_CTRL \ 315 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_ACCESS], 0, 1, 12, \ 316 0, 0, 1, 4) 317 318 #define ANA_AC_SG_ACCESS_CTRL_SGID\ 319 GENMASK(regs->fsize[FW_ANA_AC_SG_ACCESS_CTRL_SGID] + 0 - 1, 0) 320 #define ANA_AC_SG_ACCESS_CTRL_SGID_SET(x)\ 321 spx5_field_prep(ANA_AC_SG_ACCESS_CTRL_SGID, x) 322 #define ANA_AC_SG_ACCESS_CTRL_SGID_GET(x)\ 323 spx5_field_get(ANA_AC_SG_ACCESS_CTRL_SGID, x) 324 325 #define ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE BIT(28) 326 #define ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE_SET(x)\ 327 FIELD_PREP(ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE, x) 328 #define ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE_GET(x)\ 329 FIELD_GET(ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE, x) 330 331 /* ANA_AC:SG_ACCESS:SG_CYCLETIME_UPDATE_PERIOD */ 332 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD \ 333 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_ACCESS], 0, 1, 12, \ 334 8, 0, 1, 4) 335 336 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS GENMASK(15, 0) 337 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS_SET(x)\ 338 FIELD_PREP(ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS, x) 339 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS_GET(x)\ 340 FIELD_GET(ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS, x) 341 342 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA BIT(31) 343 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA_SET(x)\ 344 FIELD_PREP(ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA, x) 345 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA_GET(x)\ 346 FIELD_GET(ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA, x) 347 348 /* ANA_AC:SG_CONFIG:SG_CONFIG_REG_1 */ 349 #define ANA_AC_SG_CONFIG_REG_1 \ 350 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\ 351 48, 0, 1, 4) 352 353 /* ANA_AC:SG_CONFIG:SG_CONFIG_REG_2 */ 354 #define ANA_AC_SG_CONFIG_REG_2 \ 355 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\ 356 52, 0, 1, 4) 357 358 /* ANA_AC:SG_CONFIG:SG_CONFIG_REG_3 */ 359 #define ANA_AC_SG_CONFIG_REG_3 \ 360 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\ 361 56, 0, 1, 4) 362 363 #define ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB GENMASK(15, 0) 364 #define ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB_SET(x)\ 365 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB, x) 366 #define ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB_GET(x)\ 367 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB, x) 368 369 #define ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH GENMASK(18, 16) 370 #define ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH_SET(x)\ 371 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH, x) 372 #define ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH_GET(x)\ 373 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH, x) 374 375 #define ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE BIT(20) 376 #define ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE_SET(x)\ 377 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE, x) 378 #define ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE_GET(x)\ 379 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE, x) 380 381 #define ANA_AC_SG_CONFIG_REG_3_INIT_IPS GENMASK(24, 21) 382 #define ANA_AC_SG_CONFIG_REG_3_INIT_IPS_SET(x)\ 383 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_INIT_IPS, x) 384 #define ANA_AC_SG_CONFIG_REG_3_INIT_IPS_GET(x)\ 385 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_INIT_IPS, x) 386 387 #define ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE BIT(25) 388 #define ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE_SET(x)\ 389 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE, x) 390 #define ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE_GET(x)\ 391 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE, x) 392 393 #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA BIT(26) 394 #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA_SET(x)\ 395 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA, x) 396 #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA_GET(x)\ 397 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA, x) 398 399 #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX BIT(27) 400 #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_SET(x)\ 401 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_INVALID_RX, x) 402 #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_GET(x)\ 403 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_INVALID_RX, x) 404 405 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA BIT(28) 406 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA_SET(x)\ 407 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA, x) 408 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA_GET(x)\ 409 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA, x) 410 411 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED BIT(29) 412 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_SET(x)\ 413 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED, x) 414 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_GET(x)\ 415 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED, x) 416 417 /* ANA_AC:SG_CONFIG:SG_CONFIG_REG_4 */ 418 #define ANA_AC_SG_CONFIG_REG_4 \ 419 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\ 420 60, 0, 1, 4) 421 422 /* ANA_AC:SG_CONFIG:SG_CONFIG_REG_5 */ 423 #define ANA_AC_SG_CONFIG_REG_5 \ 424 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\ 425 64, 0, 1, 4) 426 427 /* ANA_AC:SG_CONFIG:SG_GCL_GS_CONFIG */ 428 #define ANA_AC_SG_GCL_GS_CONFIG(r) \ 429 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\ 430 0, r, 4, 4) 431 432 #define ANA_AC_SG_GCL_GS_CONFIG_IPS GENMASK(3, 0) 433 #define ANA_AC_SG_GCL_GS_CONFIG_IPS_SET(x)\ 434 FIELD_PREP(ANA_AC_SG_GCL_GS_CONFIG_IPS, x) 435 #define ANA_AC_SG_GCL_GS_CONFIG_IPS_GET(x)\ 436 FIELD_GET(ANA_AC_SG_GCL_GS_CONFIG_IPS, x) 437 438 #define ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE BIT(4) 439 #define ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE_SET(x)\ 440 FIELD_PREP(ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE, x) 441 #define ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE_GET(x)\ 442 FIELD_GET(ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE, x) 443 444 /* ANA_AC:SG_CONFIG:SG_GCL_TI_CONFIG */ 445 #define ANA_AC_SG_GCL_TI_CONFIG(r) \ 446 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\ 447 16, r, 4, 4) 448 449 /* ANA_AC:SG_CONFIG:SG_GCL_OCT_CONFIG */ 450 #define ANA_AC_SG_GCL_OCT_CONFIG(r) \ 451 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\ 452 32, r, 4, 4) 453 454 /* ANA_AC:SG_STATUS:SG_STATUS_REG_1 */ 455 #define ANA_AC_SG_STATUS_REG_1 \ 456 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_STATUS], 0, 1, 16, \ 457 0, 0, 1, 4) 458 459 /* ANA_AC:SG_STATUS:SG_STATUS_REG_2 */ 460 #define ANA_AC_SG_STATUS_REG_2 \ 461 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_STATUS], 0, 1, 16, \ 462 4, 0, 1, 4) 463 464 /* ANA_AC:SG_STATUS:SG_STATUS_REG_3 */ 465 #define ANA_AC_SG_STATUS_REG_3 \ 466 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_STATUS], 0, 1, 16, \ 467 8, 0, 1, 4) 468 469 #define ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB GENMASK(15, 0) 470 #define ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB_SET(x)\ 471 FIELD_PREP(ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB, x) 472 #define ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB_GET(x)\ 473 FIELD_GET(ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB, x) 474 475 #define ANA_AC_SG_STATUS_REG_3_GATE_STATE BIT(16) 476 #define ANA_AC_SG_STATUS_REG_3_GATE_STATE_SET(x)\ 477 FIELD_PREP(ANA_AC_SG_STATUS_REG_3_GATE_STATE, x) 478 #define ANA_AC_SG_STATUS_REG_3_GATE_STATE_GET(x)\ 479 FIELD_GET(ANA_AC_SG_STATUS_REG_3_GATE_STATE, x) 480 481 #define ANA_AC_SG_STATUS_REG_3_IPS GENMASK(23, 20) 482 #define ANA_AC_SG_STATUS_REG_3_IPS_SET(x)\ 483 FIELD_PREP(ANA_AC_SG_STATUS_REG_3_IPS, x) 484 #define ANA_AC_SG_STATUS_REG_3_IPS_GET(x)\ 485 FIELD_GET(ANA_AC_SG_STATUS_REG_3_IPS, x) 486 487 #define ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING BIT(24) 488 #define ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING_SET(x)\ 489 FIELD_PREP(ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING, x) 490 #define ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING_GET(x)\ 491 FIELD_GET(ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING, x) 492 493 #define ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX GENMASK(27, 25) 494 #define ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX_SET(x)\ 495 FIELD_PREP(ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX, x) 496 #define ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX_GET(x)\ 497 FIELD_GET(ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX, x) 498 499 /* ANA_AC:SG_STATUS:SG_STATUS_REG_4 */ 500 #define ANA_AC_SG_STATUS_REG_4 \ 501 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_STATUS], 0, 1, 16, \ 502 12, 0, 1, 4) 503 504 /* ANA_AC:STAT_GLOBAL_CFG_PORT:STAT_GLOBAL_EVENT_MASK */ 505 #define ANA_AC_PORT_SGE_CFG(r) \ 506 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_GLOBAL_CFG_PORT],\ 507 0, 1, 20, 0, r, 4, 4) 508 509 #define ANA_AC_PORT_SGE_CFG_MASK\ 510 GENMASK(regs->fsize[FW_ANA_AC_PORT_SGE_CFG_MASK] + 0 - 1, 0) 511 #define ANA_AC_PORT_SGE_CFG_MASK_SET(x)\ 512 spx5_field_prep(ANA_AC_PORT_SGE_CFG_MASK, x) 513 #define ANA_AC_PORT_SGE_CFG_MASK_GET(x)\ 514 spx5_field_get(ANA_AC_PORT_SGE_CFG_MASK, x) 515 516 /* ANA_AC:STAT_GLOBAL_CFG_PORT:STAT_RESET */ 517 #define ANA_AC_STAT_RESET \ 518 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_GLOBAL_CFG_PORT],\ 519 0, 1, 20, 16, 0, 1, 4) 520 521 #define ANA_AC_STAT_RESET_RESET BIT(0) 522 #define ANA_AC_STAT_RESET_RESET_SET(x)\ 523 FIELD_PREP(ANA_AC_STAT_RESET_RESET, x) 524 #define ANA_AC_STAT_RESET_RESET_GET(x)\ 525 FIELD_GET(ANA_AC_STAT_RESET_RESET, x) 526 527 /* ANA_AC:STAT_CNT_CFG_PORT:STAT_CFG */ 528 #define ANA_AC_PORT_STAT_CFG(g, r) \ 529 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_CNT_CFG_PORT], g,\ 530 regs->gcnt[GC_ANA_AC_STAT_CNT_CFG_PORT], 64, 4, r, 4, 4) 531 532 #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK GENMASK(11, 4) 533 #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK_SET(x)\ 534 FIELD_PREP(ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK, x) 535 #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK_GET(x)\ 536 FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK, x) 537 538 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE GENMASK(3, 1) 539 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE_SET(x)\ 540 FIELD_PREP(ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE, x) 541 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE_GET(x)\ 542 FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE, x) 543 544 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE BIT(0) 545 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE_SET(x)\ 546 FIELD_PREP(ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE, x) 547 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE_GET(x)\ 548 FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE, x) 549 550 /* ANA_AC:STAT_CNT_CFG_PORT:STAT_LSB_CNT */ 551 #define ANA_AC_PORT_STAT_LSB_CNT(g, r) \ 552 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_CNT_CFG_PORT], g,\ 553 regs->gcnt[GC_ANA_AC_STAT_CNT_CFG_PORT], 64, 20, r, 4, 4) 554 555 /* ANA_AC:STAT_GLOBAL_CFG_ACL:GLOBAL_CNT_FRM_TYPE_CFG */ 556 #define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG(r) \ 557 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_GLOBAL_CFG_ACL], \ 558 0, 1, 24, 0, r, 2, 4) 559 560 #define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE GENMASK(2, 0) 561 #define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE_SET(x)\ 562 FIELD_PREP(ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE, x) 563 #define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE_GET(x)\ 564 FIELD_GET(ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE, x) 565 566 /* ANA_AC:STAT_GLOBAL_CFG_ACL:STAT_GLOBAL_CFG */ 567 #define ANA_AC_ACL_STAT_GLOBAL_CFG(r) \ 568 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_GLOBAL_CFG_ACL], \ 569 0, 1, 24, 8, r, 2, 4) 570 571 #define ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE BIT(0) 572 #define ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE_SET(x)\ 573 FIELD_PREP(ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE, x) 574 #define ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE_GET(x)\ 575 FIELD_GET(ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE, x) 576 577 /* ANA_AC:STAT_GLOBAL_CFG_ACL:STAT_GLOBAL_EVENT_MASK */ 578 #define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK(r) \ 579 __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_GLOBAL_CFG_ACL], \ 580 0, 1, 24, 16, r, 2, 4) 581 582 #define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK GENMASK(3, 0) 583 #define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK_SET(x)\ 584 FIELD_PREP(ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK, x) 585 #define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK_GET(x)\ 586 FIELD_GET(ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK, x) 587 588 /* ANA_ACL:COMMON:VCAP_S2_CFG */ 589 #define ANA_ACL_VCAP_S2_CFG(r) \ 590 __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_COMMON], 0, 1, 592, \ 591 0, r, regs->rcnt[RC_ANA_ACL_VCAP_S2_CFG], 4) 592 593 #define ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA BIT(28) 594 #define ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA_SET(x)\ 595 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA, x) 596 #define ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA_GET(x)\ 597 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA, x) 598 599 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA GENMASK(27, 26) 600 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA_SET(x)\ 601 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA, x) 602 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA_GET(x)\ 603 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA, x) 604 605 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA GENMASK(25, 24) 606 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA_SET(x)\ 607 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA, x) 608 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA_GET(x)\ 609 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA, x) 610 611 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA GENMASK(23, 22) 612 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA_SET(x)\ 613 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA, x) 614 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA_GET(x)\ 615 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA, x) 616 617 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA GENMASK(21, 20) 618 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA_SET(x)\ 619 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA, x) 620 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA_GET(x)\ 621 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA, x) 622 623 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA GENMASK(19, 18) 624 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA_SET(x)\ 625 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA, x) 626 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA_GET(x)\ 627 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA, x) 628 629 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA GENMASK(17, 16) 630 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA_SET(x)\ 631 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA, x) 632 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA_GET(x)\ 633 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA, x) 634 635 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA GENMASK(15, 14) 636 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA_SET(x)\ 637 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA, x) 638 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA_GET(x)\ 639 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA, x) 640 641 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA GENMASK(13, 12) 642 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA_SET(x)\ 643 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA, x) 644 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA_GET(x)\ 645 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA, x) 646 647 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA GENMASK(11, 10) 648 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA_SET(x)\ 649 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA, x) 650 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA_GET(x)\ 651 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA, x) 652 653 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA GENMASK(9, 8) 654 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA_SET(x)\ 655 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA, x) 656 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA_GET(x)\ 657 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA, x) 658 659 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA GENMASK(7, 6) 660 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA_SET(x)\ 661 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA, x) 662 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA_GET(x)\ 663 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA, x) 664 665 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA GENMASK(5, 4) 666 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA_SET(x)\ 667 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA, x) 668 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA_GET(x)\ 669 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA, x) 670 671 #define ANA_ACL_VCAP_S2_CFG_SEC_ENA GENMASK(3, 0) 672 #define ANA_ACL_VCAP_S2_CFG_SEC_ENA_SET(x)\ 673 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_ENA, x) 674 #define ANA_ACL_VCAP_S2_CFG_SEC_ENA_GET(x)\ 675 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_ENA, x) 676 677 /* ANA_ACL:COMMON:SWAP_IP_CTRL */ 678 #define ANA_ACL_SWAP_IP_CTRL \ 679 __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_COMMON], 0, 1, 592, \ 680 412, 0, 1, 4) 681 682 #define ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL GENMASK(23, 18) 683 #define ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL_SET(x)\ 684 FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL, x) 685 #define ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL_GET(x)\ 686 FIELD_GET(ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL, x) 687 688 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL GENMASK(17, 10) 689 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL_SET(x)\ 690 FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL, x) 691 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL_GET(x)\ 692 FIELD_GET(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL, x) 693 694 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL GENMASK(9, 2) 695 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL_SET(x)\ 696 FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL, x) 697 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL_GET(x)\ 698 FIELD_GET(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL, x) 699 700 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA BIT(1) 701 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA_SET(x)\ 702 FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA, x) 703 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA_GET(x)\ 704 FIELD_GET(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA, x) 705 706 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA BIT(0) 707 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA_SET(x)\ 708 FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA, x) 709 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA_GET(x)\ 710 FIELD_GET(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA, x) 711 712 /* ANA_ACL:COMMON:VCAP_S2_RLEG_STAT */ 713 #define ANA_ACL_VCAP_S2_RLEG_STAT(r) \ 714 __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_COMMON], 0, 1, 592, \ 715 424, r, 4, 4) 716 717 #define ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK GENMASK(12, 6) 718 #define ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK_SET(x)\ 719 FIELD_PREP(ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK, x) 720 #define ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK_GET(x)\ 721 FIELD_GET(ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK, x) 722 723 #define ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK GENMASK(5, 0) 724 #define ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK_SET(x)\ 725 FIELD_PREP(ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK, x) 726 #define ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK_GET(x)\ 727 FIELD_GET(ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK, x) 728 729 /* ANA_ACL:COMMON:VCAP_S2_FRAGMENT_CFG */ 730 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG \ 731 __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_COMMON], 0, 1, 592, \ 732 440, 0, 1, 4) 733 734 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN GENMASK(9, 5) 735 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN_SET(x)\ 736 FIELD_PREP(ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN, x) 737 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN_GET(x)\ 738 FIELD_GET(ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN, x) 739 740 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS BIT(4) 741 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS_SET(x)\ 742 FIELD_PREP(ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS, x) 743 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS_GET(x)\ 744 FIELD_GET(ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS, x) 745 746 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES GENMASK(3, 0) 747 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_SET(x)\ 748 FIELD_PREP(ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES, x) 749 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_GET(x)\ 750 FIELD_GET(ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES, x) 751 752 /* ANA_ACL:COMMON:OWN_UPSID */ 753 #define ANA_ACL_OWN_UPSID(r) \ 754 __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_COMMON], 0, 1, 592, \ 755 580, r, regs->rcnt[RC_ANA_ACL_OWN_UPSID], 4) 756 757 #define ANA_ACL_OWN_UPSID_OWN_UPSID GENMASK(4, 0) 758 #define ANA_ACL_OWN_UPSID_OWN_UPSID_SET(x)\ 759 FIELD_PREP(ANA_ACL_OWN_UPSID_OWN_UPSID, x) 760 #define ANA_ACL_OWN_UPSID_OWN_UPSID_GET(x)\ 761 FIELD_GET(ANA_ACL_OWN_UPSID_OWN_UPSID, x) 762 763 /* ANA_ACL:KEY_SEL:VCAP_S2_KEY_SEL */ 764 #define ANA_ACL_VCAP_S2_KEY_SEL(g, r) \ 765 __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_KEY_SEL], g, \ 766 regs->gcnt[GC_ANA_ACL_KEY_SEL], 16, 0, r, 4, 4) 767 768 #define ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA BIT(13) 769 #define ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA_SET(x)\ 770 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA, x) 771 #define ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA_GET(x)\ 772 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA, x) 773 774 #define ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL BIT(12) 775 #define ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL_SET(x)\ 776 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL, x) 777 #define ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL_GET(x)\ 778 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL, x) 779 780 #define ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL GENMASK(11, 10) 781 #define ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL_SET(x)\ 782 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL, x) 783 #define ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL_GET(x)\ 784 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL, x) 785 786 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL GENMASK(9, 8) 787 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL_SET(x)\ 788 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL, x) 789 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL_GET(x)\ 790 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL, x) 791 792 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL GENMASK(7, 6) 793 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL_SET(x)\ 794 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL, x) 795 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL_GET(x)\ 796 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL, x) 797 798 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL GENMASK(5, 3) 799 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL_SET(x)\ 800 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL, x) 801 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL_GET(x)\ 802 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL, x) 803 804 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL GENMASK(2, 1) 805 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL_SET(x)\ 806 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL, x) 807 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL_GET(x)\ 808 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL, x) 809 810 #define ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL BIT(0) 811 #define ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL_SET(x)\ 812 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL, x) 813 #define ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL_GET(x)\ 814 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL, x) 815 816 /* ANA_ACL:CNT_A:CNT_A */ 817 #define ANA_ACL_CNT_A(g) \ 818 __REG(TARGET_ANA_ACL, 0, 1, 0, g, regs->gcnt[GC_ANA_ACL_CNT_A], 4, 0, \ 819 0, 1, 4) 820 821 /* ANA_ACL:CNT_B:CNT_B */ 822 #define ANA_ACL_CNT_B(g) \ 823 __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_CNT_B], g, \ 824 regs->gcnt[GC_ANA_ACL_CNT_B], 4, 0, 0, 1, 4) 825 826 /* ANA_ACL:STICKY:SEC_LOOKUP_STICKY */ 827 #define ANA_ACL_SEC_LOOKUP_STICKY(r) \ 828 __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_STICKY], 0, 1, 16, \ 829 0, r, 4, 4) 830 831 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY BIT(17) 832 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY_SET(x)\ 833 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY, x) 834 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY_GET(x)\ 835 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY, x) 836 837 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY BIT(16) 838 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY_SET(x)\ 839 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY, x) 840 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY_GET(x)\ 841 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY, x) 842 843 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY BIT(15) 844 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY_SET(x)\ 845 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY, x) 846 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY_GET(x)\ 847 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY, x) 848 849 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY BIT(14) 850 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY_SET(x)\ 851 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY, x) 852 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY_GET(x)\ 853 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY, x) 854 855 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY BIT(13) 856 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY_SET(x)\ 857 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY, x) 858 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY_GET(x)\ 859 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY, x) 860 861 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY BIT(12) 862 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY_SET(x)\ 863 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY, x) 864 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY_GET(x)\ 865 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY, x) 866 867 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY BIT(11) 868 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY_SET(x)\ 869 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY, x) 870 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY_GET(x)\ 871 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY, x) 872 873 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY BIT(10) 874 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_SET(x)\ 875 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY, x) 876 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_GET(x)\ 877 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY, x) 878 879 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY BIT(9) 880 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_SET(x)\ 881 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY, x) 882 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_GET(x)\ 883 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY, x) 884 885 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY BIT(8) 886 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY_SET(x)\ 887 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY, x) 888 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY_GET(x)\ 889 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY, x) 890 891 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY BIT(7) 892 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_SET(x)\ 893 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY, x) 894 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_GET(x)\ 895 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY, x) 896 897 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY BIT(6) 898 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_SET(x)\ 899 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY, x) 900 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_GET(x)\ 901 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY, x) 902 903 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY BIT(5) 904 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_SET(x)\ 905 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY, x) 906 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_GET(x)\ 907 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY, x) 908 909 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY BIT(4) 910 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_SET(x)\ 911 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY, x) 912 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_GET(x)\ 913 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY, x) 914 915 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY BIT(3) 916 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_SET(x)\ 917 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY, x) 918 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_GET(x)\ 919 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY, x) 920 921 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY BIT(2) 922 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY_SET(x)\ 923 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY, x) 924 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY_GET(x)\ 925 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY, x) 926 927 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY BIT(1) 928 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY_SET(x)\ 929 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY, x) 930 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY_GET(x)\ 931 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY, x) 932 933 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY BIT(0) 934 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_SET(x)\ 935 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY, x) 936 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_GET(x)\ 937 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY, x) 938 939 /* ANA_AC_POL:POL_ALL_CFG:POL_UPD_INT_CFG */ 940 #define ANA_AC_POL_POL_UPD_INT_CFG \ 941 __REG(TARGET_ANA_AC_POL, 0, 1, regs->gaddr[GA_ANA_AC_POL_POL_ALL_CFG], \ 942 0, 1, 1160, 1148, 0, 1, 4) 943 944 #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT GENMASK(9, 0) 945 #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_SET(x)\ 946 FIELD_PREP(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT, x) 947 #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_GET(x)\ 948 FIELD_GET(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT, x) 949 950 /* ANA_AC_POL:COMMON_BDLB:DLB_CTRL */ 951 #define ANA_AC_POL_BDLB_DLB_CTRL \ 952 __REG(TARGET_ANA_AC_POL, 0, 1, regs->gaddr[GA_ANA_AC_POL_COMMON_BDLB], \ 953 0, 1, 8, 0, 0, 1, 4) 954 955 #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS GENMASK(26, 19) 956 #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_SET(x)\ 957 FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS, x) 958 #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_GET(x)\ 959 FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS, x) 960 961 #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT GENMASK(18, 4) 962 #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT_SET(x)\ 963 FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT, x) 964 #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT_GET(x)\ 965 FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT, x) 966 967 #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA BIT(1) 968 #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA_SET(x)\ 969 FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA, x) 970 #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA_GET(x)\ 971 FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA, x) 972 973 #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA BIT(0) 974 #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA_SET(x)\ 975 FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA, x) 976 #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA_GET(x)\ 977 FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA, x) 978 979 /* ANA_AC_POL:COMMON_BUM_SLB:DLB_CTRL */ 980 #define ANA_AC_POL_SLB_DLB_CTRL \ 981 __REG(TARGET_ANA_AC_POL, 0, 1, \ 982 regs->gaddr[GA_ANA_AC_POL_COMMON_BUM_SLB], 0, 1, 20, 0, 0, 1, 4) 983 984 #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS GENMASK(26, 19) 985 #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_SET(x)\ 986 FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS, x) 987 #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_GET(x)\ 988 FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS, x) 989 990 #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT GENMASK(18, 4) 991 #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT_SET(x)\ 992 FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT, x) 993 #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT_GET(x)\ 994 FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT, x) 995 996 #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA BIT(1) 997 #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA_SET(x)\ 998 FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA, x) 999 #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA_GET(x)\ 1000 FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA, x) 1001 1002 #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA BIT(0) 1003 #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA_SET(x)\ 1004 FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA, x) 1005 #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA_GET(x)\ 1006 FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA, x) 1007 1008 /* ANA_AC_SDLB:LBGRP_TBL:XLB_START */ 1009 #define ANA_AC_SDLB_XLB_START(g) \ 1010 __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \ 1011 g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 0, 0, 1, 4) 1012 1013 #define ANA_AC_SDLB_XLB_START_LBSET_START\ 1014 GENMASK(regs->fsize[FW_ANA_AC_SDLB_XLB_START_LBSET_START] + 0 - 1, 0) 1015 #define ANA_AC_SDLB_XLB_START_LBSET_START_SET(x)\ 1016 spx5_field_prep(ANA_AC_SDLB_XLB_START_LBSET_START, x) 1017 #define ANA_AC_SDLB_XLB_START_LBSET_START_GET(x)\ 1018 spx5_field_get(ANA_AC_SDLB_XLB_START_LBSET_START, x) 1019 1020 /* ANA_AC_SDLB:LBGRP_TBL:PUP_INTERVAL */ 1021 #define ANA_AC_SDLB_PUP_INTERVAL(g) \ 1022 __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \ 1023 g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 4, 0, 1, 4) 1024 1025 #define ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL GENMASK(19, 0) 1026 #define ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL_SET(x)\ 1027 FIELD_PREP(ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL, x) 1028 #define ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL_GET(x)\ 1029 FIELD_GET(ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL, x) 1030 1031 /* ANA_AC_SDLB:LBGRP_TBL:PUP_CTRL */ 1032 #define ANA_AC_SDLB_PUP_CTRL(g) \ 1033 __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \ 1034 g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 8, 0, 1, 4) 1035 1036 #define ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT GENMASK(18, 0) 1037 #define ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT_SET(x)\ 1038 FIELD_PREP(ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT, x) 1039 #define ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT_GET(x)\ 1040 FIELD_GET(ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT, x) 1041 1042 #define ANA_AC_SDLB_PUP_CTRL_PUP_ENA BIT(24) 1043 #define ANA_AC_SDLB_PUP_CTRL_PUP_ENA_SET(x)\ 1044 FIELD_PREP(ANA_AC_SDLB_PUP_CTRL_PUP_ENA, x) 1045 #define ANA_AC_SDLB_PUP_CTRL_PUP_ENA_GET(x)\ 1046 FIELD_GET(ANA_AC_SDLB_PUP_CTRL_PUP_ENA, x) 1047 1048 /* ANA_AC_SDLB:LBGRP_TBL:LBGRP_MISC */ 1049 #define ANA_AC_SDLB_LBGRP_MISC(g) \ 1050 __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \ 1051 g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 12, 0, 1, 4) 1052 1053 #define ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT\ 1054 GENMASK(regs->fsize[FW_ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT] + 8 - 1, 8) 1055 #define ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT_SET(x)\ 1056 spx5_field_prep(ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT, x) 1057 #define ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT_GET(x)\ 1058 spx5_field_get(ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT, x) 1059 1060 /* ANA_AC_SDLB:LBGRP_TBL:FRM_RATE_TOKENS */ 1061 #define ANA_AC_SDLB_FRM_RATE_TOKENS(g) \ 1062 __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \ 1063 g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 16, 0, 1, 4) 1064 1065 #define ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS GENMASK(12, 0) 1066 #define ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS_SET(x)\ 1067 FIELD_PREP(ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS, x) 1068 #define ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS_GET(x)\ 1069 FIELD_GET(ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS, x) 1070 1071 /* ANA_AC_SDLB:LBGRP_TBL:LBGRP_STATE_TBL */ 1072 #define ANA_AC_SDLB_LBGRP_STATE_TBL(g) \ 1073 __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \ 1074 g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 20, 0, 1, 4) 1075 1076 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING BIT(0) 1077 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING_SET(x)\ 1078 FIELD_PREP(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING, x) 1079 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING_GET(x)\ 1080 FIELD_GET(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING, x) 1081 1082 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK BIT(1) 1083 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK_SET(x)\ 1084 FIELD_PREP(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK, x) 1085 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK_GET(x)\ 1086 FIELD_GET(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK, x) 1087 1088 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT\ 1089 GENMASK(regs->fsize[FW_ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT] + 16 - 1, 16) 1090 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT_SET(x)\ 1091 spx5_field_prep(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT, x) 1092 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT_GET(x)\ 1093 spx5_field_get(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT, x) 1094 1095 /* ANA_AC_SDLB:LBSET_TBL:PUP_TOKENS */ 1096 #define ANA_AC_SDLB_PUP_TOKENS(g, r) \ 1097 __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \ 1098 regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 0, r, 2, 4) 1099 1100 #define ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS GENMASK(12, 0) 1101 #define ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS_SET(x)\ 1102 FIELD_PREP(ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS, x) 1103 #define ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS_GET(x)\ 1104 FIELD_GET(ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS, x) 1105 1106 /* ANA_AC_SDLB:LBSET_TBL:THRES */ 1107 #define ANA_AC_SDLB_THRES(g, r) \ 1108 __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \ 1109 regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 8, r, 2, 4) 1110 1111 #define ANA_AC_SDLB_THRES_THRES GENMASK(9, 0) 1112 #define ANA_AC_SDLB_THRES_THRES_SET(x)\ 1113 FIELD_PREP(ANA_AC_SDLB_THRES_THRES, x) 1114 #define ANA_AC_SDLB_THRES_THRES_GET(x)\ 1115 FIELD_GET(ANA_AC_SDLB_THRES_THRES, x) 1116 1117 #define ANA_AC_SDLB_THRES_THRES_HYS GENMASK(25, 16) 1118 #define ANA_AC_SDLB_THRES_THRES_HYS_SET(x)\ 1119 FIELD_PREP(ANA_AC_SDLB_THRES_THRES_HYS, x) 1120 #define ANA_AC_SDLB_THRES_THRES_HYS_GET(x)\ 1121 FIELD_GET(ANA_AC_SDLB_THRES_THRES_HYS, x) 1122 1123 /* ANA_AC_SDLB:LBSET_TBL:XLB_NEXT */ 1124 #define ANA_AC_SDLB_XLB_NEXT(g) \ 1125 __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \ 1126 regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 16, 0, 1, 4) 1127 1128 #define ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT\ 1129 GENMASK(regs->fsize[FW_ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT] + 0 - 1, 0) 1130 #define ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT_SET(x)\ 1131 spx5_field_prep(ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT, x) 1132 #define ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT_GET(x)\ 1133 spx5_field_get(ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT, x) 1134 1135 #define ANA_AC_SDLB_XLB_NEXT_LBGRP\ 1136 GENMASK(regs->fsize[FW_ANA_AC_SDLB_XLB_NEXT_LBGRP] + 24 - 1, 24) 1137 #define ANA_AC_SDLB_XLB_NEXT_LBGRP_SET(x)\ 1138 spx5_field_prep(ANA_AC_SDLB_XLB_NEXT_LBGRP, x) 1139 #define ANA_AC_SDLB_XLB_NEXT_LBGRP_GET(x)\ 1140 spx5_field_get(ANA_AC_SDLB_XLB_NEXT_LBGRP, x) 1141 1142 /* ANA_AC_SDLB:LBSET_TBL:INH_CTRL */ 1143 #define ANA_AC_SDLB_INH_CTRL(g, r) \ 1144 __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \ 1145 regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 20, r, 2, 4) 1146 1147 #define ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX GENMASK(12, 0) 1148 #define ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX_SET(x)\ 1149 FIELD_PREP(ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX, x) 1150 #define ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX_GET(x)\ 1151 FIELD_GET(ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX, x) 1152 1153 #define ANA_AC_SDLB_INH_CTRL_INH_MODE GENMASK(21, 20) 1154 #define ANA_AC_SDLB_INH_CTRL_INH_MODE_SET(x)\ 1155 FIELD_PREP(ANA_AC_SDLB_INH_CTRL_INH_MODE, x) 1156 #define ANA_AC_SDLB_INH_CTRL_INH_MODE_GET(x)\ 1157 FIELD_GET(ANA_AC_SDLB_INH_CTRL_INH_MODE, x) 1158 1159 #define ANA_AC_SDLB_INH_CTRL_INH_LB BIT(24) 1160 #define ANA_AC_SDLB_INH_CTRL_INH_LB_SET(x)\ 1161 FIELD_PREP(ANA_AC_SDLB_INH_CTRL_INH_LB, x) 1162 #define ANA_AC_SDLB_INH_CTRL_INH_LB_GET(x)\ 1163 FIELD_GET(ANA_AC_SDLB_INH_CTRL_INH_LB, x) 1164 1165 /* ANA_AC_SDLB:LBSET_TBL:INH_LBSET_ADDR */ 1166 #define ANA_AC_SDLB_INH_LBSET_ADDR(g) \ 1167 __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \ 1168 regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 28, 0, 1, 4) 1169 1170 #define ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR\ 1171 GENMASK(regs->fsize[FW_ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR] + 0 - 1, 0) 1172 #define ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR_SET(x)\ 1173 spx5_field_prep(ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR, x) 1174 #define ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR_GET(x)\ 1175 spx5_field_get(ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR, x) 1176 1177 /* ANA_AC_SDLB:LBSET_TBL:DLB_MISC */ 1178 #define ANA_AC_SDLB_DLB_MISC(g) \ 1179 __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \ 1180 regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 32, 0, 1, 4) 1181 1182 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA BIT(0) 1183 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA_SET(x)\ 1184 FIELD_PREP(ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA, x) 1185 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA_GET(x)\ 1186 FIELD_GET(ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA, x) 1187 1188 #define ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA BIT(6) 1189 #define ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA_SET(x)\ 1190 FIELD_PREP(ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA, x) 1191 #define ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA_GET(x)\ 1192 FIELD_GET(ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA, x) 1193 1194 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ GENMASK(14, 8) 1195 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ_SET(x)\ 1196 FIELD_PREP(ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ, x) 1197 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ_GET(x)\ 1198 FIELD_GET(ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ, x) 1199 1200 /* ANA_AC_SDLB:LBSET_TBL:DLB_CFG */ 1201 #define ANA_AC_SDLB_DLB_CFG(g) \ 1202 __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \ 1203 regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 36, 0, 1, 4) 1204 1205 #define ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA BIT(11) 1206 #define ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA_SET(x)\ 1207 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA, x) 1208 #define ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA_GET(x)\ 1209 FIELD_GET(ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA, x) 1210 1211 #define ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL GENMASK(10, 9) 1212 #define ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL_SET(x)\ 1213 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL, x) 1214 #define ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL_GET(x)\ 1215 FIELD_GET(ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL, x) 1216 1217 #define ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS BIT(8) 1218 #define ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS_SET(x)\ 1219 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS, x) 1220 #define ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS_GET(x)\ 1221 FIELD_GET(ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS, x) 1222 1223 #define ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS BIT(7) 1224 #define ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS_SET(x)\ 1225 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS, x) 1226 #define ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS_GET(x)\ 1227 FIELD_GET(ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS, x) 1228 1229 #define ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL GENMASK(6, 5) 1230 #define ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL_SET(x)\ 1231 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL, x) 1232 #define ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL_GET(x)\ 1233 FIELD_GET(ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL, x) 1234 1235 #define ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL GENMASK(4, 3) 1236 #define ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL_SET(x)\ 1237 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL, x) 1238 #define ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL_GET(x)\ 1239 FIELD_GET(ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL, x) 1240 1241 #define ANA_AC_SDLB_DLB_CFG_DLB_MODE BIT(2) 1242 #define ANA_AC_SDLB_DLB_CFG_DLB_MODE_SET(x)\ 1243 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_DLB_MODE, x) 1244 #define ANA_AC_SDLB_DLB_CFG_DLB_MODE_GET(x)\ 1245 FIELD_GET(ANA_AC_SDLB_DLB_CFG_DLB_MODE, x) 1246 1247 #define ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK GENMASK(1, 0) 1248 #define ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK_SET(x)\ 1249 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK, x) 1250 #define ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK_GET(x)\ 1251 FIELD_GET(ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK, x) 1252 1253 /* ANA_CL:PORT:FILTER_CTRL */ 1254 #define ANA_CL_FILTER_CTRL(g) \ 1255 __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ 1256 regs->gcnt[GC_ANA_CL_PORT], 512, 4, 0, 1, 4) 1257 1258 #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS BIT(2) 1259 #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS_SET(x)\ 1260 FIELD_PREP(ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS, x) 1261 #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS_GET(x)\ 1262 FIELD_GET(ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS, x) 1263 1264 #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS BIT(1) 1265 #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS_SET(x)\ 1266 FIELD_PREP(ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS, x) 1267 #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS_GET(x)\ 1268 FIELD_GET(ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS, x) 1269 1270 #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA BIT(0) 1271 #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_SET(x)\ 1272 FIELD_PREP(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA, x) 1273 #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_GET(x)\ 1274 FIELD_GET(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA, x) 1275 1276 /* ANA_CL:PORT:VLAN_FILTER_CTRL */ 1277 #define ANA_CL_VLAN_FILTER_CTRL(g, r) \ 1278 __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ 1279 regs->gcnt[GC_ANA_CL_PORT], 512, 8, r, 3, 4) 1280 1281 #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA BIT(10) 1282 #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA_SET(x)\ 1283 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA, x) 1284 #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA_GET(x)\ 1285 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA, x) 1286 1287 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS BIT(9) 1288 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS_SET(x)\ 1289 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS, x) 1290 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS_GET(x)\ 1291 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS, x) 1292 1293 #define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS BIT(8) 1294 #define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS_SET(x)\ 1295 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS, x) 1296 #define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS_GET(x)\ 1297 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS, x) 1298 1299 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS BIT(7) 1300 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS_SET(x)\ 1301 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS, x) 1302 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS_GET(x)\ 1303 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS, x) 1304 1305 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS BIT(6) 1306 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS_SET(x)\ 1307 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS, x) 1308 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS_GET(x)\ 1309 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS, x) 1310 1311 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS BIT(5) 1312 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS_SET(x)\ 1313 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS, x) 1314 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS_GET(x)\ 1315 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS, x) 1316 1317 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS BIT(4) 1318 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS_SET(x)\ 1319 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS, x) 1320 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS_GET(x)\ 1321 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS, x) 1322 1323 #define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS BIT(3) 1324 #define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS_SET(x)\ 1325 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_STAG_DIS, x) 1326 #define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS_GET(x)\ 1327 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_STAG_DIS, x) 1328 1329 #define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS BIT(2) 1330 #define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS_SET(x)\ 1331 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS, x) 1332 #define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS_GET(x)\ 1333 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS, x) 1334 1335 #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS BIT(1) 1336 #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS_SET(x)\ 1337 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS, x) 1338 #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS_GET(x)\ 1339 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS, x) 1340 1341 #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS BIT(0) 1342 #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS_SET(x)\ 1343 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS, x) 1344 #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS_GET(x)\ 1345 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS, x) 1346 1347 /* ANA_CL:PORT:ETAG_FILTER_CTRL */ 1348 #define ANA_CL_ETAG_FILTER_CTRL(g) \ 1349 __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ 1350 regs->gcnt[GC_ANA_CL_PORT], 512, 20, 0, 1, 4) 1351 1352 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA BIT(1) 1353 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA_SET(x)\ 1354 FIELD_PREP(ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA, x) 1355 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA_GET(x)\ 1356 FIELD_GET(ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA, x) 1357 1358 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS BIT(0) 1359 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS_SET(x)\ 1360 FIELD_PREP(ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS, x) 1361 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS_GET(x)\ 1362 FIELD_GET(ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS, x) 1363 1364 /* ANA_CL:PORT:VLAN_CTRL */ 1365 #define ANA_CL_VLAN_CTRL(g) \ 1366 __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ 1367 regs->gcnt[GC_ANA_CL_PORT], 512, 32, 0, 1, 4) 1368 1369 #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS GENMASK(30, 26) 1370 #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS_SET(x)\ 1371 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS, x) 1372 #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS_GET(x)\ 1373 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS, x) 1374 1375 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP GENMASK(25, 23) 1376 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP_SET(x)\ 1377 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP, x) 1378 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP_GET(x)\ 1379 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP, x) 1380 1381 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI BIT(22) 1382 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI_SET(x)\ 1383 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI, x) 1384 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI_GET(x)\ 1385 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI, x) 1386 1387 #define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA BIT(21) 1388 #define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA_SET(x)\ 1389 FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA, x) 1390 #define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA_GET(x)\ 1391 FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA, x) 1392 1393 #define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL BIT(20) 1394 #define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL_SET(x)\ 1395 FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_TAG_SEL, x) 1396 #define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL_GET(x)\ 1397 FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_TAG_SEL, x) 1398 1399 #define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA BIT(19) 1400 #define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_SET(x)\ 1401 FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA, x) 1402 #define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_GET(x)\ 1403 FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA, x) 1404 1405 #define ANA_CL_VLAN_CTRL_VLAN_POP_CNT GENMASK(18, 17) 1406 #define ANA_CL_VLAN_CTRL_VLAN_POP_CNT_SET(x)\ 1407 FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_POP_CNT, x) 1408 #define ANA_CL_VLAN_CTRL_VLAN_POP_CNT_GET(x)\ 1409 FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_POP_CNT, x) 1410 1411 #define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE BIT(16) 1412 #define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE_SET(x)\ 1413 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_TAG_TYPE, x) 1414 #define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE_GET(x)\ 1415 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_TAG_TYPE, x) 1416 1417 #define ANA_CL_VLAN_CTRL_PORT_PCP GENMASK(15, 13) 1418 #define ANA_CL_VLAN_CTRL_PORT_PCP_SET(x)\ 1419 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_PCP, x) 1420 #define ANA_CL_VLAN_CTRL_PORT_PCP_GET(x)\ 1421 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_PCP, x) 1422 1423 #define ANA_CL_VLAN_CTRL_PORT_DEI BIT(12) 1424 #define ANA_CL_VLAN_CTRL_PORT_DEI_SET(x)\ 1425 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_DEI, x) 1426 #define ANA_CL_VLAN_CTRL_PORT_DEI_GET(x)\ 1427 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_DEI, x) 1428 1429 #define ANA_CL_VLAN_CTRL_PORT_VID GENMASK(11, 0) 1430 #define ANA_CL_VLAN_CTRL_PORT_VID_SET(x)\ 1431 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VID, x) 1432 #define ANA_CL_VLAN_CTRL_PORT_VID_GET(x)\ 1433 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VID, x) 1434 1435 /* ANA_CL:PORT:VLAN_CTRL_2 */ 1436 #define ANA_CL_VLAN_CTRL_2(g) \ 1437 __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ 1438 regs->gcnt[GC_ANA_CL_PORT], 512, 36, 0, 1, 4) 1439 1440 #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT GENMASK(1, 0) 1441 #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT_SET(x)\ 1442 FIELD_PREP(ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT, x) 1443 #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT_GET(x)\ 1444 FIELD_GET(ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT, x) 1445 1446 /* ANA_CL:PORT:PCP_DEI_MAP_CFG */ 1447 #define ANA_CL_PCP_DEI_MAP_CFG(g, r) \ 1448 __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ 1449 regs->gcnt[GC_ANA_CL_PORT], 512, 108, r, 16, 4) 1450 1451 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL GENMASK(4, 3) 1452 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL_SET(x)\ 1453 FIELD_PREP(ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL, x) 1454 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL_GET(x)\ 1455 FIELD_GET(ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL, x) 1456 1457 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL GENMASK(2, 0) 1458 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL_SET(x)\ 1459 FIELD_PREP(ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL, x) 1460 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL_GET(x)\ 1461 FIELD_GET(ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL, x) 1462 1463 /* ANA_CL:PORT:QOS_CFG */ 1464 #define ANA_CL_QOS_CFG(g) \ 1465 __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ 1466 regs->gcnt[GC_ANA_CL_PORT], 512, 172, 0, 1, 4) 1467 1468 #define ANA_CL_QOS_CFG_DEFAULT_COSID_ENA BIT(17) 1469 #define ANA_CL_QOS_CFG_DEFAULT_COSID_ENA_SET(x)\ 1470 FIELD_PREP(ANA_CL_QOS_CFG_DEFAULT_COSID_ENA, x) 1471 #define ANA_CL_QOS_CFG_DEFAULT_COSID_ENA_GET(x)\ 1472 FIELD_GET(ANA_CL_QOS_CFG_DEFAULT_COSID_ENA, x) 1473 1474 #define ANA_CL_QOS_CFG_DEFAULT_COSID_VAL GENMASK(16, 14) 1475 #define ANA_CL_QOS_CFG_DEFAULT_COSID_VAL_SET(x)\ 1476 FIELD_PREP(ANA_CL_QOS_CFG_DEFAULT_COSID_VAL, x) 1477 #define ANA_CL_QOS_CFG_DEFAULT_COSID_VAL_GET(x)\ 1478 FIELD_GET(ANA_CL_QOS_CFG_DEFAULT_COSID_VAL, x) 1479 1480 #define ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL GENMASK(13, 12) 1481 #define ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL_SET(x)\ 1482 FIELD_PREP(ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL, x) 1483 #define ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL_GET(x)\ 1484 FIELD_GET(ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL, x) 1485 1486 #define ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA BIT(11) 1487 #define ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA_SET(x)\ 1488 FIELD_PREP(ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA, x) 1489 #define ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA_GET(x)\ 1490 FIELD_GET(ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA, x) 1491 1492 #define ANA_CL_QOS_CFG_DSCP_KEEP_ENA BIT(10) 1493 #define ANA_CL_QOS_CFG_DSCP_KEEP_ENA_SET(x)\ 1494 FIELD_PREP(ANA_CL_QOS_CFG_DSCP_KEEP_ENA, x) 1495 #define ANA_CL_QOS_CFG_DSCP_KEEP_ENA_GET(x)\ 1496 FIELD_GET(ANA_CL_QOS_CFG_DSCP_KEEP_ENA, x) 1497 1498 #define ANA_CL_QOS_CFG_KEEP_ENA BIT(9) 1499 #define ANA_CL_QOS_CFG_KEEP_ENA_SET(x)\ 1500 FIELD_PREP(ANA_CL_QOS_CFG_KEEP_ENA, x) 1501 #define ANA_CL_QOS_CFG_KEEP_ENA_GET(x)\ 1502 FIELD_GET(ANA_CL_QOS_CFG_KEEP_ENA, x) 1503 1504 #define ANA_CL_QOS_CFG_PCP_DEI_DP_ENA BIT(8) 1505 #define ANA_CL_QOS_CFG_PCP_DEI_DP_ENA_SET(x)\ 1506 FIELD_PREP(ANA_CL_QOS_CFG_PCP_DEI_DP_ENA, x) 1507 #define ANA_CL_QOS_CFG_PCP_DEI_DP_ENA_GET(x)\ 1508 FIELD_GET(ANA_CL_QOS_CFG_PCP_DEI_DP_ENA, x) 1509 1510 #define ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA BIT(7) 1511 #define ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA_SET(x)\ 1512 FIELD_PREP(ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA, x) 1513 #define ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA_GET(x)\ 1514 FIELD_GET(ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA, x) 1515 1516 #define ANA_CL_QOS_CFG_DSCP_DP_ENA BIT(6) 1517 #define ANA_CL_QOS_CFG_DSCP_DP_ENA_SET(x)\ 1518 FIELD_PREP(ANA_CL_QOS_CFG_DSCP_DP_ENA, x) 1519 #define ANA_CL_QOS_CFG_DSCP_DP_ENA_GET(x)\ 1520 FIELD_GET(ANA_CL_QOS_CFG_DSCP_DP_ENA, x) 1521 1522 #define ANA_CL_QOS_CFG_DSCP_QOS_ENA BIT(5) 1523 #define ANA_CL_QOS_CFG_DSCP_QOS_ENA_SET(x)\ 1524 FIELD_PREP(ANA_CL_QOS_CFG_DSCP_QOS_ENA, x) 1525 #define ANA_CL_QOS_CFG_DSCP_QOS_ENA_GET(x)\ 1526 FIELD_GET(ANA_CL_QOS_CFG_DSCP_QOS_ENA, x) 1527 1528 #define ANA_CL_QOS_CFG_DEFAULT_DP_VAL GENMASK(4, 3) 1529 #define ANA_CL_QOS_CFG_DEFAULT_DP_VAL_SET(x)\ 1530 FIELD_PREP(ANA_CL_QOS_CFG_DEFAULT_DP_VAL, x) 1531 #define ANA_CL_QOS_CFG_DEFAULT_DP_VAL_GET(x)\ 1532 FIELD_GET(ANA_CL_QOS_CFG_DEFAULT_DP_VAL, x) 1533 1534 #define ANA_CL_QOS_CFG_DEFAULT_QOS_VAL GENMASK(2, 0) 1535 #define ANA_CL_QOS_CFG_DEFAULT_QOS_VAL_SET(x)\ 1536 FIELD_PREP(ANA_CL_QOS_CFG_DEFAULT_QOS_VAL, x) 1537 #define ANA_CL_QOS_CFG_DEFAULT_QOS_VAL_GET(x)\ 1538 FIELD_GET(ANA_CL_QOS_CFG_DEFAULT_QOS_VAL, x) 1539 1540 /* ANA_CL:PORT:CAPTURE_BPDU_CFG */ 1541 #define ANA_CL_CAPTURE_BPDU_CFG(g) \ 1542 __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ 1543 regs->gcnt[GC_ANA_CL_PORT], 512, 196, 0, 1, 4) 1544 1545 /* ANA_CL:PORT:ADV_CL_CFG_2 */ 1546 #define ANA_CL_ADV_CL_CFG_2(g, r) \ 1547 __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ 1548 regs->gcnt[GC_ANA_CL_PORT], 512, 200, r, 6, 4) 1549 1550 #define ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA BIT(1) 1551 #define ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA_SET(x)\ 1552 FIELD_PREP(ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA, x) 1553 #define ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA_GET(x)\ 1554 FIELD_GET(ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA, x) 1555 1556 #define ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA BIT(0) 1557 #define ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA_SET(x)\ 1558 FIELD_PREP(ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA, x) 1559 #define ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA_GET(x)\ 1560 FIELD_GET(ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA, x) 1561 1562 /* ANA_CL:PORT:ADV_CL_CFG */ 1563 #define ANA_CL_ADV_CL_CFG(g, r) \ 1564 __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ 1565 regs->gcnt[GC_ANA_CL_PORT], 512, 224, r, 6, 4) 1566 1567 #define ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL GENMASK(30, 26) 1568 #define ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL_SET(x)\ 1569 FIELD_PREP(ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL, x) 1570 #define ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL_GET(x)\ 1571 FIELD_GET(ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL, x) 1572 1573 #define ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL GENMASK(25, 21) 1574 #define ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL_SET(x)\ 1575 FIELD_PREP(ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL, x) 1576 #define ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL_GET(x)\ 1577 FIELD_GET(ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL, x) 1578 1579 #define ANA_CL_ADV_CL_CFG_MPLS_UC_CLM_KEY_SEL GENMASK(20, 16) 1580 #define ANA_CL_ADV_CL_CFG_MPLS_UC_CLM_KEY_SEL_SET(x)\ 1581 FIELD_PREP(ANA_CL_ADV_CL_CFG_MPLS_UC_CLM_KEY_SEL, x) 1582 #define ANA_CL_ADV_CL_CFG_MPLS_UC_CLM_KEY_SEL_GET(x)\ 1583 FIELD_GET(ANA_CL_ADV_CL_CFG_MPLS_UC_CLM_KEY_SEL, x) 1584 1585 #define ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL GENMASK(15, 11) 1586 #define ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL_SET(x)\ 1587 FIELD_PREP(ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL, x) 1588 #define ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL_GET(x)\ 1589 FIELD_GET(ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL, x) 1590 1591 #define ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL GENMASK(10, 6) 1592 #define ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL_SET(x)\ 1593 FIELD_PREP(ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL, x) 1594 #define ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL_GET(x)\ 1595 FIELD_GET(ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL, x) 1596 1597 #define ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL GENMASK(5, 1) 1598 #define ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL_SET(x)\ 1599 FIELD_PREP(ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL, x) 1600 #define ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL_GET(x)\ 1601 FIELD_GET(ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL, x) 1602 1603 #define ANA_CL_ADV_CL_CFG_LOOKUP_ENA BIT(0) 1604 #define ANA_CL_ADV_CL_CFG_LOOKUP_ENA_SET(x)\ 1605 FIELD_PREP(ANA_CL_ADV_CL_CFG_LOOKUP_ENA, x) 1606 #define ANA_CL_ADV_CL_CFG_LOOKUP_ENA_GET(x)\ 1607 FIELD_GET(ANA_CL_ADV_CL_CFG_LOOKUP_ENA, x) 1608 1609 /* ANA_CL:COMMON:OWN_UPSID */ 1610 #define ANA_CL_OWN_UPSID(r) \ 1611 __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_COMMON], 0, 1, 756, 0,\ 1612 r, regs->rcnt[RC_ANA_CL_OWN_UPSID], 4) 1613 1614 #define ANA_CL_OWN_UPSID_OWN_UPSID GENMASK(4, 0) 1615 #define ANA_CL_OWN_UPSID_OWN_UPSID_SET(x)\ 1616 FIELD_PREP(ANA_CL_OWN_UPSID_OWN_UPSID, x) 1617 #define ANA_CL_OWN_UPSID_OWN_UPSID_GET(x)\ 1618 FIELD_GET(ANA_CL_OWN_UPSID_OWN_UPSID, x) 1619 1620 /* ANA_CL:COMMON:DSCP_CFG */ 1621 #define ANA_CL_DSCP_CFG(r) \ 1622 __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_COMMON], 0, 1, 756, \ 1623 256, r, 64, 4) 1624 1625 #define ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL GENMASK(12, 7) 1626 #define ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL_SET(x)\ 1627 FIELD_PREP(ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL, x) 1628 #define ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL_GET(x)\ 1629 FIELD_GET(ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL, x) 1630 1631 #define ANA_CL_DSCP_CFG_DSCP_QOS_VAL GENMASK(6, 4) 1632 #define ANA_CL_DSCP_CFG_DSCP_QOS_VAL_SET(x)\ 1633 FIELD_PREP(ANA_CL_DSCP_CFG_DSCP_QOS_VAL, x) 1634 #define ANA_CL_DSCP_CFG_DSCP_QOS_VAL_GET(x)\ 1635 FIELD_GET(ANA_CL_DSCP_CFG_DSCP_QOS_VAL, x) 1636 1637 #define ANA_CL_DSCP_CFG_DSCP_DP_VAL GENMASK(3, 2) 1638 #define ANA_CL_DSCP_CFG_DSCP_DP_VAL_SET(x)\ 1639 FIELD_PREP(ANA_CL_DSCP_CFG_DSCP_DP_VAL, x) 1640 #define ANA_CL_DSCP_CFG_DSCP_DP_VAL_GET(x)\ 1641 FIELD_GET(ANA_CL_DSCP_CFG_DSCP_DP_VAL, x) 1642 1643 #define ANA_CL_DSCP_CFG_DSCP_REWR_ENA BIT(1) 1644 #define ANA_CL_DSCP_CFG_DSCP_REWR_ENA_SET(x)\ 1645 FIELD_PREP(ANA_CL_DSCP_CFG_DSCP_REWR_ENA, x) 1646 #define ANA_CL_DSCP_CFG_DSCP_REWR_ENA_GET(x)\ 1647 FIELD_GET(ANA_CL_DSCP_CFG_DSCP_REWR_ENA, x) 1648 1649 #define ANA_CL_DSCP_CFG_DSCP_TRUST_ENA BIT(0) 1650 #define ANA_CL_DSCP_CFG_DSCP_TRUST_ENA_SET(x)\ 1651 FIELD_PREP(ANA_CL_DSCP_CFG_DSCP_TRUST_ENA, x) 1652 #define ANA_CL_DSCP_CFG_DSCP_TRUST_ENA_GET(x)\ 1653 FIELD_GET(ANA_CL_DSCP_CFG_DSCP_TRUST_ENA, x) 1654 1655 /* ANA_CL:COMMON:QOS_MAP_CFG */ 1656 #define ANA_CL_QOS_MAP_CFG(r) \ 1657 __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_COMMON], 0, 1, 756, \ 1658 512, r, 32, 4) 1659 1660 #define ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL GENMASK(9, 4) 1661 #define ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL_SET(x)\ 1662 FIELD_PREP(ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL, x) 1663 #define ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL_GET(x)\ 1664 FIELD_GET(ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL, x) 1665 1666 /* ANA_L2:COMMON:FWD_CFG */ 1667 #define ANA_L2_FWD_CFG \ 1668 __REG(TARGET_ANA_L2, 0, 1, regs->gaddr[GA_ANA_L2_COMMON], 0, 1, \ 1669 regs->gsize[GW_ANA_L2_COMMON], 0, 0, 1, 4) 1670 1671 #define ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL GENMASK(21, 20) 1672 #define ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL_SET(x)\ 1673 FIELD_PREP(ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL, x) 1674 #define ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL_GET(x)\ 1675 FIELD_GET(ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL, x) 1676 1677 #define ANA_L2_FWD_CFG_PORT_DEFAULT_BDLB_ENA BIT(18) 1678 #define ANA_L2_FWD_CFG_PORT_DEFAULT_BDLB_ENA_SET(x)\ 1679 FIELD_PREP(ANA_L2_FWD_CFG_PORT_DEFAULT_BDLB_ENA, x) 1680 #define ANA_L2_FWD_CFG_PORT_DEFAULT_BDLB_ENA_GET(x)\ 1681 FIELD_GET(ANA_L2_FWD_CFG_PORT_DEFAULT_BDLB_ENA, x) 1682 1683 #define ANA_L2_FWD_CFG_QUEUE_DEFAULT_SDLB_ENA BIT(17) 1684 #define ANA_L2_FWD_CFG_QUEUE_DEFAULT_SDLB_ENA_SET(x)\ 1685 FIELD_PREP(ANA_L2_FWD_CFG_QUEUE_DEFAULT_SDLB_ENA, x) 1686 #define ANA_L2_FWD_CFG_QUEUE_DEFAULT_SDLB_ENA_GET(x)\ 1687 FIELD_GET(ANA_L2_FWD_CFG_QUEUE_DEFAULT_SDLB_ENA, x) 1688 1689 #define ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA BIT(16) 1690 #define ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA_SET(x)\ 1691 FIELD_PREP(ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA, x) 1692 #define ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA_GET(x)\ 1693 FIELD_GET(ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA, x) 1694 1695 #define ANA_L2_FWD_CFG_CPU_DMAC_QU GENMASK(10, 8) 1696 #define ANA_L2_FWD_CFG_CPU_DMAC_QU_SET(x)\ 1697 FIELD_PREP(ANA_L2_FWD_CFG_CPU_DMAC_QU, x) 1698 #define ANA_L2_FWD_CFG_CPU_DMAC_QU_GET(x)\ 1699 FIELD_GET(ANA_L2_FWD_CFG_CPU_DMAC_QU, x) 1700 1701 #define ANA_L2_FWD_CFG_LOOPBACK_ENA BIT(7) 1702 #define ANA_L2_FWD_CFG_LOOPBACK_ENA_SET(x)\ 1703 FIELD_PREP(ANA_L2_FWD_CFG_LOOPBACK_ENA, x) 1704 #define ANA_L2_FWD_CFG_LOOPBACK_ENA_GET(x)\ 1705 FIELD_GET(ANA_L2_FWD_CFG_LOOPBACK_ENA, x) 1706 1707 #define ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA BIT(6) 1708 #define ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA_SET(x)\ 1709 FIELD_PREP(ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA, x) 1710 #define ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA_GET(x)\ 1711 FIELD_GET(ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA, x) 1712 1713 #define ANA_L2_FWD_CFG_FILTER_MODE_SEL BIT(4) 1714 #define ANA_L2_FWD_CFG_FILTER_MODE_SEL_SET(x)\ 1715 FIELD_PREP(ANA_L2_FWD_CFG_FILTER_MODE_SEL, x) 1716 #define ANA_L2_FWD_CFG_FILTER_MODE_SEL_GET(x)\ 1717 FIELD_GET(ANA_L2_FWD_CFG_FILTER_MODE_SEL, x) 1718 1719 #define ANA_L2_FWD_CFG_FLOOD_MIRROR_ENA BIT(3) 1720 #define ANA_L2_FWD_CFG_FLOOD_MIRROR_ENA_SET(x)\ 1721 FIELD_PREP(ANA_L2_FWD_CFG_FLOOD_MIRROR_ENA, x) 1722 #define ANA_L2_FWD_CFG_FLOOD_MIRROR_ENA_GET(x)\ 1723 FIELD_GET(ANA_L2_FWD_CFG_FLOOD_MIRROR_ENA, x) 1724 1725 #define ANA_L2_FWD_CFG_FLOOD_IGNORE_VLAN_ENA BIT(2) 1726 #define ANA_L2_FWD_CFG_FLOOD_IGNORE_VLAN_ENA_SET(x)\ 1727 FIELD_PREP(ANA_L2_FWD_CFG_FLOOD_IGNORE_VLAN_ENA, x) 1728 #define ANA_L2_FWD_CFG_FLOOD_IGNORE_VLAN_ENA_GET(x)\ 1729 FIELD_GET(ANA_L2_FWD_CFG_FLOOD_IGNORE_VLAN_ENA, x) 1730 1731 #define ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA BIT(1) 1732 #define ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA_SET(x)\ 1733 FIELD_PREP(ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA, x) 1734 #define ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA_GET(x)\ 1735 FIELD_GET(ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA, x) 1736 1737 #define ANA_L2_FWD_CFG_FWD_ENA BIT(0) 1738 #define ANA_L2_FWD_CFG_FWD_ENA_SET(x)\ 1739 FIELD_PREP(ANA_L2_FWD_CFG_FWD_ENA, x) 1740 #define ANA_L2_FWD_CFG_FWD_ENA_GET(x)\ 1741 FIELD_GET(ANA_L2_FWD_CFG_FWD_ENA, x) 1742 1743 /* ANA_L2:COMMON:AUTO_LRN_CFG */ 1744 #define ANA_L2_AUTO_LRN_CFG \ 1745 __REG(TARGET_ANA_L2, 0, 1, regs->gaddr[GA_ANA_L2_COMMON], 0, 1, \ 1746 regs->gsize[GW_ANA_L2_COMMON], 24, 0, 1, 4) 1747 1748 /* SPARX5 ONLY */ 1749 /* ANA_L2:COMMON:AUTO_LRN_CFG1 */ 1750 #define ANA_L2_AUTO_LRN_CFG1 \ 1751 __REG(TARGET_ANA_L2, 0, 1, regs->gaddr[GA_ANA_L2_COMMON], 0, 1, \ 1752 regs->gsize[GW_ANA_L2_COMMON], 28, 0, 1, 4) 1753 1754 /* SPARX5 ONLY */ 1755 /* ANA_L2:COMMON:AUTO_LRN_CFG2 */ 1756 #define ANA_L2_AUTO_LRN_CFG2 \ 1757 __REG(TARGET_ANA_L2, 0, 1, regs->gaddr[GA_ANA_L2_COMMON], 0, 1, \ 1758 regs->gsize[GW_ANA_L2_COMMON], 32, 0, 1, 4) 1759 1760 #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2 BIT(0) 1761 #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2_SET(x)\ 1762 FIELD_PREP(ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2, x) 1763 #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2_GET(x)\ 1764 FIELD_GET(ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2, x) 1765 1766 /* ANA_L2:COMMON:OWN_UPSID */ 1767 #define ANA_L2_OWN_UPSID(r) \ 1768 __REG(TARGET_ANA_L2, 0, 1, regs->gaddr[GA_ANA_L2_COMMON], 0, 1, \ 1769 regs->gsize[GW_ANA_L2_COMMON], 672, r, \ 1770 regs->rcnt[RC_ANA_L2_OWN_UPSID], 4) 1771 1772 #define ANA_L2_OWN_UPSID_OWN_UPSID GENMASK(4, 0) 1773 #define ANA_L2_OWN_UPSID_OWN_UPSID_SET(x)\ 1774 FIELD_PREP(ANA_L2_OWN_UPSID_OWN_UPSID, x) 1775 #define ANA_L2_OWN_UPSID_OWN_UPSID_GET(x)\ 1776 FIELD_GET(ANA_L2_OWN_UPSID_OWN_UPSID, x) 1777 1778 /* ANA_L2:ISDX:DLB_CFG */ 1779 #define ANA_L2_DLB_CFG(g) \ 1780 __REG(TARGET_ANA_L2, 0, 1, 0, g, regs->gcnt[GC_ANA_L2_ISDX], 128, 56, \ 1781 0, 1, 4) 1782 1783 #define ANA_L2_DLB_CFG_DLB_IDX\ 1784 GENMASK(regs->fsize[FW_ANA_L2_DLB_CFG_DLB_IDX] + 0 - 1, 0) 1785 #define ANA_L2_DLB_CFG_DLB_IDX_SET(x)\ 1786 spx5_field_prep(ANA_L2_DLB_CFG_DLB_IDX, x) 1787 #define ANA_L2_DLB_CFG_DLB_IDX_GET(x)\ 1788 spx5_field_get(ANA_L2_DLB_CFG_DLB_IDX, x) 1789 1790 /* ANA_L2:ISDX:TSN_CFG */ 1791 #define ANA_L2_TSN_CFG(g) \ 1792 __REG(TARGET_ANA_L2, 0, 1, 0, g, regs->gcnt[GC_ANA_L2_ISDX], 128, 100, \ 1793 0, 1, 4) 1794 1795 #define ANA_L2_TSN_CFG_TSN_SFID\ 1796 GENMASK(regs->fsize[FW_ANA_L2_TSN_CFG_TSN_SFID] + 0 - 1, 0) 1797 #define ANA_L2_TSN_CFG_TSN_SFID_SET(x)\ 1798 spx5_field_prep(ANA_L2_TSN_CFG_TSN_SFID, x) 1799 #define ANA_L2_TSN_CFG_TSN_SFID_GET(x)\ 1800 spx5_field_get(ANA_L2_TSN_CFG_TSN_SFID, x) 1801 1802 /* ANA_L3:COMMON:VLAN_CTRL */ 1803 #define ANA_L3_VLAN_CTRL \ 1804 __REG(TARGET_ANA_L3, 0, 1, regs->gaddr[GA_ANA_L3_COMMON], 0, 1, 184, 4,\ 1805 0, 1, 4) 1806 1807 #define ANA_L3_VLAN_CTRL_VLAN_ENA BIT(0) 1808 #define ANA_L3_VLAN_CTRL_VLAN_ENA_SET(x)\ 1809 FIELD_PREP(ANA_L3_VLAN_CTRL_VLAN_ENA, x) 1810 #define ANA_L3_VLAN_CTRL_VLAN_ENA_GET(x)\ 1811 FIELD_GET(ANA_L3_VLAN_CTRL_VLAN_ENA, x) 1812 1813 /* ANA_L3:VLAN:VLAN_CFG */ 1814 #define ANA_L3_VLAN_CFG(g) \ 1815 __REG(TARGET_ANA_L3, 0, 1, 0, g, regs->gcnt[GC_ANA_L3_VLAN], 64, 8, 0, \ 1816 1, 4) 1817 1818 #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR GENMASK(30, 24) 1819 #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR_SET(x)\ 1820 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_MSTP_PTR, x) 1821 #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR_GET(x)\ 1822 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_MSTP_PTR, x) 1823 1824 #define ANA_L3_VLAN_CFG_VLAN_FID GENMASK(20, 8) 1825 #define ANA_L3_VLAN_CFG_VLAN_FID_SET(x)\ 1826 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_FID, x) 1827 #define ANA_L3_VLAN_CFG_VLAN_FID_GET(x)\ 1828 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_FID, x) 1829 1830 #define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA BIT(6) 1831 #define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA_SET(x)\ 1832 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA, x) 1833 #define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA_GET(x)\ 1834 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA, x) 1835 1836 #define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA BIT(5) 1837 #define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA_SET(x)\ 1838 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA, x) 1839 #define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA_GET(x)\ 1840 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA, x) 1841 1842 #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS BIT(4) 1843 #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS_SET(x)\ 1844 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS, x) 1845 #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS_GET(x)\ 1846 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS, x) 1847 1848 #define ANA_L3_VLAN_CFG_VLAN_LRN_DIS BIT(3) 1849 #define ANA_L3_VLAN_CFG_VLAN_LRN_DIS_SET(x)\ 1850 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_LRN_DIS, x) 1851 #define ANA_L3_VLAN_CFG_VLAN_LRN_DIS_GET(x)\ 1852 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_LRN_DIS, x) 1853 1854 #define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA BIT(2) 1855 #define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA_SET(x)\ 1856 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_RLEG_ENA, x) 1857 #define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA_GET(x)\ 1858 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_RLEG_ENA, x) 1859 1860 #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA BIT(1) 1861 #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA_SET(x)\ 1862 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA, x) 1863 #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA_GET(x)\ 1864 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA, x) 1865 1866 #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA BIT(0) 1867 #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA_SET(x)\ 1868 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA, x) 1869 #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA_GET(x)\ 1870 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA, x) 1871 1872 /* ANA_L3:VLAN:VLAN_MASK_CFG */ 1873 #define ANA_L3_VLAN_MASK_CFG(g) \ 1874 __REG(TARGET_ANA_L3, 0, 1, 0, g, regs->gcnt[GC_ANA_L3_VLAN], 64, 16, 0,\ 1875 1, 4) 1876 1877 /* SPARX5 ONLY */ 1878 /* ANA_L3:VLAN:VLAN_MASK_CFG1 */ 1879 #define ANA_L3_VLAN_MASK_CFG1(g) \ 1880 __REG(TARGET_ANA_L3, 0, 1, 0, g, regs->gcnt[GC_ANA_L3_VLAN], 64, 20, 0,\ 1881 1, 4) 1882 1883 /* SPARX5 ONLY */ 1884 /* ANA_L3:VLAN:VLAN_MASK_CFG2 */ 1885 #define ANA_L3_VLAN_MASK_CFG2(g) \ 1886 __REG(TARGET_ANA_L3, 0, 1, 0, g, regs->gcnt[GC_ANA_L3_VLAN], 64, 24, 0,\ 1887 1, 4) 1888 1889 #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2 BIT(0) 1890 #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2_SET(x)\ 1891 FIELD_PREP(ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2, x) 1892 #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2_GET(x)\ 1893 FIELD_GET(ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2, x) 1894 1895 /* ASM:DEV_STATISTICS:RX_IN_BYTES_CNT */ 1896 #define ASM_RX_IN_BYTES_CNT(g) \ 1897 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1898 0, 0, 1, 4) 1899 1900 /* ASM:DEV_STATISTICS:RX_SYMBOL_ERR_CNT */ 1901 #define ASM_RX_SYMBOL_ERR_CNT(g) \ 1902 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1903 4, 0, 1, 4) 1904 1905 /* ASM:DEV_STATISTICS:RX_PAUSE_CNT */ 1906 #define ASM_RX_PAUSE_CNT(g) \ 1907 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1908 8, 0, 1, 4) 1909 1910 /* ASM:DEV_STATISTICS:RX_UNSUP_OPCODE_CNT */ 1911 #define ASM_RX_UNSUP_OPCODE_CNT(g) \ 1912 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1913 12, 0, 1, 4) 1914 1915 /* ASM:DEV_STATISTICS:RX_OK_BYTES_CNT */ 1916 #define ASM_RX_OK_BYTES_CNT(g) \ 1917 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1918 16, 0, 1, 4) 1919 1920 /* ASM:DEV_STATISTICS:RX_BAD_BYTES_CNT */ 1921 #define ASM_RX_BAD_BYTES_CNT(g) \ 1922 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1923 20, 0, 1, 4) 1924 1925 /* ASM:DEV_STATISTICS:RX_UC_CNT */ 1926 #define ASM_RX_UC_CNT(g) \ 1927 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1928 24, 0, 1, 4) 1929 1930 /* ASM:DEV_STATISTICS:RX_MC_CNT */ 1931 #define ASM_RX_MC_CNT(g) \ 1932 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1933 28, 0, 1, 4) 1934 1935 /* ASM:DEV_STATISTICS:RX_BC_CNT */ 1936 #define ASM_RX_BC_CNT(g) \ 1937 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1938 32, 0, 1, 4) 1939 1940 /* ASM:DEV_STATISTICS:RX_CRC_ERR_CNT */ 1941 #define ASM_RX_CRC_ERR_CNT(g) \ 1942 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1943 36, 0, 1, 4) 1944 1945 /* ASM:DEV_STATISTICS:RX_UNDERSIZE_CNT */ 1946 #define ASM_RX_UNDERSIZE_CNT(g) \ 1947 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1948 40, 0, 1, 4) 1949 1950 /* ASM:DEV_STATISTICS:RX_FRAGMENTS_CNT */ 1951 #define ASM_RX_FRAGMENTS_CNT(g) \ 1952 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1953 44, 0, 1, 4) 1954 1955 /* ASM:DEV_STATISTICS:RX_IN_RANGE_LEN_ERR_CNT */ 1956 #define ASM_RX_IN_RANGE_LEN_ERR_CNT(g) \ 1957 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1958 48, 0, 1, 4) 1959 1960 /* ASM:DEV_STATISTICS:RX_OUT_OF_RANGE_LEN_ERR_CNT */ 1961 #define ASM_RX_OUT_OF_RANGE_LEN_ERR_CNT(g) \ 1962 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1963 52, 0, 1, 4) 1964 1965 /* ASM:DEV_STATISTICS:RX_OVERSIZE_CNT */ 1966 #define ASM_RX_OVERSIZE_CNT(g) \ 1967 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1968 56, 0, 1, 4) 1969 1970 /* ASM:DEV_STATISTICS:RX_JABBERS_CNT */ 1971 #define ASM_RX_JABBERS_CNT(g) \ 1972 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1973 60, 0, 1, 4) 1974 1975 /* ASM:DEV_STATISTICS:RX_SIZE64_CNT */ 1976 #define ASM_RX_SIZE64_CNT(g) \ 1977 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1978 64, 0, 1, 4) 1979 1980 /* ASM:DEV_STATISTICS:RX_SIZE65TO127_CNT */ 1981 #define ASM_RX_SIZE65TO127_CNT(g) \ 1982 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1983 68, 0, 1, 4) 1984 1985 /* ASM:DEV_STATISTICS:RX_SIZE128TO255_CNT */ 1986 #define ASM_RX_SIZE128TO255_CNT(g) \ 1987 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1988 72, 0, 1, 4) 1989 1990 /* ASM:DEV_STATISTICS:RX_SIZE256TO511_CNT */ 1991 #define ASM_RX_SIZE256TO511_CNT(g) \ 1992 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1993 76, 0, 1, 4) 1994 1995 /* ASM:DEV_STATISTICS:RX_SIZE512TO1023_CNT */ 1996 #define ASM_RX_SIZE512TO1023_CNT(g) \ 1997 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 1998 80, 0, 1, 4) 1999 2000 /* ASM:DEV_STATISTICS:RX_SIZE1024TO1518_CNT */ 2001 #define ASM_RX_SIZE1024TO1518_CNT(g) \ 2002 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2003 84, 0, 1, 4) 2004 2005 /* ASM:DEV_STATISTICS:RX_SIZE1519TOMAX_CNT */ 2006 #define ASM_RX_SIZE1519TOMAX_CNT(g) \ 2007 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2008 88, 0, 1, 4) 2009 2010 /* ASM:DEV_STATISTICS:RX_IPG_SHRINK_CNT */ 2011 #define ASM_RX_IPG_SHRINK_CNT(g) \ 2012 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2013 92, 0, 1, 4) 2014 2015 /* ASM:DEV_STATISTICS:TX_OUT_BYTES_CNT */ 2016 #define ASM_TX_OUT_BYTES_CNT(g) \ 2017 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2018 96, 0, 1, 4) 2019 2020 /* ASM:DEV_STATISTICS:TX_PAUSE_CNT */ 2021 #define ASM_TX_PAUSE_CNT(g) \ 2022 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2023 100, 0, 1, 4) 2024 2025 /* ASM:DEV_STATISTICS:TX_OK_BYTES_CNT */ 2026 #define ASM_TX_OK_BYTES_CNT(g) \ 2027 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2028 104, 0, 1, 4) 2029 2030 /* ASM:DEV_STATISTICS:TX_UC_CNT */ 2031 #define ASM_TX_UC_CNT(g) \ 2032 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2033 108, 0, 1, 4) 2034 2035 /* ASM:DEV_STATISTICS:TX_MC_CNT */ 2036 #define ASM_TX_MC_CNT(g) \ 2037 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2038 112, 0, 1, 4) 2039 2040 /* ASM:DEV_STATISTICS:TX_BC_CNT */ 2041 #define ASM_TX_BC_CNT(g) \ 2042 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2043 116, 0, 1, 4) 2044 2045 /* ASM:DEV_STATISTICS:TX_SIZE64_CNT */ 2046 #define ASM_TX_SIZE64_CNT(g) \ 2047 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2048 120, 0, 1, 4) 2049 2050 /* ASM:DEV_STATISTICS:TX_SIZE65TO127_CNT */ 2051 #define ASM_TX_SIZE65TO127_CNT(g) \ 2052 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2053 124, 0, 1, 4) 2054 2055 /* ASM:DEV_STATISTICS:TX_SIZE128TO255_CNT */ 2056 #define ASM_TX_SIZE128TO255_CNT(g) \ 2057 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2058 128, 0, 1, 4) 2059 2060 /* ASM:DEV_STATISTICS:TX_SIZE256TO511_CNT */ 2061 #define ASM_TX_SIZE256TO511_CNT(g) \ 2062 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2063 132, 0, 1, 4) 2064 2065 /* ASM:DEV_STATISTICS:TX_SIZE512TO1023_CNT */ 2066 #define ASM_TX_SIZE512TO1023_CNT(g) \ 2067 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2068 136, 0, 1, 4) 2069 2070 /* ASM:DEV_STATISTICS:TX_SIZE1024TO1518_CNT */ 2071 #define ASM_TX_SIZE1024TO1518_CNT(g) \ 2072 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2073 140, 0, 1, 4) 2074 2075 /* ASM:DEV_STATISTICS:TX_SIZE1519TOMAX_CNT */ 2076 #define ASM_TX_SIZE1519TOMAX_CNT(g) \ 2077 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2078 144, 0, 1, 4) 2079 2080 /* ASM:DEV_STATISTICS:RX_ALIGNMENT_LOST_CNT */ 2081 #define ASM_RX_ALIGNMENT_LOST_CNT(g) \ 2082 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2083 148, 0, 1, 4) 2084 2085 /* ASM:DEV_STATISTICS:RX_TAGGED_FRMS_CNT */ 2086 #define ASM_RX_TAGGED_FRMS_CNT(g) \ 2087 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2088 152, 0, 1, 4) 2089 2090 /* ASM:DEV_STATISTICS:RX_UNTAGGED_FRMS_CNT */ 2091 #define ASM_RX_UNTAGGED_FRMS_CNT(g) \ 2092 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2093 156, 0, 1, 4) 2094 2095 /* ASM:DEV_STATISTICS:TX_TAGGED_FRMS_CNT */ 2096 #define ASM_TX_TAGGED_FRMS_CNT(g) \ 2097 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2098 160, 0, 1, 4) 2099 2100 /* ASM:DEV_STATISTICS:TX_UNTAGGED_FRMS_CNT */ 2101 #define ASM_TX_UNTAGGED_FRMS_CNT(g) \ 2102 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2103 164, 0, 1, 4) 2104 2105 /* ASM:DEV_STATISTICS:PMAC_RX_SYMBOL_ERR_CNT */ 2106 #define ASM_PMAC_RX_SYMBOL_ERR_CNT(g) \ 2107 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2108 168, 0, 1, 4) 2109 2110 /* ASM:DEV_STATISTICS:PMAC_RX_PAUSE_CNT */ 2111 #define ASM_PMAC_RX_PAUSE_CNT(g) \ 2112 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2113 172, 0, 1, 4) 2114 2115 /* ASM:DEV_STATISTICS:PMAC_RX_UNSUP_OPCODE_CNT */ 2116 #define ASM_PMAC_RX_UNSUP_OPCODE_CNT(g) \ 2117 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2118 176, 0, 1, 4) 2119 2120 /* ASM:DEV_STATISTICS:PMAC_RX_OK_BYTES_CNT */ 2121 #define ASM_PMAC_RX_OK_BYTES_CNT(g) \ 2122 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2123 180, 0, 1, 4) 2124 2125 /* ASM:DEV_STATISTICS:PMAC_RX_BAD_BYTES_CNT */ 2126 #define ASM_PMAC_RX_BAD_BYTES_CNT(g) \ 2127 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2128 184, 0, 1, 4) 2129 2130 /* ASM:DEV_STATISTICS:PMAC_RX_UC_CNT */ 2131 #define ASM_PMAC_RX_UC_CNT(g) \ 2132 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2133 188, 0, 1, 4) 2134 2135 /* ASM:DEV_STATISTICS:PMAC_RX_MC_CNT */ 2136 #define ASM_PMAC_RX_MC_CNT(g) \ 2137 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2138 192, 0, 1, 4) 2139 2140 /* ASM:DEV_STATISTICS:PMAC_RX_BC_CNT */ 2141 #define ASM_PMAC_RX_BC_CNT(g) \ 2142 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2143 196, 0, 1, 4) 2144 2145 /* ASM:DEV_STATISTICS:PMAC_RX_CRC_ERR_CNT */ 2146 #define ASM_PMAC_RX_CRC_ERR_CNT(g) \ 2147 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2148 200, 0, 1, 4) 2149 2150 /* ASM:DEV_STATISTICS:PMAC_RX_UNDERSIZE_CNT */ 2151 #define ASM_PMAC_RX_UNDERSIZE_CNT(g) \ 2152 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2153 204, 0, 1, 4) 2154 2155 /* ASM:DEV_STATISTICS:PMAC_RX_FRAGMENTS_CNT */ 2156 #define ASM_PMAC_RX_FRAGMENTS_CNT(g) \ 2157 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2158 208, 0, 1, 4) 2159 2160 /* ASM:DEV_STATISTICS:PMAC_RX_IN_RANGE_LEN_ERR_CNT */ 2161 #define ASM_PMAC_RX_IN_RANGE_LEN_ERR_CNT(g) \ 2162 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2163 212, 0, 1, 4) 2164 2165 /* ASM:DEV_STATISTICS:PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT */ 2166 #define ASM_PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT(g) \ 2167 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2168 216, 0, 1, 4) 2169 2170 /* ASM:DEV_STATISTICS:PMAC_RX_OVERSIZE_CNT */ 2171 #define ASM_PMAC_RX_OVERSIZE_CNT(g) \ 2172 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2173 220, 0, 1, 4) 2174 2175 /* ASM:DEV_STATISTICS:PMAC_RX_JABBERS_CNT */ 2176 #define ASM_PMAC_RX_JABBERS_CNT(g) \ 2177 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2178 224, 0, 1, 4) 2179 2180 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE64_CNT */ 2181 #define ASM_PMAC_RX_SIZE64_CNT(g) \ 2182 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2183 228, 0, 1, 4) 2184 2185 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE65TO127_CNT */ 2186 #define ASM_PMAC_RX_SIZE65TO127_CNT(g) \ 2187 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2188 232, 0, 1, 4) 2189 2190 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE128TO255_CNT */ 2191 #define ASM_PMAC_RX_SIZE128TO255_CNT(g) \ 2192 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2193 236, 0, 1, 4) 2194 2195 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE256TO511_CNT */ 2196 #define ASM_PMAC_RX_SIZE256TO511_CNT(g) \ 2197 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2198 240, 0, 1, 4) 2199 2200 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE512TO1023_CNT */ 2201 #define ASM_PMAC_RX_SIZE512TO1023_CNT(g) \ 2202 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2203 244, 0, 1, 4) 2204 2205 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE1024TO1518_CNT */ 2206 #define ASM_PMAC_RX_SIZE1024TO1518_CNT(g) \ 2207 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2208 248, 0, 1, 4) 2209 2210 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE1519TOMAX_CNT */ 2211 #define ASM_PMAC_RX_SIZE1519TOMAX_CNT(g) \ 2212 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2213 252, 0, 1, 4) 2214 2215 /* ASM:DEV_STATISTICS:PMAC_TX_PAUSE_CNT */ 2216 #define ASM_PMAC_TX_PAUSE_CNT(g) \ 2217 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2218 256, 0, 1, 4) 2219 2220 /* ASM:DEV_STATISTICS:PMAC_TX_OK_BYTES_CNT */ 2221 #define ASM_PMAC_TX_OK_BYTES_CNT(g) \ 2222 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2223 260, 0, 1, 4) 2224 2225 /* ASM:DEV_STATISTICS:PMAC_TX_UC_CNT */ 2226 #define ASM_PMAC_TX_UC_CNT(g) \ 2227 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2228 264, 0, 1, 4) 2229 2230 /* ASM:DEV_STATISTICS:PMAC_TX_MC_CNT */ 2231 #define ASM_PMAC_TX_MC_CNT(g) \ 2232 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2233 268, 0, 1, 4) 2234 2235 /* ASM:DEV_STATISTICS:PMAC_TX_BC_CNT */ 2236 #define ASM_PMAC_TX_BC_CNT(g) \ 2237 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2238 272, 0, 1, 4) 2239 2240 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE64_CNT */ 2241 #define ASM_PMAC_TX_SIZE64_CNT(g) \ 2242 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2243 276, 0, 1, 4) 2244 2245 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE65TO127_CNT */ 2246 #define ASM_PMAC_TX_SIZE65TO127_CNT(g) \ 2247 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2248 280, 0, 1, 4) 2249 2250 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE128TO255_CNT */ 2251 #define ASM_PMAC_TX_SIZE128TO255_CNT(g) \ 2252 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2253 284, 0, 1, 4) 2254 2255 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE256TO511_CNT */ 2256 #define ASM_PMAC_TX_SIZE256TO511_CNT(g) \ 2257 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2258 288, 0, 1, 4) 2259 2260 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE512TO1023_CNT */ 2261 #define ASM_PMAC_TX_SIZE512TO1023_CNT(g) \ 2262 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2263 292, 0, 1, 4) 2264 2265 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE1024TO1518_CNT */ 2266 #define ASM_PMAC_TX_SIZE1024TO1518_CNT(g) \ 2267 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2268 296, 0, 1, 4) 2269 2270 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE1519TOMAX_CNT */ 2271 #define ASM_PMAC_TX_SIZE1519TOMAX_CNT(g) \ 2272 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2273 300, 0, 1, 4) 2274 2275 /* ASM:DEV_STATISTICS:PMAC_RX_ALIGNMENT_LOST_CNT */ 2276 #define ASM_PMAC_RX_ALIGNMENT_LOST_CNT(g) \ 2277 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2278 304, 0, 1, 4) 2279 2280 /* ASM:DEV_STATISTICS:MM_RX_ASSEMBLY_ERR_CNT */ 2281 #define ASM_MM_RX_ASSEMBLY_ERR_CNT(g) \ 2282 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2283 308, 0, 1, 4) 2284 2285 /* ASM:DEV_STATISTICS:MM_RX_SMD_ERR_CNT */ 2286 #define ASM_MM_RX_SMD_ERR_CNT(g) \ 2287 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2288 312, 0, 1, 4) 2289 2290 /* ASM:DEV_STATISTICS:MM_RX_ASSEMBLY_OK_CNT */ 2291 #define ASM_MM_RX_ASSEMBLY_OK_CNT(g) \ 2292 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2293 316, 0, 1, 4) 2294 2295 /* ASM:DEV_STATISTICS:MM_RX_MERGE_FRAG_CNT */ 2296 #define ASM_MM_RX_MERGE_FRAG_CNT(g) \ 2297 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2298 320, 0, 1, 4) 2299 2300 /* ASM:DEV_STATISTICS:MM_TX_PFRAGMENT_CNT */ 2301 #define ASM_MM_TX_PFRAGMENT_CNT(g) \ 2302 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2303 324, 0, 1, 4) 2304 2305 /* ASM:DEV_STATISTICS:TX_MULTI_COLL_CNT */ 2306 #define ASM_TX_MULTI_COLL_CNT(g) \ 2307 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2308 328, 0, 1, 4) 2309 2310 /* ASM:DEV_STATISTICS:TX_LATE_COLL_CNT */ 2311 #define ASM_TX_LATE_COLL_CNT(g) \ 2312 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2313 332, 0, 1, 4) 2314 2315 /* ASM:DEV_STATISTICS:TX_XCOLL_CNT */ 2316 #define ASM_TX_XCOLL_CNT(g) \ 2317 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2318 336, 0, 1, 4) 2319 2320 /* ASM:DEV_STATISTICS:TX_DEFER_CNT */ 2321 #define ASM_TX_DEFER_CNT(g) \ 2322 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2323 340, 0, 1, 4) 2324 2325 /* ASM:DEV_STATISTICS:TX_XDEFER_CNT */ 2326 #define ASM_TX_XDEFER_CNT(g) \ 2327 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2328 344, 0, 1, 4) 2329 2330 /* ASM:DEV_STATISTICS:TX_BACKOFF1_CNT */ 2331 #define ASM_TX_BACKOFF1_CNT(g) \ 2332 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2333 348, 0, 1, 4) 2334 2335 /* ASM:DEV_STATISTICS:TX_CSENSE_CNT */ 2336 #define ASM_TX_CSENSE_CNT(g) \ 2337 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2338 352, 0, 1, 4) 2339 2340 /* ASM:DEV_STATISTICS:RX_IN_BYTES_MSB_CNT */ 2341 #define ASM_RX_IN_BYTES_MSB_CNT(g) \ 2342 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2343 356, 0, 1, 4) 2344 2345 #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT GENMASK(3, 0) 2346 #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_SET(x)\ 2347 FIELD_PREP(ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x) 2348 #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_GET(x)\ 2349 FIELD_GET(ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x) 2350 2351 /* ASM:DEV_STATISTICS:RX_OK_BYTES_MSB_CNT */ 2352 #define ASM_RX_OK_BYTES_MSB_CNT(g) \ 2353 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2354 360, 0, 1, 4) 2355 2356 #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT GENMASK(3, 0) 2357 #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_SET(x)\ 2358 FIELD_PREP(ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x) 2359 #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_GET(x)\ 2360 FIELD_GET(ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x) 2361 2362 /* ASM:DEV_STATISTICS:PMAC_RX_OK_BYTES_MSB_CNT */ 2363 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT(g) \ 2364 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2365 364, 0, 1, 4) 2366 2367 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT GENMASK(3, 0) 2368 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_SET(x)\ 2369 FIELD_PREP(ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x) 2370 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_GET(x)\ 2371 FIELD_GET(ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x) 2372 2373 /* ASM:DEV_STATISTICS:RX_BAD_BYTES_MSB_CNT */ 2374 #define ASM_RX_BAD_BYTES_MSB_CNT(g) \ 2375 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2376 368, 0, 1, 4) 2377 2378 #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT GENMASK(3, 0) 2379 #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_SET(x)\ 2380 FIELD_PREP(ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x) 2381 #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_GET(x)\ 2382 FIELD_GET(ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x) 2383 2384 /* ASM:DEV_STATISTICS:PMAC_RX_BAD_BYTES_MSB_CNT */ 2385 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT(g) \ 2386 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2387 372, 0, 1, 4) 2388 2389 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT GENMASK(3, 0) 2390 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_SET(x)\ 2391 FIELD_PREP(ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x) 2392 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_GET(x)\ 2393 FIELD_GET(ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x) 2394 2395 /* ASM:DEV_STATISTICS:TX_OUT_BYTES_MSB_CNT */ 2396 #define ASM_TX_OUT_BYTES_MSB_CNT(g) \ 2397 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2398 376, 0, 1, 4) 2399 2400 #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT GENMASK(3, 0) 2401 #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_SET(x)\ 2402 FIELD_PREP(ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x) 2403 #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_GET(x)\ 2404 FIELD_GET(ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x) 2405 2406 /* ASM:DEV_STATISTICS:TX_OK_BYTES_MSB_CNT */ 2407 #define ASM_TX_OK_BYTES_MSB_CNT(g) \ 2408 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2409 380, 0, 1, 4) 2410 2411 #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT GENMASK(3, 0) 2412 #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_SET(x)\ 2413 FIELD_PREP(ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x) 2414 #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_GET(x)\ 2415 FIELD_GET(ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x) 2416 2417 /* ASM:DEV_STATISTICS:PMAC_TX_OK_BYTES_MSB_CNT */ 2418 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT(g) \ 2419 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2420 384, 0, 1, 4) 2421 2422 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT GENMASK(3, 0) 2423 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_SET(x)\ 2424 FIELD_PREP(ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x) 2425 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_GET(x)\ 2426 FIELD_GET(ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x) 2427 2428 /* ASM:DEV_STATISTICS:RX_SYNC_LOST_ERR_CNT */ 2429 #define ASM_RX_SYNC_LOST_ERR_CNT(g) \ 2430 __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ 2431 388, 0, 1, 4) 2432 2433 /* ASM:CFG:STAT_CFG */ 2434 #define ASM_STAT_CFG \ 2435 __REG(TARGET_ASM, 0, 1, regs->gaddr[GA_ASM_CFG], 0, 1, \ 2436 regs->gsize[GW_ASM_CFG], 0, 0, 1, 4) 2437 2438 #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT BIT(0) 2439 #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT_SET(x)\ 2440 FIELD_PREP(ASM_STAT_CFG_STAT_CNT_CLR_SHOT, x) 2441 #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT_GET(x)\ 2442 FIELD_GET(ASM_STAT_CFG_STAT_CNT_CLR_SHOT, x) 2443 2444 /* ASM:CFG:PORT_CFG */ 2445 #define ASM_PORT_CFG(r) \ 2446 __REG(TARGET_ASM, 0, 1, regs->gaddr[GA_ASM_CFG], 0, 1, \ 2447 regs->gsize[GW_ASM_CFG], 540, r, regs->rcnt[RC_ASM_PORT_CFG], 4) 2448 2449 #define ASM_PORT_CFG_CSC_STAT_DIS BIT(12) 2450 #define ASM_PORT_CFG_CSC_STAT_DIS_SET(x)\ 2451 FIELD_PREP(ASM_PORT_CFG_CSC_STAT_DIS, x) 2452 #define ASM_PORT_CFG_CSC_STAT_DIS_GET(x)\ 2453 FIELD_GET(ASM_PORT_CFG_CSC_STAT_DIS, x) 2454 2455 #define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA BIT(11) 2456 #define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA_SET(x)\ 2457 FIELD_PREP(ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA, x) 2458 #define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA_GET(x)\ 2459 FIELD_GET(ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA, x) 2460 2461 #define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA BIT(10) 2462 #define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA_SET(x)\ 2463 FIELD_PREP(ASM_PORT_CFG_IGN_TAXI_ABORT_ENA, x) 2464 #define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA_GET(x)\ 2465 FIELD_GET(ASM_PORT_CFG_IGN_TAXI_ABORT_ENA, x) 2466 2467 #define ASM_PORT_CFG_NO_PREAMBLE_ENA BIT(9) 2468 #define ASM_PORT_CFG_NO_PREAMBLE_ENA_SET(x)\ 2469 FIELD_PREP(ASM_PORT_CFG_NO_PREAMBLE_ENA, x) 2470 #define ASM_PORT_CFG_NO_PREAMBLE_ENA_GET(x)\ 2471 FIELD_GET(ASM_PORT_CFG_NO_PREAMBLE_ENA, x) 2472 2473 #define ASM_PORT_CFG_SKIP_PREAMBLE_ENA BIT(8) 2474 #define ASM_PORT_CFG_SKIP_PREAMBLE_ENA_SET(x)\ 2475 FIELD_PREP(ASM_PORT_CFG_SKIP_PREAMBLE_ENA, x) 2476 #define ASM_PORT_CFG_SKIP_PREAMBLE_ENA_GET(x)\ 2477 FIELD_GET(ASM_PORT_CFG_SKIP_PREAMBLE_ENA, x) 2478 2479 #define ASM_PORT_CFG_FRM_AGING_DIS BIT(7) 2480 #define ASM_PORT_CFG_FRM_AGING_DIS_SET(x)\ 2481 FIELD_PREP(ASM_PORT_CFG_FRM_AGING_DIS, x) 2482 #define ASM_PORT_CFG_FRM_AGING_DIS_GET(x)\ 2483 FIELD_GET(ASM_PORT_CFG_FRM_AGING_DIS, x) 2484 2485 #define ASM_PORT_CFG_PAD_ENA BIT(6) 2486 #define ASM_PORT_CFG_PAD_ENA_SET(x)\ 2487 FIELD_PREP(ASM_PORT_CFG_PAD_ENA, x) 2488 #define ASM_PORT_CFG_PAD_ENA_GET(x)\ 2489 FIELD_GET(ASM_PORT_CFG_PAD_ENA, x) 2490 2491 #define ASM_PORT_CFG_INJ_DISCARD_CFG GENMASK(5, 4) 2492 #define ASM_PORT_CFG_INJ_DISCARD_CFG_SET(x)\ 2493 FIELD_PREP(ASM_PORT_CFG_INJ_DISCARD_CFG, x) 2494 #define ASM_PORT_CFG_INJ_DISCARD_CFG_GET(x)\ 2495 FIELD_GET(ASM_PORT_CFG_INJ_DISCARD_CFG, x) 2496 2497 #define ASM_PORT_CFG_INJ_FORMAT_CFG GENMASK(3, 2) 2498 #define ASM_PORT_CFG_INJ_FORMAT_CFG_SET(x)\ 2499 FIELD_PREP(ASM_PORT_CFG_INJ_FORMAT_CFG, x) 2500 #define ASM_PORT_CFG_INJ_FORMAT_CFG_GET(x)\ 2501 FIELD_GET(ASM_PORT_CFG_INJ_FORMAT_CFG, x) 2502 2503 #define ASM_PORT_CFG_VSTAX2_AWR_ENA BIT(1) 2504 #define ASM_PORT_CFG_VSTAX2_AWR_ENA_SET(x)\ 2505 FIELD_PREP(ASM_PORT_CFG_VSTAX2_AWR_ENA, x) 2506 #define ASM_PORT_CFG_VSTAX2_AWR_ENA_GET(x)\ 2507 FIELD_GET(ASM_PORT_CFG_VSTAX2_AWR_ENA, x) 2508 2509 #define ASM_PORT_CFG_PFRM_FLUSH BIT(0) 2510 #define ASM_PORT_CFG_PFRM_FLUSH_SET(x)\ 2511 FIELD_PREP(ASM_PORT_CFG_PFRM_FLUSH, x) 2512 #define ASM_PORT_CFG_PFRM_FLUSH_GET(x)\ 2513 FIELD_GET(ASM_PORT_CFG_PFRM_FLUSH, x) 2514 2515 /* ASM:RAM_CTRL:RAM_INIT */ 2516 #define ASM_RAM_INIT \ 2517 __REG(TARGET_ASM, 0, 1, regs->gaddr[GA_ASM_RAM_CTRL], 0, 1, 4, 0, 0, 1,\ 2518 4) 2519 2520 #define ASM_RAM_INIT_RAM_INIT BIT(1) 2521 #define ASM_RAM_INIT_RAM_INIT_SET(x)\ 2522 FIELD_PREP(ASM_RAM_INIT_RAM_INIT, x) 2523 #define ASM_RAM_INIT_RAM_INIT_GET(x)\ 2524 FIELD_GET(ASM_RAM_INIT_RAM_INIT, x) 2525 2526 #define ASM_RAM_INIT_RAM_CFG_HOOK BIT(0) 2527 #define ASM_RAM_INIT_RAM_CFG_HOOK_SET(x)\ 2528 FIELD_PREP(ASM_RAM_INIT_RAM_CFG_HOOK, x) 2529 #define ASM_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 2530 FIELD_GET(ASM_RAM_INIT_RAM_CFG_HOOK, x) 2531 2532 /* SPARX5 ONLY */ 2533 /* CLKGEN:LCPLL1:LCPLL1_CORE_CLK_CFG */ 2534 #define CLKGEN_LCPLL1_CORE_CLK_CFG \ 2535 __REG(TARGET_CLKGEN, 0, 1, 12, 0, 1, 36, 0, 0, 1, 4) 2536 2537 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV GENMASK(7, 0) 2538 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(x)\ 2539 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV, x) 2540 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_GET(x)\ 2541 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV, x) 2542 2543 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV GENMASK(10, 8) 2544 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_SET(x)\ 2545 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV, x) 2546 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_GET(x)\ 2547 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV, x) 2548 2549 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR BIT(11) 2550 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_SET(x)\ 2551 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR, x) 2552 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_GET(x)\ 2553 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR, x) 2554 2555 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL GENMASK(13, 12) 2556 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_SET(x)\ 2557 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL, x) 2558 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_GET(x)\ 2559 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL, x) 2560 2561 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA BIT(14) 2562 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_SET(x)\ 2563 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA, x) 2564 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_GET(x)\ 2565 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA, x) 2566 2567 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA BIT(15) 2568 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_SET(x)\ 2569 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, x) 2570 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_GET(x)\ 2571 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, x) 2572 2573 /* CPU:CPU_REGS:PROC_CTRL */ 2574 #define CPU_PROC_CTRL \ 2575 __REG(TARGET_CPU, 0, 1, 0, 0, 1, regs->gsize[GW_CPU_CPU_REGS], \ 2576 regs->raddr[RA_CPU_PROC_CTRL], 0, 1, 4) 2577 2578 #define CPU_PROC_CTRL_AARCH64_MODE_ENA\ 2579 BIT(regs->fpos[FP_CPU_PROC_CTRL_AARCH64_MODE_ENA]) 2580 #define CPU_PROC_CTRL_AARCH64_MODE_ENA_SET(x)\ 2581 spx5_field_prep(CPU_PROC_CTRL_AARCH64_MODE_ENA, x) 2582 #define CPU_PROC_CTRL_AARCH64_MODE_ENA_GET(x)\ 2583 spx5_field_get(CPU_PROC_CTRL_AARCH64_MODE_ENA, x) 2584 2585 #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS\ 2586 BIT(regs->fpos[FP_CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS]) 2587 #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS_SET(x)\ 2588 spx5_field_prep(CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS, x) 2589 #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS_GET(x)\ 2590 spx5_field_get(CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS, x) 2591 2592 #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS\ 2593 BIT(regs->fpos[FP_CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS]) 2594 #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS_SET(x)\ 2595 spx5_field_prep(CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS, x) 2596 #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS_GET(x)\ 2597 spx5_field_get(CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS, x) 2598 2599 #define CPU_PROC_CTRL_BE_EXCEP_MODE\ 2600 BIT(regs->fpos[FP_CPU_PROC_CTRL_BE_EXCEP_MODE]) 2601 #define CPU_PROC_CTRL_BE_EXCEP_MODE_SET(x)\ 2602 spx5_field_prep(CPU_PROC_CTRL_BE_EXCEP_MODE, x) 2603 #define CPU_PROC_CTRL_BE_EXCEP_MODE_GET(x)\ 2604 spx5_field_get(CPU_PROC_CTRL_BE_EXCEP_MODE, x) 2605 2606 #define CPU_PROC_CTRL_VINITHI\ 2607 BIT(regs->fpos[FP_CPU_PROC_CTRL_VINITHI]) 2608 #define CPU_PROC_CTRL_VINITHI_SET(x)\ 2609 spx5_field_prep(CPU_PROC_CTRL_VINITHI, x) 2610 #define CPU_PROC_CTRL_VINITHI_GET(x)\ 2611 spx5_field_get(CPU_PROC_CTRL_VINITHI, x) 2612 2613 #define CPU_PROC_CTRL_CFGTE\ 2614 BIT(regs->fpos[FP_CPU_PROC_CTRL_CFGTE]) 2615 #define CPU_PROC_CTRL_CFGTE_SET(x)\ 2616 spx5_field_prep(CPU_PROC_CTRL_CFGTE, x) 2617 #define CPU_PROC_CTRL_CFGTE_GET(x)\ 2618 spx5_field_get(CPU_PROC_CTRL_CFGTE, x) 2619 2620 #define CPU_PROC_CTRL_CP15S_DISABLE\ 2621 BIT(regs->fpos[FP_CPU_PROC_CTRL_CP15S_DISABLE]) 2622 #define CPU_PROC_CTRL_CP15S_DISABLE_SET(x)\ 2623 spx5_field_prep(CPU_PROC_CTRL_CP15S_DISABLE, x) 2624 #define CPU_PROC_CTRL_CP15S_DISABLE_GET(x)\ 2625 spx5_field_get(CPU_PROC_CTRL_CP15S_DISABLE, x) 2626 2627 #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE\ 2628 BIT(regs->fpos[FP_CPU_PROC_CTRL_PROC_CRYPTO_DISABLE]) 2629 #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_SET(x)\ 2630 spx5_field_prep(CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, x) 2631 #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_GET(x)\ 2632 spx5_field_get(CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, x) 2633 2634 /* SPARX5 ONLY */ 2635 #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA BIT(4) 2636 #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA_SET(x)\ 2637 FIELD_PREP(CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA, x) 2638 #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA_GET(x)\ 2639 FIELD_GET(CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA, x) 2640 2641 /* SPARX5 ONLY */ 2642 #define CPU_PROC_CTRL_ACP_AWCACHE BIT(3) 2643 #define CPU_PROC_CTRL_ACP_AWCACHE_SET(x)\ 2644 FIELD_PREP(CPU_PROC_CTRL_ACP_AWCACHE, x) 2645 #define CPU_PROC_CTRL_ACP_AWCACHE_GET(x)\ 2646 FIELD_GET(CPU_PROC_CTRL_ACP_AWCACHE, x) 2647 2648 /* SPARX5 ONLY */ 2649 #define CPU_PROC_CTRL_ACP_ARCACHE BIT(2) 2650 #define CPU_PROC_CTRL_ACP_ARCACHE_SET(x)\ 2651 FIELD_PREP(CPU_PROC_CTRL_ACP_ARCACHE, x) 2652 #define CPU_PROC_CTRL_ACP_ARCACHE_GET(x)\ 2653 FIELD_GET(CPU_PROC_CTRL_ACP_ARCACHE, x) 2654 2655 #define CPU_PROC_CTRL_L2_FLUSH_REQ\ 2656 BIT(regs->fpos[FP_CPU_PROC_CTRL_L2_FLUSH_REQ]) 2657 #define CPU_PROC_CTRL_L2_FLUSH_REQ_SET(x)\ 2658 spx5_field_prep(CPU_PROC_CTRL_L2_FLUSH_REQ, x) 2659 #define CPU_PROC_CTRL_L2_FLUSH_REQ_GET(x)\ 2660 spx5_field_get(CPU_PROC_CTRL_L2_FLUSH_REQ, x) 2661 2662 /* SPARX5 ONLY */ 2663 #define CPU_PROC_CTRL_ACP_DISABLE BIT(0) 2664 #define CPU_PROC_CTRL_ACP_DISABLE_SET(x)\ 2665 FIELD_PREP(CPU_PROC_CTRL_ACP_DISABLE, x) 2666 #define CPU_PROC_CTRL_ACP_DISABLE_GET(x)\ 2667 FIELD_GET(CPU_PROC_CTRL_ACP_DISABLE, x) 2668 2669 /* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */ 2670 #define DEV10G_MAC_ENA_CFG(t) \ 2671 __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 0, 0, 1, \ 2672 4) 2673 2674 #define DEV10G_MAC_ENA_CFG_RX_ENA BIT(4) 2675 #define DEV10G_MAC_ENA_CFG_RX_ENA_SET(x)\ 2676 FIELD_PREP(DEV10G_MAC_ENA_CFG_RX_ENA, x) 2677 #define DEV10G_MAC_ENA_CFG_RX_ENA_GET(x)\ 2678 FIELD_GET(DEV10G_MAC_ENA_CFG_RX_ENA, x) 2679 2680 #define DEV10G_MAC_ENA_CFG_TX_ENA BIT(0) 2681 #define DEV10G_MAC_ENA_CFG_TX_ENA_SET(x)\ 2682 FIELD_PREP(DEV10G_MAC_ENA_CFG_TX_ENA, x) 2683 #define DEV10G_MAC_ENA_CFG_TX_ENA_GET(x)\ 2684 FIELD_GET(DEV10G_MAC_ENA_CFG_TX_ENA, x) 2685 2686 /* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ 2687 #define DEV10G_MAC_MAXLEN_CFG(t) \ 2688 __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 8, 0, 1, \ 2689 4) 2690 2691 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK BIT(16) 2692 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\ 2693 FIELD_PREP(DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x) 2694 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\ 2695 FIELD_GET(DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x) 2696 2697 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0) 2698 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\ 2699 FIELD_PREP(DEV10G_MAC_MAXLEN_CFG_MAX_LEN, x) 2700 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ 2701 FIELD_GET(DEV10G_MAC_MAXLEN_CFG_MAX_LEN, x) 2702 2703 /* DEV10G:MAC_CFG_STATUS:MAC_NUM_TAGS_CFG */ 2704 #define DEV10G_MAC_NUM_TAGS_CFG(t) \ 2705 __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 12, 0, 1, \ 2706 4) 2707 2708 #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS GENMASK(1, 0) 2709 #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS_SET(x)\ 2710 FIELD_PREP(DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS, x) 2711 #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS_GET(x)\ 2712 FIELD_GET(DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS, x) 2713 2714 /* DEV10G:MAC_CFG_STATUS:MAC_TAGS_CFG */ 2715 #define DEV10G_MAC_TAGS_CFG(t, r) \ 2716 __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 16, r, 3, \ 2717 4) 2718 2719 #define DEV10G_MAC_TAGS_CFG_TAG_ID GENMASK(31, 16) 2720 #define DEV10G_MAC_TAGS_CFG_TAG_ID_SET(x)\ 2721 FIELD_PREP(DEV10G_MAC_TAGS_CFG_TAG_ID, x) 2722 #define DEV10G_MAC_TAGS_CFG_TAG_ID_GET(x)\ 2723 FIELD_GET(DEV10G_MAC_TAGS_CFG_TAG_ID, x) 2724 2725 #define DEV10G_MAC_TAGS_CFG_TAG_ENA BIT(4) 2726 #define DEV10G_MAC_TAGS_CFG_TAG_ENA_SET(x)\ 2727 FIELD_PREP(DEV10G_MAC_TAGS_CFG_TAG_ENA, x) 2728 #define DEV10G_MAC_TAGS_CFG_TAG_ENA_GET(x)\ 2729 FIELD_GET(DEV10G_MAC_TAGS_CFG_TAG_ENA, x) 2730 2731 /* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ 2732 #define DEV10G_MAC_ADV_CHK_CFG(t) \ 2733 __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 28, 0, 1, \ 2734 4) 2735 2736 #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA BIT(24) 2737 #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\ 2738 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x) 2739 #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\ 2740 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x) 2741 2742 #define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA BIT(20) 2743 #define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\ 2744 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x) 2745 #define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\ 2746 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x) 2747 2748 #define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA BIT(16) 2749 #define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\ 2750 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x) 2751 #define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\ 2752 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x) 2753 2754 #define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS BIT(12) 2755 #define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\ 2756 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x) 2757 #define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\ 2758 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x) 2759 2760 #define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA BIT(8) 2761 #define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\ 2762 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x) 2763 #define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\ 2764 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x) 2765 2766 #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA BIT(4) 2767 #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\ 2768 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x) 2769 #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\ 2770 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x) 2771 2772 #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA BIT(0) 2773 #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\ 2774 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x) 2775 #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\ 2776 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x) 2777 2778 /* DEV10G:MAC_CFG_STATUS:MAC_TX_MONITOR_STICKY */ 2779 #define DEV10G_MAC_TX_MONITOR_STICKY(t) \ 2780 __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 48, 0, 1, \ 2781 4) 2782 2783 #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY BIT(4) 2784 #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY_SET(x)\ 2785 FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY, x) 2786 #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY_GET(x)\ 2787 FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY, x) 2788 2789 #define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY BIT(3) 2790 #define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY_SET(x)\ 2791 FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY, x) 2792 #define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY_GET(x)\ 2793 FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY, x) 2794 2795 #define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY BIT(2) 2796 #define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY_SET(x)\ 2797 FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY, x) 2798 #define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY_GET(x)\ 2799 FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY, x) 2800 2801 #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY BIT(1) 2802 #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY_SET(x)\ 2803 FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY, x) 2804 #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY_GET(x)\ 2805 FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY, x) 2806 2807 #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY BIT(0) 2808 #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY_SET(x)\ 2809 FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY, x) 2810 #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY_GET(x)\ 2811 FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY, x) 2812 2813 /* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */ 2814 #define DEV10G_DEV_RST_CTRL(t) \ 2815 __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 436, 0, 1, 52, 0, 0, 1,\ 2816 4) 2817 2818 #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA BIT(28) 2819 #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\ 2820 FIELD_PREP(DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA, x) 2821 #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\ 2822 FIELD_GET(DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA, x) 2823 2824 #define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS BIT(27) 2825 #define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\ 2826 FIELD_PREP(DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) 2827 #define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\ 2828 FIELD_GET(DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) 2829 2830 #define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS GENMASK(26, 25) 2831 #define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\ 2832 FIELD_PREP(DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x) 2833 #define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\ 2834 FIELD_GET(DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x) 2835 2836 #define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL GENMASK(24, 23) 2837 #define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\ 2838 FIELD_PREP(DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL, x) 2839 #define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\ 2840 FIELD_GET(DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL, x) 2841 2842 #define DEV10G_DEV_RST_CTRL_SPEED_SEL GENMASK(22, 20) 2843 #define DEV10G_DEV_RST_CTRL_SPEED_SEL_SET(x)\ 2844 FIELD_PREP(DEV10G_DEV_RST_CTRL_SPEED_SEL, x) 2845 #define DEV10G_DEV_RST_CTRL_SPEED_SEL_GET(x)\ 2846 FIELD_GET(DEV10G_DEV_RST_CTRL_SPEED_SEL, x) 2847 2848 #define DEV10G_DEV_RST_CTRL_PCS_TX_RST BIT(12) 2849 #define DEV10G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\ 2850 FIELD_PREP(DEV10G_DEV_RST_CTRL_PCS_TX_RST, x) 2851 #define DEV10G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\ 2852 FIELD_GET(DEV10G_DEV_RST_CTRL_PCS_TX_RST, x) 2853 2854 #define DEV10G_DEV_RST_CTRL_PCS_RX_RST BIT(8) 2855 #define DEV10G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\ 2856 FIELD_PREP(DEV10G_DEV_RST_CTRL_PCS_RX_RST, x) 2857 #define DEV10G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\ 2858 FIELD_GET(DEV10G_DEV_RST_CTRL_PCS_RX_RST, x) 2859 2860 #define DEV10G_DEV_RST_CTRL_MAC_TX_RST BIT(4) 2861 #define DEV10G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\ 2862 FIELD_PREP(DEV10G_DEV_RST_CTRL_MAC_TX_RST, x) 2863 #define DEV10G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\ 2864 FIELD_GET(DEV10G_DEV_RST_CTRL_MAC_TX_RST, x) 2865 2866 #define DEV10G_DEV_RST_CTRL_MAC_RX_RST BIT(0) 2867 #define DEV10G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\ 2868 FIELD_PREP(DEV10G_DEV_RST_CTRL_MAC_RX_RST, x) 2869 #define DEV10G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ 2870 FIELD_GET(DEV10G_DEV_RST_CTRL_MAC_RX_RST, x) 2871 2872 /* DEV10G:PCS25G_CFG_STATUS:PCS25G_CFG */ 2873 #define DEV10G_PCS25G_CFG(t) \ 2874 __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 488, 0, 1, 32, 0, 0, 1,\ 2875 4) 2876 2877 #define DEV10G_PCS25G_CFG_PCS25G_ENA BIT(0) 2878 #define DEV10G_PCS25G_CFG_PCS25G_ENA_SET(x)\ 2879 FIELD_PREP(DEV10G_PCS25G_CFG_PCS25G_ENA, x) 2880 #define DEV10G_PCS25G_CFG_PCS25G_ENA_GET(x)\ 2881 FIELD_GET(DEV10G_PCS25G_CFG_PCS25G_ENA, x) 2882 2883 /* SPARX5 ONLY */ 2884 /* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */ 2885 #define DEV25G_MAC_ENA_CFG(t) \ 2886 __REG(TARGET_DEV25G, t, 8, 0, 0, 1, 60, 0, 0, 1, 4) 2887 2888 #define DEV25G_MAC_ENA_CFG_RX_ENA BIT(4) 2889 #define DEV25G_MAC_ENA_CFG_RX_ENA_SET(x)\ 2890 FIELD_PREP(DEV25G_MAC_ENA_CFG_RX_ENA, x) 2891 #define DEV25G_MAC_ENA_CFG_RX_ENA_GET(x)\ 2892 FIELD_GET(DEV25G_MAC_ENA_CFG_RX_ENA, x) 2893 2894 #define DEV25G_MAC_ENA_CFG_TX_ENA BIT(0) 2895 #define DEV25G_MAC_ENA_CFG_TX_ENA_SET(x)\ 2896 FIELD_PREP(DEV25G_MAC_ENA_CFG_TX_ENA, x) 2897 #define DEV25G_MAC_ENA_CFG_TX_ENA_GET(x)\ 2898 FIELD_GET(DEV25G_MAC_ENA_CFG_TX_ENA, x) 2899 2900 /* SPARX5 ONLY */ 2901 /* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ 2902 #define DEV25G_MAC_MAXLEN_CFG(t) \ 2903 __REG(TARGET_DEV25G, t, 8, 0, 0, 1, 60, 8, 0, 1, 4) 2904 2905 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK BIT(16) 2906 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\ 2907 FIELD_PREP(DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x) 2908 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\ 2909 FIELD_GET(DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x) 2910 2911 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0) 2912 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\ 2913 FIELD_PREP(DEV25G_MAC_MAXLEN_CFG_MAX_LEN, x) 2914 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ 2915 FIELD_GET(DEV25G_MAC_MAXLEN_CFG_MAX_LEN, x) 2916 2917 /* SPARX5 ONLY */ 2918 /* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ 2919 #define DEV25G_MAC_ADV_CHK_CFG(t) \ 2920 __REG(TARGET_DEV25G, t, 8, 0, 0, 1, 60, 28, 0, 1, 4) 2921 2922 #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA BIT(24) 2923 #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\ 2924 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x) 2925 #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\ 2926 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x) 2927 2928 #define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA BIT(20) 2929 #define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\ 2930 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x) 2931 #define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\ 2932 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x) 2933 2934 #define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA BIT(16) 2935 #define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\ 2936 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x) 2937 #define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\ 2938 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x) 2939 2940 #define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS BIT(12) 2941 #define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\ 2942 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x) 2943 #define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\ 2944 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x) 2945 2946 #define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA BIT(8) 2947 #define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\ 2948 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x) 2949 #define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\ 2950 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x) 2951 2952 #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA BIT(4) 2953 #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\ 2954 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x) 2955 #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\ 2956 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x) 2957 2958 #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA BIT(0) 2959 #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\ 2960 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x) 2961 #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\ 2962 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x) 2963 2964 /* SPARX5 ONLY */ 2965 /* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */ 2966 #define DEV25G_DEV_RST_CTRL(t) \ 2967 __REG(TARGET_DEV25G, t, 8, 436, 0, 1, 52, 0, 0, 1, 4) 2968 2969 #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA BIT(28) 2970 #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\ 2971 FIELD_PREP(DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA, x) 2972 #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\ 2973 FIELD_GET(DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA, x) 2974 2975 #define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS BIT(27) 2976 #define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\ 2977 FIELD_PREP(DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) 2978 #define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\ 2979 FIELD_GET(DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) 2980 2981 #define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS GENMASK(26, 25) 2982 #define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\ 2983 FIELD_PREP(DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x) 2984 #define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\ 2985 FIELD_GET(DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x) 2986 2987 #define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL GENMASK(24, 23) 2988 #define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\ 2989 FIELD_PREP(DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL, x) 2990 #define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\ 2991 FIELD_GET(DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL, x) 2992 2993 #define DEV25G_DEV_RST_CTRL_SPEED_SEL GENMASK(22, 20) 2994 #define DEV25G_DEV_RST_CTRL_SPEED_SEL_SET(x)\ 2995 FIELD_PREP(DEV25G_DEV_RST_CTRL_SPEED_SEL, x) 2996 #define DEV25G_DEV_RST_CTRL_SPEED_SEL_GET(x)\ 2997 FIELD_GET(DEV25G_DEV_RST_CTRL_SPEED_SEL, x) 2998 2999 #define DEV25G_DEV_RST_CTRL_PCS_TX_RST BIT(12) 3000 #define DEV25G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\ 3001 FIELD_PREP(DEV25G_DEV_RST_CTRL_PCS_TX_RST, x) 3002 #define DEV25G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\ 3003 FIELD_GET(DEV25G_DEV_RST_CTRL_PCS_TX_RST, x) 3004 3005 #define DEV25G_DEV_RST_CTRL_PCS_RX_RST BIT(8) 3006 #define DEV25G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\ 3007 FIELD_PREP(DEV25G_DEV_RST_CTRL_PCS_RX_RST, x) 3008 #define DEV25G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\ 3009 FIELD_GET(DEV25G_DEV_RST_CTRL_PCS_RX_RST, x) 3010 3011 #define DEV25G_DEV_RST_CTRL_MAC_TX_RST BIT(4) 3012 #define DEV25G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\ 3013 FIELD_PREP(DEV25G_DEV_RST_CTRL_MAC_TX_RST, x) 3014 #define DEV25G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\ 3015 FIELD_GET(DEV25G_DEV_RST_CTRL_MAC_TX_RST, x) 3016 3017 #define DEV25G_DEV_RST_CTRL_MAC_RX_RST BIT(0) 3018 #define DEV25G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\ 3019 FIELD_PREP(DEV25G_DEV_RST_CTRL_MAC_RX_RST, x) 3020 #define DEV25G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ 3021 FIELD_GET(DEV25G_DEV_RST_CTRL_MAC_RX_RST, x) 3022 3023 /* SPARX5 ONLY */ 3024 /* DEV10G:PCS25G_CFG_STATUS:PCS25G_CFG */ 3025 #define DEV25G_PCS25G_CFG(t) \ 3026 __REG(TARGET_DEV25G, t, 8, 488, 0, 1, 32, 0, 0, 1, 4) 3027 3028 #define DEV25G_PCS25G_CFG_PCS25G_ENA BIT(0) 3029 #define DEV25G_PCS25G_CFG_PCS25G_ENA_SET(x)\ 3030 FIELD_PREP(DEV25G_PCS25G_CFG_PCS25G_ENA, x) 3031 #define DEV25G_PCS25G_CFG_PCS25G_ENA_GET(x)\ 3032 FIELD_GET(DEV25G_PCS25G_CFG_PCS25G_ENA, x) 3033 3034 /* SPARX5 ONLY */ 3035 /* DEV10G:PCS25G_CFG_STATUS:PCS25G_SD_CFG */ 3036 #define DEV25G_PCS25G_SD_CFG(t) \ 3037 __REG(TARGET_DEV25G, t, 8, 488, 0, 1, 32, 4, 0, 1, 4) 3038 3039 #define DEV25G_PCS25G_SD_CFG_SD_SEL BIT(8) 3040 #define DEV25G_PCS25G_SD_CFG_SD_SEL_SET(x)\ 3041 FIELD_PREP(DEV25G_PCS25G_SD_CFG_SD_SEL, x) 3042 #define DEV25G_PCS25G_SD_CFG_SD_SEL_GET(x)\ 3043 FIELD_GET(DEV25G_PCS25G_SD_CFG_SD_SEL, x) 3044 3045 #define DEV25G_PCS25G_SD_CFG_SD_POL BIT(4) 3046 #define DEV25G_PCS25G_SD_CFG_SD_POL_SET(x)\ 3047 FIELD_PREP(DEV25G_PCS25G_SD_CFG_SD_POL, x) 3048 #define DEV25G_PCS25G_SD_CFG_SD_POL_GET(x)\ 3049 FIELD_GET(DEV25G_PCS25G_SD_CFG_SD_POL, x) 3050 3051 #define DEV25G_PCS25G_SD_CFG_SD_ENA BIT(0) 3052 #define DEV25G_PCS25G_SD_CFG_SD_ENA_SET(x)\ 3053 FIELD_PREP(DEV25G_PCS25G_SD_CFG_SD_ENA, x) 3054 #define DEV25G_PCS25G_SD_CFG_SD_ENA_GET(x)\ 3055 FIELD_GET(DEV25G_PCS25G_SD_CFG_SD_ENA, x) 3056 3057 /* DEV1G:DEV_CFG_STATUS:DEV_RST_CTRL */ 3058 #define DEV2G5_DEV_RST_CTRL(t) \ 3059 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 0, 0, 1, 36, 0, 0, 1, \ 3060 4) 3061 3062 #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS BIT(23) 3063 #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\ 3064 FIELD_PREP(DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) 3065 #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\ 3066 FIELD_GET(DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) 3067 3068 #define DEV2G5_DEV_RST_CTRL_SPEED_SEL GENMASK(22, 20) 3069 #define DEV2G5_DEV_RST_CTRL_SPEED_SEL_SET(x)\ 3070 FIELD_PREP(DEV2G5_DEV_RST_CTRL_SPEED_SEL, x) 3071 #define DEV2G5_DEV_RST_CTRL_SPEED_SEL_GET(x)\ 3072 FIELD_GET(DEV2G5_DEV_RST_CTRL_SPEED_SEL, x) 3073 3074 #define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST BIT(17) 3075 #define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST_SET(x)\ 3076 FIELD_PREP(DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST, x) 3077 #define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST_GET(x)\ 3078 FIELD_GET(DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST, x) 3079 3080 #define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST BIT(16) 3081 #define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST_SET(x)\ 3082 FIELD_PREP(DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST, x) 3083 #define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST_GET(x)\ 3084 FIELD_GET(DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST, x) 3085 3086 #define DEV2G5_DEV_RST_CTRL_PCS_TX_RST BIT(12) 3087 #define DEV2G5_DEV_RST_CTRL_PCS_TX_RST_SET(x)\ 3088 FIELD_PREP(DEV2G5_DEV_RST_CTRL_PCS_TX_RST, x) 3089 #define DEV2G5_DEV_RST_CTRL_PCS_TX_RST_GET(x)\ 3090 FIELD_GET(DEV2G5_DEV_RST_CTRL_PCS_TX_RST, x) 3091 3092 #define DEV2G5_DEV_RST_CTRL_PCS_RX_RST BIT(8) 3093 #define DEV2G5_DEV_RST_CTRL_PCS_RX_RST_SET(x)\ 3094 FIELD_PREP(DEV2G5_DEV_RST_CTRL_PCS_RX_RST, x) 3095 #define DEV2G5_DEV_RST_CTRL_PCS_RX_RST_GET(x)\ 3096 FIELD_GET(DEV2G5_DEV_RST_CTRL_PCS_RX_RST, x) 3097 3098 #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST BIT(4) 3099 #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST_SET(x)\ 3100 FIELD_PREP(DEV2G5_DEV_RST_CTRL_MAC_TX_RST, x) 3101 #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST_GET(x)\ 3102 FIELD_GET(DEV2G5_DEV_RST_CTRL_MAC_TX_RST, x) 3103 3104 #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST BIT(0) 3105 #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST_SET(x)\ 3106 FIELD_PREP(DEV2G5_DEV_RST_CTRL_MAC_RX_RST, x) 3107 #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ 3108 FIELD_GET(DEV2G5_DEV_RST_CTRL_MAC_RX_RST, x) 3109 3110 /* DEV1G:MAC_CFG_STATUS:MAC_ENA_CFG */ 3111 #define DEV2G5_MAC_ENA_CFG(t) \ 3112 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 0, 0, 1, \ 3113 4) 3114 3115 #define DEV2G5_MAC_ENA_CFG_RX_ENA BIT(4) 3116 #define DEV2G5_MAC_ENA_CFG_RX_ENA_SET(x)\ 3117 FIELD_PREP(DEV2G5_MAC_ENA_CFG_RX_ENA, x) 3118 #define DEV2G5_MAC_ENA_CFG_RX_ENA_GET(x)\ 3119 FIELD_GET(DEV2G5_MAC_ENA_CFG_RX_ENA, x) 3120 3121 #define DEV2G5_MAC_ENA_CFG_TX_ENA BIT(0) 3122 #define DEV2G5_MAC_ENA_CFG_TX_ENA_SET(x)\ 3123 FIELD_PREP(DEV2G5_MAC_ENA_CFG_TX_ENA, x) 3124 #define DEV2G5_MAC_ENA_CFG_TX_ENA_GET(x)\ 3125 FIELD_GET(DEV2G5_MAC_ENA_CFG_TX_ENA, x) 3126 3127 /* DEV1G:MAC_CFG_STATUS:MAC_MODE_CFG */ 3128 #define DEV2G5_MAC_MODE_CFG(t) \ 3129 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 4, 0, 1, \ 3130 4) 3131 3132 #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA BIT(8) 3133 #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA_SET(x)\ 3134 FIELD_PREP(DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA, x) 3135 #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA_GET(x)\ 3136 FIELD_GET(DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA, x) 3137 3138 #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA BIT(4) 3139 #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA_SET(x)\ 3140 FIELD_PREP(DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA, x) 3141 #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA_GET(x)\ 3142 FIELD_GET(DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA, x) 3143 3144 #define DEV2G5_MAC_MODE_CFG_FDX_ENA BIT(0) 3145 #define DEV2G5_MAC_MODE_CFG_FDX_ENA_SET(x)\ 3146 FIELD_PREP(DEV2G5_MAC_MODE_CFG_FDX_ENA, x) 3147 #define DEV2G5_MAC_MODE_CFG_FDX_ENA_GET(x)\ 3148 FIELD_GET(DEV2G5_MAC_MODE_CFG_FDX_ENA, x) 3149 3150 /* DEV1G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ 3151 #define DEV2G5_MAC_MAXLEN_CFG(t) \ 3152 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 8, 0, 1, \ 3153 4) 3154 3155 #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0) 3156 #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\ 3157 FIELD_PREP(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN, x) 3158 #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ 3159 FIELD_GET(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN, x) 3160 3161 /* DEV1G:MAC_CFG_STATUS:MAC_TAGS_CFG */ 3162 #define DEV2G5_MAC_TAGS_CFG(t) \ 3163 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 12, 0, 1,\ 3164 4) 3165 3166 #define DEV2G5_MAC_TAGS_CFG_TAG_ID GENMASK(31, 16) 3167 #define DEV2G5_MAC_TAGS_CFG_TAG_ID_SET(x)\ 3168 FIELD_PREP(DEV2G5_MAC_TAGS_CFG_TAG_ID, x) 3169 #define DEV2G5_MAC_TAGS_CFG_TAG_ID_GET(x)\ 3170 FIELD_GET(DEV2G5_MAC_TAGS_CFG_TAG_ID, x) 3171 3172 #define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA BIT(3) 3173 #define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_SET(x)\ 3174 FIELD_PREP(DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, x) 3175 #define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_GET(x)\ 3176 FIELD_GET(DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, x) 3177 3178 #define DEV2G5_MAC_TAGS_CFG_PB_ENA GENMASK(2, 1) 3179 #define DEV2G5_MAC_TAGS_CFG_PB_ENA_SET(x)\ 3180 FIELD_PREP(DEV2G5_MAC_TAGS_CFG_PB_ENA, x) 3181 #define DEV2G5_MAC_TAGS_CFG_PB_ENA_GET(x)\ 3182 FIELD_GET(DEV2G5_MAC_TAGS_CFG_PB_ENA, x) 3183 3184 #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA BIT(0) 3185 #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA_SET(x)\ 3186 FIELD_PREP(DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA, x) 3187 #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA_GET(x)\ 3188 FIELD_GET(DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA, x) 3189 3190 /* DEV1G:MAC_CFG_STATUS:MAC_TAGS_CFG2 */ 3191 #define DEV2G5_MAC_TAGS_CFG2(t) \ 3192 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 16, 0, 1,\ 3193 4) 3194 3195 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3 GENMASK(31, 16) 3196 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3_SET(x)\ 3197 FIELD_PREP(DEV2G5_MAC_TAGS_CFG2_TAG_ID3, x) 3198 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3_GET(x)\ 3199 FIELD_GET(DEV2G5_MAC_TAGS_CFG2_TAG_ID3, x) 3200 3201 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2 GENMASK(15, 0) 3202 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2_SET(x)\ 3203 FIELD_PREP(DEV2G5_MAC_TAGS_CFG2_TAG_ID2, x) 3204 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2_GET(x)\ 3205 FIELD_GET(DEV2G5_MAC_TAGS_CFG2_TAG_ID2, x) 3206 3207 /* DEV1G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ 3208 #define DEV2G5_MAC_ADV_CHK_CFG(t) \ 3209 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 20, 0, 1,\ 3210 4) 3211 3212 #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA BIT(0) 3213 #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA_SET(x)\ 3214 FIELD_PREP(DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA, x) 3215 #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA_GET(x)\ 3216 FIELD_GET(DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA, x) 3217 3218 /* DEV1G:MAC_CFG_STATUS:MAC_IFG_CFG */ 3219 #define DEV2G5_MAC_IFG_CFG(t) \ 3220 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 24, 0, 1,\ 3221 4) 3222 3223 #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK BIT(17) 3224 #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK_SET(x)\ 3225 FIELD_PREP(DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK, x) 3226 #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK_GET(x)\ 3227 FIELD_GET(DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK, x) 3228 3229 #define DEV2G5_MAC_IFG_CFG_TX_IFG GENMASK(12, 8) 3230 #define DEV2G5_MAC_IFG_CFG_TX_IFG_SET(x)\ 3231 FIELD_PREP(DEV2G5_MAC_IFG_CFG_TX_IFG, x) 3232 #define DEV2G5_MAC_IFG_CFG_TX_IFG_GET(x)\ 3233 FIELD_GET(DEV2G5_MAC_IFG_CFG_TX_IFG, x) 3234 3235 #define DEV2G5_MAC_IFG_CFG_RX_IFG2 GENMASK(7, 4) 3236 #define DEV2G5_MAC_IFG_CFG_RX_IFG2_SET(x)\ 3237 FIELD_PREP(DEV2G5_MAC_IFG_CFG_RX_IFG2, x) 3238 #define DEV2G5_MAC_IFG_CFG_RX_IFG2_GET(x)\ 3239 FIELD_GET(DEV2G5_MAC_IFG_CFG_RX_IFG2, x) 3240 3241 #define DEV2G5_MAC_IFG_CFG_RX_IFG1 GENMASK(3, 0) 3242 #define DEV2G5_MAC_IFG_CFG_RX_IFG1_SET(x)\ 3243 FIELD_PREP(DEV2G5_MAC_IFG_CFG_RX_IFG1, x) 3244 #define DEV2G5_MAC_IFG_CFG_RX_IFG1_GET(x)\ 3245 FIELD_GET(DEV2G5_MAC_IFG_CFG_RX_IFG1, x) 3246 3247 /* DEV1G:MAC_CFG_STATUS:MAC_HDX_CFG */ 3248 #define DEV2G5_MAC_HDX_CFG(t) \ 3249 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 28, 0, 1,\ 3250 4) 3251 3252 #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC BIT(26) 3253 #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC_SET(x)\ 3254 FIELD_PREP(DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC, x) 3255 #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC_GET(x)\ 3256 FIELD_GET(DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC, x) 3257 3258 #define DEV2G5_MAC_HDX_CFG_SEED GENMASK(23, 16) 3259 #define DEV2G5_MAC_HDX_CFG_SEED_SET(x)\ 3260 FIELD_PREP(DEV2G5_MAC_HDX_CFG_SEED, x) 3261 #define DEV2G5_MAC_HDX_CFG_SEED_GET(x)\ 3262 FIELD_GET(DEV2G5_MAC_HDX_CFG_SEED, x) 3263 3264 #define DEV2G5_MAC_HDX_CFG_SEED_LOAD BIT(12) 3265 #define DEV2G5_MAC_HDX_CFG_SEED_LOAD_SET(x)\ 3266 FIELD_PREP(DEV2G5_MAC_HDX_CFG_SEED_LOAD, x) 3267 #define DEV2G5_MAC_HDX_CFG_SEED_LOAD_GET(x)\ 3268 FIELD_GET(DEV2G5_MAC_HDX_CFG_SEED_LOAD, x) 3269 3270 #define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA BIT(8) 3271 #define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA_SET(x)\ 3272 FIELD_PREP(DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA, x) 3273 #define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA_GET(x)\ 3274 FIELD_GET(DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA, x) 3275 3276 #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS GENMASK(6, 0) 3277 #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS_SET(x)\ 3278 FIELD_PREP(DEV2G5_MAC_HDX_CFG_LATE_COL_POS, x) 3279 #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS_GET(x)\ 3280 FIELD_GET(DEV2G5_MAC_HDX_CFG_LATE_COL_POS, x) 3281 3282 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_CFG */ 3283 #define DEV2G5_PCS1G_CFG(t) \ 3284 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 0, 0, 1, \ 3285 4) 3286 3287 #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE BIT(4) 3288 #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE_SET(x)\ 3289 FIELD_PREP(DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE, x) 3290 #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE_GET(x)\ 3291 FIELD_GET(DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE, x) 3292 3293 #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA BIT(1) 3294 #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA_SET(x)\ 3295 FIELD_PREP(DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA, x) 3296 #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA_GET(x)\ 3297 FIELD_GET(DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA, x) 3298 3299 #define DEV2G5_PCS1G_CFG_PCS_ENA BIT(0) 3300 #define DEV2G5_PCS1G_CFG_PCS_ENA_SET(x)\ 3301 FIELD_PREP(DEV2G5_PCS1G_CFG_PCS_ENA, x) 3302 #define DEV2G5_PCS1G_CFG_PCS_ENA_GET(x)\ 3303 FIELD_GET(DEV2G5_PCS1G_CFG_PCS_ENA, x) 3304 3305 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_MODE_CFG */ 3306 #define DEV2G5_PCS1G_MODE_CFG(t) \ 3307 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 4, 0, 1, \ 3308 4) 3309 3310 #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA BIT(4) 3311 #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA_SET(x)\ 3312 FIELD_PREP(DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA, x) 3313 #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA_GET(x)\ 3314 FIELD_GET(DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA, x) 3315 3316 #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA BIT(1) 3317 #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_SET(x)\ 3318 FIELD_PREP(DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x) 3319 #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_GET(x)\ 3320 FIELD_GET(DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x) 3321 3322 #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0) 3323 #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(x)\ 3324 FIELD_PREP(DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA, x) 3325 #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_GET(x)\ 3326 FIELD_GET(DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA, x) 3327 3328 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_SD_CFG */ 3329 #define DEV2G5_PCS1G_SD_CFG(t) \ 3330 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 8, 0, 1, \ 3331 4) 3332 3333 #define DEV2G5_PCS1G_SD_CFG_SD_SEL BIT(8) 3334 #define DEV2G5_PCS1G_SD_CFG_SD_SEL_SET(x)\ 3335 FIELD_PREP(DEV2G5_PCS1G_SD_CFG_SD_SEL, x) 3336 #define DEV2G5_PCS1G_SD_CFG_SD_SEL_GET(x)\ 3337 FIELD_GET(DEV2G5_PCS1G_SD_CFG_SD_SEL, x) 3338 3339 #define DEV2G5_PCS1G_SD_CFG_SD_POL BIT(4) 3340 #define DEV2G5_PCS1G_SD_CFG_SD_POL_SET(x)\ 3341 FIELD_PREP(DEV2G5_PCS1G_SD_CFG_SD_POL, x) 3342 #define DEV2G5_PCS1G_SD_CFG_SD_POL_GET(x)\ 3343 FIELD_GET(DEV2G5_PCS1G_SD_CFG_SD_POL, x) 3344 3345 #define DEV2G5_PCS1G_SD_CFG_SD_ENA BIT(0) 3346 #define DEV2G5_PCS1G_SD_CFG_SD_ENA_SET(x)\ 3347 FIELD_PREP(DEV2G5_PCS1G_SD_CFG_SD_ENA, x) 3348 #define DEV2G5_PCS1G_SD_CFG_SD_ENA_GET(x)\ 3349 FIELD_GET(DEV2G5_PCS1G_SD_CFG_SD_ENA, x) 3350 3351 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_ANEG_CFG */ 3352 #define DEV2G5_PCS1G_ANEG_CFG(t) \ 3353 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 12, 0, 1,\ 3354 4) 3355 3356 #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY GENMASK(31, 16) 3357 #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_SET(x)\ 3358 FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY, x) 3359 #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_GET(x)\ 3360 FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY, x) 3361 3362 #define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA BIT(8) 3363 #define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_SET(x)\ 3364 FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x) 3365 #define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_GET(x)\ 3366 FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x) 3367 3368 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT BIT(1) 3369 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT_SET(x)\ 3370 FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT, x) 3371 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT_GET(x)\ 3372 FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT, x) 3373 3374 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA BIT(0) 3375 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_SET(x)\ 3376 FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA, x) 3377 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_GET(x)\ 3378 FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA, x) 3379 3380 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_LB_CFG */ 3381 #define DEV2G5_PCS1G_LB_CFG(t) \ 3382 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 20, 0, 1,\ 3383 4) 3384 3385 #define DEV2G5_PCS1G_LB_CFG_RA_ENA BIT(4) 3386 #define DEV2G5_PCS1G_LB_CFG_RA_ENA_SET(x)\ 3387 FIELD_PREP(DEV2G5_PCS1G_LB_CFG_RA_ENA, x) 3388 #define DEV2G5_PCS1G_LB_CFG_RA_ENA_GET(x)\ 3389 FIELD_GET(DEV2G5_PCS1G_LB_CFG_RA_ENA, x) 3390 3391 #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA BIT(1) 3392 #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA_SET(x)\ 3393 FIELD_PREP(DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA, x) 3394 #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA_GET(x)\ 3395 FIELD_GET(DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA, x) 3396 3397 #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA BIT(0) 3398 #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA_SET(x)\ 3399 FIELD_PREP(DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA, x) 3400 #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA_GET(x)\ 3401 FIELD_GET(DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA, x) 3402 3403 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_ANEG_STATUS */ 3404 #define DEV2G5_PCS1G_ANEG_STATUS(t) \ 3405 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 32, 0, 1,\ 3406 4) 3407 3408 #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY GENMASK(31, 16) 3409 #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY_SET(x)\ 3410 FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY, x) 3411 #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY_GET(x)\ 3412 FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY, x) 3413 3414 #define DEV2G5_PCS1G_ANEG_STATUS_PR BIT(4) 3415 #define DEV2G5_PCS1G_ANEG_STATUS_PR_SET(x)\ 3416 FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_PR, x) 3417 #define DEV2G5_PCS1G_ANEG_STATUS_PR_GET(x)\ 3418 FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_PR, x) 3419 3420 #define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY BIT(3) 3421 #define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY_SET(x)\ 3422 FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY, x) 3423 #define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY_GET(x)\ 3424 FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY, x) 3425 3426 #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE BIT(0) 3427 #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE_SET(x)\ 3428 FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x) 3429 #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE_GET(x)\ 3430 FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x) 3431 3432 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_LINK_STATUS */ 3433 #define DEV2G5_PCS1G_LINK_STATUS(t) \ 3434 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 40, 0, 1,\ 3435 4) 3436 3437 #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR GENMASK(15, 12) 3438 #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR_SET(x)\ 3439 FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR, x) 3440 #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR_GET(x)\ 3441 FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR, x) 3442 3443 #define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT BIT(8) 3444 #define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT_SET(x)\ 3445 FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT, x) 3446 #define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT_GET(x)\ 3447 FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT, x) 3448 3449 #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS BIT(4) 3450 #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS_SET(x)\ 3451 FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS, x) 3452 #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS_GET(x)\ 3453 FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS, x) 3454 3455 #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS BIT(0) 3456 #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS_SET(x)\ 3457 FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS, x) 3458 #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS_GET(x)\ 3459 FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS, x) 3460 3461 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_STICKY */ 3462 #define DEV2G5_PCS1G_STICKY(t) \ 3463 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 48, 0, 1,\ 3464 4) 3465 3466 #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY BIT(4) 3467 #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY_SET(x)\ 3468 FIELD_PREP(DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY, x) 3469 #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY_GET(x)\ 3470 FIELD_GET(DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY, x) 3471 3472 #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY BIT(0) 3473 #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY_SET(x)\ 3474 FIELD_PREP(DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY, x) 3475 #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY_GET(x)\ 3476 FIELD_GET(DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY, x) 3477 3478 /* DEV1G:PCS_FX100_CONFIGURATION:PCS_FX100_CFG */ 3479 #define DEV2G5_PCS_FX100_CFG(t) \ 3480 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 164, 0, 1, 4, 0, 0, 1, \ 3481 4) 3482 3483 #define DEV2G5_PCS_FX100_CFG_SD_SEL BIT(26) 3484 #define DEV2G5_PCS_FX100_CFG_SD_SEL_SET(x)\ 3485 FIELD_PREP(DEV2G5_PCS_FX100_CFG_SD_SEL, x) 3486 #define DEV2G5_PCS_FX100_CFG_SD_SEL_GET(x)\ 3487 FIELD_GET(DEV2G5_PCS_FX100_CFG_SD_SEL, x) 3488 3489 #define DEV2G5_PCS_FX100_CFG_SD_POL BIT(25) 3490 #define DEV2G5_PCS_FX100_CFG_SD_POL_SET(x)\ 3491 FIELD_PREP(DEV2G5_PCS_FX100_CFG_SD_POL, x) 3492 #define DEV2G5_PCS_FX100_CFG_SD_POL_GET(x)\ 3493 FIELD_GET(DEV2G5_PCS_FX100_CFG_SD_POL, x) 3494 3495 #define DEV2G5_PCS_FX100_CFG_SD_ENA BIT(24) 3496 #define DEV2G5_PCS_FX100_CFG_SD_ENA_SET(x)\ 3497 FIELD_PREP(DEV2G5_PCS_FX100_CFG_SD_ENA, x) 3498 #define DEV2G5_PCS_FX100_CFG_SD_ENA_GET(x)\ 3499 FIELD_GET(DEV2G5_PCS_FX100_CFG_SD_ENA, x) 3500 3501 #define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA BIT(20) 3502 #define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA_SET(x)\ 3503 FIELD_PREP(DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA, x) 3504 #define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA_GET(x)\ 3505 FIELD_GET(DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA, x) 3506 3507 #define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA BIT(16) 3508 #define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA_SET(x)\ 3509 FIELD_PREP(DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA, x) 3510 #define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA_GET(x)\ 3511 FIELD_GET(DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA, x) 3512 3513 #define DEV2G5_PCS_FX100_CFG_RXBITSEL GENMASK(15, 12) 3514 #define DEV2G5_PCS_FX100_CFG_RXBITSEL_SET(x)\ 3515 FIELD_PREP(DEV2G5_PCS_FX100_CFG_RXBITSEL, x) 3516 #define DEV2G5_PCS_FX100_CFG_RXBITSEL_GET(x)\ 3517 FIELD_GET(DEV2G5_PCS_FX100_CFG_RXBITSEL, x) 3518 3519 #define DEV2G5_PCS_FX100_CFG_SIGDET_CFG GENMASK(10, 9) 3520 #define DEV2G5_PCS_FX100_CFG_SIGDET_CFG_SET(x)\ 3521 FIELD_PREP(DEV2G5_PCS_FX100_CFG_SIGDET_CFG, x) 3522 #define DEV2G5_PCS_FX100_CFG_SIGDET_CFG_GET(x)\ 3523 FIELD_GET(DEV2G5_PCS_FX100_CFG_SIGDET_CFG, x) 3524 3525 #define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA BIT(8) 3526 #define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA_SET(x)\ 3527 FIELD_PREP(DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA, x) 3528 #define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA_GET(x)\ 3529 FIELD_GET(DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA, x) 3530 3531 #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER GENMASK(7, 4) 3532 #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER_SET(x)\ 3533 FIELD_PREP(DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER, x) 3534 #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER_GET(x)\ 3535 FIELD_GET(DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER, x) 3536 3537 #define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA BIT(3) 3538 #define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA_SET(x)\ 3539 FIELD_PREP(DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA, x) 3540 #define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA_GET(x)\ 3541 FIELD_GET(DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA, x) 3542 3543 #define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA BIT(2) 3544 #define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA_SET(x)\ 3545 FIELD_PREP(DEV2G5_PCS_FX100_CFG_FEFCHK_ENA, x) 3546 #define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA_GET(x)\ 3547 FIELD_GET(DEV2G5_PCS_FX100_CFG_FEFCHK_ENA, x) 3548 3549 #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA BIT(1) 3550 #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA_SET(x)\ 3551 FIELD_PREP(DEV2G5_PCS_FX100_CFG_FEFGEN_ENA, x) 3552 #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA_GET(x)\ 3553 FIELD_GET(DEV2G5_PCS_FX100_CFG_FEFGEN_ENA, x) 3554 3555 #define DEV2G5_PCS_FX100_CFG_PCS_ENA BIT(0) 3556 #define DEV2G5_PCS_FX100_CFG_PCS_ENA_SET(x)\ 3557 FIELD_PREP(DEV2G5_PCS_FX100_CFG_PCS_ENA, x) 3558 #define DEV2G5_PCS_FX100_CFG_PCS_ENA_GET(x)\ 3559 FIELD_GET(DEV2G5_PCS_FX100_CFG_PCS_ENA, x) 3560 3561 /* DEV1G:PCS_FX100_STATUS:PCS_FX100_STATUS */ 3562 #define DEV2G5_PCS_FX100_STATUS(t) \ 3563 __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 168, 0, 1, 4, 0, 0, 1, \ 3564 4) 3565 3566 #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP GENMASK(11, 8) 3567 #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP_SET(x)\ 3568 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP, x) 3569 #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP_GET(x)\ 3570 FIELD_GET(DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP, x) 3571 3572 #define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY BIT(7) 3573 #define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY_SET(x)\ 3574 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY, x) 3575 #define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY_GET(x)\ 3576 FIELD_GET(DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY, x) 3577 3578 #define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY BIT(6) 3579 #define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY_SET(x)\ 3580 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY, x) 3581 #define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY_GET(x)\ 3582 FIELD_GET(DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY, x) 3583 3584 #define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY BIT(5) 3585 #define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY_SET(x)\ 3586 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY, x) 3587 #define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY_GET(x)\ 3588 FIELD_GET(DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY, x) 3589 3590 #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY BIT(4) 3591 #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY_SET(x)\ 3592 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY, x) 3593 #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY_GET(x)\ 3594 FIELD_GET(DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY, x) 3595 3596 #define DEV2G5_PCS_FX100_STATUS_FEF_STATUS BIT(2) 3597 #define DEV2G5_PCS_FX100_STATUS_FEF_STATUS_SET(x)\ 3598 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_FEF_STATUS, x) 3599 #define DEV2G5_PCS_FX100_STATUS_FEF_STATUS_GET(x)\ 3600 FIELD_GET(DEV2G5_PCS_FX100_STATUS_FEF_STATUS, x) 3601 3602 #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT BIT(1) 3603 #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT_SET(x)\ 3604 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT, x) 3605 #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT_GET(x)\ 3606 FIELD_GET(DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT, x) 3607 3608 #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS BIT(0) 3609 #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS_SET(x)\ 3610 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SYNC_STATUS, x) 3611 #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS_GET(x)\ 3612 FIELD_GET(DEV2G5_PCS_FX100_STATUS_SYNC_STATUS, x) 3613 3614 /* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */ 3615 #define DEV5G_MAC_ENA_CFG(t) \ 3616 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 0, 0, 1, 60, 0, 0, 1, 4) 3617 3618 #define DEV5G_MAC_ENA_CFG_RX_ENA BIT(4) 3619 #define DEV5G_MAC_ENA_CFG_RX_ENA_SET(x)\ 3620 FIELD_PREP(DEV5G_MAC_ENA_CFG_RX_ENA, x) 3621 #define DEV5G_MAC_ENA_CFG_RX_ENA_GET(x)\ 3622 FIELD_GET(DEV5G_MAC_ENA_CFG_RX_ENA, x) 3623 3624 #define DEV5G_MAC_ENA_CFG_TX_ENA BIT(0) 3625 #define DEV5G_MAC_ENA_CFG_TX_ENA_SET(x)\ 3626 FIELD_PREP(DEV5G_MAC_ENA_CFG_TX_ENA, x) 3627 #define DEV5G_MAC_ENA_CFG_TX_ENA_GET(x)\ 3628 FIELD_GET(DEV5G_MAC_ENA_CFG_TX_ENA, x) 3629 3630 /* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ 3631 #define DEV5G_MAC_MAXLEN_CFG(t) \ 3632 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 0, 0, 1, 60, 8, 0, 1, 4) 3633 3634 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK BIT(16) 3635 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\ 3636 FIELD_PREP(DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x) 3637 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\ 3638 FIELD_GET(DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x) 3639 3640 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0) 3641 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\ 3642 FIELD_PREP(DEV5G_MAC_MAXLEN_CFG_MAX_LEN, x) 3643 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ 3644 FIELD_GET(DEV5G_MAC_MAXLEN_CFG_MAX_LEN, x) 3645 3646 /* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ 3647 #define DEV5G_MAC_ADV_CHK_CFG(t) \ 3648 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 0, 0, 1, 60, 28, 0, 1, \ 3649 4) 3650 3651 #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA BIT(24) 3652 #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\ 3653 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x) 3654 #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\ 3655 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x) 3656 3657 #define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA BIT(20) 3658 #define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\ 3659 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x) 3660 #define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\ 3661 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x) 3662 3663 #define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA BIT(16) 3664 #define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\ 3665 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x) 3666 #define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\ 3667 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x) 3668 3669 #define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS BIT(12) 3670 #define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\ 3671 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x) 3672 #define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\ 3673 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x) 3674 3675 #define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA BIT(8) 3676 #define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\ 3677 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x) 3678 #define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\ 3679 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x) 3680 3681 #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA BIT(4) 3682 #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\ 3683 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x) 3684 #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\ 3685 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x) 3686 3687 #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA BIT(0) 3688 #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\ 3689 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x) 3690 #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\ 3691 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x) 3692 3693 /* DEV10G:DEV_STATISTICS_32BIT:RX_SYMBOL_ERR_CNT */ 3694 #define DEV5G_RX_SYMBOL_ERR_CNT(t) \ 3695 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 0, 0, 1, \ 3696 4) 3697 3698 /* DEV10G:DEV_STATISTICS_32BIT:RX_PAUSE_CNT */ 3699 #define DEV5G_RX_PAUSE_CNT(t) \ 3700 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 4, 0, 1, \ 3701 4) 3702 3703 /* DEV10G:DEV_STATISTICS_32BIT:RX_UNSUP_OPCODE_CNT */ 3704 #define DEV5G_RX_UNSUP_OPCODE_CNT(t) \ 3705 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 8, 0, 1, \ 3706 4) 3707 3708 /* DEV10G:DEV_STATISTICS_32BIT:RX_UC_CNT */ 3709 #define DEV5G_RX_UC_CNT(t) \ 3710 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 12, 0, 1, \ 3711 4) 3712 3713 /* DEV10G:DEV_STATISTICS_32BIT:RX_MC_CNT */ 3714 #define DEV5G_RX_MC_CNT(t) \ 3715 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 16, 0, 1, \ 3716 4) 3717 3718 /* DEV10G:DEV_STATISTICS_32BIT:RX_BC_CNT */ 3719 #define DEV5G_RX_BC_CNT(t) \ 3720 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 20, 0, 1, \ 3721 4) 3722 3723 /* DEV10G:DEV_STATISTICS_32BIT:RX_CRC_ERR_CNT */ 3724 #define DEV5G_RX_CRC_ERR_CNT(t) \ 3725 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 24, 0, 1, \ 3726 4) 3727 3728 /* DEV10G:DEV_STATISTICS_32BIT:RX_UNDERSIZE_CNT */ 3729 #define DEV5G_RX_UNDERSIZE_CNT(t) \ 3730 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 28, 0, 1, \ 3731 4) 3732 3733 /* DEV10G:DEV_STATISTICS_32BIT:RX_FRAGMENTS_CNT */ 3734 #define DEV5G_RX_FRAGMENTS_CNT(t) \ 3735 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 32, 0, 1, \ 3736 4) 3737 3738 /* DEV10G:DEV_STATISTICS_32BIT:RX_IN_RANGE_LEN_ERR_CNT */ 3739 #define DEV5G_RX_IN_RANGE_LEN_ERR_CNT(t) \ 3740 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 36, 0, 1, \ 3741 4) 3742 3743 /* DEV10G:DEV_STATISTICS_32BIT:RX_OUT_OF_RANGE_LEN_ERR_CNT */ 3744 #define DEV5G_RX_OUT_OF_RANGE_LEN_ERR_CNT(t) \ 3745 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 40, 0, 1, \ 3746 4) 3747 3748 /* DEV10G:DEV_STATISTICS_32BIT:RX_OVERSIZE_CNT */ 3749 #define DEV5G_RX_OVERSIZE_CNT(t) \ 3750 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 44, 0, 1, \ 3751 4) 3752 3753 /* DEV10G:DEV_STATISTICS_32BIT:RX_JABBERS_CNT */ 3754 #define DEV5G_RX_JABBERS_CNT(t) \ 3755 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 48, 0, 1, \ 3756 4) 3757 3758 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE64_CNT */ 3759 #define DEV5G_RX_SIZE64_CNT(t) \ 3760 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 52, 0, 1, \ 3761 4) 3762 3763 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE65TO127_CNT */ 3764 #define DEV5G_RX_SIZE65TO127_CNT(t) \ 3765 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 56, 0, 1, \ 3766 4) 3767 3768 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE128TO255_CNT */ 3769 #define DEV5G_RX_SIZE128TO255_CNT(t) \ 3770 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 60, 0, 1, \ 3771 4) 3772 3773 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE256TO511_CNT */ 3774 #define DEV5G_RX_SIZE256TO511_CNT(t) \ 3775 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 64, 0, 1, \ 3776 4) 3777 3778 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE512TO1023_CNT */ 3779 #define DEV5G_RX_SIZE512TO1023_CNT(t) \ 3780 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 68, 0, 1, \ 3781 4) 3782 3783 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE1024TO1518_CNT */ 3784 #define DEV5G_RX_SIZE1024TO1518_CNT(t) \ 3785 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 72, 0, 1, \ 3786 4) 3787 3788 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE1519TOMAX_CNT */ 3789 #define DEV5G_RX_SIZE1519TOMAX_CNT(t) \ 3790 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 76, 0, 1, \ 3791 4) 3792 3793 /* DEV10G:DEV_STATISTICS_32BIT:RX_IPG_SHRINK_CNT */ 3794 #define DEV5G_RX_IPG_SHRINK_CNT(t) \ 3795 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 80, 0, 1, \ 3796 4) 3797 3798 /* DEV10G:DEV_STATISTICS_32BIT:TX_PAUSE_CNT */ 3799 #define DEV5G_TX_PAUSE_CNT(t) \ 3800 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 84, 0, 1, \ 3801 4) 3802 3803 /* DEV10G:DEV_STATISTICS_32BIT:TX_UC_CNT */ 3804 #define DEV5G_TX_UC_CNT(t) \ 3805 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 88, 0, 1, \ 3806 4) 3807 3808 /* DEV10G:DEV_STATISTICS_32BIT:TX_MC_CNT */ 3809 #define DEV5G_TX_MC_CNT(t) \ 3810 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 92, 0, 1, \ 3811 4) 3812 3813 /* DEV10G:DEV_STATISTICS_32BIT:TX_BC_CNT */ 3814 #define DEV5G_TX_BC_CNT(t) \ 3815 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 96, 0, 1, \ 3816 4) 3817 3818 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE64_CNT */ 3819 #define DEV5G_TX_SIZE64_CNT(t) \ 3820 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 100, 0, 1,\ 3821 4) 3822 3823 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE65TO127_CNT */ 3824 #define DEV5G_TX_SIZE65TO127_CNT(t) \ 3825 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 104, 0, 1,\ 3826 4) 3827 3828 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE128TO255_CNT */ 3829 #define DEV5G_TX_SIZE128TO255_CNT(t) \ 3830 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 108, 0, 1,\ 3831 4) 3832 3833 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE256TO511_CNT */ 3834 #define DEV5G_TX_SIZE256TO511_CNT(t) \ 3835 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 112, 0, 1,\ 3836 4) 3837 3838 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE512TO1023_CNT */ 3839 #define DEV5G_TX_SIZE512TO1023_CNT(t) \ 3840 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 116, 0, 1,\ 3841 4) 3842 3843 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE1024TO1518_CNT */ 3844 #define DEV5G_TX_SIZE1024TO1518_CNT(t) \ 3845 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 120, 0, 1,\ 3846 4) 3847 3848 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE1519TOMAX_CNT */ 3849 #define DEV5G_TX_SIZE1519TOMAX_CNT(t) \ 3850 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 124, 0, 1,\ 3851 4) 3852 3853 /* DEV10G:DEV_STATISTICS_32BIT:RX_ALIGNMENT_LOST_CNT */ 3854 #define DEV5G_RX_ALIGNMENT_LOST_CNT(t) \ 3855 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 128, 0, 1,\ 3856 4) 3857 3858 /* DEV10G:DEV_STATISTICS_32BIT:RX_TAGGED_FRMS_CNT */ 3859 #define DEV5G_RX_TAGGED_FRMS_CNT(t) \ 3860 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 132, 0, 1,\ 3861 4) 3862 3863 /* DEV10G:DEV_STATISTICS_32BIT:RX_UNTAGGED_FRMS_CNT */ 3864 #define DEV5G_RX_UNTAGGED_FRMS_CNT(t) \ 3865 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 136, 0, 1,\ 3866 4) 3867 3868 /* DEV10G:DEV_STATISTICS_32BIT:TX_TAGGED_FRMS_CNT */ 3869 #define DEV5G_TX_TAGGED_FRMS_CNT(t) \ 3870 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 140, 0, 1,\ 3871 4) 3872 3873 /* DEV10G:DEV_STATISTICS_32BIT:TX_UNTAGGED_FRMS_CNT */ 3874 #define DEV5G_TX_UNTAGGED_FRMS_CNT(t) \ 3875 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 144, 0, 1,\ 3876 4) 3877 3878 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SYMBOL_ERR_CNT */ 3879 #define DEV5G_PMAC_RX_SYMBOL_ERR_CNT(t) \ 3880 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 148, 0, 1,\ 3881 4) 3882 3883 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_PAUSE_CNT */ 3884 #define DEV5G_PMAC_RX_PAUSE_CNT(t) \ 3885 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 152, 0, 1,\ 3886 4) 3887 3888 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UNSUP_OPCODE_CNT */ 3889 #define DEV5G_PMAC_RX_UNSUP_OPCODE_CNT(t) \ 3890 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 156, 0, 1,\ 3891 4) 3892 3893 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UC_CNT */ 3894 #define DEV5G_PMAC_RX_UC_CNT(t) \ 3895 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 160, 0, 1,\ 3896 4) 3897 3898 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_MC_CNT */ 3899 #define DEV5G_PMAC_RX_MC_CNT(t) \ 3900 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 164, 0, 1,\ 3901 4) 3902 3903 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_BC_CNT */ 3904 #define DEV5G_PMAC_RX_BC_CNT(t) \ 3905 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 168, 0, 1,\ 3906 4) 3907 3908 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_CRC_ERR_CNT */ 3909 #define DEV5G_PMAC_RX_CRC_ERR_CNT(t) \ 3910 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 172, 0, 1,\ 3911 4) 3912 3913 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UNDERSIZE_CNT */ 3914 #define DEV5G_PMAC_RX_UNDERSIZE_CNT(t) \ 3915 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 176, 0, 1,\ 3916 4) 3917 3918 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_FRAGMENTS_CNT */ 3919 #define DEV5G_PMAC_RX_FRAGMENTS_CNT(t) \ 3920 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 180, 0, 1,\ 3921 4) 3922 3923 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_IN_RANGE_LEN_ERR_CNT */ 3924 #define DEV5G_PMAC_RX_IN_RANGE_LEN_ERR_CNT(t) \ 3925 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 184, 0, 1,\ 3926 4) 3927 3928 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT */ 3929 #define DEV5G_PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT(t) \ 3930 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 188, 0, 1,\ 3931 4) 3932 3933 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_OVERSIZE_CNT */ 3934 #define DEV5G_PMAC_RX_OVERSIZE_CNT(t) \ 3935 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 192, 0, 1,\ 3936 4) 3937 3938 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_JABBERS_CNT */ 3939 #define DEV5G_PMAC_RX_JABBERS_CNT(t) \ 3940 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 196, 0, 1,\ 3941 4) 3942 3943 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE64_CNT */ 3944 #define DEV5G_PMAC_RX_SIZE64_CNT(t) \ 3945 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 200, 0, 1,\ 3946 4) 3947 3948 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE65TO127_CNT */ 3949 #define DEV5G_PMAC_RX_SIZE65TO127_CNT(t) \ 3950 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 204, 0, 1,\ 3951 4) 3952 3953 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE128TO255_CNT */ 3954 #define DEV5G_PMAC_RX_SIZE128TO255_CNT(t) \ 3955 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 208, 0, 1,\ 3956 4) 3957 3958 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE256TO511_CNT */ 3959 #define DEV5G_PMAC_RX_SIZE256TO511_CNT(t) \ 3960 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 212, 0, 1,\ 3961 4) 3962 3963 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE512TO1023_CNT */ 3964 #define DEV5G_PMAC_RX_SIZE512TO1023_CNT(t) \ 3965 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 216, 0, 1,\ 3966 4) 3967 3968 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE1024TO1518_CNT */ 3969 #define DEV5G_PMAC_RX_SIZE1024TO1518_CNT(t) \ 3970 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 220, 0, 1,\ 3971 4) 3972 3973 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE1519TOMAX_CNT */ 3974 #define DEV5G_PMAC_RX_SIZE1519TOMAX_CNT(t) \ 3975 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 224, 0, 1,\ 3976 4) 3977 3978 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_PAUSE_CNT */ 3979 #define DEV5G_PMAC_TX_PAUSE_CNT(t) \ 3980 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 228, 0, 1,\ 3981 4) 3982 3983 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_UC_CNT */ 3984 #define DEV5G_PMAC_TX_UC_CNT(t) \ 3985 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 232, 0, 1,\ 3986 4) 3987 3988 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_MC_CNT */ 3989 #define DEV5G_PMAC_TX_MC_CNT(t) \ 3990 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 236, 0, 1,\ 3991 4) 3992 3993 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_BC_CNT */ 3994 #define DEV5G_PMAC_TX_BC_CNT(t) \ 3995 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 240, 0, 1,\ 3996 4) 3997 3998 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE64_CNT */ 3999 #define DEV5G_PMAC_TX_SIZE64_CNT(t) \ 4000 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 244, 0, 1,\ 4001 4) 4002 4003 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE65TO127_CNT */ 4004 #define DEV5G_PMAC_TX_SIZE65TO127_CNT(t) \ 4005 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 248, 0, 1,\ 4006 4) 4007 4008 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE128TO255_CNT */ 4009 #define DEV5G_PMAC_TX_SIZE128TO255_CNT(t) \ 4010 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 252, 0, 1,\ 4011 4) 4012 4013 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE256TO511_CNT */ 4014 #define DEV5G_PMAC_TX_SIZE256TO511_CNT(t) \ 4015 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 256, 0, 1,\ 4016 4) 4017 4018 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE512TO1023_CNT */ 4019 #define DEV5G_PMAC_TX_SIZE512TO1023_CNT(t) \ 4020 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 260, 0, 1,\ 4021 4) 4022 4023 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE1024TO1518_CNT */ 4024 #define DEV5G_PMAC_TX_SIZE1024TO1518_CNT(t) \ 4025 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 264, 0, 1,\ 4026 4) 4027 4028 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE1519TOMAX_CNT */ 4029 #define DEV5G_PMAC_TX_SIZE1519TOMAX_CNT(t) \ 4030 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 268, 0, 1,\ 4031 4) 4032 4033 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_ALIGNMENT_LOST_CNT */ 4034 #define DEV5G_PMAC_RX_ALIGNMENT_LOST_CNT(t) \ 4035 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 272, 0, 1,\ 4036 4) 4037 4038 /* DEV10G:DEV_STATISTICS_32BIT:MM_RX_ASSEMBLY_ERR_CNT */ 4039 #define DEV5G_MM_RX_ASSEMBLY_ERR_CNT(t) \ 4040 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 276, 0, 1,\ 4041 4) 4042 4043 /* DEV10G:DEV_STATISTICS_32BIT:MM_RX_SMD_ERR_CNT */ 4044 #define DEV5G_MM_RX_SMD_ERR_CNT(t) \ 4045 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 280, 0, 1,\ 4046 4) 4047 4048 /* DEV10G:DEV_STATISTICS_32BIT:MM_RX_ASSEMBLY_OK_CNT */ 4049 #define DEV5G_MM_RX_ASSEMBLY_OK_CNT(t) \ 4050 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 284, 0, 1,\ 4051 4) 4052 4053 /* DEV10G:DEV_STATISTICS_32BIT:MM_RX_MERGE_FRAG_CNT */ 4054 #define DEV5G_MM_RX_MERGE_FRAG_CNT(t) \ 4055 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 288, 0, 1,\ 4056 4) 4057 4058 /* DEV10G:DEV_STATISTICS_32BIT:MM_TX_PFRAGMENT_CNT */ 4059 #define DEV5G_MM_TX_PFRAGMENT_CNT(t) \ 4060 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 292, 0, 1,\ 4061 4) 4062 4063 /* DEV10G:DEV_STATISTICS_32BIT:RX_HIH_CKSM_ERR_CNT */ 4064 #define DEV5G_RX_HIH_CKSM_ERR_CNT(t) \ 4065 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 296, 0, 1,\ 4066 4) 4067 4068 /* DEV10G:DEV_STATISTICS_32BIT:RX_XGMII_PROT_ERR_CNT */ 4069 #define DEV5G_RX_XGMII_PROT_ERR_CNT(t) \ 4070 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 300, 0, 1,\ 4071 4) 4072 4073 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_HIH_CKSM_ERR_CNT */ 4074 #define DEV5G_PMAC_RX_HIH_CKSM_ERR_CNT(t) \ 4075 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 304, 0, 1,\ 4076 4) 4077 4078 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_XGMII_PROT_ERR_CNT */ 4079 #define DEV5G_PMAC_RX_XGMII_PROT_ERR_CNT(t) \ 4080 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 308, 0, 1,\ 4081 4) 4082 4083 /* DEV10G:DEV_STATISTICS_40BIT:RX_IN_BYTES_CNT */ 4084 #define DEV5G_RX_IN_BYTES_CNT(t) \ 4085 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 0, 0, 1, \ 4086 4) 4087 4088 /* DEV10G:DEV_STATISTICS_40BIT:RX_IN_BYTES_MSB_CNT */ 4089 #define DEV5G_RX_IN_BYTES_MSB_CNT(t) \ 4090 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 4, 0, 1, \ 4091 4) 4092 4093 #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT GENMASK(7, 0) 4094 #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_SET(x)\ 4095 FIELD_PREP(DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x) 4096 #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_GET(x)\ 4097 FIELD_GET(DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x) 4098 4099 /* DEV10G:DEV_STATISTICS_40BIT:RX_OK_BYTES_CNT */ 4100 #define DEV5G_RX_OK_BYTES_CNT(t) \ 4101 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 8, 0, 1, \ 4102 4) 4103 4104 /* DEV10G:DEV_STATISTICS_40BIT:RX_OK_BYTES_MSB_CNT */ 4105 #define DEV5G_RX_OK_BYTES_MSB_CNT(t) \ 4106 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 12, 0, 1, \ 4107 4) 4108 4109 #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT GENMASK(7, 0) 4110 #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_SET(x)\ 4111 FIELD_PREP(DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x) 4112 #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_GET(x)\ 4113 FIELD_GET(DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x) 4114 4115 /* DEV10G:DEV_STATISTICS_40BIT:RX_BAD_BYTES_CNT */ 4116 #define DEV5G_RX_BAD_BYTES_CNT(t) \ 4117 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 16, 0, 1, \ 4118 4) 4119 4120 /* DEV10G:DEV_STATISTICS_40BIT:RX_BAD_BYTES_MSB_CNT */ 4121 #define DEV5G_RX_BAD_BYTES_MSB_CNT(t) \ 4122 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 20, 0, 1, \ 4123 4) 4124 4125 #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT GENMASK(7, 0) 4126 #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_SET(x)\ 4127 FIELD_PREP(DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x) 4128 #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_GET(x)\ 4129 FIELD_GET(DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x) 4130 4131 /* DEV10G:DEV_STATISTICS_40BIT:TX_OUT_BYTES_CNT */ 4132 #define DEV5G_TX_OUT_BYTES_CNT(t) \ 4133 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 24, 0, 1, \ 4134 4) 4135 4136 /* DEV10G:DEV_STATISTICS_40BIT:TX_OUT_BYTES_MSB_CNT */ 4137 #define DEV5G_TX_OUT_BYTES_MSB_CNT(t) \ 4138 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 28, 0, 1, \ 4139 4) 4140 4141 #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT GENMASK(7, 0) 4142 #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_SET(x)\ 4143 FIELD_PREP(DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x) 4144 #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_GET(x)\ 4145 FIELD_GET(DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x) 4146 4147 /* DEV10G:DEV_STATISTICS_40BIT:TX_OK_BYTES_CNT */ 4148 #define DEV5G_TX_OK_BYTES_CNT(t) \ 4149 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 32, 0, 1, \ 4150 4) 4151 4152 /* DEV10G:DEV_STATISTICS_40BIT:TX_OK_BYTES_MSB_CNT */ 4153 #define DEV5G_TX_OK_BYTES_MSB_CNT(t) \ 4154 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 36, 0, 1, \ 4155 4) 4156 4157 #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT GENMASK(7, 0) 4158 #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_SET(x)\ 4159 FIELD_PREP(DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x) 4160 #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_GET(x)\ 4161 FIELD_GET(DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x) 4162 4163 /* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_OK_BYTES_CNT */ 4164 #define DEV5G_PMAC_RX_OK_BYTES_CNT(t) \ 4165 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 40, 0, 1, \ 4166 4) 4167 4168 /* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_OK_BYTES_MSB_CNT */ 4169 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT(t) \ 4170 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 44, 0, 1, \ 4171 4) 4172 4173 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT GENMASK(7, 0) 4174 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_SET(x)\ 4175 FIELD_PREP(DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x) 4176 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_GET(x)\ 4177 FIELD_GET(DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x) 4178 4179 /* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_BAD_BYTES_CNT */ 4180 #define DEV5G_PMAC_RX_BAD_BYTES_CNT(t) \ 4181 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 48, 0, 1, \ 4182 4) 4183 4184 /* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_BAD_BYTES_MSB_CNT */ 4185 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT(t) \ 4186 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 52, 0, 1, \ 4187 4) 4188 4189 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT GENMASK(7, 0) 4190 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_SET(x)\ 4191 FIELD_PREP(DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x) 4192 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_GET(x)\ 4193 FIELD_GET(DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x) 4194 4195 /* DEV10G:DEV_STATISTICS_40BIT:PMAC_TX_OK_BYTES_CNT */ 4196 #define DEV5G_PMAC_TX_OK_BYTES_CNT(t) \ 4197 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 56, 0, 1, \ 4198 4) 4199 4200 /* DEV10G:DEV_STATISTICS_40BIT:PMAC_TX_OK_BYTES_MSB_CNT */ 4201 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT(t) \ 4202 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 60, 0, 1, \ 4203 4) 4204 4205 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT GENMASK(7, 0) 4206 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_SET(x)\ 4207 FIELD_PREP(DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x) 4208 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_GET(x)\ 4209 FIELD_GET(DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x) 4210 4211 /* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */ 4212 #define DEV5G_DEV_RST_CTRL(t) \ 4213 __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 436, 0, 1, 52, 0, 0, 1, \ 4214 4) 4215 4216 #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA BIT(28) 4217 #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\ 4218 FIELD_PREP(DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA, x) 4219 #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\ 4220 FIELD_GET(DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA, x) 4221 4222 #define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS BIT(27) 4223 #define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\ 4224 FIELD_PREP(DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) 4225 #define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\ 4226 FIELD_GET(DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x) 4227 4228 #define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS GENMASK(26, 25) 4229 #define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\ 4230 FIELD_PREP(DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x) 4231 #define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\ 4232 FIELD_GET(DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x) 4233 4234 #define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL GENMASK(24, 23) 4235 #define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\ 4236 FIELD_PREP(DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL, x) 4237 #define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\ 4238 FIELD_GET(DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL, x) 4239 4240 #define DEV5G_DEV_RST_CTRL_SPEED_SEL GENMASK(22, 20) 4241 #define DEV5G_DEV_RST_CTRL_SPEED_SEL_SET(x)\ 4242 FIELD_PREP(DEV5G_DEV_RST_CTRL_SPEED_SEL, x) 4243 #define DEV5G_DEV_RST_CTRL_SPEED_SEL_GET(x)\ 4244 FIELD_GET(DEV5G_DEV_RST_CTRL_SPEED_SEL, x) 4245 4246 #define DEV5G_DEV_RST_CTRL_PCS_TX_RST BIT(12) 4247 #define DEV5G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\ 4248 FIELD_PREP(DEV5G_DEV_RST_CTRL_PCS_TX_RST, x) 4249 #define DEV5G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\ 4250 FIELD_GET(DEV5G_DEV_RST_CTRL_PCS_TX_RST, x) 4251 4252 #define DEV5G_DEV_RST_CTRL_PCS_RX_RST BIT(8) 4253 #define DEV5G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\ 4254 FIELD_PREP(DEV5G_DEV_RST_CTRL_PCS_RX_RST, x) 4255 #define DEV5G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\ 4256 FIELD_GET(DEV5G_DEV_RST_CTRL_PCS_RX_RST, x) 4257 4258 #define DEV5G_DEV_RST_CTRL_MAC_TX_RST BIT(4) 4259 #define DEV5G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\ 4260 FIELD_PREP(DEV5G_DEV_RST_CTRL_MAC_TX_RST, x) 4261 #define DEV5G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\ 4262 FIELD_GET(DEV5G_DEV_RST_CTRL_MAC_TX_RST, x) 4263 4264 #define DEV5G_DEV_RST_CTRL_MAC_RX_RST BIT(0) 4265 #define DEV5G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\ 4266 FIELD_PREP(DEV5G_DEV_RST_CTRL_MAC_RX_RST, x) 4267 #define DEV5G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ 4268 FIELD_GET(DEV5G_DEV_RST_CTRL_MAC_RX_RST, x) 4269 4270 /* DSM:RAM_CTRL:RAM_INIT */ 4271 #define DSM_RAM_INIT \ 4272 __REG(TARGET_DSM, 0, 1, 0, 0, 1, 4, 0, 0, 1, 4) 4273 4274 #define DSM_RAM_INIT_RAM_INIT BIT(1) 4275 #define DSM_RAM_INIT_RAM_INIT_SET(x)\ 4276 FIELD_PREP(DSM_RAM_INIT_RAM_INIT, x) 4277 #define DSM_RAM_INIT_RAM_INIT_GET(x)\ 4278 FIELD_GET(DSM_RAM_INIT_RAM_INIT, x) 4279 4280 #define DSM_RAM_INIT_RAM_CFG_HOOK BIT(0) 4281 #define DSM_RAM_INIT_RAM_CFG_HOOK_SET(x)\ 4282 FIELD_PREP(DSM_RAM_INIT_RAM_CFG_HOOK, x) 4283 #define DSM_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 4284 FIELD_GET(DSM_RAM_INIT_RAM_CFG_HOOK, x) 4285 4286 /* DSM:CFG:BUF_CFG */ 4287 #define DSM_BUF_CFG(r) \ 4288 __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 0, r, \ 4289 regs->rcnt[RC_DSM_BUF_CFG], 4) 4290 4291 #define DSM_BUF_CFG_CSC_STAT_DIS BIT(13) 4292 #define DSM_BUF_CFG_CSC_STAT_DIS_SET(x)\ 4293 FIELD_PREP(DSM_BUF_CFG_CSC_STAT_DIS, x) 4294 #define DSM_BUF_CFG_CSC_STAT_DIS_GET(x)\ 4295 FIELD_GET(DSM_BUF_CFG_CSC_STAT_DIS, x) 4296 4297 #define DSM_BUF_CFG_AGING_ENA BIT(12) 4298 #define DSM_BUF_CFG_AGING_ENA_SET(x)\ 4299 FIELD_PREP(DSM_BUF_CFG_AGING_ENA, x) 4300 #define DSM_BUF_CFG_AGING_ENA_GET(x)\ 4301 FIELD_GET(DSM_BUF_CFG_AGING_ENA, x) 4302 4303 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS BIT(11) 4304 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_SET(x)\ 4305 FIELD_PREP(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS, x) 4306 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_GET(x)\ 4307 FIELD_GET(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS, x) 4308 4309 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT GENMASK(10, 0) 4310 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT_SET(x)\ 4311 FIELD_PREP(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT, x) 4312 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT_GET(x)\ 4313 FIELD_GET(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT, x) 4314 4315 /* DSM:CFG:DEV_TX_STOP_WM_CFG */ 4316 #define DSM_DEV_TX_STOP_WM_CFG(r) \ 4317 __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 1360, r, \ 4318 regs->rcnt[RC_DSM_DEV_TX_STOP_WM_CFG], 4) 4319 4320 #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA BIT(9) 4321 #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA_SET(x)\ 4322 FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA, x) 4323 #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA_GET(x)\ 4324 FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA, x) 4325 4326 #define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA BIT(8) 4327 #define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_SET(x)\ 4328 FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA, x) 4329 #define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_GET(x)\ 4330 FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA, x) 4331 4332 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM GENMASK(7, 1) 4333 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_SET(x)\ 4334 FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM, x) 4335 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_GET(x)\ 4336 FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM, x) 4337 4338 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR BIT(0) 4339 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_SET(x)\ 4340 FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR, x) 4341 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_GET(x)\ 4342 FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR, x) 4343 4344 /* DSM:CFG:RX_PAUSE_CFG */ 4345 #define DSM_RX_PAUSE_CFG(r) \ 4346 __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 1628, r, \ 4347 regs->rcnt[RC_DSM_RX_PAUSE_CFG], 4) 4348 4349 #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN BIT(1) 4350 #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN_SET(x)\ 4351 FIELD_PREP(DSM_RX_PAUSE_CFG_RX_PAUSE_EN, x) 4352 #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN_GET(x)\ 4353 FIELD_GET(DSM_RX_PAUSE_CFG_RX_PAUSE_EN, x) 4354 4355 #define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL BIT(0) 4356 #define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL_SET(x)\ 4357 FIELD_PREP(DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL, x) 4358 #define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL_GET(x)\ 4359 FIELD_GET(DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL, x) 4360 4361 /* DSM:CFG:MAC_CFG */ 4362 #define DSM_MAC_CFG(r) \ 4363 __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 2432, r, \ 4364 regs->rcnt[RC_DSM_MAC_CFG], 4) 4365 4366 #define DSM_MAC_CFG_TX_PAUSE_VAL GENMASK(31, 16) 4367 #define DSM_MAC_CFG_TX_PAUSE_VAL_SET(x)\ 4368 FIELD_PREP(DSM_MAC_CFG_TX_PAUSE_VAL, x) 4369 #define DSM_MAC_CFG_TX_PAUSE_VAL_GET(x)\ 4370 FIELD_GET(DSM_MAC_CFG_TX_PAUSE_VAL, x) 4371 4372 #define DSM_MAC_CFG_HDX_BACKPREASSURE BIT(2) 4373 #define DSM_MAC_CFG_HDX_BACKPREASSURE_SET(x)\ 4374 FIELD_PREP(DSM_MAC_CFG_HDX_BACKPREASSURE, x) 4375 #define DSM_MAC_CFG_HDX_BACKPREASSURE_GET(x)\ 4376 FIELD_GET(DSM_MAC_CFG_HDX_BACKPREASSURE, x) 4377 4378 #define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE BIT(1) 4379 #define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE_SET(x)\ 4380 FIELD_PREP(DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE, x) 4381 #define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE_GET(x)\ 4382 FIELD_GET(DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE, x) 4383 4384 #define DSM_MAC_CFG_TX_PAUSE_XON_XOFF BIT(0) 4385 #define DSM_MAC_CFG_TX_PAUSE_XON_XOFF_SET(x)\ 4386 FIELD_PREP(DSM_MAC_CFG_TX_PAUSE_XON_XOFF, x) 4387 #define DSM_MAC_CFG_TX_PAUSE_XON_XOFF_GET(x)\ 4388 FIELD_GET(DSM_MAC_CFG_TX_PAUSE_XON_XOFF, x) 4389 4390 /* DSM:CFG:MAC_ADDR_BASE_HIGH_CFG */ 4391 #define DSM_MAC_ADDR_BASE_HIGH_CFG(r) \ 4392 __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 2700, r, \ 4393 regs->rcnt[RC_DSM_MAC_ADDR_BASE_HIGH_CFG], 4) 4394 4395 #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH GENMASK(23, 0) 4396 #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH_SET(x)\ 4397 FIELD_PREP(DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH, x) 4398 #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH_GET(x)\ 4399 FIELD_GET(DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH, x) 4400 4401 /* DSM:CFG:MAC_ADDR_BASE_LOW_CFG */ 4402 #define DSM_MAC_ADDR_BASE_LOW_CFG(r) \ 4403 __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 2960, r, \ 4404 regs->rcnt[RC_DSM_MAC_ADDR_BASE_LOW_CFG], 4) 4405 4406 #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW GENMASK(23, 0) 4407 #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW_SET(x)\ 4408 FIELD_PREP(DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW, x) 4409 #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW_GET(x)\ 4410 FIELD_GET(DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW, x) 4411 4412 /* DSM:CFG:TAXI_CAL_CFG */ 4413 #define DSM_TAXI_CAL_CFG(r) \ 4414 __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 3224, r, \ 4415 regs->rcnt[RC_DSM_TAXI_CAL_CFG], 4) 4416 4417 #define DSM_TAXI_CAL_CFG_CAL_IDX GENMASK(20, 15) 4418 #define DSM_TAXI_CAL_CFG_CAL_IDX_SET(x)\ 4419 FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_IDX, x) 4420 #define DSM_TAXI_CAL_CFG_CAL_IDX_GET(x)\ 4421 FIELD_GET(DSM_TAXI_CAL_CFG_CAL_IDX, x) 4422 4423 #define DSM_TAXI_CAL_CFG_CAL_CUR_LEN GENMASK(14, 9) 4424 #define DSM_TAXI_CAL_CFG_CAL_CUR_LEN_SET(x)\ 4425 FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_CUR_LEN, x) 4426 #define DSM_TAXI_CAL_CFG_CAL_CUR_LEN_GET(x)\ 4427 FIELD_GET(DSM_TAXI_CAL_CFG_CAL_CUR_LEN, x) 4428 4429 #define DSM_TAXI_CAL_CFG_CAL_CUR_VAL GENMASK(8, 5) 4430 #define DSM_TAXI_CAL_CFG_CAL_CUR_VAL_SET(x)\ 4431 FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_CUR_VAL, x) 4432 #define DSM_TAXI_CAL_CFG_CAL_CUR_VAL_GET(x)\ 4433 FIELD_GET(DSM_TAXI_CAL_CFG_CAL_CUR_VAL, x) 4434 4435 #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL GENMASK(4, 1) 4436 #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL_SET(x)\ 4437 FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_PGM_VAL, x) 4438 #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL_GET(x)\ 4439 FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_VAL, x) 4440 4441 #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA BIT(0) 4442 #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(x)\ 4443 FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_PGM_ENA, x) 4444 #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_GET(x)\ 4445 FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_ENA, x) 4446 4447 /* EACL:ES2_KEY_SELECT_PROFILE:VCAP_ES2_KEY_SEL */ 4448 #define EACL_VCAP_ES2_KEY_SEL(g, r) \ 4449 __REG(TARGET_EACL, 0, 1, regs->gaddr[GA_EACL_ES2_KEY_SELECT_PROFILE], \ 4450 g, regs->gcnt[GC_EACL_ES2_KEY_SELECT_PROFILE], 8, 0, r, 2, 4) 4451 4452 #define EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL GENMASK(7, 5) 4453 #define EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL_SET(x)\ 4454 FIELD_PREP(EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL, x) 4455 #define EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL_GET(x)\ 4456 FIELD_GET(EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL, x) 4457 4458 #define EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL GENMASK(4, 2) 4459 #define EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL_SET(x)\ 4460 FIELD_PREP(EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL, x) 4461 #define EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL_GET(x)\ 4462 FIELD_GET(EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL, x) 4463 4464 #define EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL BIT(1) 4465 #define EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL_SET(x)\ 4466 FIELD_PREP(EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL, x) 4467 #define EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL_GET(x)\ 4468 FIELD_GET(EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL, x) 4469 4470 #define EACL_VCAP_ES2_KEY_SEL_KEY_ENA BIT(0) 4471 #define EACL_VCAP_ES2_KEY_SEL_KEY_ENA_SET(x)\ 4472 FIELD_PREP(EACL_VCAP_ES2_KEY_SEL_KEY_ENA, x) 4473 #define EACL_VCAP_ES2_KEY_SEL_KEY_ENA_GET(x)\ 4474 FIELD_GET(EACL_VCAP_ES2_KEY_SEL_KEY_ENA, x) 4475 4476 /* EACL:CNT_TBL:ES2_CNT */ 4477 #define EACL_ES2_CNT(g) \ 4478 __REG(TARGET_EACL, 0, 1, regs->gaddr[GA_EACL_CNT_TBL], g, \ 4479 regs->gcnt[GC_EACL_CNT_TBL], 4, 0, 0, 1, 4) 4480 4481 /* EACL:POL_CFG:POL_EACL_CFG */ 4482 #define EACL_POL_EACL_CFG \ 4483 __REG(TARGET_EACL, 0, 1, regs->gaddr[GA_EACL_POL_CFG], 0, 1, 780, 768, \ 4484 0, 1, 4) 4485 4486 #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED BIT(5) 4487 #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED_SET(x)\ 4488 FIELD_PREP(EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED, x) 4489 #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED_GET(x)\ 4490 FIELD_GET(EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED, x) 4491 4492 #define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY BIT(4) 4493 #define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY_SET(x)\ 4494 FIELD_PREP(EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY, x) 4495 #define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY_GET(x)\ 4496 FIELD_GET(EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY, x) 4497 4498 #define EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY BIT(3) 4499 #define EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY_SET(x)\ 4500 FIELD_PREP(EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY, x) 4501 #define EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY_GET(x)\ 4502 FIELD_GET(EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY, x) 4503 4504 #define EACL_POL_EACL_CFG_EACL_FORCE_CLOSE BIT(2) 4505 #define EACL_POL_EACL_CFG_EACL_FORCE_CLOSE_SET(x)\ 4506 FIELD_PREP(EACL_POL_EACL_CFG_EACL_FORCE_CLOSE, x) 4507 #define EACL_POL_EACL_CFG_EACL_FORCE_CLOSE_GET(x)\ 4508 FIELD_GET(EACL_POL_EACL_CFG_EACL_FORCE_CLOSE, x) 4509 4510 #define EACL_POL_EACL_CFG_EACL_FORCE_OPEN BIT(1) 4511 #define EACL_POL_EACL_CFG_EACL_FORCE_OPEN_SET(x)\ 4512 FIELD_PREP(EACL_POL_EACL_CFG_EACL_FORCE_OPEN, x) 4513 #define EACL_POL_EACL_CFG_EACL_FORCE_OPEN_GET(x)\ 4514 FIELD_GET(EACL_POL_EACL_CFG_EACL_FORCE_OPEN, x) 4515 4516 #define EACL_POL_EACL_CFG_EACL_FORCE_INIT BIT(0) 4517 #define EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(x)\ 4518 FIELD_PREP(EACL_POL_EACL_CFG_EACL_FORCE_INIT, x) 4519 #define EACL_POL_EACL_CFG_EACL_FORCE_INIT_GET(x)\ 4520 FIELD_GET(EACL_POL_EACL_CFG_EACL_FORCE_INIT, x) 4521 4522 /* EACL:ES2_STICKY:SEC_LOOKUP_STICKY */ 4523 #define EACL_SEC_LOOKUP_STICKY(r) \ 4524 __REG(TARGET_EACL, 0, 1, regs->gaddr[GA_EACL_ES2_STICKY], 0, 1, 8, 0, \ 4525 r, 2, 4) 4526 4527 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY BIT(7) 4528 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_SET(x)\ 4529 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY, x) 4530 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_GET(x)\ 4531 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY, x) 4532 4533 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY BIT(6) 4534 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_SET(x)\ 4535 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY, x) 4536 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_GET(x)\ 4537 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY, x) 4538 4539 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY BIT(5) 4540 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_SET(x)\ 4541 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY, x) 4542 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_GET(x)\ 4543 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY, x) 4544 4545 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY BIT(4) 4546 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_SET(x)\ 4547 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY, x) 4548 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_GET(x)\ 4549 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY, x) 4550 4551 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY BIT(3) 4552 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_SET(x)\ 4553 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY, x) 4554 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_GET(x)\ 4555 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY, x) 4556 4557 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY BIT(2) 4558 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_SET(x)\ 4559 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY, x) 4560 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_GET(x)\ 4561 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY, x) 4562 4563 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY BIT(1) 4564 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_SET(x)\ 4565 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY, x) 4566 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_GET(x)\ 4567 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY, x) 4568 4569 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY BIT(0) 4570 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_SET(x)\ 4571 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY, x) 4572 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_GET(x)\ 4573 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY, x) 4574 4575 /* EACL:RAM_CTRL:RAM_INIT */ 4576 #define EACL_RAM_INIT \ 4577 __REG(TARGET_EACL, 0, 1, regs->gaddr[GA_EACL_RAM_CTRL], 0, 1, 4, 0, 0, \ 4578 1, 4) 4579 4580 #define EACL_RAM_INIT_RAM_INIT BIT(1) 4581 #define EACL_RAM_INIT_RAM_INIT_SET(x)\ 4582 FIELD_PREP(EACL_RAM_INIT_RAM_INIT, x) 4583 #define EACL_RAM_INIT_RAM_INIT_GET(x)\ 4584 FIELD_GET(EACL_RAM_INIT_RAM_INIT, x) 4585 4586 #define EACL_RAM_INIT_RAM_CFG_HOOK BIT(0) 4587 #define EACL_RAM_INIT_RAM_CFG_HOOK_SET(x)\ 4588 FIELD_PREP(EACL_RAM_INIT_RAM_CFG_HOOK, x) 4589 #define EACL_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 4590 FIELD_GET(EACL_RAM_INIT_RAM_CFG_HOOK, x) 4591 4592 /* FDMA:FDMA:FDMA_CH_ACTIVATE */ 4593 #define FDMA_CH_ACTIVATE \ 4594 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 0, 0, 1, \ 4595 4) 4596 4597 #define FDMA_CH_ACTIVATE_CH_ACTIVATE GENMASK(7, 0) 4598 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_SET(x)\ 4599 FIELD_PREP(FDMA_CH_ACTIVATE_CH_ACTIVATE, x) 4600 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_GET(x)\ 4601 FIELD_GET(FDMA_CH_ACTIVATE_CH_ACTIVATE, x) 4602 4603 /* FDMA:FDMA:FDMA_CH_RELOAD */ 4604 #define FDMA_CH_RELOAD \ 4605 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 4, 0, 1, \ 4606 4) 4607 4608 #define FDMA_CH_RELOAD_CH_RELOAD GENMASK(7, 0) 4609 #define FDMA_CH_RELOAD_CH_RELOAD_SET(x)\ 4610 FIELD_PREP(FDMA_CH_RELOAD_CH_RELOAD, x) 4611 #define FDMA_CH_RELOAD_CH_RELOAD_GET(x)\ 4612 FIELD_GET(FDMA_CH_RELOAD_CH_RELOAD, x) 4613 4614 /* FDMA:FDMA:FDMA_CH_DISABLE */ 4615 #define FDMA_CH_DISABLE \ 4616 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 8, 0, 1, \ 4617 4) 4618 4619 #define FDMA_CH_DISABLE_CH_DISABLE GENMASK(7, 0) 4620 #define FDMA_CH_DISABLE_CH_DISABLE_SET(x)\ 4621 FIELD_PREP(FDMA_CH_DISABLE_CH_DISABLE, x) 4622 #define FDMA_CH_DISABLE_CH_DISABLE_GET(x)\ 4623 FIELD_GET(FDMA_CH_DISABLE_CH_DISABLE, x) 4624 4625 /* FDMA:FDMA:FDMA_DCB_LLP */ 4626 #define FDMA_DCB_LLP(r) \ 4627 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 52, r, 8, \ 4628 4) 4629 4630 /* FDMA:FDMA:FDMA_DCB_LLP1 */ 4631 #define FDMA_DCB_LLP1(r) \ 4632 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 84, r, 8, \ 4633 4) 4634 4635 /* FDMA:FDMA:FDMA_DCB_LLP_PREV */ 4636 #define FDMA_DCB_LLP_PREV(r) \ 4637 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 116, r, 8,\ 4638 4) 4639 4640 /* FDMA:FDMA:FDMA_DCB_LLP_PREV1 */ 4641 #define FDMA_DCB_LLP_PREV1(r) \ 4642 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 148, r, 8,\ 4643 4) 4644 4645 /* FDMA:FDMA:FDMA_CH_CFG */ 4646 #define FDMA_CH_CFG(r) \ 4647 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 224, r, 8,\ 4648 4) 4649 4650 #define FDMA_CH_CFG_CH_XTR_STATUS_MODE\ 4651 BIT(regs->fpos[FP_FDMA_CH_CFG_CH_XTR_STATUS_MODE]) 4652 #define FDMA_CH_CFG_CH_XTR_STATUS_MODE_SET(x)\ 4653 spx5_field_prep(FDMA_CH_CFG_CH_XTR_STATUS_MODE, x) 4654 #define FDMA_CH_CFG_CH_XTR_STATUS_MODE_GET(x)\ 4655 spx5_field_get(FDMA_CH_CFG_CH_XTR_STATUS_MODE, x) 4656 4657 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY\ 4658 BIT(regs->fpos[FP_FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY]) 4659 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(x)\ 4660 spx5_field_prep(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x) 4661 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_GET(x)\ 4662 spx5_field_get(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x) 4663 4664 #define FDMA_CH_CFG_CH_INJ_PORT\ 4665 BIT(regs->fpos[FP_FDMA_CH_CFG_CH_INJ_PORT]) 4666 #define FDMA_CH_CFG_CH_INJ_PORT_SET(x)\ 4667 spx5_field_prep(FDMA_CH_CFG_CH_INJ_PORT, x) 4668 #define FDMA_CH_CFG_CH_INJ_PORT_GET(x)\ 4669 spx5_field_get(FDMA_CH_CFG_CH_INJ_PORT, x) 4670 4671 #define FDMA_CH_CFG_CH_DCB_DB_CNT\ 4672 GENMASK(regs->fsize[FW_FDMA_CH_CFG_CH_DCB_DB_CNT] + 1 - 1, 1) 4673 #define FDMA_CH_CFG_CH_DCB_DB_CNT_SET(x)\ 4674 spx5_field_prep(FDMA_CH_CFG_CH_DCB_DB_CNT, x) 4675 #define FDMA_CH_CFG_CH_DCB_DB_CNT_GET(x)\ 4676 spx5_field_get(FDMA_CH_CFG_CH_DCB_DB_CNT, x) 4677 4678 #define FDMA_CH_CFG_CH_MEM BIT(0) 4679 #define FDMA_CH_CFG_CH_MEM_SET(x)\ 4680 FIELD_PREP(FDMA_CH_CFG_CH_MEM, x) 4681 #define FDMA_CH_CFG_CH_MEM_GET(x)\ 4682 FIELD_GET(FDMA_CH_CFG_CH_MEM, x) 4683 4684 /* FDMA:FDMA:FDMA_CH_TRANSLATE */ 4685 #define FDMA_CH_TRANSLATE(r) \ 4686 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 256, r, 8,\ 4687 4) 4688 4689 #define FDMA_CH_TRANSLATE_OFFSET GENMASK(15, 0) 4690 #define FDMA_CH_TRANSLATE_OFFSET_SET(x)\ 4691 FIELD_PREP(FDMA_CH_TRANSLATE_OFFSET, x) 4692 #define FDMA_CH_TRANSLATE_OFFSET_GET(x)\ 4693 FIELD_GET(FDMA_CH_TRANSLATE_OFFSET, x) 4694 4695 /* FDMA:FDMA:FDMA_XTR_CFG */ 4696 #define FDMA_XTR_CFG \ 4697 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 364, 0, 1,\ 4698 4) 4699 4700 #define FDMA_XTR_CFG_XTR_FIFO_WM GENMASK(15, 11) 4701 #define FDMA_XTR_CFG_XTR_FIFO_WM_SET(x)\ 4702 FIELD_PREP(FDMA_XTR_CFG_XTR_FIFO_WM, x) 4703 #define FDMA_XTR_CFG_XTR_FIFO_WM_GET(x)\ 4704 FIELD_GET(FDMA_XTR_CFG_XTR_FIFO_WM, x) 4705 4706 #define FDMA_XTR_CFG_XTR_ARB_SAT GENMASK(10, 0) 4707 #define FDMA_XTR_CFG_XTR_ARB_SAT_SET(x)\ 4708 FIELD_PREP(FDMA_XTR_CFG_XTR_ARB_SAT, x) 4709 #define FDMA_XTR_CFG_XTR_ARB_SAT_GET(x)\ 4710 FIELD_GET(FDMA_XTR_CFG_XTR_ARB_SAT, x) 4711 4712 /* FDMA:FDMA:FDMA_PORT_CTRL */ 4713 #define FDMA_PORT_CTRL(r) \ 4714 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 376, r, 2,\ 4715 4) 4716 4717 #define FDMA_PORT_CTRL_INJ_STOP BIT(4) 4718 #define FDMA_PORT_CTRL_INJ_STOP_SET(x)\ 4719 FIELD_PREP(FDMA_PORT_CTRL_INJ_STOP, x) 4720 #define FDMA_PORT_CTRL_INJ_STOP_GET(x)\ 4721 FIELD_GET(FDMA_PORT_CTRL_INJ_STOP, x) 4722 4723 #define FDMA_PORT_CTRL_INJ_STOP_FORCE BIT(3) 4724 #define FDMA_PORT_CTRL_INJ_STOP_FORCE_SET(x)\ 4725 FIELD_PREP(FDMA_PORT_CTRL_INJ_STOP_FORCE, x) 4726 #define FDMA_PORT_CTRL_INJ_STOP_FORCE_GET(x)\ 4727 FIELD_GET(FDMA_PORT_CTRL_INJ_STOP_FORCE, x) 4728 4729 #define FDMA_PORT_CTRL_XTR_STOP BIT(2) 4730 #define FDMA_PORT_CTRL_XTR_STOP_SET(x)\ 4731 FIELD_PREP(FDMA_PORT_CTRL_XTR_STOP, x) 4732 #define FDMA_PORT_CTRL_XTR_STOP_GET(x)\ 4733 FIELD_GET(FDMA_PORT_CTRL_XTR_STOP, x) 4734 4735 #define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY BIT(1) 4736 #define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY_SET(x)\ 4737 FIELD_PREP(FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY, x) 4738 #define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY_GET(x)\ 4739 FIELD_GET(FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY, x) 4740 4741 #define FDMA_PORT_CTRL_XTR_BUF_RST BIT(0) 4742 #define FDMA_PORT_CTRL_XTR_BUF_RST_SET(x)\ 4743 FIELD_PREP(FDMA_PORT_CTRL_XTR_BUF_RST, x) 4744 #define FDMA_PORT_CTRL_XTR_BUF_RST_GET(x)\ 4745 FIELD_GET(FDMA_PORT_CTRL_XTR_BUF_RST, x) 4746 4747 /* FDMA:FDMA:FDMA_INTR_DCB */ 4748 #define FDMA_INTR_DCB \ 4749 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 384, 0, 1,\ 4750 4) 4751 4752 #define FDMA_INTR_DCB_INTR_DCB GENMASK(7, 0) 4753 #define FDMA_INTR_DCB_INTR_DCB_SET(x)\ 4754 FIELD_PREP(FDMA_INTR_DCB_INTR_DCB, x) 4755 #define FDMA_INTR_DCB_INTR_DCB_GET(x)\ 4756 FIELD_GET(FDMA_INTR_DCB_INTR_DCB, x) 4757 4758 /* FDMA:FDMA:FDMA_INTR_DCB_ENA */ 4759 #define FDMA_INTR_DCB_ENA \ 4760 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 388, 0, 1,\ 4761 4) 4762 4763 #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA GENMASK(7, 0) 4764 #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA_SET(x)\ 4765 FIELD_PREP(FDMA_INTR_DCB_ENA_INTR_DCB_ENA, x) 4766 #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA_GET(x)\ 4767 FIELD_GET(FDMA_INTR_DCB_ENA_INTR_DCB_ENA, x) 4768 4769 /* FDMA:FDMA:FDMA_INTR_DB */ 4770 #define FDMA_INTR_DB \ 4771 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 392, 0, 1,\ 4772 4) 4773 4774 #define FDMA_INTR_DB_INTR_DB GENMASK(7, 0) 4775 #define FDMA_INTR_DB_INTR_DB_SET(x)\ 4776 FIELD_PREP(FDMA_INTR_DB_INTR_DB, x) 4777 #define FDMA_INTR_DB_INTR_DB_GET(x)\ 4778 FIELD_GET(FDMA_INTR_DB_INTR_DB, x) 4779 4780 /* FDMA:FDMA:FDMA_INTR_DB_ENA */ 4781 #define FDMA_INTR_DB_ENA \ 4782 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 396, 0, 1,\ 4783 4) 4784 4785 #define FDMA_INTR_DB_ENA_INTR_DB_ENA GENMASK(7, 0) 4786 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_SET(x)\ 4787 FIELD_PREP(FDMA_INTR_DB_ENA_INTR_DB_ENA, x) 4788 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_GET(x)\ 4789 FIELD_GET(FDMA_INTR_DB_ENA_INTR_DB_ENA, x) 4790 4791 /* FDMA:FDMA:FDMA_INTR_ERR */ 4792 #define FDMA_INTR_ERR \ 4793 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 400, 0, 1,\ 4794 4) 4795 4796 #define FDMA_INTR_ERR_INTR_PORT_ERR GENMASK(9, 8) 4797 #define FDMA_INTR_ERR_INTR_PORT_ERR_SET(x)\ 4798 FIELD_PREP(FDMA_INTR_ERR_INTR_PORT_ERR, x) 4799 #define FDMA_INTR_ERR_INTR_PORT_ERR_GET(x)\ 4800 FIELD_GET(FDMA_INTR_ERR_INTR_PORT_ERR, x) 4801 4802 #define FDMA_INTR_ERR_INTR_CH_ERR GENMASK(7, 0) 4803 #define FDMA_INTR_ERR_INTR_CH_ERR_SET(x)\ 4804 FIELD_PREP(FDMA_INTR_ERR_INTR_CH_ERR, x) 4805 #define FDMA_INTR_ERR_INTR_CH_ERR_GET(x)\ 4806 FIELD_GET(FDMA_INTR_ERR_INTR_CH_ERR, x) 4807 4808 /* FDMA:FDMA:FDMA_ERRORS */ 4809 #define FDMA_ERRORS \ 4810 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 412, 0, 1,\ 4811 4) 4812 4813 #define FDMA_ERRORS_ERR_XTR_WR GENMASK(31, 30) 4814 #define FDMA_ERRORS_ERR_XTR_WR_SET(x)\ 4815 FIELD_PREP(FDMA_ERRORS_ERR_XTR_WR, x) 4816 #define FDMA_ERRORS_ERR_XTR_WR_GET(x)\ 4817 FIELD_GET(FDMA_ERRORS_ERR_XTR_WR, x) 4818 4819 #define FDMA_ERRORS_ERR_XTR_OVF GENMASK(29, 28) 4820 #define FDMA_ERRORS_ERR_XTR_OVF_SET(x)\ 4821 FIELD_PREP(FDMA_ERRORS_ERR_XTR_OVF, x) 4822 #define FDMA_ERRORS_ERR_XTR_OVF_GET(x)\ 4823 FIELD_GET(FDMA_ERRORS_ERR_XTR_OVF, x) 4824 4825 #define FDMA_ERRORS_ERR_XTR_TAXI32_OVF GENMASK(27, 26) 4826 #define FDMA_ERRORS_ERR_XTR_TAXI32_OVF_SET(x)\ 4827 FIELD_PREP(FDMA_ERRORS_ERR_XTR_TAXI32_OVF, x) 4828 #define FDMA_ERRORS_ERR_XTR_TAXI32_OVF_GET(x)\ 4829 FIELD_GET(FDMA_ERRORS_ERR_XTR_TAXI32_OVF, x) 4830 4831 #define FDMA_ERRORS_ERR_DCB_XTR_DATAL GENMASK(25, 24) 4832 #define FDMA_ERRORS_ERR_DCB_XTR_DATAL_SET(x)\ 4833 FIELD_PREP(FDMA_ERRORS_ERR_DCB_XTR_DATAL, x) 4834 #define FDMA_ERRORS_ERR_DCB_XTR_DATAL_GET(x)\ 4835 FIELD_GET(FDMA_ERRORS_ERR_DCB_XTR_DATAL, x) 4836 4837 #define FDMA_ERRORS_ERR_DCB_RD GENMASK(23, 16) 4838 #define FDMA_ERRORS_ERR_DCB_RD_SET(x)\ 4839 FIELD_PREP(FDMA_ERRORS_ERR_DCB_RD, x) 4840 #define FDMA_ERRORS_ERR_DCB_RD_GET(x)\ 4841 FIELD_GET(FDMA_ERRORS_ERR_DCB_RD, x) 4842 4843 #define FDMA_ERRORS_ERR_INJ_RD GENMASK(15, 10) 4844 #define FDMA_ERRORS_ERR_INJ_RD_SET(x)\ 4845 FIELD_PREP(FDMA_ERRORS_ERR_INJ_RD, x) 4846 #define FDMA_ERRORS_ERR_INJ_RD_GET(x)\ 4847 FIELD_GET(FDMA_ERRORS_ERR_INJ_RD, x) 4848 4849 #define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC GENMASK(9, 8) 4850 #define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC_SET(x)\ 4851 FIELD_PREP(FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC, x) 4852 #define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC_GET(x)\ 4853 FIELD_GET(FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC, x) 4854 4855 #define FDMA_ERRORS_ERR_CH_WR GENMASK(7, 0) 4856 #define FDMA_ERRORS_ERR_CH_WR_SET(x)\ 4857 FIELD_PREP(FDMA_ERRORS_ERR_CH_WR, x) 4858 #define FDMA_ERRORS_ERR_CH_WR_GET(x)\ 4859 FIELD_GET(FDMA_ERRORS_ERR_CH_WR, x) 4860 4861 /* FDMA:FDMA:FDMA_ERRORS_2 */ 4862 #define FDMA_ERRORS_2 \ 4863 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 416, 0, 1,\ 4864 4) 4865 4866 #define FDMA_ERRORS_2_ERR_XTR_FRAG GENMASK(1, 0) 4867 #define FDMA_ERRORS_2_ERR_XTR_FRAG_SET(x)\ 4868 FIELD_PREP(FDMA_ERRORS_2_ERR_XTR_FRAG, x) 4869 #define FDMA_ERRORS_2_ERR_XTR_FRAG_GET(x)\ 4870 FIELD_GET(FDMA_ERRORS_2_ERR_XTR_FRAG, x) 4871 4872 /* FDMA:FDMA:FDMA_CTRL */ 4873 #define FDMA_CTRL \ 4874 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 424, 0, 1,\ 4875 4) 4876 4877 #define FDMA_CTRL_NRESET BIT(0) 4878 #define FDMA_CTRL_NRESET_SET(x)\ 4879 FIELD_PREP(FDMA_CTRL_NRESET, x) 4880 #define FDMA_CTRL_NRESET_GET(x)\ 4881 FIELD_GET(FDMA_CTRL_NRESET, x) 4882 4883 /* DEVCPU_GCB:CHIP_REGS:CHIP_ID */ 4884 #define GCB_CHIP_ID \ 4885 __REG(TARGET_GCB, 0, 1, 0, 0, 1, regs->gsize[GW_GCB_CHIP_REGS], 0, 0, \ 4886 1, 4) 4887 4888 #define GCB_CHIP_ID_REV_ID GENMASK(31, 28) 4889 #define GCB_CHIP_ID_REV_ID_SET(x)\ 4890 FIELD_PREP(GCB_CHIP_ID_REV_ID, x) 4891 #define GCB_CHIP_ID_REV_ID_GET(x)\ 4892 FIELD_GET(GCB_CHIP_ID_REV_ID, x) 4893 4894 #define GCB_CHIP_ID_PART_ID GENMASK(27, 12) 4895 #define GCB_CHIP_ID_PART_ID_SET(x)\ 4896 FIELD_PREP(GCB_CHIP_ID_PART_ID, x) 4897 #define GCB_CHIP_ID_PART_ID_GET(x)\ 4898 FIELD_GET(GCB_CHIP_ID_PART_ID, x) 4899 4900 #define GCB_CHIP_ID_MFG_ID GENMASK(11, 1) 4901 #define GCB_CHIP_ID_MFG_ID_SET(x)\ 4902 FIELD_PREP(GCB_CHIP_ID_MFG_ID, x) 4903 #define GCB_CHIP_ID_MFG_ID_GET(x)\ 4904 FIELD_GET(GCB_CHIP_ID_MFG_ID, x) 4905 4906 #define GCB_CHIP_ID_ONE BIT(0) 4907 #define GCB_CHIP_ID_ONE_SET(x)\ 4908 FIELD_PREP(GCB_CHIP_ID_ONE, x) 4909 #define GCB_CHIP_ID_ONE_GET(x)\ 4910 FIELD_GET(GCB_CHIP_ID_ONE, x) 4911 4912 /* DEVCPU_GCB:CHIP_REGS:SOFT_RST */ 4913 #define GCB_SOFT_RST \ 4914 __REG(TARGET_GCB, 0, 1, 0, 0, 1, regs->gsize[GW_GCB_CHIP_REGS], \ 4915 regs->raddr[RA_GCB_SOFT_RST], 0, 1, 4) 4916 4917 /* SPARX5 ONLY */ 4918 #define GCB_SOFT_RST_SOFT_NON_CFG_RST BIT(2) 4919 #define GCB_SOFT_RST_SOFT_NON_CFG_RST_SET(x)\ 4920 FIELD_PREP(GCB_SOFT_RST_SOFT_NON_CFG_RST, x) 4921 #define GCB_SOFT_RST_SOFT_NON_CFG_RST_GET(x)\ 4922 FIELD_GET(GCB_SOFT_RST_SOFT_NON_CFG_RST, x) 4923 4924 #define GCB_SOFT_RST_SOFT_SWC_RST BIT(1) 4925 #define GCB_SOFT_RST_SOFT_SWC_RST_SET(x)\ 4926 FIELD_PREP(GCB_SOFT_RST_SOFT_SWC_RST, x) 4927 #define GCB_SOFT_RST_SOFT_SWC_RST_GET(x)\ 4928 FIELD_GET(GCB_SOFT_RST_SOFT_SWC_RST, x) 4929 4930 #define GCB_SOFT_RST_SOFT_CHIP_RST BIT(0) 4931 #define GCB_SOFT_RST_SOFT_CHIP_RST_SET(x)\ 4932 FIELD_PREP(GCB_SOFT_RST_SOFT_CHIP_RST, x) 4933 #define GCB_SOFT_RST_SOFT_CHIP_RST_GET(x)\ 4934 FIELD_GET(GCB_SOFT_RST_SOFT_CHIP_RST, x) 4935 4936 /* SPARX5 ONLY */ 4937 /* DEVCPU_GCB:CHIP_REGS:HW_SGPIO_SD_CFG */ 4938 #define GCB_HW_SGPIO_SD_CFG \ 4939 __REG(TARGET_GCB, 0, 1, 0, 0, 1, regs->gsize[GW_GCB_CHIP_REGS], 20, 0, \ 4940 1, 4) 4941 4942 #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA BIT(1) 4943 #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA_SET(x)\ 4944 FIELD_PREP(GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA, x) 4945 #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA_GET(x)\ 4946 FIELD_GET(GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA, x) 4947 4948 #define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL BIT(0) 4949 #define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL_SET(x)\ 4950 FIELD_PREP(GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL, x) 4951 #define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL_GET(x)\ 4952 FIELD_GET(GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL, x) 4953 4954 /* DEVCPU_GCB:CHIP_REGS:HW_SGPIO_TO_SD_MAP_CFG */ 4955 #define GCB_HW_SGPIO_TO_SD_MAP_CFG(r) \ 4956 __REG(TARGET_GCB, 0, 1, 0, 0, 1, regs->gsize[GW_GCB_CHIP_REGS], \ 4957 regs->raddr[RA_GCB_HW_SGPIO_TO_SD_MAP_CFG], r, \ 4958 regs->rcnt[RC_GCB_HW_SGPIO_TO_SD_MAP_CFG], 4) 4959 4960 #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL\ 4961 GENMASK(regs->fsize[FW_GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL] + 0 - 1, 0) 4962 #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL_SET(x)\ 4963 spx5_field_prep(GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL, x) 4964 #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL_GET(x)\ 4965 spx5_field_get(GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL, x) 4966 4967 /* DEVCPU_GCB:SIO_CTRL:SIO_CLOCK */ 4968 #define GCB_SIO_CLOCK(g) \ 4969 __REG(TARGET_GCB, 0, 1, regs->gaddr[GA_GCB_SIO_CTRL], g, \ 4970 regs->gcnt[GC_GCB_SIO_CTRL], 280, 20, 0, 1, 4) 4971 4972 #define GCB_SIO_CLOCK_SIO_CLK_FREQ GENMASK(19, 8) 4973 #define GCB_SIO_CLOCK_SIO_CLK_FREQ_SET(x)\ 4974 FIELD_PREP(GCB_SIO_CLOCK_SIO_CLK_FREQ, x) 4975 #define GCB_SIO_CLOCK_SIO_CLK_FREQ_GET(x)\ 4976 FIELD_GET(GCB_SIO_CLOCK_SIO_CLK_FREQ, x) 4977 4978 #define GCB_SIO_CLOCK_SYS_CLK_PERIOD GENMASK(7, 0) 4979 #define GCB_SIO_CLOCK_SYS_CLK_PERIOD_SET(x)\ 4980 FIELD_PREP(GCB_SIO_CLOCK_SYS_CLK_PERIOD, x) 4981 #define GCB_SIO_CLOCK_SYS_CLK_PERIOD_GET(x)\ 4982 FIELD_GET(GCB_SIO_CLOCK_SYS_CLK_PERIOD, x) 4983 4984 /* HSCH:HSCH_CFG:CIR_CFG */ 4985 #define HSCH_CIR_CFG(g) \ 4986 __REG(TARGET_HSCH, 0, 1, 0, g, regs->gcnt[GC_HSCH_HSCH_CFG], 32, 0, 0, \ 4987 1, 4) 4988 4989 #define HSCH_CIR_CFG_CIR_RATE GENMASK(22, 6) 4990 #define HSCH_CIR_CFG_CIR_RATE_SET(x)\ 4991 FIELD_PREP(HSCH_CIR_CFG_CIR_RATE, x) 4992 #define HSCH_CIR_CFG_CIR_RATE_GET(x)\ 4993 FIELD_GET(HSCH_CIR_CFG_CIR_RATE, x) 4994 4995 #define HSCH_CIR_CFG_CIR_BURST GENMASK(5, 0) 4996 #define HSCH_CIR_CFG_CIR_BURST_SET(x)\ 4997 FIELD_PREP(HSCH_CIR_CFG_CIR_BURST, x) 4998 #define HSCH_CIR_CFG_CIR_BURST_GET(x)\ 4999 FIELD_GET(HSCH_CIR_CFG_CIR_BURST, x) 5000 5001 /* HSCH:HSCH_CFG:EIR_CFG */ 5002 #define HSCH_EIR_CFG(g) \ 5003 __REG(TARGET_HSCH, 0, 1, 0, g, regs->gcnt[GC_HSCH_HSCH_CFG], 32, 4, 0, \ 5004 1, 4) 5005 5006 #define HSCH_EIR_CFG_EIR_RATE GENMASK(22, 6) 5007 #define HSCH_EIR_CFG_EIR_RATE_SET(x)\ 5008 FIELD_PREP(HSCH_EIR_CFG_EIR_RATE, x) 5009 #define HSCH_EIR_CFG_EIR_RATE_GET(x)\ 5010 FIELD_GET(HSCH_EIR_CFG_EIR_RATE, x) 5011 5012 #define HSCH_EIR_CFG_EIR_BURST GENMASK(5, 0) 5013 #define HSCH_EIR_CFG_EIR_BURST_SET(x)\ 5014 FIELD_PREP(HSCH_EIR_CFG_EIR_BURST, x) 5015 #define HSCH_EIR_CFG_EIR_BURST_GET(x)\ 5016 FIELD_GET(HSCH_EIR_CFG_EIR_BURST, x) 5017 5018 /* HSCH:HSCH_CFG:SE_CFG */ 5019 #define HSCH_SE_CFG(g) \ 5020 __REG(TARGET_HSCH, 0, 1, 0, g, regs->gcnt[GC_HSCH_HSCH_CFG], 32, 8, 0, \ 5021 1, 4) 5022 5023 #define HSCH_SE_CFG_SE_DWRR_CNT\ 5024 GENMASK(regs->fsize[FW_HSCH_SE_CFG_SE_DWRR_CNT] + 6 - 1, 6) 5025 #define HSCH_SE_CFG_SE_DWRR_CNT_SET(x)\ 5026 spx5_field_prep(HSCH_SE_CFG_SE_DWRR_CNT, x) 5027 #define HSCH_SE_CFG_SE_DWRR_CNT_GET(x)\ 5028 spx5_field_get(HSCH_SE_CFG_SE_DWRR_CNT, x) 5029 5030 #define HSCH_SE_CFG_SE_AVB_ENA BIT(5) 5031 #define HSCH_SE_CFG_SE_AVB_ENA_SET(x)\ 5032 FIELD_PREP(HSCH_SE_CFG_SE_AVB_ENA, x) 5033 #define HSCH_SE_CFG_SE_AVB_ENA_GET(x)\ 5034 FIELD_GET(HSCH_SE_CFG_SE_AVB_ENA, x) 5035 5036 #define HSCH_SE_CFG_SE_FRM_MODE GENMASK(4, 3) 5037 #define HSCH_SE_CFG_SE_FRM_MODE_SET(x)\ 5038 FIELD_PREP(HSCH_SE_CFG_SE_FRM_MODE, x) 5039 #define HSCH_SE_CFG_SE_FRM_MODE_GET(x)\ 5040 FIELD_GET(HSCH_SE_CFG_SE_FRM_MODE, x) 5041 5042 #define HSCH_SE_CFG_SE_DWRR_FRM_MODE GENMASK(2, 1) 5043 #define HSCH_SE_CFG_SE_DWRR_FRM_MODE_SET(x)\ 5044 FIELD_PREP(HSCH_SE_CFG_SE_DWRR_FRM_MODE, x) 5045 #define HSCH_SE_CFG_SE_DWRR_FRM_MODE_GET(x)\ 5046 FIELD_GET(HSCH_SE_CFG_SE_DWRR_FRM_MODE, x) 5047 5048 #define HSCH_SE_CFG_SE_STOP BIT(0) 5049 #define HSCH_SE_CFG_SE_STOP_SET(x)\ 5050 FIELD_PREP(HSCH_SE_CFG_SE_STOP, x) 5051 #define HSCH_SE_CFG_SE_STOP_GET(x)\ 5052 FIELD_GET(HSCH_SE_CFG_SE_STOP, x) 5053 5054 /* HSCH:HSCH_CFG:SE_CONNECT */ 5055 #define HSCH_SE_CONNECT(g) \ 5056 __REG(TARGET_HSCH, 0, 1, 0, g, regs->gcnt[GC_HSCH_HSCH_CFG], 32, 12, 0,\ 5057 1, 4) 5058 5059 #define HSCH_SE_CONNECT_SE_LEAK_LINK\ 5060 GENMASK(regs->fsize[FW_HSCH_SE_CONNECT_SE_LEAK_LINK] + 0 - 1, 0) 5061 #define HSCH_SE_CONNECT_SE_LEAK_LINK_SET(x)\ 5062 spx5_field_prep(HSCH_SE_CONNECT_SE_LEAK_LINK, x) 5063 #define HSCH_SE_CONNECT_SE_LEAK_LINK_GET(x)\ 5064 spx5_field_get(HSCH_SE_CONNECT_SE_LEAK_LINK, x) 5065 5066 /* HSCH:HSCH_CFG:SE_DLB_SENSE */ 5067 #define HSCH_SE_DLB_SENSE(g) \ 5068 __REG(TARGET_HSCH, 0, 1, 0, g, regs->gcnt[GC_HSCH_HSCH_CFG], 32, 16, 0,\ 5069 1, 4) 5070 5071 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO GENMASK(12, 10) 5072 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_SET(x)\ 5073 FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_PRIO, x) 5074 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_GET(x)\ 5075 FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_PRIO, x) 5076 5077 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT\ 5078 GENMASK(regs->fsize[FW_HSCH_SE_DLB_SENSE_SE_DLB_DPORT] + 3 - 1, 3) 5079 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_SET(x)\ 5080 spx5_field_prep(HSCH_SE_DLB_SENSE_SE_DLB_DPORT, x) 5081 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_GET(x)\ 5082 spx5_field_get(HSCH_SE_DLB_SENSE_SE_DLB_DPORT, x) 5083 5084 #define HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA BIT(2) 5085 #define HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA_SET(x)\ 5086 FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA, x) 5087 #define HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA_GET(x)\ 5088 FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA, x) 5089 5090 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA BIT(1) 5091 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA_SET(x)\ 5092 FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA, x) 5093 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA_GET(x)\ 5094 FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA, x) 5095 5096 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA BIT(0) 5097 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA_SET(x)\ 5098 FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA, x) 5099 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA_GET(x)\ 5100 FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA, x) 5101 5102 /* HSCH:HSCH_DWRR:DWRR_ENTRY */ 5103 #define HSCH_DWRR_ENTRY(g) \ 5104 __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_HSCH_DWRR], g, \ 5105 regs->gcnt[GC_HSCH_HSCH_DWRR], 4, 0, 0, 1, 4) 5106 5107 #define HSCH_DWRR_ENTRY_DWRR_COST GENMASK(24, 20) 5108 #define HSCH_DWRR_ENTRY_DWRR_COST_SET(x)\ 5109 FIELD_PREP(HSCH_DWRR_ENTRY_DWRR_COST, x) 5110 #define HSCH_DWRR_ENTRY_DWRR_COST_GET(x)\ 5111 FIELD_GET(HSCH_DWRR_ENTRY_DWRR_COST, x) 5112 5113 #define HSCH_DWRR_ENTRY_DWRR_BALANCE GENMASK(19, 0) 5114 #define HSCH_DWRR_ENTRY_DWRR_BALANCE_SET(x)\ 5115 FIELD_PREP(HSCH_DWRR_ENTRY_DWRR_BALANCE, x) 5116 #define HSCH_DWRR_ENTRY_DWRR_BALANCE_GET(x)\ 5117 FIELD_GET(HSCH_DWRR_ENTRY_DWRR_BALANCE, x) 5118 5119 /* HSCH:HSCH_MISC:HSCH_CFG_CFG */ 5120 #define HSCH_HSCH_CFG_CFG \ 5121 __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_HSCH_MISC], 0, 1, 648, \ 5122 284, 0, 1, 4) 5123 5124 #define HSCH_HSCH_CFG_CFG_CFG_SE_IDX\ 5125 GENMASK(regs->fsize[FW_HSCH_HSCH_CFG_CFG_CFG_SE_IDX] + 14 - 1, 14) 5126 #define HSCH_HSCH_CFG_CFG_CFG_SE_IDX_SET(x)\ 5127 spx5_field_prep(HSCH_HSCH_CFG_CFG_CFG_SE_IDX, x) 5128 #define HSCH_HSCH_CFG_CFG_CFG_SE_IDX_GET(x)\ 5129 spx5_field_get(HSCH_HSCH_CFG_CFG_CFG_SE_IDX, x) 5130 5131 #define HSCH_HSCH_CFG_CFG_HSCH_LAYER GENMASK(13, 12) 5132 #define HSCH_HSCH_CFG_CFG_HSCH_LAYER_SET(x)\ 5133 FIELD_PREP(HSCH_HSCH_CFG_CFG_HSCH_LAYER, x) 5134 #define HSCH_HSCH_CFG_CFG_HSCH_LAYER_GET(x)\ 5135 FIELD_GET(HSCH_HSCH_CFG_CFG_HSCH_LAYER, x) 5136 5137 #define HSCH_HSCH_CFG_CFG_CSR_GRANT GENMASK(11, 0) 5138 #define HSCH_HSCH_CFG_CFG_CSR_GRANT_SET(x)\ 5139 FIELD_PREP(HSCH_HSCH_CFG_CFG_CSR_GRANT, x) 5140 #define HSCH_HSCH_CFG_CFG_CSR_GRANT_GET(x)\ 5141 FIELD_GET(HSCH_HSCH_CFG_CFG_CSR_GRANT, x) 5142 5143 /* SPARX5 ONLY */ 5144 /* HSCH:HSCH_MISC:SYS_CLK_PER */ 5145 #define HSCH_SYS_CLK_PER \ 5146 __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_HSCH_MISC], 0, 1, 648, \ 5147 640, 0, 1, 4) 5148 5149 #define HSCH_SYS_CLK_PER_100PS GENMASK(7, 0) 5150 #define HSCH_SYS_CLK_PER_100PS_SET(x)\ 5151 FIELD_PREP(HSCH_SYS_CLK_PER_100PS, x) 5152 #define HSCH_SYS_CLK_PER_100PS_GET(x)\ 5153 FIELD_GET(HSCH_SYS_CLK_PER_100PS, x) 5154 5155 /* HSCH:HSCH_LEAK_LISTS:HSCH_TIMER_CFG */ 5156 #define HSCH_HSCH_TIMER_CFG(g, r) \ 5157 __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_HSCH_LEAK_LISTS], g, 4, \ 5158 32, 0, r, 4, 4) 5159 5160 #define HSCH_HSCH_TIMER_CFG_LEAK_TIME GENMASK(17, 0) 5161 #define HSCH_HSCH_TIMER_CFG_LEAK_TIME_SET(x)\ 5162 FIELD_PREP(HSCH_HSCH_TIMER_CFG_LEAK_TIME, x) 5163 #define HSCH_HSCH_TIMER_CFG_LEAK_TIME_GET(x)\ 5164 FIELD_GET(HSCH_HSCH_TIMER_CFG_LEAK_TIME, x) 5165 5166 /* HSCH:HSCH_LEAK_LISTS:HSCH_LEAK_CFG */ 5167 #define HSCH_HSCH_LEAK_CFG(g, r) \ 5168 __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_HSCH_LEAK_LISTS], g, 4, \ 5169 32, 16, r, 4, 4) 5170 5171 #define HSCH_HSCH_LEAK_CFG_LEAK_FIRST\ 5172 GENMASK(regs->fsize[FW_HSCH_HSCH_LEAK_CFG_LEAK_FIRST] + 1 - 1, 1) 5173 #define HSCH_HSCH_LEAK_CFG_LEAK_FIRST_SET(x)\ 5174 spx5_field_prep(HSCH_HSCH_LEAK_CFG_LEAK_FIRST, x) 5175 #define HSCH_HSCH_LEAK_CFG_LEAK_FIRST_GET(x)\ 5176 spx5_field_get(HSCH_HSCH_LEAK_CFG_LEAK_FIRST, x) 5177 5178 #define HSCH_HSCH_LEAK_CFG_LEAK_ERR BIT(0) 5179 #define HSCH_HSCH_LEAK_CFG_LEAK_ERR_SET(x)\ 5180 FIELD_PREP(HSCH_HSCH_LEAK_CFG_LEAK_ERR, x) 5181 #define HSCH_HSCH_LEAK_CFG_LEAK_ERR_GET(x)\ 5182 FIELD_GET(HSCH_HSCH_LEAK_CFG_LEAK_ERR, x) 5183 5184 /* HSCH:SYSTEM:FLUSH_CTRL */ 5185 #define HSCH_FLUSH_CTRL \ 5186 __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_SYSTEM], 0, 1, 312, 4, 0, \ 5187 1, 4) 5188 5189 #define HSCH_FLUSH_CTRL_FLUSH_ENA BIT(27) 5190 #define HSCH_FLUSH_CTRL_FLUSH_ENA_SET(x)\ 5191 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_ENA, x) 5192 #define HSCH_FLUSH_CTRL_FLUSH_ENA_GET(x)\ 5193 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_ENA, x) 5194 5195 #define HSCH_FLUSH_CTRL_FLUSH_SRC BIT(26) 5196 #define HSCH_FLUSH_CTRL_FLUSH_SRC_SET(x)\ 5197 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_SRC, x) 5198 #define HSCH_FLUSH_CTRL_FLUSH_SRC_GET(x)\ 5199 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_SRC, x) 5200 5201 #define HSCH_FLUSH_CTRL_FLUSH_DST BIT(25) 5202 #define HSCH_FLUSH_CTRL_FLUSH_DST_SET(x)\ 5203 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_DST, x) 5204 #define HSCH_FLUSH_CTRL_FLUSH_DST_GET(x)\ 5205 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_DST, x) 5206 5207 #define HSCH_FLUSH_CTRL_FLUSH_PORT\ 5208 GENMASK(regs->fsize[FW_HSCH_FLUSH_CTRL_FLUSH_PORT] + 18 - 1, 18) 5209 #define HSCH_FLUSH_CTRL_FLUSH_PORT_SET(x)\ 5210 spx5_field_prep(HSCH_FLUSH_CTRL_FLUSH_PORT, x) 5211 #define HSCH_FLUSH_CTRL_FLUSH_PORT_GET(x)\ 5212 spx5_field_get(HSCH_FLUSH_CTRL_FLUSH_PORT, x) 5213 5214 #define HSCH_FLUSH_CTRL_FLUSH_QUEUE BIT(17) 5215 #define HSCH_FLUSH_CTRL_FLUSH_QUEUE_SET(x)\ 5216 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_QUEUE, x) 5217 #define HSCH_FLUSH_CTRL_FLUSH_QUEUE_GET(x)\ 5218 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_QUEUE, x) 5219 5220 #define HSCH_FLUSH_CTRL_FLUSH_SE BIT(16) 5221 #define HSCH_FLUSH_CTRL_FLUSH_SE_SET(x)\ 5222 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_SE, x) 5223 #define HSCH_FLUSH_CTRL_FLUSH_SE_GET(x)\ 5224 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_SE, x) 5225 5226 #define HSCH_FLUSH_CTRL_FLUSH_HIER\ 5227 GENMASK(regs->fsize[FW_HSCH_FLUSH_CTRL_FLUSH_HIER] + 0 - 1, 0) 5228 #define HSCH_FLUSH_CTRL_FLUSH_HIER_SET(x)\ 5229 spx5_field_prep(HSCH_FLUSH_CTRL_FLUSH_HIER, x) 5230 #define HSCH_FLUSH_CTRL_FLUSH_HIER_GET(x)\ 5231 spx5_field_get(HSCH_FLUSH_CTRL_FLUSH_HIER, x) 5232 5233 /* HSCH:SYSTEM:PORT_MODE */ 5234 #define HSCH_PORT_MODE(r) \ 5235 __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_SYSTEM], 0, 1, 312, 8, r, \ 5236 regs->rcnt[RC_HSCH_PORT_MODE], 4) 5237 5238 #define HSCH_PORT_MODE_DEQUEUE_DIS BIT(4) 5239 #define HSCH_PORT_MODE_DEQUEUE_DIS_SET(x)\ 5240 FIELD_PREP(HSCH_PORT_MODE_DEQUEUE_DIS, x) 5241 #define HSCH_PORT_MODE_DEQUEUE_DIS_GET(x)\ 5242 FIELD_GET(HSCH_PORT_MODE_DEQUEUE_DIS, x) 5243 5244 #define HSCH_PORT_MODE_AGE_DIS BIT(3) 5245 #define HSCH_PORT_MODE_AGE_DIS_SET(x)\ 5246 FIELD_PREP(HSCH_PORT_MODE_AGE_DIS, x) 5247 #define HSCH_PORT_MODE_AGE_DIS_GET(x)\ 5248 FIELD_GET(HSCH_PORT_MODE_AGE_DIS, x) 5249 5250 #define HSCH_PORT_MODE_TRUNC_ENA BIT(2) 5251 #define HSCH_PORT_MODE_TRUNC_ENA_SET(x)\ 5252 FIELD_PREP(HSCH_PORT_MODE_TRUNC_ENA, x) 5253 #define HSCH_PORT_MODE_TRUNC_ENA_GET(x)\ 5254 FIELD_GET(HSCH_PORT_MODE_TRUNC_ENA, x) 5255 5256 #define HSCH_PORT_MODE_EIR_REMARK_ENA BIT(1) 5257 #define HSCH_PORT_MODE_EIR_REMARK_ENA_SET(x)\ 5258 FIELD_PREP(HSCH_PORT_MODE_EIR_REMARK_ENA, x) 5259 #define HSCH_PORT_MODE_EIR_REMARK_ENA_GET(x)\ 5260 FIELD_GET(HSCH_PORT_MODE_EIR_REMARK_ENA, x) 5261 5262 #define HSCH_PORT_MODE_CPU_PRIO_MODE BIT(0) 5263 #define HSCH_PORT_MODE_CPU_PRIO_MODE_SET(x)\ 5264 FIELD_PREP(HSCH_PORT_MODE_CPU_PRIO_MODE, x) 5265 #define HSCH_PORT_MODE_CPU_PRIO_MODE_GET(x)\ 5266 FIELD_GET(HSCH_PORT_MODE_CPU_PRIO_MODE, x) 5267 5268 /* HSCH:SYSTEM:OUTB_SHARE_ENA */ 5269 #define HSCH_OUTB_SHARE_ENA(r) \ 5270 __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_SYSTEM], 0, 1, 312, 288, \ 5271 r, 5, 4) 5272 5273 #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA GENMASK(7, 0) 5274 #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_SET(x)\ 5275 FIELD_PREP(HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA, x) 5276 #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_GET(x)\ 5277 FIELD_GET(HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA, x) 5278 5279 /* HSCH:MMGT:RESET_CFG */ 5280 #define HSCH_RESET_CFG \ 5281 __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_MMGT], 0, 1, 16, 8, 0, 1, \ 5282 4) 5283 5284 #define HSCH_RESET_CFG_CORE_ENA BIT(0) 5285 #define HSCH_RESET_CFG_CORE_ENA_SET(x)\ 5286 FIELD_PREP(HSCH_RESET_CFG_CORE_ENA, x) 5287 #define HSCH_RESET_CFG_CORE_ENA_GET(x)\ 5288 FIELD_GET(HSCH_RESET_CFG_CORE_ENA, x) 5289 5290 /* HSCH:TAS_CONFIG:TAS_STATEMACHINE_CFG */ 5291 #define HSCH_TAS_STATEMACHINE_CFG \ 5292 __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_TAS_CONFIG], 0, 1, \ 5293 regs->gsize[GW_HSCH_TAS_CONFIG], 8, 0, 1, 4) 5294 5295 #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY GENMASK(7, 0) 5296 #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_SET(x)\ 5297 FIELD_PREP(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY, x) 5298 #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_GET(x)\ 5299 FIELD_GET(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY, x) 5300 5301 /* LRN:COMMON:COMMON_ACCESS_CTRL */ 5302 #define LRN_COMMON_ACCESS_CTRL \ 5303 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 0, 0, 1, 4) 5304 5305 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL GENMASK(21, 20) 5306 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL_SET(x)\ 5307 FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL, x) 5308 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL_GET(x)\ 5309 FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL, x) 5310 5311 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE BIT(19) 5312 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE_SET(x)\ 5313 FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE, x) 5314 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE_GET(x)\ 5315 FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE, x) 5316 5317 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW\ 5318 GENMASK(regs->fsize[FW_LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW] + 5 - 1, 5) 5319 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW_SET(x)\ 5320 spx5_field_prep(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW, x) 5321 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW_GET(x)\ 5322 spx5_field_get(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW, x) 5323 5324 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD GENMASK(4, 1) 5325 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_SET(x)\ 5326 FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD, x) 5327 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_GET(x)\ 5328 FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD, x) 5329 5330 #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT BIT(0) 5331 #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_SET(x)\ 5332 FIELD_PREP(LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT, x) 5333 #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_GET(x)\ 5334 FIELD_GET(LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT, x) 5335 5336 /* LRN:COMMON:MAC_ACCESS_CFG_0 */ 5337 #define LRN_MAC_ACCESS_CFG_0 \ 5338 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 4, 0, 1, 4) 5339 5340 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID GENMASK(28, 16) 5341 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID_SET(x)\ 5342 FIELD_PREP(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID, x) 5343 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID_GET(x)\ 5344 FIELD_GET(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID, x) 5345 5346 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB GENMASK(15, 0) 5347 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB_SET(x)\ 5348 FIELD_PREP(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB, x) 5349 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB_GET(x)\ 5350 FIELD_GET(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB, x) 5351 5352 /* LRN:COMMON:MAC_ACCESS_CFG_1 */ 5353 #define LRN_MAC_ACCESS_CFG_1 \ 5354 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 8, 0, 1, 4) 5355 5356 /* LRN:COMMON:MAC_ACCESS_CFG_2 */ 5357 #define LRN_MAC_ACCESS_CFG_2 \ 5358 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 12, 0, 1, 4) 5359 5360 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD BIT(28) 5361 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD_SET(x)\ 5362 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD, x) 5363 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD_GET(x)\ 5364 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD, x) 5365 5366 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL BIT(27) 5367 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL_SET(x)\ 5368 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL, x) 5369 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL_GET(x)\ 5370 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL, x) 5371 5372 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU GENMASK(26, 24) 5373 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU_SET(x)\ 5374 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU, x) 5375 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU_GET(x)\ 5376 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU, x) 5377 5378 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY BIT(23) 5379 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY_SET(x)\ 5380 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY, x) 5381 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY_GET(x)\ 5382 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY, x) 5383 5384 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE BIT(22) 5385 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE_SET(x)\ 5386 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE, x) 5387 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE_GET(x)\ 5388 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE, x) 5389 5390 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR BIT(21) 5391 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR_SET(x)\ 5392 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR, x) 5393 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR_GET(x)\ 5394 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR, x) 5395 5396 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG GENMASK(20, 19) 5397 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG_SET(x)\ 5398 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG, x) 5399 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG_GET(x)\ 5400 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG, x) 5401 5402 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL GENMASK(18, 17) 5403 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL_SET(x)\ 5404 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL, x) 5405 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL_GET(x)\ 5406 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL, x) 5407 5408 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED BIT(16) 5409 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED_SET(x)\ 5410 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED, x) 5411 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED_GET(x)\ 5412 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED, x) 5413 5414 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD BIT(15) 5415 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD_SET(x)\ 5416 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD, x) 5417 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD_GET(x)\ 5418 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD, x) 5419 5420 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE GENMASK(14, 12) 5421 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE_SET(x)\ 5422 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE, x) 5423 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE_GET(x)\ 5424 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE, x) 5425 5426 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR GENMASK(11, 0) 5427 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_SET(x)\ 5428 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR, x) 5429 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_GET(x)\ 5430 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR, x) 5431 5432 /* LRN:COMMON:MAC_ACCESS_CFG_3 */ 5433 #define LRN_MAC_ACCESS_CFG_3 \ 5434 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 16, 0, 1, 4) 5435 5436 #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX\ 5437 GENMASK(regs->fsize[FW_LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX] + 0 - 1, 0) 5438 #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX_SET(x)\ 5439 spx5_field_prep(LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX, x) 5440 #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX_GET(x)\ 5441 spx5_field_get(LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX, x) 5442 5443 /* LRN:COMMON:SCAN_NEXT_CFG */ 5444 #define LRN_SCAN_NEXT_CFG \ 5445 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 20, 0, 1, 4) 5446 5447 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL GENMASK(21, 19) 5448 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL_SET(x)\ 5449 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL, x) 5450 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL_GET(x)\ 5451 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL, x) 5452 5453 #define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL GENMASK(18, 17) 5454 #define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL_SET(x)\ 5455 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL, x) 5456 #define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL_GET(x)\ 5457 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL, x) 5458 5459 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL GENMASK(16, 15) 5460 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL_SET(x)\ 5461 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL, x) 5462 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL_GET(x)\ 5463 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL, x) 5464 5465 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA BIT(14) 5466 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA_SET(x)\ 5467 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA, x) 5468 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA_GET(x)\ 5469 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA, x) 5470 5471 #define LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA BIT(13) 5472 #define LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA_SET(x)\ 5473 FIELD_PREP(LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA, x) 5474 #define LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA_GET(x)\ 5475 FIELD_GET(LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA, x) 5476 5477 #define LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA BIT(12) 5478 #define LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA_SET(x)\ 5479 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA, x) 5480 #define LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA_GET(x)\ 5481 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA, x) 5482 5483 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA BIT(11) 5484 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA_SET(x)\ 5485 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA, x) 5486 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA_GET(x)\ 5487 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA, x) 5488 5489 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA BIT(10) 5490 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_SET(x)\ 5491 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA, x) 5492 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_GET(x)\ 5493 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA, x) 5494 5495 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA BIT(9) 5496 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA_SET(x)\ 5497 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA, x) 5498 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA_GET(x)\ 5499 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA, x) 5500 5501 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA BIT(8) 5502 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA_SET(x)\ 5503 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA, x) 5504 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA_GET(x)\ 5505 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA, x) 5506 5507 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA BIT(7) 5508 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_SET(x)\ 5509 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA, x) 5510 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_GET(x)\ 5511 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA, x) 5512 5513 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK GENMASK(6, 3) 5514 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK_SET(x)\ 5515 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK, x) 5516 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK_GET(x)\ 5517 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK, x) 5518 5519 #define LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA BIT(2) 5520 #define LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA_SET(x)\ 5521 FIELD_PREP(LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA, x) 5522 #define LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA_GET(x)\ 5523 FIELD_GET(LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA, x) 5524 5525 #define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA BIT(1) 5526 #define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA_SET(x)\ 5527 FIELD_PREP(LRN_SCAN_NEXT_CFG_FID_FILTER_ENA, x) 5528 #define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA_GET(x)\ 5529 FIELD_GET(LRN_SCAN_NEXT_CFG_FID_FILTER_ENA, x) 5530 5531 #define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA BIT(0) 5532 #define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA_SET(x)\ 5533 FIELD_PREP(LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA, x) 5534 #define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA_GET(x)\ 5535 FIELD_GET(LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA, x) 5536 5537 /* LRN:COMMON:SCAN_NEXT_CFG_1 */ 5538 #define LRN_SCAN_NEXT_CFG_1 \ 5539 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 24, 0, 1, 4) 5540 5541 #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR GENMASK(30, 16) 5542 #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR_SET(x)\ 5543 FIELD_PREP(LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR, x) 5544 #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR_GET(x)\ 5545 FIELD_GET(LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR, x) 5546 5547 #define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK GENMASK(14, 0) 5548 #define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK_SET(x)\ 5549 FIELD_PREP(LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK, x) 5550 #define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK_GET(x)\ 5551 FIELD_GET(LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK, x) 5552 5553 /* LRN:COMMON:AUTOAGE_CFG */ 5554 #define LRN_AUTOAGE_CFG(r) \ 5555 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 36, r, 4, 4) 5556 5557 #define LRN_AUTOAGE_CFG_UNIT_SIZE GENMASK(29, 28) 5558 #define LRN_AUTOAGE_CFG_UNIT_SIZE_SET(x)\ 5559 FIELD_PREP(LRN_AUTOAGE_CFG_UNIT_SIZE, x) 5560 #define LRN_AUTOAGE_CFG_UNIT_SIZE_GET(x)\ 5561 FIELD_GET(LRN_AUTOAGE_CFG_UNIT_SIZE, x) 5562 5563 #define LRN_AUTOAGE_CFG_PERIOD_VAL GENMASK(27, 0) 5564 #define LRN_AUTOAGE_CFG_PERIOD_VAL_SET(x)\ 5565 FIELD_PREP(LRN_AUTOAGE_CFG_PERIOD_VAL, x) 5566 #define LRN_AUTOAGE_CFG_PERIOD_VAL_GET(x)\ 5567 FIELD_GET(LRN_AUTOAGE_CFG_PERIOD_VAL, x) 5568 5569 /* LRN:COMMON:AUTOAGE_CFG_1 */ 5570 #define LRN_AUTOAGE_CFG_1 \ 5571 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 52, 0, 1, 4) 5572 5573 #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA BIT(25) 5574 #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA_SET(x)\ 5575 FIELD_PREP(LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA, x) 5576 #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA_GET(x)\ 5577 FIELD_GET(LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA, x) 5578 5579 #define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN GENMASK(24, 15) 5580 #define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN_SET(x)\ 5581 FIELD_PREP(LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN, x) 5582 #define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN_GET(x)\ 5583 FIELD_GET(LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN, x) 5584 5585 #define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS GENMASK(14, 7) 5586 #define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_SET(x)\ 5587 FIELD_PREP(LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS, x) 5588 #define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_GET(x)\ 5589 FIELD_GET(LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS, x) 5590 5591 #define LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA BIT(6) 5592 #define LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA_SET(x)\ 5593 FIELD_PREP(LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA, x) 5594 #define LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA_GET(x)\ 5595 FIELD_GET(LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA, x) 5596 5597 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT GENMASK(5, 2) 5598 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT_SET(x)\ 5599 FIELD_PREP(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT, x) 5600 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT_GET(x)\ 5601 FIELD_GET(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT, x) 5602 5603 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT BIT(1) 5604 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT_SET(x)\ 5605 FIELD_PREP(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT, x) 5606 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT_GET(x)\ 5607 FIELD_GET(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT, x) 5608 5609 #define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA BIT(0) 5610 #define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA_SET(x)\ 5611 FIELD_PREP(LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA, x) 5612 #define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA_GET(x)\ 5613 FIELD_GET(LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA, x) 5614 5615 /* LRN:COMMON:AUTOAGE_CFG_2 */ 5616 #define LRN_AUTOAGE_CFG_2 \ 5617 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 56, 0, 1, 4) 5618 5619 #define LRN_AUTOAGE_CFG_2_NEXT_ROW\ 5620 GENMASK(regs->fsize[FW_LRN_AUTOAGE_CFG_2_NEXT_ROW] + 4 - 1, 4) 5621 #define LRN_AUTOAGE_CFG_2_NEXT_ROW_SET(x)\ 5622 spx5_field_prep(LRN_AUTOAGE_CFG_2_NEXT_ROW, x) 5623 #define LRN_AUTOAGE_CFG_2_NEXT_ROW_GET(x)\ 5624 spx5_field_get(LRN_AUTOAGE_CFG_2_NEXT_ROW, x) 5625 5626 #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS GENMASK(3, 0) 5627 #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS_SET(x)\ 5628 FIELD_PREP(LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS, x) 5629 #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS_GET(x)\ 5630 FIELD_GET(LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS, x) 5631 5632 /* SPARX5 ONLY */ 5633 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_REGION_CTRL_2_OFF_OUTBOUND_0 */ 5634 #define PCEP_RCTRL_2_OUT_0 \ 5635 __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 4, 0, 1, 4) 5636 5637 #define PCEP_RCTRL_2_OUT_0_MSG_CODE GENMASK(7, 0) 5638 #define PCEP_RCTRL_2_OUT_0_MSG_CODE_SET(x)\ 5639 FIELD_PREP(PCEP_RCTRL_2_OUT_0_MSG_CODE, x) 5640 #define PCEP_RCTRL_2_OUT_0_MSG_CODE_GET(x)\ 5641 FIELD_GET(PCEP_RCTRL_2_OUT_0_MSG_CODE, x) 5642 5643 #define PCEP_RCTRL_2_OUT_0_TAG GENMASK(15, 8) 5644 #define PCEP_RCTRL_2_OUT_0_TAG_SET(x)\ 5645 FIELD_PREP(PCEP_RCTRL_2_OUT_0_TAG, x) 5646 #define PCEP_RCTRL_2_OUT_0_TAG_GET(x)\ 5647 FIELD_GET(PCEP_RCTRL_2_OUT_0_TAG, x) 5648 5649 #define PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN BIT(16) 5650 #define PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN_SET(x)\ 5651 FIELD_PREP(PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN, x) 5652 #define PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN_GET(x)\ 5653 FIELD_GET(PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN, x) 5654 5655 #define PCEP_RCTRL_2_OUT_0_FUNC_BYPASS BIT(19) 5656 #define PCEP_RCTRL_2_OUT_0_FUNC_BYPASS_SET(x)\ 5657 FIELD_PREP(PCEP_RCTRL_2_OUT_0_FUNC_BYPASS, x) 5658 #define PCEP_RCTRL_2_OUT_0_FUNC_BYPASS_GET(x)\ 5659 FIELD_GET(PCEP_RCTRL_2_OUT_0_FUNC_BYPASS, x) 5660 5661 #define PCEP_RCTRL_2_OUT_0_SNP BIT(20) 5662 #define PCEP_RCTRL_2_OUT_0_SNP_SET(x)\ 5663 FIELD_PREP(PCEP_RCTRL_2_OUT_0_SNP, x) 5664 #define PCEP_RCTRL_2_OUT_0_SNP_GET(x)\ 5665 FIELD_GET(PCEP_RCTRL_2_OUT_0_SNP, x) 5666 5667 #define PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD BIT(22) 5668 #define PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD_SET(x)\ 5669 FIELD_PREP(PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD, x) 5670 #define PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD_GET(x)\ 5671 FIELD_GET(PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD, x) 5672 5673 #define PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN BIT(23) 5674 #define PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN_SET(x)\ 5675 FIELD_PREP(PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN, x) 5676 #define PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN_GET(x)\ 5677 FIELD_GET(PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN, x) 5678 5679 #define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE BIT(28) 5680 #define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE_SET(x)\ 5681 FIELD_PREP(PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE, x) 5682 #define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE_GET(x)\ 5683 FIELD_GET(PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE, x) 5684 5685 #define PCEP_RCTRL_2_OUT_0_INVERT_MODE BIT(29) 5686 #define PCEP_RCTRL_2_OUT_0_INVERT_MODE_SET(x)\ 5687 FIELD_PREP(PCEP_RCTRL_2_OUT_0_INVERT_MODE, x) 5688 #define PCEP_RCTRL_2_OUT_0_INVERT_MODE_GET(x)\ 5689 FIELD_GET(PCEP_RCTRL_2_OUT_0_INVERT_MODE, x) 5690 5691 #define PCEP_RCTRL_2_OUT_0_REGION_EN BIT(31) 5692 #define PCEP_RCTRL_2_OUT_0_REGION_EN_SET(x)\ 5693 FIELD_PREP(PCEP_RCTRL_2_OUT_0_REGION_EN, x) 5694 #define PCEP_RCTRL_2_OUT_0_REGION_EN_GET(x)\ 5695 FIELD_GET(PCEP_RCTRL_2_OUT_0_REGION_EN, x) 5696 5697 /* SPARX5 ONLY */ 5698 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 */ 5699 #define PCEP_ADDR_LWR_OUT_0 \ 5700 __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 8, 0, 1, 4) 5701 5702 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW GENMASK(15, 0) 5703 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW_SET(x)\ 5704 FIELD_PREP(PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW, x) 5705 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW_GET(x)\ 5706 FIELD_GET(PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW, x) 5707 5708 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW GENMASK(31, 16) 5709 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW_SET(x)\ 5710 FIELD_PREP(PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW, x) 5711 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW_GET(x)\ 5712 FIELD_GET(PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW, x) 5713 5714 /* SPARX5 ONLY */ 5715 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 */ 5716 #define PCEP_ADDR_UPR_OUT_0 \ 5717 __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 12, 0, 1, 4) 5718 5719 /* SPARX5 ONLY */ 5720 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_LIMIT_ADDR_OFF_OUTBOUND_0 */ 5721 #define PCEP_ADDR_LIM_OUT_0 \ 5722 __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 16, 0, 1, 4) 5723 5724 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW GENMASK(15, 0) 5725 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW_SET(x)\ 5726 FIELD_PREP(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW, x) 5727 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW_GET(x)\ 5728 FIELD_GET(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW, x) 5729 5730 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW GENMASK(31, 16) 5731 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW_SET(x)\ 5732 FIELD_PREP(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW, x) 5733 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW_GET(x)\ 5734 FIELD_GET(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW, x) 5735 5736 /* SPARX5 ONLY */ 5737 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 */ 5738 #define PCEP_ADDR_LWR_TGT_OUT_0 \ 5739 __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 20, 0, 1, 4) 5740 5741 /* SPARX5 ONLY */ 5742 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 */ 5743 #define PCEP_ADDR_UPR_TGT_OUT_0 \ 5744 __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 24, 0, 1, 4) 5745 5746 /* SPARX5 ONLY */ 5747 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0 */ 5748 #define PCEP_ADDR_UPR_LIM_OUT_0 \ 5749 __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 32, 0, 1, 4) 5750 5751 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW GENMASK(1, 0) 5752 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW_SET(x)\ 5753 FIELD_PREP(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW, x) 5754 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW_GET(x)\ 5755 FIELD_GET(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW, x) 5756 5757 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW GENMASK(31, 2) 5758 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW_SET(x)\ 5759 FIELD_PREP(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW, x) 5760 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW_GET(x)\ 5761 FIELD_GET(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW, x) 5762 5763 /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */ 5764 #define PCS10G_BR_PCS_CFG(t) \ 5765 __REG(TARGET_PCS10G_BR, t, regs->tsize[TC_PCS10G_BR], 0, 0, 1, 56, 0, \ 5766 0, 1, 4) 5767 5768 #define PCS10G_BR_PCS_CFG_PCS_ENA BIT(31) 5769 #define PCS10G_BR_PCS_CFG_PCS_ENA_SET(x)\ 5770 FIELD_PREP(PCS10G_BR_PCS_CFG_PCS_ENA, x) 5771 #define PCS10G_BR_PCS_CFG_PCS_ENA_GET(x)\ 5772 FIELD_GET(PCS10G_BR_PCS_CFG_PCS_ENA, x) 5773 5774 #define PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA BIT(30) 5775 #define PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\ 5776 FIELD_PREP(PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x) 5777 #define PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\ 5778 FIELD_GET(PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x) 5779 5780 #define PCS10G_BR_PCS_CFG_SH_CNT_MAX GENMASK(29, 24) 5781 #define PCS10G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\ 5782 FIELD_PREP(PCS10G_BR_PCS_CFG_SH_CNT_MAX, x) 5783 #define PCS10G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\ 5784 FIELD_GET(PCS10G_BR_PCS_CFG_SH_CNT_MAX, x) 5785 5786 #define PCS10G_BR_PCS_CFG_RX_DATA_FLIP BIT(18) 5787 #define PCS10G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\ 5788 FIELD_PREP(PCS10G_BR_PCS_CFG_RX_DATA_FLIP, x) 5789 #define PCS10G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\ 5790 FIELD_GET(PCS10G_BR_PCS_CFG_RX_DATA_FLIP, x) 5791 5792 #define PCS10G_BR_PCS_CFG_RESYNC_ENA BIT(15) 5793 #define PCS10G_BR_PCS_CFG_RESYNC_ENA_SET(x)\ 5794 FIELD_PREP(PCS10G_BR_PCS_CFG_RESYNC_ENA, x) 5795 #define PCS10G_BR_PCS_CFG_RESYNC_ENA_GET(x)\ 5796 FIELD_GET(PCS10G_BR_PCS_CFG_RESYNC_ENA, x) 5797 5798 #define PCS10G_BR_PCS_CFG_LF_GEN_DIS BIT(14) 5799 #define PCS10G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\ 5800 FIELD_PREP(PCS10G_BR_PCS_CFG_LF_GEN_DIS, x) 5801 #define PCS10G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\ 5802 FIELD_GET(PCS10G_BR_PCS_CFG_LF_GEN_DIS, x) 5803 5804 #define PCS10G_BR_PCS_CFG_RX_TEST_MODE BIT(13) 5805 #define PCS10G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\ 5806 FIELD_PREP(PCS10G_BR_PCS_CFG_RX_TEST_MODE, x) 5807 #define PCS10G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\ 5808 FIELD_GET(PCS10G_BR_PCS_CFG_RX_TEST_MODE, x) 5809 5810 #define PCS10G_BR_PCS_CFG_RX_SCR_DISABLE BIT(12) 5811 #define PCS10G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\ 5812 FIELD_PREP(PCS10G_BR_PCS_CFG_RX_SCR_DISABLE, x) 5813 #define PCS10G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\ 5814 FIELD_GET(PCS10G_BR_PCS_CFG_RX_SCR_DISABLE, x) 5815 5816 #define PCS10G_BR_PCS_CFG_TX_DATA_FLIP BIT(7) 5817 #define PCS10G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\ 5818 FIELD_PREP(PCS10G_BR_PCS_CFG_TX_DATA_FLIP, x) 5819 #define PCS10G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\ 5820 FIELD_GET(PCS10G_BR_PCS_CFG_TX_DATA_FLIP, x) 5821 5822 #define PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA BIT(6) 5823 #define PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\ 5824 FIELD_PREP(PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x) 5825 #define PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\ 5826 FIELD_GET(PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x) 5827 5828 #define PCS10G_BR_PCS_CFG_TX_TEST_MODE BIT(4) 5829 #define PCS10G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\ 5830 FIELD_PREP(PCS10G_BR_PCS_CFG_TX_TEST_MODE, x) 5831 #define PCS10G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\ 5832 FIELD_GET(PCS10G_BR_PCS_CFG_TX_TEST_MODE, x) 5833 5834 #define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE BIT(3) 5835 #define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\ 5836 FIELD_PREP(PCS10G_BR_PCS_CFG_TX_SCR_DISABLE, x) 5837 #define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\ 5838 FIELD_GET(PCS10G_BR_PCS_CFG_TX_SCR_DISABLE, x) 5839 5840 /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */ 5841 #define PCS10G_BR_PCS_SD_CFG(t) \ 5842 __REG(TARGET_PCS10G_BR, t, regs->tsize[TC_PCS10G_BR], 0, 0, 1, 56, 4, \ 5843 0, 1, 4) 5844 5845 #define PCS10G_BR_PCS_SD_CFG_SD_SEL BIT(8) 5846 #define PCS10G_BR_PCS_SD_CFG_SD_SEL_SET(x)\ 5847 FIELD_PREP(PCS10G_BR_PCS_SD_CFG_SD_SEL, x) 5848 #define PCS10G_BR_PCS_SD_CFG_SD_SEL_GET(x)\ 5849 FIELD_GET(PCS10G_BR_PCS_SD_CFG_SD_SEL, x) 5850 5851 #define PCS10G_BR_PCS_SD_CFG_SD_POL BIT(4) 5852 #define PCS10G_BR_PCS_SD_CFG_SD_POL_SET(x)\ 5853 FIELD_PREP(PCS10G_BR_PCS_SD_CFG_SD_POL, x) 5854 #define PCS10G_BR_PCS_SD_CFG_SD_POL_GET(x)\ 5855 FIELD_GET(PCS10G_BR_PCS_SD_CFG_SD_POL, x) 5856 5857 #define PCS10G_BR_PCS_SD_CFG_SD_ENA BIT(0) 5858 #define PCS10G_BR_PCS_SD_CFG_SD_ENA_SET(x)\ 5859 FIELD_PREP(PCS10G_BR_PCS_SD_CFG_SD_ENA, x) 5860 #define PCS10G_BR_PCS_SD_CFG_SD_ENA_GET(x)\ 5861 FIELD_GET(PCS10G_BR_PCS_SD_CFG_SD_ENA, x) 5862 5863 /* SPARX5 ONLY */ 5864 /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */ 5865 #define PCS25G_BR_PCS_CFG(t) \ 5866 __REG(TARGET_PCS25G_BR, t, 8, 0, 0, 1, 56, 0, 0, 1, 4) 5867 5868 #define PCS25G_BR_PCS_CFG_PCS_ENA BIT(31) 5869 #define PCS25G_BR_PCS_CFG_PCS_ENA_SET(x)\ 5870 FIELD_PREP(PCS25G_BR_PCS_CFG_PCS_ENA, x) 5871 #define PCS25G_BR_PCS_CFG_PCS_ENA_GET(x)\ 5872 FIELD_GET(PCS25G_BR_PCS_CFG_PCS_ENA, x) 5873 5874 #define PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA BIT(30) 5875 #define PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\ 5876 FIELD_PREP(PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x) 5877 #define PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\ 5878 FIELD_GET(PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x) 5879 5880 #define PCS25G_BR_PCS_CFG_SH_CNT_MAX GENMASK(29, 24) 5881 #define PCS25G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\ 5882 FIELD_PREP(PCS25G_BR_PCS_CFG_SH_CNT_MAX, x) 5883 #define PCS25G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\ 5884 FIELD_GET(PCS25G_BR_PCS_CFG_SH_CNT_MAX, x) 5885 5886 #define PCS25G_BR_PCS_CFG_RX_DATA_FLIP BIT(18) 5887 #define PCS25G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\ 5888 FIELD_PREP(PCS25G_BR_PCS_CFG_RX_DATA_FLIP, x) 5889 #define PCS25G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\ 5890 FIELD_GET(PCS25G_BR_PCS_CFG_RX_DATA_FLIP, x) 5891 5892 #define PCS25G_BR_PCS_CFG_RESYNC_ENA BIT(15) 5893 #define PCS25G_BR_PCS_CFG_RESYNC_ENA_SET(x)\ 5894 FIELD_PREP(PCS25G_BR_PCS_CFG_RESYNC_ENA, x) 5895 #define PCS25G_BR_PCS_CFG_RESYNC_ENA_GET(x)\ 5896 FIELD_GET(PCS25G_BR_PCS_CFG_RESYNC_ENA, x) 5897 5898 #define PCS25G_BR_PCS_CFG_LF_GEN_DIS BIT(14) 5899 #define PCS25G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\ 5900 FIELD_PREP(PCS25G_BR_PCS_CFG_LF_GEN_DIS, x) 5901 #define PCS25G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\ 5902 FIELD_GET(PCS25G_BR_PCS_CFG_LF_GEN_DIS, x) 5903 5904 #define PCS25G_BR_PCS_CFG_RX_TEST_MODE BIT(13) 5905 #define PCS25G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\ 5906 FIELD_PREP(PCS25G_BR_PCS_CFG_RX_TEST_MODE, x) 5907 #define PCS25G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\ 5908 FIELD_GET(PCS25G_BR_PCS_CFG_RX_TEST_MODE, x) 5909 5910 #define PCS25G_BR_PCS_CFG_RX_SCR_DISABLE BIT(12) 5911 #define PCS25G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\ 5912 FIELD_PREP(PCS25G_BR_PCS_CFG_RX_SCR_DISABLE, x) 5913 #define PCS25G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\ 5914 FIELD_GET(PCS25G_BR_PCS_CFG_RX_SCR_DISABLE, x) 5915 5916 #define PCS25G_BR_PCS_CFG_TX_DATA_FLIP BIT(7) 5917 #define PCS25G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\ 5918 FIELD_PREP(PCS25G_BR_PCS_CFG_TX_DATA_FLIP, x) 5919 #define PCS25G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\ 5920 FIELD_GET(PCS25G_BR_PCS_CFG_TX_DATA_FLIP, x) 5921 5922 #define PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA BIT(6) 5923 #define PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\ 5924 FIELD_PREP(PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x) 5925 #define PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\ 5926 FIELD_GET(PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x) 5927 5928 #define PCS25G_BR_PCS_CFG_TX_TEST_MODE BIT(4) 5929 #define PCS25G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\ 5930 FIELD_PREP(PCS25G_BR_PCS_CFG_TX_TEST_MODE, x) 5931 #define PCS25G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\ 5932 FIELD_GET(PCS25G_BR_PCS_CFG_TX_TEST_MODE, x) 5933 5934 #define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE BIT(3) 5935 #define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\ 5936 FIELD_PREP(PCS25G_BR_PCS_CFG_TX_SCR_DISABLE, x) 5937 #define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\ 5938 FIELD_GET(PCS25G_BR_PCS_CFG_TX_SCR_DISABLE, x) 5939 5940 /* SPARX5 ONLY */ 5941 /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */ 5942 #define PCS25G_BR_PCS_SD_CFG(t) \ 5943 __REG(TARGET_PCS25G_BR, t, 8, 0, 0, 1, 56, 4, 0, 1, 4) 5944 5945 #define PCS25G_BR_PCS_SD_CFG_SD_SEL BIT(8) 5946 #define PCS25G_BR_PCS_SD_CFG_SD_SEL_SET(x)\ 5947 FIELD_PREP(PCS25G_BR_PCS_SD_CFG_SD_SEL, x) 5948 #define PCS25G_BR_PCS_SD_CFG_SD_SEL_GET(x)\ 5949 FIELD_GET(PCS25G_BR_PCS_SD_CFG_SD_SEL, x) 5950 5951 #define PCS25G_BR_PCS_SD_CFG_SD_POL BIT(4) 5952 #define PCS25G_BR_PCS_SD_CFG_SD_POL_SET(x)\ 5953 FIELD_PREP(PCS25G_BR_PCS_SD_CFG_SD_POL, x) 5954 #define PCS25G_BR_PCS_SD_CFG_SD_POL_GET(x)\ 5955 FIELD_GET(PCS25G_BR_PCS_SD_CFG_SD_POL, x) 5956 5957 #define PCS25G_BR_PCS_SD_CFG_SD_ENA BIT(0) 5958 #define PCS25G_BR_PCS_SD_CFG_SD_ENA_SET(x)\ 5959 FIELD_PREP(PCS25G_BR_PCS_SD_CFG_SD_ENA, x) 5960 #define PCS25G_BR_PCS_SD_CFG_SD_ENA_GET(x)\ 5961 FIELD_GET(PCS25G_BR_PCS_SD_CFG_SD_ENA, x) 5962 5963 /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */ 5964 #define PCS5G_BR_PCS_CFG(t) \ 5965 __REG(TARGET_PCS5G_BR, t, regs->tsize[TC_PCS5G_BR], 0, 0, 1, 56, 0, 0, \ 5966 1, 4) 5967 5968 #define PCS5G_BR_PCS_CFG_PCS_ENA BIT(31) 5969 #define PCS5G_BR_PCS_CFG_PCS_ENA_SET(x)\ 5970 FIELD_PREP(PCS5G_BR_PCS_CFG_PCS_ENA, x) 5971 #define PCS5G_BR_PCS_CFG_PCS_ENA_GET(x)\ 5972 FIELD_GET(PCS5G_BR_PCS_CFG_PCS_ENA, x) 5973 5974 #define PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA BIT(30) 5975 #define PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\ 5976 FIELD_PREP(PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x) 5977 #define PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\ 5978 FIELD_GET(PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x) 5979 5980 #define PCS5G_BR_PCS_CFG_SH_CNT_MAX GENMASK(29, 24) 5981 #define PCS5G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\ 5982 FIELD_PREP(PCS5G_BR_PCS_CFG_SH_CNT_MAX, x) 5983 #define PCS5G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\ 5984 FIELD_GET(PCS5G_BR_PCS_CFG_SH_CNT_MAX, x) 5985 5986 #define PCS5G_BR_PCS_CFG_RX_DATA_FLIP BIT(18) 5987 #define PCS5G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\ 5988 FIELD_PREP(PCS5G_BR_PCS_CFG_RX_DATA_FLIP, x) 5989 #define PCS5G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\ 5990 FIELD_GET(PCS5G_BR_PCS_CFG_RX_DATA_FLIP, x) 5991 5992 #define PCS5G_BR_PCS_CFG_RESYNC_ENA BIT(15) 5993 #define PCS5G_BR_PCS_CFG_RESYNC_ENA_SET(x)\ 5994 FIELD_PREP(PCS5G_BR_PCS_CFG_RESYNC_ENA, x) 5995 #define PCS5G_BR_PCS_CFG_RESYNC_ENA_GET(x)\ 5996 FIELD_GET(PCS5G_BR_PCS_CFG_RESYNC_ENA, x) 5997 5998 #define PCS5G_BR_PCS_CFG_LF_GEN_DIS BIT(14) 5999 #define PCS5G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\ 6000 FIELD_PREP(PCS5G_BR_PCS_CFG_LF_GEN_DIS, x) 6001 #define PCS5G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\ 6002 FIELD_GET(PCS5G_BR_PCS_CFG_LF_GEN_DIS, x) 6003 6004 #define PCS5G_BR_PCS_CFG_RX_TEST_MODE BIT(13) 6005 #define PCS5G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\ 6006 FIELD_PREP(PCS5G_BR_PCS_CFG_RX_TEST_MODE, x) 6007 #define PCS5G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\ 6008 FIELD_GET(PCS5G_BR_PCS_CFG_RX_TEST_MODE, x) 6009 6010 #define PCS5G_BR_PCS_CFG_RX_SCR_DISABLE BIT(12) 6011 #define PCS5G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\ 6012 FIELD_PREP(PCS5G_BR_PCS_CFG_RX_SCR_DISABLE, x) 6013 #define PCS5G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\ 6014 FIELD_GET(PCS5G_BR_PCS_CFG_RX_SCR_DISABLE, x) 6015 6016 #define PCS5G_BR_PCS_CFG_TX_DATA_FLIP BIT(7) 6017 #define PCS5G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\ 6018 FIELD_PREP(PCS5G_BR_PCS_CFG_TX_DATA_FLIP, x) 6019 #define PCS5G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\ 6020 FIELD_GET(PCS5G_BR_PCS_CFG_TX_DATA_FLIP, x) 6021 6022 #define PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA BIT(6) 6023 #define PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\ 6024 FIELD_PREP(PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x) 6025 #define PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\ 6026 FIELD_GET(PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x) 6027 6028 #define PCS5G_BR_PCS_CFG_TX_TEST_MODE BIT(4) 6029 #define PCS5G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\ 6030 FIELD_PREP(PCS5G_BR_PCS_CFG_TX_TEST_MODE, x) 6031 #define PCS5G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\ 6032 FIELD_GET(PCS5G_BR_PCS_CFG_TX_TEST_MODE, x) 6033 6034 #define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE BIT(3) 6035 #define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\ 6036 FIELD_PREP(PCS5G_BR_PCS_CFG_TX_SCR_DISABLE, x) 6037 #define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\ 6038 FIELD_GET(PCS5G_BR_PCS_CFG_TX_SCR_DISABLE, x) 6039 6040 /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */ 6041 #define PCS5G_BR_PCS_SD_CFG(t) \ 6042 __REG(TARGET_PCS5G_BR, t, regs->tsize[TC_PCS5G_BR], 0, 0, 1, 56, 4, 0, \ 6043 1, 4) 6044 6045 #define PCS5G_BR_PCS_SD_CFG_SD_SEL BIT(8) 6046 #define PCS5G_BR_PCS_SD_CFG_SD_SEL_SET(x)\ 6047 FIELD_PREP(PCS5G_BR_PCS_SD_CFG_SD_SEL, x) 6048 #define PCS5G_BR_PCS_SD_CFG_SD_SEL_GET(x)\ 6049 FIELD_GET(PCS5G_BR_PCS_SD_CFG_SD_SEL, x) 6050 6051 #define PCS5G_BR_PCS_SD_CFG_SD_POL BIT(4) 6052 #define PCS5G_BR_PCS_SD_CFG_SD_POL_SET(x)\ 6053 FIELD_PREP(PCS5G_BR_PCS_SD_CFG_SD_POL, x) 6054 #define PCS5G_BR_PCS_SD_CFG_SD_POL_GET(x)\ 6055 FIELD_GET(PCS5G_BR_PCS_SD_CFG_SD_POL, x) 6056 6057 #define PCS5G_BR_PCS_SD_CFG_SD_ENA BIT(0) 6058 #define PCS5G_BR_PCS_SD_CFG_SD_ENA_SET(x)\ 6059 FIELD_PREP(PCS5G_BR_PCS_SD_CFG_SD_ENA, x) 6060 #define PCS5G_BR_PCS_SD_CFG_SD_ENA_GET(x)\ 6061 FIELD_GET(PCS5G_BR_PCS_SD_CFG_SD_ENA, x) 6062 6063 /* PORT_CONF:HW_CFG:DEV5G_MODES */ 6064 #define PORT_CONF_DEV5G_MODES \ 6065 __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 0, 0, 1, 4) 6066 6067 /* SPARX5 ONLY */ 6068 #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE BIT(0) 6069 #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE_SET(x)\ 6070 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE, x) 6071 #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE_GET(x)\ 6072 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE, x) 6073 6074 /* SPARX5 ONLY */ 6075 #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE BIT(1) 6076 #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE_SET(x)\ 6077 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE, x) 6078 #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE_GET(x)\ 6079 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE, x) 6080 6081 /* SPARX5 ONLY */ 6082 #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE BIT(2) 6083 #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE_SET(x)\ 6084 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE, x) 6085 #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE_GET(x)\ 6086 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE, x) 6087 6088 /* SPARX5 ONLY */ 6089 #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE BIT(3) 6090 #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE_SET(x)\ 6091 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE, x) 6092 #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE_GET(x)\ 6093 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE, x) 6094 6095 /* SPARX5 ONLY */ 6096 #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE BIT(4) 6097 #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE_SET(x)\ 6098 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE, x) 6099 #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE_GET(x)\ 6100 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE, x) 6101 6102 /* SPARX5 ONLY */ 6103 #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE BIT(5) 6104 #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE_SET(x)\ 6105 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE, x) 6106 #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE_GET(x)\ 6107 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE, x) 6108 6109 /* SPARX5 ONLY */ 6110 #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE BIT(6) 6111 #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE_SET(x)\ 6112 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE, x) 6113 #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE_GET(x)\ 6114 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE, x) 6115 6116 /* SPARX5 ONLY */ 6117 #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE BIT(7) 6118 #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE_SET(x)\ 6119 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE, x) 6120 #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE_GET(x)\ 6121 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE, x) 6122 6123 /* SPARX5 ONLY */ 6124 #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE BIT(8) 6125 #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE_SET(x)\ 6126 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE, x) 6127 #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE_GET(x)\ 6128 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE, x) 6129 6130 #define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE BIT(9) 6131 #define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE_SET(x)\ 6132 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE, x) 6133 #define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE_GET(x)\ 6134 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE, x) 6135 6136 /* SPARX5 ONLY */ 6137 #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE BIT(10) 6138 #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE_SET(x)\ 6139 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE, x) 6140 #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE_GET(x)\ 6141 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE, x) 6142 6143 /* SPARX5 ONLY */ 6144 #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE BIT(11) 6145 #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE_SET(x)\ 6146 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE, x) 6147 #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE_GET(x)\ 6148 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE, x) 6149 6150 /* SPARX5 ONLY */ 6151 #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE BIT(12) 6152 #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_SET(x)\ 6153 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE, x) 6154 #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_GET(x)\ 6155 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE, x) 6156 6157 /* PORT_CONF:HW_CFG:DEV10G_MODES */ 6158 #define PORT_CONF_DEV10G_MODES \ 6159 __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 4, 0, 1, 4) 6160 6161 #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE BIT(0) 6162 #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE_SET(x)\ 6163 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE, x) 6164 #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE_GET(x)\ 6165 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE, x) 6166 6167 /* SPARX5 ONLY */ 6168 #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE BIT(1) 6169 #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE_SET(x)\ 6170 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE, x) 6171 #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE_GET(x)\ 6172 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE, x) 6173 6174 /* SPARX5 ONLY */ 6175 #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE BIT(2) 6176 #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE_SET(x)\ 6177 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE, x) 6178 #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE_GET(x)\ 6179 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE, x) 6180 6181 /* SPARX5 ONLY */ 6182 #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE BIT(3) 6183 #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE_SET(x)\ 6184 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE, x) 6185 #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE_GET(x)\ 6186 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE, x) 6187 6188 /* SPARX5 ONLY */ 6189 #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE BIT(4) 6190 #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE_SET(x)\ 6191 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE, x) 6192 #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE_GET(x)\ 6193 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE, x) 6194 6195 /* SPARX5 ONLY */ 6196 #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE BIT(5) 6197 #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE_SET(x)\ 6198 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE, x) 6199 #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE_GET(x)\ 6200 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE, x) 6201 6202 /* SPARX5 ONLY */ 6203 #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE BIT(6) 6204 #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE_SET(x)\ 6205 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE, x) 6206 #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE_GET(x)\ 6207 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE, x) 6208 6209 /* SPARX5 ONLY */ 6210 #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE BIT(7) 6211 #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE_SET(x)\ 6212 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE, x) 6213 #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE_GET(x)\ 6214 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE, x) 6215 6216 /* SPARX5 ONLY */ 6217 #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE BIT(8) 6218 #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE_SET(x)\ 6219 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE, x) 6220 #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE_GET(x)\ 6221 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE, x) 6222 6223 /* SPARX5 ONLY */ 6224 #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE BIT(9) 6225 #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE_SET(x)\ 6226 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE, x) 6227 #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE_GET(x)\ 6228 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE, x) 6229 6230 /* SPARX5 ONLY */ 6231 #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE BIT(10) 6232 #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE_SET(x)\ 6233 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE, x) 6234 #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE_GET(x)\ 6235 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE, x) 6236 6237 /* SPARX5 ONLY */ 6238 #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE BIT(11) 6239 #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE_SET(x)\ 6240 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE, x) 6241 #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE_GET(x)\ 6242 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE, x) 6243 6244 /* SPARX5 ONLY */ 6245 /* PORT_CONF:HW_CFG:DEV25G_MODES */ 6246 #define PORT_CONF_DEV25G_MODES \ 6247 __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 8, 0, 1, 4) 6248 6249 #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE BIT(0) 6250 #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE_SET(x)\ 6251 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE, x) 6252 #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE_GET(x)\ 6253 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE, x) 6254 6255 #define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE BIT(1) 6256 #define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE_SET(x)\ 6257 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE, x) 6258 #define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE_GET(x)\ 6259 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE, x) 6260 6261 #define PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE BIT(2) 6262 #define PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE_SET(x)\ 6263 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE, x) 6264 #define PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE_GET(x)\ 6265 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE, x) 6266 6267 #define PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE BIT(3) 6268 #define PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE_SET(x)\ 6269 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE, x) 6270 #define PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE_GET(x)\ 6271 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE, x) 6272 6273 #define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE BIT(4) 6274 #define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE_SET(x)\ 6275 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE, x) 6276 #define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE_GET(x)\ 6277 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE, x) 6278 6279 #define PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE BIT(5) 6280 #define PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE_SET(x)\ 6281 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE, x) 6282 #define PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE_GET(x)\ 6283 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE, x) 6284 6285 #define PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE BIT(6) 6286 #define PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE_SET(x)\ 6287 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE, x) 6288 #define PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE_GET(x)\ 6289 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE, x) 6290 6291 #define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE BIT(7) 6292 #define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE_SET(x)\ 6293 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE, x) 6294 #define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE_GET(x)\ 6295 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE, x) 6296 6297 /* PORT_CONF:HW_CFG:QSGMII_ENA */ 6298 #define PORT_CONF_QSGMII_ENA \ 6299 __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 12, 0, 1, 4) 6300 6301 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0 BIT(0) 6302 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0_SET(x)\ 6303 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_0, x) 6304 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0_GET(x)\ 6305 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_0, x) 6306 6307 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1 BIT(1) 6308 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1_SET(x)\ 6309 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_1, x) 6310 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1_GET(x)\ 6311 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_1, x) 6312 6313 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_2 BIT(2) 6314 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_2_SET(x)\ 6315 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_2, x) 6316 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_2_GET(x)\ 6317 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_2, x) 6318 6319 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_3 BIT(3) 6320 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_3_SET(x)\ 6321 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_3, x) 6322 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_3_GET(x)\ 6323 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_3, x) 6324 6325 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4 BIT(4) 6326 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4_SET(x)\ 6327 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_4, x) 6328 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4_GET(x)\ 6329 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_4, x) 6330 6331 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5 BIT(5) 6332 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5_SET(x)\ 6333 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_5, x) 6334 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5_GET(x)\ 6335 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_5, x) 6336 6337 /* SPARX5 ONLY */ 6338 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6 BIT(6) 6339 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6_SET(x)\ 6340 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_6, x) 6341 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6_GET(x)\ 6342 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_6, x) 6343 6344 /* SPARX5 ONLY */ 6345 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7 BIT(7) 6346 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7_SET(x)\ 6347 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_7, x) 6348 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7_GET(x)\ 6349 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_7, x) 6350 6351 /* SPARX5 ONLY */ 6352 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8 BIT(8) 6353 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8_SET(x)\ 6354 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_8, x) 6355 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8_GET(x)\ 6356 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_8, x) 6357 6358 /* SPARX5 ONLY */ 6359 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9 BIT(9) 6360 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9_SET(x)\ 6361 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_9, x) 6362 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9_GET(x)\ 6363 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_9, x) 6364 6365 /* SPARX5 ONLY */ 6366 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10 BIT(10) 6367 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10_SET(x)\ 6368 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_10, x) 6369 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10_GET(x)\ 6370 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_10, x) 6371 6372 /* SPARX5 ONLY */ 6373 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11 BIT(11) 6374 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11_SET(x)\ 6375 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_11, x) 6376 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11_GET(x)\ 6377 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_11, x) 6378 6379 /* SPARX5 ONLY */ 6380 /* PORT_CONF:USGMII_CFG_STAT:USGMII_CFG */ 6381 #define PORT_CONF_USGMII_CFG(g) \ 6382 __REG(TARGET_PORT_CONF, 0, 1, 72, g, 6, 8, 0, 0, 1, 4) 6383 6384 #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM BIT(9) 6385 #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM_SET(x)\ 6386 FIELD_PREP(PORT_CONF_USGMII_CFG_BYPASS_SCRAM, x) 6387 #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM_GET(x)\ 6388 FIELD_GET(PORT_CONF_USGMII_CFG_BYPASS_SCRAM, x) 6389 6390 #define PORT_CONF_USGMII_CFG_BYPASS_DESCRAM BIT(8) 6391 #define PORT_CONF_USGMII_CFG_BYPASS_DESCRAM_SET(x)\ 6392 FIELD_PREP(PORT_CONF_USGMII_CFG_BYPASS_DESCRAM, x) 6393 #define PORT_CONF_USGMII_CFG_BYPASS_DESCRAM_GET(x)\ 6394 FIELD_GET(PORT_CONF_USGMII_CFG_BYPASS_DESCRAM, x) 6395 6396 #define PORT_CONF_USGMII_CFG_FLIP_LANES BIT(7) 6397 #define PORT_CONF_USGMII_CFG_FLIP_LANES_SET(x)\ 6398 FIELD_PREP(PORT_CONF_USGMII_CFG_FLIP_LANES, x) 6399 #define PORT_CONF_USGMII_CFG_FLIP_LANES_GET(x)\ 6400 FIELD_GET(PORT_CONF_USGMII_CFG_FLIP_LANES, x) 6401 6402 #define PORT_CONF_USGMII_CFG_SHYST_DIS BIT(6) 6403 #define PORT_CONF_USGMII_CFG_SHYST_DIS_SET(x)\ 6404 FIELD_PREP(PORT_CONF_USGMII_CFG_SHYST_DIS, x) 6405 #define PORT_CONF_USGMII_CFG_SHYST_DIS_GET(x)\ 6406 FIELD_GET(PORT_CONF_USGMII_CFG_SHYST_DIS, x) 6407 6408 #define PORT_CONF_USGMII_CFG_E_DET_ENA BIT(5) 6409 #define PORT_CONF_USGMII_CFG_E_DET_ENA_SET(x)\ 6410 FIELD_PREP(PORT_CONF_USGMII_CFG_E_DET_ENA, x) 6411 #define PORT_CONF_USGMII_CFG_E_DET_ENA_GET(x)\ 6412 FIELD_GET(PORT_CONF_USGMII_CFG_E_DET_ENA, x) 6413 6414 #define PORT_CONF_USGMII_CFG_USE_I1_ENA BIT(4) 6415 #define PORT_CONF_USGMII_CFG_USE_I1_ENA_SET(x)\ 6416 FIELD_PREP(PORT_CONF_USGMII_CFG_USE_I1_ENA, x) 6417 #define PORT_CONF_USGMII_CFG_USE_I1_ENA_GET(x)\ 6418 FIELD_GET(PORT_CONF_USGMII_CFG_USE_I1_ENA, x) 6419 6420 #define PORT_CONF_USGMII_CFG_QUAD_MODE BIT(1) 6421 #define PORT_CONF_USGMII_CFG_QUAD_MODE_SET(x)\ 6422 FIELD_PREP(PORT_CONF_USGMII_CFG_QUAD_MODE, x) 6423 #define PORT_CONF_USGMII_CFG_QUAD_MODE_GET(x)\ 6424 FIELD_GET(PORT_CONF_USGMII_CFG_QUAD_MODE, x) 6425 6426 /* DEVCPU_PTP:PTP_CFG:PTP_PIN_INTR */ 6427 #define PTP_PTP_PIN_INTR \ 6428 __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_CFG], 0, 1, 16, 0, 0, 1,\ 6429 4) 6430 6431 #define PTP_PTP_PIN_INTR_INTR_PTP\ 6432 GENMASK(regs->fsize[FW_PTP_PTP_PIN_INTR_INTR_PTP] + 0 - 1, 0) 6433 #define PTP_PTP_PIN_INTR_INTR_PTP_SET(x)\ 6434 spx5_field_prep(PTP_PTP_PIN_INTR_INTR_PTP, x) 6435 #define PTP_PTP_PIN_INTR_INTR_PTP_GET(x)\ 6436 spx5_field_get(PTP_PTP_PIN_INTR_INTR_PTP, x) 6437 6438 /* DEVCPU_PTP:PTP_CFG:PTP_PIN_INTR_ENA */ 6439 #define PTP_PTP_PIN_INTR_ENA \ 6440 __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_CFG], 0, 1, 16, 4, 0, 1,\ 6441 4) 6442 6443 #define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA\ 6444 GENMASK(regs->fsize[FW_PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA] + 0 - 1, 0) 6445 #define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA_SET(x)\ 6446 spx5_field_prep(PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA, x) 6447 #define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA_GET(x)\ 6448 spx5_field_get(PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA, x) 6449 6450 /* DEVCPU_PTP:PTP_CFG:PTP_INTR_IDENT */ 6451 #define PTP_PTP_INTR_IDENT \ 6452 __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_CFG], 0, 1, 16, 8, 0, 1,\ 6453 4) 6454 6455 #define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT\ 6456 GENMASK(regs->fsize[FW_PTP_PTP_INTR_IDENT_INTR_PTP_IDENT] + 0 - 1, 0) 6457 #define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT_SET(x)\ 6458 spx5_field_prep(PTP_PTP_INTR_IDENT_INTR_PTP_IDENT, x) 6459 #define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT_GET(x)\ 6460 spx5_field_get(PTP_PTP_INTR_IDENT_INTR_PTP_IDENT, x) 6461 6462 /* DEVCPU_PTP:PTP_CFG:PTP_DOM_CFG */ 6463 #define PTP_PTP_DOM_CFG \ 6464 __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_CFG], 0, 1, 16, 12, 0, \ 6465 1, 4) 6466 6467 #define PTP_PTP_DOM_CFG_PTP_ENA GENMASK(11, 9) 6468 #define PTP_PTP_DOM_CFG_PTP_ENA_SET(x)\ 6469 FIELD_PREP(PTP_PTP_DOM_CFG_PTP_ENA, x) 6470 #define PTP_PTP_DOM_CFG_PTP_ENA_GET(x)\ 6471 FIELD_GET(PTP_PTP_DOM_CFG_PTP_ENA, x) 6472 6473 #define PTP_PTP_DOM_CFG_PTP_HOLD GENMASK(8, 6) 6474 #define PTP_PTP_DOM_CFG_PTP_HOLD_SET(x)\ 6475 FIELD_PREP(PTP_PTP_DOM_CFG_PTP_HOLD, x) 6476 #define PTP_PTP_DOM_CFG_PTP_HOLD_GET(x)\ 6477 FIELD_GET(PTP_PTP_DOM_CFG_PTP_HOLD, x) 6478 6479 #define PTP_PTP_DOM_CFG_PTP_TOD_FREEZE GENMASK(5, 3) 6480 #define PTP_PTP_DOM_CFG_PTP_TOD_FREEZE_SET(x)\ 6481 FIELD_PREP(PTP_PTP_DOM_CFG_PTP_TOD_FREEZE, x) 6482 #define PTP_PTP_DOM_CFG_PTP_TOD_FREEZE_GET(x)\ 6483 FIELD_GET(PTP_PTP_DOM_CFG_PTP_TOD_FREEZE, x) 6484 6485 #define PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS GENMASK(2, 0) 6486 #define PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_SET(x)\ 6487 FIELD_PREP(PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS, x) 6488 #define PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_GET(x)\ 6489 FIELD_GET(PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS, x) 6490 6491 /* DEVCPU_PTP:PTP_TOD_DOMAINS:CLK_PER_CFG */ 6492 #define PTP_CLK_PER_CFG(g, r) \ 6493 __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_TOD_DOMAINS], g, 3, 28, \ 6494 0, r, 2, 4) 6495 6496 /* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_NSEC */ 6497 #define PTP_PTP_CUR_NSEC(g) \ 6498 __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_TOD_DOMAINS], g, 3, 28, \ 6499 8, 0, 1, 4) 6500 6501 #define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC GENMASK(29, 0) 6502 #define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC_SET(x)\ 6503 FIELD_PREP(PTP_PTP_CUR_NSEC_PTP_CUR_NSEC, x) 6504 #define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC_GET(x)\ 6505 FIELD_GET(PTP_PTP_CUR_NSEC_PTP_CUR_NSEC, x) 6506 6507 /* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_NSEC_FRAC */ 6508 #define PTP_PTP_CUR_NSEC_FRAC(g) \ 6509 __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_TOD_DOMAINS], g, 3, 28, \ 6510 12, 0, 1, 4) 6511 6512 #define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC GENMASK(7, 0) 6513 #define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC_SET(x)\ 6514 FIELD_PREP(PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC, x) 6515 #define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC_GET(x)\ 6516 FIELD_GET(PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC, x) 6517 6518 /* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_SEC_LSB */ 6519 #define PTP_PTP_CUR_SEC_LSB(g) \ 6520 __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_TOD_DOMAINS], g, 3, 28, \ 6521 16, 0, 1, 4) 6522 6523 /* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_SEC_MSB */ 6524 #define PTP_PTP_CUR_SEC_MSB(g) \ 6525 __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_TOD_DOMAINS], g, 3, 28, \ 6526 20, 0, 1, 4) 6527 6528 #define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB GENMASK(15, 0) 6529 #define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB_SET(x)\ 6530 FIELD_PREP(PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB, x) 6531 #define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB_GET(x)\ 6532 FIELD_GET(PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB, x) 6533 6534 /* DEVCPU_PTP:PTP_TOD_DOMAINS:NTP_CUR_NSEC */ 6535 #define PTP_NTP_CUR_NSEC(g) \ 6536 __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_TOD_DOMAINS], g, 3, 28, \ 6537 24, 0, 1, 4) 6538 6539 /* DEVCPU_PTP:PTP_PINS:PTP_PIN_CFG */ 6540 #define PTP_PTP_PIN_CFG(g) \ 6541 __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 0, 0, 1,\ 6542 4) 6543 6544 #define PTP_PTP_PIN_CFG_PTP_PIN_ACTION\ 6545 GENMASK(regs->fpos[FP_PTP_PTP_PIN_CFG_PTP_PIN_ACTION] + 2, regs->fpos[FP_PTP_PTP_PIN_CFG_PTP_PIN_ACTION]) 6546 #define PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(x)\ 6547 spx5_field_prep(PTP_PTP_PIN_CFG_PTP_PIN_ACTION, x) 6548 #define PTP_PTP_PIN_CFG_PTP_PIN_ACTION_GET(x)\ 6549 spx5_field_get(PTP_PTP_PIN_CFG_PTP_PIN_ACTION, x) 6550 6551 #define PTP_PTP_PIN_CFG_PTP_PIN_SYNC\ 6552 GENMASK(regs->fpos[FP_PTP_PTP_PIN_CFG_PTP_PIN_SYNC] + 1, regs->fpos[FP_PTP_PTP_PIN_CFG_PTP_PIN_SYNC]) 6553 #define PTP_PTP_PIN_CFG_PTP_PIN_SYNC_SET(x)\ 6554 spx5_field_prep(PTP_PTP_PIN_CFG_PTP_PIN_SYNC, x) 6555 #define PTP_PTP_PIN_CFG_PTP_PIN_SYNC_GET(x)\ 6556 spx5_field_get(PTP_PTP_PIN_CFG_PTP_PIN_SYNC, x) 6557 6558 #define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL\ 6559 BIT(regs->fpos[FP_PTP_PTP_PIN_CFG_PTP_PIN_INV_POL]) 6560 #define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL_SET(x)\ 6561 spx5_field_prep(PTP_PTP_PIN_CFG_PTP_PIN_INV_POL, x) 6562 #define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL_GET(x)\ 6563 spx5_field_get(PTP_PTP_PIN_CFG_PTP_PIN_INV_POL, x) 6564 6565 #define PTP_PTP_PIN_CFG_PTP_PIN_SELECT\ 6566 GENMASK(regs->fsize[FW_PTP_PTP_PIN_CFG_PTP_PIN_SELECT] + 21 - 1, 21) 6567 #define PTP_PTP_PIN_CFG_PTP_PIN_SELECT_SET(x)\ 6568 spx5_field_prep(PTP_PTP_PIN_CFG_PTP_PIN_SELECT, x) 6569 #define PTP_PTP_PIN_CFG_PTP_PIN_SELECT_GET(x)\ 6570 spx5_field_get(PTP_PTP_PIN_CFG_PTP_PIN_SELECT, x) 6571 6572 #define PTP_PTP_PIN_CFG_PTP_CLK_SELECT GENMASK(20, 18) 6573 #define PTP_PTP_PIN_CFG_PTP_CLK_SELECT_SET(x)\ 6574 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_CLK_SELECT, x) 6575 #define PTP_PTP_PIN_CFG_PTP_CLK_SELECT_GET(x)\ 6576 FIELD_GET(PTP_PTP_PIN_CFG_PTP_CLK_SELECT, x) 6577 6578 #define PTP_PTP_PIN_CFG_PTP_PIN_DOM GENMASK(17, 16) 6579 #define PTP_PTP_PIN_CFG_PTP_PIN_DOM_SET(x)\ 6580 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_DOM, x) 6581 #define PTP_PTP_PIN_CFG_PTP_PIN_DOM_GET(x)\ 6582 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_DOM, x) 6583 6584 #define PTP_PTP_PIN_CFG_PTP_PIN_OPT GENMASK(15, 14) 6585 #define PTP_PTP_PIN_CFG_PTP_PIN_OPT_SET(x)\ 6586 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_OPT, x) 6587 #define PTP_PTP_PIN_CFG_PTP_PIN_OPT_GET(x)\ 6588 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_OPT, x) 6589 6590 #define PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK BIT(13) 6591 #define PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK_SET(x)\ 6592 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK, x) 6593 #define PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK_GET(x)\ 6594 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK, x) 6595 6596 #define PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS GENMASK(12, 0) 6597 #define PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS_SET(x)\ 6598 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS, x) 6599 #define PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS_GET(x)\ 6600 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS, x) 6601 6602 /* DEVCPU_PTP:PTP_PINS:PTP_TOD_SEC_MSB */ 6603 #define PTP_PTP_TOD_SEC_MSB(g) \ 6604 __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 4, 0, 1,\ 6605 4) 6606 6607 #define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB GENMASK(15, 0) 6608 #define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_SET(x)\ 6609 FIELD_PREP(PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB, x) 6610 #define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_GET(x)\ 6611 FIELD_GET(PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB, x) 6612 6613 /* DEVCPU_PTP:PTP_PINS:PTP_TOD_SEC_LSB */ 6614 #define PTP_PTP_TOD_SEC_LSB(g) \ 6615 __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 8, 0, 1,\ 6616 4) 6617 6618 /* DEVCPU_PTP:PTP_PINS:PTP_TOD_NSEC */ 6619 #define PTP_PTP_TOD_NSEC(g) \ 6620 __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 12, 0, \ 6621 1, 4) 6622 6623 #define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC GENMASK(29, 0) 6624 #define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_SET(x)\ 6625 FIELD_PREP(PTP_PTP_TOD_NSEC_PTP_TOD_NSEC, x) 6626 #define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_GET(x)\ 6627 FIELD_GET(PTP_PTP_TOD_NSEC_PTP_TOD_NSEC, x) 6628 6629 /* DEVCPU_PTP:PTP_PINS:PTP_TOD_NSEC_FRAC */ 6630 #define PTP_PTP_TOD_NSEC_FRAC(g) \ 6631 __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 16, 0, \ 6632 1, 4) 6633 6634 #define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC GENMASK(7, 0) 6635 #define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC_SET(x)\ 6636 FIELD_PREP(PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC, x) 6637 #define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC_GET(x)\ 6638 FIELD_GET(PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC, x) 6639 6640 /* DEVCPU_PTP:PTP_PINS:NTP_NSEC */ 6641 #define PTP_NTP_NSEC(g) \ 6642 __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 20, 0, \ 6643 1, 4) 6644 6645 /* DEVCPU_PTP:PTP_PINS:PIN_WF_HIGH_PERIOD */ 6646 #define PTP_PIN_WF_HIGH_PERIOD(g) \ 6647 __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 24, 0, \ 6648 1, 4) 6649 6650 #define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH GENMASK(29, 0) 6651 #define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH_SET(x)\ 6652 FIELD_PREP(PTP_PIN_WF_HIGH_PERIOD_PIN_WFH, x) 6653 #define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH_GET(x)\ 6654 FIELD_GET(PTP_PIN_WF_HIGH_PERIOD_PIN_WFH, x) 6655 6656 /* DEVCPU_PTP:PTP_PINS:PIN_WF_LOW_PERIOD */ 6657 #define PTP_PIN_WF_LOW_PERIOD(g) \ 6658 __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 28, 0, \ 6659 1, 4) 6660 6661 #define PTP_PIN_WF_LOW_PERIOD_PIN_WFL GENMASK(29, 0) 6662 #define PTP_PIN_WF_LOW_PERIOD_PIN_WFL_SET(x)\ 6663 FIELD_PREP(PTP_PIN_WF_LOW_PERIOD_PIN_WFL, x) 6664 #define PTP_PIN_WF_LOW_PERIOD_PIN_WFL_GET(x)\ 6665 FIELD_GET(PTP_PIN_WF_LOW_PERIOD_PIN_WFL, x) 6666 6667 /* DEVCPU_PTP:PTP_PINS:PIN_IOBOUNCH_DELAY */ 6668 #define PTP_PIN_IOBOUNCH_DELAY(g) \ 6669 __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 32, 0, \ 6670 1, 4) 6671 6672 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL GENMASK(18, 3) 6673 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL_SET(x)\ 6674 FIELD_PREP(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL, x) 6675 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL_GET(x)\ 6676 FIELD_GET(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL, x) 6677 6678 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG GENMASK(2, 0) 6679 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG_SET(x)\ 6680 FIELD_PREP(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG, x) 6681 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG_GET(x)\ 6682 FIELD_GET(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG, x) 6683 6684 /* DEVCPU_PTP:PHASE_DETECTOR_CTRL:PHAD_CTRL */ 6685 #define PTP_PHAD_CTRL(g) \ 6686 __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PHASE_DETECTOR_CTRL], g, \ 6687 regs->gcnt[GC_PTP_PHASE_DETECTOR_CTRL], \ 6688 regs->gsize[GW_PTP_PHASE_DETECTOR_CTRL], 0, 0, 1, 4) 6689 6690 #define PTP_PHAD_CTRL_PHAD_ENA\ 6691 BIT(regs->fpos[FP_PTP_PHAD_CTRL_PHAD_ENA]) 6692 #define PTP_PHAD_CTRL_PHAD_ENA_SET(x)\ 6693 spx5_field_prep(PTP_PHAD_CTRL_PHAD_ENA, x) 6694 #define PTP_PHAD_CTRL_PHAD_ENA_GET(x)\ 6695 spx5_field_get(PTP_PHAD_CTRL_PHAD_ENA, x) 6696 6697 #define PTP_PHAD_CTRL_PHAD_FAILED\ 6698 BIT(regs->fpos[FP_PTP_PHAD_CTRL_PHAD_FAILED]) 6699 #define PTP_PHAD_CTRL_PHAD_FAILED_SET(x)\ 6700 spx5_field_prep(PTP_PHAD_CTRL_PHAD_FAILED, x) 6701 #define PTP_PHAD_CTRL_PHAD_FAILED_GET(x)\ 6702 spx5_field_get(PTP_PHAD_CTRL_PHAD_FAILED, x) 6703 6704 /* SPARX5 ONLY */ 6705 #define PTP_PHAD_CTRL_REDUCED_RES GENMASK(5, 3) 6706 #define PTP_PHAD_CTRL_REDUCED_RES_SET(x)\ 6707 FIELD_PREP(PTP_PHAD_CTRL_REDUCED_RES, x) 6708 #define PTP_PHAD_CTRL_REDUCED_RES_GET(x)\ 6709 FIELD_GET(PTP_PHAD_CTRL_REDUCED_RES, x) 6710 6711 #define PTP_PHAD_CTRL_LOCK_ACC GENMASK(2, 0) 6712 #define PTP_PHAD_CTRL_LOCK_ACC_SET(x)\ 6713 FIELD_PREP(PTP_PHAD_CTRL_LOCK_ACC, x) 6714 #define PTP_PHAD_CTRL_LOCK_ACC_GET(x)\ 6715 FIELD_GET(PTP_PHAD_CTRL_LOCK_ACC, x) 6716 6717 /* DEVCPU_PTP:PHASE_DETECTOR_CTRL:PHAD_CYC_STAT */ 6718 #define PTP_PHAD_CYC_STAT(g) \ 6719 __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PHASE_DETECTOR_CTRL], g, \ 6720 regs->gcnt[GC_PTP_PHASE_DETECTOR_CTRL], \ 6721 regs->gsize[GW_PTP_PHASE_DETECTOR_CTRL], 4, 0, 1, 4) 6722 6723 /* QFWD:SYSTEM:SWITCH_PORT_MODE */ 6724 #define QFWD_SWITCH_PORT_MODE(r) \ 6725 __REG(TARGET_QFWD, 0, 1, 0, 0, 1, 340, 0, r, \ 6726 regs->rcnt[RC_QFWD_SWITCH_PORT_MODE], 4) 6727 6728 #define QFWD_SWITCH_PORT_MODE_PORT_ENA BIT(19) 6729 #define QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(x)\ 6730 FIELD_PREP(QFWD_SWITCH_PORT_MODE_PORT_ENA, x) 6731 #define QFWD_SWITCH_PORT_MODE_PORT_ENA_GET(x)\ 6732 FIELD_GET(QFWD_SWITCH_PORT_MODE_PORT_ENA, x) 6733 6734 #define QFWD_SWITCH_PORT_MODE_FWD_URGENCY GENMASK(18, 10) 6735 #define QFWD_SWITCH_PORT_MODE_FWD_URGENCY_SET(x)\ 6736 FIELD_PREP(QFWD_SWITCH_PORT_MODE_FWD_URGENCY, x) 6737 #define QFWD_SWITCH_PORT_MODE_FWD_URGENCY_GET(x)\ 6738 FIELD_GET(QFWD_SWITCH_PORT_MODE_FWD_URGENCY, x) 6739 6740 #define QFWD_SWITCH_PORT_MODE_YEL_RSRVD GENMASK(9, 6) 6741 #define QFWD_SWITCH_PORT_MODE_YEL_RSRVD_SET(x)\ 6742 FIELD_PREP(QFWD_SWITCH_PORT_MODE_YEL_RSRVD, x) 6743 #define QFWD_SWITCH_PORT_MODE_YEL_RSRVD_GET(x)\ 6744 FIELD_GET(QFWD_SWITCH_PORT_MODE_YEL_RSRVD, x) 6745 6746 #define QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE BIT(5) 6747 #define QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE_SET(x)\ 6748 FIELD_PREP(QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE, x) 6749 #define QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE_GET(x)\ 6750 FIELD_GET(QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE, x) 6751 6752 #define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING BIT(4) 6753 #define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING_SET(x)\ 6754 FIELD_PREP(QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING, x) 6755 #define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING_GET(x)\ 6756 FIELD_GET(QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING, x) 6757 6758 #define QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING BIT(3) 6759 #define QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING_SET(x)\ 6760 FIELD_PREP(QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING, x) 6761 #define QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING_GET(x)\ 6762 FIELD_GET(QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING, x) 6763 6764 #define QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE BIT(2) 6765 #define QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE_SET(x)\ 6766 FIELD_PREP(QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE, x) 6767 #define QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE_GET(x)\ 6768 FIELD_GET(QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE, x) 6769 6770 #define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS BIT(1) 6771 #define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS_SET(x)\ 6772 FIELD_PREP(QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS, x) 6773 #define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS_GET(x)\ 6774 FIELD_GET(QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS, x) 6775 6776 #define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE BIT(0) 6777 #define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE_SET(x)\ 6778 FIELD_PREP(QFWD_SWITCH_PORT_MODE_LEARNALL_MORE, x) 6779 #define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE_GET(x)\ 6780 FIELD_GET(QFWD_SWITCH_PORT_MODE_LEARNALL_MORE, x) 6781 6782 /* QFWD:SYSTEM:FRAME_COPY_CFG */ 6783 #define QFWD_FRAME_COPY_CFG(r) \ 6784 __REG(TARGET_QFWD, 0, 1, 0, 0, 1, 340, 284, r, 12, 4) 6785 6786 #define QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL\ 6787 GENMASK(regs->fsize[FW_QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL] + 6 - 1, 6) 6788 #define QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL_SET(x)\ 6789 spx5_field_prep(QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL, x) 6790 #define QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL_GET(x)\ 6791 spx5_field_get(QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL, x) 6792 6793 /* QRES:RES_CTRL:RES_CFG */ 6794 #define QRES_RES_CFG(g) \ 6795 __REG(TARGET_QRES, 0, 1, 0, g, 5120, 16, 0, 0, 1, 4) 6796 6797 #define QRES_RES_CFG_WM_HIGH\ 6798 GENMASK(regs->fsize[FW_QRES_RES_CFG_WM_HIGH] + 0 - 1, 0) 6799 #define QRES_RES_CFG_WM_HIGH_SET(x)\ 6800 spx5_field_prep(QRES_RES_CFG_WM_HIGH, x) 6801 #define QRES_RES_CFG_WM_HIGH_GET(x)\ 6802 spx5_field_get(QRES_RES_CFG_WM_HIGH, x) 6803 6804 /* QRES:RES_CTRL:RES_STAT */ 6805 #define QRES_RES_STAT(g) \ 6806 __REG(TARGET_QRES, 0, 1, 0, g, 5120, 16, 4, 0, 1, 4) 6807 6808 #define QRES_RES_STAT_MAXUSE\ 6809 GENMASK(regs->fsize[FW_QRES_RES_STAT_MAXUSE] + 0 - 1, 0) 6810 #define QRES_RES_STAT_MAXUSE_SET(x)\ 6811 spx5_field_prep(QRES_RES_STAT_MAXUSE, x) 6812 #define QRES_RES_STAT_MAXUSE_GET(x)\ 6813 spx5_field_get(QRES_RES_STAT_MAXUSE, x) 6814 6815 /* QRES:RES_CTRL:RES_STAT_CUR */ 6816 #define QRES_RES_STAT_CUR(g) \ 6817 __REG(TARGET_QRES, 0, 1, 0, g, 5120, 16, 8, 0, 1, 4) 6818 6819 #define QRES_RES_STAT_CUR_INUSE\ 6820 GENMASK(regs->fsize[FW_QRES_RES_STAT_CUR_INUSE] + 0 - 1, 0) 6821 #define QRES_RES_STAT_CUR_INUSE_SET(x)\ 6822 spx5_field_prep(QRES_RES_STAT_CUR_INUSE, x) 6823 #define QRES_RES_STAT_CUR_INUSE_GET(x)\ 6824 spx5_field_get(QRES_RES_STAT_CUR_INUSE, x) 6825 6826 /* DEVCPU_QS:XTR:XTR_GRP_CFG */ 6827 #define QS_XTR_GRP_CFG(r) \ 6828 __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 0, r, 2, 4) 6829 6830 #define QS_XTR_GRP_CFG_MODE GENMASK(3, 2) 6831 #define QS_XTR_GRP_CFG_MODE_SET(x)\ 6832 FIELD_PREP(QS_XTR_GRP_CFG_MODE, x) 6833 #define QS_XTR_GRP_CFG_MODE_GET(x)\ 6834 FIELD_GET(QS_XTR_GRP_CFG_MODE, x) 6835 6836 #define QS_XTR_GRP_CFG_STATUS_WORD_POS BIT(1) 6837 #define QS_XTR_GRP_CFG_STATUS_WORD_POS_SET(x)\ 6838 FIELD_PREP(QS_XTR_GRP_CFG_STATUS_WORD_POS, x) 6839 #define QS_XTR_GRP_CFG_STATUS_WORD_POS_GET(x)\ 6840 FIELD_GET(QS_XTR_GRP_CFG_STATUS_WORD_POS, x) 6841 6842 #define QS_XTR_GRP_CFG_BYTE_SWAP BIT(0) 6843 #define QS_XTR_GRP_CFG_BYTE_SWAP_SET(x)\ 6844 FIELD_PREP(QS_XTR_GRP_CFG_BYTE_SWAP, x) 6845 #define QS_XTR_GRP_CFG_BYTE_SWAP_GET(x)\ 6846 FIELD_GET(QS_XTR_GRP_CFG_BYTE_SWAP, x) 6847 6848 /* DEVCPU_QS:XTR:XTR_RD */ 6849 #define QS_XTR_RD(r) \ 6850 __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 8, r, 2, 4) 6851 6852 /* DEVCPU_QS:XTR:XTR_FLUSH */ 6853 #define QS_XTR_FLUSH \ 6854 __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 24, 0, 1, 4) 6855 6856 #define QS_XTR_FLUSH_FLUSH GENMASK(1, 0) 6857 #define QS_XTR_FLUSH_FLUSH_SET(x)\ 6858 FIELD_PREP(QS_XTR_FLUSH_FLUSH, x) 6859 #define QS_XTR_FLUSH_FLUSH_GET(x)\ 6860 FIELD_GET(QS_XTR_FLUSH_FLUSH, x) 6861 6862 /* DEVCPU_QS:XTR:XTR_DATA_PRESENT */ 6863 #define QS_XTR_DATA_PRESENT \ 6864 __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 28, 0, 1, 4) 6865 6866 #define QS_XTR_DATA_PRESENT_DATA_PRESENT GENMASK(1, 0) 6867 #define QS_XTR_DATA_PRESENT_DATA_PRESENT_SET(x)\ 6868 FIELD_PREP(QS_XTR_DATA_PRESENT_DATA_PRESENT, x) 6869 #define QS_XTR_DATA_PRESENT_DATA_PRESENT_GET(x)\ 6870 FIELD_GET(QS_XTR_DATA_PRESENT_DATA_PRESENT, x) 6871 6872 /* DEVCPU_QS:INJ:INJ_GRP_CFG */ 6873 #define QS_INJ_GRP_CFG(r) \ 6874 __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 0, r, 2, 4) 6875 6876 #define QS_INJ_GRP_CFG_MODE GENMASK(3, 2) 6877 #define QS_INJ_GRP_CFG_MODE_SET(x)\ 6878 FIELD_PREP(QS_INJ_GRP_CFG_MODE, x) 6879 #define QS_INJ_GRP_CFG_MODE_GET(x)\ 6880 FIELD_GET(QS_INJ_GRP_CFG_MODE, x) 6881 6882 #define QS_INJ_GRP_CFG_BYTE_SWAP BIT(0) 6883 #define QS_INJ_GRP_CFG_BYTE_SWAP_SET(x)\ 6884 FIELD_PREP(QS_INJ_GRP_CFG_BYTE_SWAP, x) 6885 #define QS_INJ_GRP_CFG_BYTE_SWAP_GET(x)\ 6886 FIELD_GET(QS_INJ_GRP_CFG_BYTE_SWAP, x) 6887 6888 /* DEVCPU_QS:INJ:INJ_WR */ 6889 #define QS_INJ_WR(r) \ 6890 __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 8, r, 2, 4) 6891 6892 /* DEVCPU_QS:INJ:INJ_CTRL */ 6893 #define QS_INJ_CTRL(r) \ 6894 __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 16, r, 2, 4) 6895 6896 #define QS_INJ_CTRL_GAP_SIZE GENMASK(24, 21) 6897 #define QS_INJ_CTRL_GAP_SIZE_SET(x)\ 6898 FIELD_PREP(QS_INJ_CTRL_GAP_SIZE, x) 6899 #define QS_INJ_CTRL_GAP_SIZE_GET(x)\ 6900 FIELD_GET(QS_INJ_CTRL_GAP_SIZE, x) 6901 6902 #define QS_INJ_CTRL_ABORT BIT(20) 6903 #define QS_INJ_CTRL_ABORT_SET(x)\ 6904 FIELD_PREP(QS_INJ_CTRL_ABORT, x) 6905 #define QS_INJ_CTRL_ABORT_GET(x)\ 6906 FIELD_GET(QS_INJ_CTRL_ABORT, x) 6907 6908 #define QS_INJ_CTRL_EOF BIT(19) 6909 #define QS_INJ_CTRL_EOF_SET(x)\ 6910 FIELD_PREP(QS_INJ_CTRL_EOF, x) 6911 #define QS_INJ_CTRL_EOF_GET(x)\ 6912 FIELD_GET(QS_INJ_CTRL_EOF, x) 6913 6914 #define QS_INJ_CTRL_SOF BIT(18) 6915 #define QS_INJ_CTRL_SOF_SET(x)\ 6916 FIELD_PREP(QS_INJ_CTRL_SOF, x) 6917 #define QS_INJ_CTRL_SOF_GET(x)\ 6918 FIELD_GET(QS_INJ_CTRL_SOF, x) 6919 6920 #define QS_INJ_CTRL_VLD_BYTES GENMASK(17, 16) 6921 #define QS_INJ_CTRL_VLD_BYTES_SET(x)\ 6922 FIELD_PREP(QS_INJ_CTRL_VLD_BYTES, x) 6923 #define QS_INJ_CTRL_VLD_BYTES_GET(x)\ 6924 FIELD_GET(QS_INJ_CTRL_VLD_BYTES, x) 6925 6926 /* DEVCPU_QS:INJ:INJ_STATUS */ 6927 #define QS_INJ_STATUS \ 6928 __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 24, 0, 1, 4) 6929 6930 #define QS_INJ_STATUS_WMARK_REACHED GENMASK(5, 4) 6931 #define QS_INJ_STATUS_WMARK_REACHED_SET(x)\ 6932 FIELD_PREP(QS_INJ_STATUS_WMARK_REACHED, x) 6933 #define QS_INJ_STATUS_WMARK_REACHED_GET(x)\ 6934 FIELD_GET(QS_INJ_STATUS_WMARK_REACHED, x) 6935 6936 #define QS_INJ_STATUS_FIFO_RDY GENMASK(3, 2) 6937 #define QS_INJ_STATUS_FIFO_RDY_SET(x)\ 6938 FIELD_PREP(QS_INJ_STATUS_FIFO_RDY, x) 6939 #define QS_INJ_STATUS_FIFO_RDY_GET(x)\ 6940 FIELD_GET(QS_INJ_STATUS_FIFO_RDY, x) 6941 6942 #define QS_INJ_STATUS_INJ_IN_PROGRESS GENMASK(1, 0) 6943 #define QS_INJ_STATUS_INJ_IN_PROGRESS_SET(x)\ 6944 FIELD_PREP(QS_INJ_STATUS_INJ_IN_PROGRESS, x) 6945 #define QS_INJ_STATUS_INJ_IN_PROGRESS_GET(x)\ 6946 FIELD_GET(QS_INJ_STATUS_INJ_IN_PROGRESS, x) 6947 6948 /* QSYS:PAUSE_CFG:PAUSE_CFG */ 6949 #define QSYS_PAUSE_CFG(r) \ 6950 __REG(TARGET_QSYS, 0, 1, 544, 0, 1, regs->gsize[GW_QSYS_PAUSE_CFG], 0, \ 6951 r, regs->rcnt[RC_QSYS_PAUSE_CFG], 4) 6952 6953 #define QSYS_PAUSE_CFG_PAUSE_START\ 6954 GENMASK(regs->fsize[FW_QSYS_PAUSE_CFG_PAUSE_START] + 14 - 1, 14) 6955 #define QSYS_PAUSE_CFG_PAUSE_START_SET(x)\ 6956 spx5_field_prep(QSYS_PAUSE_CFG_PAUSE_START, x) 6957 #define QSYS_PAUSE_CFG_PAUSE_START_GET(x)\ 6958 spx5_field_get(QSYS_PAUSE_CFG_PAUSE_START, x) 6959 6960 #define QSYS_PAUSE_CFG_PAUSE_STOP\ 6961 GENMASK(regs->fsize[FW_QSYS_PAUSE_CFG_PAUSE_STOP] + 2 - 1, 2) 6962 #define QSYS_PAUSE_CFG_PAUSE_STOP_SET(x)\ 6963 spx5_field_prep(QSYS_PAUSE_CFG_PAUSE_STOP, x) 6964 #define QSYS_PAUSE_CFG_PAUSE_STOP_GET(x)\ 6965 spx5_field_get(QSYS_PAUSE_CFG_PAUSE_STOP, x) 6966 6967 #define QSYS_PAUSE_CFG_PAUSE_ENA BIT(1) 6968 #define QSYS_PAUSE_CFG_PAUSE_ENA_SET(x)\ 6969 FIELD_PREP(QSYS_PAUSE_CFG_PAUSE_ENA, x) 6970 #define QSYS_PAUSE_CFG_PAUSE_ENA_GET(x)\ 6971 FIELD_GET(QSYS_PAUSE_CFG_PAUSE_ENA, x) 6972 6973 #define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA BIT(0) 6974 #define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA_SET(x)\ 6975 FIELD_PREP(QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA, x) 6976 #define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA_GET(x)\ 6977 FIELD_GET(QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA, x) 6978 6979 /* QSYS:PAUSE_CFG:ATOP */ 6980 #define QSYS_ATOP(r) \ 6981 __REG(TARGET_QSYS, 0, 1, 544, 0, 1, regs->gsize[GW_QSYS_PAUSE_CFG], \ 6982 284, r, regs->rcnt[RC_QSYS_ATOP], 4) 6983 6984 #define QSYS_ATOP_ATOP\ 6985 GENMASK(regs->fsize[FW_QSYS_ATOP_ATOP] + 0 - 1, 0) 6986 #define QSYS_ATOP_ATOP_SET(x)\ 6987 spx5_field_prep(QSYS_ATOP_ATOP, x) 6988 #define QSYS_ATOP_ATOP_GET(x)\ 6989 spx5_field_get(QSYS_ATOP_ATOP, x) 6990 6991 /* QSYS:PAUSE_CFG:FWD_PRESSURE */ 6992 #define QSYS_FWD_PRESSURE(r) \ 6993 __REG(TARGET_QSYS, 0, 1, 544, 0, 1, regs->gsize[GW_QSYS_PAUSE_CFG], \ 6994 564, r, regs->rcnt[RC_QSYS_FWD_PRESSURE], 4) 6995 6996 #define QSYS_FWD_PRESSURE_FWD_PRESSURE GENMASK(11, 1) 6997 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_SET(x)\ 6998 FIELD_PREP(QSYS_FWD_PRESSURE_FWD_PRESSURE, x) 6999 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_GET(x)\ 7000 FIELD_GET(QSYS_FWD_PRESSURE_FWD_PRESSURE, x) 7001 7002 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS BIT(0) 7003 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS_SET(x)\ 7004 FIELD_PREP(QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS, x) 7005 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS_GET(x)\ 7006 FIELD_GET(QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS, x) 7007 7008 /* QSYS:PAUSE_CFG:ATOP_TOT_CFG */ 7009 #define QSYS_ATOP_TOT_CFG \ 7010 __REG(TARGET_QSYS, 0, 1, 544, 0, 1, regs->gsize[GW_QSYS_PAUSE_CFG], \ 7011 844, 0, 1, 4) 7012 7013 #define QSYS_ATOP_TOT_CFG_ATOP_TOT\ 7014 GENMASK(regs->fsize[FW_QSYS_ATOP_TOT_CFG_ATOP_TOT] + 0 - 1, 0) 7015 #define QSYS_ATOP_TOT_CFG_ATOP_TOT_SET(x)\ 7016 spx5_field_prep(QSYS_ATOP_TOT_CFG_ATOP_TOT, x) 7017 #define QSYS_ATOP_TOT_CFG_ATOP_TOT_GET(x)\ 7018 spx5_field_get(QSYS_ATOP_TOT_CFG_ATOP_TOT, x) 7019 7020 /* QSYS:CALCFG:CAL_AUTO */ 7021 #define QSYS_CAL_AUTO(r) \ 7022 __REG(TARGET_QSYS, 0, 1, regs->gaddr[GA_QSYS_CALCFG], 0, 1, 40, 0, r, \ 7023 regs->rcnt[RC_QSYS_CAL_AUTO], 4) 7024 7025 #define QSYS_CAL_AUTO_CAL_AUTO GENMASK(29, 0) 7026 #define QSYS_CAL_AUTO_CAL_AUTO_SET(x)\ 7027 FIELD_PREP(QSYS_CAL_AUTO_CAL_AUTO, x) 7028 #define QSYS_CAL_AUTO_CAL_AUTO_GET(x)\ 7029 FIELD_GET(QSYS_CAL_AUTO_CAL_AUTO, x) 7030 7031 /* QSYS:CALCFG:CAL_CTRL */ 7032 #define QSYS_CAL_CTRL \ 7033 __REG(TARGET_QSYS, 0, 1, regs->gaddr[GA_QSYS_CALCFG], 0, 1, 40, 36, 0, \ 7034 1, 4) 7035 7036 #define QSYS_CAL_CTRL_CAL_MODE GENMASK(14, 11) 7037 #define QSYS_CAL_CTRL_CAL_MODE_SET(x)\ 7038 FIELD_PREP(QSYS_CAL_CTRL_CAL_MODE, x) 7039 #define QSYS_CAL_CTRL_CAL_MODE_GET(x)\ 7040 FIELD_GET(QSYS_CAL_CTRL_CAL_MODE, x) 7041 7042 #define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE GENMASK(10, 1) 7043 #define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE_SET(x)\ 7044 FIELD_PREP(QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE, x) 7045 #define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE_GET(x)\ 7046 FIELD_GET(QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE, x) 7047 7048 #define QSYS_CAL_CTRL_CAL_AUTO_ERROR BIT(0) 7049 #define QSYS_CAL_CTRL_CAL_AUTO_ERROR_SET(x)\ 7050 FIELD_PREP(QSYS_CAL_CTRL_CAL_AUTO_ERROR, x) 7051 #define QSYS_CAL_CTRL_CAL_AUTO_ERROR_GET(x)\ 7052 FIELD_GET(QSYS_CAL_CTRL_CAL_AUTO_ERROR, x) 7053 7054 /* QSYS:RAM_CTRL:RAM_INIT */ 7055 #define QSYS_RAM_INIT \ 7056 __REG(TARGET_QSYS, 0, 1, regs->gaddr[GA_QSYS_RAM_CTRL], 0, 1, 4, 0, 0, \ 7057 1, 4) 7058 7059 #define QSYS_RAM_INIT_RAM_INIT BIT(1) 7060 #define QSYS_RAM_INIT_RAM_INIT_SET(x)\ 7061 FIELD_PREP(QSYS_RAM_INIT_RAM_INIT, x) 7062 #define QSYS_RAM_INIT_RAM_INIT_GET(x)\ 7063 FIELD_GET(QSYS_RAM_INIT_RAM_INIT, x) 7064 7065 #define QSYS_RAM_INIT_RAM_CFG_HOOK BIT(0) 7066 #define QSYS_RAM_INIT_RAM_CFG_HOOK_SET(x)\ 7067 FIELD_PREP(QSYS_RAM_INIT_RAM_CFG_HOOK, x) 7068 #define QSYS_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 7069 FIELD_GET(QSYS_RAM_INIT_RAM_CFG_HOOK, x) 7070 7071 /* REW:COMMON:OWN_UPSID */ 7072 #define REW_OWN_UPSID(r) \ 7073 __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_COMMON], 0, 1, 1232, 0, r, \ 7074 regs->rcnt[RC_REW_OWN_UPSID], 4) 7075 7076 #define REW_OWN_UPSID_OWN_UPSID GENMASK(4, 0) 7077 #define REW_OWN_UPSID_OWN_UPSID_SET(x)\ 7078 FIELD_PREP(REW_OWN_UPSID_OWN_UPSID, x) 7079 #define REW_OWN_UPSID_OWN_UPSID_GET(x)\ 7080 FIELD_GET(REW_OWN_UPSID_OWN_UPSID, x) 7081 7082 /* REW:COMMON:RTAG_ETAG_CTRL */ 7083 #define REW_RTAG_ETAG_CTRL(r) \ 7084 __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_COMMON], 0, 1, 1232, 560, r,\ 7085 regs->rcnt[RC_REW_RTAG_ETAG_CTRL], 4) 7086 7087 #define REW_RTAG_ETAG_CTRL_IPE_TBL\ 7088 GENMASK(regs->fsize[FW_REW_RTAG_ETAG_CTRL_IPE_TBL] + 3 - 1, 3) 7089 #define REW_RTAG_ETAG_CTRL_IPE_TBL_SET(x)\ 7090 spx5_field_prep(REW_RTAG_ETAG_CTRL_IPE_TBL, x) 7091 #define REW_RTAG_ETAG_CTRL_IPE_TBL_GET(x)\ 7092 spx5_field_get(REW_RTAG_ETAG_CTRL_IPE_TBL, x) 7093 7094 #define REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA GENMASK(2, 1) 7095 #define REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA_SET(x)\ 7096 FIELD_PREP(REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA, x) 7097 #define REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA_GET(x)\ 7098 FIELD_GET(REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA, x) 7099 7100 #define REW_RTAG_ETAG_CTRL_KEEP_ETAG BIT(0) 7101 #define REW_RTAG_ETAG_CTRL_KEEP_ETAG_SET(x)\ 7102 FIELD_PREP(REW_RTAG_ETAG_CTRL_KEEP_ETAG, x) 7103 #define REW_RTAG_ETAG_CTRL_KEEP_ETAG_GET(x)\ 7104 FIELD_GET(REW_RTAG_ETAG_CTRL_KEEP_ETAG, x) 7105 7106 /* REW:COMMON:ES0_CTRL */ 7107 #define REW_ES0_CTRL \ 7108 __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_COMMON], 0, 1, 1232, 852, 0,\ 7109 1, 4) 7110 7111 #define REW_ES0_CTRL_ES0_BY_RT_FWD BIT(5) 7112 #define REW_ES0_CTRL_ES0_BY_RT_FWD_SET(x)\ 7113 FIELD_PREP(REW_ES0_CTRL_ES0_BY_RT_FWD, x) 7114 #define REW_ES0_CTRL_ES0_BY_RT_FWD_GET(x)\ 7115 FIELD_GET(REW_ES0_CTRL_ES0_BY_RT_FWD, x) 7116 7117 #define REW_ES0_CTRL_ES0_BY_RLEG BIT(4) 7118 #define REW_ES0_CTRL_ES0_BY_RLEG_SET(x)\ 7119 FIELD_PREP(REW_ES0_CTRL_ES0_BY_RLEG, x) 7120 #define REW_ES0_CTRL_ES0_BY_RLEG_GET(x)\ 7121 FIELD_GET(REW_ES0_CTRL_ES0_BY_RLEG, x) 7122 7123 #define REW_ES0_CTRL_ES0_DPORT_ENA BIT(3) 7124 #define REW_ES0_CTRL_ES0_DPORT_ENA_SET(x)\ 7125 FIELD_PREP(REW_ES0_CTRL_ES0_DPORT_ENA, x) 7126 #define REW_ES0_CTRL_ES0_DPORT_ENA_GET(x)\ 7127 FIELD_GET(REW_ES0_CTRL_ES0_DPORT_ENA, x) 7128 7129 #define REW_ES0_CTRL_ES0_FRM_LBK_CFG BIT(2) 7130 #define REW_ES0_CTRL_ES0_FRM_LBK_CFG_SET(x)\ 7131 FIELD_PREP(REW_ES0_CTRL_ES0_FRM_LBK_CFG, x) 7132 #define REW_ES0_CTRL_ES0_FRM_LBK_CFG_GET(x)\ 7133 FIELD_GET(REW_ES0_CTRL_ES0_FRM_LBK_CFG, x) 7134 7135 #define REW_ES0_CTRL_ES0_VD2_ENCAP_ID_ENA BIT(1) 7136 #define REW_ES0_CTRL_ES0_VD2_ENCAP_ID_ENA_SET(x)\ 7137 FIELD_PREP(REW_ES0_CTRL_ES0_VD2_ENCAP_ID_ENA, x) 7138 #define REW_ES0_CTRL_ES0_VD2_ENCAP_ID_ENA_GET(x)\ 7139 FIELD_GET(REW_ES0_CTRL_ES0_VD2_ENCAP_ID_ENA, x) 7140 7141 #define REW_ES0_CTRL_ES0_LU_ENA BIT(0) 7142 #define REW_ES0_CTRL_ES0_LU_ENA_SET(x)\ 7143 FIELD_PREP(REW_ES0_CTRL_ES0_LU_ENA, x) 7144 #define REW_ES0_CTRL_ES0_LU_ENA_GET(x)\ 7145 FIELD_GET(REW_ES0_CTRL_ES0_LU_ENA, x) 7146 7147 /* REW:PORT:PORT_VLAN_CFG */ 7148 #define REW_PORT_VLAN_CFG(g) \ 7149 __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g, \ 7150 regs->gcnt[GC_REW_PORT], 256, 0, 0, 1, 4) 7151 7152 #define REW_PORT_VLAN_CFG_PORT_PCP GENMASK(15, 13) 7153 #define REW_PORT_VLAN_CFG_PORT_PCP_SET(x)\ 7154 FIELD_PREP(REW_PORT_VLAN_CFG_PORT_PCP, x) 7155 #define REW_PORT_VLAN_CFG_PORT_PCP_GET(x)\ 7156 FIELD_GET(REW_PORT_VLAN_CFG_PORT_PCP, x) 7157 7158 #define REW_PORT_VLAN_CFG_PORT_DEI BIT(12) 7159 #define REW_PORT_VLAN_CFG_PORT_DEI_SET(x)\ 7160 FIELD_PREP(REW_PORT_VLAN_CFG_PORT_DEI, x) 7161 #define REW_PORT_VLAN_CFG_PORT_DEI_GET(x)\ 7162 FIELD_GET(REW_PORT_VLAN_CFG_PORT_DEI, x) 7163 7164 #define REW_PORT_VLAN_CFG_PORT_VID GENMASK(11, 0) 7165 #define REW_PORT_VLAN_CFG_PORT_VID_SET(x)\ 7166 FIELD_PREP(REW_PORT_VLAN_CFG_PORT_VID, x) 7167 #define REW_PORT_VLAN_CFG_PORT_VID_GET(x)\ 7168 FIELD_GET(REW_PORT_VLAN_CFG_PORT_VID, x) 7169 7170 /* REW:PORT:PCP_MAP_DE0 */ 7171 #define REW_PCP_MAP_DE0(g, r) \ 7172 __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g, \ 7173 regs->gcnt[GC_REW_PORT], 256, 4, r, 8, 4) 7174 7175 #define REW_PCP_MAP_DE0_PCP_DE0 GENMASK(2, 0) 7176 #define REW_PCP_MAP_DE0_PCP_DE0_SET(x)\ 7177 FIELD_PREP(REW_PCP_MAP_DE0_PCP_DE0, x) 7178 #define REW_PCP_MAP_DE0_PCP_DE0_GET(x)\ 7179 FIELD_GET(REW_PCP_MAP_DE0_PCP_DE0, x) 7180 7181 /* REW:PORT:PCP_MAP_DE1 */ 7182 #define REW_PCP_MAP_DE1(g, r) \ 7183 __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g, \ 7184 regs->gcnt[GC_REW_PORT], 256, 36, r, 8, 4) 7185 7186 #define REW_PCP_MAP_DE1_PCP_DE1 GENMASK(2, 0) 7187 #define REW_PCP_MAP_DE1_PCP_DE1_SET(x)\ 7188 FIELD_PREP(REW_PCP_MAP_DE1_PCP_DE1, x) 7189 #define REW_PCP_MAP_DE1_PCP_DE1_GET(x)\ 7190 FIELD_GET(REW_PCP_MAP_DE1_PCP_DE1, x) 7191 7192 /* REW:PORT:DEI_MAP_DE0 */ 7193 #define REW_DEI_MAP_DE0(g, r) \ 7194 __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g, \ 7195 regs->gcnt[GC_REW_PORT], 256, 68, r, 8, 4) 7196 7197 #define REW_DEI_MAP_DE0_DEI_DE0 BIT(0) 7198 #define REW_DEI_MAP_DE0_DEI_DE0_SET(x)\ 7199 FIELD_PREP(REW_DEI_MAP_DE0_DEI_DE0, x) 7200 #define REW_DEI_MAP_DE0_DEI_DE0_GET(x)\ 7201 FIELD_GET(REW_DEI_MAP_DE0_DEI_DE0, x) 7202 7203 /* REW:PORT:DEI_MAP_DE1 */ 7204 #define REW_DEI_MAP_DE1(g, r) \ 7205 __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g, \ 7206 regs->gcnt[GC_REW_PORT], 256, 100, r, 8, 4) 7207 7208 #define REW_DEI_MAP_DE1_DEI_DE1 BIT(0) 7209 #define REW_DEI_MAP_DE1_DEI_DE1_SET(x)\ 7210 FIELD_PREP(REW_DEI_MAP_DE1_DEI_DE1, x) 7211 #define REW_DEI_MAP_DE1_DEI_DE1_GET(x)\ 7212 FIELD_GET(REW_DEI_MAP_DE1_DEI_DE1, x) 7213 7214 /* REW:PORT:TAG_CTRL */ 7215 #define REW_TAG_CTRL(g) \ 7216 __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g, \ 7217 regs->gcnt[GC_REW_PORT], 256, 132, 0, 1, 4) 7218 7219 #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED BIT(13) 7220 #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED_SET(x)\ 7221 FIELD_PREP(REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED, x) 7222 #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED_GET(x)\ 7223 FIELD_GET(REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED, x) 7224 7225 #define REW_TAG_CTRL_TAG_CFG GENMASK(12, 11) 7226 #define REW_TAG_CTRL_TAG_CFG_SET(x)\ 7227 FIELD_PREP(REW_TAG_CTRL_TAG_CFG, x) 7228 #define REW_TAG_CTRL_TAG_CFG_GET(x)\ 7229 FIELD_GET(REW_TAG_CTRL_TAG_CFG, x) 7230 7231 #define REW_TAG_CTRL_TAG_TPID_CFG GENMASK(10, 8) 7232 #define REW_TAG_CTRL_TAG_TPID_CFG_SET(x)\ 7233 FIELD_PREP(REW_TAG_CTRL_TAG_TPID_CFG, x) 7234 #define REW_TAG_CTRL_TAG_TPID_CFG_GET(x)\ 7235 FIELD_GET(REW_TAG_CTRL_TAG_TPID_CFG, x) 7236 7237 #define REW_TAG_CTRL_TAG_VID_CFG GENMASK(7, 6) 7238 #define REW_TAG_CTRL_TAG_VID_CFG_SET(x)\ 7239 FIELD_PREP(REW_TAG_CTRL_TAG_VID_CFG, x) 7240 #define REW_TAG_CTRL_TAG_VID_CFG_GET(x)\ 7241 FIELD_GET(REW_TAG_CTRL_TAG_VID_CFG, x) 7242 7243 #define REW_TAG_CTRL_TAG_PCP_CFG GENMASK(5, 3) 7244 #define REW_TAG_CTRL_TAG_PCP_CFG_SET(x)\ 7245 FIELD_PREP(REW_TAG_CTRL_TAG_PCP_CFG, x) 7246 #define REW_TAG_CTRL_TAG_PCP_CFG_GET(x)\ 7247 FIELD_GET(REW_TAG_CTRL_TAG_PCP_CFG, x) 7248 7249 #define REW_TAG_CTRL_TAG_DEI_CFG GENMASK(2, 0) 7250 #define REW_TAG_CTRL_TAG_DEI_CFG_SET(x)\ 7251 FIELD_PREP(REW_TAG_CTRL_TAG_DEI_CFG, x) 7252 #define REW_TAG_CTRL_TAG_DEI_CFG_GET(x)\ 7253 FIELD_GET(REW_TAG_CTRL_TAG_DEI_CFG, x) 7254 7255 /* REW:PORT:DSCP_MAP */ 7256 #define REW_DSCP_MAP(g) \ 7257 __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g, \ 7258 regs->gcnt[GC_REW_PORT], 256, 136, 0, 1, 4) 7259 7260 #define REW_DSCP_MAP_DSCP_UPDATE_ENA BIT(1) 7261 #define REW_DSCP_MAP_DSCP_UPDATE_ENA_SET(x)\ 7262 FIELD_PREP(REW_DSCP_MAP_DSCP_UPDATE_ENA, x) 7263 #define REW_DSCP_MAP_DSCP_UPDATE_ENA_GET(x)\ 7264 FIELD_GET(REW_DSCP_MAP_DSCP_UPDATE_ENA, x) 7265 7266 #define REW_DSCP_MAP_DSCP_REMAP_ENA BIT(0) 7267 #define REW_DSCP_MAP_DSCP_REMAP_ENA_SET(x)\ 7268 FIELD_PREP(REW_DSCP_MAP_DSCP_REMAP_ENA, x) 7269 #define REW_DSCP_MAP_DSCP_REMAP_ENA_GET(x)\ 7270 FIELD_GET(REW_DSCP_MAP_DSCP_REMAP_ENA, x) 7271 7272 /* SPARX5 ONLY */ 7273 /* REW:PTP_CTRL:PTP_TWOSTEP_CTRL */ 7274 #define REW_PTP_TWOSTEP_CTRL \ 7275 __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 0, 0, 1, 4) 7276 7277 #define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA BIT(12) 7278 #define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_SET(x)\ 7279 FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA, x) 7280 #define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_GET(x)\ 7281 FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA, x) 7282 7283 #define REW_PTP_TWOSTEP_CTRL_PTP_NXT BIT(11) 7284 #define REW_PTP_TWOSTEP_CTRL_PTP_NXT_SET(x)\ 7285 FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_NXT, x) 7286 #define REW_PTP_TWOSTEP_CTRL_PTP_NXT_GET(x)\ 7287 FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_NXT, x) 7288 7289 #define REW_PTP_TWOSTEP_CTRL_PTP_VLD BIT(10) 7290 #define REW_PTP_TWOSTEP_CTRL_PTP_VLD_SET(x)\ 7291 FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_VLD, x) 7292 #define REW_PTP_TWOSTEP_CTRL_PTP_VLD_GET(x)\ 7293 FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_VLD, x) 7294 7295 #define REW_PTP_TWOSTEP_CTRL_STAMP_TX BIT(9) 7296 #define REW_PTP_TWOSTEP_CTRL_STAMP_TX_SET(x)\ 7297 FIELD_PREP(REW_PTP_TWOSTEP_CTRL_STAMP_TX, x) 7298 #define REW_PTP_TWOSTEP_CTRL_STAMP_TX_GET(x)\ 7299 FIELD_GET(REW_PTP_TWOSTEP_CTRL_STAMP_TX, x) 7300 7301 #define REW_PTP_TWOSTEP_CTRL_STAMP_PORT GENMASK(8, 1) 7302 #define REW_PTP_TWOSTEP_CTRL_STAMP_PORT_SET(x)\ 7303 FIELD_PREP(REW_PTP_TWOSTEP_CTRL_STAMP_PORT, x) 7304 #define REW_PTP_TWOSTEP_CTRL_STAMP_PORT_GET(x)\ 7305 FIELD_GET(REW_PTP_TWOSTEP_CTRL_STAMP_PORT, x) 7306 7307 #define REW_PTP_TWOSTEP_CTRL_PTP_OVFL BIT(0) 7308 #define REW_PTP_TWOSTEP_CTRL_PTP_OVFL_SET(x)\ 7309 FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_OVFL, x) 7310 #define REW_PTP_TWOSTEP_CTRL_PTP_OVFL_GET(x)\ 7311 FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_OVFL, x) 7312 7313 /* SPARX5 ONLY */ 7314 /* REW:PTP_CTRL:PTP_TWOSTEP_STAMP */ 7315 #define REW_PTP_TWOSTEP_STAMP \ 7316 __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 4, 0, 1, 4) 7317 7318 #define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC GENMASK(29, 0) 7319 #define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC_SET(x)\ 7320 FIELD_PREP(REW_PTP_TWOSTEP_STAMP_STAMP_NSEC, x) 7321 #define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC_GET(x)\ 7322 FIELD_GET(REW_PTP_TWOSTEP_STAMP_STAMP_NSEC, x) 7323 7324 /* SPARX5 ONLY */ 7325 /* REW:PTP_CTRL:PTP_TWOSTEP_STAMP_SUBNS */ 7326 #define REW_PTP_TWOSTEP_STAMP_SUBNS \ 7327 __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 8, 0, 1, 4) 7328 7329 #define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC GENMASK(7, 0) 7330 #define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC_SET(x)\ 7331 FIELD_PREP(REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC, x) 7332 #define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC_GET(x)\ 7333 FIELD_GET(REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC, x) 7334 7335 /* SPARX5 ONLY */ 7336 /* REW:PTP_CTRL:PTP_RSRV_NOT_ZERO */ 7337 #define REW_PTP_RSRV_NOT_ZERO \ 7338 __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 12, 0, 1, 4) 7339 7340 /* SPARX5 ONLY */ 7341 /* REW:PTP_CTRL:PTP_RSRV_NOT_ZERO1 */ 7342 #define REW_PTP_RSRV_NOT_ZERO1 \ 7343 __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 16, 0, 1, 4) 7344 7345 /* SPARX5 ONLY */ 7346 /* REW:PTP_CTRL:PTP_RSRV_NOT_ZERO2 */ 7347 #define REW_PTP_RSRV_NOT_ZERO2 \ 7348 __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 20, 0, 1, 4) 7349 7350 #define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2 GENMASK(5, 0) 7351 #define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2_SET(x)\ 7352 FIELD_PREP(REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2, x) 7353 #define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2_GET(x)\ 7354 FIELD_GET(REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2, x) 7355 7356 /* SPARX5 ONLY */ 7357 /* REW:PTP_CTRL:PTP_GEN_STAMP_FMT */ 7358 #define REW_PTP_GEN_STAMP_FMT(r) \ 7359 __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 24, r, 4, 4) 7360 7361 #define REW_PTP_GEN_STAMP_FMT_RT_OFS GENMASK(6, 2) 7362 #define REW_PTP_GEN_STAMP_FMT_RT_OFS_SET(x)\ 7363 FIELD_PREP(REW_PTP_GEN_STAMP_FMT_RT_OFS, x) 7364 #define REW_PTP_GEN_STAMP_FMT_RT_OFS_GET(x)\ 7365 FIELD_GET(REW_PTP_GEN_STAMP_FMT_RT_OFS, x) 7366 7367 #define REW_PTP_GEN_STAMP_FMT_RT_FMT GENMASK(1, 0) 7368 #define REW_PTP_GEN_STAMP_FMT_RT_FMT_SET(x)\ 7369 FIELD_PREP(REW_PTP_GEN_STAMP_FMT_RT_FMT, x) 7370 #define REW_PTP_GEN_STAMP_FMT_RT_FMT_GET(x)\ 7371 FIELD_GET(REW_PTP_GEN_STAMP_FMT_RT_FMT, x) 7372 7373 /* REW:RAM_CTRL:RAM_INIT */ 7374 #define REW_RAM_INIT \ 7375 __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_RAM_CTRL], 0, 1, 4, 0, 0, 1,\ 7376 4) 7377 7378 #define REW_RAM_INIT_RAM_INIT BIT(1) 7379 #define REW_RAM_INIT_RAM_INIT_SET(x)\ 7380 FIELD_PREP(REW_RAM_INIT_RAM_INIT, x) 7381 #define REW_RAM_INIT_RAM_INIT_GET(x)\ 7382 FIELD_GET(REW_RAM_INIT_RAM_INIT, x) 7383 7384 #define REW_RAM_INIT_RAM_CFG_HOOK BIT(0) 7385 #define REW_RAM_INIT_RAM_CFG_HOOK_SET(x)\ 7386 FIELD_PREP(REW_RAM_INIT_RAM_CFG_HOOK, x) 7387 #define REW_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 7388 FIELD_GET(REW_RAM_INIT_RAM_CFG_HOOK, x) 7389 7390 /* VCAP_ES0:VCAP_CORE_CFG:VCAP_UPDATE_CTRL */ 7391 #define VCAP_ES0_CTRL \ 7392 __REG(TARGET_VCAP_ES0, 0, 1, 0, 0, 1, 8, 0, 0, 1, 4) 7393 7394 #define VCAP_ES0_CTRL_UPDATE_CMD GENMASK(24, 22) 7395 #define VCAP_ES0_CTRL_UPDATE_CMD_SET(x)\ 7396 FIELD_PREP(VCAP_ES0_CTRL_UPDATE_CMD, x) 7397 #define VCAP_ES0_CTRL_UPDATE_CMD_GET(x)\ 7398 FIELD_GET(VCAP_ES0_CTRL_UPDATE_CMD, x) 7399 7400 #define VCAP_ES0_CTRL_UPDATE_ENTRY_DIS BIT(21) 7401 #define VCAP_ES0_CTRL_UPDATE_ENTRY_DIS_SET(x)\ 7402 FIELD_PREP(VCAP_ES0_CTRL_UPDATE_ENTRY_DIS, x) 7403 #define VCAP_ES0_CTRL_UPDATE_ENTRY_DIS_GET(x)\ 7404 FIELD_GET(VCAP_ES0_CTRL_UPDATE_ENTRY_DIS, x) 7405 7406 #define VCAP_ES0_CTRL_UPDATE_ACTION_DIS BIT(20) 7407 #define VCAP_ES0_CTRL_UPDATE_ACTION_DIS_SET(x)\ 7408 FIELD_PREP(VCAP_ES0_CTRL_UPDATE_ACTION_DIS, x) 7409 #define VCAP_ES0_CTRL_UPDATE_ACTION_DIS_GET(x)\ 7410 FIELD_GET(VCAP_ES0_CTRL_UPDATE_ACTION_DIS, x) 7411 7412 #define VCAP_ES0_CTRL_UPDATE_CNT_DIS BIT(19) 7413 #define VCAP_ES0_CTRL_UPDATE_CNT_DIS_SET(x)\ 7414 FIELD_PREP(VCAP_ES0_CTRL_UPDATE_CNT_DIS, x) 7415 #define VCAP_ES0_CTRL_UPDATE_CNT_DIS_GET(x)\ 7416 FIELD_GET(VCAP_ES0_CTRL_UPDATE_CNT_DIS, x) 7417 7418 #define VCAP_ES0_CTRL_UPDATE_ADDR GENMASK(18, 3) 7419 #define VCAP_ES0_CTRL_UPDATE_ADDR_SET(x)\ 7420 FIELD_PREP(VCAP_ES0_CTRL_UPDATE_ADDR, x) 7421 #define VCAP_ES0_CTRL_UPDATE_ADDR_GET(x)\ 7422 FIELD_GET(VCAP_ES0_CTRL_UPDATE_ADDR, x) 7423 7424 #define VCAP_ES0_CTRL_UPDATE_SHOT BIT(2) 7425 #define VCAP_ES0_CTRL_UPDATE_SHOT_SET(x)\ 7426 FIELD_PREP(VCAP_ES0_CTRL_UPDATE_SHOT, x) 7427 #define VCAP_ES0_CTRL_UPDATE_SHOT_GET(x)\ 7428 FIELD_GET(VCAP_ES0_CTRL_UPDATE_SHOT, x) 7429 7430 #define VCAP_ES0_CTRL_CLEAR_CACHE BIT(1) 7431 #define VCAP_ES0_CTRL_CLEAR_CACHE_SET(x)\ 7432 FIELD_PREP(VCAP_ES0_CTRL_CLEAR_CACHE, x) 7433 #define VCAP_ES0_CTRL_CLEAR_CACHE_GET(x)\ 7434 FIELD_GET(VCAP_ES0_CTRL_CLEAR_CACHE, x) 7435 7436 #define VCAP_ES0_CTRL_MV_TRAFFIC_IGN BIT(0) 7437 #define VCAP_ES0_CTRL_MV_TRAFFIC_IGN_SET(x)\ 7438 FIELD_PREP(VCAP_ES0_CTRL_MV_TRAFFIC_IGN, x) 7439 #define VCAP_ES0_CTRL_MV_TRAFFIC_IGN_GET(x)\ 7440 FIELD_GET(VCAP_ES0_CTRL_MV_TRAFFIC_IGN, x) 7441 7442 /* VCAP_ES0:VCAP_CORE_CFG:VCAP_MV_CFG */ 7443 #define VCAP_ES0_CFG \ 7444 __REG(TARGET_VCAP_ES0, 0, 1, 0, 0, 1, 8, 4, 0, 1, 4) 7445 7446 #define VCAP_ES0_CFG_MV_NUM_POS GENMASK(31, 16) 7447 #define VCAP_ES0_CFG_MV_NUM_POS_SET(x)\ 7448 FIELD_PREP(VCAP_ES0_CFG_MV_NUM_POS, x) 7449 #define VCAP_ES0_CFG_MV_NUM_POS_GET(x)\ 7450 FIELD_GET(VCAP_ES0_CFG_MV_NUM_POS, x) 7451 7452 #define VCAP_ES0_CFG_MV_SIZE GENMASK(15, 0) 7453 #define VCAP_ES0_CFG_MV_SIZE_SET(x)\ 7454 FIELD_PREP(VCAP_ES0_CFG_MV_SIZE, x) 7455 #define VCAP_ES0_CFG_MV_SIZE_GET(x)\ 7456 FIELD_GET(VCAP_ES0_CFG_MV_SIZE, x) 7457 7458 /* VCAP_ES0:VCAP_CORE_CACHE:VCAP_ENTRY_DAT */ 7459 #define VCAP_ES0_VCAP_ENTRY_DAT(r) \ 7460 __REG(TARGET_VCAP_ES0, 0, 1, 8, 0, 1, 904, 0, r, 64, 4) 7461 7462 /* VCAP_ES0:VCAP_CORE_CACHE:VCAP_MASK_DAT */ 7463 #define VCAP_ES0_VCAP_MASK_DAT(r) \ 7464 __REG(TARGET_VCAP_ES0, 0, 1, 8, 0, 1, 904, 256, r, 64, 4) 7465 7466 /* VCAP_ES0:VCAP_CORE_CACHE:VCAP_ACTION_DAT */ 7467 #define VCAP_ES0_VCAP_ACTION_DAT(r) \ 7468 __REG(TARGET_VCAP_ES0, 0, 1, 8, 0, 1, 904, 512, r, 64, 4) 7469 7470 /* VCAP_ES0:VCAP_CORE_CACHE:VCAP_CNT_DAT */ 7471 #define VCAP_ES0_VCAP_CNT_DAT(r) \ 7472 __REG(TARGET_VCAP_ES0, 0, 1, 8, 0, 1, 904, 768, r, 32, 4) 7473 7474 /* VCAP_ES0:VCAP_CORE_CACHE:VCAP_CNT_FW_DAT */ 7475 #define VCAP_ES0_VCAP_CNT_FW_DAT \ 7476 __REG(TARGET_VCAP_ES0, 0, 1, 8, 0, 1, 904, 896, 0, 1, 4) 7477 7478 /* VCAP_ES0:VCAP_CORE_CACHE:VCAP_TG_DAT */ 7479 #define VCAP_ES0_VCAP_TG_DAT \ 7480 __REG(TARGET_VCAP_ES0, 0, 1, 8, 0, 1, 904, 900, 0, 1, 4) 7481 7482 /* VCAP_ES0:VCAP_CORE_MAP:VCAP_CORE_IDX */ 7483 #define VCAP_ES0_IDX \ 7484 __REG(TARGET_VCAP_ES0, 0, 1, 912, 0, 1, 8, 0, 0, 1, 4) 7485 7486 #define VCAP_ES0_IDX_CORE_IDX GENMASK(3, 0) 7487 #define VCAP_ES0_IDX_CORE_IDX_SET(x)\ 7488 FIELD_PREP(VCAP_ES0_IDX_CORE_IDX, x) 7489 #define VCAP_ES0_IDX_CORE_IDX_GET(x)\ 7490 FIELD_GET(VCAP_ES0_IDX_CORE_IDX, x) 7491 7492 /* VCAP_ES0:VCAP_CORE_MAP:VCAP_CORE_MAP */ 7493 #define VCAP_ES0_MAP \ 7494 __REG(TARGET_VCAP_ES0, 0, 1, 912, 0, 1, 8, 4, 0, 1, 4) 7495 7496 #define VCAP_ES0_MAP_CORE_MAP GENMASK(2, 0) 7497 #define VCAP_ES0_MAP_CORE_MAP_SET(x)\ 7498 FIELD_PREP(VCAP_ES0_MAP_CORE_MAP, x) 7499 #define VCAP_ES0_MAP_CORE_MAP_GET(x)\ 7500 FIELD_GET(VCAP_ES0_MAP_CORE_MAP, x) 7501 7502 /* VCAP_ES0:VCAP_CORE_STICKY:VCAP_STICKY */ 7503 #define VCAP_ES0_VCAP_STICKY \ 7504 __REG(TARGET_VCAP_ES0, 0, 1, 920, 0, 1, 4, 0, 0, 1, 4) 7505 7506 #define VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY BIT(0) 7507 #define VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_SET(x)\ 7508 FIELD_PREP(VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY, x) 7509 #define VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_GET(x)\ 7510 FIELD_GET(VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY, x) 7511 7512 /* VCAP_ES0:VCAP_CONST:VCAP_VER */ 7513 #define VCAP_ES0_VCAP_VER \ 7514 __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 0, 0, 1, 4) 7515 7516 /* VCAP_ES0:VCAP_CONST:ENTRY_WIDTH */ 7517 #define VCAP_ES0_ENTRY_WIDTH \ 7518 __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 4, 0, 1, 4) 7519 7520 /* VCAP_ES0:VCAP_CONST:ENTRY_CNT */ 7521 #define VCAP_ES0_ENTRY_CNT \ 7522 __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 8, 0, 1, 4) 7523 7524 /* VCAP_ES0:VCAP_CONST:ENTRY_SWCNT */ 7525 #define VCAP_ES0_ENTRY_SWCNT \ 7526 __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 12, 0, 1, 4) 7527 7528 /* VCAP_ES0:VCAP_CONST:ENTRY_TG_WIDTH */ 7529 #define VCAP_ES0_ENTRY_TG_WIDTH \ 7530 __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 16, 0, 1, 4) 7531 7532 /* VCAP_ES0:VCAP_CONST:ACTION_DEF_CNT */ 7533 #define VCAP_ES0_ACTION_DEF_CNT \ 7534 __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 20, 0, 1, 4) 7535 7536 /* VCAP_ES0:VCAP_CONST:ACTION_WIDTH */ 7537 #define VCAP_ES0_ACTION_WIDTH \ 7538 __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 24, 0, 1, 4) 7539 7540 /* VCAP_ES0:VCAP_CONST:CNT_WIDTH */ 7541 #define VCAP_ES0_CNT_WIDTH \ 7542 __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 28, 0, 1, 4) 7543 7544 /* VCAP_ES0:VCAP_CONST:CORE_CNT */ 7545 #define VCAP_ES0_CORE_CNT \ 7546 __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 32, 0, 1, 4) 7547 7548 /* VCAP_ES0:VCAP_CONST:IF_CNT */ 7549 #define VCAP_ES0_IF_CNT \ 7550 __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 36, 0, 1, 4) 7551 7552 /* VCAP_ES2:VCAP_CORE_CFG:VCAP_UPDATE_CTRL */ 7553 #define VCAP_ES2_CTRL \ 7554 __REG(TARGET_VCAP_ES2, 0, 1, 0, 0, 1, 8, 0, 0, 1, 4) 7555 7556 #define VCAP_ES2_CTRL_UPDATE_CMD GENMASK(24, 22) 7557 #define VCAP_ES2_CTRL_UPDATE_CMD_SET(x)\ 7558 FIELD_PREP(VCAP_ES2_CTRL_UPDATE_CMD, x) 7559 #define VCAP_ES2_CTRL_UPDATE_CMD_GET(x)\ 7560 FIELD_GET(VCAP_ES2_CTRL_UPDATE_CMD, x) 7561 7562 #define VCAP_ES2_CTRL_UPDATE_ENTRY_DIS BIT(21) 7563 #define VCAP_ES2_CTRL_UPDATE_ENTRY_DIS_SET(x)\ 7564 FIELD_PREP(VCAP_ES2_CTRL_UPDATE_ENTRY_DIS, x) 7565 #define VCAP_ES2_CTRL_UPDATE_ENTRY_DIS_GET(x)\ 7566 FIELD_GET(VCAP_ES2_CTRL_UPDATE_ENTRY_DIS, x) 7567 7568 #define VCAP_ES2_CTRL_UPDATE_ACTION_DIS BIT(20) 7569 #define VCAP_ES2_CTRL_UPDATE_ACTION_DIS_SET(x)\ 7570 FIELD_PREP(VCAP_ES2_CTRL_UPDATE_ACTION_DIS, x) 7571 #define VCAP_ES2_CTRL_UPDATE_ACTION_DIS_GET(x)\ 7572 FIELD_GET(VCAP_ES2_CTRL_UPDATE_ACTION_DIS, x) 7573 7574 #define VCAP_ES2_CTRL_UPDATE_CNT_DIS BIT(19) 7575 #define VCAP_ES2_CTRL_UPDATE_CNT_DIS_SET(x)\ 7576 FIELD_PREP(VCAP_ES2_CTRL_UPDATE_CNT_DIS, x) 7577 #define VCAP_ES2_CTRL_UPDATE_CNT_DIS_GET(x)\ 7578 FIELD_GET(VCAP_ES2_CTRL_UPDATE_CNT_DIS, x) 7579 7580 #define VCAP_ES2_CTRL_UPDATE_ADDR GENMASK(18, 3) 7581 #define VCAP_ES2_CTRL_UPDATE_ADDR_SET(x)\ 7582 FIELD_PREP(VCAP_ES2_CTRL_UPDATE_ADDR, x) 7583 #define VCAP_ES2_CTRL_UPDATE_ADDR_GET(x)\ 7584 FIELD_GET(VCAP_ES2_CTRL_UPDATE_ADDR, x) 7585 7586 #define VCAP_ES2_CTRL_UPDATE_SHOT BIT(2) 7587 #define VCAP_ES2_CTRL_UPDATE_SHOT_SET(x)\ 7588 FIELD_PREP(VCAP_ES2_CTRL_UPDATE_SHOT, x) 7589 #define VCAP_ES2_CTRL_UPDATE_SHOT_GET(x)\ 7590 FIELD_GET(VCAP_ES2_CTRL_UPDATE_SHOT, x) 7591 7592 #define VCAP_ES2_CTRL_CLEAR_CACHE BIT(1) 7593 #define VCAP_ES2_CTRL_CLEAR_CACHE_SET(x)\ 7594 FIELD_PREP(VCAP_ES2_CTRL_CLEAR_CACHE, x) 7595 #define VCAP_ES2_CTRL_CLEAR_CACHE_GET(x)\ 7596 FIELD_GET(VCAP_ES2_CTRL_CLEAR_CACHE, x) 7597 7598 #define VCAP_ES2_CTRL_MV_TRAFFIC_IGN BIT(0) 7599 #define VCAP_ES2_CTRL_MV_TRAFFIC_IGN_SET(x)\ 7600 FIELD_PREP(VCAP_ES2_CTRL_MV_TRAFFIC_IGN, x) 7601 #define VCAP_ES2_CTRL_MV_TRAFFIC_IGN_GET(x)\ 7602 FIELD_GET(VCAP_ES2_CTRL_MV_TRAFFIC_IGN, x) 7603 7604 /* VCAP_ES2:VCAP_CORE_CFG:VCAP_MV_CFG */ 7605 #define VCAP_ES2_CFG \ 7606 __REG(TARGET_VCAP_ES2, 0, 1, 0, 0, 1, 8, 4, 0, 1, 4) 7607 7608 #define VCAP_ES2_CFG_MV_NUM_POS GENMASK(31, 16) 7609 #define VCAP_ES2_CFG_MV_NUM_POS_SET(x)\ 7610 FIELD_PREP(VCAP_ES2_CFG_MV_NUM_POS, x) 7611 #define VCAP_ES2_CFG_MV_NUM_POS_GET(x)\ 7612 FIELD_GET(VCAP_ES2_CFG_MV_NUM_POS, x) 7613 7614 #define VCAP_ES2_CFG_MV_SIZE GENMASK(15, 0) 7615 #define VCAP_ES2_CFG_MV_SIZE_SET(x)\ 7616 FIELD_PREP(VCAP_ES2_CFG_MV_SIZE, x) 7617 #define VCAP_ES2_CFG_MV_SIZE_GET(x)\ 7618 FIELD_GET(VCAP_ES2_CFG_MV_SIZE, x) 7619 7620 /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_ENTRY_DAT */ 7621 #define VCAP_ES2_VCAP_ENTRY_DAT(r) \ 7622 __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 0, r, 64, 4) 7623 7624 /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_MASK_DAT */ 7625 #define VCAP_ES2_VCAP_MASK_DAT(r) \ 7626 __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 256, r, 64, 4) 7627 7628 /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_ACTION_DAT */ 7629 #define VCAP_ES2_VCAP_ACTION_DAT(r) \ 7630 __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 512, r, 64, 4) 7631 7632 /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_CNT_DAT */ 7633 #define VCAP_ES2_VCAP_CNT_DAT(r) \ 7634 __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 768, r, 32, 4) 7635 7636 /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_CNT_FW_DAT */ 7637 #define VCAP_ES2_VCAP_CNT_FW_DAT \ 7638 __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 896, 0, 1, 4) 7639 7640 /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_TG_DAT */ 7641 #define VCAP_ES2_VCAP_TG_DAT \ 7642 __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 900, 0, 1, 4) 7643 7644 /* VCAP_ES2:VCAP_CORE_MAP:VCAP_CORE_IDX */ 7645 #define VCAP_ES2_IDX \ 7646 __REG(TARGET_VCAP_ES2, 0, 1, 912, 0, 1, 8, 0, 0, 1, 4) 7647 7648 #define VCAP_ES2_IDX_CORE_IDX GENMASK(3, 0) 7649 #define VCAP_ES2_IDX_CORE_IDX_SET(x)\ 7650 FIELD_PREP(VCAP_ES2_IDX_CORE_IDX, x) 7651 #define VCAP_ES2_IDX_CORE_IDX_GET(x)\ 7652 FIELD_GET(VCAP_ES2_IDX_CORE_IDX, x) 7653 7654 /* VCAP_ES2:VCAP_CORE_MAP:VCAP_CORE_MAP */ 7655 #define VCAP_ES2_MAP \ 7656 __REG(TARGET_VCAP_ES2, 0, 1, 912, 0, 1, 8, 4, 0, 1, 4) 7657 7658 #define VCAP_ES2_MAP_CORE_MAP GENMASK(2, 0) 7659 #define VCAP_ES2_MAP_CORE_MAP_SET(x)\ 7660 FIELD_PREP(VCAP_ES2_MAP_CORE_MAP, x) 7661 #define VCAP_ES2_MAP_CORE_MAP_GET(x)\ 7662 FIELD_GET(VCAP_ES2_MAP_CORE_MAP, x) 7663 7664 /* VCAP_ES2:VCAP_CORE_STICKY:VCAP_STICKY */ 7665 #define VCAP_ES2_VCAP_STICKY \ 7666 __REG(TARGET_VCAP_ES2, 0, 1, 920, 0, 1, 4, 0, 0, 1, 4) 7667 7668 #define VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY BIT(0) 7669 #define VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_SET(x)\ 7670 FIELD_PREP(VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY, x) 7671 #define VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_GET(x)\ 7672 FIELD_GET(VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY, x) 7673 7674 /* VCAP_ES2:VCAP_CONST:VCAP_VER */ 7675 #define VCAP_ES2_VCAP_VER \ 7676 __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 0, 0, 1, 4) 7677 7678 /* VCAP_ES2:VCAP_CONST:ENTRY_WIDTH */ 7679 #define VCAP_ES2_ENTRY_WIDTH \ 7680 __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 4, 0, 1, 4) 7681 7682 /* VCAP_ES2:VCAP_CONST:ENTRY_CNT */ 7683 #define VCAP_ES2_ENTRY_CNT \ 7684 __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 8, 0, 1, 4) 7685 7686 /* VCAP_ES2:VCAP_CONST:ENTRY_SWCNT */ 7687 #define VCAP_ES2_ENTRY_SWCNT \ 7688 __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 12, 0, 1, 4) 7689 7690 /* VCAP_ES2:VCAP_CONST:ENTRY_TG_WIDTH */ 7691 #define VCAP_ES2_ENTRY_TG_WIDTH \ 7692 __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 16, 0, 1, 4) 7693 7694 /* VCAP_ES2:VCAP_CONST:ACTION_DEF_CNT */ 7695 #define VCAP_ES2_ACTION_DEF_CNT \ 7696 __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 20, 0, 1, 4) 7697 7698 /* VCAP_ES2:VCAP_CONST:ACTION_WIDTH */ 7699 #define VCAP_ES2_ACTION_WIDTH \ 7700 __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 24, 0, 1, 4) 7701 7702 /* VCAP_ES2:VCAP_CONST:CNT_WIDTH */ 7703 #define VCAP_ES2_CNT_WIDTH \ 7704 __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 28, 0, 1, 4) 7705 7706 /* VCAP_ES2:VCAP_CONST:CORE_CNT */ 7707 #define VCAP_ES2_CORE_CNT \ 7708 __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 32, 0, 1, 4) 7709 7710 /* VCAP_ES2:VCAP_CONST:IF_CNT */ 7711 #define VCAP_ES2_IF_CNT \ 7712 __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 36, 0, 1, 4) 7713 7714 /* VCAP_SUPER:VCAP_CORE_CFG:VCAP_UPDATE_CTRL */ 7715 #define VCAP_SUPER_CTRL \ 7716 __REG(TARGET_VCAP_SUPER, 0, 1, 0, 0, 1, 8, 0, 0, 1, 4) 7717 7718 #define VCAP_SUPER_CTRL_UPDATE_CMD GENMASK(24, 22) 7719 #define VCAP_SUPER_CTRL_UPDATE_CMD_SET(x)\ 7720 FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_CMD, x) 7721 #define VCAP_SUPER_CTRL_UPDATE_CMD_GET(x)\ 7722 FIELD_GET(VCAP_SUPER_CTRL_UPDATE_CMD, x) 7723 7724 #define VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS BIT(21) 7725 #define VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS_SET(x)\ 7726 FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS, x) 7727 #define VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS_GET(x)\ 7728 FIELD_GET(VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS, x) 7729 7730 #define VCAP_SUPER_CTRL_UPDATE_ACTION_DIS BIT(20) 7731 #define VCAP_SUPER_CTRL_UPDATE_ACTION_DIS_SET(x)\ 7732 FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_ACTION_DIS, x) 7733 #define VCAP_SUPER_CTRL_UPDATE_ACTION_DIS_GET(x)\ 7734 FIELD_GET(VCAP_SUPER_CTRL_UPDATE_ACTION_DIS, x) 7735 7736 #define VCAP_SUPER_CTRL_UPDATE_CNT_DIS BIT(19) 7737 #define VCAP_SUPER_CTRL_UPDATE_CNT_DIS_SET(x)\ 7738 FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_CNT_DIS, x) 7739 #define VCAP_SUPER_CTRL_UPDATE_CNT_DIS_GET(x)\ 7740 FIELD_GET(VCAP_SUPER_CTRL_UPDATE_CNT_DIS, x) 7741 7742 #define VCAP_SUPER_CTRL_UPDATE_ADDR GENMASK(18, 3) 7743 #define VCAP_SUPER_CTRL_UPDATE_ADDR_SET(x)\ 7744 FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_ADDR, x) 7745 #define VCAP_SUPER_CTRL_UPDATE_ADDR_GET(x)\ 7746 FIELD_GET(VCAP_SUPER_CTRL_UPDATE_ADDR, x) 7747 7748 #define VCAP_SUPER_CTRL_UPDATE_SHOT BIT(2) 7749 #define VCAP_SUPER_CTRL_UPDATE_SHOT_SET(x)\ 7750 FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_SHOT, x) 7751 #define VCAP_SUPER_CTRL_UPDATE_SHOT_GET(x)\ 7752 FIELD_GET(VCAP_SUPER_CTRL_UPDATE_SHOT, x) 7753 7754 #define VCAP_SUPER_CTRL_CLEAR_CACHE BIT(1) 7755 #define VCAP_SUPER_CTRL_CLEAR_CACHE_SET(x)\ 7756 FIELD_PREP(VCAP_SUPER_CTRL_CLEAR_CACHE, x) 7757 #define VCAP_SUPER_CTRL_CLEAR_CACHE_GET(x)\ 7758 FIELD_GET(VCAP_SUPER_CTRL_CLEAR_CACHE, x) 7759 7760 #define VCAP_SUPER_CTRL_MV_TRAFFIC_IGN BIT(0) 7761 #define VCAP_SUPER_CTRL_MV_TRAFFIC_IGN_SET(x)\ 7762 FIELD_PREP(VCAP_SUPER_CTRL_MV_TRAFFIC_IGN, x) 7763 #define VCAP_SUPER_CTRL_MV_TRAFFIC_IGN_GET(x)\ 7764 FIELD_GET(VCAP_SUPER_CTRL_MV_TRAFFIC_IGN, x) 7765 7766 /* VCAP_SUPER:VCAP_CORE_CFG:VCAP_MV_CFG */ 7767 #define VCAP_SUPER_CFG \ 7768 __REG(TARGET_VCAP_SUPER, 0, 1, 0, 0, 1, 8, 4, 0, 1, 4) 7769 7770 #define VCAP_SUPER_CFG_MV_NUM_POS GENMASK(31, 16) 7771 #define VCAP_SUPER_CFG_MV_NUM_POS_SET(x)\ 7772 FIELD_PREP(VCAP_SUPER_CFG_MV_NUM_POS, x) 7773 #define VCAP_SUPER_CFG_MV_NUM_POS_GET(x)\ 7774 FIELD_GET(VCAP_SUPER_CFG_MV_NUM_POS, x) 7775 7776 #define VCAP_SUPER_CFG_MV_SIZE GENMASK(15, 0) 7777 #define VCAP_SUPER_CFG_MV_SIZE_SET(x)\ 7778 FIELD_PREP(VCAP_SUPER_CFG_MV_SIZE, x) 7779 #define VCAP_SUPER_CFG_MV_SIZE_GET(x)\ 7780 FIELD_GET(VCAP_SUPER_CFG_MV_SIZE, x) 7781 7782 /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_ENTRY_DAT */ 7783 #define VCAP_SUPER_VCAP_ENTRY_DAT(r) \ 7784 __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 0, r, 64, 4) 7785 7786 /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_MASK_DAT */ 7787 #define VCAP_SUPER_VCAP_MASK_DAT(r) \ 7788 __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 256, r, 64, 4) 7789 7790 /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_ACTION_DAT */ 7791 #define VCAP_SUPER_VCAP_ACTION_DAT(r) \ 7792 __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 512, r, 64, 4) 7793 7794 /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_CNT_DAT */ 7795 #define VCAP_SUPER_VCAP_CNT_DAT(r) \ 7796 __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 768, r, 32, 4) 7797 7798 /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_CNT_FW_DAT */ 7799 #define VCAP_SUPER_VCAP_CNT_FW_DAT \ 7800 __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 896, 0, 1, 4) 7801 7802 /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_TG_DAT */ 7803 #define VCAP_SUPER_VCAP_TG_DAT \ 7804 __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 900, 0, 1, 4) 7805 7806 /* VCAP_SUPER:VCAP_CORE_MAP:VCAP_CORE_IDX */ 7807 #define VCAP_SUPER_IDX \ 7808 __REG(TARGET_VCAP_SUPER, 0, 1, 912, 0, 1, 8, 0, 0, 1, 4) 7809 7810 #define VCAP_SUPER_IDX_CORE_IDX GENMASK(3, 0) 7811 #define VCAP_SUPER_IDX_CORE_IDX_SET(x)\ 7812 FIELD_PREP(VCAP_SUPER_IDX_CORE_IDX, x) 7813 #define VCAP_SUPER_IDX_CORE_IDX_GET(x)\ 7814 FIELD_GET(VCAP_SUPER_IDX_CORE_IDX, x) 7815 7816 /* VCAP_SUPER:VCAP_CORE_MAP:VCAP_CORE_MAP */ 7817 #define VCAP_SUPER_MAP \ 7818 __REG(TARGET_VCAP_SUPER, 0, 1, 912, 0, 1, 8, 4, 0, 1, 4) 7819 7820 #define VCAP_SUPER_MAP_CORE_MAP GENMASK(2, 0) 7821 #define VCAP_SUPER_MAP_CORE_MAP_SET(x)\ 7822 FIELD_PREP(VCAP_SUPER_MAP_CORE_MAP, x) 7823 #define VCAP_SUPER_MAP_CORE_MAP_GET(x)\ 7824 FIELD_GET(VCAP_SUPER_MAP_CORE_MAP, x) 7825 7826 /* VCAP_SUPER:VCAP_CONST:VCAP_VER */ 7827 #define VCAP_SUPER_VCAP_VER \ 7828 __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 0, 0, 1, 4) 7829 7830 /* VCAP_SUPER:VCAP_CONST:ENTRY_WIDTH */ 7831 #define VCAP_SUPER_ENTRY_WIDTH \ 7832 __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 4, 0, 1, 4) 7833 7834 /* VCAP_SUPER:VCAP_CONST:ENTRY_CNT */ 7835 #define VCAP_SUPER_ENTRY_CNT \ 7836 __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 8, 0, 1, 4) 7837 7838 /* VCAP_SUPER:VCAP_CONST:ENTRY_SWCNT */ 7839 #define VCAP_SUPER_ENTRY_SWCNT \ 7840 __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 12, 0, 1, 4) 7841 7842 /* VCAP_SUPER:VCAP_CONST:ENTRY_TG_WIDTH */ 7843 #define VCAP_SUPER_ENTRY_TG_WIDTH \ 7844 __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 16, 0, 1, 4) 7845 7846 /* VCAP_SUPER:VCAP_CONST:ACTION_DEF_CNT */ 7847 #define VCAP_SUPER_ACTION_DEF_CNT \ 7848 __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 20, 0, 1, 4) 7849 7850 /* VCAP_SUPER:VCAP_CONST:ACTION_WIDTH */ 7851 #define VCAP_SUPER_ACTION_WIDTH \ 7852 __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 24, 0, 1, 4) 7853 7854 /* VCAP_SUPER:VCAP_CONST:CNT_WIDTH */ 7855 #define VCAP_SUPER_CNT_WIDTH \ 7856 __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 28, 0, 1, 4) 7857 7858 /* VCAP_SUPER:VCAP_CONST:CORE_CNT */ 7859 #define VCAP_SUPER_CORE_CNT \ 7860 __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 32, 0, 1, 4) 7861 7862 /* VCAP_SUPER:VCAP_CONST:IF_CNT */ 7863 #define VCAP_SUPER_IF_CNT \ 7864 __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 36, 0, 1, 4) 7865 7866 /* VCAP_SUPER:RAM_CTRL:RAM_INIT */ 7867 #define VCAP_SUPER_RAM_INIT \ 7868 __REG(TARGET_VCAP_SUPER, 0, 1, 1120, 0, 1, 4, 0, 0, 1, 4) 7869 7870 #define VCAP_SUPER_RAM_INIT_RAM_INIT BIT(1) 7871 #define VCAP_SUPER_RAM_INIT_RAM_INIT_SET(x)\ 7872 FIELD_PREP(VCAP_SUPER_RAM_INIT_RAM_INIT, x) 7873 #define VCAP_SUPER_RAM_INIT_RAM_INIT_GET(x)\ 7874 FIELD_GET(VCAP_SUPER_RAM_INIT_RAM_INIT, x) 7875 7876 #define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK BIT(0) 7877 #define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK_SET(x)\ 7878 FIELD_PREP(VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK, x) 7879 #define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 7880 FIELD_GET(VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK, x) 7881 7882 /* VOP:RAM_CTRL:RAM_INIT */ 7883 #define VOP_RAM_INIT \ 7884 __REG(TARGET_VOP, 0, 1, regs->gaddr[GA_VOP_RAM_CTRL], 0, 1, 4, 0, 0, 1,\ 7885 4) 7886 7887 #define VOP_RAM_INIT_RAM_INIT BIT(1) 7888 #define VOP_RAM_INIT_RAM_INIT_SET(x)\ 7889 FIELD_PREP(VOP_RAM_INIT_RAM_INIT, x) 7890 #define VOP_RAM_INIT_RAM_INIT_GET(x)\ 7891 FIELD_GET(VOP_RAM_INIT_RAM_INIT, x) 7892 7893 #define VOP_RAM_INIT_RAM_CFG_HOOK BIT(0) 7894 #define VOP_RAM_INIT_RAM_CFG_HOOK_SET(x)\ 7895 FIELD_PREP(VOP_RAM_INIT_RAM_CFG_HOOK, x) 7896 #define VOP_RAM_INIT_RAM_CFG_HOOK_GET(x)\ 7897 FIELD_GET(VOP_RAM_INIT_RAM_CFG_HOOK, x) 7898 7899 /* XQS:SYSTEM:STAT_CFG */ 7900 #define XQS_STAT_CFG \ 7901 __REG(TARGET_XQS, 0, 1, regs->gaddr[GA_XQS_SYSTEM], 0, 1, 872, 860, 0, \ 7902 1, 4) 7903 7904 #define XQS_STAT_CFG_STAT_CLEAR_SHOT GENMASK(21, 18) 7905 #define XQS_STAT_CFG_STAT_CLEAR_SHOT_SET(x)\ 7906 FIELD_PREP(XQS_STAT_CFG_STAT_CLEAR_SHOT, x) 7907 #define XQS_STAT_CFG_STAT_CLEAR_SHOT_GET(x)\ 7908 FIELD_GET(XQS_STAT_CFG_STAT_CLEAR_SHOT, x) 7909 7910 #define XQS_STAT_CFG_STAT_VIEW\ 7911 GENMASK(regs->fsize[FW_XQS_STAT_CFG_STAT_VIEW] + 5 - 1, 5) 7912 #define XQS_STAT_CFG_STAT_VIEW_SET(x)\ 7913 spx5_field_prep(XQS_STAT_CFG_STAT_VIEW, x) 7914 #define XQS_STAT_CFG_STAT_VIEW_GET(x)\ 7915 spx5_field_get(XQS_STAT_CFG_STAT_VIEW, x) 7916 7917 #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY BIT(4) 7918 #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY_SET(x)\ 7919 FIELD_PREP(XQS_STAT_CFG_STAT_SRV_PKT_ONLY, x) 7920 #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY_GET(x)\ 7921 FIELD_GET(XQS_STAT_CFG_STAT_SRV_PKT_ONLY, x) 7922 7923 #define XQS_STAT_CFG_STAT_WRAP_DIS GENMASK(3, 0) 7924 #define XQS_STAT_CFG_STAT_WRAP_DIS_SET(x)\ 7925 FIELD_PREP(XQS_STAT_CFG_STAT_WRAP_DIS, x) 7926 #define XQS_STAT_CFG_STAT_WRAP_DIS_GET(x)\ 7927 FIELD_GET(XQS_STAT_CFG_STAT_WRAP_DIS, x) 7928 7929 /* XQS:QLIMIT_SHR:QLIMIT_SHR_TOP_CFG */ 7930 #define XQS_QLIMIT_SHR_TOP_CFG(g) \ 7931 __REG(TARGET_XQS, 0, 1, regs->gaddr[GA_XQS_QLIMIT_SHR], g, 4, 48, 0, 0,\ 7932 1, 4) 7933 7934 #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP\ 7935 GENMASK(regs->fsize[FW_XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP] + 0 - 1, 0) 7936 #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP_SET(x)\ 7937 spx5_field_prep(XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP, x) 7938 #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP_GET(x)\ 7939 spx5_field_get(XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP, x) 7940 7941 /* XQS:QLIMIT_SHR:QLIMIT_SHR_ATOP_CFG */ 7942 #define XQS_QLIMIT_SHR_ATOP_CFG(g) \ 7943 __REG(TARGET_XQS, 0, 1, regs->gaddr[GA_XQS_QLIMIT_SHR], g, 4, 48, 4, 0,\ 7944 1, 4) 7945 7946 #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP\ 7947 GENMASK(regs->fsize[FW_XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP] + 0 - 1, 0) 7948 #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP_SET(x)\ 7949 spx5_field_prep(XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP, x) 7950 #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP_GET(x)\ 7951 spx5_field_get(XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP, x) 7952 7953 /* XQS:QLIMIT_SHR:QLIMIT_SHR_CTOP_CFG */ 7954 #define XQS_QLIMIT_SHR_CTOP_CFG(g) \ 7955 __REG(TARGET_XQS, 0, 1, regs->gaddr[GA_XQS_QLIMIT_SHR], g, 4, 48, 8, 0,\ 7956 1, 4) 7957 7958 #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP\ 7959 GENMASK(regs->fsize[FW_XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP] + 0 - 1, 0) 7960 #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP_SET(x)\ 7961 spx5_field_prep(XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP, x) 7962 #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP_GET(x)\ 7963 spx5_field_get(XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP, x) 7964 7965 /* XQS:QLIMIT_SHR:QLIMIT_SHR_QLIM_CFG */ 7966 #define XQS_QLIMIT_SHR_QLIM_CFG(g) \ 7967 __REG(TARGET_XQS, 0, 1, regs->gaddr[GA_XQS_QLIMIT_SHR], g, 4, 48, 12, \ 7968 0, 1, 4) 7969 7970 #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM\ 7971 GENMASK(regs->fsize[FW_XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM] + 0 - 1, 0) 7972 #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM_SET(x)\ 7973 spx5_field_prep(XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM, x) 7974 #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM_GET(x)\ 7975 spx5_field_get(XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM, x) 7976 7977 /* XQS:STAT:CNT */ 7978 #define XQS_CNT(g) \ 7979 __REG(TARGET_XQS, 0, 1, 0, g, 1024, 4, 0, 0, 1, 4) 7980 7981 #endif /* _SPARX5_MAIN_REGS_H_ */ 7982