1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* Microchip Sparx5 Switch driver 3 * 4 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. 5 */ 6 7 #ifndef __SPARX5_MAIN_H__ 8 #define __SPARX5_MAIN_H__ 9 10 #include <linux/types.h> 11 #include <linux/phy/phy.h> 12 #include <linux/netdevice.h> 13 #include <linux/phy.h> 14 #include <linux/if_vlan.h> 15 #include <linux/bitmap.h> 16 #include <linux/phylink.h> 17 #include <linux/net_tstamp.h> 18 #include <linux/ptp_clock_kernel.h> 19 #include <linux/hrtimer.h> 20 #include <linux/debugfs.h> 21 #include <net/flow_offload.h> 22 23 #include <fdma_api.h> 24 25 #include "sparx5_main_regs.h" 26 27 /* Target chip type */ 28 enum spx5_target_chiptype { 29 SPX5_TARGET_CT_7546 = 0x7546, /* SparX-5-64 Enterprise */ 30 SPX5_TARGET_CT_7549 = 0x7549, /* SparX-5-90 Enterprise */ 31 SPX5_TARGET_CT_7552 = 0x7552, /* SparX-5-128 Enterprise */ 32 SPX5_TARGET_CT_7556 = 0x7556, /* SparX-5-160 Enterprise */ 33 SPX5_TARGET_CT_7558 = 0x7558, /* SparX-5-200 Enterprise */ 34 SPX5_TARGET_CT_7546TSN = 0x47546, /* SparX-5-64i Industrial */ 35 SPX5_TARGET_CT_7549TSN = 0x47549, /* SparX-5-90i Industrial */ 36 SPX5_TARGET_CT_7552TSN = 0x47552, /* SparX-5-128i Industrial */ 37 SPX5_TARGET_CT_7556TSN = 0x47556, /* SparX-5-160i Industrial */ 38 SPX5_TARGET_CT_7558TSN = 0x47558, /* SparX-5-200i Industrial */ 39 }; 40 41 enum sparx5_port_max_tags { 42 SPX5_PORT_MAX_TAGS_NONE, /* No extra tags allowed */ 43 SPX5_PORT_MAX_TAGS_ONE, /* Single tag allowed */ 44 SPX5_PORT_MAX_TAGS_TWO /* Single and double tag allowed */ 45 }; 46 47 enum sparx5_vlan_port_type { 48 SPX5_VLAN_PORT_TYPE_UNAWARE, /* VLAN unaware port */ 49 SPX5_VLAN_PORT_TYPE_C, /* C-port */ 50 SPX5_VLAN_PORT_TYPE_S, /* S-port */ 51 SPX5_VLAN_PORT_TYPE_S_CUSTOM /* S-port using custom type */ 52 }; 53 54 #define SPX5_PORTS 65 55 #define SPX5_PORT_CPU (SPX5_PORTS) /* Next port is CPU port */ 56 #define SPX5_PORT_CPU_0 (SPX5_PORT_CPU + 0) /* CPU Port 65 */ 57 #define SPX5_PORT_CPU_1 (SPX5_PORT_CPU + 1) /* CPU Port 66 */ 58 #define SPX5_PORT_VD0 (SPX5_PORT_CPU + 2) /* VD0/Port 67 used for IPMC */ 59 #define SPX5_PORT_VD1 (SPX5_PORT_CPU + 3) /* VD1/Port 68 used for AFI/OAM */ 60 #define SPX5_PORT_VD2 (SPX5_PORT_CPU + 4) /* VD2/Port 69 used for IPinIP*/ 61 #define SPX5_PORTS_ALL (SPX5_PORT_CPU + 5) /* Total number of ports */ 62 63 #define PGID_BASE SPX5_PORTS /* Starts after port PGIDs */ 64 #define PGID_UC_FLOOD (PGID_BASE + 0) 65 #define PGID_MC_FLOOD (PGID_BASE + 1) 66 #define PGID_IPV4_MC_DATA (PGID_BASE + 2) 67 #define PGID_IPV4_MC_CTRL (PGID_BASE + 3) 68 #define PGID_IPV6_MC_DATA (PGID_BASE + 4) 69 #define PGID_IPV6_MC_CTRL (PGID_BASE + 5) 70 #define PGID_BCAST (PGID_BASE + 6) 71 #define PGID_CPU (PGID_BASE + 7) 72 #define PGID_MCAST_START (PGID_BASE + 8) 73 74 #define PGID_TABLE_SIZE 3290 75 76 #define IFH_LEN 9 /* 36 bytes */ 77 #define NULL_VID 0 78 #define SPX5_MACT_PULL_DELAY (2 * HZ) 79 #define SPX5_STATS_CHECK_DELAY (1 * HZ) 80 #define SPX5_PRIOS 8 /* Number of priority queues */ 81 #define SPX5_BUFFER_CELL_SZ 184 /* Cell size */ 82 #define SPX5_BUFFER_MEMORY 4194280 /* 22795 words * 184 bytes */ 83 84 #define XTR_QUEUE 0 85 #define INJ_QUEUE 0 86 87 #define FDMA_DCB_MAX 64 88 #define FDMA_RX_DCB_MAX_DBS 15 89 #define FDMA_TX_DCB_MAX_DBS 1 90 91 #define SPARX5_PHC_COUNT 3 92 #define SPARX5_PHC_PORT 0 93 94 #define IFH_REW_OP_NOOP 0x0 95 #define IFH_REW_OP_ONE_STEP_PTP 0x3 96 #define IFH_REW_OP_TWO_STEP_PTP 0x4 97 98 #define IFH_PDU_TYPE_NONE 0x0 99 #define IFH_PDU_TYPE_PTP 0x5 100 #define IFH_PDU_TYPE_IPV4_UDP_PTP 0x6 101 #define IFH_PDU_TYPE_IPV6_UDP_PTP 0x7 102 103 struct sparx5; 104 105 /* Frame DMA receive state: 106 * For each DB, there is a SKB, and the skb data pointer is mapped in 107 * the DB. Once a frame is received the skb is given to the upper layers 108 * and a new skb is added to the dcb. 109 * When the db_index reached FDMA_RX_DCB_MAX_DBS the DB is reused. 110 */ 111 struct sparx5_rx { 112 struct fdma fdma; 113 struct sk_buff *skb[FDMA_DCB_MAX][FDMA_RX_DCB_MAX_DBS]; 114 dma_addr_t dma; 115 struct napi_struct napi; 116 struct net_device *ndev; 117 u64 packets; 118 }; 119 120 /* Frame DMA transmit state: 121 * DCBs are chained using the DCBs nextptr field. 122 */ 123 struct sparx5_tx { 124 struct fdma fdma; 125 u64 packets; 126 u64 dropped; 127 }; 128 129 struct sparx5_port_config { 130 phy_interface_t portmode; 131 u32 bandwidth; 132 int speed; 133 int duplex; 134 enum phy_media media; 135 bool inband; 136 bool power_down; 137 bool autoneg; 138 bool serdes_reset; 139 u32 pause; 140 u32 pause_adv; 141 phy_interface_t phy_mode; 142 u32 sd_sgpio; 143 }; 144 145 struct sparx5_port { 146 struct net_device *ndev; 147 struct sparx5 *sparx5; 148 struct device_node *of_node; 149 struct phy *serdes; 150 struct sparx5_port_config conf; 151 struct phylink_config phylink_config; 152 struct phylink *phylink; 153 struct phylink_pcs phylink_pcs; 154 struct flow_stats mirror_stats; 155 u16 portno; 156 /* Ingress default VLAN (pvid) */ 157 u16 pvid; 158 /* Egress default VLAN (vid) */ 159 u16 vid; 160 bool signd_internal; 161 bool signd_active_high; 162 bool signd_enable; 163 bool flow_control; 164 enum sparx5_port_max_tags max_vlan_tags; 165 enum sparx5_vlan_port_type vlan_type; 166 u32 custom_etype; 167 bool vlan_aware; 168 struct hrtimer inj_timer; 169 /* ptp */ 170 u8 ptp_cmd; 171 u16 ts_id; 172 struct sk_buff_head tx_skbs; 173 bool is_mrouter; 174 struct list_head tc_templates; /* list of TC templates on this port */ 175 }; 176 177 enum sparx5_core_clockfreq { 178 SPX5_CORE_CLOCK_DEFAULT, /* Defaults to the highest supported frequency */ 179 SPX5_CORE_CLOCK_250MHZ, /* 250MHZ core clock frequency */ 180 SPX5_CORE_CLOCK_500MHZ, /* 500MHZ core clock frequency */ 181 SPX5_CORE_CLOCK_625MHZ, /* 625MHZ core clock frequency */ 182 }; 183 184 struct sparx5_phc { 185 struct ptp_clock *clock; 186 struct ptp_clock_info info; 187 struct kernel_hwtstamp_config hwtstamp_config; 188 struct sparx5 *sparx5; 189 u8 index; 190 }; 191 192 struct sparx5_skb_cb { 193 u8 rew_op; 194 u8 pdu_type; 195 u8 pdu_w16_offset; 196 u16 ts_id; 197 unsigned long jiffies; 198 }; 199 200 struct sparx5_mdb_entry { 201 struct list_head list; 202 DECLARE_BITMAP(port_mask, SPX5_PORTS); 203 unsigned char addr[ETH_ALEN]; 204 bool cpu_copy; 205 u16 vid; 206 u16 pgid_idx; 207 }; 208 209 struct sparx5_mall_mirror_entry { 210 u32 idx; 211 struct sparx5_port *port; 212 }; 213 214 struct sparx5_mall_entry { 215 struct list_head list; 216 struct sparx5_port *port; 217 unsigned long cookie; 218 enum flow_action_id type; 219 bool ingress; 220 union { 221 struct sparx5_mall_mirror_entry mirror; 222 }; 223 }; 224 225 #define SPARX5_PTP_TIMEOUT msecs_to_jiffies(10) 226 #define SPARX5_SKB_CB(skb) \ 227 ((struct sparx5_skb_cb *)((skb)->cb)) 228 229 struct sparx5 { 230 struct platform_device *pdev; 231 struct device *dev; 232 u32 chip_id; 233 enum spx5_target_chiptype target_ct; 234 void __iomem *regs[NUM_TARGETS]; 235 int port_count; 236 struct mutex lock; /* MAC reg lock */ 237 /* port structures are in net device */ 238 struct sparx5_port *ports[SPX5_PORTS]; 239 enum sparx5_core_clockfreq coreclock; 240 /* Statistics */ 241 u32 num_stats; 242 u32 num_ethtool_stats; 243 const char * const *stats_layout; 244 u64 *stats; 245 /* Workqueue for reading stats */ 246 struct mutex queue_stats_lock; 247 struct delayed_work stats_work; 248 struct workqueue_struct *stats_queue; 249 /* Notifiers */ 250 struct notifier_block netdevice_nb; 251 struct notifier_block switchdev_nb; 252 struct notifier_block switchdev_blocking_nb; 253 /* Switch state */ 254 u8 base_mac[ETH_ALEN]; 255 /* Associated bridge device (when bridged) */ 256 struct net_device *hw_bridge_dev; 257 /* Bridged interfaces */ 258 DECLARE_BITMAP(bridge_mask, SPX5_PORTS); 259 DECLARE_BITMAP(bridge_fwd_mask, SPX5_PORTS); 260 DECLARE_BITMAP(bridge_lrn_mask, SPX5_PORTS); 261 DECLARE_BITMAP(vlan_mask[VLAN_N_VID], SPX5_PORTS); 262 /* SW MAC table */ 263 struct list_head mact_entries; 264 /* mac table list (mact_entries) mutex */ 265 struct mutex mact_lock; 266 /* SW MDB table */ 267 struct list_head mdb_entries; 268 /* mdb list mutex */ 269 struct mutex mdb_lock; 270 struct delayed_work mact_work; 271 struct workqueue_struct *mact_queue; 272 /* Board specifics */ 273 bool sd_sgpio_remapping; 274 /* Register based inj/xtr */ 275 int xtr_irq; 276 /* Frame DMA */ 277 int fdma_irq; 278 spinlock_t tx_lock; /* lock for frame transmission */ 279 struct sparx5_rx rx; 280 struct sparx5_tx tx; 281 /* PTP */ 282 bool ptp; 283 struct sparx5_phc phc[SPARX5_PHC_COUNT]; 284 spinlock_t ptp_clock_lock; /* lock for phc */ 285 spinlock_t ptp_ts_id_lock; /* lock for ts_id */ 286 struct mutex ptp_lock; /* lock for ptp interface state */ 287 u16 ptp_skbs; 288 int ptp_irq; 289 /* VCAP */ 290 struct vcap_control *vcap_ctrl; 291 /* PGID allocation map */ 292 u8 pgid_map[PGID_TABLE_SIZE]; 293 struct list_head mall_entries; 294 /* Common root for debugfs */ 295 struct dentry *debugfs_root; 296 }; 297 298 /* sparx5_switchdev.c */ 299 int sparx5_register_notifier_blocks(struct sparx5 *sparx5); 300 void sparx5_unregister_notifier_blocks(struct sparx5 *sparx5); 301 302 /* sparx5_packet.c */ 303 struct frame_info { 304 int src_port; 305 u32 timestamp; 306 }; 307 308 void sparx5_xtr_flush(struct sparx5 *sparx5, u8 grp); 309 void sparx5_ifh_parse(u32 *ifh, struct frame_info *info); 310 irqreturn_t sparx5_xtr_handler(int irq, void *_priv); 311 netdev_tx_t sparx5_port_xmit_impl(struct sk_buff *skb, struct net_device *dev); 312 int sparx5_manual_injection_mode(struct sparx5 *sparx5); 313 void sparx5_port_inj_timer_setup(struct sparx5_port *port); 314 315 /* sparx5_fdma.c */ 316 int sparx5_fdma_start(struct sparx5 *sparx5); 317 int sparx5_fdma_stop(struct sparx5 *sparx5); 318 int sparx5_fdma_xmit(struct sparx5 *sparx5, u32 *ifh, struct sk_buff *skb); 319 irqreturn_t sparx5_fdma_handler(int irq, void *args); 320 321 /* sparx5_mactable.c */ 322 void sparx5_mact_pull_work(struct work_struct *work); 323 int sparx5_mact_learn(struct sparx5 *sparx5, int port, 324 const unsigned char mac[ETH_ALEN], u16 vid); 325 bool sparx5_mact_getnext(struct sparx5 *sparx5, 326 unsigned char mac[ETH_ALEN], u16 *vid, u32 *pcfg2); 327 int sparx5_mact_find(struct sparx5 *sparx5, 328 const unsigned char mac[ETH_ALEN], u16 vid, u32 *pcfg2); 329 int sparx5_mact_forget(struct sparx5 *sparx5, 330 const unsigned char mac[ETH_ALEN], u16 vid); 331 int sparx5_add_mact_entry(struct sparx5 *sparx5, 332 struct net_device *dev, 333 u16 portno, 334 const unsigned char *addr, u16 vid); 335 int sparx5_del_mact_entry(struct sparx5 *sparx5, 336 const unsigned char *addr, 337 u16 vid); 338 int sparx5_mc_sync(struct net_device *dev, const unsigned char *addr); 339 int sparx5_mc_unsync(struct net_device *dev, const unsigned char *addr); 340 void sparx5_set_ageing(struct sparx5 *sparx5, int msecs); 341 void sparx5_mact_init(struct sparx5 *sparx5); 342 343 /* sparx5_vlan.c */ 344 void sparx5_pgid_update_mask(struct sparx5_port *port, int pgid, bool enable); 345 void sparx5_pgid_clear(struct sparx5 *spx5, int pgid); 346 void sparx5_pgid_read_mask(struct sparx5 *sparx5, int pgid, u32 portmask[3]); 347 void sparx5_update_fwd(struct sparx5 *sparx5); 348 void sparx5_vlan_init(struct sparx5 *sparx5); 349 void sparx5_vlan_port_setup(struct sparx5 *sparx5, int portno); 350 int sparx5_vlan_vid_add(struct sparx5_port *port, u16 vid, bool pvid, 351 bool untagged); 352 int sparx5_vlan_vid_del(struct sparx5_port *port, u16 vid); 353 void sparx5_vlan_port_apply(struct sparx5 *sparx5, struct sparx5_port *port); 354 355 /* sparx5_calendar.c */ 356 int sparx5_config_auto_calendar(struct sparx5 *sparx5); 357 int sparx5_config_dsm_calendar(struct sparx5 *sparx5); 358 359 /* sparx5_ethtool.c */ 360 void sparx5_get_stats64(struct net_device *ndev, struct rtnl_link_stats64 *stats); 361 int sparx_stats_init(struct sparx5 *sparx5); 362 363 /* sparx5_dcb.c */ 364 #ifdef CONFIG_SPARX5_DCB 365 int sparx5_dcb_init(struct sparx5 *sparx5); 366 #else 367 static inline int sparx5_dcb_init(struct sparx5 *sparx5) 368 { 369 return 0; 370 } 371 #endif 372 373 /* sparx5_netdev.c */ 374 void sparx5_set_port_ifh_timestamp(void *ifh_hdr, u64 timestamp); 375 void sparx5_set_port_ifh_rew_op(void *ifh_hdr, u32 rew_op); 376 void sparx5_set_port_ifh_pdu_type(void *ifh_hdr, u32 pdu_type); 377 void sparx5_set_port_ifh_pdu_w16_offset(void *ifh_hdr, u32 pdu_w16_offset); 378 void sparx5_set_port_ifh(void *ifh_hdr, u16 portno); 379 bool sparx5_netdevice_check(const struct net_device *dev); 380 struct net_device *sparx5_create_netdev(struct sparx5 *sparx5, u32 portno); 381 int sparx5_register_netdevs(struct sparx5 *sparx5); 382 void sparx5_destroy_netdevs(struct sparx5 *sparx5); 383 void sparx5_unregister_netdevs(struct sparx5 *sparx5); 384 385 /* sparx5_ptp.c */ 386 int sparx5_ptp_init(struct sparx5 *sparx5); 387 void sparx5_ptp_deinit(struct sparx5 *sparx5); 388 int sparx5_ptp_hwtstamp_set(struct sparx5_port *port, 389 struct kernel_hwtstamp_config *cfg, 390 struct netlink_ext_ack *extack); 391 void sparx5_ptp_hwtstamp_get(struct sparx5_port *port, 392 struct kernel_hwtstamp_config *cfg); 393 void sparx5_ptp_rxtstamp(struct sparx5 *sparx5, struct sk_buff *skb, 394 u64 timestamp); 395 int sparx5_ptp_txtstamp_request(struct sparx5_port *port, 396 struct sk_buff *skb); 397 void sparx5_ptp_txtstamp_release(struct sparx5_port *port, 398 struct sk_buff *skb); 399 irqreturn_t sparx5_ptp_irq_handler(int irq, void *args); 400 int sparx5_ptp_gettime64(struct ptp_clock_info *ptp, struct timespec64 *ts); 401 402 /* sparx5_vcap_impl.c */ 403 int sparx5_vcap_init(struct sparx5 *sparx5); 404 void sparx5_vcap_destroy(struct sparx5 *sparx5); 405 406 /* sparx5_pgid.c */ 407 enum sparx5_pgid_type { 408 SPX5_PGID_FREE, 409 SPX5_PGID_RESERVED, 410 SPX5_PGID_MULTICAST, 411 }; 412 413 void sparx5_pgid_init(struct sparx5 *spx5); 414 int sparx5_pgid_alloc_mcast(struct sparx5 *spx5, u16 *idx); 415 int sparx5_pgid_free(struct sparx5 *spx5, u16 idx); 416 417 /* sparx5_pool.c */ 418 struct sparx5_pool_entry { 419 u16 ref_cnt; 420 u32 idx; /* tc index */ 421 }; 422 423 u32 sparx5_pool_idx_to_id(u32 idx); 424 int sparx5_pool_put(struct sparx5_pool_entry *pool, int size, u32 id); 425 int sparx5_pool_get(struct sparx5_pool_entry *pool, int size, u32 *id); 426 int sparx5_pool_get_with_idx(struct sparx5_pool_entry *pool, int size, u32 idx, 427 u32 *id); 428 429 /* sparx5_sdlb.c */ 430 #define SPX5_SDLB_PUP_TOKEN_DISABLE 0x1FFF 431 #define SPX5_SDLB_PUP_TOKEN_MAX (SPX5_SDLB_PUP_TOKEN_DISABLE - 1) 432 #define SPX5_SDLB_GROUP_RATE_MAX 25000000000ULL 433 #define SPX5_SDLB_2CYCLES_TYPE2_THRES_OFFSET 13 434 #define SPX5_SDLB_CNT 4096 435 #define SPX5_SDLB_GROUP_CNT 10 436 #define SPX5_CLK_PER_100PS_DEFAULT 16 437 438 struct sparx5_sdlb_group { 439 u64 max_rate; 440 u32 min_burst; 441 u32 frame_size; 442 u32 pup_interval; 443 u32 nsets; 444 }; 445 446 extern struct sparx5_sdlb_group sdlb_groups[SPX5_SDLB_GROUP_CNT]; 447 int sparx5_sdlb_pup_token_get(struct sparx5 *sparx5, u32 pup_interval, 448 u64 rate); 449 450 int sparx5_sdlb_clk_hz_get(struct sparx5 *sparx5); 451 int sparx5_sdlb_group_get_by_rate(struct sparx5 *sparx5, u32 rate, u32 burst); 452 int sparx5_sdlb_group_get_by_index(struct sparx5 *sparx5, u32 idx, u32 *group); 453 454 int sparx5_sdlb_group_add(struct sparx5 *sparx5, u32 group, u32 idx); 455 int sparx5_sdlb_group_del(struct sparx5 *sparx5, u32 group, u32 idx); 456 457 void sparx5_sdlb_group_init(struct sparx5 *sparx5, u64 max_rate, u32 min_burst, 458 u32 frame_size, u32 idx); 459 460 /* sparx5_police.c */ 461 enum { 462 /* More policer types will be added later */ 463 SPX5_POL_SERVICE 464 }; 465 466 struct sparx5_policer { 467 u32 type; 468 u32 idx; 469 u64 rate; 470 u32 burst; 471 u32 group; 472 u8 event_mask; 473 }; 474 475 int sparx5_policer_conf_set(struct sparx5 *sparx5, struct sparx5_policer *pol); 476 477 /* sparx5_psfp.c */ 478 #define SPX5_PSFP_GCE_CNT 4 479 #define SPX5_PSFP_SG_CNT 1024 480 #define SPX5_PSFP_SG_MIN_CYCLE_TIME_NS (1 * NSEC_PER_USEC) 481 #define SPX5_PSFP_SG_MAX_CYCLE_TIME_NS ((1 * NSEC_PER_SEC) - 1) 482 #define SPX5_PSFP_SG_MAX_IPV (SPX5_PRIOS - 1) 483 #define SPX5_PSFP_SG_OPEN (SPX5_PSFP_SG_CNT - 1) 484 #define SPX5_PSFP_SG_CYCLE_TIME_DEFAULT 1000000 485 #define SPX5_PSFP_SF_MAX_SDU 16383 486 487 struct sparx5_psfp_fm { 488 struct sparx5_policer pol; 489 }; 490 491 struct sparx5_psfp_gce { 492 bool gate_state; /* StreamGateState */ 493 u32 interval; /* TimeInterval */ 494 u32 ipv; /* InternalPriorityValue */ 495 u32 maxoctets; /* IntervalOctetMax */ 496 }; 497 498 struct sparx5_psfp_sg { 499 bool gate_state; /* PSFPAdminGateStates */ 500 bool gate_enabled; /* PSFPGateEnabled */ 501 u32 ipv; /* PSFPAdminIPV */ 502 struct timespec64 basetime; /* PSFPAdminBaseTime */ 503 u32 cycletime; /* PSFPAdminCycleTime */ 504 u32 cycletimeext; /* PSFPAdminCycleTimeExtension */ 505 u32 num_entries; /* PSFPAdminControlListLength */ 506 struct sparx5_psfp_gce gce[SPX5_PSFP_GCE_CNT]; 507 }; 508 509 struct sparx5_psfp_sf { 510 bool sblock_osize_ena; 511 bool sblock_osize; 512 u32 max_sdu; 513 u32 sgid; /* Gate id */ 514 u32 fmid; /* Flow meter id */ 515 }; 516 517 int sparx5_psfp_fm_add(struct sparx5 *sparx5, u32 uidx, 518 struct sparx5_psfp_fm *fm, u32 *id); 519 int sparx5_psfp_fm_del(struct sparx5 *sparx5, u32 id); 520 521 int sparx5_psfp_sg_add(struct sparx5 *sparx5, u32 uidx, 522 struct sparx5_psfp_sg *sg, u32 *id); 523 int sparx5_psfp_sg_del(struct sparx5 *sparx5, u32 id); 524 525 int sparx5_psfp_sf_add(struct sparx5 *sparx5, const struct sparx5_psfp_sf *sf, 526 u32 *id); 527 int sparx5_psfp_sf_del(struct sparx5 *sparx5, u32 id); 528 529 u32 sparx5_psfp_isdx_get_sf(struct sparx5 *sparx5, u32 isdx); 530 u32 sparx5_psfp_isdx_get_fm(struct sparx5 *sparx5, u32 isdx); 531 u32 sparx5_psfp_sf_get_sg(struct sparx5 *sparx5, u32 sfid); 532 void sparx5_isdx_conf_set(struct sparx5 *sparx5, u32 isdx, u32 sfid, u32 fmid); 533 534 void sparx5_psfp_init(struct sparx5 *sparx5); 535 536 /* sparx5_qos.c */ 537 void sparx5_new_base_time(struct sparx5 *sparx5, const u32 cycle_time, 538 const ktime_t org_base_time, ktime_t *new_base_time); 539 540 /* sparx5_mirror.c */ 541 int sparx5_mirror_add(struct sparx5_mall_entry *entry); 542 void sparx5_mirror_del(struct sparx5_mall_entry *entry); 543 void sparx5_mirror_stats(struct sparx5_mall_entry *entry, 544 struct flow_stats *fstats); 545 546 /* Clock period in picoseconds */ 547 static inline u32 sparx5_clk_period(enum sparx5_core_clockfreq cclock) 548 { 549 switch (cclock) { 550 case SPX5_CORE_CLOCK_250MHZ: 551 return 4000; 552 case SPX5_CORE_CLOCK_500MHZ: 553 return 2000; 554 case SPX5_CORE_CLOCK_625MHZ: 555 default: 556 return 1600; 557 } 558 } 559 560 static inline bool sparx5_is_baser(phy_interface_t interface) 561 { 562 return interface == PHY_INTERFACE_MODE_5GBASER || 563 interface == PHY_INTERFACE_MODE_10GBASER || 564 interface == PHY_INTERFACE_MODE_25GBASER; 565 } 566 567 extern const struct phylink_mac_ops sparx5_phylink_mac_ops; 568 extern const struct phylink_pcs_ops sparx5_phylink_pcs_ops; 569 extern const struct ethtool_ops sparx5_ethtool_ops; 570 extern const struct dcbnl_rtnl_ops sparx5_dcbnl_ops; 571 572 /* Calculate raw offset */ 573 static inline __pure int spx5_offset(int id, int tinst, int tcnt, 574 int gbase, int ginst, 575 int gcnt, int gwidth, 576 int raddr, int rinst, 577 int rcnt, int rwidth) 578 { 579 WARN_ON((tinst) >= tcnt); 580 WARN_ON((ginst) >= gcnt); 581 WARN_ON((rinst) >= rcnt); 582 return gbase + ((ginst) * gwidth) + 583 raddr + ((rinst) * rwidth); 584 } 585 586 /* Read, Write and modify registers content. 587 * The register definition macros start at the id 588 */ 589 static inline void __iomem *spx5_addr(void __iomem *base[], 590 int id, int tinst, int tcnt, 591 int gbase, int ginst, 592 int gcnt, int gwidth, 593 int raddr, int rinst, 594 int rcnt, int rwidth) 595 { 596 WARN_ON((tinst) >= tcnt); 597 WARN_ON((ginst) >= gcnt); 598 WARN_ON((rinst) >= rcnt); 599 return base[id + (tinst)] + 600 gbase + ((ginst) * gwidth) + 601 raddr + ((rinst) * rwidth); 602 } 603 604 static inline void __iomem *spx5_inst_addr(void __iomem *base, 605 int gbase, int ginst, 606 int gcnt, int gwidth, 607 int raddr, int rinst, 608 int rcnt, int rwidth) 609 { 610 WARN_ON((ginst) >= gcnt); 611 WARN_ON((rinst) >= rcnt); 612 return base + 613 gbase + ((ginst) * gwidth) + 614 raddr + ((rinst) * rwidth); 615 } 616 617 static inline u32 spx5_rd(struct sparx5 *sparx5, int id, int tinst, int tcnt, 618 int gbase, int ginst, int gcnt, int gwidth, 619 int raddr, int rinst, int rcnt, int rwidth) 620 { 621 return readl(spx5_addr(sparx5->regs, id, tinst, tcnt, gbase, ginst, 622 gcnt, gwidth, raddr, rinst, rcnt, rwidth)); 623 } 624 625 static inline u32 spx5_inst_rd(void __iomem *iomem, int id, int tinst, int tcnt, 626 int gbase, int ginst, int gcnt, int gwidth, 627 int raddr, int rinst, int rcnt, int rwidth) 628 { 629 return readl(spx5_inst_addr(iomem, gbase, ginst, 630 gcnt, gwidth, raddr, rinst, rcnt, rwidth)); 631 } 632 633 static inline void spx5_wr(u32 val, struct sparx5 *sparx5, 634 int id, int tinst, int tcnt, 635 int gbase, int ginst, int gcnt, int gwidth, 636 int raddr, int rinst, int rcnt, int rwidth) 637 { 638 writel(val, spx5_addr(sparx5->regs, id, tinst, tcnt, 639 gbase, ginst, gcnt, gwidth, 640 raddr, rinst, rcnt, rwidth)); 641 } 642 643 static inline void spx5_inst_wr(u32 val, void __iomem *iomem, 644 int id, int tinst, int tcnt, 645 int gbase, int ginst, int gcnt, int gwidth, 646 int raddr, int rinst, int rcnt, int rwidth) 647 { 648 writel(val, spx5_inst_addr(iomem, 649 gbase, ginst, gcnt, gwidth, 650 raddr, rinst, rcnt, rwidth)); 651 } 652 653 static inline void spx5_rmw(u32 val, u32 mask, struct sparx5 *sparx5, 654 int id, int tinst, int tcnt, 655 int gbase, int ginst, int gcnt, int gwidth, 656 int raddr, int rinst, int rcnt, int rwidth) 657 { 658 u32 nval; 659 660 nval = readl(spx5_addr(sparx5->regs, id, tinst, tcnt, gbase, ginst, 661 gcnt, gwidth, raddr, rinst, rcnt, rwidth)); 662 nval = (nval & ~mask) | (val & mask); 663 writel(nval, spx5_addr(sparx5->regs, id, tinst, tcnt, gbase, ginst, 664 gcnt, gwidth, raddr, rinst, rcnt, rwidth)); 665 } 666 667 static inline void spx5_inst_rmw(u32 val, u32 mask, void __iomem *iomem, 668 int id, int tinst, int tcnt, 669 int gbase, int ginst, int gcnt, int gwidth, 670 int raddr, int rinst, int rcnt, int rwidth) 671 { 672 u32 nval; 673 674 nval = readl(spx5_inst_addr(iomem, gbase, ginst, gcnt, gwidth, raddr, 675 rinst, rcnt, rwidth)); 676 nval = (nval & ~mask) | (val & mask); 677 writel(nval, spx5_inst_addr(iomem, gbase, ginst, gcnt, gwidth, raddr, 678 rinst, rcnt, rwidth)); 679 } 680 681 static inline void __iomem *spx5_inst_get(struct sparx5 *sparx5, int id, int tinst) 682 { 683 return sparx5->regs[id + tinst]; 684 } 685 686 static inline void __iomem *spx5_reg_get(struct sparx5 *sparx5, 687 int id, int tinst, int tcnt, 688 int gbase, int ginst, int gcnt, int gwidth, 689 int raddr, int rinst, int rcnt, int rwidth) 690 { 691 return spx5_addr(sparx5->regs, id, tinst, tcnt, 692 gbase, ginst, gcnt, gwidth, 693 raddr, rinst, rcnt, rwidth); 694 } 695 696 #endif /* __SPARX5_MAIN_H__ */ 697