1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Microchip Sparx5 Switch driver 3 * 4 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. 5 * 6 * The Sparx5 Chip Register Model can be browsed at this location: 7 * https://github.com/microchip-ung/sparx-5_reginfo 8 */ 9 #include <linux/module.h> 10 #include <linux/device.h> 11 #include <linux/netdevice.h> 12 #include <linux/platform_device.h> 13 #include <linux/interrupt.h> 14 #include <linux/of.h> 15 #include <linux/of_net.h> 16 #include <linux/of_mdio.h> 17 #include <net/switchdev.h> 18 #include <linux/etherdevice.h> 19 #include <linux/io.h> 20 #include <linux/printk.h> 21 #include <linux/iopoll.h> 22 #include <linux/mfd/syscon.h> 23 #include <linux/regmap.h> 24 #include <linux/types.h> 25 #include <linux/reset.h> 26 27 #include "sparx5_main_regs.h" 28 #include "sparx5_main.h" 29 #include "sparx5_port.h" 30 #include "sparx5_qos.h" 31 32 const struct sparx5_regs *regs; 33 34 #define IO_RANGES 3 35 36 struct initial_port_config { 37 u32 portno; 38 struct device_node *node; 39 struct sparx5_port_config conf; 40 struct phy *serdes; 41 }; 42 43 struct sparx5_ram_config { 44 void __iomem *init_reg; 45 u32 init_val; 46 }; 47 48 static const struct sparx5_main_io_resource sparx5_main_iomap[] = { 49 { TARGET_CPU, 0, 0 }, /* 0x600000000 */ 50 { TARGET_FDMA, 0x80000, 0 }, /* 0x600080000 */ 51 { TARGET_PCEP, 0x400000, 0 }, /* 0x600400000 */ 52 { TARGET_DEV2G5, 0x10004000, 1 }, /* 0x610004000 */ 53 { TARGET_DEV5G, 0x10008000, 1 }, /* 0x610008000 */ 54 { TARGET_PCS5G_BR, 0x1000c000, 1 }, /* 0x61000c000 */ 55 { TARGET_DEV2G5 + 1, 0x10010000, 1 }, /* 0x610010000 */ 56 { TARGET_DEV5G + 1, 0x10014000, 1 }, /* 0x610014000 */ 57 { TARGET_PCS5G_BR + 1, 0x10018000, 1 }, /* 0x610018000 */ 58 { TARGET_DEV2G5 + 2, 0x1001c000, 1 }, /* 0x61001c000 */ 59 { TARGET_DEV5G + 2, 0x10020000, 1 }, /* 0x610020000 */ 60 { TARGET_PCS5G_BR + 2, 0x10024000, 1 }, /* 0x610024000 */ 61 { TARGET_DEV2G5 + 6, 0x10028000, 1 }, /* 0x610028000 */ 62 { TARGET_DEV5G + 6, 0x1002c000, 1 }, /* 0x61002c000 */ 63 { TARGET_PCS5G_BR + 6, 0x10030000, 1 }, /* 0x610030000 */ 64 { TARGET_DEV2G5 + 7, 0x10034000, 1 }, /* 0x610034000 */ 65 { TARGET_DEV5G + 7, 0x10038000, 1 }, /* 0x610038000 */ 66 { TARGET_PCS5G_BR + 7, 0x1003c000, 1 }, /* 0x61003c000 */ 67 { TARGET_DEV2G5 + 8, 0x10040000, 1 }, /* 0x610040000 */ 68 { TARGET_DEV5G + 8, 0x10044000, 1 }, /* 0x610044000 */ 69 { TARGET_PCS5G_BR + 8, 0x10048000, 1 }, /* 0x610048000 */ 70 { TARGET_DEV2G5 + 9, 0x1004c000, 1 }, /* 0x61004c000 */ 71 { TARGET_DEV5G + 9, 0x10050000, 1 }, /* 0x610050000 */ 72 { TARGET_PCS5G_BR + 9, 0x10054000, 1 }, /* 0x610054000 */ 73 { TARGET_DEV2G5 + 10, 0x10058000, 1 }, /* 0x610058000 */ 74 { TARGET_DEV5G + 10, 0x1005c000, 1 }, /* 0x61005c000 */ 75 { TARGET_PCS5G_BR + 10, 0x10060000, 1 }, /* 0x610060000 */ 76 { TARGET_DEV2G5 + 11, 0x10064000, 1 }, /* 0x610064000 */ 77 { TARGET_DEV5G + 11, 0x10068000, 1 }, /* 0x610068000 */ 78 { TARGET_PCS5G_BR + 11, 0x1006c000, 1 }, /* 0x61006c000 */ 79 { TARGET_DEV2G5 + 12, 0x10070000, 1 }, /* 0x610070000 */ 80 { TARGET_DEV10G, 0x10074000, 1 }, /* 0x610074000 */ 81 { TARGET_PCS10G_BR, 0x10078000, 1 }, /* 0x610078000 */ 82 { TARGET_DEV2G5 + 14, 0x1007c000, 1 }, /* 0x61007c000 */ 83 { TARGET_DEV10G + 2, 0x10080000, 1 }, /* 0x610080000 */ 84 { TARGET_PCS10G_BR + 2, 0x10084000, 1 }, /* 0x610084000 */ 85 { TARGET_DEV2G5 + 15, 0x10088000, 1 }, /* 0x610088000 */ 86 { TARGET_DEV10G + 3, 0x1008c000, 1 }, /* 0x61008c000 */ 87 { TARGET_PCS10G_BR + 3, 0x10090000, 1 }, /* 0x610090000 */ 88 { TARGET_DEV2G5 + 16, 0x10094000, 1 }, /* 0x610094000 */ 89 { TARGET_DEV2G5 + 17, 0x10098000, 1 }, /* 0x610098000 */ 90 { TARGET_DEV2G5 + 18, 0x1009c000, 1 }, /* 0x61009c000 */ 91 { TARGET_DEV2G5 + 19, 0x100a0000, 1 }, /* 0x6100a0000 */ 92 { TARGET_DEV2G5 + 20, 0x100a4000, 1 }, /* 0x6100a4000 */ 93 { TARGET_DEV2G5 + 21, 0x100a8000, 1 }, /* 0x6100a8000 */ 94 { TARGET_DEV2G5 + 22, 0x100ac000, 1 }, /* 0x6100ac000 */ 95 { TARGET_DEV2G5 + 23, 0x100b0000, 1 }, /* 0x6100b0000 */ 96 { TARGET_DEV2G5 + 32, 0x100b4000, 1 }, /* 0x6100b4000 */ 97 { TARGET_DEV2G5 + 33, 0x100b8000, 1 }, /* 0x6100b8000 */ 98 { TARGET_DEV2G5 + 34, 0x100bc000, 1 }, /* 0x6100bc000 */ 99 { TARGET_DEV2G5 + 35, 0x100c0000, 1 }, /* 0x6100c0000 */ 100 { TARGET_DEV2G5 + 36, 0x100c4000, 1 }, /* 0x6100c4000 */ 101 { TARGET_DEV2G5 + 37, 0x100c8000, 1 }, /* 0x6100c8000 */ 102 { TARGET_DEV2G5 + 38, 0x100cc000, 1 }, /* 0x6100cc000 */ 103 { TARGET_DEV2G5 + 39, 0x100d0000, 1 }, /* 0x6100d0000 */ 104 { TARGET_DEV2G5 + 40, 0x100d4000, 1 }, /* 0x6100d4000 */ 105 { TARGET_DEV2G5 + 41, 0x100d8000, 1 }, /* 0x6100d8000 */ 106 { TARGET_DEV2G5 + 42, 0x100dc000, 1 }, /* 0x6100dc000 */ 107 { TARGET_DEV2G5 + 43, 0x100e0000, 1 }, /* 0x6100e0000 */ 108 { TARGET_DEV2G5 + 44, 0x100e4000, 1 }, /* 0x6100e4000 */ 109 { TARGET_DEV2G5 + 45, 0x100e8000, 1 }, /* 0x6100e8000 */ 110 { TARGET_DEV2G5 + 46, 0x100ec000, 1 }, /* 0x6100ec000 */ 111 { TARGET_DEV2G5 + 47, 0x100f0000, 1 }, /* 0x6100f0000 */ 112 { TARGET_DEV2G5 + 57, 0x100f4000, 1 }, /* 0x6100f4000 */ 113 { TARGET_DEV25G + 1, 0x100f8000, 1 }, /* 0x6100f8000 */ 114 { TARGET_PCS25G_BR + 1, 0x100fc000, 1 }, /* 0x6100fc000 */ 115 { TARGET_DEV2G5 + 59, 0x10104000, 1 }, /* 0x610104000 */ 116 { TARGET_DEV25G + 3, 0x10108000, 1 }, /* 0x610108000 */ 117 { TARGET_PCS25G_BR + 3, 0x1010c000, 1 }, /* 0x61010c000 */ 118 { TARGET_DEV2G5 + 60, 0x10114000, 1 }, /* 0x610114000 */ 119 { TARGET_DEV25G + 4, 0x10118000, 1 }, /* 0x610118000 */ 120 { TARGET_PCS25G_BR + 4, 0x1011c000, 1 }, /* 0x61011c000 */ 121 { TARGET_DEV2G5 + 64, 0x10124000, 1 }, /* 0x610124000 */ 122 { TARGET_DEV5G + 12, 0x10128000, 1 }, /* 0x610128000 */ 123 { TARGET_PCS5G_BR + 12, 0x1012c000, 1 }, /* 0x61012c000 */ 124 { TARGET_PORT_CONF, 0x10130000, 1 }, /* 0x610130000 */ 125 { TARGET_DEV2G5 + 3, 0x10404000, 1 }, /* 0x610404000 */ 126 { TARGET_DEV5G + 3, 0x10408000, 1 }, /* 0x610408000 */ 127 { TARGET_PCS5G_BR + 3, 0x1040c000, 1 }, /* 0x61040c000 */ 128 { TARGET_DEV2G5 + 4, 0x10410000, 1 }, /* 0x610410000 */ 129 { TARGET_DEV5G + 4, 0x10414000, 1 }, /* 0x610414000 */ 130 { TARGET_PCS5G_BR + 4, 0x10418000, 1 }, /* 0x610418000 */ 131 { TARGET_DEV2G5 + 5, 0x1041c000, 1 }, /* 0x61041c000 */ 132 { TARGET_DEV5G + 5, 0x10420000, 1 }, /* 0x610420000 */ 133 { TARGET_PCS5G_BR + 5, 0x10424000, 1 }, /* 0x610424000 */ 134 { TARGET_DEV2G5 + 13, 0x10428000, 1 }, /* 0x610428000 */ 135 { TARGET_DEV10G + 1, 0x1042c000, 1 }, /* 0x61042c000 */ 136 { TARGET_PCS10G_BR + 1, 0x10430000, 1 }, /* 0x610430000 */ 137 { TARGET_DEV2G5 + 24, 0x10434000, 1 }, /* 0x610434000 */ 138 { TARGET_DEV2G5 + 25, 0x10438000, 1 }, /* 0x610438000 */ 139 { TARGET_DEV2G5 + 26, 0x1043c000, 1 }, /* 0x61043c000 */ 140 { TARGET_DEV2G5 + 27, 0x10440000, 1 }, /* 0x610440000 */ 141 { TARGET_DEV2G5 + 28, 0x10444000, 1 }, /* 0x610444000 */ 142 { TARGET_DEV2G5 + 29, 0x10448000, 1 }, /* 0x610448000 */ 143 { TARGET_DEV2G5 + 30, 0x1044c000, 1 }, /* 0x61044c000 */ 144 { TARGET_DEV2G5 + 31, 0x10450000, 1 }, /* 0x610450000 */ 145 { TARGET_DEV2G5 + 48, 0x10454000, 1 }, /* 0x610454000 */ 146 { TARGET_DEV10G + 4, 0x10458000, 1 }, /* 0x610458000 */ 147 { TARGET_PCS10G_BR + 4, 0x1045c000, 1 }, /* 0x61045c000 */ 148 { TARGET_DEV2G5 + 49, 0x10460000, 1 }, /* 0x610460000 */ 149 { TARGET_DEV10G + 5, 0x10464000, 1 }, /* 0x610464000 */ 150 { TARGET_PCS10G_BR + 5, 0x10468000, 1 }, /* 0x610468000 */ 151 { TARGET_DEV2G5 + 50, 0x1046c000, 1 }, /* 0x61046c000 */ 152 { TARGET_DEV10G + 6, 0x10470000, 1 }, /* 0x610470000 */ 153 { TARGET_PCS10G_BR + 6, 0x10474000, 1 }, /* 0x610474000 */ 154 { TARGET_DEV2G5 + 51, 0x10478000, 1 }, /* 0x610478000 */ 155 { TARGET_DEV10G + 7, 0x1047c000, 1 }, /* 0x61047c000 */ 156 { TARGET_PCS10G_BR + 7, 0x10480000, 1 }, /* 0x610480000 */ 157 { TARGET_DEV2G5 + 52, 0x10484000, 1 }, /* 0x610484000 */ 158 { TARGET_DEV10G + 8, 0x10488000, 1 }, /* 0x610488000 */ 159 { TARGET_PCS10G_BR + 8, 0x1048c000, 1 }, /* 0x61048c000 */ 160 { TARGET_DEV2G5 + 53, 0x10490000, 1 }, /* 0x610490000 */ 161 { TARGET_DEV10G + 9, 0x10494000, 1 }, /* 0x610494000 */ 162 { TARGET_PCS10G_BR + 9, 0x10498000, 1 }, /* 0x610498000 */ 163 { TARGET_DEV2G5 + 54, 0x1049c000, 1 }, /* 0x61049c000 */ 164 { TARGET_DEV10G + 10, 0x104a0000, 1 }, /* 0x6104a0000 */ 165 { TARGET_PCS10G_BR + 10, 0x104a4000, 1 }, /* 0x6104a4000 */ 166 { TARGET_DEV2G5 + 55, 0x104a8000, 1 }, /* 0x6104a8000 */ 167 { TARGET_DEV10G + 11, 0x104ac000, 1 }, /* 0x6104ac000 */ 168 { TARGET_PCS10G_BR + 11, 0x104b0000, 1 }, /* 0x6104b0000 */ 169 { TARGET_DEV2G5 + 56, 0x104b4000, 1 }, /* 0x6104b4000 */ 170 { TARGET_DEV25G, 0x104b8000, 1 }, /* 0x6104b8000 */ 171 { TARGET_PCS25G_BR, 0x104bc000, 1 }, /* 0x6104bc000 */ 172 { TARGET_DEV2G5 + 58, 0x104c4000, 1 }, /* 0x6104c4000 */ 173 { TARGET_DEV25G + 2, 0x104c8000, 1 }, /* 0x6104c8000 */ 174 { TARGET_PCS25G_BR + 2, 0x104cc000, 1 }, /* 0x6104cc000 */ 175 { TARGET_DEV2G5 + 61, 0x104d4000, 1 }, /* 0x6104d4000 */ 176 { TARGET_DEV25G + 5, 0x104d8000, 1 }, /* 0x6104d8000 */ 177 { TARGET_PCS25G_BR + 5, 0x104dc000, 1 }, /* 0x6104dc000 */ 178 { TARGET_DEV2G5 + 62, 0x104e4000, 1 }, /* 0x6104e4000 */ 179 { TARGET_DEV25G + 6, 0x104e8000, 1 }, /* 0x6104e8000 */ 180 { TARGET_PCS25G_BR + 6, 0x104ec000, 1 }, /* 0x6104ec000 */ 181 { TARGET_DEV2G5 + 63, 0x104f4000, 1 }, /* 0x6104f4000 */ 182 { TARGET_DEV25G + 7, 0x104f8000, 1 }, /* 0x6104f8000 */ 183 { TARGET_PCS25G_BR + 7, 0x104fc000, 1 }, /* 0x6104fc000 */ 184 { TARGET_DSM, 0x10504000, 1 }, /* 0x610504000 */ 185 { TARGET_ASM, 0x10600000, 1 }, /* 0x610600000 */ 186 { TARGET_GCB, 0x11010000, 2 }, /* 0x611010000 */ 187 { TARGET_QS, 0x11030000, 2 }, /* 0x611030000 */ 188 { TARGET_PTP, 0x11040000, 2 }, /* 0x611040000 */ 189 { TARGET_ANA_ACL, 0x11050000, 2 }, /* 0x611050000 */ 190 { TARGET_LRN, 0x11060000, 2 }, /* 0x611060000 */ 191 { TARGET_VCAP_SUPER, 0x11080000, 2 }, /* 0x611080000 */ 192 { TARGET_QSYS, 0x110a0000, 2 }, /* 0x6110a0000 */ 193 { TARGET_QFWD, 0x110b0000, 2 }, /* 0x6110b0000 */ 194 { TARGET_XQS, 0x110c0000, 2 }, /* 0x6110c0000 */ 195 { TARGET_VCAP_ES2, 0x110d0000, 2 }, /* 0x6110d0000 */ 196 { TARGET_VCAP_ES0, 0x110e0000, 2 }, /* 0x6110e0000 */ 197 { TARGET_CLKGEN, 0x11100000, 2 }, /* 0x611100000 */ 198 { TARGET_ANA_AC_POL, 0x11200000, 2 }, /* 0x611200000 */ 199 { TARGET_QRES, 0x11280000, 2 }, /* 0x611280000 */ 200 { TARGET_EACL, 0x112c0000, 2 }, /* 0x6112c0000 */ 201 { TARGET_ANA_CL, 0x11400000, 2 }, /* 0x611400000 */ 202 { TARGET_ANA_L3, 0x11480000, 2 }, /* 0x611480000 */ 203 { TARGET_ANA_AC_SDLB, 0x11500000, 2 }, /* 0x611500000 */ 204 { TARGET_HSCH, 0x11580000, 2 }, /* 0x611580000 */ 205 { TARGET_REW, 0x11600000, 2 }, /* 0x611600000 */ 206 { TARGET_ANA_L2, 0x11800000, 2 }, /* 0x611800000 */ 207 { TARGET_ANA_AC, 0x11900000, 2 }, /* 0x611900000 */ 208 { TARGET_VOP, 0x11a00000, 2 }, /* 0x611a00000 */ 209 }; 210 211 bool is_sparx5(struct sparx5 *sparx5) 212 { 213 switch (sparx5->target_ct) { 214 case SPX5_TARGET_CT_7546: 215 case SPX5_TARGET_CT_7549: 216 case SPX5_TARGET_CT_7552: 217 case SPX5_TARGET_CT_7556: 218 case SPX5_TARGET_CT_7558: 219 case SPX5_TARGET_CT_7546TSN: 220 case SPX5_TARGET_CT_7549TSN: 221 case SPX5_TARGET_CT_7552TSN: 222 case SPX5_TARGET_CT_7556TSN: 223 case SPX5_TARGET_CT_7558TSN: 224 return true; 225 default: 226 return false; 227 } 228 } 229 230 static int sparx5_create_targets(struct sparx5 *sparx5) 231 { 232 const struct sparx5_main_io_resource *iomap = sparx5->data->iomap; 233 int iomap_size = sparx5->data->iomap_size; 234 int ioranges = sparx5->data->ioranges; 235 struct resource *iores[IO_RANGES]; 236 void __iomem *iomem[IO_RANGES]; 237 void __iomem *begin[IO_RANGES]; 238 int range_id[IO_RANGES]; 239 int idx, jdx; 240 241 for (idx = 0, jdx = 0; jdx < iomap_size; jdx++) { 242 const struct sparx5_main_io_resource *io = &iomap[jdx]; 243 244 if (idx == io->range) { 245 range_id[idx] = jdx; 246 idx++; 247 } 248 } 249 for (idx = 0; idx < ioranges; idx++) { 250 iores[idx] = platform_get_resource(sparx5->pdev, IORESOURCE_MEM, 251 idx); 252 if (!iores[idx]) { 253 dev_err(sparx5->dev, "Invalid resource\n"); 254 return -EINVAL; 255 } 256 iomem[idx] = devm_ioremap(sparx5->dev, 257 iores[idx]->start, 258 resource_size(iores[idx])); 259 if (!iomem[idx]) { 260 dev_err(sparx5->dev, "Unable to get switch registers: %s\n", 261 iores[idx]->name); 262 return -ENOMEM; 263 } 264 begin[idx] = iomem[idx] - iomap[range_id[idx]].offset; 265 } 266 for (jdx = 0; jdx < iomap_size; jdx++) { 267 const struct sparx5_main_io_resource *io = &iomap[jdx]; 268 269 sparx5->regs[io->id] = begin[io->range] + io->offset; 270 } 271 return 0; 272 } 273 274 static int sparx5_create_port(struct sparx5 *sparx5, 275 struct initial_port_config *config) 276 { 277 struct sparx5_port *spx5_port; 278 struct net_device *ndev; 279 struct phylink *phylink; 280 int err; 281 282 ndev = sparx5_create_netdev(sparx5, config->portno); 283 if (IS_ERR(ndev)) { 284 dev_err(sparx5->dev, "Could not create net device: %02u\n", 285 config->portno); 286 return PTR_ERR(ndev); 287 } 288 spx5_port = netdev_priv(ndev); 289 spx5_port->of_node = config->node; 290 spx5_port->serdes = config->serdes; 291 spx5_port->pvid = NULL_VID; 292 spx5_port->signd_internal = true; 293 spx5_port->signd_active_high = true; 294 spx5_port->signd_enable = true; 295 spx5_port->max_vlan_tags = SPX5_PORT_MAX_TAGS_NONE; 296 spx5_port->vlan_type = SPX5_VLAN_PORT_TYPE_UNAWARE; 297 spx5_port->custom_etype = 0x8880; /* Vitesse */ 298 spx5_port->phylink_pcs.poll = true; 299 spx5_port->phylink_pcs.ops = &sparx5_phylink_pcs_ops; 300 spx5_port->phylink_pcs.neg_mode = true; 301 spx5_port->is_mrouter = false; 302 INIT_LIST_HEAD(&spx5_port->tc_templates); 303 sparx5->ports[config->portno] = spx5_port; 304 305 err = sparx5_port_init(sparx5, spx5_port, &config->conf); 306 if (err) { 307 dev_err(sparx5->dev, "port init failed\n"); 308 return err; 309 } 310 spx5_port->conf = config->conf; 311 312 /* Setup VLAN */ 313 sparx5_vlan_port_setup(sparx5, spx5_port->portno); 314 315 /* Create a phylink for PHY management. Also handles SFPs */ 316 spx5_port->phylink_config.dev = &spx5_port->ndev->dev; 317 spx5_port->phylink_config.type = PHYLINK_NETDEV; 318 spx5_port->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | 319 MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000FD | 320 MAC_2500FD | MAC_5000FD | MAC_10000FD | MAC_25000FD; 321 322 __set_bit(PHY_INTERFACE_MODE_SGMII, 323 spx5_port->phylink_config.supported_interfaces); 324 __set_bit(PHY_INTERFACE_MODE_QSGMII, 325 spx5_port->phylink_config.supported_interfaces); 326 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 327 spx5_port->phylink_config.supported_interfaces); 328 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 329 spx5_port->phylink_config.supported_interfaces); 330 331 if (spx5_port->conf.bandwidth == SPEED_5000 || 332 spx5_port->conf.bandwidth == SPEED_10000 || 333 spx5_port->conf.bandwidth == SPEED_25000) 334 __set_bit(PHY_INTERFACE_MODE_5GBASER, 335 spx5_port->phylink_config.supported_interfaces); 336 337 if (spx5_port->conf.bandwidth == SPEED_10000 || 338 spx5_port->conf.bandwidth == SPEED_25000) 339 __set_bit(PHY_INTERFACE_MODE_10GBASER, 340 spx5_port->phylink_config.supported_interfaces); 341 342 if (spx5_port->conf.bandwidth == SPEED_25000) 343 __set_bit(PHY_INTERFACE_MODE_25GBASER, 344 spx5_port->phylink_config.supported_interfaces); 345 346 phylink = phylink_create(&spx5_port->phylink_config, 347 of_fwnode_handle(config->node), 348 config->conf.phy_mode, 349 &sparx5_phylink_mac_ops); 350 if (IS_ERR(phylink)) 351 return PTR_ERR(phylink); 352 353 spx5_port->phylink = phylink; 354 355 return 0; 356 } 357 358 static int sparx5_init_ram(struct sparx5 *s5) 359 { 360 const struct sparx5_ram_config spx5_ram_cfg[] = { 361 {spx5_reg_get(s5, ANA_AC_STAT_RESET), ANA_AC_STAT_RESET_RESET}, 362 {spx5_reg_get(s5, ASM_STAT_CFG), ASM_STAT_CFG_STAT_CNT_CLR_SHOT}, 363 {spx5_reg_get(s5, QSYS_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}, 364 {spx5_reg_get(s5, REW_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}, 365 {spx5_reg_get(s5, VOP_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}, 366 {spx5_reg_get(s5, ANA_AC_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}, 367 {spx5_reg_get(s5, ASM_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}, 368 {spx5_reg_get(s5, EACL_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}, 369 {spx5_reg_get(s5, VCAP_SUPER_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}, 370 {spx5_reg_get(s5, DSM_RAM_INIT), QSYS_RAM_INIT_RAM_INIT} 371 }; 372 const struct sparx5_ram_config *cfg; 373 u32 value, pending, jdx, idx; 374 375 for (jdx = 0; jdx < 10; jdx++) { 376 pending = ARRAY_SIZE(spx5_ram_cfg); 377 for (idx = 0; idx < ARRAY_SIZE(spx5_ram_cfg); idx++) { 378 cfg = &spx5_ram_cfg[idx]; 379 if (jdx == 0) { 380 writel(cfg->init_val, cfg->init_reg); 381 } else { 382 value = readl(cfg->init_reg); 383 if ((value & cfg->init_val) != cfg->init_val) 384 pending--; 385 } 386 } 387 if (!pending) 388 break; 389 usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC); 390 } 391 392 if (pending > 0) { 393 /* Still initializing, should be complete in 394 * less than 1ms 395 */ 396 dev_err(s5->dev, "Memory initialization error\n"); 397 return -EINVAL; 398 } 399 return 0; 400 } 401 402 static int sparx5_init_switchcore(struct sparx5 *sparx5) 403 { 404 u32 value; 405 int err = 0; 406 407 spx5_rmw(EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(1), 408 EACL_POL_EACL_CFG_EACL_FORCE_INIT, 409 sparx5, 410 EACL_POL_EACL_CFG); 411 412 spx5_rmw(EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(0), 413 EACL_POL_EACL_CFG_EACL_FORCE_INIT, 414 sparx5, 415 EACL_POL_EACL_CFG); 416 417 /* Initialize memories, if not done already */ 418 value = spx5_rd(sparx5, HSCH_RESET_CFG); 419 if (!(value & HSCH_RESET_CFG_CORE_ENA)) { 420 err = sparx5_init_ram(sparx5); 421 if (err) 422 return err; 423 } 424 425 /* Reset counters */ 426 spx5_wr(ANA_AC_STAT_RESET_RESET_SET(1), sparx5, ANA_AC_STAT_RESET); 427 spx5_wr(ASM_STAT_CFG_STAT_CNT_CLR_SHOT_SET(1), sparx5, ASM_STAT_CFG); 428 429 /* Enable switch-core and queue system */ 430 spx5_wr(HSCH_RESET_CFG_CORE_ENA_SET(1), sparx5, HSCH_RESET_CFG); 431 432 return 0; 433 } 434 435 static int sparx5_init_coreclock(struct sparx5 *sparx5) 436 { 437 enum sparx5_core_clockfreq freq = sparx5->coreclock; 438 u32 clk_div, clk_period, pol_upd_int, idx; 439 440 /* Verify if core clock frequency is supported on target. 441 * If 'VTSS_CORE_CLOCK_DEFAULT' then the highest supported 442 * freq. is used 443 */ 444 switch (sparx5->target_ct) { 445 case SPX5_TARGET_CT_7546: 446 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) 447 freq = SPX5_CORE_CLOCK_250MHZ; 448 else if (sparx5->coreclock != SPX5_CORE_CLOCK_250MHZ) 449 freq = 0; /* Not supported */ 450 break; 451 case SPX5_TARGET_CT_7549: 452 case SPX5_TARGET_CT_7552: 453 case SPX5_TARGET_CT_7556: 454 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) 455 freq = SPX5_CORE_CLOCK_500MHZ; 456 else if (sparx5->coreclock != SPX5_CORE_CLOCK_500MHZ) 457 freq = 0; /* Not supported */ 458 break; 459 case SPX5_TARGET_CT_7558: 460 case SPX5_TARGET_CT_7558TSN: 461 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) 462 freq = SPX5_CORE_CLOCK_625MHZ; 463 else if (sparx5->coreclock != SPX5_CORE_CLOCK_625MHZ) 464 freq = 0; /* Not supported */ 465 break; 466 case SPX5_TARGET_CT_7546TSN: 467 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) 468 freq = SPX5_CORE_CLOCK_625MHZ; 469 break; 470 case SPX5_TARGET_CT_7549TSN: 471 case SPX5_TARGET_CT_7552TSN: 472 case SPX5_TARGET_CT_7556TSN: 473 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) 474 freq = SPX5_CORE_CLOCK_625MHZ; 475 else if (sparx5->coreclock == SPX5_CORE_CLOCK_250MHZ) 476 freq = 0; /* Not supported */ 477 break; 478 default: 479 dev_err(sparx5->dev, "Target (%#04x) not supported\n", 480 sparx5->target_ct); 481 return -ENODEV; 482 } 483 484 if (is_sparx5(sparx5)) { 485 switch (freq) { 486 case SPX5_CORE_CLOCK_250MHZ: 487 clk_div = 10; 488 pol_upd_int = 312; 489 break; 490 case SPX5_CORE_CLOCK_500MHZ: 491 clk_div = 5; 492 pol_upd_int = 624; 493 break; 494 case SPX5_CORE_CLOCK_625MHZ: 495 clk_div = 4; 496 pol_upd_int = 780; 497 break; 498 default: 499 dev_err(sparx5->dev, 500 "%d coreclock not supported on (%#04x)\n", 501 sparx5->coreclock, sparx5->target_ct); 502 return -EINVAL; 503 } 504 505 /* Configure the LCPLL */ 506 spx5_rmw(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(clk_div) | 507 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_SET(0) | 508 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_SET(0) | 509 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_SET(0) | 510 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_SET(0) | 511 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_SET(1), 512 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV | 513 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV | 514 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR | 515 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL | 516 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA | 517 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, 518 sparx5, CLKGEN_LCPLL1_CORE_CLK_CFG); 519 } 520 521 /* Update state with chosen frequency */ 522 sparx5->coreclock = freq; 523 clk_period = sparx5_clk_period(freq); 524 525 spx5_rmw(HSCH_SYS_CLK_PER_100PS_SET(clk_period / 100), 526 HSCH_SYS_CLK_PER_100PS, 527 sparx5, 528 HSCH_SYS_CLK_PER); 529 530 spx5_rmw(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_SET(clk_period / 100), 531 ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS, 532 sparx5, 533 ANA_AC_POL_BDLB_DLB_CTRL); 534 535 spx5_rmw(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_SET(clk_period / 100), 536 ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS, 537 sparx5, 538 ANA_AC_POL_SLB_DLB_CTRL); 539 540 spx5_rmw(LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_SET(clk_period / 100), 541 LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS, 542 sparx5, 543 LRN_AUTOAGE_CFG_1); 544 545 for (idx = 0; idx < sparx5->data->consts->n_sio_clks; idx++) 546 spx5_rmw(GCB_SIO_CLOCK_SYS_CLK_PERIOD_SET(clk_period / 100), 547 GCB_SIO_CLOCK_SYS_CLK_PERIOD, 548 sparx5, 549 GCB_SIO_CLOCK(idx)); 550 551 spx5_rmw(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_SET 552 ((256 * 1000) / clk_period), 553 HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY, 554 sparx5, 555 HSCH_TAS_STATEMACHINE_CFG); 556 557 spx5_rmw(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_SET(pol_upd_int), 558 ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT, 559 sparx5, 560 ANA_AC_POL_POL_UPD_INT_CFG); 561 562 return 0; 563 } 564 565 static u32 qlim_wm(struct sparx5 *sparx5, int fraction) 566 { 567 return (sparx5->data->consts->buf_size / SPX5_BUFFER_CELL_SZ - 100) * 568 fraction / 100; 569 } 570 571 static int sparx5_qlim_set(struct sparx5 *sparx5) 572 { 573 const struct sparx5_consts *consts = sparx5->data->consts; 574 u32 res, dp, prio; 575 576 for (res = 0; res < 2; res++) { 577 for (prio = 0; prio < 8; prio++) 578 spx5_wr(0xFFF, sparx5, 579 QRES_RES_CFG(prio + 580 consts->qres_max_prio_idx + 581 res * 1024)); 582 583 for (dp = 0; dp < 4; dp++) 584 spx5_wr(0xFFF, sparx5, 585 QRES_RES_CFG(dp + 586 consts->qres_max_colour_idx + 587 res * 1024)); 588 } 589 590 /* Set 80,90,95,100% of memory size for top watermarks */ 591 spx5_wr(qlim_wm(sparx5, 80), sparx5, XQS_QLIMIT_SHR_QLIM_CFG(0)); 592 spx5_wr(qlim_wm(sparx5, 90), sparx5, XQS_QLIMIT_SHR_CTOP_CFG(0)); 593 spx5_wr(qlim_wm(sparx5, 95), sparx5, XQS_QLIMIT_SHR_ATOP_CFG(0)); 594 spx5_wr(qlim_wm(sparx5, 100), sparx5, XQS_QLIMIT_SHR_TOP_CFG(0)); 595 596 return 0; 597 } 598 599 /* Some boards needs to map the SGPIO for signal detect explicitly to the 600 * port module 601 */ 602 static void sparx5_board_init(struct sparx5 *sparx5) 603 { 604 int idx; 605 606 if (!sparx5->sd_sgpio_remapping) 607 return; 608 609 /* Enable SGPIO Signal Detect remapping */ 610 spx5_rmw(GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL, 611 GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL, 612 sparx5, 613 GCB_HW_SGPIO_SD_CFG); 614 615 /* Refer to LOS SGPIO */ 616 for (idx = 0; idx < sparx5->data->consts->n_ports; idx++) 617 if (sparx5->ports[idx]) 618 if (sparx5->ports[idx]->conf.sd_sgpio != ~0) 619 spx5_wr(sparx5->ports[idx]->conf.sd_sgpio, 620 sparx5, 621 GCB_HW_SGPIO_TO_SD_MAP_CFG(idx)); 622 } 623 624 static int sparx5_start(struct sparx5 *sparx5) 625 { 626 u8 broadcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 627 const struct sparx5_consts *consts = sparx5->data->consts; 628 const struct sparx5_ops *ops = sparx5->data->ops; 629 char queue_name[32]; 630 u32 idx; 631 int err; 632 633 /* Setup own UPSIDs */ 634 for (idx = 0; idx < consts->n_own_upsids; idx++) { 635 spx5_wr(idx, sparx5, ANA_AC_OWN_UPSID(idx)); 636 spx5_wr(idx, sparx5, ANA_CL_OWN_UPSID(idx)); 637 spx5_wr(idx, sparx5, ANA_L2_OWN_UPSID(idx)); 638 spx5_wr(idx, sparx5, REW_OWN_UPSID(idx)); 639 } 640 641 /* Enable CPU ports */ 642 for (idx = consts->n_ports; idx < consts->n_ports_all; idx++) 643 spx5_rmw(QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(1), 644 QFWD_SWITCH_PORT_MODE_PORT_ENA, 645 sparx5, 646 QFWD_SWITCH_PORT_MODE(idx)); 647 648 /* Init masks */ 649 sparx5_update_fwd(sparx5); 650 651 /* CPU copy CPU pgids */ 652 spx5_wr(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1), sparx5, 653 ANA_AC_PGID_MISC_CFG(sparx5_get_pgid(sparx5, PGID_CPU))); 654 spx5_wr(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1), sparx5, 655 ANA_AC_PGID_MISC_CFG(sparx5_get_pgid(sparx5, PGID_BCAST))); 656 657 /* Recalc injected frame FCS */ 658 for (idx = sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_0); 659 idx <= sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_1); idx++) 660 spx5_rmw(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_SET(1), 661 ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA, 662 sparx5, ANA_CL_FILTER_CTRL(idx)); 663 664 /* Init MAC table, ageing */ 665 sparx5_mact_init(sparx5); 666 667 /* Init PGID table arbitrator */ 668 sparx5_pgid_init(sparx5); 669 670 /* Setup VLANs */ 671 sparx5_vlan_init(sparx5); 672 673 /* Add host mode BC address (points only to CPU) */ 674 sparx5_mact_learn(sparx5, sparx5_get_pgid(sparx5, PGID_CPU), broadcast, 675 NULL_VID); 676 677 /* Enable queue limitation watermarks */ 678 sparx5_qlim_set(sparx5); 679 680 err = sparx5_config_auto_calendar(sparx5); 681 if (err) 682 return err; 683 684 err = sparx5_config_dsm_calendar(sparx5); 685 if (err) 686 return err; 687 688 /* Init stats */ 689 err = sparx_stats_init(sparx5); 690 if (err) 691 return err; 692 693 /* Init mact_sw struct */ 694 mutex_init(&sparx5->mact_lock); 695 INIT_LIST_HEAD(&sparx5->mact_entries); 696 snprintf(queue_name, sizeof(queue_name), "%s-mact", 697 dev_name(sparx5->dev)); 698 sparx5->mact_queue = create_singlethread_workqueue(queue_name); 699 if (!sparx5->mact_queue) 700 return -ENOMEM; 701 702 INIT_DELAYED_WORK(&sparx5->mact_work, sparx5_mact_pull_work); 703 queue_delayed_work(sparx5->mact_queue, &sparx5->mact_work, 704 SPX5_MACT_PULL_DELAY); 705 706 mutex_init(&sparx5->mdb_lock); 707 INIT_LIST_HEAD(&sparx5->mdb_entries); 708 709 err = sparx5_register_netdevs(sparx5); 710 if (err) 711 return err; 712 713 sparx5_board_init(sparx5); 714 err = sparx5_register_notifier_blocks(sparx5); 715 if (err) 716 return err; 717 718 err = sparx5_vcap_init(sparx5); 719 if (err) { 720 sparx5_unregister_notifier_blocks(sparx5); 721 return err; 722 } 723 724 /* Start Frame DMA with fallback to register based INJ/XTR */ 725 err = -ENXIO; 726 if (sparx5->fdma_irq >= 0) { 727 if (GCB_CHIP_ID_REV_ID_GET(sparx5->chip_id) > 0) 728 err = devm_request_threaded_irq(sparx5->dev, 729 sparx5->fdma_irq, 730 NULL, 731 sparx5_fdma_handler, 732 IRQF_ONESHOT, 733 "sparx5-fdma", sparx5); 734 if (!err) 735 err = sparx5_fdma_start(sparx5); 736 if (err) 737 sparx5->fdma_irq = -ENXIO; 738 } else { 739 sparx5->fdma_irq = -ENXIO; 740 } 741 if (err && sparx5->xtr_irq >= 0) { 742 err = devm_request_irq(sparx5->dev, sparx5->xtr_irq, 743 sparx5_xtr_handler, IRQF_SHARED, 744 "sparx5-xtr", sparx5); 745 if (!err) 746 err = sparx5_manual_injection_mode(sparx5); 747 if (err) 748 sparx5->xtr_irq = -ENXIO; 749 } else { 750 sparx5->xtr_irq = -ENXIO; 751 } 752 753 if (sparx5->ptp_irq >= 0) { 754 err = devm_request_threaded_irq(sparx5->dev, sparx5->ptp_irq, 755 NULL, ops->ptp_irq_handler, 756 IRQF_ONESHOT, "sparx5-ptp", 757 sparx5); 758 if (err) 759 sparx5->ptp_irq = -ENXIO; 760 761 sparx5->ptp = 1; 762 } 763 764 return err; 765 } 766 767 static void sparx5_cleanup_ports(struct sparx5 *sparx5) 768 { 769 sparx5_unregister_netdevs(sparx5); 770 sparx5_destroy_netdevs(sparx5); 771 } 772 773 static int mchp_sparx5_probe(struct platform_device *pdev) 774 { 775 struct initial_port_config *configs, *config; 776 struct device_node *np = pdev->dev.of_node; 777 struct device_node *ports, *portnp; 778 struct reset_control *reset; 779 struct sparx5 *sparx5; 780 int idx = 0, err = 0; 781 782 if (!np && !pdev->dev.platform_data) 783 return -ENODEV; 784 785 sparx5 = devm_kzalloc(&pdev->dev, sizeof(*sparx5), GFP_KERNEL); 786 if (!sparx5) 787 return -ENOMEM; 788 789 platform_set_drvdata(pdev, sparx5); 790 sparx5->pdev = pdev; 791 sparx5->dev = &pdev->dev; 792 spin_lock_init(&sparx5->tx_lock); 793 794 sparx5->data = device_get_match_data(sparx5->dev); 795 if (!sparx5->data) 796 return -EINVAL; 797 798 regs = sparx5->data->regs; 799 800 /* Do switch core reset if available */ 801 reset = devm_reset_control_get_optional_shared(&pdev->dev, "switch"); 802 if (IS_ERR(reset)) 803 return dev_err_probe(&pdev->dev, PTR_ERR(reset), 804 "Failed to get switch reset controller.\n"); 805 reset_control_reset(reset); 806 807 /* Default values, some from DT */ 808 sparx5->coreclock = SPX5_CORE_CLOCK_DEFAULT; 809 810 sparx5->debugfs_root = debugfs_create_dir("sparx5", NULL); 811 812 ports = of_get_child_by_name(np, "ethernet-ports"); 813 if (!ports) { 814 dev_err(sparx5->dev, "no ethernet-ports child node found\n"); 815 return -ENODEV; 816 } 817 sparx5->port_count = of_get_child_count(ports); 818 819 configs = kcalloc(sparx5->port_count, 820 sizeof(struct initial_port_config), GFP_KERNEL); 821 if (!configs) { 822 err = -ENOMEM; 823 goto cleanup_pnode; 824 } 825 826 for_each_available_child_of_node(ports, portnp) { 827 struct sparx5_port_config *conf; 828 struct phy *serdes; 829 u32 portno; 830 831 err = of_property_read_u32(portnp, "reg", &portno); 832 if (err) { 833 dev_err(sparx5->dev, "port reg property error\n"); 834 continue; 835 } 836 config = &configs[idx]; 837 conf = &config->conf; 838 conf->speed = SPEED_UNKNOWN; 839 conf->bandwidth = SPEED_UNKNOWN; 840 err = of_get_phy_mode(portnp, &conf->phy_mode); 841 if (err) { 842 dev_err(sparx5->dev, "port %u: missing phy-mode\n", 843 portno); 844 continue; 845 } 846 err = of_property_read_u32(portnp, "microchip,bandwidth", 847 &conf->bandwidth); 848 if (err) { 849 dev_err(sparx5->dev, "port %u: missing bandwidth\n", 850 portno); 851 continue; 852 } 853 err = of_property_read_u32(portnp, "microchip,sd-sgpio", &conf->sd_sgpio); 854 if (err) 855 conf->sd_sgpio = ~0; 856 else 857 sparx5->sd_sgpio_remapping = true; 858 serdes = devm_of_phy_get(sparx5->dev, portnp, NULL); 859 if (IS_ERR(serdes)) { 860 err = dev_err_probe(sparx5->dev, PTR_ERR(serdes), 861 "port %u: missing serdes\n", 862 portno); 863 of_node_put(portnp); 864 goto cleanup_config; 865 } 866 config->portno = portno; 867 config->node = portnp; 868 config->serdes = serdes; 869 870 conf->media = PHY_MEDIA_DAC; 871 conf->serdes_reset = true; 872 conf->portmode = conf->phy_mode; 873 conf->power_down = true; 874 idx++; 875 } 876 877 err = sparx5_create_targets(sparx5); 878 if (err) 879 goto cleanup_config; 880 881 if (of_get_mac_address(np, sparx5->base_mac)) { 882 dev_info(sparx5->dev, "MAC addr was not set, use random MAC\n"); 883 eth_random_addr(sparx5->base_mac); 884 sparx5->base_mac[5] = 0; 885 } 886 887 sparx5->fdma_irq = platform_get_irq_byname(sparx5->pdev, "fdma"); 888 sparx5->xtr_irq = platform_get_irq_byname(sparx5->pdev, "xtr"); 889 sparx5->ptp_irq = platform_get_irq_byname(sparx5->pdev, "ptp"); 890 891 /* Read chip ID to check CPU interface */ 892 sparx5->chip_id = spx5_rd(sparx5, GCB_CHIP_ID); 893 894 sparx5->target_ct = (enum spx5_target_chiptype) 895 GCB_CHIP_ID_PART_ID_GET(sparx5->chip_id); 896 897 /* Initialize Switchcore and internal RAMs */ 898 err = sparx5_init_switchcore(sparx5); 899 if (err) { 900 dev_err(sparx5->dev, "Switchcore initialization error\n"); 901 goto cleanup_config; 902 } 903 904 /* Initialize the LC-PLL (core clock) and set affected registers */ 905 err = sparx5_init_coreclock(sparx5); 906 if (err) { 907 dev_err(sparx5->dev, "LC-PLL initialization error\n"); 908 goto cleanup_config; 909 } 910 911 for (idx = 0; idx < sparx5->port_count; ++idx) { 912 config = &configs[idx]; 913 if (!config->node) 914 continue; 915 916 err = sparx5_create_port(sparx5, config); 917 if (err) { 918 dev_err(sparx5->dev, "port create error\n"); 919 goto cleanup_ports; 920 } 921 } 922 923 err = sparx5_start(sparx5); 924 if (err) { 925 dev_err(sparx5->dev, "Start failed\n"); 926 goto cleanup_ports; 927 } 928 929 err = sparx5_qos_init(sparx5); 930 if (err) { 931 dev_err(sparx5->dev, "Failed to initialize QoS\n"); 932 goto cleanup_ports; 933 } 934 935 err = sparx5_ptp_init(sparx5); 936 if (err) { 937 dev_err(sparx5->dev, "PTP failed\n"); 938 goto cleanup_ports; 939 } 940 941 INIT_LIST_HEAD(&sparx5->mall_entries); 942 943 goto cleanup_config; 944 945 cleanup_ports: 946 sparx5_cleanup_ports(sparx5); 947 if (sparx5->mact_queue) 948 destroy_workqueue(sparx5->mact_queue); 949 cleanup_config: 950 kfree(configs); 951 cleanup_pnode: 952 of_node_put(ports); 953 return err; 954 } 955 956 static void mchp_sparx5_remove(struct platform_device *pdev) 957 { 958 struct sparx5 *sparx5 = platform_get_drvdata(pdev); 959 960 debugfs_remove_recursive(sparx5->debugfs_root); 961 if (sparx5->xtr_irq) { 962 disable_irq(sparx5->xtr_irq); 963 sparx5->xtr_irq = -ENXIO; 964 } 965 if (sparx5->fdma_irq) { 966 disable_irq(sparx5->fdma_irq); 967 sparx5->fdma_irq = -ENXIO; 968 } 969 sparx5_ptp_deinit(sparx5); 970 sparx5_fdma_stop(sparx5); 971 sparx5_cleanup_ports(sparx5); 972 sparx5_vcap_destroy(sparx5); 973 /* Unregister netdevs */ 974 sparx5_unregister_notifier_blocks(sparx5); 975 destroy_workqueue(sparx5->mact_queue); 976 } 977 978 static const struct sparx5_regs sparx5_regs = { 979 .tsize = sparx5_tsize, 980 .gaddr = sparx5_gaddr, 981 .gcnt = sparx5_gcnt, 982 .gsize = sparx5_gsize, 983 .raddr = sparx5_raddr, 984 .rcnt = sparx5_rcnt, 985 .fpos = sparx5_fpos, 986 .fsize = sparx5_fsize, 987 }; 988 989 static const struct sparx5_consts sparx5_consts = { 990 .n_ports = 65, 991 .n_ports_all = 70, 992 .n_hsch_l1_elems = 64, 993 .n_hsch_queues = 8, 994 .n_lb_groups = 10, 995 .n_pgids = 2113, /* (2048 + n_ports) */ 996 .n_sio_clks = 3, 997 .n_own_upsids = 3, 998 .n_auto_cals = 7, 999 .n_filters = 1024, 1000 .n_gates = 1024, 1001 .n_sdlbs = 4096, 1002 .n_dsm_cal_taxis = 8, 1003 .buf_size = 4194280, 1004 .qres_max_prio_idx = 630, 1005 .qres_max_colour_idx = 638, 1006 .tod_pin = 4, 1007 }; 1008 1009 static const struct sparx5_ops sparx5_ops = { 1010 .is_port_2g5 = &sparx5_port_is_2g5, 1011 .is_port_5g = &sparx5_port_is_5g, 1012 .is_port_10g = &sparx5_port_is_10g, 1013 .is_port_25g = &sparx5_port_is_25g, 1014 .get_port_dev_index = &sparx5_port_dev_mapping, 1015 .get_port_dev_bit = &sparx5_port_dev_mapping, 1016 .get_hsch_max_group_rate = &sparx5_get_hsch_max_group_rate, 1017 .get_sdlb_group = &sparx5_get_sdlb_group, 1018 .set_port_mux = &sparx5_port_mux_set, 1019 .ptp_irq_handler = &sparx5_ptp_irq_handler, 1020 .dsm_calendar_calc = &sparx5_dsm_calendar_calc, 1021 }; 1022 1023 static const struct sparx5_match_data sparx5_desc = { 1024 .iomap = sparx5_main_iomap, 1025 .iomap_size = ARRAY_SIZE(sparx5_main_iomap), 1026 .ioranges = 3, 1027 .regs = &sparx5_regs, 1028 .consts = &sparx5_consts, 1029 .ops = &sparx5_ops, 1030 }; 1031 1032 static const struct of_device_id mchp_sparx5_match[] = { 1033 { .compatible = "microchip,sparx5-switch", .data = &sparx5_desc }, 1034 { } 1035 }; 1036 MODULE_DEVICE_TABLE(of, mchp_sparx5_match); 1037 1038 static struct platform_driver mchp_sparx5_driver = { 1039 .probe = mchp_sparx5_probe, 1040 .remove = mchp_sparx5_remove, 1041 .driver = { 1042 .name = "sparx5-switch", 1043 .of_match_table = mchp_sparx5_match, 1044 }, 1045 }; 1046 1047 module_platform_driver(mchp_sparx5_driver); 1048 1049 MODULE_DESCRIPTION("Microchip Sparx5 switch driver"); 1050 MODULE_AUTHOR("Steen Hegelund <steen.hegelund@microchip.com>"); 1051 MODULE_LICENSE("Dual MIT/GPL"); 1052