1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 3 /* This file is autogenerated by cml-utils 2021-10-10 13:25:08 +0200. 4 * Commit ID: 26db2002924973d36a30b369c94f025a678fe9ea (dirty) 5 */ 6 7 #ifndef _LAN966X_REGS_H_ 8 #define _LAN966X_REGS_H_ 9 10 #include <linux/bitfield.h> 11 #include <linux/types.h> 12 #include <linux/bug.h> 13 14 enum lan966x_target { 15 TARGET_AFI = 2, 16 TARGET_ANA = 3, 17 TARGET_CHIP_TOP = 5, 18 TARGET_CPU = 6, 19 TARGET_DEV = 13, 20 TARGET_FDMA = 21, 21 TARGET_GCB = 27, 22 TARGET_ORG = 36, 23 TARGET_PTP = 41, 24 TARGET_QS = 42, 25 TARGET_QSYS = 46, 26 TARGET_REW = 47, 27 TARGET_SYS = 52, 28 TARGET_VCAP = 61, 29 NUM_TARGETS = 66 30 }; 31 32 #define __REG(...) __VA_ARGS__ 33 34 /* AFI:PORT_TBL:PORT_FRM_OUT */ 35 #define AFI_PORT_FRM_OUT(g) __REG(TARGET_AFI, 0, 1, 98816, g, 10, 8, 0, 0, 1, 4) 36 37 #define AFI_PORT_FRM_OUT_FRM_OUT_CNT GENMASK(26, 16) 38 #define AFI_PORT_FRM_OUT_FRM_OUT_CNT_SET(x)\ 39 FIELD_PREP(AFI_PORT_FRM_OUT_FRM_OUT_CNT, x) 40 #define AFI_PORT_FRM_OUT_FRM_OUT_CNT_GET(x)\ 41 FIELD_GET(AFI_PORT_FRM_OUT_FRM_OUT_CNT, x) 42 43 /* AFI:PORT_TBL:PORT_CFG */ 44 #define AFI_PORT_CFG(g) __REG(TARGET_AFI, 0, 1, 98816, g, 10, 8, 4, 0, 1, 4) 45 46 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ BIT(16) 47 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ_SET(x)\ 48 FIELD_PREP(AFI_PORT_CFG_FC_SKIP_TTI_INJ, x) 49 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ_GET(x)\ 50 FIELD_GET(AFI_PORT_CFG_FC_SKIP_TTI_INJ, x) 51 52 #define AFI_PORT_CFG_FRM_OUT_MAX GENMASK(9, 0) 53 #define AFI_PORT_CFG_FRM_OUT_MAX_SET(x)\ 54 FIELD_PREP(AFI_PORT_CFG_FRM_OUT_MAX, x) 55 #define AFI_PORT_CFG_FRM_OUT_MAX_GET(x)\ 56 FIELD_GET(AFI_PORT_CFG_FRM_OUT_MAX, x) 57 58 /* ANA:ANA:ADVLEARN */ 59 #define ANA_ADVLEARN __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 0, 0, 1, 4) 60 61 #define ANA_ADVLEARN_VLAN_CHK BIT(0) 62 #define ANA_ADVLEARN_VLAN_CHK_SET(x)\ 63 FIELD_PREP(ANA_ADVLEARN_VLAN_CHK, x) 64 #define ANA_ADVLEARN_VLAN_CHK_GET(x)\ 65 FIELD_GET(ANA_ADVLEARN_VLAN_CHK, x) 66 67 /* ANA:ANA:VLANMASK */ 68 #define ANA_VLANMASK __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 8, 0, 1, 4) 69 70 /* ANA:ANA:ANAINTR */ 71 #define ANA_ANAINTR __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 16, 0, 1, 4) 72 73 #define ANA_ANAINTR_INTR BIT(1) 74 #define ANA_ANAINTR_INTR_SET(x)\ 75 FIELD_PREP(ANA_ANAINTR_INTR, x) 76 #define ANA_ANAINTR_INTR_GET(x)\ 77 FIELD_GET(ANA_ANAINTR_INTR, x) 78 79 #define ANA_ANAINTR_INTR_ENA BIT(0) 80 #define ANA_ANAINTR_INTR_ENA_SET(x)\ 81 FIELD_PREP(ANA_ANAINTR_INTR_ENA, x) 82 #define ANA_ANAINTR_INTR_ENA_GET(x)\ 83 FIELD_GET(ANA_ANAINTR_INTR_ENA, x) 84 85 /* ANA:ANA:AUTOAGE */ 86 #define ANA_AUTOAGE __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 44, 0, 1, 4) 87 88 #define ANA_AUTOAGE_AGE_PERIOD GENMASK(20, 1) 89 #define ANA_AUTOAGE_AGE_PERIOD_SET(x)\ 90 FIELD_PREP(ANA_AUTOAGE_AGE_PERIOD, x) 91 #define ANA_AUTOAGE_AGE_PERIOD_GET(x)\ 92 FIELD_GET(ANA_AUTOAGE_AGE_PERIOD, x) 93 94 /* ANA:ANA:MIRRORPORTS */ 95 #define ANA_MIRRORPORTS __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 60, 0, 1, 4) 96 97 #define ANA_MIRRORPORTS_MIRRORPORTS GENMASK(8, 0) 98 #define ANA_MIRRORPORTS_MIRRORPORTS_SET(x)\ 99 FIELD_PREP(ANA_MIRRORPORTS_MIRRORPORTS, x) 100 #define ANA_MIRRORPORTS_MIRRORPORTS_GET(x)\ 101 FIELD_GET(ANA_MIRRORPORTS_MIRRORPORTS, x) 102 103 /* ANA:ANA:EMIRRORPORTS */ 104 #define ANA_EMIRRORPORTS __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 64, 0, 1, 4) 105 106 #define ANA_EMIRRORPORTS_EMIRRORPORTS GENMASK(8, 0) 107 #define ANA_EMIRRORPORTS_EMIRRORPORTS_SET(x)\ 108 FIELD_PREP(ANA_EMIRRORPORTS_EMIRRORPORTS, x) 109 #define ANA_EMIRRORPORTS_EMIRRORPORTS_GET(x)\ 110 FIELD_GET(ANA_EMIRRORPORTS_EMIRRORPORTS, x) 111 112 /* ANA:ANA:FLOODING */ 113 #define ANA_FLOODING(r) __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 68, r, 8, 4) 114 115 #define ANA_FLOODING_FLD_UNICAST GENMASK(17, 12) 116 #define ANA_FLOODING_FLD_UNICAST_SET(x)\ 117 FIELD_PREP(ANA_FLOODING_FLD_UNICAST, x) 118 #define ANA_FLOODING_FLD_UNICAST_GET(x)\ 119 FIELD_GET(ANA_FLOODING_FLD_UNICAST, x) 120 121 #define ANA_FLOODING_FLD_BROADCAST GENMASK(11, 6) 122 #define ANA_FLOODING_FLD_BROADCAST_SET(x)\ 123 FIELD_PREP(ANA_FLOODING_FLD_BROADCAST, x) 124 #define ANA_FLOODING_FLD_BROADCAST_GET(x)\ 125 FIELD_GET(ANA_FLOODING_FLD_BROADCAST, x) 126 127 #define ANA_FLOODING_FLD_MULTICAST GENMASK(5, 0) 128 #define ANA_FLOODING_FLD_MULTICAST_SET(x)\ 129 FIELD_PREP(ANA_FLOODING_FLD_MULTICAST, x) 130 #define ANA_FLOODING_FLD_MULTICAST_GET(x)\ 131 FIELD_GET(ANA_FLOODING_FLD_MULTICAST, x) 132 133 /* ANA:ANA:FLOODING_IPMC */ 134 #define ANA_FLOODING_IPMC __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 100, 0, 1, 4) 135 136 #define ANA_FLOODING_IPMC_FLD_MC4_CTRL GENMASK(23, 18) 137 #define ANA_FLOODING_IPMC_FLD_MC4_CTRL_SET(x)\ 138 FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC4_CTRL, x) 139 #define ANA_FLOODING_IPMC_FLD_MC4_CTRL_GET(x)\ 140 FIELD_GET(ANA_FLOODING_IPMC_FLD_MC4_CTRL, x) 141 142 #define ANA_FLOODING_IPMC_FLD_MC4_DATA GENMASK(17, 12) 143 #define ANA_FLOODING_IPMC_FLD_MC4_DATA_SET(x)\ 144 FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC4_DATA, x) 145 #define ANA_FLOODING_IPMC_FLD_MC4_DATA_GET(x)\ 146 FIELD_GET(ANA_FLOODING_IPMC_FLD_MC4_DATA, x) 147 148 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL GENMASK(11, 6) 149 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL_SET(x)\ 150 FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC6_CTRL, x) 151 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL_GET(x)\ 152 FIELD_GET(ANA_FLOODING_IPMC_FLD_MC6_CTRL, x) 153 154 #define ANA_FLOODING_IPMC_FLD_MC6_DATA GENMASK(5, 0) 155 #define ANA_FLOODING_IPMC_FLD_MC6_DATA_SET(x)\ 156 FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC6_DATA, x) 157 #define ANA_FLOODING_IPMC_FLD_MC6_DATA_GET(x)\ 158 FIELD_GET(ANA_FLOODING_IPMC_FLD_MC6_DATA, x) 159 160 /* ANA:PGID:PGID */ 161 #define ANA_PGID(g) __REG(TARGET_ANA, 0, 1, 27648, g, 89, 8, 0, 0, 1, 4) 162 163 #define ANA_PGID_PGID GENMASK(8, 0) 164 #define ANA_PGID_PGID_SET(x)\ 165 FIELD_PREP(ANA_PGID_PGID, x) 166 #define ANA_PGID_PGID_GET(x)\ 167 FIELD_GET(ANA_PGID_PGID, x) 168 169 /* ANA:PGID:PGID_CFG */ 170 #define ANA_PGID_CFG(g) __REG(TARGET_ANA, 0, 1, 27648, g, 89, 8, 4, 0, 1, 4) 171 172 #define ANA_PGID_CFG_OBEY_VLAN BIT(0) 173 #define ANA_PGID_CFG_OBEY_VLAN_SET(x)\ 174 FIELD_PREP(ANA_PGID_CFG_OBEY_VLAN, x) 175 #define ANA_PGID_CFG_OBEY_VLAN_GET(x)\ 176 FIELD_GET(ANA_PGID_CFG_OBEY_VLAN, x) 177 178 /* ANA:ANA_TABLES:MACHDATA */ 179 #define ANA_MACHDATA __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 40, 0, 1, 4) 180 181 /* ANA:ANA_TABLES:MACLDATA */ 182 #define ANA_MACLDATA __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 44, 0, 1, 4) 183 184 /* ANA:ANA_TABLES:MACACCESS */ 185 #define ANA_MACACCESS __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 48, 0, 1, 4) 186 187 #define ANA_MACACCESS_CHANGE2SW BIT(17) 188 #define ANA_MACACCESS_CHANGE2SW_SET(x)\ 189 FIELD_PREP(ANA_MACACCESS_CHANGE2SW, x) 190 #define ANA_MACACCESS_CHANGE2SW_GET(x)\ 191 FIELD_GET(ANA_MACACCESS_CHANGE2SW, x) 192 193 #define ANA_MACACCESS_MAC_CPU_COPY BIT(16) 194 #define ANA_MACACCESS_MAC_CPU_COPY_SET(x)\ 195 FIELD_PREP(ANA_MACACCESS_MAC_CPU_COPY, x) 196 #define ANA_MACACCESS_MAC_CPU_COPY_GET(x)\ 197 FIELD_GET(ANA_MACACCESS_MAC_CPU_COPY, x) 198 199 #define ANA_MACACCESS_VALID BIT(12) 200 #define ANA_MACACCESS_VALID_SET(x)\ 201 FIELD_PREP(ANA_MACACCESS_VALID, x) 202 #define ANA_MACACCESS_VALID_GET(x)\ 203 FIELD_GET(ANA_MACACCESS_VALID, x) 204 205 #define ANA_MACACCESS_ENTRYTYPE GENMASK(11, 10) 206 #define ANA_MACACCESS_ENTRYTYPE_SET(x)\ 207 FIELD_PREP(ANA_MACACCESS_ENTRYTYPE, x) 208 #define ANA_MACACCESS_ENTRYTYPE_GET(x)\ 209 FIELD_GET(ANA_MACACCESS_ENTRYTYPE, x) 210 211 #define ANA_MACACCESS_DEST_IDX GENMASK(9, 4) 212 #define ANA_MACACCESS_DEST_IDX_SET(x)\ 213 FIELD_PREP(ANA_MACACCESS_DEST_IDX, x) 214 #define ANA_MACACCESS_DEST_IDX_GET(x)\ 215 FIELD_GET(ANA_MACACCESS_DEST_IDX, x) 216 217 #define ANA_MACACCESS_MAC_TABLE_CMD GENMASK(3, 0) 218 #define ANA_MACACCESS_MAC_TABLE_CMD_SET(x)\ 219 FIELD_PREP(ANA_MACACCESS_MAC_TABLE_CMD, x) 220 #define ANA_MACACCESS_MAC_TABLE_CMD_GET(x)\ 221 FIELD_GET(ANA_MACACCESS_MAC_TABLE_CMD, x) 222 223 /* ANA:ANA_TABLES:MACTINDX */ 224 #define ANA_MACTINDX __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 52, 0, 1, 4) 225 226 #define ANA_MACTINDX_BUCKET GENMASK(12, 11) 227 #define ANA_MACTINDX_BUCKET_SET(x)\ 228 FIELD_PREP(ANA_MACTINDX_BUCKET, x) 229 #define ANA_MACTINDX_BUCKET_GET(x)\ 230 FIELD_GET(ANA_MACTINDX_BUCKET, x) 231 232 #define ANA_MACTINDX_M_INDEX GENMASK(10, 0) 233 #define ANA_MACTINDX_M_INDEX_SET(x)\ 234 FIELD_PREP(ANA_MACTINDX_M_INDEX, x) 235 #define ANA_MACTINDX_M_INDEX_GET(x)\ 236 FIELD_GET(ANA_MACTINDX_M_INDEX, x) 237 238 /* ANA:ANA_TABLES:VLAN_PORT_MASK */ 239 #define ANA_VLAN_PORT_MASK __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 56, 0, 1, 4) 240 241 #define ANA_VLAN_PORT_MASK_VLAN_PORT_MASK GENMASK(8, 0) 242 #define ANA_VLAN_PORT_MASK_VLAN_PORT_MASK_SET(x)\ 243 FIELD_PREP(ANA_VLAN_PORT_MASK_VLAN_PORT_MASK, x) 244 #define ANA_VLAN_PORT_MASK_VLAN_PORT_MASK_GET(x)\ 245 FIELD_GET(ANA_VLAN_PORT_MASK_VLAN_PORT_MASK, x) 246 247 /* ANA:ANA_TABLES:VLANACCESS */ 248 #define ANA_VLANACCESS __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 60, 0, 1, 4) 249 250 #define ANA_VLANACCESS_VLAN_TBL_CMD GENMASK(1, 0) 251 #define ANA_VLANACCESS_VLAN_TBL_CMD_SET(x)\ 252 FIELD_PREP(ANA_VLANACCESS_VLAN_TBL_CMD, x) 253 #define ANA_VLANACCESS_VLAN_TBL_CMD_GET(x)\ 254 FIELD_GET(ANA_VLANACCESS_VLAN_TBL_CMD, x) 255 256 /* ANA:ANA_TABLES:VLANTIDX */ 257 #define ANA_VLANTIDX __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 64, 0, 1, 4) 258 259 #define ANA_VLANTIDX_VLAN_PGID_CPU_DIS BIT(18) 260 #define ANA_VLANTIDX_VLAN_PGID_CPU_DIS_SET(x)\ 261 FIELD_PREP(ANA_VLANTIDX_VLAN_PGID_CPU_DIS, x) 262 #define ANA_VLANTIDX_VLAN_PGID_CPU_DIS_GET(x)\ 263 FIELD_GET(ANA_VLANTIDX_VLAN_PGID_CPU_DIS, x) 264 265 #define ANA_VLANTIDX_V_INDEX GENMASK(11, 0) 266 #define ANA_VLANTIDX_V_INDEX_SET(x)\ 267 FIELD_PREP(ANA_VLANTIDX_V_INDEX, x) 268 #define ANA_VLANTIDX_V_INDEX_GET(x)\ 269 FIELD_GET(ANA_VLANTIDX_V_INDEX, x) 270 271 /* ANA:PORT:VLAN_CFG */ 272 #define ANA_VLAN_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 0, 0, 1, 4) 273 274 #define ANA_VLAN_CFG_VLAN_AWARE_ENA BIT(20) 275 #define ANA_VLAN_CFG_VLAN_AWARE_ENA_SET(x)\ 276 FIELD_PREP(ANA_VLAN_CFG_VLAN_AWARE_ENA, x) 277 #define ANA_VLAN_CFG_VLAN_AWARE_ENA_GET(x)\ 278 FIELD_GET(ANA_VLAN_CFG_VLAN_AWARE_ENA, x) 279 280 #define ANA_VLAN_CFG_VLAN_POP_CNT GENMASK(19, 18) 281 #define ANA_VLAN_CFG_VLAN_POP_CNT_SET(x)\ 282 FIELD_PREP(ANA_VLAN_CFG_VLAN_POP_CNT, x) 283 #define ANA_VLAN_CFG_VLAN_POP_CNT_GET(x)\ 284 FIELD_GET(ANA_VLAN_CFG_VLAN_POP_CNT, x) 285 286 #define ANA_VLAN_CFG_VLAN_PCP GENMASK(15, 13) 287 #define ANA_VLAN_CFG_VLAN_PCP_SET(x)\ 288 FIELD_PREP(ANA_VLAN_CFG_VLAN_PCP, x) 289 #define ANA_VLAN_CFG_VLAN_PCP_GET(x)\ 290 FIELD_GET(ANA_VLAN_CFG_VLAN_PCP, x) 291 292 #define ANA_VLAN_CFG_VLAN_DEI BIT(12) 293 #define ANA_VLAN_CFG_VLAN_DEI_SET(x)\ 294 FIELD_PREP(ANA_VLAN_CFG_VLAN_DEI, x) 295 #define ANA_VLAN_CFG_VLAN_DEI_GET(x)\ 296 FIELD_GET(ANA_VLAN_CFG_VLAN_DEI, x) 297 298 #define ANA_VLAN_CFG_VLAN_VID GENMASK(11, 0) 299 #define ANA_VLAN_CFG_VLAN_VID_SET(x)\ 300 FIELD_PREP(ANA_VLAN_CFG_VLAN_VID, x) 301 #define ANA_VLAN_CFG_VLAN_VID_GET(x)\ 302 FIELD_GET(ANA_VLAN_CFG_VLAN_VID, x) 303 304 /* ANA:PORT:DROP_CFG */ 305 #define ANA_DROP_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 4, 0, 1, 4) 306 307 #define ANA_DROP_CFG_DROP_UNTAGGED_ENA BIT(6) 308 #define ANA_DROP_CFG_DROP_UNTAGGED_ENA_SET(x)\ 309 FIELD_PREP(ANA_DROP_CFG_DROP_UNTAGGED_ENA, x) 310 #define ANA_DROP_CFG_DROP_UNTAGGED_ENA_GET(x)\ 311 FIELD_GET(ANA_DROP_CFG_DROP_UNTAGGED_ENA, x) 312 313 #define ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA BIT(3) 314 #define ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA_SET(x)\ 315 FIELD_PREP(ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA, x) 316 #define ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA_GET(x)\ 317 FIELD_GET(ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA, x) 318 319 #define ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA BIT(2) 320 #define ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA_SET(x)\ 321 FIELD_PREP(ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, x) 322 #define ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA_GET(x)\ 323 FIELD_GET(ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, x) 324 325 #define ANA_DROP_CFG_DROP_MC_SMAC_ENA BIT(0) 326 #define ANA_DROP_CFG_DROP_MC_SMAC_ENA_SET(x)\ 327 FIELD_PREP(ANA_DROP_CFG_DROP_MC_SMAC_ENA, x) 328 #define ANA_DROP_CFG_DROP_MC_SMAC_ENA_GET(x)\ 329 FIELD_GET(ANA_DROP_CFG_DROP_MC_SMAC_ENA, x) 330 331 /* ANA:PORT:QOS_CFG */ 332 #define ANA_QOS_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 8, 0, 1, 4) 333 334 #define ANA_QOS_CFG_DP_DEFAULT_VAL BIT(8) 335 #define ANA_QOS_CFG_DP_DEFAULT_VAL_SET(x)\ 336 FIELD_PREP(ANA_QOS_CFG_DP_DEFAULT_VAL, x) 337 #define ANA_QOS_CFG_DP_DEFAULT_VAL_GET(x)\ 338 FIELD_GET(ANA_QOS_CFG_DP_DEFAULT_VAL, x) 339 340 #define ANA_QOS_CFG_QOS_DEFAULT_VAL GENMASK(7, 5) 341 #define ANA_QOS_CFG_QOS_DEFAULT_VAL_SET(x)\ 342 FIELD_PREP(ANA_QOS_CFG_QOS_DEFAULT_VAL, x) 343 #define ANA_QOS_CFG_QOS_DEFAULT_VAL_GET(x)\ 344 FIELD_GET(ANA_QOS_CFG_QOS_DEFAULT_VAL, x) 345 346 #define ANA_QOS_CFG_QOS_DSCP_ENA BIT(4) 347 #define ANA_QOS_CFG_QOS_DSCP_ENA_SET(x)\ 348 FIELD_PREP(ANA_QOS_CFG_QOS_DSCP_ENA, x) 349 #define ANA_QOS_CFG_QOS_DSCP_ENA_GET(x)\ 350 FIELD_GET(ANA_QOS_CFG_QOS_DSCP_ENA, x) 351 352 #define ANA_QOS_CFG_QOS_PCP_ENA BIT(3) 353 #define ANA_QOS_CFG_QOS_PCP_ENA_SET(x)\ 354 FIELD_PREP(ANA_QOS_CFG_QOS_PCP_ENA, x) 355 #define ANA_QOS_CFG_QOS_PCP_ENA_GET(x)\ 356 FIELD_GET(ANA_QOS_CFG_QOS_PCP_ENA, x) 357 358 #define ANA_QOS_CFG_DSCP_REWR_CFG GENMASK(1, 0) 359 #define ANA_QOS_CFG_DSCP_REWR_CFG_SET(x)\ 360 FIELD_PREP(ANA_QOS_CFG_DSCP_REWR_CFG, x) 361 #define ANA_QOS_CFG_DSCP_REWR_CFG_GET(x)\ 362 FIELD_GET(ANA_QOS_CFG_DSCP_REWR_CFG, x) 363 364 /* ANA:PORT:VCAP_CFG */ 365 #define ANA_VCAP_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 12, 0, 1, 4) 366 367 #define ANA_VCAP_CFG_S1_ENA BIT(14) 368 #define ANA_VCAP_CFG_S1_ENA_SET(x)\ 369 FIELD_PREP(ANA_VCAP_CFG_S1_ENA, x) 370 #define ANA_VCAP_CFG_S1_ENA_GET(x)\ 371 FIELD_GET(ANA_VCAP_CFG_S1_ENA, x) 372 373 /* ANA:PORT:VCAP_S1_KEY_CFG */ 374 #define ANA_VCAP_S1_CFG(g, r) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 16, r, 3, 4) 375 376 #define ANA_VCAP_S1_CFG_KEY_RT_CFG GENMASK(11, 9) 377 #define ANA_VCAP_S1_CFG_KEY_RT_CFG_SET(x)\ 378 FIELD_PREP(ANA_VCAP_S1_CFG_KEY_RT_CFG, x) 379 #define ANA_VCAP_S1_CFG_KEY_RT_CFG_GET(x)\ 380 FIELD_GET(ANA_VCAP_S1_CFG_KEY_RT_CFG, x) 381 382 #define ANA_VCAP_S1_CFG_KEY_IP6_CFG GENMASK(8, 6) 383 #define ANA_VCAP_S1_CFG_KEY_IP6_CFG_SET(x)\ 384 FIELD_PREP(ANA_VCAP_S1_CFG_KEY_IP6_CFG, x) 385 #define ANA_VCAP_S1_CFG_KEY_IP6_CFG_GET(x)\ 386 FIELD_GET(ANA_VCAP_S1_CFG_KEY_IP6_CFG, x) 387 388 #define ANA_VCAP_S1_CFG_KEY_IP4_CFG GENMASK(5, 3) 389 #define ANA_VCAP_S1_CFG_KEY_IP4_CFG_SET(x)\ 390 FIELD_PREP(ANA_VCAP_S1_CFG_KEY_IP4_CFG, x) 391 #define ANA_VCAP_S1_CFG_KEY_IP4_CFG_GET(x)\ 392 FIELD_GET(ANA_VCAP_S1_CFG_KEY_IP4_CFG, x) 393 394 #define ANA_VCAP_S1_CFG_KEY_OTHER_CFG GENMASK(2, 0) 395 #define ANA_VCAP_S1_CFG_KEY_OTHER_CFG_SET(x)\ 396 FIELD_PREP(ANA_VCAP_S1_CFG_KEY_OTHER_CFG, x) 397 #define ANA_VCAP_S1_CFG_KEY_OTHER_CFG_GET(x)\ 398 FIELD_GET(ANA_VCAP_S1_CFG_KEY_OTHER_CFG, x) 399 400 /* ANA:PORT:VCAP_S2_CFG */ 401 #define ANA_VCAP_S2_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 28, 0, 1, 4) 402 403 #define ANA_VCAP_S2_CFG_ISDX_ENA GENMASK(20, 19) 404 #define ANA_VCAP_S2_CFG_ISDX_ENA_SET(x)\ 405 FIELD_PREP(ANA_VCAP_S2_CFG_ISDX_ENA, x) 406 #define ANA_VCAP_S2_CFG_ISDX_ENA_GET(x)\ 407 FIELD_GET(ANA_VCAP_S2_CFG_ISDX_ENA, x) 408 409 #define ANA_VCAP_S2_CFG_UDP_PAYLOAD_ENA GENMASK(18, 17) 410 #define ANA_VCAP_S2_CFG_UDP_PAYLOAD_ENA_SET(x)\ 411 FIELD_PREP(ANA_VCAP_S2_CFG_UDP_PAYLOAD_ENA, x) 412 #define ANA_VCAP_S2_CFG_UDP_PAYLOAD_ENA_GET(x)\ 413 FIELD_GET(ANA_VCAP_S2_CFG_UDP_PAYLOAD_ENA, x) 414 415 #define ANA_VCAP_S2_CFG_ETYPE_PAYLOAD_ENA GENMASK(16, 15) 416 #define ANA_VCAP_S2_CFG_ETYPE_PAYLOAD_ENA_SET(x)\ 417 FIELD_PREP(ANA_VCAP_S2_CFG_ETYPE_PAYLOAD_ENA, x) 418 #define ANA_VCAP_S2_CFG_ETYPE_PAYLOAD_ENA_GET(x)\ 419 FIELD_GET(ANA_VCAP_S2_CFG_ETYPE_PAYLOAD_ENA, x) 420 421 #define ANA_VCAP_S2_CFG_ENA BIT(14) 422 #define ANA_VCAP_S2_CFG_ENA_SET(x)\ 423 FIELD_PREP(ANA_VCAP_S2_CFG_ENA, x) 424 #define ANA_VCAP_S2_CFG_ENA_GET(x)\ 425 FIELD_GET(ANA_VCAP_S2_CFG_ENA, x) 426 427 #define ANA_VCAP_S2_CFG_SNAP_DIS GENMASK(13, 12) 428 #define ANA_VCAP_S2_CFG_SNAP_DIS_SET(x)\ 429 FIELD_PREP(ANA_VCAP_S2_CFG_SNAP_DIS, x) 430 #define ANA_VCAP_S2_CFG_SNAP_DIS_GET(x)\ 431 FIELD_GET(ANA_VCAP_S2_CFG_SNAP_DIS, x) 432 433 #define ANA_VCAP_S2_CFG_ARP_DIS GENMASK(11, 10) 434 #define ANA_VCAP_S2_CFG_ARP_DIS_SET(x)\ 435 FIELD_PREP(ANA_VCAP_S2_CFG_ARP_DIS, x) 436 #define ANA_VCAP_S2_CFG_ARP_DIS_GET(x)\ 437 FIELD_GET(ANA_VCAP_S2_CFG_ARP_DIS, x) 438 439 #define ANA_VCAP_S2_CFG_IP_TCPUDP_DIS GENMASK(9, 8) 440 #define ANA_VCAP_S2_CFG_IP_TCPUDP_DIS_SET(x)\ 441 FIELD_PREP(ANA_VCAP_S2_CFG_IP_TCPUDP_DIS, x) 442 #define ANA_VCAP_S2_CFG_IP_TCPUDP_DIS_GET(x)\ 443 FIELD_GET(ANA_VCAP_S2_CFG_IP_TCPUDP_DIS, x) 444 445 #define ANA_VCAP_S2_CFG_IP_OTHER_DIS GENMASK(7, 6) 446 #define ANA_VCAP_S2_CFG_IP_OTHER_DIS_SET(x)\ 447 FIELD_PREP(ANA_VCAP_S2_CFG_IP_OTHER_DIS, x) 448 #define ANA_VCAP_S2_CFG_IP_OTHER_DIS_GET(x)\ 449 FIELD_GET(ANA_VCAP_S2_CFG_IP_OTHER_DIS, x) 450 451 #define ANA_VCAP_S2_CFG_IP6_CFG GENMASK(5, 2) 452 #define ANA_VCAP_S2_CFG_IP6_CFG_SET(x)\ 453 FIELD_PREP(ANA_VCAP_S2_CFG_IP6_CFG, x) 454 #define ANA_VCAP_S2_CFG_IP6_CFG_GET(x)\ 455 FIELD_GET(ANA_VCAP_S2_CFG_IP6_CFG, x) 456 457 #define ANA_VCAP_S2_CFG_OAM_DIS GENMASK(1, 0) 458 #define ANA_VCAP_S2_CFG_OAM_DIS_SET(x)\ 459 FIELD_PREP(ANA_VCAP_S2_CFG_OAM_DIS, x) 460 #define ANA_VCAP_S2_CFG_OAM_DIS_GET(x)\ 461 FIELD_GET(ANA_VCAP_S2_CFG_OAM_DIS, x) 462 463 /* ANA:PORT:QOS_PCP_DEI_MAP_CFG */ 464 #define ANA_PCP_DEI_CFG(g, r) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 32, r, 16, 4) 465 466 #define ANA_PCP_DEI_CFG_DP_PCP_DEI_VAL BIT(3) 467 #define ANA_PCP_DEI_CFG_DP_PCP_DEI_VAL_SET(x)\ 468 FIELD_PREP(ANA_PCP_DEI_CFG_DP_PCP_DEI_VAL, x) 469 #define ANA_PCP_DEI_CFG_DP_PCP_DEI_VAL_GET(x)\ 470 FIELD_GET(ANA_PCP_DEI_CFG_DP_PCP_DEI_VAL, x) 471 472 #define ANA_PCP_DEI_CFG_QOS_PCP_DEI_VAL GENMASK(2, 0) 473 #define ANA_PCP_DEI_CFG_QOS_PCP_DEI_VAL_SET(x)\ 474 FIELD_PREP(ANA_PCP_DEI_CFG_QOS_PCP_DEI_VAL, x) 475 #define ANA_PCP_DEI_CFG_QOS_PCP_DEI_VAL_GET(x)\ 476 FIELD_GET(ANA_PCP_DEI_CFG_QOS_PCP_DEI_VAL, x) 477 478 /* ANA:PORT:CPU_FWD_CFG */ 479 #define ANA_CPU_FWD_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 96, 0, 1, 4) 480 481 #define ANA_CPU_FWD_CFG_MLD_REDIR_ENA BIT(6) 482 #define ANA_CPU_FWD_CFG_MLD_REDIR_ENA_SET(x)\ 483 FIELD_PREP(ANA_CPU_FWD_CFG_MLD_REDIR_ENA, x) 484 #define ANA_CPU_FWD_CFG_MLD_REDIR_ENA_GET(x)\ 485 FIELD_GET(ANA_CPU_FWD_CFG_MLD_REDIR_ENA, x) 486 487 #define ANA_CPU_FWD_CFG_IGMP_REDIR_ENA BIT(5) 488 #define ANA_CPU_FWD_CFG_IGMP_REDIR_ENA_SET(x)\ 489 FIELD_PREP(ANA_CPU_FWD_CFG_IGMP_REDIR_ENA, x) 490 #define ANA_CPU_FWD_CFG_IGMP_REDIR_ENA_GET(x)\ 491 FIELD_GET(ANA_CPU_FWD_CFG_IGMP_REDIR_ENA, x) 492 493 #define ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA BIT(4) 494 #define ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA_SET(x)\ 495 FIELD_PREP(ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA, x) 496 #define ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA_GET(x)\ 497 FIELD_GET(ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA, x) 498 499 #define ANA_CPU_FWD_CFG_SRC_COPY_ENA BIT(3) 500 #define ANA_CPU_FWD_CFG_SRC_COPY_ENA_SET(x)\ 501 FIELD_PREP(ANA_CPU_FWD_CFG_SRC_COPY_ENA, x) 502 #define ANA_CPU_FWD_CFG_SRC_COPY_ENA_GET(x)\ 503 FIELD_GET(ANA_CPU_FWD_CFG_SRC_COPY_ENA, x) 504 505 /* ANA:PORT:CPU_FWD_BPDU_CFG */ 506 #define ANA_CPU_FWD_BPDU_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 100, 0, 1, 4) 507 508 /* ANA:PORT:PORT_CFG */ 509 #define ANA_PORT_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 112, 0, 1, 4) 510 511 #define ANA_PORT_CFG_SRC_MIRROR_ENA BIT(13) 512 #define ANA_PORT_CFG_SRC_MIRROR_ENA_SET(x)\ 513 FIELD_PREP(ANA_PORT_CFG_SRC_MIRROR_ENA, x) 514 #define ANA_PORT_CFG_SRC_MIRROR_ENA_GET(x)\ 515 FIELD_GET(ANA_PORT_CFG_SRC_MIRROR_ENA, x) 516 517 #define ANA_PORT_CFG_LEARNAUTO BIT(6) 518 #define ANA_PORT_CFG_LEARNAUTO_SET(x)\ 519 FIELD_PREP(ANA_PORT_CFG_LEARNAUTO, x) 520 #define ANA_PORT_CFG_LEARNAUTO_GET(x)\ 521 FIELD_GET(ANA_PORT_CFG_LEARNAUTO, x) 522 523 #define ANA_PORT_CFG_LEARN_ENA BIT(5) 524 #define ANA_PORT_CFG_LEARN_ENA_SET(x)\ 525 FIELD_PREP(ANA_PORT_CFG_LEARN_ENA, x) 526 #define ANA_PORT_CFG_LEARN_ENA_GET(x)\ 527 FIELD_GET(ANA_PORT_CFG_LEARN_ENA, x) 528 529 #define ANA_PORT_CFG_RECV_ENA BIT(4) 530 #define ANA_PORT_CFG_RECV_ENA_SET(x)\ 531 FIELD_PREP(ANA_PORT_CFG_RECV_ENA, x) 532 #define ANA_PORT_CFG_RECV_ENA_GET(x)\ 533 FIELD_GET(ANA_PORT_CFG_RECV_ENA, x) 534 535 #define ANA_PORT_CFG_PORTID_VAL GENMASK(3, 0) 536 #define ANA_PORT_CFG_PORTID_VAL_SET(x)\ 537 FIELD_PREP(ANA_PORT_CFG_PORTID_VAL, x) 538 #define ANA_PORT_CFG_PORTID_VAL_GET(x)\ 539 FIELD_GET(ANA_PORT_CFG_PORTID_VAL, x) 540 541 /* ANA:COMMON:DSCP_REWR_CFG */ 542 #define ANA_DSCP_REWR_CFG(r) __REG(TARGET_ANA, 0, 1, 31232, 0, 1, 552, 332, r, 16, 4) 543 544 #define ANA_DSCP_REWR_CFG_DSCP_QOS_REWR_VAL GENMASK(5, 0) 545 #define ANA_DSCP_REWR_CFG_DSCP_QOS_REWR_VAL_SET(x)\ 546 FIELD_PREP(ANA_DSCP_REWR_CFG_DSCP_QOS_REWR_VAL, x) 547 #define ANA_DSCP_REWR_CFG_DSCP_QOS_REWR_VAL_GET(x)\ 548 FIELD_GET(ANA_DSCP_REWR_CFG_DSCP_QOS_REWR_VAL, x) 549 550 /* ANA:PORT:POL_CFG */ 551 #define ANA_POL_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 116, 0, 1, 4) 552 553 #define ANA_POL_CFG_PORT_POL_ENA BIT(17) 554 #define ANA_POL_CFG_PORT_POL_ENA_SET(x)\ 555 FIELD_PREP(ANA_POL_CFG_PORT_POL_ENA, x) 556 #define ANA_POL_CFG_PORT_POL_ENA_GET(x)\ 557 FIELD_GET(ANA_POL_CFG_PORT_POL_ENA, x) 558 559 #define ANA_POL_CFG_POL_ORDER GENMASK(8, 0) 560 #define ANA_POL_CFG_POL_ORDER_SET(x)\ 561 FIELD_PREP(ANA_POL_CFG_POL_ORDER, x) 562 #define ANA_POL_CFG_POL_ORDER_GET(x)\ 563 FIELD_GET(ANA_POL_CFG_POL_ORDER, x) 564 565 /* ANA:PFC:PFC_CFG */ 566 #define ANA_PFC_CFG(g) __REG(TARGET_ANA, 0, 1, 30720, g, 8, 64, 0, 0, 1, 4) 567 568 #define ANA_PFC_CFG_FC_LINK_SPEED GENMASK(1, 0) 569 #define ANA_PFC_CFG_FC_LINK_SPEED_SET(x)\ 570 FIELD_PREP(ANA_PFC_CFG_FC_LINK_SPEED, x) 571 #define ANA_PFC_CFG_FC_LINK_SPEED_GET(x)\ 572 FIELD_GET(ANA_PFC_CFG_FC_LINK_SPEED, x) 573 574 /* ANA:COMMON:AGGR_CFG */ 575 #define ANA_AGGR_CFG __REG(TARGET_ANA, 0, 1, 31232, 0, 1, 552, 0, 0, 1, 4) 576 577 #define ANA_AGGR_CFG_AC_RND_ENA BIT(6) 578 #define ANA_AGGR_CFG_AC_RND_ENA_SET(x)\ 579 FIELD_PREP(ANA_AGGR_CFG_AC_RND_ENA, x) 580 #define ANA_AGGR_CFG_AC_RND_ENA_GET(x)\ 581 FIELD_GET(ANA_AGGR_CFG_AC_RND_ENA, x) 582 583 #define ANA_AGGR_CFG_AC_DMAC_ENA BIT(5) 584 #define ANA_AGGR_CFG_AC_DMAC_ENA_SET(x)\ 585 FIELD_PREP(ANA_AGGR_CFG_AC_DMAC_ENA, x) 586 #define ANA_AGGR_CFG_AC_DMAC_ENA_GET(x)\ 587 FIELD_GET(ANA_AGGR_CFG_AC_DMAC_ENA, x) 588 589 #define ANA_AGGR_CFG_AC_SMAC_ENA BIT(4) 590 #define ANA_AGGR_CFG_AC_SMAC_ENA_SET(x)\ 591 FIELD_PREP(ANA_AGGR_CFG_AC_SMAC_ENA, x) 592 #define ANA_AGGR_CFG_AC_SMAC_ENA_GET(x)\ 593 FIELD_GET(ANA_AGGR_CFG_AC_SMAC_ENA, x) 594 595 #define ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA BIT(3) 596 #define ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA_SET(x)\ 597 FIELD_PREP(ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA, x) 598 #define ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA_GET(x)\ 599 FIELD_GET(ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA, x) 600 601 #define ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA BIT(2) 602 #define ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA_SET(x)\ 603 FIELD_PREP(ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA, x) 604 #define ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA_GET(x)\ 605 FIELD_GET(ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA, x) 606 607 #define ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA BIT(1) 608 #define ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA_SET(x)\ 609 FIELD_PREP(ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA, x) 610 #define ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA_GET(x)\ 611 FIELD_GET(ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA, x) 612 613 #define ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA BIT(0) 614 #define ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA_SET(x)\ 615 FIELD_PREP(ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, x) 616 #define ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA_GET(x)\ 617 FIELD_GET(ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, x) 618 619 /* ANA:COMMON:DSCP_CFG */ 620 #define ANA_DSCP_CFG(r) __REG(TARGET_ANA, 0, 1, 31232, 0, 1, 552, 76, r, 64, 4) 621 622 #define ANA_DSCP_CFG_DP_DSCP_VAL BIT(11) 623 #define ANA_DSCP_CFG_DP_DSCP_VAL_SET(x)\ 624 FIELD_PREP(ANA_DSCP_CFG_DP_DSCP_VAL, x) 625 #define ANA_DSCP_CFG_DP_DSCP_VAL_GET(x)\ 626 FIELD_GET(ANA_DSCP_CFG_DP_DSCP_VAL, x) 627 628 #define ANA_DSCP_CFG_QOS_DSCP_VAL GENMASK(10, 8) 629 #define ANA_DSCP_CFG_QOS_DSCP_VAL_SET(x)\ 630 FIELD_PREP(ANA_DSCP_CFG_QOS_DSCP_VAL, x) 631 #define ANA_DSCP_CFG_QOS_DSCP_VAL_GET(x)\ 632 FIELD_GET(ANA_DSCP_CFG_QOS_DSCP_VAL, x) 633 634 #define ANA_DSCP_CFG_DSCP_TRUST_ENA BIT(1) 635 #define ANA_DSCP_CFG_DSCP_TRUST_ENA_SET(x)\ 636 FIELD_PREP(ANA_DSCP_CFG_DSCP_TRUST_ENA, x) 637 #define ANA_DSCP_CFG_DSCP_TRUST_ENA_GET(x)\ 638 FIELD_GET(ANA_DSCP_CFG_DSCP_TRUST_ENA, x) 639 640 #define ANA_DSCP_CFG_DSCP_REWR_ENA BIT(0) 641 #define ANA_DSCP_CFG_DSCP_REWR_ENA_SET(x)\ 642 FIELD_PREP(ANA_DSCP_CFG_DSCP_REWR_ENA, x) 643 #define ANA_DSCP_CFG_DSCP_REWR_ENA_GET(x)\ 644 FIELD_GET(ANA_DSCP_CFG_DSCP_REWR_ENA, x) 645 646 /* ANA:POL:POL_PIR_CFG */ 647 #define ANA_POL_PIR_CFG(g) __REG(TARGET_ANA, 0, 1, 16384, g, 345, 32, 0, 0, 1, 4) 648 649 #define ANA_POL_PIR_CFG_PIR_RATE GENMASK(20, 6) 650 #define ANA_POL_PIR_CFG_PIR_RATE_SET(x)\ 651 FIELD_PREP(ANA_POL_PIR_CFG_PIR_RATE, x) 652 #define ANA_POL_PIR_CFG_PIR_RATE_GET(x)\ 653 FIELD_GET(ANA_POL_PIR_CFG_PIR_RATE, x) 654 655 #define ANA_POL_PIR_CFG_PIR_BURST GENMASK(5, 0) 656 #define ANA_POL_PIR_CFG_PIR_BURST_SET(x)\ 657 FIELD_PREP(ANA_POL_PIR_CFG_PIR_BURST, x) 658 #define ANA_POL_PIR_CFG_PIR_BURST_GET(x)\ 659 FIELD_GET(ANA_POL_PIR_CFG_PIR_BURST, x) 660 661 /* ANA:POL:POL_MODE_CFG */ 662 #define ANA_POL_MODE(g) __REG(TARGET_ANA, 0, 1, 16384, g, 345, 32, 8, 0, 1, 4) 663 664 #define ANA_POL_MODE_DROP_ON_YELLOW_ENA BIT(11) 665 #define ANA_POL_MODE_DROP_ON_YELLOW_ENA_SET(x)\ 666 FIELD_PREP(ANA_POL_MODE_DROP_ON_YELLOW_ENA, x) 667 #define ANA_POL_MODE_DROP_ON_YELLOW_ENA_GET(x)\ 668 FIELD_GET(ANA_POL_MODE_DROP_ON_YELLOW_ENA, x) 669 670 #define ANA_POL_MODE_MARK_ALL_FRMS_RED_ENA BIT(10) 671 #define ANA_POL_MODE_MARK_ALL_FRMS_RED_ENA_SET(x)\ 672 FIELD_PREP(ANA_POL_MODE_MARK_ALL_FRMS_RED_ENA, x) 673 #define ANA_POL_MODE_MARK_ALL_FRMS_RED_ENA_GET(x)\ 674 FIELD_GET(ANA_POL_MODE_MARK_ALL_FRMS_RED_ENA, x) 675 676 #define ANA_POL_MODE_IPG_SIZE GENMASK(9, 5) 677 #define ANA_POL_MODE_IPG_SIZE_SET(x)\ 678 FIELD_PREP(ANA_POL_MODE_IPG_SIZE, x) 679 #define ANA_POL_MODE_IPG_SIZE_GET(x)\ 680 FIELD_GET(ANA_POL_MODE_IPG_SIZE, x) 681 682 #define ANA_POL_MODE_FRM_MODE GENMASK(4, 3) 683 #define ANA_POL_MODE_FRM_MODE_SET(x)\ 684 FIELD_PREP(ANA_POL_MODE_FRM_MODE, x) 685 #define ANA_POL_MODE_FRM_MODE_GET(x)\ 686 FIELD_GET(ANA_POL_MODE_FRM_MODE, x) 687 688 #define ANA_POL_MODE_OVERSHOOT_ENA BIT(0) 689 #define ANA_POL_MODE_OVERSHOOT_ENA_SET(x)\ 690 FIELD_PREP(ANA_POL_MODE_OVERSHOOT_ENA, x) 691 #define ANA_POL_MODE_OVERSHOOT_ENA_GET(x)\ 692 FIELD_GET(ANA_POL_MODE_OVERSHOOT_ENA, x) 693 694 /* ANA:POL:POL_PIR_STATE */ 695 #define ANA_POL_PIR_STATE(g) __REG(TARGET_ANA, 0, 1, 16384, g, 345, 32, 12, 0, 1, 4) 696 697 #define ANA_POL_PIR_STATE_PIR_LVL GENMASK(21, 0) 698 #define ANA_POL_PIR_STATE_PIR_LVL_SET(x)\ 699 FIELD_PREP(ANA_POL_PIR_STATE_PIR_LVL, x) 700 #define ANA_POL_PIR_STATE_PIR_LVL_GET(x)\ 701 FIELD_GET(ANA_POL_PIR_STATE_PIR_LVL, x) 702 703 /* CHIP_TOP:CUPHY_CFG:CUPHY_PORT_CFG */ 704 #define CHIP_TOP_CUPHY_PORT_CFG(r) __REG(TARGET_CHIP_TOP, 0, 1, 16, 0, 1, 20, 8, r, 2, 4) 705 706 #define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA BIT(0) 707 #define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA_SET(x)\ 708 FIELD_PREP(CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA, x) 709 #define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA_GET(x)\ 710 FIELD_GET(CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA, x) 711 712 /* DEV:PORT_MODE:CLOCK_CFG */ 713 #define DEV_CLOCK_CFG(t) __REG(TARGET_DEV, t, 8, 0, 0, 1, 28, 0, 0, 1, 4) 714 715 #define DEV_CLOCK_CFG_MAC_TX_RST BIT(7) 716 #define DEV_CLOCK_CFG_MAC_TX_RST_SET(x)\ 717 FIELD_PREP(DEV_CLOCK_CFG_MAC_TX_RST, x) 718 #define DEV_CLOCK_CFG_MAC_TX_RST_GET(x)\ 719 FIELD_GET(DEV_CLOCK_CFG_MAC_TX_RST, x) 720 721 #define DEV_CLOCK_CFG_MAC_RX_RST BIT(6) 722 #define DEV_CLOCK_CFG_MAC_RX_RST_SET(x)\ 723 FIELD_PREP(DEV_CLOCK_CFG_MAC_RX_RST, x) 724 #define DEV_CLOCK_CFG_MAC_RX_RST_GET(x)\ 725 FIELD_GET(DEV_CLOCK_CFG_MAC_RX_RST, x) 726 727 #define DEV_CLOCK_CFG_PCS_TX_RST BIT(5) 728 #define DEV_CLOCK_CFG_PCS_TX_RST_SET(x)\ 729 FIELD_PREP(DEV_CLOCK_CFG_PCS_TX_RST, x) 730 #define DEV_CLOCK_CFG_PCS_TX_RST_GET(x)\ 731 FIELD_GET(DEV_CLOCK_CFG_PCS_TX_RST, x) 732 733 #define DEV_CLOCK_CFG_PCS_RX_RST BIT(4) 734 #define DEV_CLOCK_CFG_PCS_RX_RST_SET(x)\ 735 FIELD_PREP(DEV_CLOCK_CFG_PCS_RX_RST, x) 736 #define DEV_CLOCK_CFG_PCS_RX_RST_GET(x)\ 737 FIELD_GET(DEV_CLOCK_CFG_PCS_RX_RST, x) 738 739 #define DEV_CLOCK_CFG_PORT_RST BIT(3) 740 #define DEV_CLOCK_CFG_PORT_RST_SET(x)\ 741 FIELD_PREP(DEV_CLOCK_CFG_PORT_RST, x) 742 #define DEV_CLOCK_CFG_PORT_RST_GET(x)\ 743 FIELD_GET(DEV_CLOCK_CFG_PORT_RST, x) 744 745 #define DEV_CLOCK_CFG_LINK_SPEED GENMASK(1, 0) 746 #define DEV_CLOCK_CFG_LINK_SPEED_SET(x)\ 747 FIELD_PREP(DEV_CLOCK_CFG_LINK_SPEED, x) 748 #define DEV_CLOCK_CFG_LINK_SPEED_GET(x)\ 749 FIELD_GET(DEV_CLOCK_CFG_LINK_SPEED, x) 750 751 /* DEV:MAC_CFG_STATUS:MAC_ENA_CFG */ 752 #define DEV_MAC_ENA_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 0, 0, 1, 4) 753 754 #define DEV_MAC_ENA_CFG_RX_ENA BIT(4) 755 #define DEV_MAC_ENA_CFG_RX_ENA_SET(x)\ 756 FIELD_PREP(DEV_MAC_ENA_CFG_RX_ENA, x) 757 #define DEV_MAC_ENA_CFG_RX_ENA_GET(x)\ 758 FIELD_GET(DEV_MAC_ENA_CFG_RX_ENA, x) 759 760 #define DEV_MAC_ENA_CFG_TX_ENA BIT(0) 761 #define DEV_MAC_ENA_CFG_TX_ENA_SET(x)\ 762 FIELD_PREP(DEV_MAC_ENA_CFG_TX_ENA, x) 763 #define DEV_MAC_ENA_CFG_TX_ENA_GET(x)\ 764 FIELD_GET(DEV_MAC_ENA_CFG_TX_ENA, x) 765 766 /* DEV:MAC_CFG_STATUS:MAC_MODE_CFG */ 767 #define DEV_MAC_MODE_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 4, 0, 1, 4) 768 769 #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA BIT(4) 770 #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA_SET(x)\ 771 FIELD_PREP(DEV_MAC_MODE_CFG_GIGA_MODE_ENA, x) 772 #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA_GET(x)\ 773 FIELD_GET(DEV_MAC_MODE_CFG_GIGA_MODE_ENA, x) 774 775 /* DEV:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ 776 #define DEV_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 8, 0, 1, 4) 777 778 #define DEV_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0) 779 #define DEV_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\ 780 FIELD_PREP(DEV_MAC_MAXLEN_CFG_MAX_LEN, x) 781 #define DEV_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ 782 FIELD_GET(DEV_MAC_MAXLEN_CFG_MAX_LEN, x) 783 784 /* DEV:MAC_CFG_STATUS:MAC_TAGS_CFG */ 785 #define DEV_MAC_TAGS_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 12, 0, 1, 4) 786 787 #define DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA BIT(1) 788 #define DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA_SET(x)\ 789 FIELD_PREP(DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA, x) 790 #define DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA_GET(x)\ 791 FIELD_GET(DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA, x) 792 793 #define DEV_MAC_TAGS_CFG_VLAN_AWR_ENA BIT(0) 794 #define DEV_MAC_TAGS_CFG_VLAN_AWR_ENA_SET(x)\ 795 FIELD_PREP(DEV_MAC_TAGS_CFG_VLAN_AWR_ENA, x) 796 #define DEV_MAC_TAGS_CFG_VLAN_AWR_ENA_GET(x)\ 797 FIELD_GET(DEV_MAC_TAGS_CFG_VLAN_AWR_ENA, x) 798 799 /* DEV:MAC_CFG_STATUS:MAC_IFG_CFG */ 800 #define DEV_MAC_IFG_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 20, 0, 1, 4) 801 802 #define DEV_MAC_IFG_CFG_TX_IFG GENMASK(12, 8) 803 #define DEV_MAC_IFG_CFG_TX_IFG_SET(x)\ 804 FIELD_PREP(DEV_MAC_IFG_CFG_TX_IFG, x) 805 #define DEV_MAC_IFG_CFG_TX_IFG_GET(x)\ 806 FIELD_GET(DEV_MAC_IFG_CFG_TX_IFG, x) 807 808 #define DEV_MAC_IFG_CFG_RX_IFG2 GENMASK(7, 4) 809 #define DEV_MAC_IFG_CFG_RX_IFG2_SET(x)\ 810 FIELD_PREP(DEV_MAC_IFG_CFG_RX_IFG2, x) 811 #define DEV_MAC_IFG_CFG_RX_IFG2_GET(x)\ 812 FIELD_GET(DEV_MAC_IFG_CFG_RX_IFG2, x) 813 814 #define DEV_MAC_IFG_CFG_RX_IFG1 GENMASK(3, 0) 815 #define DEV_MAC_IFG_CFG_RX_IFG1_SET(x)\ 816 FIELD_PREP(DEV_MAC_IFG_CFG_RX_IFG1, x) 817 #define DEV_MAC_IFG_CFG_RX_IFG1_GET(x)\ 818 FIELD_GET(DEV_MAC_IFG_CFG_RX_IFG1, x) 819 820 /* DEV:MAC_CFG_STATUS:MAC_HDX_CFG */ 821 #define DEV_MAC_HDX_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 24, 0, 1, 4) 822 823 #define DEV_MAC_HDX_CFG_SEED GENMASK(23, 16) 824 #define DEV_MAC_HDX_CFG_SEED_SET(x)\ 825 FIELD_PREP(DEV_MAC_HDX_CFG_SEED, x) 826 #define DEV_MAC_HDX_CFG_SEED_GET(x)\ 827 FIELD_GET(DEV_MAC_HDX_CFG_SEED, x) 828 829 #define DEV_MAC_HDX_CFG_SEED_LOAD BIT(12) 830 #define DEV_MAC_HDX_CFG_SEED_LOAD_SET(x)\ 831 FIELD_PREP(DEV_MAC_HDX_CFG_SEED_LOAD, x) 832 #define DEV_MAC_HDX_CFG_SEED_LOAD_GET(x)\ 833 FIELD_GET(DEV_MAC_HDX_CFG_SEED_LOAD, x) 834 835 /* DEV:MAC_CFG_STATUS:MAC_FC_MAC_LOW_CFG */ 836 #define DEV_FC_MAC_LOW_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 32, 0, 1, 4) 837 838 /* DEV:MAC_CFG_STATUS:MAC_FC_MAC_HIGH_CFG */ 839 #define DEV_FC_MAC_HIGH_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 36, 0, 1, 4) 840 841 /* DEV:PCS1G_CFG_STATUS:PCS1G_CFG */ 842 #define DEV_PCS1G_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 0, 0, 1, 4) 843 844 #define DEV_PCS1G_CFG_PCS_ENA BIT(0) 845 #define DEV_PCS1G_CFG_PCS_ENA_SET(x)\ 846 FIELD_PREP(DEV_PCS1G_CFG_PCS_ENA, x) 847 #define DEV_PCS1G_CFG_PCS_ENA_GET(x)\ 848 FIELD_GET(DEV_PCS1G_CFG_PCS_ENA, x) 849 850 /* DEV:PCS1G_CFG_STATUS:PCS1G_MODE_CFG */ 851 #define DEV_PCS1G_MODE_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 4, 0, 1, 4) 852 853 #define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0) 854 #define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(x)\ 855 FIELD_PREP(DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA, x) 856 #define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA_GET(x)\ 857 FIELD_GET(DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA, x) 858 859 #define DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA BIT(1) 860 #define DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_SET(x)\ 861 FIELD_PREP(DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x) 862 #define DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_GET(x)\ 863 FIELD_GET(DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x) 864 865 /* DEV:PCS1G_CFG_STATUS:PCS1G_SD_CFG */ 866 #define DEV_PCS1G_SD_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 8, 0, 1, 4) 867 868 #define DEV_PCS1G_SD_CFG_SD_ENA BIT(0) 869 #define DEV_PCS1G_SD_CFG_SD_ENA_SET(x)\ 870 FIELD_PREP(DEV_PCS1G_SD_CFG_SD_ENA, x) 871 #define DEV_PCS1G_SD_CFG_SD_ENA_GET(x)\ 872 FIELD_GET(DEV_PCS1G_SD_CFG_SD_ENA, x) 873 874 /* DEV:PCS1G_CFG_STATUS:PCS1G_ANEG_CFG */ 875 #define DEV_PCS1G_ANEG_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 12, 0, 1, 4) 876 877 #define DEV_PCS1G_ANEG_CFG_ADV_ABILITY GENMASK(31, 16) 878 #define DEV_PCS1G_ANEG_CFG_ADV_ABILITY_SET(x)\ 879 FIELD_PREP(DEV_PCS1G_ANEG_CFG_ADV_ABILITY, x) 880 #define DEV_PCS1G_ANEG_CFG_ADV_ABILITY_GET(x)\ 881 FIELD_GET(DEV_PCS1G_ANEG_CFG_ADV_ABILITY, x) 882 883 #define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA BIT(8) 884 #define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_SET(x)\ 885 FIELD_PREP(DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x) 886 #define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_GET(x)\ 887 FIELD_GET(DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x) 888 889 #define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT BIT(1) 890 #define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT_SET(x)\ 891 FIELD_PREP(DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT, x) 892 #define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT_GET(x)\ 893 FIELD_GET(DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT, x) 894 895 #define DEV_PCS1G_ANEG_CFG_ENA BIT(0) 896 #define DEV_PCS1G_ANEG_CFG_ENA_SET(x)\ 897 FIELD_PREP(DEV_PCS1G_ANEG_CFG_ENA, x) 898 #define DEV_PCS1G_ANEG_CFG_ENA_GET(x)\ 899 FIELD_GET(DEV_PCS1G_ANEG_CFG_ENA, x) 900 901 /* DEV:PCS1G_CFG_STATUS:PCS1G_ANEG_STATUS */ 902 #define DEV_PCS1G_ANEG_STATUS(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 32, 0, 1, 4) 903 904 #define DEV_PCS1G_ANEG_STATUS_LP_ADV GENMASK(31, 16) 905 #define DEV_PCS1G_ANEG_STATUS_LP_ADV_SET(x)\ 906 FIELD_PREP(DEV_PCS1G_ANEG_STATUS_LP_ADV, x) 907 #define DEV_PCS1G_ANEG_STATUS_LP_ADV_GET(x)\ 908 FIELD_GET(DEV_PCS1G_ANEG_STATUS_LP_ADV, x) 909 910 #define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE BIT(0) 911 #define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE_SET(x)\ 912 FIELD_PREP(DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x) 913 #define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE_GET(x)\ 914 FIELD_GET(DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x) 915 916 /* DEV:PCS1G_CFG_STATUS:PCS1G_LINK_STATUS */ 917 #define DEV_PCS1G_LINK_STATUS(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 40, 0, 1, 4) 918 919 #define DEV_PCS1G_LINK_STATUS_LINK_STATUS BIT(4) 920 #define DEV_PCS1G_LINK_STATUS_LINK_STATUS_SET(x)\ 921 FIELD_PREP(DEV_PCS1G_LINK_STATUS_LINK_STATUS, x) 922 #define DEV_PCS1G_LINK_STATUS_LINK_STATUS_GET(x)\ 923 FIELD_GET(DEV_PCS1G_LINK_STATUS_LINK_STATUS, x) 924 925 #define DEV_PCS1G_LINK_STATUS_SYNC_STATUS BIT(0) 926 #define DEV_PCS1G_LINK_STATUS_SYNC_STATUS_SET(x)\ 927 FIELD_PREP(DEV_PCS1G_LINK_STATUS_SYNC_STATUS, x) 928 #define DEV_PCS1G_LINK_STATUS_SYNC_STATUS_GET(x)\ 929 FIELD_GET(DEV_PCS1G_LINK_STATUS_SYNC_STATUS, x) 930 931 /* DEV:PCS1G_CFG_STATUS:PCS1G_STICKY */ 932 #define DEV_PCS1G_STICKY(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 48, 0, 1, 4) 933 934 #define DEV_PCS1G_STICKY_LINK_DOWN_STICKY BIT(4) 935 #define DEV_PCS1G_STICKY_LINK_DOWN_STICKY_SET(x)\ 936 FIELD_PREP(DEV_PCS1G_STICKY_LINK_DOWN_STICKY, x) 937 #define DEV_PCS1G_STICKY_LINK_DOWN_STICKY_GET(x)\ 938 FIELD_GET(DEV_PCS1G_STICKY_LINK_DOWN_STICKY, x) 939 940 /* FDMA:FDMA:FDMA_CH_ACTIVATE */ 941 #define FDMA_CH_ACTIVATE __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 0, 0, 1, 4) 942 943 #define FDMA_CH_ACTIVATE_CH_ACTIVATE GENMASK(7, 0) 944 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_SET(x)\ 945 FIELD_PREP(FDMA_CH_ACTIVATE_CH_ACTIVATE, x) 946 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_GET(x)\ 947 FIELD_GET(FDMA_CH_ACTIVATE_CH_ACTIVATE, x) 948 949 /* FDMA:FDMA:FDMA_CH_RELOAD */ 950 #define FDMA_CH_RELOAD __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 4, 0, 1, 4) 951 952 #define FDMA_CH_RELOAD_CH_RELOAD GENMASK(7, 0) 953 #define FDMA_CH_RELOAD_CH_RELOAD_SET(x)\ 954 FIELD_PREP(FDMA_CH_RELOAD_CH_RELOAD, x) 955 #define FDMA_CH_RELOAD_CH_RELOAD_GET(x)\ 956 FIELD_GET(FDMA_CH_RELOAD_CH_RELOAD, x) 957 958 /* FDMA:FDMA:FDMA_CH_DISABLE */ 959 #define FDMA_CH_DISABLE __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 8, 0, 1, 4) 960 961 #define FDMA_CH_DISABLE_CH_DISABLE GENMASK(7, 0) 962 #define FDMA_CH_DISABLE_CH_DISABLE_SET(x)\ 963 FIELD_PREP(FDMA_CH_DISABLE_CH_DISABLE, x) 964 #define FDMA_CH_DISABLE_CH_DISABLE_GET(x)\ 965 FIELD_GET(FDMA_CH_DISABLE_CH_DISABLE, x) 966 967 /* FDMA:FDMA:FDMA_CH_DB_DISCARD */ 968 #define FDMA_CH_DB_DISCARD __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 16, 0, 1, 4) 969 970 #define FDMA_CH_DB_DISCARD_DB_DISCARD GENMASK(7, 0) 971 #define FDMA_CH_DB_DISCARD_DB_DISCARD_SET(x)\ 972 FIELD_PREP(FDMA_CH_DB_DISCARD_DB_DISCARD, x) 973 #define FDMA_CH_DB_DISCARD_DB_DISCARD_GET(x)\ 974 FIELD_GET(FDMA_CH_DB_DISCARD_DB_DISCARD, x) 975 976 /* FDMA:FDMA:FDMA_DCB_LLP */ 977 #define FDMA_DCB_LLP(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 52, r, 8, 4) 978 979 /* FDMA:FDMA:FDMA_DCB_LLP1 */ 980 #define FDMA_DCB_LLP1(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 84, r, 8, 4) 981 982 /* FDMA:FDMA:FDMA_CH_ACTIVE */ 983 #define FDMA_CH_ACTIVE __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 180, 0, 1, 4) 984 985 /* FDMA:FDMA:FDMA_CH_CFG */ 986 #define FDMA_CH_CFG(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 224, r, 8, 4) 987 988 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY BIT(4) 989 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(x)\ 990 FIELD_PREP(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x) 991 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_GET(x)\ 992 FIELD_GET(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x) 993 994 #define FDMA_CH_CFG_CH_INJ_PORT BIT(3) 995 #define FDMA_CH_CFG_CH_INJ_PORT_SET(x)\ 996 FIELD_PREP(FDMA_CH_CFG_CH_INJ_PORT, x) 997 #define FDMA_CH_CFG_CH_INJ_PORT_GET(x)\ 998 FIELD_GET(FDMA_CH_CFG_CH_INJ_PORT, x) 999 1000 #define FDMA_CH_CFG_CH_DCB_DB_CNT GENMASK(2, 1) 1001 #define FDMA_CH_CFG_CH_DCB_DB_CNT_SET(x)\ 1002 FIELD_PREP(FDMA_CH_CFG_CH_DCB_DB_CNT, x) 1003 #define FDMA_CH_CFG_CH_DCB_DB_CNT_GET(x)\ 1004 FIELD_GET(FDMA_CH_CFG_CH_DCB_DB_CNT, x) 1005 1006 #define FDMA_CH_CFG_CH_MEM BIT(0) 1007 #define FDMA_CH_CFG_CH_MEM_SET(x)\ 1008 FIELD_PREP(FDMA_CH_CFG_CH_MEM, x) 1009 #define FDMA_CH_CFG_CH_MEM_GET(x)\ 1010 FIELD_GET(FDMA_CH_CFG_CH_MEM, x) 1011 1012 /* FDMA:FDMA:FDMA_PORT_CTRL */ 1013 #define FDMA_PORT_CTRL(r) __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 376, r, 2, 4) 1014 1015 #define FDMA_PORT_CTRL_INJ_STOP BIT(4) 1016 #define FDMA_PORT_CTRL_INJ_STOP_SET(x)\ 1017 FIELD_PREP(FDMA_PORT_CTRL_INJ_STOP, x) 1018 #define FDMA_PORT_CTRL_INJ_STOP_GET(x)\ 1019 FIELD_GET(FDMA_PORT_CTRL_INJ_STOP, x) 1020 1021 #define FDMA_PORT_CTRL_XTR_STOP BIT(2) 1022 #define FDMA_PORT_CTRL_XTR_STOP_SET(x)\ 1023 FIELD_PREP(FDMA_PORT_CTRL_XTR_STOP, x) 1024 #define FDMA_PORT_CTRL_XTR_STOP_GET(x)\ 1025 FIELD_GET(FDMA_PORT_CTRL_XTR_STOP, x) 1026 1027 /* FDMA:FDMA:FDMA_INTR_DB */ 1028 #define FDMA_INTR_DB __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 392, 0, 1, 4) 1029 1030 /* FDMA:FDMA:FDMA_INTR_DB_ENA */ 1031 #define FDMA_INTR_DB_ENA __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 396, 0, 1, 4) 1032 1033 #define FDMA_INTR_DB_ENA_INTR_DB_ENA GENMASK(7, 0) 1034 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_SET(x)\ 1035 FIELD_PREP(FDMA_INTR_DB_ENA_INTR_DB_ENA, x) 1036 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_GET(x)\ 1037 FIELD_GET(FDMA_INTR_DB_ENA_INTR_DB_ENA, x) 1038 1039 /* FDMA:FDMA:FDMA_INTR_ERR */ 1040 #define FDMA_INTR_ERR __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 400, 0, 1, 4) 1041 1042 /* FDMA:FDMA:FDMA_ERRORS */ 1043 #define FDMA_ERRORS __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 412, 0, 1, 4) 1044 1045 /* PTP:PTP_CFG:PTP_PIN_INTR */ 1046 #define PTP_PIN_INTR __REG(TARGET_PTP, 0, 1, 512, 0, 1, 16, 0, 0, 1, 4) 1047 1048 #define PTP_PIN_INTR_INTR_PTP GENMASK(7, 0) 1049 #define PTP_PIN_INTR_INTR_PTP_SET(x)\ 1050 FIELD_PREP(PTP_PIN_INTR_INTR_PTP, x) 1051 #define PTP_PIN_INTR_INTR_PTP_GET(x)\ 1052 FIELD_GET(PTP_PIN_INTR_INTR_PTP, x) 1053 1054 /* PTP:PTP_CFG:PTP_PIN_INTR_ENA */ 1055 #define PTP_PIN_INTR_ENA __REG(TARGET_PTP, 0, 1, 512, 0, 1, 16, 4, 0, 1, 4) 1056 1057 #define PTP_PIN_INTR_ENA_INTR_ENA GENMASK(7, 0) 1058 #define PTP_PIN_INTR_ENA_INTR_ENA_SET(x)\ 1059 FIELD_PREP(PTP_PIN_INTR_ENA_INTR_ENA, x) 1060 #define PTP_PIN_INTR_ENA_INTR_ENA_GET(x)\ 1061 FIELD_GET(PTP_PIN_INTR_ENA_INTR_ENA, x) 1062 1063 /* PTP:PTP_CFG:PTP_DOM_CFG */ 1064 #define PTP_DOM_CFG __REG(TARGET_PTP, 0, 1, 512, 0, 1, 16, 12, 0, 1, 4) 1065 1066 #define PTP_DOM_CFG_ENA GENMASK(11, 9) 1067 #define PTP_DOM_CFG_ENA_SET(x)\ 1068 FIELD_PREP(PTP_DOM_CFG_ENA, x) 1069 #define PTP_DOM_CFG_ENA_GET(x)\ 1070 FIELD_GET(PTP_DOM_CFG_ENA, x) 1071 1072 #define PTP_DOM_CFG_CLKCFG_DIS GENMASK(2, 0) 1073 #define PTP_DOM_CFG_CLKCFG_DIS_SET(x)\ 1074 FIELD_PREP(PTP_DOM_CFG_CLKCFG_DIS, x) 1075 #define PTP_DOM_CFG_CLKCFG_DIS_GET(x)\ 1076 FIELD_GET(PTP_DOM_CFG_CLKCFG_DIS, x) 1077 1078 /* PTP:PTP_TOD_DOMAINS:CLK_PER_CFG */ 1079 #define PTP_CLK_PER_CFG(g, r) __REG(TARGET_PTP, 0, 1, 528, g, 3, 28, 0, r, 2, 4) 1080 1081 /* PTP:PTP_PINS:PTP_PIN_CFG */ 1082 #define PTP_PIN_CFG(g) __REG(TARGET_PTP, 0, 1, 0, g, 8, 64, 0, 0, 1, 4) 1083 1084 #define PTP_PIN_CFG_PIN_ACTION GENMASK(29, 27) 1085 #define PTP_PIN_CFG_PIN_ACTION_SET(x)\ 1086 FIELD_PREP(PTP_PIN_CFG_PIN_ACTION, x) 1087 #define PTP_PIN_CFG_PIN_ACTION_GET(x)\ 1088 FIELD_GET(PTP_PIN_CFG_PIN_ACTION, x) 1089 1090 #define PTP_PIN_CFG_PIN_SYNC GENMASK(26, 25) 1091 #define PTP_PIN_CFG_PIN_SYNC_SET(x)\ 1092 FIELD_PREP(PTP_PIN_CFG_PIN_SYNC, x) 1093 #define PTP_PIN_CFG_PIN_SYNC_GET(x)\ 1094 FIELD_GET(PTP_PIN_CFG_PIN_SYNC, x) 1095 1096 #define PTP_PIN_CFG_PIN_SELECT GENMASK(23, 21) 1097 #define PTP_PIN_CFG_PIN_SELECT_SET(x)\ 1098 FIELD_PREP(PTP_PIN_CFG_PIN_SELECT, x) 1099 #define PTP_PIN_CFG_PIN_SELECT_GET(x)\ 1100 FIELD_GET(PTP_PIN_CFG_PIN_SELECT, x) 1101 1102 #define PTP_PIN_CFG_PIN_DOM GENMASK(17, 16) 1103 #define PTP_PIN_CFG_PIN_DOM_SET(x)\ 1104 FIELD_PREP(PTP_PIN_CFG_PIN_DOM, x) 1105 #define PTP_PIN_CFG_PIN_DOM_GET(x)\ 1106 FIELD_GET(PTP_PIN_CFG_PIN_DOM, x) 1107 1108 /* PTP:PTP_PINS:PTP_TOD_SEC_MSB */ 1109 #define PTP_TOD_SEC_MSB(g) __REG(TARGET_PTP, 0, 1, 0, g, 8, 64, 4, 0, 1, 4) 1110 1111 #define PTP_TOD_SEC_MSB_TOD_SEC_MSB GENMASK(15, 0) 1112 #define PTP_TOD_SEC_MSB_TOD_SEC_MSB_SET(x)\ 1113 FIELD_PREP(PTP_TOD_SEC_MSB_TOD_SEC_MSB, x) 1114 #define PTP_TOD_SEC_MSB_TOD_SEC_MSB_GET(x)\ 1115 FIELD_GET(PTP_TOD_SEC_MSB_TOD_SEC_MSB, x) 1116 1117 /* PTP:PTP_PINS:PTP_TOD_SEC_LSB */ 1118 #define PTP_TOD_SEC_LSB(g) __REG(TARGET_PTP, 0, 1, 0, g, 8, 64, 8, 0, 1, 4) 1119 1120 /* PTP:PTP_PINS:PTP_TOD_NSEC */ 1121 #define PTP_TOD_NSEC(g) __REG(TARGET_PTP, 0, 1, 0, g, 8, 64, 12, 0, 1, 4) 1122 1123 #define PTP_TOD_NSEC_TOD_NSEC GENMASK(29, 0) 1124 #define PTP_TOD_NSEC_TOD_NSEC_SET(x)\ 1125 FIELD_PREP(PTP_TOD_NSEC_TOD_NSEC, x) 1126 #define PTP_TOD_NSEC_TOD_NSEC_GET(x)\ 1127 FIELD_GET(PTP_TOD_NSEC_TOD_NSEC, x) 1128 1129 /* PTP:PTP_PINS:WF_HIGH_PERIOD */ 1130 #define PTP_WF_HIGH_PERIOD(g) __REG(TARGET_PTP,\ 1131 0, 1, 0, g, 8, 64, 24, 0, 1, 4) 1132 1133 #define PTP_WF_HIGH_PERIOD_PIN_WFH(x) ((x) & GENMASK(29, 0)) 1134 #define PTP_WF_HIGH_PERIOD_PIN_WFH_M GENMASK(29, 0) 1135 #define PTP_WF_HIGH_PERIOD_PIN_WFH_X(x) ((x) & GENMASK(29, 0)) 1136 1137 /* PTP:PTP_PINS:WF_LOW_PERIOD */ 1138 #define PTP_WF_LOW_PERIOD(g) __REG(TARGET_PTP,\ 1139 0, 1, 0, g, 8, 64, 28, 0, 1, 4) 1140 1141 #define PTP_WF_LOW_PERIOD_PIN_WFL(x) ((x) & GENMASK(29, 0)) 1142 #define PTP_WF_LOW_PERIOD_PIN_WFL_M GENMASK(29, 0) 1143 #define PTP_WF_LOW_PERIOD_PIN_WFL_X(x) ((x) & GENMASK(29, 0)) 1144 1145 /* PTP:PTP_TS_FIFO:PTP_TWOSTEP_CTRL */ 1146 #define PTP_TWOSTEP_CTRL __REG(TARGET_PTP, 0, 1, 612, 0, 1, 12, 0, 0, 1, 4) 1147 1148 #define PTP_TWOSTEP_CTRL_NXT BIT(11) 1149 #define PTP_TWOSTEP_CTRL_NXT_SET(x)\ 1150 FIELD_PREP(PTP_TWOSTEP_CTRL_NXT, x) 1151 #define PTP_TWOSTEP_CTRL_NXT_GET(x)\ 1152 FIELD_GET(PTP_TWOSTEP_CTRL_NXT, x) 1153 1154 #define PTP_TWOSTEP_CTRL_VLD BIT(10) 1155 #define PTP_TWOSTEP_CTRL_VLD_SET(x)\ 1156 FIELD_PREP(PTP_TWOSTEP_CTRL_VLD, x) 1157 #define PTP_TWOSTEP_CTRL_VLD_GET(x)\ 1158 FIELD_GET(PTP_TWOSTEP_CTRL_VLD, x) 1159 1160 #define PTP_TWOSTEP_CTRL_STAMP_TX BIT(9) 1161 #define PTP_TWOSTEP_CTRL_STAMP_TX_SET(x)\ 1162 FIELD_PREP(PTP_TWOSTEP_CTRL_STAMP_TX, x) 1163 #define PTP_TWOSTEP_CTRL_STAMP_TX_GET(x)\ 1164 FIELD_GET(PTP_TWOSTEP_CTRL_STAMP_TX, x) 1165 1166 #define PTP_TWOSTEP_CTRL_STAMP_PORT GENMASK(8, 1) 1167 #define PTP_TWOSTEP_CTRL_STAMP_PORT_SET(x)\ 1168 FIELD_PREP(PTP_TWOSTEP_CTRL_STAMP_PORT, x) 1169 #define PTP_TWOSTEP_CTRL_STAMP_PORT_GET(x)\ 1170 FIELD_GET(PTP_TWOSTEP_CTRL_STAMP_PORT, x) 1171 1172 #define PTP_TWOSTEP_CTRL_OVFL BIT(0) 1173 #define PTP_TWOSTEP_CTRL_OVFL_SET(x)\ 1174 FIELD_PREP(PTP_TWOSTEP_CTRL_OVFL, x) 1175 #define PTP_TWOSTEP_CTRL_OVFL_GET(x)\ 1176 FIELD_GET(PTP_TWOSTEP_CTRL_OVFL, x) 1177 1178 /* PTP:PTP_TS_FIFO:PTP_TWOSTEP_STAMP */ 1179 #define PTP_TWOSTEP_STAMP __REG(TARGET_PTP, 0, 1, 612, 0, 1, 12, 4, 0, 1, 4) 1180 1181 #define PTP_TWOSTEP_STAMP_STAMP_NSEC GENMASK(31, 2) 1182 #define PTP_TWOSTEP_STAMP_STAMP_NSEC_SET(x)\ 1183 FIELD_PREP(PTP_TWOSTEP_STAMP_STAMP_NSEC, x) 1184 #define PTP_TWOSTEP_STAMP_STAMP_NSEC_GET(x)\ 1185 FIELD_GET(PTP_TWOSTEP_STAMP_STAMP_NSEC, x) 1186 1187 /* DEVCPU_QS:XTR:XTR_GRP_CFG */ 1188 #define QS_XTR_GRP_CFG(r) __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 0, r, 2, 4) 1189 1190 #define QS_XTR_GRP_CFG_MODE GENMASK(3, 2) 1191 #define QS_XTR_GRP_CFG_MODE_SET(x)\ 1192 FIELD_PREP(QS_XTR_GRP_CFG_MODE, x) 1193 #define QS_XTR_GRP_CFG_MODE_GET(x)\ 1194 FIELD_GET(QS_XTR_GRP_CFG_MODE, x) 1195 1196 #define QS_XTR_GRP_CFG_BYTE_SWAP BIT(0) 1197 #define QS_XTR_GRP_CFG_BYTE_SWAP_SET(x)\ 1198 FIELD_PREP(QS_XTR_GRP_CFG_BYTE_SWAP, x) 1199 #define QS_XTR_GRP_CFG_BYTE_SWAP_GET(x)\ 1200 FIELD_GET(QS_XTR_GRP_CFG_BYTE_SWAP, x) 1201 1202 /* DEVCPU_QS:XTR:XTR_RD */ 1203 #define QS_XTR_RD(r) __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 8, r, 2, 4) 1204 1205 /* DEVCPU_QS:XTR:XTR_FLUSH */ 1206 #define QS_XTR_FLUSH __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 24, 0, 1, 4) 1207 1208 /* DEVCPU_QS:XTR:XTR_DATA_PRESENT */ 1209 #define QS_XTR_DATA_PRESENT __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 28, 0, 1, 4) 1210 1211 /* DEVCPU_QS:INJ:INJ_GRP_CFG */ 1212 #define QS_INJ_GRP_CFG(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 0, r, 2, 4) 1213 1214 #define QS_INJ_GRP_CFG_MODE GENMASK(3, 2) 1215 #define QS_INJ_GRP_CFG_MODE_SET(x)\ 1216 FIELD_PREP(QS_INJ_GRP_CFG_MODE, x) 1217 #define QS_INJ_GRP_CFG_MODE_GET(x)\ 1218 FIELD_GET(QS_INJ_GRP_CFG_MODE, x) 1219 1220 #define QS_INJ_GRP_CFG_BYTE_SWAP BIT(0) 1221 #define QS_INJ_GRP_CFG_BYTE_SWAP_SET(x)\ 1222 FIELD_PREP(QS_INJ_GRP_CFG_BYTE_SWAP, x) 1223 #define QS_INJ_GRP_CFG_BYTE_SWAP_GET(x)\ 1224 FIELD_GET(QS_INJ_GRP_CFG_BYTE_SWAP, x) 1225 1226 /* DEVCPU_QS:INJ:INJ_WR */ 1227 #define QS_INJ_WR(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 8, r, 2, 4) 1228 1229 /* DEVCPU_QS:INJ:INJ_CTRL */ 1230 #define QS_INJ_CTRL(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 16, r, 2, 4) 1231 1232 #define QS_INJ_CTRL_GAP_SIZE GENMASK(24, 21) 1233 #define QS_INJ_CTRL_GAP_SIZE_SET(x)\ 1234 FIELD_PREP(QS_INJ_CTRL_GAP_SIZE, x) 1235 #define QS_INJ_CTRL_GAP_SIZE_GET(x)\ 1236 FIELD_GET(QS_INJ_CTRL_GAP_SIZE, x) 1237 1238 #define QS_INJ_CTRL_EOF BIT(19) 1239 #define QS_INJ_CTRL_EOF_SET(x)\ 1240 FIELD_PREP(QS_INJ_CTRL_EOF, x) 1241 #define QS_INJ_CTRL_EOF_GET(x)\ 1242 FIELD_GET(QS_INJ_CTRL_EOF, x) 1243 1244 #define QS_INJ_CTRL_SOF BIT(18) 1245 #define QS_INJ_CTRL_SOF_SET(x)\ 1246 FIELD_PREP(QS_INJ_CTRL_SOF, x) 1247 #define QS_INJ_CTRL_SOF_GET(x)\ 1248 FIELD_GET(QS_INJ_CTRL_SOF, x) 1249 1250 #define QS_INJ_CTRL_VLD_BYTES GENMASK(17, 16) 1251 #define QS_INJ_CTRL_VLD_BYTES_SET(x)\ 1252 FIELD_PREP(QS_INJ_CTRL_VLD_BYTES, x) 1253 #define QS_INJ_CTRL_VLD_BYTES_GET(x)\ 1254 FIELD_GET(QS_INJ_CTRL_VLD_BYTES, x) 1255 1256 /* DEVCPU_QS:INJ:INJ_STATUS */ 1257 #define QS_INJ_STATUS __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 24, 0, 1, 4) 1258 1259 #define QS_INJ_STATUS_WMARK_REACHED GENMASK(5, 4) 1260 #define QS_INJ_STATUS_WMARK_REACHED_SET(x)\ 1261 FIELD_PREP(QS_INJ_STATUS_WMARK_REACHED, x) 1262 #define QS_INJ_STATUS_WMARK_REACHED_GET(x)\ 1263 FIELD_GET(QS_INJ_STATUS_WMARK_REACHED, x) 1264 1265 #define QS_INJ_STATUS_FIFO_RDY GENMASK(3, 2) 1266 #define QS_INJ_STATUS_FIFO_RDY_SET(x)\ 1267 FIELD_PREP(QS_INJ_STATUS_FIFO_RDY, x) 1268 #define QS_INJ_STATUS_FIFO_RDY_GET(x)\ 1269 FIELD_GET(QS_INJ_STATUS_FIFO_RDY, x) 1270 1271 /* QSYS:SYSTEM:PORT_MODE */ 1272 #define QSYS_PORT_MODE(r) __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 0, r, 10, 4) 1273 1274 #define QSYS_PORT_MODE_DEQUEUE_DIS BIT(1) 1275 #define QSYS_PORT_MODE_DEQUEUE_DIS_SET(x)\ 1276 FIELD_PREP(QSYS_PORT_MODE_DEQUEUE_DIS, x) 1277 #define QSYS_PORT_MODE_DEQUEUE_DIS_GET(x)\ 1278 FIELD_GET(QSYS_PORT_MODE_DEQUEUE_DIS, x) 1279 1280 /* QSYS:SYSTEM:SWITCH_PORT_MODE */ 1281 #define QSYS_SW_PORT_MODE(r) __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 80, r, 9, 4) 1282 1283 #define QSYS_SW_PORT_MODE_PORT_ENA BIT(18) 1284 #define QSYS_SW_PORT_MODE_PORT_ENA_SET(x)\ 1285 FIELD_PREP(QSYS_SW_PORT_MODE_PORT_ENA, x) 1286 #define QSYS_SW_PORT_MODE_PORT_ENA_GET(x)\ 1287 FIELD_GET(QSYS_SW_PORT_MODE_PORT_ENA, x) 1288 1289 #define QSYS_SW_PORT_MODE_SCH_NEXT_CFG GENMASK(16, 14) 1290 #define QSYS_SW_PORT_MODE_SCH_NEXT_CFG_SET(x)\ 1291 FIELD_PREP(QSYS_SW_PORT_MODE_SCH_NEXT_CFG, x) 1292 #define QSYS_SW_PORT_MODE_SCH_NEXT_CFG_GET(x)\ 1293 FIELD_GET(QSYS_SW_PORT_MODE_SCH_NEXT_CFG, x) 1294 1295 #define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE BIT(12) 1296 #define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE_SET(x)\ 1297 FIELD_PREP(QSYS_SW_PORT_MODE_INGRESS_DROP_MODE, x) 1298 #define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE_GET(x)\ 1299 FIELD_GET(QSYS_SW_PORT_MODE_INGRESS_DROP_MODE, x) 1300 1301 #define QSYS_SW_PORT_MODE_TX_PFC_ENA GENMASK(11, 4) 1302 #define QSYS_SW_PORT_MODE_TX_PFC_ENA_SET(x)\ 1303 FIELD_PREP(QSYS_SW_PORT_MODE_TX_PFC_ENA, x) 1304 #define QSYS_SW_PORT_MODE_TX_PFC_ENA_GET(x)\ 1305 FIELD_GET(QSYS_SW_PORT_MODE_TX_PFC_ENA, x) 1306 1307 #define QSYS_SW_PORT_MODE_AGING_MODE GENMASK(1, 0) 1308 #define QSYS_SW_PORT_MODE_AGING_MODE_SET(x)\ 1309 FIELD_PREP(QSYS_SW_PORT_MODE_AGING_MODE, x) 1310 #define QSYS_SW_PORT_MODE_AGING_MODE_GET(x)\ 1311 FIELD_GET(QSYS_SW_PORT_MODE_AGING_MODE, x) 1312 1313 /* QSYS:SYSTEM:SW_STATUS */ 1314 #define QSYS_SW_STATUS(r) __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 164, r, 9, 4) 1315 1316 #define QSYS_SW_STATUS_EQ_AVAIL GENMASK(7, 0) 1317 #define QSYS_SW_STATUS_EQ_AVAIL_SET(x)\ 1318 FIELD_PREP(QSYS_SW_STATUS_EQ_AVAIL, x) 1319 #define QSYS_SW_STATUS_EQ_AVAIL_GET(x)\ 1320 FIELD_GET(QSYS_SW_STATUS_EQ_AVAIL, x) 1321 1322 /* QSYS:SYSTEM:CPU_GROUP_MAP */ 1323 #define QSYS_CPU_GROUP_MAP __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 204, 0, 1, 4) 1324 1325 /* QSYS:RES_CTRL:RES_CFG */ 1326 #define QSYS_RES_CFG(g) __REG(TARGET_QSYS, 0, 1, 32768, g, 1024, 8, 0, 0, 1, 4) 1327 1328 /* QSYS:HSCH:CIR_CFG */ 1329 #define QSYS_CIR_CFG(g) __REG(TARGET_QSYS, 0, 1, 16384, g, 90, 128, 0, 0, 1, 4) 1330 1331 #define QSYS_CIR_CFG_CIR_RATE GENMASK(20, 6) 1332 #define QSYS_CIR_CFG_CIR_RATE_SET(x)\ 1333 FIELD_PREP(QSYS_CIR_CFG_CIR_RATE, x) 1334 #define QSYS_CIR_CFG_CIR_RATE_GET(x)\ 1335 FIELD_GET(QSYS_CIR_CFG_CIR_RATE, x) 1336 1337 #define QSYS_CIR_CFG_CIR_BURST GENMASK(5, 0) 1338 #define QSYS_CIR_CFG_CIR_BURST_SET(x)\ 1339 FIELD_PREP(QSYS_CIR_CFG_CIR_BURST, x) 1340 #define QSYS_CIR_CFG_CIR_BURST_GET(x)\ 1341 FIELD_GET(QSYS_CIR_CFG_CIR_BURST, x) 1342 1343 /* QSYS:HSCH:SE_CFG */ 1344 #define QSYS_SE_CFG(g) __REG(TARGET_QSYS, 0, 1, 16384, g, 90, 128, 8, 0, 1, 4) 1345 1346 #define QSYS_SE_CFG_SE_DWRR_CNT GENMASK(9, 6) 1347 #define QSYS_SE_CFG_SE_DWRR_CNT_SET(x)\ 1348 FIELD_PREP(QSYS_SE_CFG_SE_DWRR_CNT, x) 1349 #define QSYS_SE_CFG_SE_DWRR_CNT_GET(x)\ 1350 FIELD_GET(QSYS_SE_CFG_SE_DWRR_CNT, x) 1351 1352 #define QSYS_SE_CFG_SE_RR_ENA BIT(5) 1353 #define QSYS_SE_CFG_SE_RR_ENA_SET(x)\ 1354 FIELD_PREP(QSYS_SE_CFG_SE_RR_ENA, x) 1355 #define QSYS_SE_CFG_SE_RR_ENA_GET(x)\ 1356 FIELD_GET(QSYS_SE_CFG_SE_RR_ENA, x) 1357 1358 #define QSYS_SE_CFG_SE_AVB_ENA BIT(4) 1359 #define QSYS_SE_CFG_SE_AVB_ENA_SET(x)\ 1360 FIELD_PREP(QSYS_SE_CFG_SE_AVB_ENA, x) 1361 #define QSYS_SE_CFG_SE_AVB_ENA_GET(x)\ 1362 FIELD_GET(QSYS_SE_CFG_SE_AVB_ENA, x) 1363 1364 #define QSYS_SE_CFG_SE_FRM_MODE GENMASK(3, 2) 1365 #define QSYS_SE_CFG_SE_FRM_MODE_SET(x)\ 1366 FIELD_PREP(QSYS_SE_CFG_SE_FRM_MODE, x) 1367 #define QSYS_SE_CFG_SE_FRM_MODE_GET(x)\ 1368 FIELD_GET(QSYS_SE_CFG_SE_FRM_MODE, x) 1369 1370 #define QSYS_SE_DWRR_CFG(g, r) __REG(TARGET_QSYS, 0, 1, 16384, g, 90, 128, 12, r, 12, 4) 1371 1372 #define QSYS_SE_DWRR_CFG_DWRR_COST GENMASK(4, 0) 1373 #define QSYS_SE_DWRR_CFG_DWRR_COST_SET(x)\ 1374 FIELD_PREP(QSYS_SE_DWRR_CFG_DWRR_COST, x) 1375 #define QSYS_SE_DWRR_CFG_DWRR_COST_GET(x)\ 1376 FIELD_GET(QSYS_SE_DWRR_CFG_DWRR_COST, x) 1377 1378 /* QSYS:TAS_CONFIG:TAS_CFG_CTRL */ 1379 #define QSYS_TAS_CFG_CTRL __REG(TARGET_QSYS, 0, 1, 57372, 0, 1, 12, 0, 0, 1, 4) 1380 1381 #define QSYS_TAS_CFG_CTRL_LIST_NUM_MAX GENMASK(27, 23) 1382 #define QSYS_TAS_CFG_CTRL_LIST_NUM_MAX_SET(x)\ 1383 FIELD_PREP(QSYS_TAS_CFG_CTRL_LIST_NUM_MAX, x) 1384 #define QSYS_TAS_CFG_CTRL_LIST_NUM_MAX_GET(x)\ 1385 FIELD_GET(QSYS_TAS_CFG_CTRL_LIST_NUM_MAX, x) 1386 1387 #define QSYS_TAS_CFG_CTRL_LIST_NUM GENMASK(22, 18) 1388 #define QSYS_TAS_CFG_CTRL_LIST_NUM_SET(x)\ 1389 FIELD_PREP(QSYS_TAS_CFG_CTRL_LIST_NUM, x) 1390 #define QSYS_TAS_CFG_CTRL_LIST_NUM_GET(x)\ 1391 FIELD_GET(QSYS_TAS_CFG_CTRL_LIST_NUM, x) 1392 1393 #define QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q BIT(17) 1394 #define QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q_SET(x)\ 1395 FIELD_PREP(QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q, x) 1396 #define QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q_GET(x)\ 1397 FIELD_GET(QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q, x) 1398 1399 #define QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM GENMASK(16, 5) 1400 #define QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM_SET(x)\ 1401 FIELD_PREP(QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM, x) 1402 #define QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM_GET(x)\ 1403 FIELD_GET(QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM, x) 1404 1405 /* QSYS:TAS_CONFIG:TAS_GATE_STATE_CTRL */ 1406 #define QSYS_TAS_GS_CTRL __REG(TARGET_QSYS, 0, 1, 57372, 0, 1, 12, 4, 0, 1, 4) 1407 1408 #define QSYS_TAS_GS_CTRL_HSCH_POS GENMASK(2, 0) 1409 #define QSYS_TAS_GS_CTRL_HSCH_POS_SET(x)\ 1410 FIELD_PREP(QSYS_TAS_GS_CTRL_HSCH_POS, x) 1411 #define QSYS_TAS_GS_CTRL_HSCH_POS_GET(x)\ 1412 FIELD_GET(QSYS_TAS_GS_CTRL_HSCH_POS, x) 1413 1414 /* QSYS:TAS_CONFIG:TAS_STATEMACHINE_CFG */ 1415 #define QSYS_TAS_STM_CFG __REG(TARGET_QSYS, 0, 1, 57372, 0, 1, 12, 8, 0, 1, 4) 1416 1417 #define QSYS_TAS_STM_CFG_REVISIT_DLY GENMASK(7, 0) 1418 #define QSYS_TAS_STM_CFG_REVISIT_DLY_SET(x)\ 1419 FIELD_PREP(QSYS_TAS_STM_CFG_REVISIT_DLY, x) 1420 #define QSYS_TAS_STM_CFG_REVISIT_DLY_GET(x)\ 1421 FIELD_GET(QSYS_TAS_STM_CFG_REVISIT_DLY, x) 1422 1423 /* QSYS:TAS_PROFILE_CFG:TAS_PROFILE_CONFIG */ 1424 #define QSYS_TAS_PROFILE_CFG(g) __REG(TARGET_QSYS, 0, 1, 30720, g, 16, 64, 32, 0, 1, 4) 1425 1426 #define QSYS_TAS_PROFILE_CFG_PORT_NUM GENMASK(21, 19) 1427 #define QSYS_TAS_PROFILE_CFG_PORT_NUM_SET(x)\ 1428 FIELD_PREP(QSYS_TAS_PROFILE_CFG_PORT_NUM, x) 1429 #define QSYS_TAS_PROFILE_CFG_PORT_NUM_GET(x)\ 1430 FIELD_GET(QSYS_TAS_PROFILE_CFG_PORT_NUM, x) 1431 1432 #define QSYS_TAS_PROFILE_CFG_LINK_SPEED GENMASK(18, 16) 1433 #define QSYS_TAS_PROFILE_CFG_LINK_SPEED_SET(x)\ 1434 FIELD_PREP(QSYS_TAS_PROFILE_CFG_LINK_SPEED, x) 1435 #define QSYS_TAS_PROFILE_CFG_LINK_SPEED_GET(x)\ 1436 FIELD_GET(QSYS_TAS_PROFILE_CFG_LINK_SPEED, x) 1437 1438 /* QSYS:TAS_LIST_CFG:TAS_BASE_TIME_NSEC */ 1439 #define QSYS_TAS_BT_NSEC __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 0, 0, 1, 4) 1440 1441 #define QSYS_TAS_BT_NSEC_NSEC GENMASK(29, 0) 1442 #define QSYS_TAS_BT_NSEC_NSEC_SET(x)\ 1443 FIELD_PREP(QSYS_TAS_BT_NSEC_NSEC, x) 1444 #define QSYS_TAS_BT_NSEC_NSEC_GET(x)\ 1445 FIELD_GET(QSYS_TAS_BT_NSEC_NSEC, x) 1446 1447 /* QSYS:TAS_LIST_CFG:TAS_BASE_TIME_SEC_LSB */ 1448 #define QSYS_TAS_BT_SEC_LSB __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 4, 0, 1, 4) 1449 1450 /* QSYS:TAS_LIST_CFG:TAS_BASE_TIME_SEC_MSB */ 1451 #define QSYS_TAS_BT_SEC_MSB __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 8, 0, 1, 4) 1452 1453 #define QSYS_TAS_BT_SEC_MSB_SEC_MSB GENMASK(15, 0) 1454 #define QSYS_TAS_BT_SEC_MSB_SEC_MSB_SET(x)\ 1455 FIELD_PREP(QSYS_TAS_BT_SEC_MSB_SEC_MSB, x) 1456 #define QSYS_TAS_BT_SEC_MSB_SEC_MSB_GET(x)\ 1457 FIELD_GET(QSYS_TAS_BT_SEC_MSB_SEC_MSB, x) 1458 1459 /* QSYS:TAS_LIST_CFG:TAS_CYCLE_TIME_CFG */ 1460 #define QSYS_TAS_CT_CFG __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 24, 0, 1, 4) 1461 1462 /* QSYS:TAS_LIST_CFG:TAS_STARTUP_CFG */ 1463 #define QSYS_TAS_STARTUP_CFG __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 28, 0, 1, 4) 1464 1465 #define QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX GENMASK(27, 23) 1466 #define QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX_SET(x)\ 1467 FIELD_PREP(QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX, x) 1468 #define QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX_GET(x)\ 1469 FIELD_GET(QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX, x) 1470 1471 /* QSYS:TAS_LIST_CFG:TAS_LIST_CFG */ 1472 #define QSYS_TAS_LIST_CFG __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 32, 0, 1, 4) 1473 1474 #define QSYS_TAS_LIST_CFG_LIST_BASE_ADDR GENMASK(11, 0) 1475 #define QSYS_TAS_LIST_CFG_LIST_BASE_ADDR_SET(x)\ 1476 FIELD_PREP(QSYS_TAS_LIST_CFG_LIST_BASE_ADDR, x) 1477 #define QSYS_TAS_LIST_CFG_LIST_BASE_ADDR_GET(x)\ 1478 FIELD_GET(QSYS_TAS_LIST_CFG_LIST_BASE_ADDR, x) 1479 1480 /* QSYS:TAS_LIST_CFG:TAS_LIST_STATE */ 1481 #define QSYS_TAS_LST __REG(TARGET_QSYS, 0, 1, 27904, 0, 1, 64, 36, 0, 1, 4) 1482 1483 #define QSYS_TAS_LST_LIST_STATE GENMASK(2, 0) 1484 #define QSYS_TAS_LST_LIST_STATE_SET(x)\ 1485 FIELD_PREP(QSYS_TAS_LST_LIST_STATE, x) 1486 #define QSYS_TAS_LST_LIST_STATE_GET(x)\ 1487 FIELD_GET(QSYS_TAS_LST_LIST_STATE, x) 1488 1489 /* QSYS:TAS_GCL_CFG:TAS_GCL_CTRL_CFG */ 1490 #define QSYS_TAS_GCL_CT_CFG __REG(TARGET_QSYS, 0, 1, 27968, 0, 1, 16, 0, 0, 1, 4) 1491 1492 #define QSYS_TAS_GCL_CT_CFG_HSCH_POS GENMASK(12, 10) 1493 #define QSYS_TAS_GCL_CT_CFG_HSCH_POS_SET(x)\ 1494 FIELD_PREP(QSYS_TAS_GCL_CT_CFG_HSCH_POS, x) 1495 #define QSYS_TAS_GCL_CT_CFG_HSCH_POS_GET(x)\ 1496 FIELD_GET(QSYS_TAS_GCL_CT_CFG_HSCH_POS, x) 1497 1498 #define QSYS_TAS_GCL_CT_CFG_GATE_STATE GENMASK(9, 2) 1499 #define QSYS_TAS_GCL_CT_CFG_GATE_STATE_SET(x)\ 1500 FIELD_PREP(QSYS_TAS_GCL_CT_CFG_GATE_STATE, x) 1501 #define QSYS_TAS_GCL_CT_CFG_GATE_STATE_GET(x)\ 1502 FIELD_GET(QSYS_TAS_GCL_CT_CFG_GATE_STATE, x) 1503 1504 #define QSYS_TAS_GCL_CT_CFG_OP_TYPE GENMASK(1, 0) 1505 #define QSYS_TAS_GCL_CT_CFG_OP_TYPE_SET(x)\ 1506 FIELD_PREP(QSYS_TAS_GCL_CT_CFG_OP_TYPE, x) 1507 #define QSYS_TAS_GCL_CT_CFG_OP_TYPE_GET(x)\ 1508 FIELD_GET(QSYS_TAS_GCL_CT_CFG_OP_TYPE, x) 1509 1510 /* QSYS:TAS_GCL_CFG:TAS_GCL_CTRL_CFG2 */ 1511 #define QSYS_TAS_GCL_CT_CFG2 __REG(TARGET_QSYS, 0, 1, 27968, 0, 1, 16, 4, 0, 1, 4) 1512 1513 #define QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE GENMASK(15, 12) 1514 #define QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE_SET(x)\ 1515 FIELD_PREP(QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE, x) 1516 #define QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE_GET(x)\ 1517 FIELD_GET(QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE, x) 1518 1519 #define QSYS_TAS_GCL_CT_CFG2_NEXT_GCL GENMASK(11, 0) 1520 #define QSYS_TAS_GCL_CT_CFG2_NEXT_GCL_SET(x)\ 1521 FIELD_PREP(QSYS_TAS_GCL_CT_CFG2_NEXT_GCL, x) 1522 #define QSYS_TAS_GCL_CT_CFG2_NEXT_GCL_GET(x)\ 1523 FIELD_GET(QSYS_TAS_GCL_CT_CFG2_NEXT_GCL, x) 1524 1525 /* QSYS:TAS_GCL_CFG:TAS_GCL_TIME_CFG */ 1526 #define QSYS_TAS_GCL_TM_CFG __REG(TARGET_QSYS, 0, 1, 27968, 0, 1, 16, 8, 0, 1, 4) 1527 1528 /* QSYS:HSCH_TAS_STATE:TAS_GATE_STATE */ 1529 #define QSYS_TAS_GATE_STATE __REG(TARGET_QSYS, 0, 1, 28004, 0, 1, 4, 0, 0, 1, 4) 1530 1531 #define QSYS_TAS_GATE_STATE_TAS_GATE_STATE GENMASK(7, 0) 1532 #define QSYS_TAS_GATE_STATE_TAS_GATE_STATE_SET(x)\ 1533 FIELD_PREP(QSYS_TAS_GATE_STATE_TAS_GATE_STATE, x) 1534 #define QSYS_TAS_GATE_STATE_TAS_GATE_STATE_GET(x)\ 1535 FIELD_GET(QSYS_TAS_GATE_STATE_TAS_GATE_STATE, x) 1536 1537 /* REW:PORT:PORT_VLAN_CFG */ 1538 #define REW_PORT_VLAN_CFG(g) __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 0, 0, 1, 4) 1539 1540 #define REW_PORT_VLAN_CFG_PORT_TPID GENMASK(31, 16) 1541 #define REW_PORT_VLAN_CFG_PORT_TPID_SET(x)\ 1542 FIELD_PREP(REW_PORT_VLAN_CFG_PORT_TPID, x) 1543 #define REW_PORT_VLAN_CFG_PORT_TPID_GET(x)\ 1544 FIELD_GET(REW_PORT_VLAN_CFG_PORT_TPID, x) 1545 1546 #define REW_PORT_VLAN_CFG_PORT_VID GENMASK(11, 0) 1547 #define REW_PORT_VLAN_CFG_PORT_VID_SET(x)\ 1548 FIELD_PREP(REW_PORT_VLAN_CFG_PORT_VID, x) 1549 #define REW_PORT_VLAN_CFG_PORT_VID_GET(x)\ 1550 FIELD_GET(REW_PORT_VLAN_CFG_PORT_VID, x) 1551 1552 /* REW:PORT:TAG_CFG */ 1553 #define REW_TAG_CFG(g) __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 4, 0, 1, 4) 1554 1555 #define REW_TAG_CFG_TAG_CFG GENMASK(8, 7) 1556 #define REW_TAG_CFG_TAG_CFG_SET(x)\ 1557 FIELD_PREP(REW_TAG_CFG_TAG_CFG, x) 1558 #define REW_TAG_CFG_TAG_CFG_GET(x)\ 1559 FIELD_GET(REW_TAG_CFG_TAG_CFG, x) 1560 1561 #define REW_TAG_CFG_TAG_TPID_CFG GENMASK(6, 5) 1562 #define REW_TAG_CFG_TAG_TPID_CFG_SET(x)\ 1563 FIELD_PREP(REW_TAG_CFG_TAG_TPID_CFG, x) 1564 #define REW_TAG_CFG_TAG_TPID_CFG_GET(x)\ 1565 FIELD_GET(REW_TAG_CFG_TAG_TPID_CFG, x) 1566 1567 #define REW_TAG_CFG_TAG_PCP_CFG GENMASK(3, 2) 1568 #define REW_TAG_CFG_TAG_PCP_CFG_SET(x)\ 1569 FIELD_PREP(REW_TAG_CFG_TAG_PCP_CFG, x) 1570 #define REW_TAG_CFG_TAG_PCP_CFG_GET(x)\ 1571 FIELD_GET(REW_TAG_CFG_TAG_PCP_CFG, x) 1572 1573 #define REW_TAG_CFG_TAG_DEI_CFG GENMASK(1, 0) 1574 #define REW_TAG_CFG_TAG_DEI_CFG_SET(x)\ 1575 FIELD_PREP(REW_TAG_CFG_TAG_DEI_CFG, x) 1576 #define REW_TAG_CFG_TAG_DEI_CFG_GET(x)\ 1577 FIELD_GET(REW_TAG_CFG_TAG_DEI_CFG, x) 1578 1579 /* REW:PORT:PORT_CFG */ 1580 #define REW_PORT_CFG(g) __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 8, 0, 1, 4) 1581 1582 #define REW_PORT_CFG_ES0_EN BIT(4) 1583 #define REW_PORT_CFG_ES0_EN_SET(x)\ 1584 FIELD_PREP(REW_PORT_CFG_ES0_EN, x) 1585 #define REW_PORT_CFG_ES0_EN_GET(x)\ 1586 FIELD_GET(REW_PORT_CFG_ES0_EN, x) 1587 1588 #define REW_PORT_CFG_NO_REWRITE BIT(0) 1589 #define REW_PORT_CFG_NO_REWRITE_SET(x)\ 1590 FIELD_PREP(REW_PORT_CFG_NO_REWRITE, x) 1591 #define REW_PORT_CFG_NO_REWRITE_GET(x)\ 1592 FIELD_GET(REW_PORT_CFG_NO_REWRITE, x) 1593 1594 /* REW:PORT:DSCP_CFG */ 1595 #define REW_DSCP_CFG(g) __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 12, 0, 1, 4) 1596 1597 #define REW_DSCP_CFG_DSCP_REWR_CFG GENMASK(1, 0) 1598 #define REW_DSCP_CFG_DSCP_REWR_CFG_SET(x)\ 1599 FIELD_PREP(REW_DSCP_CFG_DSCP_REWR_CFG, x) 1600 #define REW_DSCP_CFG_DSCP_REWR_CFG_GET(x)\ 1601 FIELD_GET(REW_DSCP_CFG_DSCP_REWR_CFG, x) 1602 1603 /* REW:PORT:PCP_DEI_QOS_MAP_CFG */ 1604 #define REW_PCP_DEI_CFG(g, r) __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 16, r, 16, 4) 1605 1606 #define REW_PCP_DEI_CFG_DEI_QOS_VAL BIT(3) 1607 #define REW_PCP_DEI_CFG_DEI_QOS_VAL_SET(x)\ 1608 FIELD_PREP(REW_PCP_DEI_CFG_DEI_QOS_VAL, x) 1609 #define REW_PCP_DEI_CFG_DEI_QOS_VAL_GET(x)\ 1610 FIELD_GET(REW_PCP_DEI_CFG_DEI_QOS_VAL, x) 1611 1612 #define REW_PCP_DEI_CFG_PCP_QOS_VAL GENMASK(2, 0) 1613 #define REW_PCP_DEI_CFG_PCP_QOS_VAL_SET(x)\ 1614 FIELD_PREP(REW_PCP_DEI_CFG_PCP_QOS_VAL, x) 1615 #define REW_PCP_DEI_CFG_PCP_QOS_VAL_GET(x)\ 1616 FIELD_GET(REW_PCP_DEI_CFG_PCP_QOS_VAL, x) 1617 1618 /* REW:COMMON:STAT_CFG */ 1619 #define REW_STAT_CFG __REG(TARGET_REW, 0, 1, 3072, 0, 1, 528, 520, 0, 1, 4) 1620 1621 #define REW_STAT_CFG_STAT_MODE GENMASK(1, 0) 1622 #define REW_STAT_CFG_STAT_MODE_SET(x)\ 1623 FIELD_PREP(REW_STAT_CFG_STAT_MODE, x) 1624 #define REW_STAT_CFG_STAT_MODE_GET(x)\ 1625 FIELD_GET(REW_STAT_CFG_STAT_MODE, x) 1626 1627 /* SYS:SYSTEM:RESET_CFG */ 1628 #define SYS_RESET_CFG __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 0, 0, 1, 4) 1629 1630 #define SYS_RESET_CFG_CORE_ENA BIT(0) 1631 #define SYS_RESET_CFG_CORE_ENA_SET(x)\ 1632 FIELD_PREP(SYS_RESET_CFG_CORE_ENA, x) 1633 #define SYS_RESET_CFG_CORE_ENA_GET(x)\ 1634 FIELD_GET(SYS_RESET_CFG_CORE_ENA, x) 1635 1636 /* SYS:SYSTEM:PORT_MODE */ 1637 #define SYS_PORT_MODE(r) __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 44, r, 10, 4) 1638 1639 #define SYS_PORT_MODE_INCL_INJ_HDR GENMASK(5, 4) 1640 #define SYS_PORT_MODE_INCL_INJ_HDR_SET(x)\ 1641 FIELD_PREP(SYS_PORT_MODE_INCL_INJ_HDR, x) 1642 #define SYS_PORT_MODE_INCL_INJ_HDR_GET(x)\ 1643 FIELD_GET(SYS_PORT_MODE_INCL_INJ_HDR, x) 1644 1645 #define SYS_PORT_MODE_INCL_XTR_HDR GENMASK(3, 2) 1646 #define SYS_PORT_MODE_INCL_XTR_HDR_SET(x)\ 1647 FIELD_PREP(SYS_PORT_MODE_INCL_XTR_HDR, x) 1648 #define SYS_PORT_MODE_INCL_XTR_HDR_GET(x)\ 1649 FIELD_GET(SYS_PORT_MODE_INCL_XTR_HDR, x) 1650 1651 /* SYS:SYSTEM:FRONT_PORT_MODE */ 1652 #define SYS_FRONT_PORT_MODE(r) __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 84, r, 8, 4) 1653 1654 #define SYS_FRONT_PORT_MODE_HDX_MODE BIT(1) 1655 #define SYS_FRONT_PORT_MODE_HDX_MODE_SET(x)\ 1656 FIELD_PREP(SYS_FRONT_PORT_MODE_HDX_MODE, x) 1657 #define SYS_FRONT_PORT_MODE_HDX_MODE_GET(x)\ 1658 FIELD_GET(SYS_FRONT_PORT_MODE_HDX_MODE, x) 1659 1660 /* SYS:SYSTEM:FRM_AGING */ 1661 #define SYS_FRM_AGING __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 116, 0, 1, 4) 1662 1663 #define SYS_FRM_AGING_AGE_TX_ENA BIT(20) 1664 #define SYS_FRM_AGING_AGE_TX_ENA_SET(x)\ 1665 FIELD_PREP(SYS_FRM_AGING_AGE_TX_ENA, x) 1666 #define SYS_FRM_AGING_AGE_TX_ENA_GET(x)\ 1667 FIELD_GET(SYS_FRM_AGING_AGE_TX_ENA, x) 1668 1669 /* SYS:SYSTEM:STAT_CFG */ 1670 #define SYS_STAT_CFG __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 120, 0, 1, 4) 1671 1672 #define SYS_STAT_CFG_STAT_VIEW GENMASK(9, 0) 1673 #define SYS_STAT_CFG_STAT_VIEW_SET(x)\ 1674 FIELD_PREP(SYS_STAT_CFG_STAT_VIEW, x) 1675 #define SYS_STAT_CFG_STAT_VIEW_GET(x)\ 1676 FIELD_GET(SYS_STAT_CFG_STAT_VIEW, x) 1677 1678 /* SYS:PAUSE_CFG:PAUSE_CFG */ 1679 #define SYS_PAUSE_CFG(r) __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 0, r, 9, 4) 1680 1681 #define SYS_PAUSE_CFG_PAUSE_START GENMASK(18, 10) 1682 #define SYS_PAUSE_CFG_PAUSE_START_SET(x)\ 1683 FIELD_PREP(SYS_PAUSE_CFG_PAUSE_START, x) 1684 #define SYS_PAUSE_CFG_PAUSE_START_GET(x)\ 1685 FIELD_GET(SYS_PAUSE_CFG_PAUSE_START, x) 1686 1687 #define SYS_PAUSE_CFG_PAUSE_STOP GENMASK(9, 1) 1688 #define SYS_PAUSE_CFG_PAUSE_STOP_SET(x)\ 1689 FIELD_PREP(SYS_PAUSE_CFG_PAUSE_STOP, x) 1690 #define SYS_PAUSE_CFG_PAUSE_STOP_GET(x)\ 1691 FIELD_GET(SYS_PAUSE_CFG_PAUSE_STOP, x) 1692 1693 #define SYS_PAUSE_CFG_PAUSE_ENA BIT(0) 1694 #define SYS_PAUSE_CFG_PAUSE_ENA_SET(x)\ 1695 FIELD_PREP(SYS_PAUSE_CFG_PAUSE_ENA, x) 1696 #define SYS_PAUSE_CFG_PAUSE_ENA_GET(x)\ 1697 FIELD_GET(SYS_PAUSE_CFG_PAUSE_ENA, x) 1698 1699 /* SYS:PAUSE_CFG:ATOP */ 1700 #define SYS_ATOP(r) __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 40, r, 9, 4) 1701 1702 /* SYS:PAUSE_CFG:ATOP_TOT_CFG */ 1703 #define SYS_ATOP_TOT_CFG __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 76, 0, 1, 4) 1704 1705 /* SYS:PAUSE_CFG:MAC_FC_CFG */ 1706 #define SYS_MAC_FC_CFG(r) __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 80, r, 8, 4) 1707 1708 #define SYS_MAC_FC_CFG_FC_LINK_SPEED GENMASK(27, 26) 1709 #define SYS_MAC_FC_CFG_FC_LINK_SPEED_SET(x)\ 1710 FIELD_PREP(SYS_MAC_FC_CFG_FC_LINK_SPEED, x) 1711 #define SYS_MAC_FC_CFG_FC_LINK_SPEED_GET(x)\ 1712 FIELD_GET(SYS_MAC_FC_CFG_FC_LINK_SPEED, x) 1713 1714 #define SYS_MAC_FC_CFG_FC_LATENCY_CFG GENMASK(25, 20) 1715 #define SYS_MAC_FC_CFG_FC_LATENCY_CFG_SET(x)\ 1716 FIELD_PREP(SYS_MAC_FC_CFG_FC_LATENCY_CFG, x) 1717 #define SYS_MAC_FC_CFG_FC_LATENCY_CFG_GET(x)\ 1718 FIELD_GET(SYS_MAC_FC_CFG_FC_LATENCY_CFG, x) 1719 1720 #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA BIT(18) 1721 #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA_SET(x)\ 1722 FIELD_PREP(SYS_MAC_FC_CFG_ZERO_PAUSE_ENA, x) 1723 #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA_GET(x)\ 1724 FIELD_GET(SYS_MAC_FC_CFG_ZERO_PAUSE_ENA, x) 1725 1726 #define SYS_MAC_FC_CFG_TX_FC_ENA BIT(17) 1727 #define SYS_MAC_FC_CFG_TX_FC_ENA_SET(x)\ 1728 FIELD_PREP(SYS_MAC_FC_CFG_TX_FC_ENA, x) 1729 #define SYS_MAC_FC_CFG_TX_FC_ENA_GET(x)\ 1730 FIELD_GET(SYS_MAC_FC_CFG_TX_FC_ENA, x) 1731 1732 #define SYS_MAC_FC_CFG_RX_FC_ENA BIT(16) 1733 #define SYS_MAC_FC_CFG_RX_FC_ENA_SET(x)\ 1734 FIELD_PREP(SYS_MAC_FC_CFG_RX_FC_ENA, x) 1735 #define SYS_MAC_FC_CFG_RX_FC_ENA_GET(x)\ 1736 FIELD_GET(SYS_MAC_FC_CFG_RX_FC_ENA, x) 1737 1738 #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG GENMASK(15, 0) 1739 #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG_SET(x)\ 1740 FIELD_PREP(SYS_MAC_FC_CFG_PAUSE_VAL_CFG, x) 1741 #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG_GET(x)\ 1742 FIELD_GET(SYS_MAC_FC_CFG_PAUSE_VAL_CFG, x) 1743 1744 /* SYS:STAT:CNT */ 1745 #define SYS_CNT(g) __REG(TARGET_SYS, 0, 1, 0, g, 896, 4, 0, 0, 1, 4) 1746 1747 /* SYS:RAM_CTRL:RAM_INIT */ 1748 #define SYS_RAM_INIT __REG(TARGET_SYS, 0, 1, 4432, 0, 1, 4, 0, 0, 1, 4) 1749 1750 #define SYS_RAM_INIT_RAM_INIT BIT(1) 1751 #define SYS_RAM_INIT_RAM_INIT_SET(x)\ 1752 FIELD_PREP(SYS_RAM_INIT_RAM_INIT, x) 1753 #define SYS_RAM_INIT_RAM_INIT_GET(x)\ 1754 FIELD_GET(SYS_RAM_INIT_RAM_INIT, x) 1755 1756 /* VCAP:VCAP_CORE_CFG:VCAP_UPDATE_CTRL */ 1757 #define VCAP_UPDATE_CTRL(t) __REG(TARGET_VCAP, t, 3, 0, 0, 1, 8, 0, 0, 1, 4) 1758 1759 #define VCAP_UPDATE_CTRL_UPDATE_CMD GENMASK(24, 22) 1760 #define VCAP_UPDATE_CTRL_UPDATE_CMD_SET(x)\ 1761 FIELD_PREP(VCAP_UPDATE_CTRL_UPDATE_CMD, x) 1762 #define VCAP_UPDATE_CTRL_UPDATE_CMD_GET(x)\ 1763 FIELD_GET(VCAP_UPDATE_CTRL_UPDATE_CMD, x) 1764 1765 #define VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS BIT(21) 1766 #define VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS_SET(x)\ 1767 FIELD_PREP(VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS, x) 1768 #define VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS_GET(x)\ 1769 FIELD_GET(VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS, x) 1770 1771 #define VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS BIT(20) 1772 #define VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS_SET(x)\ 1773 FIELD_PREP(VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS, x) 1774 #define VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS_GET(x)\ 1775 FIELD_GET(VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS, x) 1776 1777 #define VCAP_UPDATE_CTRL_UPDATE_CNT_DIS BIT(19) 1778 #define VCAP_UPDATE_CTRL_UPDATE_CNT_DIS_SET(x)\ 1779 FIELD_PREP(VCAP_UPDATE_CTRL_UPDATE_CNT_DIS, x) 1780 #define VCAP_UPDATE_CTRL_UPDATE_CNT_DIS_GET(x)\ 1781 FIELD_GET(VCAP_UPDATE_CTRL_UPDATE_CNT_DIS, x) 1782 1783 #define VCAP_UPDATE_CTRL_UPDATE_ADDR GENMASK(18, 3) 1784 #define VCAP_UPDATE_CTRL_UPDATE_ADDR_SET(x)\ 1785 FIELD_PREP(VCAP_UPDATE_CTRL_UPDATE_ADDR, x) 1786 #define VCAP_UPDATE_CTRL_UPDATE_ADDR_GET(x)\ 1787 FIELD_GET(VCAP_UPDATE_CTRL_UPDATE_ADDR, x) 1788 1789 #define VCAP_UPDATE_CTRL_UPDATE_SHOT BIT(2) 1790 #define VCAP_UPDATE_CTRL_UPDATE_SHOT_SET(x)\ 1791 FIELD_PREP(VCAP_UPDATE_CTRL_UPDATE_SHOT, x) 1792 #define VCAP_UPDATE_CTRL_UPDATE_SHOT_GET(x)\ 1793 FIELD_GET(VCAP_UPDATE_CTRL_UPDATE_SHOT, x) 1794 1795 #define VCAP_UPDATE_CTRL_CLEAR_CACHE BIT(1) 1796 #define VCAP_UPDATE_CTRL_CLEAR_CACHE_SET(x)\ 1797 FIELD_PREP(VCAP_UPDATE_CTRL_CLEAR_CACHE, x) 1798 #define VCAP_UPDATE_CTRL_CLEAR_CACHE_GET(x)\ 1799 FIELD_GET(VCAP_UPDATE_CTRL_CLEAR_CACHE, x) 1800 1801 #define VCAP_UPDATE_CTRL_MV_TRAFFIC_IGN BIT(0) 1802 #define VCAP_UPDATE_CTRL_MV_TRAFFIC_IGN_SET(x)\ 1803 FIELD_PREP(VCAP_UPDATE_CTRL_MV_TRAFFIC_IGN, x) 1804 #define VCAP_UPDATE_CTRL_MV_TRAFFIC_IGN_GET(x)\ 1805 FIELD_GET(VCAP_UPDATE_CTRL_MV_TRAFFIC_IGN, x) 1806 1807 /* VCAP:VCAP_CORE_CFG:VCAP_MV_CFG */ 1808 #define VCAP_MV_CFG(t) __REG(TARGET_VCAP, t, 3, 0, 0, 1, 8, 4, 0, 1, 4) 1809 1810 #define VCAP_MV_CFG_MV_NUM_POS GENMASK(31, 16) 1811 #define VCAP_MV_CFG_MV_NUM_POS_SET(x)\ 1812 FIELD_PREP(VCAP_MV_CFG_MV_NUM_POS, x) 1813 #define VCAP_MV_CFG_MV_NUM_POS_GET(x)\ 1814 FIELD_GET(VCAP_MV_CFG_MV_NUM_POS, x) 1815 1816 #define VCAP_MV_CFG_MV_SIZE GENMASK(15, 0) 1817 #define VCAP_MV_CFG_MV_SIZE_SET(x)\ 1818 FIELD_PREP(VCAP_MV_CFG_MV_SIZE, x) 1819 #define VCAP_MV_CFG_MV_SIZE_GET(x)\ 1820 FIELD_GET(VCAP_MV_CFG_MV_SIZE, x) 1821 1822 /* VCAP:VCAP_CORE_CACHE:VCAP_ENTRY_DAT */ 1823 #define VCAP_ENTRY_DAT(t, r) __REG(TARGET_VCAP, t, 3, 8, 0, 1, 904, 0, r, 64, 4) 1824 1825 /* VCAP:VCAP_CORE_CACHE:VCAP_MASK_DAT */ 1826 #define VCAP_MASK_DAT(t, r) __REG(TARGET_VCAP, t, 3, 8, 0, 1, 904, 256, r, 64, 4) 1827 1828 /* VCAP:VCAP_CORE_CACHE:VCAP_ACTION_DAT */ 1829 #define VCAP_ACTION_DAT(t, r) __REG(TARGET_VCAP, t, 3, 8, 0, 1, 904, 512, r, 64, 4) 1830 1831 /* VCAP:VCAP_CORE_CACHE:VCAP_CNT_DAT */ 1832 #define VCAP_CNT_DAT(t, r) __REG(TARGET_VCAP, t, 3, 8, 0, 1, 904, 768, r, 32, 4) 1833 1834 /* VCAP:VCAP_CORE_CACHE:VCAP_CNT_FW_DAT */ 1835 #define VCAP_CNT_FW_DAT(t) __REG(TARGET_VCAP, t, 3, 8, 0, 1, 904, 896, 0, 1, 4) 1836 1837 /* VCAP:VCAP_CORE_CACHE:VCAP_TG_DAT */ 1838 #define VCAP_TG_DAT(t) __REG(TARGET_VCAP, t, 3, 8, 0, 1, 904, 900, 0, 1, 4) 1839 1840 /* VCAP:VCAP_CORE_MAP:VCAP_CORE_IDX */ 1841 #define VCAP_CORE_IDX(t) __REG(TARGET_VCAP, t, 3, 912, 0, 1, 8, 0, 0, 1, 4) 1842 1843 #define VCAP_CORE_IDX_CORE_IDX GENMASK(3, 0) 1844 #define VCAP_CORE_IDX_CORE_IDX_SET(x)\ 1845 FIELD_PREP(VCAP_CORE_IDX_CORE_IDX, x) 1846 #define VCAP_CORE_IDX_CORE_IDX_GET(x)\ 1847 FIELD_GET(VCAP_CORE_IDX_CORE_IDX, x) 1848 1849 /* VCAP:VCAP_CORE_MAP:VCAP_CORE_MAP */ 1850 #define VCAP_CORE_MAP(t) __REG(TARGET_VCAP, t, 3, 912, 0, 1, 8, 4, 0, 1, 4) 1851 1852 #define VCAP_CORE_MAP_CORE_MAP GENMASK(2, 0) 1853 #define VCAP_CORE_MAP_CORE_MAP_SET(x)\ 1854 FIELD_PREP(VCAP_CORE_MAP_CORE_MAP, x) 1855 #define VCAP_CORE_MAP_CORE_MAP_GET(x)\ 1856 FIELD_GET(VCAP_CORE_MAP_CORE_MAP, x) 1857 1858 /* VCAP:VCAP_CONST:VCAP_VER */ 1859 #define VCAP_VER(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 0, 0, 1, 4) 1860 1861 /* VCAP:VCAP_CONST:ENTRY_WIDTH */ 1862 #define VCAP_ENTRY_WIDTH(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 4, 0, 1, 4) 1863 1864 /* VCAP:VCAP_CONST:ENTRY_CNT */ 1865 #define VCAP_ENTRY_CNT(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 8, 0, 1, 4) 1866 1867 /* VCAP:VCAP_CONST:ENTRY_SWCNT */ 1868 #define VCAP_ENTRY_SWCNT(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 12, 0, 1, 4) 1869 1870 /* VCAP:VCAP_CONST:ENTRY_TG_WIDTH */ 1871 #define VCAP_ENTRY_TG_WIDTH(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 16, 0, 1, 4) 1872 1873 /* VCAP:VCAP_CONST:ACTION_DEF_CNT */ 1874 #define VCAP_ACTION_DEF_CNT(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 20, 0, 1, 4) 1875 1876 /* VCAP:VCAP_CONST:ACTION_WIDTH */ 1877 #define VCAP_ACTION_WIDTH(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 24, 0, 1, 4) 1878 1879 /* VCAP:VCAP_CONST:CNT_WIDTH */ 1880 #define VCAP_CNT_WIDTH(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 28, 0, 1, 4) 1881 1882 /* VCAP:VCAP_CONST:CORE_CNT */ 1883 #define VCAP_CORE_CNT(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 32, 0, 1, 4) 1884 1885 /* VCAP:VCAP_CONST:IF_CNT */ 1886 #define VCAP_IF_CNT(t) __REG(TARGET_VCAP, t, 3, 924, 0, 1, 40, 36, 0, 1, 4) 1887 1888 #endif /* _LAN966X_REGS_H_ */ 1889