1 // SPDX-License-Identifier: GPL-2.0+ 2 3 #include <linux/netdevice.h> 4 #include <linux/phy/phy.h> 5 6 #include "lan966x_main.h" 7 8 /* Watermark encode */ 9 #define MULTIPLIER_BIT BIT(8) 10 static u32 lan966x_wm_enc(u32 value) 11 { 12 value /= LAN966X_BUFFER_CELL_SZ; 13 14 if (value >= MULTIPLIER_BIT) { 15 value /= 16; 16 if (value >= MULTIPLIER_BIT) 17 value = (MULTIPLIER_BIT - 1); 18 19 value |= MULTIPLIER_BIT; 20 } 21 22 return value; 23 } 24 25 static void lan966x_port_link_down(struct lan966x_port *port) 26 { 27 struct lan966x *lan966x = port->lan966x; 28 u32 val, delay = 0; 29 30 /* 0.5: Disable any AFI */ 31 lan_rmw(AFI_PORT_CFG_FC_SKIP_TTI_INJ_SET(1) | 32 AFI_PORT_CFG_FRM_OUT_MAX_SET(0), 33 AFI_PORT_CFG_FC_SKIP_TTI_INJ | 34 AFI_PORT_CFG_FRM_OUT_MAX, 35 lan966x, AFI_PORT_CFG(port->chip_port)); 36 37 /* wait for reg afi_port_frm_out to become 0 for the port */ 38 while (true) { 39 val = lan_rd(lan966x, AFI_PORT_FRM_OUT(port->chip_port)); 40 if (!AFI_PORT_FRM_OUT_FRM_OUT_CNT_GET(val)) 41 break; 42 43 usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC); 44 delay++; 45 if (delay == 2000) { 46 pr_err("AFI timeout chip port %u", port->chip_port); 47 break; 48 } 49 } 50 51 delay = 0; 52 53 /* 1: Reset the PCS Rx clock domain */ 54 lan_rmw(DEV_CLOCK_CFG_PCS_RX_RST_SET(1), 55 DEV_CLOCK_CFG_PCS_RX_RST, 56 lan966x, DEV_CLOCK_CFG(port->chip_port)); 57 58 /* 2: Disable MAC frame reception */ 59 lan_rmw(DEV_MAC_ENA_CFG_RX_ENA_SET(0), 60 DEV_MAC_ENA_CFG_RX_ENA, 61 lan966x, DEV_MAC_ENA_CFG(port->chip_port)); 62 63 /* 3: Disable traffic being sent to or from switch port */ 64 lan_rmw(QSYS_SW_PORT_MODE_PORT_ENA_SET(0), 65 QSYS_SW_PORT_MODE_PORT_ENA, 66 lan966x, QSYS_SW_PORT_MODE(port->chip_port)); 67 68 /* 4: Disable dequeuing from the egress queues */ 69 lan_rmw(QSYS_PORT_MODE_DEQUEUE_DIS_SET(1), 70 QSYS_PORT_MODE_DEQUEUE_DIS, 71 lan966x, QSYS_PORT_MODE(port->chip_port)); 72 73 /* 5: Disable Flowcontrol */ 74 lan_rmw(SYS_PAUSE_CFG_PAUSE_ENA_SET(0), 75 SYS_PAUSE_CFG_PAUSE_ENA, 76 lan966x, SYS_PAUSE_CFG(port->chip_port)); 77 78 /* 5.1: Disable PFC */ 79 lan_rmw(QSYS_SW_PORT_MODE_TX_PFC_ENA_SET(0), 80 QSYS_SW_PORT_MODE_TX_PFC_ENA, 81 lan966x, QSYS_SW_PORT_MODE(port->chip_port)); 82 83 /* 6: Wait a worst case time 8ms (jumbo/10Mbit) */ 84 usleep_range(8 * USEC_PER_MSEC, 9 * USEC_PER_MSEC); 85 86 /* 7: Disable HDX backpressure */ 87 lan_rmw(SYS_FRONT_PORT_MODE_HDX_MODE_SET(0), 88 SYS_FRONT_PORT_MODE_HDX_MODE, 89 lan966x, SYS_FRONT_PORT_MODE(port->chip_port)); 90 91 /* 8: Flush the queues accociated with the port */ 92 lan_rmw(QSYS_SW_PORT_MODE_AGING_MODE_SET(3), 93 QSYS_SW_PORT_MODE_AGING_MODE, 94 lan966x, QSYS_SW_PORT_MODE(port->chip_port)); 95 96 /* 9: Enable dequeuing from the egress queues */ 97 lan_rmw(QSYS_PORT_MODE_DEQUEUE_DIS_SET(0), 98 QSYS_PORT_MODE_DEQUEUE_DIS, 99 lan966x, QSYS_PORT_MODE(port->chip_port)); 100 101 /* 10: Wait until flushing is complete */ 102 while (true) { 103 val = lan_rd(lan966x, QSYS_SW_STATUS(port->chip_port)); 104 if (!QSYS_SW_STATUS_EQ_AVAIL_GET(val)) 105 break; 106 107 usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC); 108 delay++; 109 if (delay == 2000) { 110 pr_err("Flush timeout chip port %u", port->chip_port); 111 break; 112 } 113 } 114 115 /* 11: Reset the Port and MAC clock domains */ 116 lan_rmw(DEV_MAC_ENA_CFG_TX_ENA_SET(0), 117 DEV_MAC_ENA_CFG_TX_ENA, 118 lan966x, DEV_MAC_ENA_CFG(port->chip_port)); 119 120 lan_rmw(DEV_CLOCK_CFG_PORT_RST_SET(1), 121 DEV_CLOCK_CFG_PORT_RST, 122 lan966x, DEV_CLOCK_CFG(port->chip_port)); 123 124 usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC); 125 126 lan_rmw(DEV_CLOCK_CFG_MAC_TX_RST_SET(1) | 127 DEV_CLOCK_CFG_MAC_RX_RST_SET(1) | 128 DEV_CLOCK_CFG_PORT_RST_SET(1), 129 DEV_CLOCK_CFG_MAC_TX_RST | 130 DEV_CLOCK_CFG_MAC_RX_RST | 131 DEV_CLOCK_CFG_PORT_RST, 132 lan966x, DEV_CLOCK_CFG(port->chip_port)); 133 134 /* 12: Clear flushing */ 135 lan_rmw(QSYS_SW_PORT_MODE_AGING_MODE_SET(2), 136 QSYS_SW_PORT_MODE_AGING_MODE, 137 lan966x, QSYS_SW_PORT_MODE(port->chip_port)); 138 139 /* The port is disabled and flushed, now set up the port in the 140 * new operating mode 141 */ 142 } 143 144 static void lan966x_port_link_up(struct lan966x_port *port) 145 { 146 struct lan966x_port_config *config = &port->config; 147 struct lan966x *lan966x = port->lan966x; 148 int speed = 0, mode = 0; 149 int atop_wm = 0; 150 151 switch (config->speed) { 152 case SPEED_10: 153 speed = LAN966X_SPEED_10; 154 break; 155 case SPEED_100: 156 speed = LAN966X_SPEED_100; 157 break; 158 case SPEED_1000: 159 speed = LAN966X_SPEED_1000; 160 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA_SET(1); 161 break; 162 case SPEED_2500: 163 speed = LAN966X_SPEED_2500; 164 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA_SET(1); 165 break; 166 } 167 168 lan966x_taprio_speed_set(port, config->speed); 169 170 /* Also the GIGA_MODE_ENA(1) needs to be set regardless of the 171 * port speed for QSGMII ports. 172 */ 173 if (phy_interface_num_ports(config->portmode) == 4) 174 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA_SET(1); 175 176 lan_wr(config->duplex | mode, 177 lan966x, DEV_MAC_MODE_CFG(port->chip_port)); 178 179 lan_rmw(DEV_MAC_IFG_CFG_TX_IFG_SET(config->duplex ? 6 : 5) | 180 DEV_MAC_IFG_CFG_RX_IFG1_SET(config->speed == SPEED_10 ? 2 : 1) | 181 DEV_MAC_IFG_CFG_RX_IFG2_SET(2), 182 DEV_MAC_IFG_CFG_TX_IFG | 183 DEV_MAC_IFG_CFG_RX_IFG1 | 184 DEV_MAC_IFG_CFG_RX_IFG2, 185 lan966x, DEV_MAC_IFG_CFG(port->chip_port)); 186 187 lan_rmw(DEV_MAC_HDX_CFG_SEED_SET(4) | 188 DEV_MAC_HDX_CFG_SEED_LOAD_SET(1), 189 DEV_MAC_HDX_CFG_SEED | 190 DEV_MAC_HDX_CFG_SEED_LOAD, 191 lan966x, DEV_MAC_HDX_CFG(port->chip_port)); 192 193 if (config->portmode == PHY_INTERFACE_MODE_GMII) { 194 if (config->speed == SPEED_1000) 195 lan_rmw(CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA_SET(1), 196 CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA, 197 lan966x, 198 CHIP_TOP_CUPHY_PORT_CFG(port->chip_port)); 199 else 200 lan_rmw(CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA_SET(0), 201 CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA, 202 lan966x, 203 CHIP_TOP_CUPHY_PORT_CFG(port->chip_port)); 204 } 205 206 /* No PFC */ 207 lan_wr(ANA_PFC_CFG_FC_LINK_SPEED_SET(speed), 208 lan966x, ANA_PFC_CFG(port->chip_port)); 209 210 lan_rmw(DEV_PCS1G_CFG_PCS_ENA_SET(1), 211 DEV_PCS1G_CFG_PCS_ENA, 212 lan966x, DEV_PCS1G_CFG(port->chip_port)); 213 214 lan_rmw(DEV_PCS1G_SD_CFG_SD_ENA_SET(0), 215 DEV_PCS1G_SD_CFG_SD_ENA, 216 lan966x, DEV_PCS1G_SD_CFG(port->chip_port)); 217 218 /* Set Pause WM hysteresis, start/stop are in 1518 byte units */ 219 lan_wr(SYS_PAUSE_CFG_PAUSE_ENA_SET(1) | 220 SYS_PAUSE_CFG_PAUSE_STOP_SET(lan966x_wm_enc(4 * 1518)) | 221 SYS_PAUSE_CFG_PAUSE_START_SET(lan966x_wm_enc(6 * 1518)), 222 lan966x, SYS_PAUSE_CFG(port->chip_port)); 223 224 /* Set SMAC of Pause frame (00:00:00:00:00:00) */ 225 lan_wr(0, lan966x, DEV_FC_MAC_LOW_CFG(port->chip_port)); 226 lan_wr(0, lan966x, DEV_FC_MAC_HIGH_CFG(port->chip_port)); 227 228 /* Flow control */ 229 lan_rmw(SYS_MAC_FC_CFG_FC_LINK_SPEED_SET(speed) | 230 SYS_MAC_FC_CFG_FC_LATENCY_CFG_SET(7) | 231 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA_SET(1) | 232 SYS_MAC_FC_CFG_PAUSE_VAL_CFG_SET(0xffff) | 233 SYS_MAC_FC_CFG_RX_FC_ENA_SET(config->pause & MLO_PAUSE_RX ? 1 : 0) | 234 SYS_MAC_FC_CFG_TX_FC_ENA_SET(config->pause & MLO_PAUSE_TX ? 1 : 0), 235 SYS_MAC_FC_CFG_FC_LINK_SPEED | 236 SYS_MAC_FC_CFG_FC_LATENCY_CFG | 237 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA | 238 SYS_MAC_FC_CFG_PAUSE_VAL_CFG | 239 SYS_MAC_FC_CFG_RX_FC_ENA | 240 SYS_MAC_FC_CFG_TX_FC_ENA, 241 lan966x, SYS_MAC_FC_CFG(port->chip_port)); 242 243 /* Tail dropping watermark */ 244 atop_wm = lan966x->shared_queue_sz; 245 246 /* The total memory size is diveded by number of front ports plus CPU 247 * port 248 */ 249 lan_wr(lan966x_wm_enc(atop_wm / lan966x->num_phys_ports + 1), lan966x, 250 SYS_ATOP(port->chip_port)); 251 lan_wr(lan966x_wm_enc(atop_wm), lan966x, SYS_ATOP_TOT_CFG); 252 253 /* This needs to be at the end */ 254 /* Enable MAC module */ 255 lan_wr(DEV_MAC_ENA_CFG_RX_ENA_SET(1) | 256 DEV_MAC_ENA_CFG_TX_ENA_SET(1), 257 lan966x, DEV_MAC_ENA_CFG(port->chip_port)); 258 259 /* Take out the clock from reset */ 260 lan_wr(DEV_CLOCK_CFG_LINK_SPEED_SET(speed), 261 lan966x, DEV_CLOCK_CFG(port->chip_port)); 262 263 /* Core: Enable port for frame transfer */ 264 lan_wr(QSYS_SW_PORT_MODE_PORT_ENA_SET(1) | 265 QSYS_SW_PORT_MODE_SCH_NEXT_CFG_SET(1) | 266 QSYS_SW_PORT_MODE_INGRESS_DROP_MODE_SET(1), 267 lan966x, QSYS_SW_PORT_MODE(port->chip_port)); 268 269 lan_rmw(AFI_PORT_CFG_FC_SKIP_TTI_INJ_SET(0) | 270 AFI_PORT_CFG_FRM_OUT_MAX_SET(16), 271 AFI_PORT_CFG_FC_SKIP_TTI_INJ | 272 AFI_PORT_CFG_FRM_OUT_MAX, 273 lan966x, AFI_PORT_CFG(port->chip_port)); 274 } 275 276 void lan966x_port_config_down(struct lan966x_port *port) 277 { 278 lan966x_port_link_down(port); 279 } 280 281 void lan966x_port_config_up(struct lan966x_port *port) 282 { 283 lan966x_port_link_up(port); 284 } 285 286 void lan966x_port_status_get(struct lan966x_port *port, 287 struct phylink_link_state *state) 288 { 289 struct lan966x *lan966x = port->lan966x; 290 bool link_down; 291 u16 bmsr = 0; 292 u16 lp_adv; 293 u32 val; 294 295 val = lan_rd(lan966x, DEV_PCS1G_STICKY(port->chip_port)); 296 link_down = DEV_PCS1G_STICKY_LINK_DOWN_STICKY_GET(val); 297 if (link_down) 298 lan_wr(val, lan966x, DEV_PCS1G_STICKY(port->chip_port)); 299 300 /* Get both current Link and Sync status */ 301 val = lan_rd(lan966x, DEV_PCS1G_LINK_STATUS(port->chip_port)); 302 state->link = DEV_PCS1G_LINK_STATUS_LINK_STATUS_GET(val) && 303 DEV_PCS1G_LINK_STATUS_SYNC_STATUS_GET(val); 304 state->link &= !link_down; 305 306 /* Get PCS ANEG status register */ 307 val = lan_rd(lan966x, DEV_PCS1G_ANEG_STATUS(port->chip_port)); 308 /* Aneg complete provides more information */ 309 if (DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE_GET(val)) { 310 state->an_complete = true; 311 312 bmsr |= state->link ? BMSR_LSTATUS : 0; 313 bmsr |= BMSR_ANEGCOMPLETE; 314 315 lp_adv = DEV_PCS1G_ANEG_STATUS_LP_ADV_GET(val); 316 phylink_mii_c22_pcs_decode_state(state, bmsr, lp_adv); 317 } else { 318 if (!state->link) 319 return; 320 321 if (state->interface == PHY_INTERFACE_MODE_1000BASEX) 322 state->speed = SPEED_1000; 323 else if (state->interface == PHY_INTERFACE_MODE_2500BASEX) 324 state->speed = SPEED_2500; 325 326 state->duplex = DUPLEX_FULL; 327 } 328 } 329 330 int lan966x_port_pcs_set(struct lan966x_port *port, 331 struct lan966x_port_config *config) 332 { 333 struct lan966x *lan966x = port->lan966x; 334 bool inband_aneg = false; 335 bool outband; 336 bool full_preamble = false; 337 338 if (config->portmode == PHY_INTERFACE_MODE_QUSGMII) 339 full_preamble = true; 340 341 if (config->inband) { 342 if (config->portmode == PHY_INTERFACE_MODE_SGMII || 343 phy_interface_num_ports(config->portmode) == 4) 344 inband_aneg = true; /* Cisco-SGMII in-band-aneg */ 345 else if (config->portmode == PHY_INTERFACE_MODE_1000BASEX && 346 config->autoneg) 347 inband_aneg = true; /* Clause-37 in-band-aneg */ 348 349 outband = false; 350 } else { 351 outband = true; 352 } 353 354 /* Disable or enable inband. 355 * For QUSGMII, we rely on the preamble to transmit data such as 356 * timestamps, therefore force full preamble transmission, and prevent 357 * premable shortening 358 */ 359 lan_rmw(DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(outband) | 360 DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_SET(full_preamble), 361 DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA | 362 DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, 363 lan966x, DEV_PCS1G_MODE_CFG(port->chip_port)); 364 365 /* Enable PCS */ 366 lan_wr(DEV_PCS1G_CFG_PCS_ENA_SET(1), 367 lan966x, DEV_PCS1G_CFG(port->chip_port)); 368 369 if (inband_aneg) { 370 int adv = phylink_mii_c22_pcs_encode_advertisement(config->portmode, 371 config->advertising); 372 if (adv >= 0) 373 /* Enable in-band aneg */ 374 lan_wr(DEV_PCS1G_ANEG_CFG_ADV_ABILITY_SET(adv) | 375 DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_SET(1) | 376 DEV_PCS1G_ANEG_CFG_ENA_SET(1) | 377 DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT_SET(1), 378 lan966x, DEV_PCS1G_ANEG_CFG(port->chip_port)); 379 } else { 380 lan_wr(0, lan966x, DEV_PCS1G_ANEG_CFG(port->chip_port)); 381 } 382 383 /* Take PCS out of reset */ 384 lan_rmw(DEV_CLOCK_CFG_LINK_SPEED_SET(LAN966X_SPEED_1000) | 385 DEV_CLOCK_CFG_PCS_RX_RST_SET(0) | 386 DEV_CLOCK_CFG_PCS_TX_RST_SET(0), 387 DEV_CLOCK_CFG_LINK_SPEED | 388 DEV_CLOCK_CFG_PCS_RX_RST | 389 DEV_CLOCK_CFG_PCS_TX_RST, 390 lan966x, DEV_CLOCK_CFG(port->chip_port)); 391 392 port->config = *config; 393 394 return 0; 395 } 396 397 static void lan966x_port_qos_pcp_set(struct lan966x_port *port, 398 struct lan966x_port_qos_pcp *qos) 399 { 400 u8 *pcp_itr = qos->map; 401 u8 pcp, dp; 402 403 lan_rmw(ANA_QOS_CFG_QOS_PCP_ENA_SET(qos->enable), 404 ANA_QOS_CFG_QOS_PCP_ENA, 405 port->lan966x, ANA_QOS_CFG(port->chip_port)); 406 407 /* Map PCP and DEI to priority */ 408 for (int i = 0; i < ARRAY_SIZE(qos->map); i++) { 409 pcp = *(pcp_itr + i); 410 dp = (i < LAN966X_PORT_QOS_PCP_COUNT) ? 0 : 1; 411 412 lan_rmw(ANA_PCP_DEI_CFG_QOS_PCP_DEI_VAL_SET(pcp) | 413 ANA_PCP_DEI_CFG_DP_PCP_DEI_VAL_SET(dp), 414 ANA_PCP_DEI_CFG_QOS_PCP_DEI_VAL | 415 ANA_PCP_DEI_CFG_DP_PCP_DEI_VAL, 416 port->lan966x, 417 ANA_PCP_DEI_CFG(port->chip_port, i)); 418 } 419 } 420 421 static void lan966x_port_qos_dscp_set(struct lan966x_port *port, 422 struct lan966x_port_qos_dscp *qos) 423 { 424 struct lan966x *lan966x = port->lan966x; 425 426 /* Enable/disable dscp for qos classification. */ 427 lan_rmw(ANA_QOS_CFG_QOS_DSCP_ENA_SET(qos->enable), 428 ANA_QOS_CFG_QOS_DSCP_ENA, 429 lan966x, ANA_QOS_CFG(port->chip_port)); 430 431 /* Map each dscp value to priority and dp */ 432 for (int i = 0; i < ARRAY_SIZE(qos->map); i++) 433 lan_rmw(ANA_DSCP_CFG_DP_DSCP_VAL_SET(0) | 434 ANA_DSCP_CFG_QOS_DSCP_VAL_SET(*(qos->map + i)), 435 ANA_DSCP_CFG_DP_DSCP_VAL | 436 ANA_DSCP_CFG_QOS_DSCP_VAL, 437 lan966x, ANA_DSCP_CFG(i)); 438 439 /* Set per-dscp trust */ 440 for (int i = 0; i < ARRAY_SIZE(qos->map); i++) 441 lan_rmw(ANA_DSCP_CFG_DSCP_TRUST_ENA_SET(qos->enable), 442 ANA_DSCP_CFG_DSCP_TRUST_ENA, 443 lan966x, ANA_DSCP_CFG(i)); 444 } 445 446 static int lan966x_port_qos_default_set(struct lan966x_port *port, 447 struct lan966x_port_qos *qos) 448 { 449 /* Set default prio and dp level */ 450 lan_rmw(ANA_QOS_CFG_DP_DEFAULT_VAL_SET(0) | 451 ANA_QOS_CFG_QOS_DEFAULT_VAL_SET(qos->default_prio), 452 ANA_QOS_CFG_DP_DEFAULT_VAL | 453 ANA_QOS_CFG_QOS_DEFAULT_VAL, 454 port->lan966x, ANA_QOS_CFG(port->chip_port)); 455 456 /* Set default pcp and dei for untagged frames */ 457 lan_rmw(ANA_VLAN_CFG_VLAN_DEI_SET(0) | 458 ANA_VLAN_CFG_VLAN_PCP_SET(0), 459 ANA_VLAN_CFG_VLAN_DEI | 460 ANA_VLAN_CFG_VLAN_PCP, 461 port->lan966x, ANA_VLAN_CFG(port->chip_port)); 462 463 return 0; 464 } 465 466 static void lan966x_port_qos_pcp_rewr_set(struct lan966x_port *port, 467 struct lan966x_port_qos_pcp_rewr *qos) 468 { 469 u8 mode = LAN966X_PORT_REW_TAG_CTRL_CLASSIFIED; 470 u8 pcp, dei; 471 472 if (qos->enable) 473 mode = LAN966X_PORT_REW_TAG_CTRL_MAPPED; 474 475 /* Map the values only if it is enabled otherwise will be the classified 476 * value 477 */ 478 lan_rmw(REW_TAG_CFG_TAG_PCP_CFG_SET(mode) | 479 REW_TAG_CFG_TAG_DEI_CFG_SET(mode), 480 REW_TAG_CFG_TAG_PCP_CFG | 481 REW_TAG_CFG_TAG_DEI_CFG, 482 port->lan966x, REW_TAG_CFG(port->chip_port)); 483 484 /* Map each value to pcp and dei */ 485 for (int i = 0; i < ARRAY_SIZE(qos->map); i++) { 486 pcp = qos->map[i]; 487 if (pcp > LAN966X_PORT_QOS_PCP_COUNT) 488 dei = 1; 489 else 490 dei = 0; 491 492 lan_rmw(REW_PCP_DEI_CFG_DEI_QOS_VAL_SET(dei) | 493 REW_PCP_DEI_CFG_PCP_QOS_VAL_SET(pcp), 494 REW_PCP_DEI_CFG_DEI_QOS_VAL | 495 REW_PCP_DEI_CFG_PCP_QOS_VAL, 496 port->lan966x, 497 REW_PCP_DEI_CFG(port->chip_port, 498 i + dei * LAN966X_PORT_QOS_PCP_COUNT)); 499 } 500 } 501 502 static void lan966x_port_qos_dscp_rewr_set(struct lan966x_port *port, 503 struct lan966x_port_qos_dscp_rewr *qos) 504 { 505 u16 dscp; 506 u8 mode; 507 508 if (qos->enable) 509 mode = LAN966X_PORT_REW_DSCP_ANALIZER; 510 else 511 mode = LAN966X_PORT_REW_DSCP_FRAME; 512 513 /* Enable the rewrite otherwise will use the values from the frame */ 514 lan_rmw(REW_DSCP_CFG_DSCP_REWR_CFG_SET(mode), 515 REW_DSCP_CFG_DSCP_REWR_CFG, 516 port->lan966x, REW_DSCP_CFG(port->chip_port)); 517 518 /* Map each classified Qos class and DP to classified DSCP value */ 519 for (int i = 0; i < ARRAY_SIZE(qos->map); i++) { 520 dscp = qos->map[i]; 521 522 lan_rmw(ANA_DSCP_REWR_CFG_DSCP_QOS_REWR_VAL_SET(dscp), 523 ANA_DSCP_REWR_CFG_DSCP_QOS_REWR_VAL, 524 port->lan966x, ANA_DSCP_REWR_CFG(i)); 525 } 526 } 527 528 void lan966x_port_qos_dscp_rewr_mode_set(struct lan966x_port *port, 529 int mode) 530 { 531 lan_rmw(ANA_QOS_CFG_DSCP_REWR_CFG_SET(mode), 532 ANA_QOS_CFG_DSCP_REWR_CFG, 533 port->lan966x, ANA_QOS_CFG(port->chip_port)); 534 } 535 536 void lan966x_port_qos_set(struct lan966x_port *port, 537 struct lan966x_port_qos *qos) 538 { 539 lan966x_port_qos_pcp_set(port, &qos->pcp); 540 lan966x_port_qos_dscp_set(port, &qos->dscp); 541 lan966x_port_qos_default_set(port, qos); 542 lan966x_port_qos_pcp_rewr_set(port, &qos->pcp_rewr); 543 lan966x_port_qos_dscp_rewr_set(port, &qos->dscp_rewr); 544 } 545 546 void lan966x_port_init(struct lan966x_port *port) 547 { 548 struct lan966x_port_config *config = &port->config; 549 struct lan966x *lan966x = port->lan966x; 550 551 lan_rmw(ANA_PORT_CFG_LEARN_ENA_SET(0), 552 ANA_PORT_CFG_LEARN_ENA, 553 lan966x, ANA_PORT_CFG(port->chip_port)); 554 555 lan966x_port_config_down(port); 556 557 if (lan966x->fdma) 558 lan966x_fdma_netdev_init(lan966x, port->dev); 559 560 if (phy_interface_num_ports(config->portmode) != 4) 561 return; 562 563 lan_rmw(DEV_CLOCK_CFG_PCS_RX_RST_SET(0) | 564 DEV_CLOCK_CFG_PCS_TX_RST_SET(0) | 565 DEV_CLOCK_CFG_LINK_SPEED_SET(LAN966X_SPEED_1000), 566 DEV_CLOCK_CFG_PCS_RX_RST | 567 DEV_CLOCK_CFG_PCS_TX_RST | 568 DEV_CLOCK_CFG_LINK_SPEED, 569 lan966x, DEV_CLOCK_CFG(port->chip_port)); 570 } 571