1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/types.h> 7 #include <linux/pci.h> 8 #include <linux/netdevice.h> 9 #include <linux/etherdevice.h> 10 #include <linux/ethtool.h> 11 #include <linux/slab.h> 12 #include <linux/device.h> 13 #include <linux/skbuff.h> 14 #include <linux/if_vlan.h> 15 #include <linux/if_bridge.h> 16 #include <linux/workqueue.h> 17 #include <linux/jiffies.h> 18 #include <linux/bitops.h> 19 #include <linux/list.h> 20 #include <linux/notifier.h> 21 #include <linux/dcbnl.h> 22 #include <linux/inetdevice.h> 23 #include <linux/netlink.h> 24 #include <linux/random.h> 25 #include <net/switchdev.h> 26 #include <net/pkt_cls.h> 27 #include <net/tc_act/tc_mirred.h> 28 #include <net/netevent.h> 29 #include <net/tc_act/tc_sample.h> 30 #include <net/addrconf.h> 31 32 #include "spectrum.h" 33 #include "pci.h" 34 #include "core.h" 35 #include "reg.h" 36 #include "port.h" 37 #include "trap.h" 38 #include "txheader.h" 39 #include "spectrum_cnt.h" 40 #include "spectrum_dpipe.h" 41 #include "spectrum_acl_flex_actions.h" 42 #include "spectrum_span.h" 43 #include "../mlxfw/mlxfw.h" 44 45 #define MLXSW_SP_FWREV_MINOR_TO_BRANCH(minor) ((minor) / 100) 46 47 #define MLXSW_SP1_FWREV_MAJOR 13 48 #define MLXSW_SP1_FWREV_MINOR 1703 49 #define MLXSW_SP1_FWREV_SUBMINOR 4 50 #define MLXSW_SP1_FWREV_CAN_RESET_MINOR 1702 51 52 static const struct mlxsw_fw_rev mlxsw_sp1_fw_rev = { 53 .major = MLXSW_SP1_FWREV_MAJOR, 54 .minor = MLXSW_SP1_FWREV_MINOR, 55 .subminor = MLXSW_SP1_FWREV_SUBMINOR, 56 .can_reset_minor = MLXSW_SP1_FWREV_CAN_RESET_MINOR, 57 }; 58 59 #define MLXSW_SP1_FW_FILENAME \ 60 "mellanox/mlxsw_spectrum-" __stringify(MLXSW_SP1_FWREV_MAJOR) \ 61 "." __stringify(MLXSW_SP1_FWREV_MINOR) \ 62 "." __stringify(MLXSW_SP1_FWREV_SUBMINOR) ".mfa2" 63 64 static const char mlxsw_sp1_driver_name[] = "mlxsw_spectrum"; 65 static const char mlxsw_sp2_driver_name[] = "mlxsw_spectrum2"; 66 static const char mlxsw_sp_driver_version[] = "1.0"; 67 68 /* tx_hdr_version 69 * Tx header version. 70 * Must be set to 1. 71 */ 72 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4); 73 74 /* tx_hdr_ctl 75 * Packet control type. 76 * 0 - Ethernet control (e.g. EMADs, LACP) 77 * 1 - Ethernet data 78 */ 79 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2); 80 81 /* tx_hdr_proto 82 * Packet protocol type. Must be set to 1 (Ethernet). 83 */ 84 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3); 85 86 /* tx_hdr_rx_is_router 87 * Packet is sent from the router. Valid for data packets only. 88 */ 89 MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1); 90 91 /* tx_hdr_fid_valid 92 * Indicates if the 'fid' field is valid and should be used for 93 * forwarding lookup. Valid for data packets only. 94 */ 95 MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1); 96 97 /* tx_hdr_swid 98 * Switch partition ID. Must be set to 0. 99 */ 100 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3); 101 102 /* tx_hdr_control_tclass 103 * Indicates if the packet should use the control TClass and not one 104 * of the data TClasses. 105 */ 106 MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1); 107 108 /* tx_hdr_etclass 109 * Egress TClass to be used on the egress device on the egress port. 110 */ 111 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4); 112 113 /* tx_hdr_port_mid 114 * Destination local port for unicast packets. 115 * Destination multicast ID for multicast packets. 116 * 117 * Control packets are directed to a specific egress port, while data 118 * packets are transmitted through the CPU port (0) into the switch partition, 119 * where forwarding rules are applied. 120 */ 121 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16); 122 123 /* tx_hdr_fid 124 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is 125 * set, otherwise calculated based on the packet's VID using VID to FID mapping. 126 * Valid for data packets only. 127 */ 128 MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16); 129 130 /* tx_hdr_type 131 * 0 - Data packets 132 * 6 - Control packets 133 */ 134 MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4); 135 136 struct mlxsw_sp_mlxfw_dev { 137 struct mlxfw_dev mlxfw_dev; 138 struct mlxsw_sp *mlxsw_sp; 139 }; 140 141 static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev, 142 u16 component_index, u32 *p_max_size, 143 u8 *p_align_bits, u16 *p_max_write_size) 144 { 145 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 146 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 147 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 148 char mcqi_pl[MLXSW_REG_MCQI_LEN]; 149 int err; 150 151 mlxsw_reg_mcqi_pack(mcqi_pl, component_index); 152 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl); 153 if (err) 154 return err; 155 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits, 156 p_max_write_size); 157 158 *p_align_bits = max_t(u8, *p_align_bits, 2); 159 *p_max_write_size = min_t(u16, *p_max_write_size, 160 MLXSW_REG_MCDA_MAX_DATA_LEN); 161 return 0; 162 } 163 164 static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle) 165 { 166 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 167 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 168 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 169 char mcc_pl[MLXSW_REG_MCC_LEN]; 170 u8 control_state; 171 int err; 172 173 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0); 174 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 175 if (err) 176 return err; 177 178 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state); 179 if (control_state != MLXFW_FSM_STATE_IDLE) 180 return -EBUSY; 181 182 mlxsw_reg_mcc_pack(mcc_pl, 183 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE, 184 0, *fwhandle, 0); 185 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 186 } 187 188 static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev, 189 u32 fwhandle, u16 component_index, 190 u32 component_size) 191 { 192 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 193 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 194 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 195 char mcc_pl[MLXSW_REG_MCC_LEN]; 196 197 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT, 198 component_index, fwhandle, component_size); 199 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 200 } 201 202 static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev, 203 u32 fwhandle, u8 *data, u16 size, 204 u32 offset) 205 { 206 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 207 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 208 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 209 char mcda_pl[MLXSW_REG_MCDA_LEN]; 210 211 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data); 212 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl); 213 } 214 215 static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev, 216 u32 fwhandle, u16 component_index) 217 { 218 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 219 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 220 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 221 char mcc_pl[MLXSW_REG_MCC_LEN]; 222 223 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT, 224 component_index, fwhandle, 0); 225 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 226 } 227 228 static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 229 { 230 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 231 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 232 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 233 char mcc_pl[MLXSW_REG_MCC_LEN]; 234 235 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0, 236 fwhandle, 0); 237 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 238 } 239 240 static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 241 enum mlxfw_fsm_state *fsm_state, 242 enum mlxfw_fsm_state_err *fsm_state_err) 243 { 244 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 245 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 246 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 247 char mcc_pl[MLXSW_REG_MCC_LEN]; 248 u8 control_state; 249 u8 error_code; 250 int err; 251 252 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0); 253 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 254 if (err) 255 return err; 256 257 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state); 258 *fsm_state = control_state; 259 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code, 260 MLXFW_FSM_STATE_ERR_MAX); 261 return 0; 262 } 263 264 static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 265 { 266 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 267 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 268 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 269 char mcc_pl[MLXSW_REG_MCC_LEN]; 270 271 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0, 272 fwhandle, 0); 273 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 274 } 275 276 static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 277 { 278 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 279 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 280 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 281 char mcc_pl[MLXSW_REG_MCC_LEN]; 282 283 mlxsw_reg_mcc_pack(mcc_pl, 284 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0, 285 fwhandle, 0); 286 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 287 } 288 289 static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = { 290 .component_query = mlxsw_sp_component_query, 291 .fsm_lock = mlxsw_sp_fsm_lock, 292 .fsm_component_update = mlxsw_sp_fsm_component_update, 293 .fsm_block_download = mlxsw_sp_fsm_block_download, 294 .fsm_component_verify = mlxsw_sp_fsm_component_verify, 295 .fsm_activate = mlxsw_sp_fsm_activate, 296 .fsm_query_state = mlxsw_sp_fsm_query_state, 297 .fsm_cancel = mlxsw_sp_fsm_cancel, 298 .fsm_release = mlxsw_sp_fsm_release 299 }; 300 301 static int mlxsw_sp_firmware_flash(struct mlxsw_sp *mlxsw_sp, 302 const struct firmware *firmware) 303 { 304 struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = { 305 .mlxfw_dev = { 306 .ops = &mlxsw_sp_mlxfw_dev_ops, 307 .psid = mlxsw_sp->bus_info->psid, 308 .psid_size = strlen(mlxsw_sp->bus_info->psid), 309 }, 310 .mlxsw_sp = mlxsw_sp 311 }; 312 313 return mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev, firmware); 314 } 315 316 static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp) 317 { 318 const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev; 319 const struct mlxsw_fw_rev *req_rev = mlxsw_sp->req_rev; 320 const char *fw_filename = mlxsw_sp->fw_filename; 321 const struct firmware *firmware; 322 int err; 323 324 /* Don't check if driver does not require it */ 325 if (!req_rev || !fw_filename) 326 return 0; 327 328 /* Validate driver & FW are compatible */ 329 if (rev->major != req_rev->major) { 330 WARN(1, "Mismatch in major FW version [%d:%d] is never expected; Please contact support\n", 331 rev->major, req_rev->major); 332 return -EINVAL; 333 } 334 if (MLXSW_SP_FWREV_MINOR_TO_BRANCH(rev->minor) == 335 MLXSW_SP_FWREV_MINOR_TO_BRANCH(req_rev->minor) && 336 (rev->minor > req_rev->minor || 337 (rev->minor == req_rev->minor && 338 rev->subminor >= req_rev->subminor))) 339 return 0; 340 341 dev_info(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d is incompatible with the driver\n", 342 rev->major, rev->minor, rev->subminor); 343 dev_info(mlxsw_sp->bus_info->dev, "Flashing firmware using file %s\n", 344 fw_filename); 345 346 err = request_firmware_direct(&firmware, fw_filename, 347 mlxsw_sp->bus_info->dev); 348 if (err) { 349 dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n", 350 fw_filename); 351 return err; 352 } 353 354 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware); 355 release_firmware(firmware); 356 if (err) 357 dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n"); 358 359 /* On FW flash success, tell the caller FW reset is needed 360 * if current FW supports it. 361 */ 362 if (rev->minor >= req_rev->can_reset_minor) 363 return err ? err : -EAGAIN; 364 else 365 return 0; 366 } 367 368 int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp, 369 unsigned int counter_index, u64 *packets, 370 u64 *bytes) 371 { 372 char mgpc_pl[MLXSW_REG_MGPC_LEN]; 373 int err; 374 375 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP, 376 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 377 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl); 378 if (err) 379 return err; 380 if (packets) 381 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl); 382 if (bytes) 383 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl); 384 return 0; 385 } 386 387 static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp, 388 unsigned int counter_index) 389 { 390 char mgpc_pl[MLXSW_REG_MGPC_LEN]; 391 392 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR, 393 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 394 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl); 395 } 396 397 int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp, 398 unsigned int *p_counter_index) 399 { 400 int err; 401 402 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW, 403 p_counter_index); 404 if (err) 405 return err; 406 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index); 407 if (err) 408 goto err_counter_clear; 409 return 0; 410 411 err_counter_clear: 412 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW, 413 *p_counter_index); 414 return err; 415 } 416 417 void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp, 418 unsigned int counter_index) 419 { 420 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW, 421 counter_index); 422 } 423 424 static void mlxsw_sp_txhdr_construct(struct sk_buff *skb, 425 const struct mlxsw_tx_info *tx_info) 426 { 427 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN); 428 429 memset(txhdr, 0, MLXSW_TXHDR_LEN); 430 431 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1); 432 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL); 433 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH); 434 mlxsw_tx_hdr_swid_set(txhdr, 0); 435 mlxsw_tx_hdr_control_tclass_set(txhdr, 1); 436 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port); 437 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL); 438 } 439 440 enum mlxsw_reg_spms_state mlxsw_sp_stp_spms_state(u8 state) 441 { 442 switch (state) { 443 case BR_STATE_FORWARDING: 444 return MLXSW_REG_SPMS_STATE_FORWARDING; 445 case BR_STATE_LEARNING: 446 return MLXSW_REG_SPMS_STATE_LEARNING; 447 case BR_STATE_LISTENING: /* fall-through */ 448 case BR_STATE_DISABLED: /* fall-through */ 449 case BR_STATE_BLOCKING: 450 return MLXSW_REG_SPMS_STATE_DISCARDING; 451 default: 452 BUG(); 453 } 454 } 455 456 int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid, 457 u8 state) 458 { 459 enum mlxsw_reg_spms_state spms_state = mlxsw_sp_stp_spms_state(state); 460 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 461 char *spms_pl; 462 int err; 463 464 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL); 465 if (!spms_pl) 466 return -ENOMEM; 467 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port); 468 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state); 469 470 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl); 471 kfree(spms_pl); 472 return err; 473 } 474 475 static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp) 476 { 477 char spad_pl[MLXSW_REG_SPAD_LEN] = {0}; 478 int err; 479 480 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl); 481 if (err) 482 return err; 483 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac); 484 return 0; 485 } 486 487 static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port, 488 bool enable, u32 rate) 489 { 490 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 491 char mpsc_pl[MLXSW_REG_MPSC_LEN]; 492 493 mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate); 494 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl); 495 } 496 497 static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port, 498 bool is_up) 499 { 500 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 501 char paos_pl[MLXSW_REG_PAOS_LEN]; 502 503 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port, 504 is_up ? MLXSW_PORT_ADMIN_STATUS_UP : 505 MLXSW_PORT_ADMIN_STATUS_DOWN); 506 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl); 507 } 508 509 static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port, 510 unsigned char *addr) 511 { 512 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 513 char ppad_pl[MLXSW_REG_PPAD_LEN]; 514 515 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port); 516 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr); 517 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl); 518 } 519 520 static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port) 521 { 522 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 523 unsigned char *addr = mlxsw_sp_port->dev->dev_addr; 524 525 ether_addr_copy(addr, mlxsw_sp->base_mac); 526 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port; 527 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr); 528 } 529 530 static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu) 531 { 532 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 533 char pmtu_pl[MLXSW_REG_PMTU_LEN]; 534 int max_mtu; 535 int err; 536 537 mtu += MLXSW_TXHDR_LEN + ETH_HLEN; 538 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0); 539 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl); 540 if (err) 541 return err; 542 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl); 543 544 if (mtu > max_mtu) 545 return -EINVAL; 546 547 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu); 548 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl); 549 } 550 551 static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid) 552 { 553 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 554 char pspa_pl[MLXSW_REG_PSPA_LEN]; 555 556 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port); 557 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl); 558 } 559 560 int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable) 561 { 562 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 563 char svpe_pl[MLXSW_REG_SVPE_LEN]; 564 565 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable); 566 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl); 567 } 568 569 int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid, 570 bool learn_enable) 571 { 572 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 573 char *spvmlr_pl; 574 int err; 575 576 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL); 577 if (!spvmlr_pl) 578 return -ENOMEM; 579 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid, 580 learn_enable); 581 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl); 582 kfree(spvmlr_pl); 583 return err; 584 } 585 586 static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, 587 u16 vid) 588 { 589 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 590 char spvid_pl[MLXSW_REG_SPVID_LEN]; 591 592 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid); 593 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl); 594 } 595 596 static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port, 597 bool allow) 598 { 599 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 600 char spaft_pl[MLXSW_REG_SPAFT_LEN]; 601 602 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow); 603 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl); 604 } 605 606 int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid) 607 { 608 int err; 609 610 if (!vid) { 611 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false); 612 if (err) 613 return err; 614 } else { 615 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid); 616 if (err) 617 return err; 618 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true); 619 if (err) 620 goto err_port_allow_untagged_set; 621 } 622 623 mlxsw_sp_port->pvid = vid; 624 return 0; 625 626 err_port_allow_untagged_set: 627 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid); 628 return err; 629 } 630 631 static int 632 mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port) 633 { 634 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 635 char sspr_pl[MLXSW_REG_SSPR_LEN]; 636 637 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port); 638 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl); 639 } 640 641 static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp, 642 u8 local_port, u8 *p_module, 643 u8 *p_width, u8 *p_lane) 644 { 645 char pmlp_pl[MLXSW_REG_PMLP_LEN]; 646 int err; 647 648 mlxsw_reg_pmlp_pack(pmlp_pl, local_port); 649 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl); 650 if (err) 651 return err; 652 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0); 653 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl); 654 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0); 655 return 0; 656 } 657 658 static int mlxsw_sp_port_module_map(struct mlxsw_sp_port *mlxsw_sp_port, 659 u8 module, u8 width, u8 lane) 660 { 661 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 662 char pmlp_pl[MLXSW_REG_PMLP_LEN]; 663 int i; 664 665 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port); 666 mlxsw_reg_pmlp_width_set(pmlp_pl, width); 667 for (i = 0; i < width; i++) { 668 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module); 669 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */ 670 } 671 672 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl); 673 } 674 675 static int mlxsw_sp_port_module_unmap(struct mlxsw_sp_port *mlxsw_sp_port) 676 { 677 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 678 char pmlp_pl[MLXSW_REG_PMLP_LEN]; 679 680 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port); 681 mlxsw_reg_pmlp_width_set(pmlp_pl, 0); 682 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl); 683 } 684 685 static int mlxsw_sp_port_open(struct net_device *dev) 686 { 687 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 688 int err; 689 690 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true); 691 if (err) 692 return err; 693 netif_start_queue(dev); 694 return 0; 695 } 696 697 static int mlxsw_sp_port_stop(struct net_device *dev) 698 { 699 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 700 701 netif_stop_queue(dev); 702 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false); 703 } 704 705 static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb, 706 struct net_device *dev) 707 { 708 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 709 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 710 struct mlxsw_sp_port_pcpu_stats *pcpu_stats; 711 const struct mlxsw_tx_info tx_info = { 712 .local_port = mlxsw_sp_port->local_port, 713 .is_emad = false, 714 }; 715 u64 len; 716 int err; 717 718 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info)) 719 return NETDEV_TX_BUSY; 720 721 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) { 722 struct sk_buff *skb_orig = skb; 723 724 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN); 725 if (!skb) { 726 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped); 727 dev_kfree_skb_any(skb_orig); 728 return NETDEV_TX_OK; 729 } 730 dev_consume_skb_any(skb_orig); 731 } 732 733 if (eth_skb_pad(skb)) { 734 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped); 735 return NETDEV_TX_OK; 736 } 737 738 mlxsw_sp_txhdr_construct(skb, &tx_info); 739 /* TX header is consumed by HW on the way so we shouldn't count its 740 * bytes as being sent. 741 */ 742 len = skb->len - MLXSW_TXHDR_LEN; 743 744 /* Due to a race we might fail here because of a full queue. In that 745 * unlikely case we simply drop the packet. 746 */ 747 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info); 748 749 if (!err) { 750 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats); 751 u64_stats_update_begin(&pcpu_stats->syncp); 752 pcpu_stats->tx_packets++; 753 pcpu_stats->tx_bytes += len; 754 u64_stats_update_end(&pcpu_stats->syncp); 755 } else { 756 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped); 757 dev_kfree_skb_any(skb); 758 } 759 return NETDEV_TX_OK; 760 } 761 762 static void mlxsw_sp_set_rx_mode(struct net_device *dev) 763 { 764 } 765 766 static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p) 767 { 768 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 769 struct sockaddr *addr = p; 770 int err; 771 772 if (!is_valid_ether_addr(addr->sa_data)) 773 return -EADDRNOTAVAIL; 774 775 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data); 776 if (err) 777 return err; 778 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 779 return 0; 780 } 781 782 static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp, 783 int mtu) 784 { 785 return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu); 786 } 787 788 #define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */ 789 790 static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu, 791 u16 delay) 792 { 793 delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay, 794 BITS_PER_BYTE)); 795 return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp, 796 mtu); 797 } 798 799 /* Maximum delay buffer needed in case of PAUSE frames, in bytes. 800 * Assumes 100m cable and maximum MTU. 801 */ 802 #define MLXSW_SP_PAUSE_DELAY 58752 803 804 static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu, 805 u16 delay, bool pfc, bool pause) 806 { 807 if (pfc) 808 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay); 809 else if (pause) 810 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY); 811 else 812 return 0; 813 } 814 815 static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres, 816 bool lossy) 817 { 818 if (lossy) 819 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size); 820 else 821 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size, 822 thres); 823 } 824 825 int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu, 826 u8 *prio_tc, bool pause_en, 827 struct ieee_pfc *my_pfc) 828 { 829 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 830 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0; 831 u16 delay = !!my_pfc ? my_pfc->delay : 0; 832 char pbmc_pl[MLXSW_REG_PBMC_LEN]; 833 int i, j, err; 834 835 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0); 836 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl); 837 if (err) 838 return err; 839 840 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 841 bool configure = false; 842 bool pfc = false; 843 bool lossy; 844 u16 thres; 845 846 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) { 847 if (prio_tc[j] == i) { 848 pfc = pfc_en & BIT(j); 849 configure = true; 850 break; 851 } 852 } 853 854 if (!configure) 855 continue; 856 857 lossy = !(pfc || pause_en); 858 thres = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu); 859 delay = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay, pfc, 860 pause_en); 861 mlxsw_sp_pg_buf_pack(pbmc_pl, i, thres + delay, thres, lossy); 862 } 863 864 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl); 865 } 866 867 static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, 868 int mtu, bool pause_en) 869 { 870 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0}; 871 bool dcb_en = !!mlxsw_sp_port->dcb.ets; 872 struct ieee_pfc *my_pfc; 873 u8 *prio_tc; 874 875 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc; 876 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL; 877 878 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc, 879 pause_en, my_pfc); 880 } 881 882 static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu) 883 { 884 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 885 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port); 886 int err; 887 888 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en); 889 if (err) 890 return err; 891 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu); 892 if (err) 893 goto err_span_port_mtu_update; 894 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu); 895 if (err) 896 goto err_port_mtu_set; 897 dev->mtu = mtu; 898 return 0; 899 900 err_port_mtu_set: 901 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu); 902 err_span_port_mtu_update: 903 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en); 904 return err; 905 } 906 907 static int 908 mlxsw_sp_port_get_sw_stats64(const struct net_device *dev, 909 struct rtnl_link_stats64 *stats) 910 { 911 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 912 struct mlxsw_sp_port_pcpu_stats *p; 913 u64 rx_packets, rx_bytes, tx_packets, tx_bytes; 914 u32 tx_dropped = 0; 915 unsigned int start; 916 int i; 917 918 for_each_possible_cpu(i) { 919 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i); 920 do { 921 start = u64_stats_fetch_begin_irq(&p->syncp); 922 rx_packets = p->rx_packets; 923 rx_bytes = p->rx_bytes; 924 tx_packets = p->tx_packets; 925 tx_bytes = p->tx_bytes; 926 } while (u64_stats_fetch_retry_irq(&p->syncp, start)); 927 928 stats->rx_packets += rx_packets; 929 stats->rx_bytes += rx_bytes; 930 stats->tx_packets += tx_packets; 931 stats->tx_bytes += tx_bytes; 932 /* tx_dropped is u32, updated without syncp protection. */ 933 tx_dropped += p->tx_dropped; 934 } 935 stats->tx_dropped = tx_dropped; 936 return 0; 937 } 938 939 static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id) 940 { 941 switch (attr_id) { 942 case IFLA_OFFLOAD_XSTATS_CPU_HIT: 943 return true; 944 } 945 946 return false; 947 } 948 949 static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev, 950 void *sp) 951 { 952 switch (attr_id) { 953 case IFLA_OFFLOAD_XSTATS_CPU_HIT: 954 return mlxsw_sp_port_get_sw_stats64(dev, sp); 955 } 956 957 return -EINVAL; 958 } 959 960 static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp, 961 int prio, char *ppcnt_pl) 962 { 963 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 964 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 965 966 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio); 967 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl); 968 } 969 970 static int mlxsw_sp_port_get_hw_stats(struct net_device *dev, 971 struct rtnl_link_stats64 *stats) 972 { 973 char ppcnt_pl[MLXSW_REG_PPCNT_LEN]; 974 int err; 975 976 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 977 0, ppcnt_pl); 978 if (err) 979 goto out; 980 981 stats->tx_packets = 982 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl); 983 stats->rx_packets = 984 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl); 985 stats->tx_bytes = 986 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl); 987 stats->rx_bytes = 988 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl); 989 stats->multicast = 990 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl); 991 992 stats->rx_crc_errors = 993 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl); 994 stats->rx_frame_errors = 995 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl); 996 997 stats->rx_length_errors = ( 998 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) + 999 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) + 1000 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl)); 1001 1002 stats->rx_errors = (stats->rx_crc_errors + 1003 stats->rx_frame_errors + stats->rx_length_errors); 1004 1005 out: 1006 return err; 1007 } 1008 1009 static void 1010 mlxsw_sp_port_get_hw_xstats(struct net_device *dev, 1011 struct mlxsw_sp_port_xstats *xstats) 1012 { 1013 char ppcnt_pl[MLXSW_REG_PPCNT_LEN]; 1014 int err, i; 1015 1016 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0, 1017 ppcnt_pl); 1018 if (!err) 1019 xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl); 1020 1021 for (i = 0; i < TC_MAX_QUEUE; i++) { 1022 err = mlxsw_sp_port_get_stats_raw(dev, 1023 MLXSW_REG_PPCNT_TC_CONG_TC, 1024 i, ppcnt_pl); 1025 if (!err) 1026 xstats->wred_drop[i] = 1027 mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl); 1028 1029 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT, 1030 i, ppcnt_pl); 1031 if (err) 1032 continue; 1033 1034 xstats->backlog[i] = 1035 mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl); 1036 xstats->tail_drop[i] = 1037 mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl); 1038 } 1039 1040 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 1041 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_PRIO_CNT, 1042 i, ppcnt_pl); 1043 if (err) 1044 continue; 1045 1046 xstats->tx_packets[i] = mlxsw_reg_ppcnt_tx_frames_get(ppcnt_pl); 1047 xstats->tx_bytes[i] = mlxsw_reg_ppcnt_tx_octets_get(ppcnt_pl); 1048 } 1049 } 1050 1051 static void update_stats_cache(struct work_struct *work) 1052 { 1053 struct mlxsw_sp_port *mlxsw_sp_port = 1054 container_of(work, struct mlxsw_sp_port, 1055 periodic_hw_stats.update_dw.work); 1056 1057 if (!netif_carrier_ok(mlxsw_sp_port->dev)) 1058 goto out; 1059 1060 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev, 1061 &mlxsw_sp_port->periodic_hw_stats.stats); 1062 mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev, 1063 &mlxsw_sp_port->periodic_hw_stats.xstats); 1064 1065 out: 1066 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 1067 MLXSW_HW_STATS_UPDATE_TIME); 1068 } 1069 1070 /* Return the stats from a cache that is updated periodically, 1071 * as this function might get called in an atomic context. 1072 */ 1073 static void 1074 mlxsw_sp_port_get_stats64(struct net_device *dev, 1075 struct rtnl_link_stats64 *stats) 1076 { 1077 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1078 1079 memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats)); 1080 } 1081 1082 static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, 1083 u16 vid_begin, u16 vid_end, 1084 bool is_member, bool untagged) 1085 { 1086 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1087 char *spvm_pl; 1088 int err; 1089 1090 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL); 1091 if (!spvm_pl) 1092 return -ENOMEM; 1093 1094 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin, 1095 vid_end, is_member, untagged); 1096 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl); 1097 kfree(spvm_pl); 1098 return err; 1099 } 1100 1101 int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin, 1102 u16 vid_end, bool is_member, bool untagged) 1103 { 1104 u16 vid, vid_e; 1105 int err; 1106 1107 for (vid = vid_begin; vid <= vid_end; 1108 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) { 1109 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1), 1110 vid_end); 1111 1112 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e, 1113 is_member, untagged); 1114 if (err) 1115 return err; 1116 } 1117 1118 return 0; 1119 } 1120 1121 static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port) 1122 { 1123 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp; 1124 1125 list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp, 1126 &mlxsw_sp_port->vlans_list, list) 1127 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan); 1128 } 1129 1130 static struct mlxsw_sp_port_vlan * 1131 mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid) 1132 { 1133 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 1134 bool untagged = vid == 1; 1135 int err; 1136 1137 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged); 1138 if (err) 1139 return ERR_PTR(err); 1140 1141 mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL); 1142 if (!mlxsw_sp_port_vlan) { 1143 err = -ENOMEM; 1144 goto err_port_vlan_alloc; 1145 } 1146 1147 mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port; 1148 mlxsw_sp_port_vlan->ref_count = 1; 1149 mlxsw_sp_port_vlan->vid = vid; 1150 list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list); 1151 1152 return mlxsw_sp_port_vlan; 1153 1154 err_port_vlan_alloc: 1155 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false); 1156 return ERR_PTR(err); 1157 } 1158 1159 static void 1160 mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan) 1161 { 1162 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port; 1163 u16 vid = mlxsw_sp_port_vlan->vid; 1164 1165 list_del(&mlxsw_sp_port_vlan->list); 1166 kfree(mlxsw_sp_port_vlan); 1167 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false); 1168 } 1169 1170 struct mlxsw_sp_port_vlan * 1171 mlxsw_sp_port_vlan_get(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid) 1172 { 1173 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 1174 1175 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid); 1176 if (mlxsw_sp_port_vlan) { 1177 mlxsw_sp_port_vlan->ref_count++; 1178 return mlxsw_sp_port_vlan; 1179 } 1180 1181 return mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid); 1182 } 1183 1184 void mlxsw_sp_port_vlan_put(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan) 1185 { 1186 struct mlxsw_sp_fid *fid = mlxsw_sp_port_vlan->fid; 1187 1188 if (--mlxsw_sp_port_vlan->ref_count != 0) 1189 return; 1190 1191 if (mlxsw_sp_port_vlan->bridge_port) 1192 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan); 1193 else if (fid) 1194 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan); 1195 1196 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan); 1197 } 1198 1199 static int mlxsw_sp_port_add_vid(struct net_device *dev, 1200 __be16 __always_unused proto, u16 vid) 1201 { 1202 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1203 1204 /* VLAN 0 is added to HW filter when device goes up, but it is 1205 * reserved in our case, so simply return. 1206 */ 1207 if (!vid) 1208 return 0; 1209 1210 return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_get(mlxsw_sp_port, vid)); 1211 } 1212 1213 static int mlxsw_sp_port_kill_vid(struct net_device *dev, 1214 __be16 __always_unused proto, u16 vid) 1215 { 1216 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1217 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 1218 1219 /* VLAN 0 is removed from HW filter when device goes down, but 1220 * it is reserved in our case, so simply return. 1221 */ 1222 if (!vid) 1223 return 0; 1224 1225 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid); 1226 if (!mlxsw_sp_port_vlan) 1227 return 0; 1228 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan); 1229 1230 return 0; 1231 } 1232 1233 static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name, 1234 size_t len) 1235 { 1236 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1237 1238 return mlxsw_core_port_get_phys_port_name(mlxsw_sp_port->mlxsw_sp->core, 1239 mlxsw_sp_port->local_port, 1240 name, len); 1241 } 1242 1243 static struct mlxsw_sp_port_mall_tc_entry * 1244 mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port, 1245 unsigned long cookie) { 1246 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry; 1247 1248 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list) 1249 if (mall_tc_entry->cookie == cookie) 1250 return mall_tc_entry; 1251 1252 return NULL; 1253 } 1254 1255 static int 1256 mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port, 1257 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror, 1258 const struct tc_action *a, 1259 bool ingress) 1260 { 1261 enum mlxsw_sp_span_type span_type; 1262 struct net_device *to_dev; 1263 1264 to_dev = tcf_mirred_dev(a); 1265 if (!to_dev) { 1266 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n"); 1267 return -EINVAL; 1268 } 1269 1270 mirror->ingress = ingress; 1271 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS; 1272 return mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_dev, span_type, 1273 true, &mirror->span_id); 1274 } 1275 1276 static void 1277 mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port, 1278 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror) 1279 { 1280 enum mlxsw_sp_span_type span_type; 1281 1282 span_type = mirror->ingress ? 1283 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS; 1284 mlxsw_sp_span_mirror_del(mlxsw_sp_port, mirror->span_id, 1285 span_type, true); 1286 } 1287 1288 static int 1289 mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port, 1290 struct tc_cls_matchall_offload *cls, 1291 const struct tc_action *a, 1292 bool ingress) 1293 { 1294 int err; 1295 1296 if (!mlxsw_sp_port->sample) 1297 return -EOPNOTSUPP; 1298 if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) { 1299 netdev_err(mlxsw_sp_port->dev, "sample already active\n"); 1300 return -EEXIST; 1301 } 1302 if (tcf_sample_rate(a) > MLXSW_REG_MPSC_RATE_MAX) { 1303 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n"); 1304 return -EOPNOTSUPP; 1305 } 1306 1307 rcu_assign_pointer(mlxsw_sp_port->sample->psample_group, 1308 tcf_sample_psample_group(a)); 1309 mlxsw_sp_port->sample->truncate = tcf_sample_truncate(a); 1310 mlxsw_sp_port->sample->trunc_size = tcf_sample_trunc_size(a); 1311 mlxsw_sp_port->sample->rate = tcf_sample_rate(a); 1312 1313 err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, tcf_sample_rate(a)); 1314 if (err) 1315 goto err_port_sample_set; 1316 return 0; 1317 1318 err_port_sample_set: 1319 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL); 1320 return err; 1321 } 1322 1323 static void 1324 mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port) 1325 { 1326 if (!mlxsw_sp_port->sample) 1327 return; 1328 1329 mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1); 1330 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL); 1331 } 1332 1333 static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port, 1334 struct tc_cls_matchall_offload *f, 1335 bool ingress) 1336 { 1337 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry; 1338 __be16 protocol = f->common.protocol; 1339 const struct tc_action *a; 1340 LIST_HEAD(actions); 1341 int err; 1342 1343 if (!tcf_exts_has_one_action(f->exts)) { 1344 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n"); 1345 return -EOPNOTSUPP; 1346 } 1347 1348 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL); 1349 if (!mall_tc_entry) 1350 return -ENOMEM; 1351 mall_tc_entry->cookie = f->cookie; 1352 1353 a = tcf_exts_first_action(f->exts); 1354 1355 if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) { 1356 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror; 1357 1358 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR; 1359 mirror = &mall_tc_entry->mirror; 1360 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port, 1361 mirror, a, ingress); 1362 } else if (is_tcf_sample(a) && protocol == htons(ETH_P_ALL)) { 1363 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE; 1364 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, f, 1365 a, ingress); 1366 } else { 1367 err = -EOPNOTSUPP; 1368 } 1369 1370 if (err) 1371 goto err_add_action; 1372 1373 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list); 1374 return 0; 1375 1376 err_add_action: 1377 kfree(mall_tc_entry); 1378 return err; 1379 } 1380 1381 static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port, 1382 struct tc_cls_matchall_offload *f) 1383 { 1384 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry; 1385 1386 mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port, 1387 f->cookie); 1388 if (!mall_tc_entry) { 1389 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n"); 1390 return; 1391 } 1392 list_del(&mall_tc_entry->list); 1393 1394 switch (mall_tc_entry->type) { 1395 case MLXSW_SP_PORT_MALL_MIRROR: 1396 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port, 1397 &mall_tc_entry->mirror); 1398 break; 1399 case MLXSW_SP_PORT_MALL_SAMPLE: 1400 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port); 1401 break; 1402 default: 1403 WARN_ON(1); 1404 } 1405 1406 kfree(mall_tc_entry); 1407 } 1408 1409 static int mlxsw_sp_setup_tc_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port, 1410 struct tc_cls_matchall_offload *f, 1411 bool ingress) 1412 { 1413 switch (f->command) { 1414 case TC_CLSMATCHALL_REPLACE: 1415 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port, f, 1416 ingress); 1417 case TC_CLSMATCHALL_DESTROY: 1418 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port, f); 1419 return 0; 1420 default: 1421 return -EOPNOTSUPP; 1422 } 1423 } 1424 1425 static int 1426 mlxsw_sp_setup_tc_cls_flower(struct mlxsw_sp_acl_block *acl_block, 1427 struct tc_cls_flower_offload *f) 1428 { 1429 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_acl_block_mlxsw_sp(acl_block); 1430 1431 switch (f->command) { 1432 case TC_CLSFLOWER_REPLACE: 1433 return mlxsw_sp_flower_replace(mlxsw_sp, acl_block, f); 1434 case TC_CLSFLOWER_DESTROY: 1435 mlxsw_sp_flower_destroy(mlxsw_sp, acl_block, f); 1436 return 0; 1437 case TC_CLSFLOWER_STATS: 1438 return mlxsw_sp_flower_stats(mlxsw_sp, acl_block, f); 1439 case TC_CLSFLOWER_TMPLT_CREATE: 1440 return mlxsw_sp_flower_tmplt_create(mlxsw_sp, acl_block, f); 1441 case TC_CLSFLOWER_TMPLT_DESTROY: 1442 mlxsw_sp_flower_tmplt_destroy(mlxsw_sp, acl_block, f); 1443 return 0; 1444 default: 1445 return -EOPNOTSUPP; 1446 } 1447 } 1448 1449 static int mlxsw_sp_setup_tc_block_cb_matchall(enum tc_setup_type type, 1450 void *type_data, 1451 void *cb_priv, bool ingress) 1452 { 1453 struct mlxsw_sp_port *mlxsw_sp_port = cb_priv; 1454 1455 switch (type) { 1456 case TC_SETUP_CLSMATCHALL: 1457 if (!tc_cls_can_offload_and_chain0(mlxsw_sp_port->dev, 1458 type_data)) 1459 return -EOPNOTSUPP; 1460 1461 return mlxsw_sp_setup_tc_cls_matchall(mlxsw_sp_port, type_data, 1462 ingress); 1463 case TC_SETUP_CLSFLOWER: 1464 return 0; 1465 default: 1466 return -EOPNOTSUPP; 1467 } 1468 } 1469 1470 static int mlxsw_sp_setup_tc_block_cb_matchall_ig(enum tc_setup_type type, 1471 void *type_data, 1472 void *cb_priv) 1473 { 1474 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data, 1475 cb_priv, true); 1476 } 1477 1478 static int mlxsw_sp_setup_tc_block_cb_matchall_eg(enum tc_setup_type type, 1479 void *type_data, 1480 void *cb_priv) 1481 { 1482 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data, 1483 cb_priv, false); 1484 } 1485 1486 static int mlxsw_sp_setup_tc_block_cb_flower(enum tc_setup_type type, 1487 void *type_data, void *cb_priv) 1488 { 1489 struct mlxsw_sp_acl_block *acl_block = cb_priv; 1490 1491 switch (type) { 1492 case TC_SETUP_CLSMATCHALL: 1493 return 0; 1494 case TC_SETUP_CLSFLOWER: 1495 if (mlxsw_sp_acl_block_disabled(acl_block)) 1496 return -EOPNOTSUPP; 1497 1498 return mlxsw_sp_setup_tc_cls_flower(acl_block, type_data); 1499 default: 1500 return -EOPNOTSUPP; 1501 } 1502 } 1503 1504 static int 1505 mlxsw_sp_setup_tc_block_flower_bind(struct mlxsw_sp_port *mlxsw_sp_port, 1506 struct tcf_block *block, bool ingress, 1507 struct netlink_ext_ack *extack) 1508 { 1509 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1510 struct mlxsw_sp_acl_block *acl_block; 1511 struct tcf_block_cb *block_cb; 1512 int err; 1513 1514 block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower, 1515 mlxsw_sp); 1516 if (!block_cb) { 1517 acl_block = mlxsw_sp_acl_block_create(mlxsw_sp, block->net); 1518 if (!acl_block) 1519 return -ENOMEM; 1520 block_cb = __tcf_block_cb_register(block, 1521 mlxsw_sp_setup_tc_block_cb_flower, 1522 mlxsw_sp, acl_block, extack); 1523 if (IS_ERR(block_cb)) { 1524 err = PTR_ERR(block_cb); 1525 goto err_cb_register; 1526 } 1527 } else { 1528 acl_block = tcf_block_cb_priv(block_cb); 1529 } 1530 tcf_block_cb_incref(block_cb); 1531 err = mlxsw_sp_acl_block_bind(mlxsw_sp, acl_block, 1532 mlxsw_sp_port, ingress); 1533 if (err) 1534 goto err_block_bind; 1535 1536 if (ingress) 1537 mlxsw_sp_port->ing_acl_block = acl_block; 1538 else 1539 mlxsw_sp_port->eg_acl_block = acl_block; 1540 1541 return 0; 1542 1543 err_block_bind: 1544 if (!tcf_block_cb_decref(block_cb)) { 1545 __tcf_block_cb_unregister(block, block_cb); 1546 err_cb_register: 1547 mlxsw_sp_acl_block_destroy(acl_block); 1548 } 1549 return err; 1550 } 1551 1552 static void 1553 mlxsw_sp_setup_tc_block_flower_unbind(struct mlxsw_sp_port *mlxsw_sp_port, 1554 struct tcf_block *block, bool ingress) 1555 { 1556 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1557 struct mlxsw_sp_acl_block *acl_block; 1558 struct tcf_block_cb *block_cb; 1559 int err; 1560 1561 block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower, 1562 mlxsw_sp); 1563 if (!block_cb) 1564 return; 1565 1566 if (ingress) 1567 mlxsw_sp_port->ing_acl_block = NULL; 1568 else 1569 mlxsw_sp_port->eg_acl_block = NULL; 1570 1571 acl_block = tcf_block_cb_priv(block_cb); 1572 err = mlxsw_sp_acl_block_unbind(mlxsw_sp, acl_block, 1573 mlxsw_sp_port, ingress); 1574 if (!err && !tcf_block_cb_decref(block_cb)) { 1575 __tcf_block_cb_unregister(block, block_cb); 1576 mlxsw_sp_acl_block_destroy(acl_block); 1577 } 1578 } 1579 1580 static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port, 1581 struct tc_block_offload *f) 1582 { 1583 tc_setup_cb_t *cb; 1584 bool ingress; 1585 int err; 1586 1587 if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) { 1588 cb = mlxsw_sp_setup_tc_block_cb_matchall_ig; 1589 ingress = true; 1590 } else if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_EGRESS) { 1591 cb = mlxsw_sp_setup_tc_block_cb_matchall_eg; 1592 ingress = false; 1593 } else { 1594 return -EOPNOTSUPP; 1595 } 1596 1597 switch (f->command) { 1598 case TC_BLOCK_BIND: 1599 err = tcf_block_cb_register(f->block, cb, mlxsw_sp_port, 1600 mlxsw_sp_port, f->extack); 1601 if (err) 1602 return err; 1603 err = mlxsw_sp_setup_tc_block_flower_bind(mlxsw_sp_port, 1604 f->block, ingress, 1605 f->extack); 1606 if (err) { 1607 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port); 1608 return err; 1609 } 1610 return 0; 1611 case TC_BLOCK_UNBIND: 1612 mlxsw_sp_setup_tc_block_flower_unbind(mlxsw_sp_port, 1613 f->block, ingress); 1614 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port); 1615 return 0; 1616 default: 1617 return -EOPNOTSUPP; 1618 } 1619 } 1620 1621 static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type, 1622 void *type_data) 1623 { 1624 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1625 1626 switch (type) { 1627 case TC_SETUP_BLOCK: 1628 return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data); 1629 case TC_SETUP_QDISC_RED: 1630 return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data); 1631 case TC_SETUP_QDISC_PRIO: 1632 return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data); 1633 default: 1634 return -EOPNOTSUPP; 1635 } 1636 } 1637 1638 1639 static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable) 1640 { 1641 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1642 1643 if (!enable) { 1644 if (mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->ing_acl_block) || 1645 mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->eg_acl_block) || 1646 !list_empty(&mlxsw_sp_port->mall_tc_list)) { 1647 netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n"); 1648 return -EINVAL; 1649 } 1650 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->ing_acl_block); 1651 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->eg_acl_block); 1652 } else { 1653 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->ing_acl_block); 1654 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->eg_acl_block); 1655 } 1656 return 0; 1657 } 1658 1659 typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable); 1660 1661 static int mlxsw_sp_handle_feature(struct net_device *dev, 1662 netdev_features_t wanted_features, 1663 netdev_features_t feature, 1664 mlxsw_sp_feature_handler feature_handler) 1665 { 1666 netdev_features_t changes = wanted_features ^ dev->features; 1667 bool enable = !!(wanted_features & feature); 1668 int err; 1669 1670 if (!(changes & feature)) 1671 return 0; 1672 1673 err = feature_handler(dev, enable); 1674 if (err) { 1675 netdev_err(dev, "%s feature %pNF failed, err %d\n", 1676 enable ? "Enable" : "Disable", &feature, err); 1677 return err; 1678 } 1679 1680 if (enable) 1681 dev->features |= feature; 1682 else 1683 dev->features &= ~feature; 1684 1685 return 0; 1686 } 1687 static int mlxsw_sp_set_features(struct net_device *dev, 1688 netdev_features_t features) 1689 { 1690 return mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC, 1691 mlxsw_sp_feature_hw_tc); 1692 } 1693 1694 static const struct net_device_ops mlxsw_sp_port_netdev_ops = { 1695 .ndo_open = mlxsw_sp_port_open, 1696 .ndo_stop = mlxsw_sp_port_stop, 1697 .ndo_start_xmit = mlxsw_sp_port_xmit, 1698 .ndo_setup_tc = mlxsw_sp_setup_tc, 1699 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode, 1700 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address, 1701 .ndo_change_mtu = mlxsw_sp_port_change_mtu, 1702 .ndo_get_stats64 = mlxsw_sp_port_get_stats64, 1703 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats, 1704 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats, 1705 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid, 1706 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid, 1707 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name, 1708 .ndo_set_features = mlxsw_sp_set_features, 1709 }; 1710 1711 static void mlxsw_sp_port_get_drvinfo(struct net_device *dev, 1712 struct ethtool_drvinfo *drvinfo) 1713 { 1714 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1715 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1716 1717 strlcpy(drvinfo->driver, mlxsw_sp->bus_info->device_kind, 1718 sizeof(drvinfo->driver)); 1719 strlcpy(drvinfo->version, mlxsw_sp_driver_version, 1720 sizeof(drvinfo->version)); 1721 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), 1722 "%d.%d.%d", 1723 mlxsw_sp->bus_info->fw_rev.major, 1724 mlxsw_sp->bus_info->fw_rev.minor, 1725 mlxsw_sp->bus_info->fw_rev.subminor); 1726 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name, 1727 sizeof(drvinfo->bus_info)); 1728 } 1729 1730 static void mlxsw_sp_port_get_pauseparam(struct net_device *dev, 1731 struct ethtool_pauseparam *pause) 1732 { 1733 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1734 1735 pause->rx_pause = mlxsw_sp_port->link.rx_pause; 1736 pause->tx_pause = mlxsw_sp_port->link.tx_pause; 1737 } 1738 1739 static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port, 1740 struct ethtool_pauseparam *pause) 1741 { 1742 char pfcc_pl[MLXSW_REG_PFCC_LEN]; 1743 1744 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port); 1745 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause); 1746 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause); 1747 1748 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc), 1749 pfcc_pl); 1750 } 1751 1752 static int mlxsw_sp_port_set_pauseparam(struct net_device *dev, 1753 struct ethtool_pauseparam *pause) 1754 { 1755 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1756 bool pause_en = pause->tx_pause || pause->rx_pause; 1757 int err; 1758 1759 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) { 1760 netdev_err(dev, "PFC already enabled on port\n"); 1761 return -EINVAL; 1762 } 1763 1764 if (pause->autoneg) { 1765 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n"); 1766 return -EINVAL; 1767 } 1768 1769 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en); 1770 if (err) { 1771 netdev_err(dev, "Failed to configure port's headroom\n"); 1772 return err; 1773 } 1774 1775 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause); 1776 if (err) { 1777 netdev_err(dev, "Failed to set PAUSE parameters\n"); 1778 goto err_port_pause_configure; 1779 } 1780 1781 mlxsw_sp_port->link.rx_pause = pause->rx_pause; 1782 mlxsw_sp_port->link.tx_pause = pause->tx_pause; 1783 1784 return 0; 1785 1786 err_port_pause_configure: 1787 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port); 1788 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en); 1789 return err; 1790 } 1791 1792 struct mlxsw_sp_port_hw_stats { 1793 char str[ETH_GSTRING_LEN]; 1794 u64 (*getter)(const char *payload); 1795 bool cells_bytes; 1796 }; 1797 1798 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = { 1799 { 1800 .str = "a_frames_transmitted_ok", 1801 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get, 1802 }, 1803 { 1804 .str = "a_frames_received_ok", 1805 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get, 1806 }, 1807 { 1808 .str = "a_frame_check_sequence_errors", 1809 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get, 1810 }, 1811 { 1812 .str = "a_alignment_errors", 1813 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get, 1814 }, 1815 { 1816 .str = "a_octets_transmitted_ok", 1817 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get, 1818 }, 1819 { 1820 .str = "a_octets_received_ok", 1821 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get, 1822 }, 1823 { 1824 .str = "a_multicast_frames_xmitted_ok", 1825 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get, 1826 }, 1827 { 1828 .str = "a_broadcast_frames_xmitted_ok", 1829 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get, 1830 }, 1831 { 1832 .str = "a_multicast_frames_received_ok", 1833 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get, 1834 }, 1835 { 1836 .str = "a_broadcast_frames_received_ok", 1837 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get, 1838 }, 1839 { 1840 .str = "a_in_range_length_errors", 1841 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get, 1842 }, 1843 { 1844 .str = "a_out_of_range_length_field", 1845 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get, 1846 }, 1847 { 1848 .str = "a_frame_too_long_errors", 1849 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get, 1850 }, 1851 { 1852 .str = "a_symbol_error_during_carrier", 1853 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get, 1854 }, 1855 { 1856 .str = "a_mac_control_frames_transmitted", 1857 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get, 1858 }, 1859 { 1860 .str = "a_mac_control_frames_received", 1861 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get, 1862 }, 1863 { 1864 .str = "a_unsupported_opcodes_received", 1865 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get, 1866 }, 1867 { 1868 .str = "a_pause_mac_ctrl_frames_received", 1869 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get, 1870 }, 1871 { 1872 .str = "a_pause_mac_ctrl_frames_xmitted", 1873 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get, 1874 }, 1875 }; 1876 1877 #define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats) 1878 1879 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_rfc_2819_stats[] = { 1880 { 1881 .str = "ether_pkts64octets", 1882 .getter = mlxsw_reg_ppcnt_ether_stats_pkts64octets_get, 1883 }, 1884 { 1885 .str = "ether_pkts65to127octets", 1886 .getter = mlxsw_reg_ppcnt_ether_stats_pkts65to127octets_get, 1887 }, 1888 { 1889 .str = "ether_pkts128to255octets", 1890 .getter = mlxsw_reg_ppcnt_ether_stats_pkts128to255octets_get, 1891 }, 1892 { 1893 .str = "ether_pkts256to511octets", 1894 .getter = mlxsw_reg_ppcnt_ether_stats_pkts256to511octets_get, 1895 }, 1896 { 1897 .str = "ether_pkts512to1023octets", 1898 .getter = mlxsw_reg_ppcnt_ether_stats_pkts512to1023octets_get, 1899 }, 1900 { 1901 .str = "ether_pkts1024to1518octets", 1902 .getter = mlxsw_reg_ppcnt_ether_stats_pkts1024to1518octets_get, 1903 }, 1904 { 1905 .str = "ether_pkts1519to2047octets", 1906 .getter = mlxsw_reg_ppcnt_ether_stats_pkts1519to2047octets_get, 1907 }, 1908 { 1909 .str = "ether_pkts2048to4095octets", 1910 .getter = mlxsw_reg_ppcnt_ether_stats_pkts2048to4095octets_get, 1911 }, 1912 { 1913 .str = "ether_pkts4096to8191octets", 1914 .getter = mlxsw_reg_ppcnt_ether_stats_pkts4096to8191octets_get, 1915 }, 1916 { 1917 .str = "ether_pkts8192to10239octets", 1918 .getter = mlxsw_reg_ppcnt_ether_stats_pkts8192to10239octets_get, 1919 }, 1920 }; 1921 1922 #define MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN \ 1923 ARRAY_SIZE(mlxsw_sp_port_hw_rfc_2819_stats) 1924 1925 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = { 1926 { 1927 .str = "rx_octets_prio", 1928 .getter = mlxsw_reg_ppcnt_rx_octets_get, 1929 }, 1930 { 1931 .str = "rx_frames_prio", 1932 .getter = mlxsw_reg_ppcnt_rx_frames_get, 1933 }, 1934 { 1935 .str = "tx_octets_prio", 1936 .getter = mlxsw_reg_ppcnt_tx_octets_get, 1937 }, 1938 { 1939 .str = "tx_frames_prio", 1940 .getter = mlxsw_reg_ppcnt_tx_frames_get, 1941 }, 1942 { 1943 .str = "rx_pause_prio", 1944 .getter = mlxsw_reg_ppcnt_rx_pause_get, 1945 }, 1946 { 1947 .str = "rx_pause_duration_prio", 1948 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get, 1949 }, 1950 { 1951 .str = "tx_pause_prio", 1952 .getter = mlxsw_reg_ppcnt_tx_pause_get, 1953 }, 1954 { 1955 .str = "tx_pause_duration_prio", 1956 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get, 1957 }, 1958 }; 1959 1960 #define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats) 1961 1962 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = { 1963 { 1964 .str = "tc_transmit_queue_tc", 1965 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get, 1966 .cells_bytes = true, 1967 }, 1968 { 1969 .str = "tc_no_buffer_discard_uc_tc", 1970 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get, 1971 }, 1972 }; 1973 1974 #define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats) 1975 1976 #define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \ 1977 MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN + \ 1978 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN * \ 1979 IEEE_8021QAZ_MAX_TCS) + \ 1980 (MLXSW_SP_PORT_HW_TC_STATS_LEN * \ 1981 TC_MAX_QUEUE)) 1982 1983 static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio) 1984 { 1985 int i; 1986 1987 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) { 1988 snprintf(*p, ETH_GSTRING_LEN, "%s_%d", 1989 mlxsw_sp_port_hw_prio_stats[i].str, prio); 1990 *p += ETH_GSTRING_LEN; 1991 } 1992 } 1993 1994 static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc) 1995 { 1996 int i; 1997 1998 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) { 1999 snprintf(*p, ETH_GSTRING_LEN, "%s_%d", 2000 mlxsw_sp_port_hw_tc_stats[i].str, tc); 2001 *p += ETH_GSTRING_LEN; 2002 } 2003 } 2004 2005 static void mlxsw_sp_port_get_strings(struct net_device *dev, 2006 u32 stringset, u8 *data) 2007 { 2008 u8 *p = data; 2009 int i; 2010 2011 switch (stringset) { 2012 case ETH_SS_STATS: 2013 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) { 2014 memcpy(p, mlxsw_sp_port_hw_stats[i].str, 2015 ETH_GSTRING_LEN); 2016 p += ETH_GSTRING_LEN; 2017 } 2018 for (i = 0; i < MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN; i++) { 2019 memcpy(p, mlxsw_sp_port_hw_rfc_2819_stats[i].str, 2020 ETH_GSTRING_LEN); 2021 p += ETH_GSTRING_LEN; 2022 } 2023 2024 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) 2025 mlxsw_sp_port_get_prio_strings(&p, i); 2026 2027 for (i = 0; i < TC_MAX_QUEUE; i++) 2028 mlxsw_sp_port_get_tc_strings(&p, i); 2029 2030 break; 2031 } 2032 } 2033 2034 static int mlxsw_sp_port_set_phys_id(struct net_device *dev, 2035 enum ethtool_phys_id_state state) 2036 { 2037 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 2038 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2039 char mlcr_pl[MLXSW_REG_MLCR_LEN]; 2040 bool active; 2041 2042 switch (state) { 2043 case ETHTOOL_ID_ACTIVE: 2044 active = true; 2045 break; 2046 case ETHTOOL_ID_INACTIVE: 2047 active = false; 2048 break; 2049 default: 2050 return -EOPNOTSUPP; 2051 } 2052 2053 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active); 2054 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl); 2055 } 2056 2057 static int 2058 mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats, 2059 int *p_len, enum mlxsw_reg_ppcnt_grp grp) 2060 { 2061 switch (grp) { 2062 case MLXSW_REG_PPCNT_IEEE_8023_CNT: 2063 *p_hw_stats = mlxsw_sp_port_hw_stats; 2064 *p_len = MLXSW_SP_PORT_HW_STATS_LEN; 2065 break; 2066 case MLXSW_REG_PPCNT_RFC_2819_CNT: 2067 *p_hw_stats = mlxsw_sp_port_hw_rfc_2819_stats; 2068 *p_len = MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN; 2069 break; 2070 case MLXSW_REG_PPCNT_PRIO_CNT: 2071 *p_hw_stats = mlxsw_sp_port_hw_prio_stats; 2072 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN; 2073 break; 2074 case MLXSW_REG_PPCNT_TC_CNT: 2075 *p_hw_stats = mlxsw_sp_port_hw_tc_stats; 2076 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN; 2077 break; 2078 default: 2079 WARN_ON(1); 2080 return -EOPNOTSUPP; 2081 } 2082 return 0; 2083 } 2084 2085 static void __mlxsw_sp_port_get_stats(struct net_device *dev, 2086 enum mlxsw_reg_ppcnt_grp grp, int prio, 2087 u64 *data, int data_index) 2088 { 2089 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 2090 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2091 struct mlxsw_sp_port_hw_stats *hw_stats; 2092 char ppcnt_pl[MLXSW_REG_PPCNT_LEN]; 2093 int i, len; 2094 int err; 2095 2096 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp); 2097 if (err) 2098 return; 2099 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl); 2100 for (i = 0; i < len; i++) { 2101 data[data_index + i] = hw_stats[i].getter(ppcnt_pl); 2102 if (!hw_stats[i].cells_bytes) 2103 continue; 2104 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp, 2105 data[data_index + i]); 2106 } 2107 } 2108 2109 static void mlxsw_sp_port_get_stats(struct net_device *dev, 2110 struct ethtool_stats *stats, u64 *data) 2111 { 2112 int i, data_index = 0; 2113 2114 /* IEEE 802.3 Counters */ 2115 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0, 2116 data, data_index); 2117 data_index = MLXSW_SP_PORT_HW_STATS_LEN; 2118 2119 /* RFC 2819 Counters */ 2120 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_RFC_2819_CNT, 0, 2121 data, data_index); 2122 data_index += MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN; 2123 2124 /* Per-Priority Counters */ 2125 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 2126 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i, 2127 data, data_index); 2128 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN; 2129 } 2130 2131 /* Per-TC Counters */ 2132 for (i = 0; i < TC_MAX_QUEUE; i++) { 2133 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i, 2134 data, data_index); 2135 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN; 2136 } 2137 } 2138 2139 static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset) 2140 { 2141 switch (sset) { 2142 case ETH_SS_STATS: 2143 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN; 2144 default: 2145 return -EOPNOTSUPP; 2146 } 2147 } 2148 2149 struct mlxsw_sp_port_link_mode { 2150 enum ethtool_link_mode_bit_indices mask_ethtool; 2151 u32 mask; 2152 u32 speed; 2153 }; 2154 2155 static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = { 2156 { 2157 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T, 2158 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT, 2159 .speed = SPEED_100, 2160 }, 2161 { 2162 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII | 2163 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX, 2164 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 2165 .speed = SPEED_1000, 2166 }, 2167 { 2168 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T, 2169 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 2170 .speed = SPEED_10000, 2171 }, 2172 { 2173 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 | 2174 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4, 2175 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, 2176 .speed = SPEED_10000, 2177 }, 2178 { 2179 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR | 2180 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR | 2181 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR | 2182 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR, 2183 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 2184 .speed = SPEED_10000, 2185 }, 2186 { 2187 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2, 2188 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT, 2189 .speed = SPEED_20000, 2190 }, 2191 { 2192 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4, 2193 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 2194 .speed = SPEED_40000, 2195 }, 2196 { 2197 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4, 2198 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 2199 .speed = SPEED_40000, 2200 }, 2201 { 2202 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4, 2203 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 2204 .speed = SPEED_40000, 2205 }, 2206 { 2207 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4, 2208 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, 2209 .speed = SPEED_40000, 2210 }, 2211 { 2212 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR, 2213 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 2214 .speed = SPEED_25000, 2215 }, 2216 { 2217 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR, 2218 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 2219 .speed = SPEED_25000, 2220 }, 2221 { 2222 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR, 2223 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 2224 .speed = SPEED_25000, 2225 }, 2226 { 2227 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR, 2228 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 2229 .speed = SPEED_25000, 2230 }, 2231 { 2232 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2, 2233 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, 2234 .speed = SPEED_50000, 2235 }, 2236 { 2237 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2, 2238 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, 2239 .speed = SPEED_50000, 2240 }, 2241 { 2242 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2, 2243 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, 2244 .speed = SPEED_50000, 2245 }, 2246 { 2247 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4, 2248 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT, 2249 .speed = SPEED_56000, 2250 }, 2251 { 2252 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4, 2253 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT, 2254 .speed = SPEED_56000, 2255 }, 2256 { 2257 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4, 2258 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT, 2259 .speed = SPEED_56000, 2260 }, 2261 { 2262 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4, 2263 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT, 2264 .speed = SPEED_56000, 2265 }, 2266 { 2267 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4, 2268 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 2269 .speed = SPEED_100000, 2270 }, 2271 { 2272 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4, 2273 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 2274 .speed = SPEED_100000, 2275 }, 2276 { 2277 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4, 2278 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, 2279 .speed = SPEED_100000, 2280 }, 2281 { 2282 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4, 2283 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, 2284 .speed = SPEED_100000, 2285 }, 2286 }; 2287 2288 #define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode) 2289 2290 static void 2291 mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto, 2292 struct ethtool_link_ksettings *cmd) 2293 { 2294 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR | 2295 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR | 2296 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 | 2297 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 | 2298 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 | 2299 MLXSW_REG_PTYS_ETH_SPEED_SGMII)) 2300 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE); 2301 2302 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR | 2303 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 | 2304 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 | 2305 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 | 2306 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX)) 2307 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane); 2308 } 2309 2310 static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode) 2311 { 2312 int i; 2313 2314 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) { 2315 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) 2316 __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool, 2317 mode); 2318 } 2319 } 2320 2321 static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto, 2322 struct ethtool_link_ksettings *cmd) 2323 { 2324 u32 speed = SPEED_UNKNOWN; 2325 u8 duplex = DUPLEX_UNKNOWN; 2326 int i; 2327 2328 if (!carrier_ok) 2329 goto out; 2330 2331 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) { 2332 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) { 2333 speed = mlxsw_sp_port_link_mode[i].speed; 2334 duplex = DUPLEX_FULL; 2335 break; 2336 } 2337 } 2338 out: 2339 cmd->base.speed = speed; 2340 cmd->base.duplex = duplex; 2341 } 2342 2343 static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto) 2344 { 2345 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR | 2346 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 | 2347 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 | 2348 MLXSW_REG_PTYS_ETH_SPEED_SGMII)) 2349 return PORT_FIBRE; 2350 2351 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR | 2352 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 | 2353 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4)) 2354 return PORT_DA; 2355 2356 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR | 2357 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 | 2358 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 | 2359 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4)) 2360 return PORT_NONE; 2361 2362 return PORT_OTHER; 2363 } 2364 2365 static u32 2366 mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd) 2367 { 2368 u32 ptys_proto = 0; 2369 int i; 2370 2371 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) { 2372 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool, 2373 cmd->link_modes.advertising)) 2374 ptys_proto |= mlxsw_sp_port_link_mode[i].mask; 2375 } 2376 return ptys_proto; 2377 } 2378 2379 static u32 mlxsw_sp_to_ptys_speed(u32 speed) 2380 { 2381 u32 ptys_proto = 0; 2382 int i; 2383 2384 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) { 2385 if (speed == mlxsw_sp_port_link_mode[i].speed) 2386 ptys_proto |= mlxsw_sp_port_link_mode[i].mask; 2387 } 2388 return ptys_proto; 2389 } 2390 2391 static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed) 2392 { 2393 u32 ptys_proto = 0; 2394 int i; 2395 2396 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) { 2397 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed) 2398 ptys_proto |= mlxsw_sp_port_link_mode[i].mask; 2399 } 2400 return ptys_proto; 2401 } 2402 2403 static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap, 2404 struct ethtool_link_ksettings *cmd) 2405 { 2406 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause); 2407 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg); 2408 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause); 2409 2410 mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd); 2411 mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported); 2412 } 2413 2414 static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg, 2415 struct ethtool_link_ksettings *cmd) 2416 { 2417 if (!autoneg) 2418 return; 2419 2420 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg); 2421 mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising); 2422 } 2423 2424 static void 2425 mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status, 2426 struct ethtool_link_ksettings *cmd) 2427 { 2428 if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp) 2429 return; 2430 2431 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg); 2432 mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising); 2433 } 2434 2435 static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev, 2436 struct ethtool_link_ksettings *cmd) 2437 { 2438 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp; 2439 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 2440 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2441 char ptys_pl[MLXSW_REG_PTYS_LEN]; 2442 u8 autoneg_status; 2443 bool autoneg; 2444 int err; 2445 2446 autoneg = mlxsw_sp_port->link.autoneg; 2447 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0, false); 2448 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 2449 if (err) 2450 return err; 2451 mlxsw_reg_ptys_eth_unpack(ptys_pl, ð_proto_cap, ð_proto_admin, 2452 ð_proto_oper); 2453 2454 mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd); 2455 2456 mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd); 2457 2458 eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl); 2459 autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl); 2460 mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd); 2461 2462 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE; 2463 cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper); 2464 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper, 2465 cmd); 2466 2467 return 0; 2468 } 2469 2470 static int 2471 mlxsw_sp_port_set_link_ksettings(struct net_device *dev, 2472 const struct ethtool_link_ksettings *cmd) 2473 { 2474 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 2475 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2476 char ptys_pl[MLXSW_REG_PTYS_LEN]; 2477 u32 eth_proto_cap, eth_proto_new; 2478 bool autoneg; 2479 int err; 2480 2481 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0, false); 2482 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 2483 if (err) 2484 return err; 2485 mlxsw_reg_ptys_eth_unpack(ptys_pl, ð_proto_cap, NULL, NULL); 2486 2487 autoneg = cmd->base.autoneg == AUTONEG_ENABLE; 2488 eth_proto_new = autoneg ? 2489 mlxsw_sp_to_ptys_advert_link(cmd) : 2490 mlxsw_sp_to_ptys_speed(cmd->base.speed); 2491 2492 eth_proto_new = eth_proto_new & eth_proto_cap; 2493 if (!eth_proto_new) { 2494 netdev_err(dev, "No supported speed requested\n"); 2495 return -EINVAL; 2496 } 2497 2498 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 2499 eth_proto_new, autoneg); 2500 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 2501 if (err) 2502 return err; 2503 2504 if (!netif_running(dev)) 2505 return 0; 2506 2507 mlxsw_sp_port->link.autoneg = autoneg; 2508 2509 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false); 2510 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true); 2511 2512 return 0; 2513 } 2514 2515 static int mlxsw_sp_flash_device(struct net_device *dev, 2516 struct ethtool_flash *flash) 2517 { 2518 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 2519 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2520 const struct firmware *firmware; 2521 int err; 2522 2523 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS) 2524 return -EOPNOTSUPP; 2525 2526 dev_hold(dev); 2527 rtnl_unlock(); 2528 2529 err = request_firmware_direct(&firmware, flash->data, &dev->dev); 2530 if (err) 2531 goto out; 2532 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware); 2533 release_firmware(firmware); 2534 out: 2535 rtnl_lock(); 2536 dev_put(dev); 2537 return err; 2538 } 2539 2540 #define MLXSW_SP_I2C_ADDR_LOW 0x50 2541 #define MLXSW_SP_I2C_ADDR_HIGH 0x51 2542 #define MLXSW_SP_EEPROM_PAGE_LENGTH 256 2543 2544 static int mlxsw_sp_query_module_eeprom(struct mlxsw_sp_port *mlxsw_sp_port, 2545 u16 offset, u16 size, void *data, 2546 unsigned int *p_read_size) 2547 { 2548 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2549 char eeprom_tmp[MLXSW_SP_REG_MCIA_EEPROM_SIZE]; 2550 char mcia_pl[MLXSW_REG_MCIA_LEN]; 2551 u16 i2c_addr; 2552 int status; 2553 int err; 2554 2555 size = min_t(u16, size, MLXSW_SP_REG_MCIA_EEPROM_SIZE); 2556 2557 if (offset < MLXSW_SP_EEPROM_PAGE_LENGTH && 2558 offset + size > MLXSW_SP_EEPROM_PAGE_LENGTH) 2559 /* Cross pages read, read until offset 256 in low page */ 2560 size = MLXSW_SP_EEPROM_PAGE_LENGTH - offset; 2561 2562 i2c_addr = MLXSW_SP_I2C_ADDR_LOW; 2563 if (offset >= MLXSW_SP_EEPROM_PAGE_LENGTH) { 2564 i2c_addr = MLXSW_SP_I2C_ADDR_HIGH; 2565 offset -= MLXSW_SP_EEPROM_PAGE_LENGTH; 2566 } 2567 2568 mlxsw_reg_mcia_pack(mcia_pl, mlxsw_sp_port->mapping.module, 2569 0, 0, offset, size, i2c_addr); 2570 2571 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcia), mcia_pl); 2572 if (err) 2573 return err; 2574 2575 status = mlxsw_reg_mcia_status_get(mcia_pl); 2576 if (status) 2577 return -EIO; 2578 2579 mlxsw_reg_mcia_eeprom_memcpy_from(mcia_pl, eeprom_tmp); 2580 memcpy(data, eeprom_tmp, size); 2581 *p_read_size = size; 2582 2583 return 0; 2584 } 2585 2586 enum mlxsw_sp_eeprom_module_info_rev_id { 2587 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00, 2588 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01, 2589 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03, 2590 }; 2591 2592 enum mlxsw_sp_eeprom_module_info_id { 2593 MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP = 0x03, 2594 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP = 0x0C, 2595 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D, 2596 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11, 2597 }; 2598 2599 enum mlxsw_sp_eeprom_module_info { 2600 MLXSW_SP_EEPROM_MODULE_INFO_ID, 2601 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID, 2602 MLXSW_SP_EEPROM_MODULE_INFO_SIZE, 2603 }; 2604 2605 static int mlxsw_sp_get_module_info(struct net_device *netdev, 2606 struct ethtool_modinfo *modinfo) 2607 { 2608 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev); 2609 u8 module_info[MLXSW_SP_EEPROM_MODULE_INFO_SIZE]; 2610 u8 module_rev_id, module_id; 2611 unsigned int read_size; 2612 int err; 2613 2614 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, 0, 2615 MLXSW_SP_EEPROM_MODULE_INFO_SIZE, 2616 module_info, &read_size); 2617 if (err) 2618 return err; 2619 2620 if (read_size < MLXSW_SP_EEPROM_MODULE_INFO_SIZE) 2621 return -EIO; 2622 2623 module_rev_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_REV_ID]; 2624 module_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_ID]; 2625 2626 switch (module_id) { 2627 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP: 2628 modinfo->type = ETH_MODULE_SFF_8436; 2629 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 2630 break; 2631 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS: 2632 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28: 2633 if (module_id == MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 || 2634 module_rev_id >= MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636) { 2635 modinfo->type = ETH_MODULE_SFF_8636; 2636 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; 2637 } else { 2638 modinfo->type = ETH_MODULE_SFF_8436; 2639 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 2640 } 2641 break; 2642 case MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP: 2643 modinfo->type = ETH_MODULE_SFF_8472; 2644 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 2645 break; 2646 default: 2647 return -EINVAL; 2648 } 2649 2650 return 0; 2651 } 2652 2653 static int mlxsw_sp_get_module_eeprom(struct net_device *netdev, 2654 struct ethtool_eeprom *ee, 2655 u8 *data) 2656 { 2657 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev); 2658 int offset = ee->offset; 2659 unsigned int read_size; 2660 int i = 0; 2661 int err; 2662 2663 if (!ee->len) 2664 return -EINVAL; 2665 2666 memset(data, 0, ee->len); 2667 2668 while (i < ee->len) { 2669 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, offset, 2670 ee->len - i, data + i, 2671 &read_size); 2672 if (err) { 2673 netdev_err(mlxsw_sp_port->dev, "Eeprom query failed\n"); 2674 return err; 2675 } 2676 2677 i += read_size; 2678 offset += read_size; 2679 } 2680 2681 return 0; 2682 } 2683 2684 static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = { 2685 .get_drvinfo = mlxsw_sp_port_get_drvinfo, 2686 .get_link = ethtool_op_get_link, 2687 .get_pauseparam = mlxsw_sp_port_get_pauseparam, 2688 .set_pauseparam = mlxsw_sp_port_set_pauseparam, 2689 .get_strings = mlxsw_sp_port_get_strings, 2690 .set_phys_id = mlxsw_sp_port_set_phys_id, 2691 .get_ethtool_stats = mlxsw_sp_port_get_stats, 2692 .get_sset_count = mlxsw_sp_port_get_sset_count, 2693 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings, 2694 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings, 2695 .flash_device = mlxsw_sp_flash_device, 2696 .get_module_info = mlxsw_sp_get_module_info, 2697 .get_module_eeprom = mlxsw_sp_get_module_eeprom, 2698 }; 2699 2700 static int 2701 mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width) 2702 { 2703 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2704 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width; 2705 char ptys_pl[MLXSW_REG_PTYS_LEN]; 2706 u32 eth_proto_admin; 2707 2708 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed); 2709 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 2710 eth_proto_admin, mlxsw_sp_port->link.autoneg); 2711 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 2712 } 2713 2714 int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port, 2715 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index, 2716 bool dwrr, u8 dwrr_weight) 2717 { 2718 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2719 char qeec_pl[MLXSW_REG_QEEC_LEN]; 2720 2721 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index, 2722 next_index); 2723 mlxsw_reg_qeec_de_set(qeec_pl, true); 2724 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr); 2725 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight); 2726 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl); 2727 } 2728 2729 int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port, 2730 enum mlxsw_reg_qeec_hr hr, u8 index, 2731 u8 next_index, u32 maxrate) 2732 { 2733 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2734 char qeec_pl[MLXSW_REG_QEEC_LEN]; 2735 2736 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index, 2737 next_index); 2738 mlxsw_reg_qeec_mase_set(qeec_pl, true); 2739 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate); 2740 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl); 2741 } 2742 2743 int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port, 2744 u8 switch_prio, u8 tclass) 2745 { 2746 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2747 char qtct_pl[MLXSW_REG_QTCT_LEN]; 2748 2749 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio, 2750 tclass); 2751 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl); 2752 } 2753 2754 static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port) 2755 { 2756 int err, i; 2757 2758 /* Setup the elements hierarcy, so that each TC is linked to 2759 * one subgroup, which are all member in the same group. 2760 */ 2761 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 2762 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false, 2763 0); 2764 if (err) 2765 return err; 2766 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 2767 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 2768 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i, 2769 0, false, 0); 2770 if (err) 2771 return err; 2772 } 2773 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 2774 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 2775 MLXSW_REG_QEEC_HIERARCY_TC, i, i, 2776 false, 0); 2777 if (err) 2778 return err; 2779 2780 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 2781 MLXSW_REG_QEEC_HIERARCY_TC, 2782 i + 8, i, 2783 false, 0); 2784 if (err) 2785 return err; 2786 } 2787 2788 /* Make sure the max shaper is disabled in all hierarchies that 2789 * support it. 2790 */ 2791 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 2792 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0, 2793 MLXSW_REG_QEEC_MAS_DIS); 2794 if (err) 2795 return err; 2796 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 2797 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 2798 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, 2799 i, 0, 2800 MLXSW_REG_QEEC_MAS_DIS); 2801 if (err) 2802 return err; 2803 } 2804 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 2805 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 2806 MLXSW_REG_QEEC_HIERARCY_TC, 2807 i, i, 2808 MLXSW_REG_QEEC_MAS_DIS); 2809 if (err) 2810 return err; 2811 2812 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 2813 MLXSW_REG_QEEC_HIERARCY_TC, 2814 i + 8, i, 2815 MLXSW_REG_QEEC_MAS_DIS); 2816 if (err) 2817 return err; 2818 } 2819 2820 /* Map all priorities to traffic class 0. */ 2821 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 2822 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0); 2823 if (err) 2824 return err; 2825 } 2826 2827 return 0; 2828 } 2829 2830 static int mlxsw_sp_port_tc_mc_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, 2831 bool enable) 2832 { 2833 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2834 char qtctm_pl[MLXSW_REG_QTCTM_LEN]; 2835 2836 mlxsw_reg_qtctm_pack(qtctm_pl, mlxsw_sp_port->local_port, enable); 2837 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtctm), qtctm_pl); 2838 } 2839 2840 static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port, 2841 bool split, u8 module, u8 width, u8 lane) 2842 { 2843 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 2844 struct mlxsw_sp_port *mlxsw_sp_port; 2845 struct net_device *dev; 2846 int err; 2847 2848 err = mlxsw_core_port_init(mlxsw_sp->core, local_port); 2849 if (err) { 2850 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n", 2851 local_port); 2852 return err; 2853 } 2854 2855 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port)); 2856 if (!dev) { 2857 err = -ENOMEM; 2858 goto err_alloc_etherdev; 2859 } 2860 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev); 2861 mlxsw_sp_port = netdev_priv(dev); 2862 mlxsw_sp_port->dev = dev; 2863 mlxsw_sp_port->mlxsw_sp = mlxsw_sp; 2864 mlxsw_sp_port->local_port = local_port; 2865 mlxsw_sp_port->pvid = 1; 2866 mlxsw_sp_port->split = split; 2867 mlxsw_sp_port->mapping.module = module; 2868 mlxsw_sp_port->mapping.width = width; 2869 mlxsw_sp_port->mapping.lane = lane; 2870 mlxsw_sp_port->link.autoneg = 1; 2871 INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list); 2872 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list); 2873 2874 mlxsw_sp_port->pcpu_stats = 2875 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats); 2876 if (!mlxsw_sp_port->pcpu_stats) { 2877 err = -ENOMEM; 2878 goto err_alloc_stats; 2879 } 2880 2881 mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample), 2882 GFP_KERNEL); 2883 if (!mlxsw_sp_port->sample) { 2884 err = -ENOMEM; 2885 goto err_alloc_sample; 2886 } 2887 2888 INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw, 2889 &update_stats_cache); 2890 2891 dev->netdev_ops = &mlxsw_sp_port_netdev_ops; 2892 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops; 2893 2894 err = mlxsw_sp_port_module_map(mlxsw_sp_port, module, width, lane); 2895 if (err) { 2896 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n", 2897 mlxsw_sp_port->local_port); 2898 goto err_port_module_map; 2899 } 2900 2901 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0); 2902 if (err) { 2903 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n", 2904 mlxsw_sp_port->local_port); 2905 goto err_port_swid_set; 2906 } 2907 2908 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port); 2909 if (err) { 2910 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n", 2911 mlxsw_sp_port->local_port); 2912 goto err_dev_addr_init; 2913 } 2914 2915 netif_carrier_off(dev); 2916 2917 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG | 2918 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC; 2919 dev->hw_features |= NETIF_F_HW_TC; 2920 2921 dev->min_mtu = 0; 2922 dev->max_mtu = ETH_MAX_MTU; 2923 2924 /* Each packet needs to have a Tx header (metadata) on top all other 2925 * headers. 2926 */ 2927 dev->needed_headroom = MLXSW_TXHDR_LEN; 2928 2929 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port); 2930 if (err) { 2931 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n", 2932 mlxsw_sp_port->local_port); 2933 goto err_port_system_port_mapping_set; 2934 } 2935 2936 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width); 2937 if (err) { 2938 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n", 2939 mlxsw_sp_port->local_port); 2940 goto err_port_speed_by_width_set; 2941 } 2942 2943 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN); 2944 if (err) { 2945 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n", 2946 mlxsw_sp_port->local_port); 2947 goto err_port_mtu_set; 2948 } 2949 2950 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false); 2951 if (err) 2952 goto err_port_admin_status_set; 2953 2954 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port); 2955 if (err) { 2956 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n", 2957 mlxsw_sp_port->local_port); 2958 goto err_port_buffers_init; 2959 } 2960 2961 err = mlxsw_sp_port_ets_init(mlxsw_sp_port); 2962 if (err) { 2963 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n", 2964 mlxsw_sp_port->local_port); 2965 goto err_port_ets_init; 2966 } 2967 2968 err = mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, true); 2969 if (err) { 2970 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC MC mode\n", 2971 mlxsw_sp_port->local_port); 2972 goto err_port_tc_mc_mode; 2973 } 2974 2975 /* ETS and buffers must be initialized before DCB. */ 2976 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port); 2977 if (err) { 2978 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n", 2979 mlxsw_sp_port->local_port); 2980 goto err_port_dcb_init; 2981 } 2982 2983 err = mlxsw_sp_port_fids_init(mlxsw_sp_port); 2984 if (err) { 2985 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n", 2986 mlxsw_sp_port->local_port); 2987 goto err_port_fids_init; 2988 } 2989 2990 err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port); 2991 if (err) { 2992 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n", 2993 mlxsw_sp_port->local_port); 2994 goto err_port_qdiscs_init; 2995 } 2996 2997 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1); 2998 if (IS_ERR(mlxsw_sp_port_vlan)) { 2999 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n", 3000 mlxsw_sp_port->local_port); 3001 err = PTR_ERR(mlxsw_sp_port_vlan); 3002 goto err_port_vlan_get; 3003 } 3004 3005 mlxsw_sp_port_switchdev_init(mlxsw_sp_port); 3006 mlxsw_sp->ports[local_port] = mlxsw_sp_port; 3007 err = register_netdev(dev); 3008 if (err) { 3009 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n", 3010 mlxsw_sp_port->local_port); 3011 goto err_register_netdev; 3012 } 3013 3014 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port, 3015 mlxsw_sp_port, dev, module + 1, 3016 mlxsw_sp_port->split, lane / width); 3017 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0); 3018 return 0; 3019 3020 err_register_netdev: 3021 mlxsw_sp->ports[local_port] = NULL; 3022 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port); 3023 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan); 3024 err_port_vlan_get: 3025 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port); 3026 err_port_qdiscs_init: 3027 mlxsw_sp_port_fids_fini(mlxsw_sp_port); 3028 err_port_fids_init: 3029 mlxsw_sp_port_dcb_fini(mlxsw_sp_port); 3030 err_port_dcb_init: 3031 mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false); 3032 err_port_tc_mc_mode: 3033 err_port_ets_init: 3034 err_port_buffers_init: 3035 err_port_admin_status_set: 3036 err_port_mtu_set: 3037 err_port_speed_by_width_set: 3038 err_port_system_port_mapping_set: 3039 err_dev_addr_init: 3040 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT); 3041 err_port_swid_set: 3042 mlxsw_sp_port_module_unmap(mlxsw_sp_port); 3043 err_port_module_map: 3044 kfree(mlxsw_sp_port->sample); 3045 err_alloc_sample: 3046 free_percpu(mlxsw_sp_port->pcpu_stats); 3047 err_alloc_stats: 3048 free_netdev(dev); 3049 err_alloc_etherdev: 3050 mlxsw_core_port_fini(mlxsw_sp->core, local_port); 3051 return err; 3052 } 3053 3054 static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port) 3055 { 3056 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port]; 3057 3058 cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw); 3059 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp); 3060 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */ 3061 mlxsw_sp->ports[local_port] = NULL; 3062 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port); 3063 mlxsw_sp_port_vlan_flush(mlxsw_sp_port); 3064 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port); 3065 mlxsw_sp_port_fids_fini(mlxsw_sp_port); 3066 mlxsw_sp_port_dcb_fini(mlxsw_sp_port); 3067 mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false); 3068 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT); 3069 mlxsw_sp_port_module_unmap(mlxsw_sp_port); 3070 kfree(mlxsw_sp_port->sample); 3071 free_percpu(mlxsw_sp_port->pcpu_stats); 3072 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list)); 3073 free_netdev(mlxsw_sp_port->dev); 3074 mlxsw_core_port_fini(mlxsw_sp->core, local_port); 3075 } 3076 3077 static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port) 3078 { 3079 return mlxsw_sp->ports[local_port] != NULL; 3080 } 3081 3082 static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp) 3083 { 3084 int i; 3085 3086 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++) 3087 if (mlxsw_sp_port_created(mlxsw_sp, i)) 3088 mlxsw_sp_port_remove(mlxsw_sp, i); 3089 kfree(mlxsw_sp->port_to_module); 3090 kfree(mlxsw_sp->ports); 3091 } 3092 3093 static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp) 3094 { 3095 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core); 3096 u8 module, width, lane; 3097 size_t alloc_size; 3098 int i; 3099 int err; 3100 3101 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports; 3102 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL); 3103 if (!mlxsw_sp->ports) 3104 return -ENOMEM; 3105 3106 mlxsw_sp->port_to_module = kmalloc_array(max_ports, sizeof(int), 3107 GFP_KERNEL); 3108 if (!mlxsw_sp->port_to_module) { 3109 err = -ENOMEM; 3110 goto err_port_to_module_alloc; 3111 } 3112 3113 for (i = 1; i < max_ports; i++) { 3114 /* Mark as invalid */ 3115 mlxsw_sp->port_to_module[i] = -1; 3116 3117 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module, 3118 &width, &lane); 3119 if (err) 3120 goto err_port_module_info_get; 3121 if (!width) 3122 continue; 3123 mlxsw_sp->port_to_module[i] = module; 3124 err = mlxsw_sp_port_create(mlxsw_sp, i, false, 3125 module, width, lane); 3126 if (err) 3127 goto err_port_create; 3128 } 3129 return 0; 3130 3131 err_port_create: 3132 err_port_module_info_get: 3133 for (i--; i >= 1; i--) 3134 if (mlxsw_sp_port_created(mlxsw_sp, i)) 3135 mlxsw_sp_port_remove(mlxsw_sp, i); 3136 kfree(mlxsw_sp->port_to_module); 3137 err_port_to_module_alloc: 3138 kfree(mlxsw_sp->ports); 3139 return err; 3140 } 3141 3142 static u8 mlxsw_sp_cluster_base_port_get(u8 local_port) 3143 { 3144 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX; 3145 3146 return local_port - offset; 3147 } 3148 3149 static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port, 3150 u8 module, unsigned int count) 3151 { 3152 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count; 3153 int err, i; 3154 3155 for (i = 0; i < count; i++) { 3156 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true, 3157 module, width, i * width); 3158 if (err) 3159 goto err_port_create; 3160 } 3161 3162 return 0; 3163 3164 err_port_create: 3165 for (i--; i >= 0; i--) 3166 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i)) 3167 mlxsw_sp_port_remove(mlxsw_sp, base_port + i); 3168 return err; 3169 } 3170 3171 static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp, 3172 u8 base_port, unsigned int count) 3173 { 3174 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH; 3175 int i; 3176 3177 /* Split by four means we need to re-create two ports, otherwise 3178 * only one. 3179 */ 3180 count = count / 2; 3181 3182 for (i = 0; i < count; i++) { 3183 local_port = base_port + i * 2; 3184 if (mlxsw_sp->port_to_module[local_port] < 0) 3185 continue; 3186 module = mlxsw_sp->port_to_module[local_port]; 3187 3188 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module, 3189 width, 0); 3190 } 3191 } 3192 3193 static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port, 3194 unsigned int count, 3195 struct netlink_ext_ack *extack) 3196 { 3197 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3198 struct mlxsw_sp_port *mlxsw_sp_port; 3199 u8 module, cur_width, base_port; 3200 int i; 3201 int err; 3202 3203 mlxsw_sp_port = mlxsw_sp->ports[local_port]; 3204 if (!mlxsw_sp_port) { 3205 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n", 3206 local_port); 3207 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist"); 3208 return -EINVAL; 3209 } 3210 3211 module = mlxsw_sp_port->mapping.module; 3212 cur_width = mlxsw_sp_port->mapping.width; 3213 3214 if (count != 2 && count != 4) { 3215 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n"); 3216 NL_SET_ERR_MSG_MOD(extack, "Port can only be split into 2 or 4 ports"); 3217 return -EINVAL; 3218 } 3219 3220 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) { 3221 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n"); 3222 NL_SET_ERR_MSG_MOD(extack, "Port cannot be split further"); 3223 return -EINVAL; 3224 } 3225 3226 /* Make sure we have enough slave (even) ports for the split. */ 3227 if (count == 2) { 3228 base_port = local_port; 3229 if (mlxsw_sp->ports[base_port + 1]) { 3230 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n"); 3231 NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration"); 3232 return -EINVAL; 3233 } 3234 } else { 3235 base_port = mlxsw_sp_cluster_base_port_get(local_port); 3236 if (mlxsw_sp->ports[base_port + 1] || 3237 mlxsw_sp->ports[base_port + 3]) { 3238 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n"); 3239 NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration"); 3240 return -EINVAL; 3241 } 3242 } 3243 3244 for (i = 0; i < count; i++) 3245 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i)) 3246 mlxsw_sp_port_remove(mlxsw_sp, base_port + i); 3247 3248 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count); 3249 if (err) { 3250 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n"); 3251 goto err_port_split_create; 3252 } 3253 3254 return 0; 3255 3256 err_port_split_create: 3257 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count); 3258 return err; 3259 } 3260 3261 static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port, 3262 struct netlink_ext_ack *extack) 3263 { 3264 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3265 struct mlxsw_sp_port *mlxsw_sp_port; 3266 u8 cur_width, base_port; 3267 unsigned int count; 3268 int i; 3269 3270 mlxsw_sp_port = mlxsw_sp->ports[local_port]; 3271 if (!mlxsw_sp_port) { 3272 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n", 3273 local_port); 3274 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist"); 3275 return -EINVAL; 3276 } 3277 3278 if (!mlxsw_sp_port->split) { 3279 netdev_err(mlxsw_sp_port->dev, "Port was not split\n"); 3280 NL_SET_ERR_MSG_MOD(extack, "Port was not split"); 3281 return -EINVAL; 3282 } 3283 3284 cur_width = mlxsw_sp_port->mapping.width; 3285 count = cur_width == 1 ? 4 : 2; 3286 3287 base_port = mlxsw_sp_cluster_base_port_get(local_port); 3288 3289 /* Determine which ports to remove. */ 3290 if (count == 2 && local_port >= base_port + 2) 3291 base_port = base_port + 2; 3292 3293 for (i = 0; i < count; i++) 3294 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i)) 3295 mlxsw_sp_port_remove(mlxsw_sp, base_port + i); 3296 3297 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count); 3298 3299 return 0; 3300 } 3301 3302 static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg, 3303 char *pude_pl, void *priv) 3304 { 3305 struct mlxsw_sp *mlxsw_sp = priv; 3306 struct mlxsw_sp_port *mlxsw_sp_port; 3307 enum mlxsw_reg_pude_oper_status status; 3308 u8 local_port; 3309 3310 local_port = mlxsw_reg_pude_local_port_get(pude_pl); 3311 mlxsw_sp_port = mlxsw_sp->ports[local_port]; 3312 if (!mlxsw_sp_port) 3313 return; 3314 3315 status = mlxsw_reg_pude_oper_status_get(pude_pl); 3316 if (status == MLXSW_PORT_OPER_STATUS_UP) { 3317 netdev_info(mlxsw_sp_port->dev, "link up\n"); 3318 netif_carrier_on(mlxsw_sp_port->dev); 3319 } else { 3320 netdev_info(mlxsw_sp_port->dev, "link down\n"); 3321 netif_carrier_off(mlxsw_sp_port->dev); 3322 } 3323 } 3324 3325 static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb, 3326 u8 local_port, void *priv) 3327 { 3328 struct mlxsw_sp *mlxsw_sp = priv; 3329 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port]; 3330 struct mlxsw_sp_port_pcpu_stats *pcpu_stats; 3331 3332 if (unlikely(!mlxsw_sp_port)) { 3333 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n", 3334 local_port); 3335 return; 3336 } 3337 3338 skb->dev = mlxsw_sp_port->dev; 3339 3340 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats); 3341 u64_stats_update_begin(&pcpu_stats->syncp); 3342 pcpu_stats->rx_packets++; 3343 pcpu_stats->rx_bytes += skb->len; 3344 u64_stats_update_end(&pcpu_stats->syncp); 3345 3346 skb->protocol = eth_type_trans(skb, skb->dev); 3347 netif_receive_skb(skb); 3348 } 3349 3350 static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port, 3351 void *priv) 3352 { 3353 skb->offload_fwd_mark = 1; 3354 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv); 3355 } 3356 3357 static void mlxsw_sp_rx_listener_mr_mark_func(struct sk_buff *skb, 3358 u8 local_port, void *priv) 3359 { 3360 skb->offload_mr_fwd_mark = 1; 3361 skb->offload_fwd_mark = 1; 3362 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv); 3363 } 3364 3365 static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port, 3366 void *priv) 3367 { 3368 struct mlxsw_sp *mlxsw_sp = priv; 3369 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port]; 3370 struct psample_group *psample_group; 3371 u32 size; 3372 3373 if (unlikely(!mlxsw_sp_port)) { 3374 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n", 3375 local_port); 3376 goto out; 3377 } 3378 if (unlikely(!mlxsw_sp_port->sample)) { 3379 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n", 3380 local_port); 3381 goto out; 3382 } 3383 3384 size = mlxsw_sp_port->sample->truncate ? 3385 mlxsw_sp_port->sample->trunc_size : skb->len; 3386 3387 rcu_read_lock(); 3388 psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group); 3389 if (!psample_group) 3390 goto out_unlock; 3391 psample_sample_packet(psample_group, skb, size, 3392 mlxsw_sp_port->dev->ifindex, 0, 3393 mlxsw_sp_port->sample->rate); 3394 out_unlock: 3395 rcu_read_unlock(); 3396 out: 3397 consume_skb(skb); 3398 } 3399 3400 #define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \ 3401 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \ 3402 _is_ctrl, SP_##_trap_group, DISCARD) 3403 3404 #define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \ 3405 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \ 3406 _is_ctrl, SP_##_trap_group, DISCARD) 3407 3408 #define MLXSW_SP_RXL_MR_MARK(_trap_id, _action, _trap_group, _is_ctrl) \ 3409 MLXSW_RXL(mlxsw_sp_rx_listener_mr_mark_func, _trap_id, _action, \ 3410 _is_ctrl, SP_##_trap_group, DISCARD) 3411 3412 #define MLXSW_SP_EVENTL(_func, _trap_id) \ 3413 MLXSW_EVENTL(_func, _trap_id, SP_EVENT) 3414 3415 static const struct mlxsw_listener mlxsw_sp_listener[] = { 3416 /* Events */ 3417 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE), 3418 /* L2 traps */ 3419 MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true), 3420 MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true), 3421 MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true), 3422 MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false), 3423 MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false), 3424 MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false), 3425 MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false), 3426 MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false), 3427 MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false), 3428 MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false), 3429 MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false), 3430 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false), 3431 MLXSW_SP_RXL_MARK(IPV6_MLDV12_LISTENER_QUERY, MIRROR_TO_CPU, IPV6_MLD, 3432 false), 3433 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD, 3434 false), 3435 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_DONE, TRAP_TO_CPU, IPV6_MLD, 3436 false), 3437 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV2_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD, 3438 false), 3439 /* L3 traps */ 3440 MLXSW_SP_RXL_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false), 3441 MLXSW_SP_RXL_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false), 3442 MLXSW_SP_RXL_MARK(LBERROR, TRAP_TO_CPU, ROUTER_EXP, false), 3443 MLXSW_SP_RXL_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false), 3444 MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP, 3445 false), 3446 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, false), 3447 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false), 3448 MLXSW_SP_RXL_MARK(IPV6_ALL_NODES_LINK, TRAP_TO_CPU, ROUTER_EXP, false), 3449 MLXSW_SP_RXL_MARK(IPV6_ALL_ROUTERS_LINK, TRAP_TO_CPU, ROUTER_EXP, 3450 false), 3451 MLXSW_SP_RXL_MARK(IPV4_OSPF, TRAP_TO_CPU, OSPF, false), 3452 MLXSW_SP_RXL_MARK(IPV6_OSPF, TRAP_TO_CPU, OSPF, false), 3453 MLXSW_SP_RXL_MARK(IPV6_DHCP, TRAP_TO_CPU, DHCP, false), 3454 MLXSW_SP_RXL_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false), 3455 MLXSW_SP_RXL_MARK(IPV4_BGP, TRAP_TO_CPU, BGP, false), 3456 MLXSW_SP_RXL_MARK(IPV6_BGP, TRAP_TO_CPU, BGP, false), 3457 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_SOLICITATION, TRAP_TO_CPU, IPV6_ND, 3458 false), 3459 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND, 3460 false), 3461 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_SOLICITATION, TRAP_TO_CPU, IPV6_ND, 3462 false), 3463 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND, 3464 false), 3465 MLXSW_SP_RXL_MARK(L3_IPV6_REDIRECTION, TRAP_TO_CPU, IPV6_ND, false), 3466 MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, 3467 false), 3468 MLXSW_SP_RXL_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, HOST_MISS, false), 3469 MLXSW_SP_RXL_MARK(HOST_MISS_IPV6, TRAP_TO_CPU, HOST_MISS, false), 3470 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV4, TRAP_TO_CPU, ROUTER_EXP, false), 3471 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV6, TRAP_TO_CPU, ROUTER_EXP, false), 3472 MLXSW_SP_RXL_MARK(IPIP_DECAP_ERROR, TRAP_TO_CPU, ROUTER_EXP, false), 3473 MLXSW_SP_RXL_MARK(DECAP_ECN0, TRAP_TO_CPU, ROUTER_EXP, false), 3474 MLXSW_SP_RXL_MARK(IPV4_VRRP, TRAP_TO_CPU, ROUTER_EXP, false), 3475 MLXSW_SP_RXL_MARK(IPV6_VRRP, TRAP_TO_CPU, ROUTER_EXP, false), 3476 /* PKT Sample trap */ 3477 MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU, 3478 false, SP_IP2ME, DISCARD), 3479 /* ACL trap */ 3480 MLXSW_SP_RXL_NO_MARK(ACL0, TRAP_TO_CPU, IP2ME, false), 3481 /* Multicast Router Traps */ 3482 MLXSW_SP_RXL_MARK(IPV4_PIM, TRAP_TO_CPU, PIM, false), 3483 MLXSW_SP_RXL_MARK(IPV6_PIM, TRAP_TO_CPU, PIM, false), 3484 MLXSW_SP_RXL_MARK(RPF, TRAP_TO_CPU, RPF, false), 3485 MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false), 3486 MLXSW_SP_RXL_MR_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false), 3487 /* NVE traps */ 3488 MLXSW_SP_RXL_MARK(NVE_ENCAP_ARP, TRAP_TO_CPU, ARP, false), 3489 }; 3490 3491 static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core) 3492 { 3493 char qpcr_pl[MLXSW_REG_QPCR_LEN]; 3494 enum mlxsw_reg_qpcr_ir_units ir_units; 3495 int max_cpu_policers; 3496 bool is_bytes; 3497 u8 burst_size; 3498 u32 rate; 3499 int i, err; 3500 3501 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS)) 3502 return -EIO; 3503 3504 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS); 3505 3506 ir_units = MLXSW_REG_QPCR_IR_UNITS_M; 3507 for (i = 0; i < max_cpu_policers; i++) { 3508 is_bytes = false; 3509 switch (i) { 3510 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP: 3511 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP: 3512 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP: 3513 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF: 3514 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM: 3515 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF: 3516 rate = 128; 3517 burst_size = 7; 3518 break; 3519 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP: 3520 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD: 3521 rate = 16 * 1024; 3522 burst_size = 10; 3523 break; 3524 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP: 3525 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP: 3526 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP: 3527 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS: 3528 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP: 3529 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE: 3530 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND: 3531 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST: 3532 rate = 1024; 3533 burst_size = 7; 3534 break; 3535 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME: 3536 is_bytes = true; 3537 rate = 4 * 1024; 3538 burst_size = 4; 3539 break; 3540 default: 3541 continue; 3542 } 3543 3544 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate, 3545 burst_size); 3546 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl); 3547 if (err) 3548 return err; 3549 } 3550 3551 return 0; 3552 } 3553 3554 static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core) 3555 { 3556 char htgt_pl[MLXSW_REG_HTGT_LEN]; 3557 enum mlxsw_reg_htgt_trap_group i; 3558 int max_cpu_policers; 3559 int max_trap_groups; 3560 u8 priority, tc; 3561 u16 policer_id; 3562 int err; 3563 3564 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS)) 3565 return -EIO; 3566 3567 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS); 3568 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS); 3569 3570 for (i = 0; i < max_trap_groups; i++) { 3571 policer_id = i; 3572 switch (i) { 3573 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP: 3574 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP: 3575 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP: 3576 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF: 3577 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM: 3578 priority = 5; 3579 tc = 5; 3580 break; 3581 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP: 3582 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP: 3583 priority = 4; 3584 tc = 4; 3585 break; 3586 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP: 3587 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME: 3588 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD: 3589 priority = 3; 3590 tc = 3; 3591 break; 3592 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP: 3593 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND: 3594 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF: 3595 priority = 2; 3596 tc = 2; 3597 break; 3598 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS: 3599 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP: 3600 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE: 3601 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST: 3602 priority = 1; 3603 tc = 1; 3604 break; 3605 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT: 3606 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY; 3607 tc = MLXSW_REG_HTGT_DEFAULT_TC; 3608 policer_id = MLXSW_REG_HTGT_INVALID_POLICER; 3609 break; 3610 default: 3611 continue; 3612 } 3613 3614 if (max_cpu_policers <= policer_id && 3615 policer_id != MLXSW_REG_HTGT_INVALID_POLICER) 3616 return -EIO; 3617 3618 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc); 3619 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl); 3620 if (err) 3621 return err; 3622 } 3623 3624 return 0; 3625 } 3626 3627 static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp) 3628 { 3629 int i; 3630 int err; 3631 3632 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core); 3633 if (err) 3634 return err; 3635 3636 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core); 3637 if (err) 3638 return err; 3639 3640 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) { 3641 err = mlxsw_core_trap_register(mlxsw_sp->core, 3642 &mlxsw_sp_listener[i], 3643 mlxsw_sp); 3644 if (err) 3645 goto err_listener_register; 3646 3647 } 3648 return 0; 3649 3650 err_listener_register: 3651 for (i--; i >= 0; i--) { 3652 mlxsw_core_trap_unregister(mlxsw_sp->core, 3653 &mlxsw_sp_listener[i], 3654 mlxsw_sp); 3655 } 3656 return err; 3657 } 3658 3659 static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp) 3660 { 3661 int i; 3662 3663 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) { 3664 mlxsw_core_trap_unregister(mlxsw_sp->core, 3665 &mlxsw_sp_listener[i], 3666 mlxsw_sp); 3667 } 3668 } 3669 3670 static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp) 3671 { 3672 char slcr_pl[MLXSW_REG_SLCR_LEN]; 3673 u32 seed; 3674 int err; 3675 3676 get_random_bytes(&seed, sizeof(seed)); 3677 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC | 3678 MLXSW_REG_SLCR_LAG_HASH_DMAC | 3679 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE | 3680 MLXSW_REG_SLCR_LAG_HASH_VLANID | 3681 MLXSW_REG_SLCR_LAG_HASH_SIP | 3682 MLXSW_REG_SLCR_LAG_HASH_DIP | 3683 MLXSW_REG_SLCR_LAG_HASH_SPORT | 3684 MLXSW_REG_SLCR_LAG_HASH_DPORT | 3685 MLXSW_REG_SLCR_LAG_HASH_IPPROTO, seed); 3686 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl); 3687 if (err) 3688 return err; 3689 3690 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) || 3691 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS)) 3692 return -EIO; 3693 3694 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG), 3695 sizeof(struct mlxsw_sp_upper), 3696 GFP_KERNEL); 3697 if (!mlxsw_sp->lags) 3698 return -ENOMEM; 3699 3700 return 0; 3701 } 3702 3703 static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp) 3704 { 3705 kfree(mlxsw_sp->lags); 3706 } 3707 3708 static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core) 3709 { 3710 char htgt_pl[MLXSW_REG_HTGT_LEN]; 3711 3712 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 3713 MLXSW_REG_HTGT_INVALID_POLICER, 3714 MLXSW_REG_HTGT_DEFAULT_PRIORITY, 3715 MLXSW_REG_HTGT_DEFAULT_TC); 3716 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl); 3717 } 3718 3719 static int mlxsw_sp_netdevice_event(struct notifier_block *unused, 3720 unsigned long event, void *ptr); 3721 3722 static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core, 3723 const struct mlxsw_bus_info *mlxsw_bus_info) 3724 { 3725 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3726 int err; 3727 3728 mlxsw_sp->core = mlxsw_core; 3729 mlxsw_sp->bus_info = mlxsw_bus_info; 3730 3731 err = mlxsw_sp_fw_rev_validate(mlxsw_sp); 3732 if (err) 3733 return err; 3734 3735 err = mlxsw_sp_base_mac_get(mlxsw_sp); 3736 if (err) { 3737 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n"); 3738 return err; 3739 } 3740 3741 err = mlxsw_sp_kvdl_init(mlxsw_sp); 3742 if (err) { 3743 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n"); 3744 return err; 3745 } 3746 3747 err = mlxsw_sp_fids_init(mlxsw_sp); 3748 if (err) { 3749 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n"); 3750 goto err_fids_init; 3751 } 3752 3753 err = mlxsw_sp_traps_init(mlxsw_sp); 3754 if (err) { 3755 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n"); 3756 goto err_traps_init; 3757 } 3758 3759 err = mlxsw_sp_buffers_init(mlxsw_sp); 3760 if (err) { 3761 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n"); 3762 goto err_buffers_init; 3763 } 3764 3765 err = mlxsw_sp_lag_init(mlxsw_sp); 3766 if (err) { 3767 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n"); 3768 goto err_lag_init; 3769 } 3770 3771 /* Initialize SPAN before router and switchdev, so that those components 3772 * can call mlxsw_sp_span_respin(). 3773 */ 3774 err = mlxsw_sp_span_init(mlxsw_sp); 3775 if (err) { 3776 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n"); 3777 goto err_span_init; 3778 } 3779 3780 err = mlxsw_sp_switchdev_init(mlxsw_sp); 3781 if (err) { 3782 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n"); 3783 goto err_switchdev_init; 3784 } 3785 3786 err = mlxsw_sp_counter_pool_init(mlxsw_sp); 3787 if (err) { 3788 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n"); 3789 goto err_counter_pool_init; 3790 } 3791 3792 err = mlxsw_sp_afa_init(mlxsw_sp); 3793 if (err) { 3794 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n"); 3795 goto err_afa_init; 3796 } 3797 3798 err = mlxsw_sp_router_init(mlxsw_sp); 3799 if (err) { 3800 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n"); 3801 goto err_router_init; 3802 } 3803 3804 /* Initialize netdevice notifier after router and SPAN is initialized, 3805 * so that the event handler can use router structures and call SPAN 3806 * respin. 3807 */ 3808 mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event; 3809 err = register_netdevice_notifier(&mlxsw_sp->netdevice_nb); 3810 if (err) { 3811 dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n"); 3812 goto err_netdev_notifier; 3813 } 3814 3815 err = mlxsw_sp_acl_init(mlxsw_sp); 3816 if (err) { 3817 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n"); 3818 goto err_acl_init; 3819 } 3820 3821 err = mlxsw_sp_dpipe_init(mlxsw_sp); 3822 if (err) { 3823 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n"); 3824 goto err_dpipe_init; 3825 } 3826 3827 err = mlxsw_sp_ports_create(mlxsw_sp); 3828 if (err) { 3829 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n"); 3830 goto err_ports_create; 3831 } 3832 3833 return 0; 3834 3835 err_ports_create: 3836 mlxsw_sp_dpipe_fini(mlxsw_sp); 3837 err_dpipe_init: 3838 mlxsw_sp_acl_fini(mlxsw_sp); 3839 err_acl_init: 3840 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb); 3841 err_netdev_notifier: 3842 mlxsw_sp_router_fini(mlxsw_sp); 3843 err_router_init: 3844 mlxsw_sp_afa_fini(mlxsw_sp); 3845 err_afa_init: 3846 mlxsw_sp_counter_pool_fini(mlxsw_sp); 3847 err_counter_pool_init: 3848 mlxsw_sp_switchdev_fini(mlxsw_sp); 3849 err_switchdev_init: 3850 mlxsw_sp_span_fini(mlxsw_sp); 3851 err_span_init: 3852 mlxsw_sp_lag_fini(mlxsw_sp); 3853 err_lag_init: 3854 mlxsw_sp_buffers_fini(mlxsw_sp); 3855 err_buffers_init: 3856 mlxsw_sp_traps_fini(mlxsw_sp); 3857 err_traps_init: 3858 mlxsw_sp_fids_fini(mlxsw_sp); 3859 err_fids_init: 3860 mlxsw_sp_kvdl_fini(mlxsw_sp); 3861 return err; 3862 } 3863 3864 static int mlxsw_sp1_init(struct mlxsw_core *mlxsw_core, 3865 const struct mlxsw_bus_info *mlxsw_bus_info) 3866 { 3867 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3868 3869 mlxsw_sp->req_rev = &mlxsw_sp1_fw_rev; 3870 mlxsw_sp->fw_filename = MLXSW_SP1_FW_FILENAME; 3871 mlxsw_sp->kvdl_ops = &mlxsw_sp1_kvdl_ops; 3872 mlxsw_sp->afa_ops = &mlxsw_sp1_act_afa_ops; 3873 mlxsw_sp->afk_ops = &mlxsw_sp1_afk_ops; 3874 mlxsw_sp->mr_tcam_ops = &mlxsw_sp1_mr_tcam_ops; 3875 mlxsw_sp->acl_tcam_ops = &mlxsw_sp1_acl_tcam_ops; 3876 3877 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info); 3878 } 3879 3880 static int mlxsw_sp2_init(struct mlxsw_core *mlxsw_core, 3881 const struct mlxsw_bus_info *mlxsw_bus_info) 3882 { 3883 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3884 3885 mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops; 3886 mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops; 3887 mlxsw_sp->afk_ops = &mlxsw_sp2_afk_ops; 3888 mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops; 3889 mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops; 3890 3891 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info); 3892 } 3893 3894 static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core) 3895 { 3896 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3897 3898 mlxsw_sp_ports_remove(mlxsw_sp); 3899 mlxsw_sp_dpipe_fini(mlxsw_sp); 3900 mlxsw_sp_acl_fini(mlxsw_sp); 3901 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb); 3902 mlxsw_sp_router_fini(mlxsw_sp); 3903 mlxsw_sp_afa_fini(mlxsw_sp); 3904 mlxsw_sp_counter_pool_fini(mlxsw_sp); 3905 mlxsw_sp_switchdev_fini(mlxsw_sp); 3906 mlxsw_sp_span_fini(mlxsw_sp); 3907 mlxsw_sp_lag_fini(mlxsw_sp); 3908 mlxsw_sp_buffers_fini(mlxsw_sp); 3909 mlxsw_sp_traps_fini(mlxsw_sp); 3910 mlxsw_sp_fids_fini(mlxsw_sp); 3911 mlxsw_sp_kvdl_fini(mlxsw_sp); 3912 } 3913 3914 static const struct mlxsw_config_profile mlxsw_sp1_config_profile = { 3915 .used_max_mid = 1, 3916 .max_mid = MLXSW_SP_MID_MAX, 3917 .used_flood_tables = 1, 3918 .used_flood_mode = 1, 3919 .flood_mode = 3, 3920 .max_fid_offset_flood_tables = 3, 3921 .fid_offset_flood_table_size = VLAN_N_VID - 1, 3922 .max_fid_flood_tables = 3, 3923 .fid_flood_table_size = MLXSW_SP_FID_8021D_MAX, 3924 .used_max_ib_mc = 1, 3925 .max_ib_mc = 0, 3926 .used_max_pkey = 1, 3927 .max_pkey = 0, 3928 .used_kvd_sizes = 1, 3929 .kvd_hash_single_parts = 59, 3930 .kvd_hash_double_parts = 41, 3931 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE, 3932 .swid_config = { 3933 { 3934 .used_type = 1, 3935 .type = MLXSW_PORT_SWID_TYPE_ETH, 3936 } 3937 }, 3938 }; 3939 3940 static const struct mlxsw_config_profile mlxsw_sp2_config_profile = { 3941 .used_max_mid = 1, 3942 .max_mid = MLXSW_SP_MID_MAX, 3943 .used_flood_tables = 1, 3944 .used_flood_mode = 1, 3945 .flood_mode = 3, 3946 .max_fid_offset_flood_tables = 3, 3947 .fid_offset_flood_table_size = VLAN_N_VID - 1, 3948 .max_fid_flood_tables = 3, 3949 .fid_flood_table_size = MLXSW_SP_FID_8021D_MAX, 3950 .used_max_ib_mc = 1, 3951 .max_ib_mc = 0, 3952 .used_max_pkey = 1, 3953 .max_pkey = 0, 3954 .swid_config = { 3955 { 3956 .used_type = 1, 3957 .type = MLXSW_PORT_SWID_TYPE_ETH, 3958 } 3959 }, 3960 }; 3961 3962 static void 3963 mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core, 3964 struct devlink_resource_size_params *kvd_size_params, 3965 struct devlink_resource_size_params *linear_size_params, 3966 struct devlink_resource_size_params *hash_double_size_params, 3967 struct devlink_resource_size_params *hash_single_size_params) 3968 { 3969 u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core, 3970 KVD_SINGLE_MIN_SIZE); 3971 u32 double_size_min = MLXSW_CORE_RES_GET(mlxsw_core, 3972 KVD_DOUBLE_MIN_SIZE); 3973 u32 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE); 3974 u32 linear_size_min = 0; 3975 3976 devlink_resource_size_params_init(kvd_size_params, kvd_size, kvd_size, 3977 MLXSW_SP_KVD_GRANULARITY, 3978 DEVLINK_RESOURCE_UNIT_ENTRY); 3979 devlink_resource_size_params_init(linear_size_params, linear_size_min, 3980 kvd_size - single_size_min - 3981 double_size_min, 3982 MLXSW_SP_KVD_GRANULARITY, 3983 DEVLINK_RESOURCE_UNIT_ENTRY); 3984 devlink_resource_size_params_init(hash_double_size_params, 3985 double_size_min, 3986 kvd_size - single_size_min - 3987 linear_size_min, 3988 MLXSW_SP_KVD_GRANULARITY, 3989 DEVLINK_RESOURCE_UNIT_ENTRY); 3990 devlink_resource_size_params_init(hash_single_size_params, 3991 single_size_min, 3992 kvd_size - double_size_min - 3993 linear_size_min, 3994 MLXSW_SP_KVD_GRANULARITY, 3995 DEVLINK_RESOURCE_UNIT_ENTRY); 3996 } 3997 3998 static int mlxsw_sp1_resources_kvd_register(struct mlxsw_core *mlxsw_core) 3999 { 4000 struct devlink *devlink = priv_to_devlink(mlxsw_core); 4001 struct devlink_resource_size_params hash_single_size_params; 4002 struct devlink_resource_size_params hash_double_size_params; 4003 struct devlink_resource_size_params linear_size_params; 4004 struct devlink_resource_size_params kvd_size_params; 4005 u32 kvd_size, single_size, double_size, linear_size; 4006 const struct mlxsw_config_profile *profile; 4007 int err; 4008 4009 profile = &mlxsw_sp1_config_profile; 4010 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE)) 4011 return -EIO; 4012 4013 mlxsw_sp_resource_size_params_prepare(mlxsw_core, &kvd_size_params, 4014 &linear_size_params, 4015 &hash_double_size_params, 4016 &hash_single_size_params); 4017 4018 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE); 4019 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD, 4020 kvd_size, MLXSW_SP_RESOURCE_KVD, 4021 DEVLINK_RESOURCE_ID_PARENT_TOP, 4022 &kvd_size_params); 4023 if (err) 4024 return err; 4025 4026 linear_size = profile->kvd_linear_size; 4027 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_LINEAR, 4028 linear_size, 4029 MLXSW_SP_RESOURCE_KVD_LINEAR, 4030 MLXSW_SP_RESOURCE_KVD, 4031 &linear_size_params); 4032 if (err) 4033 return err; 4034 4035 err = mlxsw_sp1_kvdl_resources_register(mlxsw_core); 4036 if (err) 4037 return err; 4038 4039 double_size = kvd_size - linear_size; 4040 double_size *= profile->kvd_hash_double_parts; 4041 double_size /= profile->kvd_hash_double_parts + 4042 profile->kvd_hash_single_parts; 4043 double_size = rounddown(double_size, MLXSW_SP_KVD_GRANULARITY); 4044 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_DOUBLE, 4045 double_size, 4046 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE, 4047 MLXSW_SP_RESOURCE_KVD, 4048 &hash_double_size_params); 4049 if (err) 4050 return err; 4051 4052 single_size = kvd_size - double_size - linear_size; 4053 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_SINGLE, 4054 single_size, 4055 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE, 4056 MLXSW_SP_RESOURCE_KVD, 4057 &hash_single_size_params); 4058 if (err) 4059 return err; 4060 4061 return 0; 4062 } 4063 4064 static int mlxsw_sp1_resources_register(struct mlxsw_core *mlxsw_core) 4065 { 4066 return mlxsw_sp1_resources_kvd_register(mlxsw_core); 4067 } 4068 4069 static int mlxsw_sp2_resources_register(struct mlxsw_core *mlxsw_core) 4070 { 4071 return 0; 4072 } 4073 4074 static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core, 4075 const struct mlxsw_config_profile *profile, 4076 u64 *p_single_size, u64 *p_double_size, 4077 u64 *p_linear_size) 4078 { 4079 struct devlink *devlink = priv_to_devlink(mlxsw_core); 4080 u32 double_size; 4081 int err; 4082 4083 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SINGLE_MIN_SIZE) || 4084 !MLXSW_CORE_RES_VALID(mlxsw_core, KVD_DOUBLE_MIN_SIZE)) 4085 return -EIO; 4086 4087 /* The hash part is what left of the kvd without the 4088 * linear part. It is split to the single size and 4089 * double size by the parts ratio from the profile. 4090 * Both sizes must be a multiplications of the 4091 * granularity from the profile. In case the user 4092 * provided the sizes they are obtained via devlink. 4093 */ 4094 err = devlink_resource_size_get(devlink, 4095 MLXSW_SP_RESOURCE_KVD_LINEAR, 4096 p_linear_size); 4097 if (err) 4098 *p_linear_size = profile->kvd_linear_size; 4099 4100 err = devlink_resource_size_get(devlink, 4101 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE, 4102 p_double_size); 4103 if (err) { 4104 double_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) - 4105 *p_linear_size; 4106 double_size *= profile->kvd_hash_double_parts; 4107 double_size /= profile->kvd_hash_double_parts + 4108 profile->kvd_hash_single_parts; 4109 *p_double_size = rounddown(double_size, 4110 MLXSW_SP_KVD_GRANULARITY); 4111 } 4112 4113 err = devlink_resource_size_get(devlink, 4114 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE, 4115 p_single_size); 4116 if (err) 4117 *p_single_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) - 4118 *p_double_size - *p_linear_size; 4119 4120 /* Check results are legal. */ 4121 if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) || 4122 *p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) || 4123 MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size) 4124 return -EIO; 4125 4126 return 0; 4127 } 4128 4129 static struct mlxsw_driver mlxsw_sp1_driver = { 4130 .kind = mlxsw_sp1_driver_name, 4131 .priv_size = sizeof(struct mlxsw_sp), 4132 .init = mlxsw_sp1_init, 4133 .fini = mlxsw_sp_fini, 4134 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set, 4135 .port_split = mlxsw_sp_port_split, 4136 .port_unsplit = mlxsw_sp_port_unsplit, 4137 .sb_pool_get = mlxsw_sp_sb_pool_get, 4138 .sb_pool_set = mlxsw_sp_sb_pool_set, 4139 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get, 4140 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set, 4141 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get, 4142 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set, 4143 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot, 4144 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear, 4145 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get, 4146 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get, 4147 .txhdr_construct = mlxsw_sp_txhdr_construct, 4148 .resources_register = mlxsw_sp1_resources_register, 4149 .kvd_sizes_get = mlxsw_sp_kvd_sizes_get, 4150 .txhdr_len = MLXSW_TXHDR_LEN, 4151 .profile = &mlxsw_sp1_config_profile, 4152 .res_query_enabled = true, 4153 }; 4154 4155 static struct mlxsw_driver mlxsw_sp2_driver = { 4156 .kind = mlxsw_sp2_driver_name, 4157 .priv_size = sizeof(struct mlxsw_sp), 4158 .init = mlxsw_sp2_init, 4159 .fini = mlxsw_sp_fini, 4160 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set, 4161 .port_split = mlxsw_sp_port_split, 4162 .port_unsplit = mlxsw_sp_port_unsplit, 4163 .sb_pool_get = mlxsw_sp_sb_pool_get, 4164 .sb_pool_set = mlxsw_sp_sb_pool_set, 4165 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get, 4166 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set, 4167 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get, 4168 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set, 4169 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot, 4170 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear, 4171 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get, 4172 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get, 4173 .txhdr_construct = mlxsw_sp_txhdr_construct, 4174 .resources_register = mlxsw_sp2_resources_register, 4175 .txhdr_len = MLXSW_TXHDR_LEN, 4176 .profile = &mlxsw_sp2_config_profile, 4177 .res_query_enabled = true, 4178 }; 4179 4180 bool mlxsw_sp_port_dev_check(const struct net_device *dev) 4181 { 4182 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops; 4183 } 4184 4185 static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data) 4186 { 4187 struct mlxsw_sp_port **p_mlxsw_sp_port = data; 4188 int ret = 0; 4189 4190 if (mlxsw_sp_port_dev_check(lower_dev)) { 4191 *p_mlxsw_sp_port = netdev_priv(lower_dev); 4192 ret = 1; 4193 } 4194 4195 return ret; 4196 } 4197 4198 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev) 4199 { 4200 struct mlxsw_sp_port *mlxsw_sp_port; 4201 4202 if (mlxsw_sp_port_dev_check(dev)) 4203 return netdev_priv(dev); 4204 4205 mlxsw_sp_port = NULL; 4206 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port); 4207 4208 return mlxsw_sp_port; 4209 } 4210 4211 struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev) 4212 { 4213 struct mlxsw_sp_port *mlxsw_sp_port; 4214 4215 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev); 4216 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL; 4217 } 4218 4219 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev) 4220 { 4221 struct mlxsw_sp_port *mlxsw_sp_port; 4222 4223 if (mlxsw_sp_port_dev_check(dev)) 4224 return netdev_priv(dev); 4225 4226 mlxsw_sp_port = NULL; 4227 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk, 4228 &mlxsw_sp_port); 4229 4230 return mlxsw_sp_port; 4231 } 4232 4233 struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev) 4234 { 4235 struct mlxsw_sp_port *mlxsw_sp_port; 4236 4237 rcu_read_lock(); 4238 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev); 4239 if (mlxsw_sp_port) 4240 dev_hold(mlxsw_sp_port->dev); 4241 rcu_read_unlock(); 4242 return mlxsw_sp_port; 4243 } 4244 4245 void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port) 4246 { 4247 dev_put(mlxsw_sp_port->dev); 4248 } 4249 4250 static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id) 4251 { 4252 char sldr_pl[MLXSW_REG_SLDR_LEN]; 4253 4254 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id); 4255 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 4256 } 4257 4258 static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id) 4259 { 4260 char sldr_pl[MLXSW_REG_SLDR_LEN]; 4261 4262 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id); 4263 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 4264 } 4265 4266 static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port, 4267 u16 lag_id, u8 port_index) 4268 { 4269 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4270 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 4271 4272 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port, 4273 lag_id, port_index); 4274 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 4275 } 4276 4277 static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port, 4278 u16 lag_id) 4279 { 4280 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4281 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 4282 4283 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port, 4284 lag_id); 4285 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 4286 } 4287 4288 static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port, 4289 u16 lag_id) 4290 { 4291 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4292 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 4293 4294 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port, 4295 lag_id); 4296 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 4297 } 4298 4299 static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port, 4300 u16 lag_id) 4301 { 4302 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4303 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 4304 4305 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port, 4306 lag_id); 4307 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 4308 } 4309 4310 static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp, 4311 struct net_device *lag_dev, 4312 u16 *p_lag_id) 4313 { 4314 struct mlxsw_sp_upper *lag; 4315 int free_lag_id = -1; 4316 u64 max_lag; 4317 int i; 4318 4319 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG); 4320 for (i = 0; i < max_lag; i++) { 4321 lag = mlxsw_sp_lag_get(mlxsw_sp, i); 4322 if (lag->ref_count) { 4323 if (lag->dev == lag_dev) { 4324 *p_lag_id = i; 4325 return 0; 4326 } 4327 } else if (free_lag_id < 0) { 4328 free_lag_id = i; 4329 } 4330 } 4331 if (free_lag_id < 0) 4332 return -EBUSY; 4333 *p_lag_id = free_lag_id; 4334 return 0; 4335 } 4336 4337 static bool 4338 mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp, 4339 struct net_device *lag_dev, 4340 struct netdev_lag_upper_info *lag_upper_info, 4341 struct netlink_ext_ack *extack) 4342 { 4343 u16 lag_id; 4344 4345 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0) { 4346 NL_SET_ERR_MSG_MOD(extack, "Exceeded number of supported LAG devices"); 4347 return false; 4348 } 4349 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 4350 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type"); 4351 return false; 4352 } 4353 return true; 4354 } 4355 4356 static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp, 4357 u16 lag_id, u8 *p_port_index) 4358 { 4359 u64 max_lag_members; 4360 int i; 4361 4362 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core, 4363 MAX_LAG_MEMBERS); 4364 for (i = 0; i < max_lag_members; i++) { 4365 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) { 4366 *p_port_index = i; 4367 return 0; 4368 } 4369 } 4370 return -EBUSY; 4371 } 4372 4373 static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port, 4374 struct net_device *lag_dev) 4375 { 4376 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4377 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 4378 struct mlxsw_sp_upper *lag; 4379 u16 lag_id; 4380 u8 port_index; 4381 int err; 4382 4383 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id); 4384 if (err) 4385 return err; 4386 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id); 4387 if (!lag->ref_count) { 4388 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id); 4389 if (err) 4390 return err; 4391 lag->dev = lag_dev; 4392 } 4393 4394 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index); 4395 if (err) 4396 return err; 4397 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index); 4398 if (err) 4399 goto err_col_port_add; 4400 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id); 4401 if (err) 4402 goto err_col_port_enable; 4403 4404 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index, 4405 mlxsw_sp_port->local_port); 4406 mlxsw_sp_port->lag_id = lag_id; 4407 mlxsw_sp_port->lagged = 1; 4408 lag->ref_count++; 4409 4410 /* Port is no longer usable as a router interface */ 4411 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, 1); 4412 if (mlxsw_sp_port_vlan->fid) 4413 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan); 4414 4415 return 0; 4416 4417 err_col_port_enable: 4418 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id); 4419 err_col_port_add: 4420 if (!lag->ref_count) 4421 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id); 4422 return err; 4423 } 4424 4425 static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port, 4426 struct net_device *lag_dev) 4427 { 4428 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4429 u16 lag_id = mlxsw_sp_port->lag_id; 4430 struct mlxsw_sp_upper *lag; 4431 4432 if (!mlxsw_sp_port->lagged) 4433 return; 4434 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id); 4435 WARN_ON(lag->ref_count == 0); 4436 4437 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id); 4438 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id); 4439 4440 /* Any VLANs configured on the port are no longer valid */ 4441 mlxsw_sp_port_vlan_flush(mlxsw_sp_port); 4442 4443 if (lag->ref_count == 1) 4444 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id); 4445 4446 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id, 4447 mlxsw_sp_port->local_port); 4448 mlxsw_sp_port->lagged = 0; 4449 lag->ref_count--; 4450 4451 mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1); 4452 /* Make sure untagged frames are allowed to ingress */ 4453 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1); 4454 } 4455 4456 static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port, 4457 u16 lag_id) 4458 { 4459 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4460 char sldr_pl[MLXSW_REG_SLDR_LEN]; 4461 4462 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id, 4463 mlxsw_sp_port->local_port); 4464 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 4465 } 4466 4467 static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port, 4468 u16 lag_id) 4469 { 4470 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4471 char sldr_pl[MLXSW_REG_SLDR_LEN]; 4472 4473 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id, 4474 mlxsw_sp_port->local_port); 4475 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 4476 } 4477 4478 static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port, 4479 bool lag_tx_enabled) 4480 { 4481 if (lag_tx_enabled) 4482 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, 4483 mlxsw_sp_port->lag_id); 4484 else 4485 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port, 4486 mlxsw_sp_port->lag_id); 4487 } 4488 4489 static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port, 4490 struct netdev_lag_lower_state_info *info) 4491 { 4492 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled); 4493 } 4494 4495 static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, 4496 bool enable) 4497 { 4498 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4499 enum mlxsw_reg_spms_state spms_state; 4500 char *spms_pl; 4501 u16 vid; 4502 int err; 4503 4504 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING : 4505 MLXSW_REG_SPMS_STATE_DISCARDING; 4506 4507 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL); 4508 if (!spms_pl) 4509 return -ENOMEM; 4510 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port); 4511 4512 for (vid = 0; vid < VLAN_N_VID; vid++) 4513 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state); 4514 4515 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl); 4516 kfree(spms_pl); 4517 return err; 4518 } 4519 4520 static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port) 4521 { 4522 u16 vid = 1; 4523 int err; 4524 4525 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true); 4526 if (err) 4527 return err; 4528 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true); 4529 if (err) 4530 goto err_port_stp_set; 4531 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1, 4532 true, false); 4533 if (err) 4534 goto err_port_vlan_set; 4535 4536 for (; vid <= VLAN_N_VID - 1; vid++) { 4537 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, 4538 vid, false); 4539 if (err) 4540 goto err_vid_learning_set; 4541 } 4542 4543 return 0; 4544 4545 err_vid_learning_set: 4546 for (vid--; vid >= 1; vid--) 4547 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true); 4548 err_port_vlan_set: 4549 mlxsw_sp_port_stp_set(mlxsw_sp_port, false); 4550 err_port_stp_set: 4551 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false); 4552 return err; 4553 } 4554 4555 static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port) 4556 { 4557 u16 vid; 4558 4559 for (vid = VLAN_N_VID - 1; vid >= 1; vid--) 4560 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, 4561 vid, true); 4562 4563 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1, 4564 false, false); 4565 mlxsw_sp_port_stp_set(mlxsw_sp_port, false); 4566 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false); 4567 } 4568 4569 static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev, 4570 struct net_device *dev, 4571 unsigned long event, void *ptr) 4572 { 4573 struct netdev_notifier_changeupper_info *info; 4574 struct mlxsw_sp_port *mlxsw_sp_port; 4575 struct netlink_ext_ack *extack; 4576 struct net_device *upper_dev; 4577 struct mlxsw_sp *mlxsw_sp; 4578 int err = 0; 4579 4580 mlxsw_sp_port = netdev_priv(dev); 4581 mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4582 info = ptr; 4583 extack = netdev_notifier_info_to_extack(&info->info); 4584 4585 switch (event) { 4586 case NETDEV_PRECHANGEUPPER: 4587 upper_dev = info->upper_dev; 4588 if (!is_vlan_dev(upper_dev) && 4589 !netif_is_lag_master(upper_dev) && 4590 !netif_is_bridge_master(upper_dev) && 4591 !netif_is_ovs_master(upper_dev) && 4592 !netif_is_macvlan(upper_dev)) { 4593 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 4594 return -EINVAL; 4595 } 4596 if (!info->linking) 4597 break; 4598 if (netdev_has_any_upper_dev(upper_dev) && 4599 (!netif_is_bridge_master(upper_dev) || 4600 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, 4601 upper_dev))) { 4602 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported"); 4603 return -EINVAL; 4604 } 4605 if (netif_is_lag_master(upper_dev) && 4606 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev, 4607 info->upper_info, extack)) 4608 return -EINVAL; 4609 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) { 4610 NL_SET_ERR_MSG_MOD(extack, "Master device is a LAG master and this device has a VLAN"); 4611 return -EINVAL; 4612 } 4613 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) && 4614 !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) { 4615 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on a LAG port"); 4616 return -EINVAL; 4617 } 4618 if (netif_is_macvlan(upper_dev) && 4619 !mlxsw_sp_rif_find_by_dev(mlxsw_sp, lower_dev)) { 4620 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces"); 4621 return -EOPNOTSUPP; 4622 } 4623 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) { 4624 NL_SET_ERR_MSG_MOD(extack, "Master device is an OVS master and this device has a VLAN"); 4625 return -EINVAL; 4626 } 4627 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) { 4628 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on an OVS port"); 4629 return -EINVAL; 4630 } 4631 if (is_vlan_dev(upper_dev) && 4632 vlan_dev_vlan_id(upper_dev) == 1) { 4633 NL_SET_ERR_MSG_MOD(extack, "Creating a VLAN device with VID 1 is unsupported: VLAN 1 carries untagged traffic"); 4634 return -EINVAL; 4635 } 4636 break; 4637 case NETDEV_CHANGEUPPER: 4638 upper_dev = info->upper_dev; 4639 if (netif_is_bridge_master(upper_dev)) { 4640 if (info->linking) 4641 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port, 4642 lower_dev, 4643 upper_dev, 4644 extack); 4645 else 4646 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, 4647 lower_dev, 4648 upper_dev); 4649 } else if (netif_is_lag_master(upper_dev)) { 4650 if (info->linking) 4651 err = mlxsw_sp_port_lag_join(mlxsw_sp_port, 4652 upper_dev); 4653 else 4654 mlxsw_sp_port_lag_leave(mlxsw_sp_port, 4655 upper_dev); 4656 } else if (netif_is_ovs_master(upper_dev)) { 4657 if (info->linking) 4658 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port); 4659 else 4660 mlxsw_sp_port_ovs_leave(mlxsw_sp_port); 4661 } else if (netif_is_macvlan(upper_dev)) { 4662 if (!info->linking) 4663 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev); 4664 } 4665 break; 4666 } 4667 4668 return err; 4669 } 4670 4671 static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev, 4672 unsigned long event, void *ptr) 4673 { 4674 struct netdev_notifier_changelowerstate_info *info; 4675 struct mlxsw_sp_port *mlxsw_sp_port; 4676 int err; 4677 4678 mlxsw_sp_port = netdev_priv(dev); 4679 info = ptr; 4680 4681 switch (event) { 4682 case NETDEV_CHANGELOWERSTATE: 4683 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) { 4684 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port, 4685 info->lower_state_info); 4686 if (err) 4687 netdev_err(dev, "Failed to reflect link aggregation lower state change\n"); 4688 } 4689 break; 4690 } 4691 4692 return 0; 4693 } 4694 4695 static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev, 4696 struct net_device *port_dev, 4697 unsigned long event, void *ptr) 4698 { 4699 switch (event) { 4700 case NETDEV_PRECHANGEUPPER: 4701 case NETDEV_CHANGEUPPER: 4702 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev, 4703 event, ptr); 4704 case NETDEV_CHANGELOWERSTATE: 4705 return mlxsw_sp_netdevice_port_lower_event(port_dev, event, 4706 ptr); 4707 } 4708 4709 return 0; 4710 } 4711 4712 static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev, 4713 unsigned long event, void *ptr) 4714 { 4715 struct net_device *dev; 4716 struct list_head *iter; 4717 int ret; 4718 4719 netdev_for_each_lower_dev(lag_dev, dev, iter) { 4720 if (mlxsw_sp_port_dev_check(dev)) { 4721 ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event, 4722 ptr); 4723 if (ret) 4724 return ret; 4725 } 4726 } 4727 4728 return 0; 4729 } 4730 4731 static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev, 4732 struct net_device *dev, 4733 unsigned long event, void *ptr, 4734 u16 vid) 4735 { 4736 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 4737 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4738 struct netdev_notifier_changeupper_info *info = ptr; 4739 struct netlink_ext_ack *extack; 4740 struct net_device *upper_dev; 4741 int err = 0; 4742 4743 extack = netdev_notifier_info_to_extack(&info->info); 4744 4745 switch (event) { 4746 case NETDEV_PRECHANGEUPPER: 4747 upper_dev = info->upper_dev; 4748 if (!netif_is_bridge_master(upper_dev) && 4749 !netif_is_macvlan(upper_dev)) { 4750 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 4751 return -EINVAL; 4752 } 4753 if (!info->linking) 4754 break; 4755 if (netdev_has_any_upper_dev(upper_dev) && 4756 (!netif_is_bridge_master(upper_dev) || 4757 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, 4758 upper_dev))) { 4759 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported"); 4760 return -EINVAL; 4761 } 4762 if (netif_is_macvlan(upper_dev) && 4763 !mlxsw_sp_rif_find_by_dev(mlxsw_sp, vlan_dev)) { 4764 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces"); 4765 return -EOPNOTSUPP; 4766 } 4767 break; 4768 case NETDEV_CHANGEUPPER: 4769 upper_dev = info->upper_dev; 4770 if (netif_is_bridge_master(upper_dev)) { 4771 if (info->linking) 4772 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port, 4773 vlan_dev, 4774 upper_dev, 4775 extack); 4776 else 4777 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, 4778 vlan_dev, 4779 upper_dev); 4780 } else if (netif_is_macvlan(upper_dev)) { 4781 if (!info->linking) 4782 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev); 4783 } else { 4784 err = -EINVAL; 4785 WARN_ON(1); 4786 } 4787 break; 4788 } 4789 4790 return err; 4791 } 4792 4793 static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev, 4794 struct net_device *lag_dev, 4795 unsigned long event, 4796 void *ptr, u16 vid) 4797 { 4798 struct net_device *dev; 4799 struct list_head *iter; 4800 int ret; 4801 4802 netdev_for_each_lower_dev(lag_dev, dev, iter) { 4803 if (mlxsw_sp_port_dev_check(dev)) { 4804 ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev, 4805 event, ptr, 4806 vid); 4807 if (ret) 4808 return ret; 4809 } 4810 } 4811 4812 return 0; 4813 } 4814 4815 static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev, 4816 unsigned long event, void *ptr) 4817 { 4818 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev); 4819 u16 vid = vlan_dev_vlan_id(vlan_dev); 4820 4821 if (mlxsw_sp_port_dev_check(real_dev)) 4822 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev, 4823 event, ptr, vid); 4824 else if (netif_is_lag_master(real_dev)) 4825 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev, 4826 real_dev, event, 4827 ptr, vid); 4828 4829 return 0; 4830 } 4831 4832 static int mlxsw_sp_netdevice_bridge_event(struct net_device *br_dev, 4833 unsigned long event, void *ptr) 4834 { 4835 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(br_dev); 4836 struct netdev_notifier_changeupper_info *info = ptr; 4837 struct netlink_ext_ack *extack; 4838 struct net_device *upper_dev; 4839 4840 if (!mlxsw_sp) 4841 return 0; 4842 4843 extack = netdev_notifier_info_to_extack(&info->info); 4844 4845 switch (event) { 4846 case NETDEV_PRECHANGEUPPER: 4847 upper_dev = info->upper_dev; 4848 if (!is_vlan_dev(upper_dev) && !netif_is_macvlan(upper_dev)) { 4849 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 4850 return -EOPNOTSUPP; 4851 } 4852 if (!info->linking) 4853 break; 4854 if (netif_is_macvlan(upper_dev) && 4855 !mlxsw_sp_rif_find_by_dev(mlxsw_sp, br_dev)) { 4856 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces"); 4857 return -EOPNOTSUPP; 4858 } 4859 break; 4860 case NETDEV_CHANGEUPPER: 4861 upper_dev = info->upper_dev; 4862 if (info->linking) 4863 break; 4864 if (is_vlan_dev(upper_dev)) 4865 mlxsw_sp_rif_destroy_by_dev(mlxsw_sp, upper_dev); 4866 if (netif_is_macvlan(upper_dev)) 4867 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev); 4868 break; 4869 } 4870 4871 return 0; 4872 } 4873 4874 static int mlxsw_sp_netdevice_macvlan_event(struct net_device *macvlan_dev, 4875 unsigned long event, void *ptr) 4876 { 4877 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(macvlan_dev); 4878 struct netdev_notifier_changeupper_info *info = ptr; 4879 struct netlink_ext_ack *extack; 4880 4881 if (!mlxsw_sp || event != NETDEV_PRECHANGEUPPER) 4882 return 0; 4883 4884 extack = netdev_notifier_info_to_extack(&info->info); 4885 4886 /* VRF enslavement is handled in mlxsw_sp_netdevice_vrf_event() */ 4887 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 4888 4889 return -EOPNOTSUPP; 4890 } 4891 4892 static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr) 4893 { 4894 struct netdev_notifier_changeupper_info *info = ptr; 4895 4896 if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER) 4897 return false; 4898 return netif_is_l3_master(info->upper_dev); 4899 } 4900 4901 static int mlxsw_sp_netdevice_event(struct notifier_block *nb, 4902 unsigned long event, void *ptr) 4903 { 4904 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 4905 struct mlxsw_sp_span_entry *span_entry; 4906 struct mlxsw_sp *mlxsw_sp; 4907 int err = 0; 4908 4909 mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb); 4910 if (event == NETDEV_UNREGISTER) { 4911 span_entry = mlxsw_sp_span_entry_find_by_port(mlxsw_sp, dev); 4912 if (span_entry) 4913 mlxsw_sp_span_entry_invalidate(mlxsw_sp, span_entry); 4914 } 4915 mlxsw_sp_span_respin(mlxsw_sp); 4916 4917 if (mlxsw_sp_netdev_is_ipip_ol(mlxsw_sp, dev)) 4918 err = mlxsw_sp_netdevice_ipip_ol_event(mlxsw_sp, dev, 4919 event, ptr); 4920 else if (mlxsw_sp_netdev_is_ipip_ul(mlxsw_sp, dev)) 4921 err = mlxsw_sp_netdevice_ipip_ul_event(mlxsw_sp, dev, 4922 event, ptr); 4923 else if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU) 4924 err = mlxsw_sp_netdevice_router_port_event(dev); 4925 else if (mlxsw_sp_is_vrf_event(event, ptr)) 4926 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr); 4927 else if (mlxsw_sp_port_dev_check(dev)) 4928 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr); 4929 else if (netif_is_lag_master(dev)) 4930 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr); 4931 else if (is_vlan_dev(dev)) 4932 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr); 4933 else if (netif_is_bridge_master(dev)) 4934 err = mlxsw_sp_netdevice_bridge_event(dev, event, ptr); 4935 else if (netif_is_macvlan(dev)) 4936 err = mlxsw_sp_netdevice_macvlan_event(dev, event, ptr); 4937 4938 return notifier_from_errno(err); 4939 } 4940 4941 static struct notifier_block mlxsw_sp_inetaddr_valid_nb __read_mostly = { 4942 .notifier_call = mlxsw_sp_inetaddr_valid_event, 4943 }; 4944 4945 static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = { 4946 .notifier_call = mlxsw_sp_inetaddr_event, 4947 }; 4948 4949 static struct notifier_block mlxsw_sp_inet6addr_valid_nb __read_mostly = { 4950 .notifier_call = mlxsw_sp_inet6addr_valid_event, 4951 }; 4952 4953 static struct notifier_block mlxsw_sp_inet6addr_nb __read_mostly = { 4954 .notifier_call = mlxsw_sp_inet6addr_event, 4955 }; 4956 4957 static const struct pci_device_id mlxsw_sp1_pci_id_table[] = { 4958 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0}, 4959 {0, }, 4960 }; 4961 4962 static struct pci_driver mlxsw_sp1_pci_driver = { 4963 .name = mlxsw_sp1_driver_name, 4964 .id_table = mlxsw_sp1_pci_id_table, 4965 }; 4966 4967 static const struct pci_device_id mlxsw_sp2_pci_id_table[] = { 4968 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM2), 0}, 4969 {0, }, 4970 }; 4971 4972 static struct pci_driver mlxsw_sp2_pci_driver = { 4973 .name = mlxsw_sp2_driver_name, 4974 .id_table = mlxsw_sp2_pci_id_table, 4975 }; 4976 4977 static int __init mlxsw_sp_module_init(void) 4978 { 4979 int err; 4980 4981 register_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb); 4982 register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb); 4983 register_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb); 4984 register_inet6addr_notifier(&mlxsw_sp_inet6addr_nb); 4985 4986 err = mlxsw_core_driver_register(&mlxsw_sp1_driver); 4987 if (err) 4988 goto err_sp1_core_driver_register; 4989 4990 err = mlxsw_core_driver_register(&mlxsw_sp2_driver); 4991 if (err) 4992 goto err_sp2_core_driver_register; 4993 4994 err = mlxsw_pci_driver_register(&mlxsw_sp1_pci_driver); 4995 if (err) 4996 goto err_sp1_pci_driver_register; 4997 4998 err = mlxsw_pci_driver_register(&mlxsw_sp2_pci_driver); 4999 if (err) 5000 goto err_sp2_pci_driver_register; 5001 5002 return 0; 5003 5004 err_sp2_pci_driver_register: 5005 mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver); 5006 err_sp1_pci_driver_register: 5007 mlxsw_core_driver_unregister(&mlxsw_sp2_driver); 5008 err_sp2_core_driver_register: 5009 mlxsw_core_driver_unregister(&mlxsw_sp1_driver); 5010 err_sp1_core_driver_register: 5011 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb); 5012 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb); 5013 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb); 5014 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb); 5015 return err; 5016 } 5017 5018 static void __exit mlxsw_sp_module_exit(void) 5019 { 5020 mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver); 5021 mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver); 5022 mlxsw_core_driver_unregister(&mlxsw_sp2_driver); 5023 mlxsw_core_driver_unregister(&mlxsw_sp1_driver); 5024 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb); 5025 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb); 5026 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb); 5027 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb); 5028 } 5029 5030 module_init(mlxsw_sp_module_init); 5031 module_exit(mlxsw_sp_module_exit); 5032 5033 MODULE_LICENSE("Dual BSD/GPL"); 5034 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>"); 5035 MODULE_DESCRIPTION("Mellanox Spectrum driver"); 5036 MODULE_DEVICE_TABLE(pci, mlxsw_sp1_pci_id_table); 5037 MODULE_DEVICE_TABLE(pci, mlxsw_sp2_pci_id_table); 5038 MODULE_FIRMWARE(MLXSW_SP1_FW_FILENAME); 5039