1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/types.h> 7 #include <linux/pci.h> 8 #include <linux/netdevice.h> 9 #include <linux/etherdevice.h> 10 #include <linux/ethtool.h> 11 #include <linux/slab.h> 12 #include <linux/device.h> 13 #include <linux/skbuff.h> 14 #include <linux/if_vlan.h> 15 #include <linux/if_bridge.h> 16 #include <linux/workqueue.h> 17 #include <linux/jiffies.h> 18 #include <linux/bitops.h> 19 #include <linux/list.h> 20 #include <linux/notifier.h> 21 #include <linux/dcbnl.h> 22 #include <linux/inetdevice.h> 23 #include <linux/netlink.h> 24 #include <linux/jhash.h> 25 #include <linux/log2.h> 26 #include <linux/refcount.h> 27 #include <linux/rhashtable.h> 28 #include <net/switchdev.h> 29 #include <net/pkt_cls.h> 30 #include <net/netevent.h> 31 #include <net/addrconf.h> 32 #include <linux/ptp_classify.h> 33 34 #include "spectrum.h" 35 #include "pci.h" 36 #include "core.h" 37 #include "core_env.h" 38 #include "reg.h" 39 #include "port.h" 40 #include "trap.h" 41 #include "txheader.h" 42 #include "spectrum_cnt.h" 43 #include "spectrum_dpipe.h" 44 #include "spectrum_acl_flex_actions.h" 45 #include "spectrum_span.h" 46 #include "spectrum_ptp.h" 47 #include "spectrum_trap.h" 48 49 #define MLXSW_SP_FWREV_MINOR 2010 50 #define MLXSW_SP_FWREV_SUBMINOR 1006 51 52 #define MLXSW_SP1_FWREV_MAJOR 13 53 #define MLXSW_SP1_FWREV_CAN_RESET_MINOR 1702 54 55 static const struct mlxsw_fw_rev mlxsw_sp1_fw_rev = { 56 .major = MLXSW_SP1_FWREV_MAJOR, 57 .minor = MLXSW_SP_FWREV_MINOR, 58 .subminor = MLXSW_SP_FWREV_SUBMINOR, 59 .can_reset_minor = MLXSW_SP1_FWREV_CAN_RESET_MINOR, 60 }; 61 62 #define MLXSW_SP1_FW_FILENAME \ 63 "mellanox/mlxsw_spectrum-" __stringify(MLXSW_SP1_FWREV_MAJOR) \ 64 "." __stringify(MLXSW_SP_FWREV_MINOR) \ 65 "." __stringify(MLXSW_SP_FWREV_SUBMINOR) ".mfa2" 66 67 #define MLXSW_SP2_FWREV_MAJOR 29 68 69 static const struct mlxsw_fw_rev mlxsw_sp2_fw_rev = { 70 .major = MLXSW_SP2_FWREV_MAJOR, 71 .minor = MLXSW_SP_FWREV_MINOR, 72 .subminor = MLXSW_SP_FWREV_SUBMINOR, 73 }; 74 75 #define MLXSW_SP2_FW_FILENAME \ 76 "mellanox/mlxsw_spectrum2-" __stringify(MLXSW_SP2_FWREV_MAJOR) \ 77 "." __stringify(MLXSW_SP_FWREV_MINOR) \ 78 "." __stringify(MLXSW_SP_FWREV_SUBMINOR) ".mfa2" 79 80 #define MLXSW_SP3_FWREV_MAJOR 30 81 82 static const struct mlxsw_fw_rev mlxsw_sp3_fw_rev = { 83 .major = MLXSW_SP3_FWREV_MAJOR, 84 .minor = MLXSW_SP_FWREV_MINOR, 85 .subminor = MLXSW_SP_FWREV_SUBMINOR, 86 }; 87 88 #define MLXSW_SP3_FW_FILENAME \ 89 "mellanox/mlxsw_spectrum3-" __stringify(MLXSW_SP3_FWREV_MAJOR) \ 90 "." __stringify(MLXSW_SP_FWREV_MINOR) \ 91 "." __stringify(MLXSW_SP_FWREV_SUBMINOR) ".mfa2" 92 93 #define MLXSW_SP_LINECARDS_INI_BUNDLE_FILENAME \ 94 "mellanox/lc_ini_bundle_" \ 95 __stringify(MLXSW_SP_FWREV_MINOR) "_" \ 96 __stringify(MLXSW_SP_FWREV_SUBMINOR) ".bin" 97 98 static const char mlxsw_sp1_driver_name[] = "mlxsw_spectrum"; 99 static const char mlxsw_sp2_driver_name[] = "mlxsw_spectrum2"; 100 static const char mlxsw_sp3_driver_name[] = "mlxsw_spectrum3"; 101 static const char mlxsw_sp4_driver_name[] = "mlxsw_spectrum4"; 102 103 static const unsigned char mlxsw_sp1_mac_mask[ETH_ALEN] = { 104 0xff, 0xff, 0xff, 0xff, 0xfc, 0x00 105 }; 106 static const unsigned char mlxsw_sp2_mac_mask[ETH_ALEN] = { 107 0xff, 0xff, 0xff, 0xff, 0xf0, 0x00 108 }; 109 110 int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp, 111 unsigned int counter_index, bool clear, 112 u64 *packets, u64 *bytes) 113 { 114 enum mlxsw_reg_mgpc_opcode op = clear ? MLXSW_REG_MGPC_OPCODE_CLEAR : 115 MLXSW_REG_MGPC_OPCODE_NOP; 116 char mgpc_pl[MLXSW_REG_MGPC_LEN]; 117 int err; 118 119 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, op, 120 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 121 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl); 122 if (err) 123 return err; 124 if (packets) 125 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl); 126 if (bytes) 127 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl); 128 return 0; 129 } 130 131 static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp, 132 unsigned int counter_index) 133 { 134 char mgpc_pl[MLXSW_REG_MGPC_LEN]; 135 136 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR, 137 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 138 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl); 139 } 140 141 int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp, 142 unsigned int *p_counter_index) 143 { 144 int err; 145 146 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW, 147 p_counter_index); 148 if (err) 149 return err; 150 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index); 151 if (err) 152 goto err_counter_clear; 153 return 0; 154 155 err_counter_clear: 156 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW, 157 *p_counter_index); 158 return err; 159 } 160 161 void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp, 162 unsigned int counter_index) 163 { 164 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW, 165 counter_index); 166 } 167 168 static bool mlxsw_sp_skb_requires_ts(struct sk_buff *skb) 169 { 170 unsigned int type; 171 172 if (!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) 173 return false; 174 175 type = ptp_classify_raw(skb); 176 return !!ptp_parse_header(skb, type); 177 } 178 179 static void mlxsw_sp_txhdr_info_data_init(struct mlxsw_core *mlxsw_core, 180 struct sk_buff *skb, 181 struct mlxsw_txhdr_info *txhdr_info) 182 { 183 /* Resource validation was done as part of PTP init. */ 184 u16 max_fid = MLXSW_CORE_RES_GET(mlxsw_core, FID); 185 186 txhdr_info->data = true; 187 txhdr_info->max_fid = max_fid; 188 } 189 190 static struct sk_buff * 191 mlxsw_sp_vlan_tag_push(struct mlxsw_sp *mlxsw_sp, struct sk_buff *skb) 192 { 193 /* In some Spectrum ASICs, in order for PTP event packets to have their 194 * correction field correctly set on the egress port they must be 195 * transmitted as data packets. Such packets ingress the ASIC via the 196 * CPU port and must have a VLAN tag, as the CPU port is not configured 197 * with a PVID. Push the default VLAN (4095), which is configured as 198 * egress untagged on all the ports. 199 */ 200 if (skb_vlan_tagged(skb)) 201 return skb; 202 203 return vlan_insert_tag_set_proto(skb, htons(ETH_P_8021Q), 204 MLXSW_SP_DEFAULT_VID); 205 } 206 207 static struct sk_buff * 208 mlxsw_sp_txhdr_preparations(struct mlxsw_sp *mlxsw_sp, struct sk_buff *skb, 209 struct mlxsw_txhdr_info *txhdr_info) 210 { 211 if (likely(!mlxsw_sp_skb_requires_ts(skb))) 212 return skb; 213 214 if (!mlxsw_sp->ptp_ops->tx_as_data) 215 return skb; 216 217 /* Special handling for PTP events that require a time stamp and cannot 218 * be transmitted as regular control packets. 219 */ 220 mlxsw_sp_txhdr_info_data_init(mlxsw_sp->core, skb, txhdr_info); 221 return mlxsw_sp_vlan_tag_push(mlxsw_sp, skb); 222 } 223 224 enum mlxsw_reg_spms_state mlxsw_sp_stp_spms_state(u8 state) 225 { 226 switch (state) { 227 case BR_STATE_FORWARDING: 228 return MLXSW_REG_SPMS_STATE_FORWARDING; 229 case BR_STATE_LEARNING: 230 return MLXSW_REG_SPMS_STATE_LEARNING; 231 case BR_STATE_LISTENING: 232 case BR_STATE_DISABLED: 233 case BR_STATE_BLOCKING: 234 return MLXSW_REG_SPMS_STATE_DISCARDING; 235 default: 236 BUG(); 237 } 238 } 239 240 int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid, 241 u8 state) 242 { 243 enum mlxsw_reg_spms_state spms_state = mlxsw_sp_stp_spms_state(state); 244 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 245 char *spms_pl; 246 int err; 247 248 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL); 249 if (!spms_pl) 250 return -ENOMEM; 251 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port); 252 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state); 253 254 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl); 255 kfree(spms_pl); 256 return err; 257 } 258 259 static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp) 260 { 261 char spad_pl[MLXSW_REG_SPAD_LEN] = {0}; 262 int err; 263 264 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl); 265 if (err) 266 return err; 267 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac); 268 return 0; 269 } 270 271 int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port, 272 bool is_up) 273 { 274 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 275 char paos_pl[MLXSW_REG_PAOS_LEN]; 276 277 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port, 278 is_up ? MLXSW_PORT_ADMIN_STATUS_UP : 279 MLXSW_PORT_ADMIN_STATUS_DOWN); 280 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl); 281 } 282 283 static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port, 284 const unsigned char *addr) 285 { 286 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 287 char ppad_pl[MLXSW_REG_PPAD_LEN]; 288 289 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port); 290 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr); 291 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl); 292 } 293 294 static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port) 295 { 296 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 297 298 eth_hw_addr_gen(mlxsw_sp_port->dev, mlxsw_sp->base_mac, 299 mlxsw_sp_port->local_port); 300 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, 301 mlxsw_sp_port->dev->dev_addr); 302 } 303 304 static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu) 305 { 306 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 307 char pmtu_pl[MLXSW_REG_PMTU_LEN]; 308 309 mtu += MLXSW_PORT_ETH_FRAME_HDR; 310 311 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu); 312 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl); 313 } 314 315 static int mlxsw_sp_port_swid_set(struct mlxsw_sp *mlxsw_sp, 316 u16 local_port, u8 swid) 317 { 318 char pspa_pl[MLXSW_REG_PSPA_LEN]; 319 320 mlxsw_reg_pspa_pack(pspa_pl, swid, local_port); 321 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl); 322 } 323 324 int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable) 325 { 326 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 327 char svpe_pl[MLXSW_REG_SVPE_LEN]; 328 329 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable); 330 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl); 331 } 332 333 int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid, 334 bool learn_enable) 335 { 336 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 337 char *spvmlr_pl; 338 int err; 339 340 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL); 341 if (!spvmlr_pl) 342 return -ENOMEM; 343 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid, 344 learn_enable); 345 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl); 346 kfree(spvmlr_pl); 347 return err; 348 } 349 350 int mlxsw_sp_port_security_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable) 351 { 352 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 353 char spfsr_pl[MLXSW_REG_SPFSR_LEN]; 354 int err; 355 356 if (mlxsw_sp_port->security == enable) 357 return 0; 358 359 mlxsw_reg_spfsr_pack(spfsr_pl, mlxsw_sp_port->local_port, enable); 360 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spfsr), spfsr_pl); 361 if (err) 362 return err; 363 364 mlxsw_sp_port->security = enable; 365 return 0; 366 } 367 368 int mlxsw_sp_ethtype_to_sver_type(u16 ethtype, u8 *p_sver_type) 369 { 370 switch (ethtype) { 371 case ETH_P_8021Q: 372 *p_sver_type = 0; 373 break; 374 case ETH_P_8021AD: 375 *p_sver_type = 1; 376 break; 377 default: 378 return -EINVAL; 379 } 380 381 return 0; 382 } 383 384 int mlxsw_sp_port_egress_ethtype_set(struct mlxsw_sp_port *mlxsw_sp_port, 385 u16 ethtype) 386 { 387 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 388 char spevet_pl[MLXSW_REG_SPEVET_LEN]; 389 u8 sver_type; 390 int err; 391 392 err = mlxsw_sp_ethtype_to_sver_type(ethtype, &sver_type); 393 if (err) 394 return err; 395 396 mlxsw_reg_spevet_pack(spevet_pl, mlxsw_sp_port->local_port, sver_type); 397 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spevet), spevet_pl); 398 } 399 400 static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, 401 u16 vid, u16 ethtype) 402 { 403 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 404 char spvid_pl[MLXSW_REG_SPVID_LEN]; 405 u8 sver_type; 406 int err; 407 408 err = mlxsw_sp_ethtype_to_sver_type(ethtype, &sver_type); 409 if (err) 410 return err; 411 412 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid, 413 sver_type); 414 415 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl); 416 } 417 418 static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port, 419 bool allow) 420 { 421 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 422 char spaft_pl[MLXSW_REG_SPAFT_LEN]; 423 424 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow); 425 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl); 426 } 427 428 int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid, 429 u16 ethtype) 430 { 431 int err; 432 433 if (!vid) { 434 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false); 435 if (err) 436 return err; 437 } else { 438 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid, ethtype); 439 if (err) 440 return err; 441 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true); 442 if (err) 443 goto err_port_allow_untagged_set; 444 } 445 446 mlxsw_sp_port->pvid = vid; 447 return 0; 448 449 err_port_allow_untagged_set: 450 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid, ethtype); 451 return err; 452 } 453 454 static int 455 mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port) 456 { 457 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 458 char sspr_pl[MLXSW_REG_SSPR_LEN]; 459 460 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port); 461 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl); 462 } 463 464 static int 465 mlxsw_sp_port_module_info_parse(struct mlxsw_sp *mlxsw_sp, 466 u16 local_port, char *pmlp_pl, 467 struct mlxsw_sp_port_mapping *port_mapping) 468 { 469 bool separate_rxtx; 470 u8 first_lane; 471 u8 slot_index; 472 u8 module; 473 u8 width; 474 int i; 475 476 module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0); 477 slot_index = mlxsw_reg_pmlp_slot_index_get(pmlp_pl, 0); 478 width = mlxsw_reg_pmlp_width_get(pmlp_pl); 479 separate_rxtx = mlxsw_reg_pmlp_rxtx_get(pmlp_pl); 480 first_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0); 481 482 if (width && !is_power_of_2(width)) { 483 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: width value is not power of 2\n", 484 local_port); 485 return -EINVAL; 486 } 487 488 for (i = 0; i < width; i++) { 489 if (mlxsw_reg_pmlp_module_get(pmlp_pl, i) != module) { 490 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: contains multiple modules\n", 491 local_port); 492 return -EINVAL; 493 } 494 if (mlxsw_reg_pmlp_slot_index_get(pmlp_pl, i) != slot_index) { 495 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: contains multiple slot indexes\n", 496 local_port); 497 return -EINVAL; 498 } 499 if (separate_rxtx && 500 mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, i) != 501 mlxsw_reg_pmlp_rx_lane_get(pmlp_pl, i)) { 502 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: TX and RX lane numbers are different\n", 503 local_port); 504 return -EINVAL; 505 } 506 if (mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, i) != i + first_lane) { 507 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: TX and RX lane numbers are not sequential\n", 508 local_port); 509 return -EINVAL; 510 } 511 } 512 513 port_mapping->module = module; 514 port_mapping->slot_index = slot_index; 515 port_mapping->width = width; 516 port_mapping->module_width = width; 517 port_mapping->lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0); 518 return 0; 519 } 520 521 static int 522 mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp, u16 local_port, 523 struct mlxsw_sp_port_mapping *port_mapping) 524 { 525 char pmlp_pl[MLXSW_REG_PMLP_LEN]; 526 int err; 527 528 mlxsw_reg_pmlp_pack(pmlp_pl, local_port); 529 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl); 530 if (err) 531 return err; 532 return mlxsw_sp_port_module_info_parse(mlxsw_sp, local_port, 533 pmlp_pl, port_mapping); 534 } 535 536 static int 537 mlxsw_sp_port_module_map(struct mlxsw_sp *mlxsw_sp, u16 local_port, 538 const struct mlxsw_sp_port_mapping *port_mapping) 539 { 540 char pmlp_pl[MLXSW_REG_PMLP_LEN]; 541 int i, err; 542 543 mlxsw_env_module_port_map(mlxsw_sp->core, port_mapping->slot_index, 544 port_mapping->module); 545 546 mlxsw_reg_pmlp_pack(pmlp_pl, local_port); 547 mlxsw_reg_pmlp_width_set(pmlp_pl, port_mapping->width); 548 for (i = 0; i < port_mapping->width; i++) { 549 mlxsw_reg_pmlp_slot_index_set(pmlp_pl, i, 550 port_mapping->slot_index); 551 mlxsw_reg_pmlp_module_set(pmlp_pl, i, port_mapping->module); 552 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, port_mapping->lane + i); /* Rx & Tx */ 553 } 554 555 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl); 556 if (err) 557 goto err_pmlp_write; 558 return 0; 559 560 err_pmlp_write: 561 mlxsw_env_module_port_unmap(mlxsw_sp->core, port_mapping->slot_index, 562 port_mapping->module); 563 return err; 564 } 565 566 static void mlxsw_sp_port_module_unmap(struct mlxsw_sp *mlxsw_sp, u16 local_port, 567 u8 slot_index, u8 module) 568 { 569 char pmlp_pl[MLXSW_REG_PMLP_LEN]; 570 571 mlxsw_reg_pmlp_pack(pmlp_pl, local_port); 572 mlxsw_reg_pmlp_width_set(pmlp_pl, 0); 573 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl); 574 mlxsw_env_module_port_unmap(mlxsw_sp->core, slot_index, module); 575 } 576 577 static int mlxsw_sp_port_open(struct net_device *dev) 578 { 579 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 580 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 581 int err; 582 583 err = mlxsw_env_module_port_up(mlxsw_sp->core, 584 mlxsw_sp_port->mapping.slot_index, 585 mlxsw_sp_port->mapping.module); 586 if (err) 587 return err; 588 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true); 589 if (err) 590 goto err_port_admin_status_set; 591 netif_start_queue(dev); 592 return 0; 593 594 err_port_admin_status_set: 595 mlxsw_env_module_port_down(mlxsw_sp->core, 596 mlxsw_sp_port->mapping.slot_index, 597 mlxsw_sp_port->mapping.module); 598 return err; 599 } 600 601 static int mlxsw_sp_port_stop(struct net_device *dev) 602 { 603 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 604 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 605 606 netif_stop_queue(dev); 607 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false); 608 mlxsw_env_module_port_down(mlxsw_sp->core, 609 mlxsw_sp_port->mapping.slot_index, 610 mlxsw_sp_port->mapping.module); 611 return 0; 612 } 613 614 static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb, 615 struct net_device *dev) 616 { 617 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 618 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 619 struct mlxsw_sp_port_pcpu_stats *pcpu_stats; 620 struct mlxsw_txhdr_info txhdr_info = { 621 .tx_info.local_port = mlxsw_sp_port->local_port, 622 .tx_info.is_emad = false, 623 }; 624 u64 len; 625 int err; 626 627 memset(skb->cb, 0, sizeof(struct mlxsw_skb_cb)); 628 629 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &txhdr_info.tx_info)) 630 return NETDEV_TX_BUSY; 631 632 if (eth_skb_pad(skb)) { 633 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped); 634 return NETDEV_TX_OK; 635 } 636 637 skb = mlxsw_sp_txhdr_preparations(mlxsw_sp, skb, &txhdr_info); 638 if (!skb) { 639 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped); 640 return NETDEV_TX_OK; 641 } 642 643 /* TX header is consumed by HW on the way so we shouldn't count its 644 * bytes as being sent. 645 */ 646 len = skb->len - MLXSW_TXHDR_LEN; 647 648 /* Due to a race we might fail here because of a full queue. In that 649 * unlikely case we simply drop the packet. 650 */ 651 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &txhdr_info); 652 653 if (!err) { 654 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats); 655 u64_stats_update_begin(&pcpu_stats->syncp); 656 pcpu_stats->tx_packets++; 657 pcpu_stats->tx_bytes += len; 658 u64_stats_update_end(&pcpu_stats->syncp); 659 } else { 660 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped); 661 dev_kfree_skb_any(skb); 662 } 663 return NETDEV_TX_OK; 664 } 665 666 static void mlxsw_sp_set_rx_mode(struct net_device *dev) 667 { 668 } 669 670 static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p) 671 { 672 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 673 struct sockaddr *addr = p; 674 int err; 675 676 if (!is_valid_ether_addr(addr->sa_data)) 677 return -EADDRNOTAVAIL; 678 679 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data); 680 if (err) 681 return err; 682 eth_hw_addr_set(dev, addr->sa_data); 683 return 0; 684 } 685 686 static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu) 687 { 688 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 689 struct mlxsw_sp_hdroom orig_hdroom; 690 struct mlxsw_sp_hdroom hdroom; 691 int err; 692 693 orig_hdroom = *mlxsw_sp_port->hdroom; 694 695 hdroom = orig_hdroom; 696 hdroom.mtu = mtu; 697 mlxsw_sp_hdroom_bufs_reset_sizes(mlxsw_sp_port, &hdroom); 698 699 err = mlxsw_sp_hdroom_configure(mlxsw_sp_port, &hdroom); 700 if (err) { 701 netdev_err(dev, "Failed to configure port's headroom\n"); 702 return err; 703 } 704 705 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu); 706 if (err) 707 goto err_port_mtu_set; 708 WRITE_ONCE(dev->mtu, mtu); 709 return 0; 710 711 err_port_mtu_set: 712 mlxsw_sp_hdroom_configure(mlxsw_sp_port, &orig_hdroom); 713 return err; 714 } 715 716 static int 717 mlxsw_sp_port_get_sw_stats64(const struct net_device *dev, 718 struct rtnl_link_stats64 *stats) 719 { 720 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 721 struct mlxsw_sp_port_pcpu_stats *p; 722 u64 rx_packets, rx_bytes, tx_packets, tx_bytes; 723 u32 tx_dropped = 0; 724 unsigned int start; 725 int i; 726 727 for_each_possible_cpu(i) { 728 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i); 729 do { 730 start = u64_stats_fetch_begin(&p->syncp); 731 rx_packets = p->rx_packets; 732 rx_bytes = p->rx_bytes; 733 tx_packets = p->tx_packets; 734 tx_bytes = p->tx_bytes; 735 } while (u64_stats_fetch_retry(&p->syncp, start)); 736 737 stats->rx_packets += rx_packets; 738 stats->rx_bytes += rx_bytes; 739 stats->tx_packets += tx_packets; 740 stats->tx_bytes += tx_bytes; 741 /* tx_dropped is u32, updated without syncp protection. */ 742 tx_dropped += p->tx_dropped; 743 } 744 stats->tx_dropped = tx_dropped; 745 return 0; 746 } 747 748 static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id) 749 { 750 switch (attr_id) { 751 case IFLA_OFFLOAD_XSTATS_CPU_HIT: 752 return true; 753 } 754 755 return false; 756 } 757 758 static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev, 759 void *sp) 760 { 761 switch (attr_id) { 762 case IFLA_OFFLOAD_XSTATS_CPU_HIT: 763 return mlxsw_sp_port_get_sw_stats64(dev, sp); 764 } 765 766 return -EINVAL; 767 } 768 769 int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp, 770 int prio, char *ppcnt_pl) 771 { 772 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 773 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 774 775 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio); 776 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl); 777 } 778 779 static int mlxsw_sp_port_get_hw_stats(struct net_device *dev, 780 struct rtnl_link_stats64 *stats) 781 { 782 char ppcnt_pl[MLXSW_REG_PPCNT_LEN]; 783 int err; 784 785 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 786 0, ppcnt_pl); 787 if (err) 788 goto out; 789 790 stats->tx_packets = 791 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl); 792 stats->rx_packets = 793 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl); 794 stats->tx_bytes = 795 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl); 796 stats->rx_bytes = 797 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl); 798 stats->multicast = 799 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl); 800 801 stats->rx_crc_errors = 802 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl); 803 stats->rx_frame_errors = 804 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl); 805 806 stats->rx_length_errors = ( 807 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) + 808 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) + 809 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl)); 810 811 stats->rx_errors = (stats->rx_crc_errors + 812 stats->rx_frame_errors + stats->rx_length_errors); 813 814 out: 815 return err; 816 } 817 818 static void 819 mlxsw_sp_port_get_hw_xstats(struct net_device *dev, 820 struct mlxsw_sp_port_xstats *xstats) 821 { 822 char ppcnt_pl[MLXSW_REG_PPCNT_LEN]; 823 int err, i; 824 825 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0, 826 ppcnt_pl); 827 if (!err) 828 xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl); 829 830 for (i = 0; i < TC_MAX_QUEUE; i++) { 831 err = mlxsw_sp_port_get_stats_raw(dev, 832 MLXSW_REG_PPCNT_TC_CONG_CNT, 833 i, ppcnt_pl); 834 if (err) 835 goto tc_cnt; 836 837 xstats->wred_drop[i] = 838 mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl); 839 xstats->tc_ecn[i] = mlxsw_reg_ppcnt_ecn_marked_tc_get(ppcnt_pl); 840 841 tc_cnt: 842 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT, 843 i, ppcnt_pl); 844 if (err) 845 continue; 846 847 xstats->backlog[i] = 848 mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl); 849 xstats->tail_drop[i] = 850 mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl); 851 } 852 853 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 854 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_PRIO_CNT, 855 i, ppcnt_pl); 856 if (err) 857 continue; 858 859 xstats->tx_packets[i] = mlxsw_reg_ppcnt_tx_frames_get(ppcnt_pl); 860 xstats->tx_bytes[i] = mlxsw_reg_ppcnt_tx_octets_get(ppcnt_pl); 861 } 862 } 863 864 static void update_stats_cache(struct work_struct *work) 865 { 866 struct mlxsw_sp_port *mlxsw_sp_port = 867 container_of(work, struct mlxsw_sp_port, 868 periodic_hw_stats.update_dw.work); 869 870 if (!netif_carrier_ok(mlxsw_sp_port->dev)) 871 /* Note: mlxsw_sp_port_down_wipe_counters() clears the cache as 872 * necessary when port goes down. 873 */ 874 goto out; 875 876 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev, 877 &mlxsw_sp_port->periodic_hw_stats.stats); 878 mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev, 879 &mlxsw_sp_port->periodic_hw_stats.xstats); 880 881 out: 882 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 883 MLXSW_HW_STATS_UPDATE_TIME); 884 } 885 886 /* Return the stats from a cache that is updated periodically, 887 * as this function might get called in an atomic context. 888 */ 889 static void 890 mlxsw_sp_port_get_stats64(struct net_device *dev, 891 struct rtnl_link_stats64 *stats) 892 { 893 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 894 895 memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats)); 896 } 897 898 static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, 899 u16 vid_begin, u16 vid_end, 900 bool is_member, bool untagged) 901 { 902 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 903 char *spvm_pl; 904 int err; 905 906 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL); 907 if (!spvm_pl) 908 return -ENOMEM; 909 910 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin, 911 vid_end, is_member, untagged); 912 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl); 913 kfree(spvm_pl); 914 return err; 915 } 916 917 int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin, 918 u16 vid_end, bool is_member, bool untagged) 919 { 920 u16 vid, vid_e; 921 int err; 922 923 for (vid = vid_begin; vid <= vid_end; 924 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) { 925 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1), 926 vid_end); 927 928 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e, 929 is_member, untagged); 930 if (err) 931 return err; 932 } 933 934 return 0; 935 } 936 937 static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port, 938 bool flush_default) 939 { 940 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp; 941 942 list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp, 943 &mlxsw_sp_port->vlans_list, list) { 944 if (!flush_default && 945 mlxsw_sp_port_vlan->vid == MLXSW_SP_DEFAULT_VID) 946 continue; 947 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan); 948 } 949 } 950 951 static void 952 mlxsw_sp_port_vlan_cleanup(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan) 953 { 954 if (mlxsw_sp_port_vlan->bridge_port) 955 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan); 956 else if (mlxsw_sp_port_vlan->fid) 957 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan); 958 } 959 960 struct mlxsw_sp_port_vlan * 961 mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid) 962 { 963 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 964 bool untagged = vid == MLXSW_SP_DEFAULT_VID; 965 int err; 966 967 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid); 968 if (mlxsw_sp_port_vlan) 969 return ERR_PTR(-EEXIST); 970 971 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged); 972 if (err) 973 return ERR_PTR(err); 974 975 mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL); 976 if (!mlxsw_sp_port_vlan) { 977 err = -ENOMEM; 978 goto err_port_vlan_alloc; 979 } 980 981 mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port; 982 mlxsw_sp_port_vlan->vid = vid; 983 list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list); 984 985 return mlxsw_sp_port_vlan; 986 987 err_port_vlan_alloc: 988 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false); 989 return ERR_PTR(err); 990 } 991 992 void mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan) 993 { 994 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port; 995 u16 vid = mlxsw_sp_port_vlan->vid; 996 997 mlxsw_sp_port_vlan_cleanup(mlxsw_sp_port_vlan); 998 list_del(&mlxsw_sp_port_vlan->list); 999 kfree(mlxsw_sp_port_vlan); 1000 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false); 1001 } 1002 1003 static int mlxsw_sp_port_add_vid(struct net_device *dev, 1004 __be16 __always_unused proto, u16 vid) 1005 { 1006 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1007 1008 /* VLAN 0 is added to HW filter when device goes up, but it is 1009 * reserved in our case, so simply return. 1010 */ 1011 if (!vid) 1012 return 0; 1013 1014 return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid)); 1015 } 1016 1017 int mlxsw_sp_port_kill_vid(struct net_device *dev, 1018 __be16 __always_unused proto, u16 vid) 1019 { 1020 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1021 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 1022 1023 /* VLAN 0 is removed from HW filter when device goes down, but 1024 * it is reserved in our case, so simply return. 1025 */ 1026 if (!vid) 1027 return 0; 1028 1029 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid); 1030 if (!mlxsw_sp_port_vlan) 1031 return 0; 1032 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan); 1033 1034 return 0; 1035 } 1036 1037 static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port, 1038 struct flow_block_offload *f) 1039 { 1040 switch (f->binder_type) { 1041 case FLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS: 1042 return mlxsw_sp_setup_tc_block_clsact(mlxsw_sp_port, f, true); 1043 case FLOW_BLOCK_BINDER_TYPE_CLSACT_EGRESS: 1044 return mlxsw_sp_setup_tc_block_clsact(mlxsw_sp_port, f, false); 1045 case FLOW_BLOCK_BINDER_TYPE_RED_EARLY_DROP: 1046 return mlxsw_sp_setup_tc_block_qevent_early_drop(mlxsw_sp_port, f); 1047 case FLOW_BLOCK_BINDER_TYPE_RED_MARK: 1048 return mlxsw_sp_setup_tc_block_qevent_mark(mlxsw_sp_port, f); 1049 default: 1050 return -EOPNOTSUPP; 1051 } 1052 } 1053 1054 static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type, 1055 void *type_data) 1056 { 1057 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1058 1059 switch (type) { 1060 case TC_SETUP_BLOCK: 1061 return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data); 1062 case TC_SETUP_QDISC_RED: 1063 return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data); 1064 case TC_SETUP_QDISC_PRIO: 1065 return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data); 1066 case TC_SETUP_QDISC_ETS: 1067 return mlxsw_sp_setup_tc_ets(mlxsw_sp_port, type_data); 1068 case TC_SETUP_QDISC_TBF: 1069 return mlxsw_sp_setup_tc_tbf(mlxsw_sp_port, type_data); 1070 case TC_SETUP_QDISC_FIFO: 1071 return mlxsw_sp_setup_tc_fifo(mlxsw_sp_port, type_data); 1072 default: 1073 return -EOPNOTSUPP; 1074 } 1075 } 1076 1077 static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable) 1078 { 1079 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1080 1081 if (!enable) { 1082 if (mlxsw_sp_flow_block_rule_count(mlxsw_sp_port->ing_flow_block) || 1083 mlxsw_sp_flow_block_rule_count(mlxsw_sp_port->eg_flow_block)) { 1084 netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n"); 1085 return -EINVAL; 1086 } 1087 mlxsw_sp_flow_block_disable_inc(mlxsw_sp_port->ing_flow_block); 1088 mlxsw_sp_flow_block_disable_inc(mlxsw_sp_port->eg_flow_block); 1089 } else { 1090 mlxsw_sp_flow_block_disable_dec(mlxsw_sp_port->ing_flow_block); 1091 mlxsw_sp_flow_block_disable_dec(mlxsw_sp_port->eg_flow_block); 1092 } 1093 return 0; 1094 } 1095 1096 static int mlxsw_sp_feature_loopback(struct net_device *dev, bool enable) 1097 { 1098 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1099 char pplr_pl[MLXSW_REG_PPLR_LEN]; 1100 int err; 1101 1102 if (netif_running(dev)) 1103 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false); 1104 1105 mlxsw_reg_pplr_pack(pplr_pl, mlxsw_sp_port->local_port, enable); 1106 err = mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pplr), 1107 pplr_pl); 1108 1109 if (netif_running(dev)) 1110 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true); 1111 1112 return err; 1113 } 1114 1115 typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable); 1116 1117 static int mlxsw_sp_handle_feature(struct net_device *dev, 1118 netdev_features_t wanted_features, 1119 netdev_features_t feature, 1120 mlxsw_sp_feature_handler feature_handler) 1121 { 1122 netdev_features_t changes = wanted_features ^ dev->features; 1123 bool enable = !!(wanted_features & feature); 1124 int err; 1125 1126 if (!(changes & feature)) 1127 return 0; 1128 1129 err = feature_handler(dev, enable); 1130 if (err) { 1131 netdev_err(dev, "%s feature %pNF failed, err %d\n", 1132 enable ? "Enable" : "Disable", &feature, err); 1133 return err; 1134 } 1135 1136 if (enable) 1137 dev->features |= feature; 1138 else 1139 dev->features &= ~feature; 1140 1141 return 0; 1142 } 1143 static int mlxsw_sp_set_features(struct net_device *dev, 1144 netdev_features_t features) 1145 { 1146 netdev_features_t oper_features = dev->features; 1147 int err = 0; 1148 1149 err |= mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC, 1150 mlxsw_sp_feature_hw_tc); 1151 err |= mlxsw_sp_handle_feature(dev, features, NETIF_F_LOOPBACK, 1152 mlxsw_sp_feature_loopback); 1153 1154 if (err) { 1155 dev->features = oper_features; 1156 return -EINVAL; 1157 } 1158 1159 return 0; 1160 } 1161 1162 static int mlxsw_sp_port_hwtstamp_set(struct net_device *dev, 1163 struct kernel_hwtstamp_config *config, 1164 struct netlink_ext_ack *extack) 1165 { 1166 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1167 1168 return mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_set(mlxsw_sp_port, 1169 config, extack); 1170 } 1171 1172 static int mlxsw_sp_port_hwtstamp_get(struct net_device *dev, 1173 struct kernel_hwtstamp_config *config) 1174 { 1175 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1176 1177 return mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_get(mlxsw_sp_port, 1178 config); 1179 } 1180 1181 static inline void mlxsw_sp_port_ptp_clear(struct mlxsw_sp_port *mlxsw_sp_port) 1182 { 1183 struct kernel_hwtstamp_config config = {}; 1184 1185 mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_set(mlxsw_sp_port, &config, 1186 NULL); 1187 } 1188 1189 static const struct net_device_ops mlxsw_sp_port_netdev_ops = { 1190 .ndo_open = mlxsw_sp_port_open, 1191 .ndo_stop = mlxsw_sp_port_stop, 1192 .ndo_start_xmit = mlxsw_sp_port_xmit, 1193 .ndo_setup_tc = mlxsw_sp_setup_tc, 1194 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode, 1195 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address, 1196 .ndo_change_mtu = mlxsw_sp_port_change_mtu, 1197 .ndo_get_stats64 = mlxsw_sp_port_get_stats64, 1198 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats, 1199 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats, 1200 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid, 1201 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid, 1202 .ndo_set_features = mlxsw_sp_set_features, 1203 .ndo_hwtstamp_get = mlxsw_sp_port_hwtstamp_get, 1204 .ndo_hwtstamp_set = mlxsw_sp_port_hwtstamp_set, 1205 }; 1206 1207 static int 1208 mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port) 1209 { 1210 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1211 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper; 1212 const struct mlxsw_sp_port_type_speed_ops *ops; 1213 char ptys_pl[MLXSW_REG_PTYS_LEN]; 1214 u32 eth_proto_cap_masked; 1215 int err; 1216 1217 ops = mlxsw_sp->port_type_speed_ops; 1218 1219 /* Set advertised speeds to speeds supported by both the driver 1220 * and the device. 1221 */ 1222 ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port, 1223 0, false); 1224 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 1225 if (err) 1226 return err; 1227 1228 ops->reg_ptys_eth_unpack(mlxsw_sp, ptys_pl, ð_proto_cap, 1229 ð_proto_admin, ð_proto_oper); 1230 eth_proto_cap_masked = ops->ptys_proto_cap_masked_get(eth_proto_cap); 1231 ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port, 1232 eth_proto_cap_masked, 1233 mlxsw_sp_port->link.autoneg); 1234 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 1235 } 1236 1237 int mlxsw_sp_port_speed_get(struct mlxsw_sp_port *mlxsw_sp_port, u32 *speed) 1238 { 1239 const struct mlxsw_sp_port_type_speed_ops *port_type_speed_ops; 1240 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1241 char ptys_pl[MLXSW_REG_PTYS_LEN]; 1242 u32 eth_proto_oper; 1243 int err; 1244 1245 port_type_speed_ops = mlxsw_sp->port_type_speed_ops; 1246 port_type_speed_ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, 1247 mlxsw_sp_port->local_port, 0, 1248 false); 1249 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 1250 if (err) 1251 return err; 1252 port_type_speed_ops->reg_ptys_eth_unpack(mlxsw_sp, ptys_pl, NULL, NULL, 1253 ð_proto_oper); 1254 *speed = port_type_speed_ops->from_ptys_speed(mlxsw_sp, eth_proto_oper); 1255 return 0; 1256 } 1257 1258 int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port, 1259 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index, 1260 bool dwrr, u8 dwrr_weight) 1261 { 1262 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1263 char qeec_pl[MLXSW_REG_QEEC_LEN]; 1264 1265 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index, 1266 next_index); 1267 mlxsw_reg_qeec_de_set(qeec_pl, true); 1268 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr); 1269 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight); 1270 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl); 1271 } 1272 1273 int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port, 1274 enum mlxsw_reg_qeec_hr hr, u8 index, 1275 u8 next_index, u32 maxrate, u8 burst_size) 1276 { 1277 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1278 char qeec_pl[MLXSW_REG_QEEC_LEN]; 1279 1280 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index, 1281 next_index); 1282 mlxsw_reg_qeec_mase_set(qeec_pl, true); 1283 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate); 1284 mlxsw_reg_qeec_max_shaper_bs_set(qeec_pl, burst_size); 1285 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl); 1286 } 1287 1288 static int mlxsw_sp_port_min_bw_set(struct mlxsw_sp_port *mlxsw_sp_port, 1289 enum mlxsw_reg_qeec_hr hr, u8 index, 1290 u8 next_index, u32 minrate) 1291 { 1292 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1293 char qeec_pl[MLXSW_REG_QEEC_LEN]; 1294 1295 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index, 1296 next_index); 1297 mlxsw_reg_qeec_mise_set(qeec_pl, true); 1298 mlxsw_reg_qeec_min_shaper_rate_set(qeec_pl, minrate); 1299 1300 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl); 1301 } 1302 1303 int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port, 1304 u8 switch_prio, u8 tclass) 1305 { 1306 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1307 char qtct_pl[MLXSW_REG_QTCT_LEN]; 1308 1309 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio, 1310 tclass); 1311 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl); 1312 } 1313 1314 static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port) 1315 { 1316 int err, i; 1317 1318 /* Setup the elements hierarcy, so that each TC is linked to 1319 * one subgroup, which are all member in the same group. 1320 */ 1321 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 1322 MLXSW_REG_QEEC_HR_GROUP, 0, 0, false, 0); 1323 if (err) 1324 return err; 1325 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 1326 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 1327 MLXSW_REG_QEEC_HR_SUBGROUP, i, 1328 0, false, 0); 1329 if (err) 1330 return err; 1331 } 1332 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 1333 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 1334 MLXSW_REG_QEEC_HR_TC, i, i, 1335 false, 0); 1336 if (err) 1337 return err; 1338 1339 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 1340 MLXSW_REG_QEEC_HR_TC, 1341 i + 8, i, 1342 true, 100); 1343 if (err) 1344 return err; 1345 } 1346 1347 /* Make sure the max shaper is disabled in all hierarchies that support 1348 * it. Note that this disables ptps (PTP shaper), but that is intended 1349 * for the initial configuration. 1350 */ 1351 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 1352 MLXSW_REG_QEEC_HR_PORT, 0, 0, 1353 MLXSW_REG_QEEC_MAS_DIS, 0); 1354 if (err) 1355 return err; 1356 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 1357 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 1358 MLXSW_REG_QEEC_HR_SUBGROUP, 1359 i, 0, 1360 MLXSW_REG_QEEC_MAS_DIS, 0); 1361 if (err) 1362 return err; 1363 } 1364 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 1365 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 1366 MLXSW_REG_QEEC_HR_TC, 1367 i, i, 1368 MLXSW_REG_QEEC_MAS_DIS, 0); 1369 if (err) 1370 return err; 1371 1372 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 1373 MLXSW_REG_QEEC_HR_TC, 1374 i + 8, i, 1375 MLXSW_REG_QEEC_MAS_DIS, 0); 1376 if (err) 1377 return err; 1378 } 1379 1380 /* Configure the min shaper for multicast TCs. */ 1381 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 1382 err = mlxsw_sp_port_min_bw_set(mlxsw_sp_port, 1383 MLXSW_REG_QEEC_HR_TC, 1384 i + 8, i, 1385 MLXSW_REG_QEEC_MIS_MIN); 1386 if (err) 1387 return err; 1388 } 1389 1390 /* Map all priorities to traffic class 0. */ 1391 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 1392 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0); 1393 if (err) 1394 return err; 1395 } 1396 1397 return 0; 1398 } 1399 1400 static int mlxsw_sp_port_tc_mc_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, 1401 bool enable) 1402 { 1403 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1404 char qtctm_pl[MLXSW_REG_QTCTM_LEN]; 1405 1406 mlxsw_reg_qtctm_pack(qtctm_pl, mlxsw_sp_port->local_port, enable); 1407 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtctm), qtctm_pl); 1408 } 1409 1410 static int mlxsw_sp_port_overheat_init_val_set(struct mlxsw_sp_port *mlxsw_sp_port) 1411 { 1412 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1413 u8 slot_index = mlxsw_sp_port->mapping.slot_index; 1414 u8 module = mlxsw_sp_port->mapping.module; 1415 u64 overheat_counter; 1416 int err; 1417 1418 err = mlxsw_env_module_overheat_counter_get(mlxsw_sp->core, slot_index, 1419 module, &overheat_counter); 1420 if (err) 1421 return err; 1422 1423 mlxsw_sp_port->module_overheat_initial_val = overheat_counter; 1424 return 0; 1425 } 1426 1427 int 1428 mlxsw_sp_port_vlan_classification_set(struct mlxsw_sp_port *mlxsw_sp_port, 1429 bool is_8021ad_tagged, 1430 bool is_8021q_tagged) 1431 { 1432 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1433 char spvc_pl[MLXSW_REG_SPVC_LEN]; 1434 1435 mlxsw_reg_spvc_pack(spvc_pl, mlxsw_sp_port->local_port, 1436 is_8021ad_tagged, is_8021q_tagged); 1437 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvc), spvc_pl); 1438 } 1439 1440 static int mlxsw_sp_port_label_info_get(struct mlxsw_sp *mlxsw_sp, 1441 u16 local_port, u8 *port_number, 1442 u8 *split_port_subnumber, 1443 u8 *slot_index) 1444 { 1445 char pllp_pl[MLXSW_REG_PLLP_LEN]; 1446 int err; 1447 1448 mlxsw_reg_pllp_pack(pllp_pl, local_port); 1449 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pllp), pllp_pl); 1450 if (err) 1451 return err; 1452 mlxsw_reg_pllp_unpack(pllp_pl, port_number, 1453 split_port_subnumber, slot_index); 1454 return 0; 1455 } 1456 1457 static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u16 local_port, 1458 bool split, 1459 struct mlxsw_sp_port_mapping *port_mapping) 1460 { 1461 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 1462 struct mlxsw_sp_port *mlxsw_sp_port; 1463 u32 lanes = port_mapping->width; 1464 u8 split_port_subnumber; 1465 struct net_device *dev; 1466 u8 port_number; 1467 u8 slot_index; 1468 bool splittable; 1469 int err; 1470 1471 err = mlxsw_sp_port_module_map(mlxsw_sp, local_port, port_mapping); 1472 if (err) { 1473 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n", 1474 local_port); 1475 return err; 1476 } 1477 1478 err = mlxsw_sp_port_swid_set(mlxsw_sp, local_port, 0); 1479 if (err) { 1480 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n", 1481 local_port); 1482 goto err_port_swid_set; 1483 } 1484 1485 err = mlxsw_sp_port_label_info_get(mlxsw_sp, local_port, &port_number, 1486 &split_port_subnumber, &slot_index); 1487 if (err) { 1488 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to get port label information\n", 1489 local_port); 1490 goto err_port_label_info_get; 1491 } 1492 1493 splittable = lanes > 1 && !split; 1494 err = mlxsw_core_port_init(mlxsw_sp->core, local_port, slot_index, 1495 port_number, split, split_port_subnumber, 1496 splittable, lanes, mlxsw_sp->base_mac, 1497 sizeof(mlxsw_sp->base_mac)); 1498 if (err) { 1499 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n", 1500 local_port); 1501 goto err_core_port_init; 1502 } 1503 1504 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port)); 1505 if (!dev) { 1506 err = -ENOMEM; 1507 goto err_alloc_etherdev; 1508 } 1509 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev); 1510 dev_net_set(dev, mlxsw_sp_net(mlxsw_sp)); 1511 mlxsw_sp_port = netdev_priv(dev); 1512 mlxsw_core_port_netdev_link(mlxsw_sp->core, local_port, 1513 mlxsw_sp_port, dev); 1514 mlxsw_sp_port->dev = dev; 1515 mlxsw_sp_port->mlxsw_sp = mlxsw_sp; 1516 mlxsw_sp_port->local_port = local_port; 1517 mlxsw_sp_port->pvid = MLXSW_SP_DEFAULT_VID; 1518 mlxsw_sp_port->split = split; 1519 mlxsw_sp_port->mapping = *port_mapping; 1520 mlxsw_sp_port->link.autoneg = 1; 1521 INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list); 1522 1523 mlxsw_sp_port->pcpu_stats = 1524 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats); 1525 if (!mlxsw_sp_port->pcpu_stats) { 1526 err = -ENOMEM; 1527 goto err_alloc_stats; 1528 } 1529 1530 INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw, 1531 &update_stats_cache); 1532 1533 dev->netdev_ops = &mlxsw_sp_port_netdev_ops; 1534 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops; 1535 1536 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port); 1537 if (err) { 1538 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n", 1539 mlxsw_sp_port->local_port); 1540 goto err_dev_addr_init; 1541 } 1542 1543 netif_carrier_off(dev); 1544 1545 dev->features |= NETIF_F_SG | NETIF_F_HW_VLAN_CTAG_FILTER | 1546 NETIF_F_HW_TC | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 1547 dev->hw_features |= NETIF_F_HW_TC | NETIF_F_LOOPBACK | 1548 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 1549 dev->vlan_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 1550 dev->lltx = true; 1551 dev->netns_immutable = true; 1552 1553 dev->min_mtu = ETH_MIN_MTU; 1554 dev->max_mtu = MLXSW_PORT_MAX_MTU - MLXSW_PORT_ETH_FRAME_HDR; 1555 1556 /* Each packet needs to have a Tx header (metadata) on top all other 1557 * headers. 1558 */ 1559 dev->needed_headroom = MLXSW_TXHDR_LEN; 1560 1561 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port); 1562 if (err) { 1563 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n", 1564 mlxsw_sp_port->local_port); 1565 goto err_port_system_port_mapping_set; 1566 } 1567 1568 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port); 1569 if (err) { 1570 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n", 1571 mlxsw_sp_port->local_port); 1572 goto err_port_speed_by_width_set; 1573 } 1574 1575 err = mlxsw_sp->port_type_speed_ops->ptys_max_speed(mlxsw_sp_port, 1576 &mlxsw_sp_port->max_speed); 1577 if (err) { 1578 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to get maximum speed\n", 1579 mlxsw_sp_port->local_port); 1580 goto err_max_speed_get; 1581 } 1582 1583 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN); 1584 if (err) { 1585 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n", 1586 mlxsw_sp_port->local_port); 1587 goto err_port_mtu_set; 1588 } 1589 1590 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false); 1591 if (err) 1592 goto err_port_admin_status_set; 1593 1594 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port); 1595 if (err) { 1596 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n", 1597 mlxsw_sp_port->local_port); 1598 goto err_port_buffers_init; 1599 } 1600 1601 err = mlxsw_sp_port_ets_init(mlxsw_sp_port); 1602 if (err) { 1603 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n", 1604 mlxsw_sp_port->local_port); 1605 goto err_port_ets_init; 1606 } 1607 1608 err = mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, true); 1609 if (err) { 1610 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC MC mode\n", 1611 mlxsw_sp_port->local_port); 1612 goto err_port_tc_mc_mode; 1613 } 1614 1615 /* ETS and buffers must be initialized before DCB. */ 1616 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port); 1617 if (err) { 1618 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n", 1619 mlxsw_sp_port->local_port); 1620 goto err_port_dcb_init; 1621 } 1622 1623 err = mlxsw_sp_port_fids_init(mlxsw_sp_port); 1624 if (err) { 1625 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n", 1626 mlxsw_sp_port->local_port); 1627 goto err_port_fids_init; 1628 } 1629 1630 err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port); 1631 if (err) { 1632 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n", 1633 mlxsw_sp_port->local_port); 1634 goto err_port_qdiscs_init; 1635 } 1636 1637 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 0, VLAN_N_VID - 1, false, 1638 false); 1639 if (err) { 1640 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to clear VLAN filter\n", 1641 mlxsw_sp_port->local_port); 1642 goto err_port_vlan_clear; 1643 } 1644 1645 err = mlxsw_sp_port_nve_init(mlxsw_sp_port); 1646 if (err) { 1647 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize NVE\n", 1648 mlxsw_sp_port->local_port); 1649 goto err_port_nve_init; 1650 } 1651 1652 err = mlxsw_sp_port_pvid_set(mlxsw_sp_port, MLXSW_SP_DEFAULT_VID, 1653 ETH_P_8021Q); 1654 if (err) { 1655 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set PVID\n", 1656 mlxsw_sp_port->local_port); 1657 goto err_port_pvid_set; 1658 } 1659 1660 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_create(mlxsw_sp_port, 1661 MLXSW_SP_DEFAULT_VID); 1662 if (IS_ERR(mlxsw_sp_port_vlan)) { 1663 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n", 1664 mlxsw_sp_port->local_port); 1665 err = PTR_ERR(mlxsw_sp_port_vlan); 1666 goto err_port_vlan_create; 1667 } 1668 mlxsw_sp_port->default_vlan = mlxsw_sp_port_vlan; 1669 1670 /* Set SPVC.et0=true and SPVC.et1=false to make the local port to treat 1671 * only packets with 802.1q header as tagged packets. 1672 */ 1673 err = mlxsw_sp_port_vlan_classification_set(mlxsw_sp_port, false, true); 1674 if (err) { 1675 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set default VLAN classification\n", 1676 local_port); 1677 goto err_port_vlan_classification_set; 1678 } 1679 1680 INIT_DELAYED_WORK(&mlxsw_sp_port->ptp.shaper_dw, 1681 mlxsw_sp->ptp_ops->shaper_work); 1682 1683 mlxsw_sp->ports[local_port] = mlxsw_sp_port; 1684 1685 err = mlxsw_sp_port_overheat_init_val_set(mlxsw_sp_port); 1686 if (err) { 1687 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set overheat initial value\n", 1688 mlxsw_sp_port->local_port); 1689 goto err_port_overheat_init_val_set; 1690 } 1691 1692 err = register_netdev(dev); 1693 if (err) { 1694 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n", 1695 mlxsw_sp_port->local_port); 1696 goto err_register_netdev; 1697 } 1698 1699 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0); 1700 return 0; 1701 1702 err_register_netdev: 1703 err_port_overheat_init_val_set: 1704 mlxsw_sp_port_vlan_classification_set(mlxsw_sp_port, true, true); 1705 err_port_vlan_classification_set: 1706 mlxsw_sp->ports[local_port] = NULL; 1707 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan); 1708 err_port_vlan_create: 1709 err_port_pvid_set: 1710 mlxsw_sp_port_nve_fini(mlxsw_sp_port); 1711 err_port_nve_init: 1712 err_port_vlan_clear: 1713 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port); 1714 err_port_qdiscs_init: 1715 mlxsw_sp_port_fids_fini(mlxsw_sp_port); 1716 err_port_fids_init: 1717 mlxsw_sp_port_dcb_fini(mlxsw_sp_port); 1718 err_port_dcb_init: 1719 mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false); 1720 err_port_tc_mc_mode: 1721 err_port_ets_init: 1722 mlxsw_sp_port_buffers_fini(mlxsw_sp_port); 1723 err_port_buffers_init: 1724 err_port_admin_status_set: 1725 err_port_mtu_set: 1726 err_max_speed_get: 1727 err_port_speed_by_width_set: 1728 err_port_system_port_mapping_set: 1729 err_dev_addr_init: 1730 free_percpu(mlxsw_sp_port->pcpu_stats); 1731 err_alloc_stats: 1732 free_netdev(dev); 1733 err_alloc_etherdev: 1734 mlxsw_core_port_fini(mlxsw_sp->core, local_port); 1735 err_core_port_init: 1736 err_port_label_info_get: 1737 mlxsw_sp_port_swid_set(mlxsw_sp, local_port, 1738 MLXSW_PORT_SWID_DISABLED_PORT); 1739 err_port_swid_set: 1740 mlxsw_sp_port_module_unmap(mlxsw_sp, local_port, 1741 port_mapping->slot_index, 1742 port_mapping->module); 1743 return err; 1744 } 1745 1746 static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u16 local_port) 1747 { 1748 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port]; 1749 u8 slot_index = mlxsw_sp_port->mapping.slot_index; 1750 u8 module = mlxsw_sp_port->mapping.module; 1751 1752 cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw); 1753 cancel_delayed_work_sync(&mlxsw_sp_port->ptp.shaper_dw); 1754 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */ 1755 mlxsw_sp_port_ptp_clear(mlxsw_sp_port); 1756 mlxsw_sp_port_vlan_classification_set(mlxsw_sp_port, true, true); 1757 mlxsw_sp->ports[local_port] = NULL; 1758 mlxsw_sp_port_vlan_flush(mlxsw_sp_port, true); 1759 mlxsw_sp_port_nve_fini(mlxsw_sp_port); 1760 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port); 1761 mlxsw_sp_port_fids_fini(mlxsw_sp_port); 1762 mlxsw_sp_port_dcb_fini(mlxsw_sp_port); 1763 mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false); 1764 mlxsw_sp_port_buffers_fini(mlxsw_sp_port); 1765 free_percpu(mlxsw_sp_port->pcpu_stats); 1766 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list)); 1767 free_netdev(mlxsw_sp_port->dev); 1768 mlxsw_core_port_fini(mlxsw_sp->core, local_port); 1769 mlxsw_sp_port_swid_set(mlxsw_sp, local_port, 1770 MLXSW_PORT_SWID_DISABLED_PORT); 1771 mlxsw_sp_port_module_unmap(mlxsw_sp, local_port, slot_index, module); 1772 } 1773 1774 static int mlxsw_sp_cpu_port_create(struct mlxsw_sp *mlxsw_sp) 1775 { 1776 struct mlxsw_sp_port *mlxsw_sp_port; 1777 int err; 1778 1779 mlxsw_sp_port = kzalloc(sizeof(*mlxsw_sp_port), GFP_KERNEL); 1780 if (!mlxsw_sp_port) 1781 return -ENOMEM; 1782 1783 mlxsw_sp_port->mlxsw_sp = mlxsw_sp; 1784 mlxsw_sp_port->local_port = MLXSW_PORT_CPU_PORT; 1785 1786 err = mlxsw_core_cpu_port_init(mlxsw_sp->core, 1787 mlxsw_sp_port, 1788 mlxsw_sp->base_mac, 1789 sizeof(mlxsw_sp->base_mac)); 1790 if (err) { 1791 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize core CPU port\n"); 1792 goto err_core_cpu_port_init; 1793 } 1794 1795 mlxsw_sp->ports[MLXSW_PORT_CPU_PORT] = mlxsw_sp_port; 1796 return 0; 1797 1798 err_core_cpu_port_init: 1799 kfree(mlxsw_sp_port); 1800 return err; 1801 } 1802 1803 static void mlxsw_sp_cpu_port_remove(struct mlxsw_sp *mlxsw_sp) 1804 { 1805 struct mlxsw_sp_port *mlxsw_sp_port = 1806 mlxsw_sp->ports[MLXSW_PORT_CPU_PORT]; 1807 1808 mlxsw_core_cpu_port_fini(mlxsw_sp->core); 1809 mlxsw_sp->ports[MLXSW_PORT_CPU_PORT] = NULL; 1810 kfree(mlxsw_sp_port); 1811 } 1812 1813 static bool mlxsw_sp_local_port_valid(u16 local_port) 1814 { 1815 return local_port != MLXSW_PORT_CPU_PORT; 1816 } 1817 1818 static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u16 local_port) 1819 { 1820 if (!mlxsw_sp_local_port_valid(local_port)) 1821 return false; 1822 return mlxsw_sp->ports[local_port] != NULL; 1823 } 1824 1825 static int mlxsw_sp_port_mapping_event_set(struct mlxsw_sp *mlxsw_sp, 1826 u16 local_port, bool enable) 1827 { 1828 char pmecr_pl[MLXSW_REG_PMECR_LEN]; 1829 1830 mlxsw_reg_pmecr_pack(pmecr_pl, local_port, 1831 enable ? MLXSW_REG_PMECR_E_GENERATE_EVENT : 1832 MLXSW_REG_PMECR_E_DO_NOT_GENERATE_EVENT); 1833 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmecr), pmecr_pl); 1834 } 1835 1836 struct mlxsw_sp_port_mapping_event { 1837 struct list_head list; 1838 char pmlp_pl[MLXSW_REG_PMLP_LEN]; 1839 }; 1840 1841 static void mlxsw_sp_port_mapping_events_work(struct work_struct *work) 1842 { 1843 struct mlxsw_sp_port_mapping_event *event, *next_event; 1844 struct mlxsw_sp_port_mapping_events *events; 1845 struct mlxsw_sp_port_mapping port_mapping; 1846 struct mlxsw_sp *mlxsw_sp; 1847 struct devlink *devlink; 1848 LIST_HEAD(event_queue); 1849 u16 local_port; 1850 int err; 1851 1852 events = container_of(work, struct mlxsw_sp_port_mapping_events, work); 1853 mlxsw_sp = container_of(events, struct mlxsw_sp, port_mapping_events); 1854 devlink = priv_to_devlink(mlxsw_sp->core); 1855 1856 spin_lock_bh(&events->queue_lock); 1857 list_splice_init(&events->queue, &event_queue); 1858 spin_unlock_bh(&events->queue_lock); 1859 1860 list_for_each_entry_safe(event, next_event, &event_queue, list) { 1861 local_port = mlxsw_reg_pmlp_local_port_get(event->pmlp_pl); 1862 err = mlxsw_sp_port_module_info_parse(mlxsw_sp, local_port, 1863 event->pmlp_pl, &port_mapping); 1864 if (err) 1865 goto out; 1866 1867 if (WARN_ON_ONCE(!port_mapping.width)) 1868 goto out; 1869 1870 devl_lock(devlink); 1871 1872 if (!mlxsw_sp_port_created(mlxsw_sp, local_port)) 1873 mlxsw_sp_port_create(mlxsw_sp, local_port, 1874 false, &port_mapping); 1875 else 1876 WARN_ON_ONCE(1); 1877 1878 devl_unlock(devlink); 1879 1880 mlxsw_sp->port_mapping[local_port] = port_mapping; 1881 1882 out: 1883 kfree(event); 1884 } 1885 } 1886 1887 static void 1888 mlxsw_sp_port_mapping_listener_func(const struct mlxsw_reg_info *reg, 1889 char *pmlp_pl, void *priv) 1890 { 1891 struct mlxsw_sp_port_mapping_events *events; 1892 struct mlxsw_sp_port_mapping_event *event; 1893 struct mlxsw_sp *mlxsw_sp = priv; 1894 u16 local_port; 1895 1896 local_port = mlxsw_reg_pmlp_local_port_get(pmlp_pl); 1897 if (WARN_ON_ONCE(!mlxsw_sp_local_port_is_valid(mlxsw_sp, local_port))) 1898 return; 1899 1900 events = &mlxsw_sp->port_mapping_events; 1901 event = kmalloc(sizeof(*event), GFP_ATOMIC); 1902 if (!event) 1903 return; 1904 memcpy(event->pmlp_pl, pmlp_pl, sizeof(event->pmlp_pl)); 1905 spin_lock(&events->queue_lock); 1906 list_add_tail(&event->list, &events->queue); 1907 spin_unlock(&events->queue_lock); 1908 mlxsw_core_schedule_work(&events->work); 1909 } 1910 1911 static void 1912 __mlxsw_sp_port_mapping_events_cancel(struct mlxsw_sp *mlxsw_sp) 1913 { 1914 struct mlxsw_sp_port_mapping_event *event, *next_event; 1915 struct mlxsw_sp_port_mapping_events *events; 1916 1917 events = &mlxsw_sp->port_mapping_events; 1918 1919 /* Caller needs to make sure that no new event is going to appear. */ 1920 cancel_work_sync(&events->work); 1921 list_for_each_entry_safe(event, next_event, &events->queue, list) { 1922 list_del(&event->list); 1923 kfree(event); 1924 } 1925 } 1926 1927 static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp) 1928 { 1929 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core); 1930 int i; 1931 1932 for (i = 1; i < max_ports; i++) 1933 mlxsw_sp_port_mapping_event_set(mlxsw_sp, i, false); 1934 /* Make sure all scheduled events are processed */ 1935 __mlxsw_sp_port_mapping_events_cancel(mlxsw_sp); 1936 1937 for (i = 1; i < max_ports; i++) 1938 if (mlxsw_sp_port_created(mlxsw_sp, i)) 1939 mlxsw_sp_port_remove(mlxsw_sp, i); 1940 mlxsw_sp_cpu_port_remove(mlxsw_sp); 1941 kfree(mlxsw_sp->ports); 1942 mlxsw_sp->ports = NULL; 1943 } 1944 1945 static void 1946 mlxsw_sp_ports_remove_selected(struct mlxsw_core *mlxsw_core, 1947 bool (*selector)(void *priv, u16 local_port), 1948 void *priv) 1949 { 1950 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 1951 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_core); 1952 int i; 1953 1954 for (i = 1; i < max_ports; i++) 1955 if (mlxsw_sp_port_created(mlxsw_sp, i) && selector(priv, i)) 1956 mlxsw_sp_port_remove(mlxsw_sp, i); 1957 } 1958 1959 static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp) 1960 { 1961 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core); 1962 struct mlxsw_sp_port_mapping_events *events; 1963 struct mlxsw_sp_port_mapping *port_mapping; 1964 size_t alloc_size; 1965 int i; 1966 int err; 1967 1968 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports; 1969 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL); 1970 if (!mlxsw_sp->ports) 1971 return -ENOMEM; 1972 1973 events = &mlxsw_sp->port_mapping_events; 1974 INIT_LIST_HEAD(&events->queue); 1975 spin_lock_init(&events->queue_lock); 1976 INIT_WORK(&events->work, mlxsw_sp_port_mapping_events_work); 1977 1978 for (i = 1; i < max_ports; i++) { 1979 err = mlxsw_sp_port_mapping_event_set(mlxsw_sp, i, true); 1980 if (err) 1981 goto err_event_enable; 1982 } 1983 1984 err = mlxsw_sp_cpu_port_create(mlxsw_sp); 1985 if (err) 1986 goto err_cpu_port_create; 1987 1988 for (i = 1; i < max_ports; i++) { 1989 port_mapping = &mlxsw_sp->port_mapping[i]; 1990 if (!port_mapping->width) 1991 continue; 1992 err = mlxsw_sp_port_create(mlxsw_sp, i, false, port_mapping); 1993 if (err) 1994 goto err_port_create; 1995 } 1996 return 0; 1997 1998 err_port_create: 1999 for (i--; i >= 1; i--) 2000 if (mlxsw_sp_port_created(mlxsw_sp, i)) 2001 mlxsw_sp_port_remove(mlxsw_sp, i); 2002 i = max_ports; 2003 mlxsw_sp_cpu_port_remove(mlxsw_sp); 2004 err_cpu_port_create: 2005 err_event_enable: 2006 for (i--; i >= 1; i--) 2007 mlxsw_sp_port_mapping_event_set(mlxsw_sp, i, false); 2008 /* Make sure all scheduled events are processed */ 2009 __mlxsw_sp_port_mapping_events_cancel(mlxsw_sp); 2010 kfree(mlxsw_sp->ports); 2011 mlxsw_sp->ports = NULL; 2012 return err; 2013 } 2014 2015 static int mlxsw_sp_port_module_info_init(struct mlxsw_sp *mlxsw_sp) 2016 { 2017 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core); 2018 struct mlxsw_sp_port_mapping *port_mapping; 2019 int i; 2020 int err; 2021 2022 mlxsw_sp->port_mapping = kcalloc(max_ports, 2023 sizeof(struct mlxsw_sp_port_mapping), 2024 GFP_KERNEL); 2025 if (!mlxsw_sp->port_mapping) 2026 return -ENOMEM; 2027 2028 for (i = 1; i < max_ports; i++) { 2029 port_mapping = &mlxsw_sp->port_mapping[i]; 2030 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, port_mapping); 2031 if (err) 2032 goto err_port_module_info_get; 2033 } 2034 return 0; 2035 2036 err_port_module_info_get: 2037 kfree(mlxsw_sp->port_mapping); 2038 return err; 2039 } 2040 2041 static void mlxsw_sp_port_module_info_fini(struct mlxsw_sp *mlxsw_sp) 2042 { 2043 kfree(mlxsw_sp->port_mapping); 2044 } 2045 2046 static int 2047 mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, 2048 struct mlxsw_sp_port_mapping *port_mapping, 2049 unsigned int count, const char *pmtdb_pl) 2050 { 2051 struct mlxsw_sp_port_mapping split_port_mapping; 2052 int err, i; 2053 2054 split_port_mapping = *port_mapping; 2055 split_port_mapping.width /= count; 2056 for (i = 0; i < count; i++) { 2057 u16 s_local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i); 2058 2059 if (!mlxsw_sp_local_port_valid(s_local_port)) 2060 continue; 2061 2062 err = mlxsw_sp_port_create(mlxsw_sp, s_local_port, 2063 true, &split_port_mapping); 2064 if (err) 2065 goto err_port_create; 2066 split_port_mapping.lane += split_port_mapping.width; 2067 } 2068 2069 return 0; 2070 2071 err_port_create: 2072 for (i--; i >= 0; i--) { 2073 u16 s_local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i); 2074 2075 if (mlxsw_sp_port_created(mlxsw_sp, s_local_port)) 2076 mlxsw_sp_port_remove(mlxsw_sp, s_local_port); 2077 } 2078 return err; 2079 } 2080 2081 static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp, 2082 unsigned int count, 2083 const char *pmtdb_pl) 2084 { 2085 struct mlxsw_sp_port_mapping *port_mapping; 2086 int i; 2087 2088 /* Go over original unsplit ports in the gap and recreate them. */ 2089 for (i = 0; i < count; i++) { 2090 u16 local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i); 2091 2092 port_mapping = &mlxsw_sp->port_mapping[local_port]; 2093 if (!port_mapping->width || !mlxsw_sp_local_port_valid(local_port)) 2094 continue; 2095 mlxsw_sp_port_create(mlxsw_sp, local_port, 2096 false, port_mapping); 2097 } 2098 } 2099 2100 static struct mlxsw_sp_port * 2101 mlxsw_sp_port_get_by_local_port(struct mlxsw_sp *mlxsw_sp, u16 local_port) 2102 { 2103 if (mlxsw_sp->ports && mlxsw_sp->ports[local_port]) 2104 return mlxsw_sp->ports[local_port]; 2105 return NULL; 2106 } 2107 2108 static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u16 local_port, 2109 unsigned int count, 2110 struct netlink_ext_ack *extack) 2111 { 2112 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 2113 struct mlxsw_sp_port_mapping port_mapping; 2114 struct mlxsw_sp_port *mlxsw_sp_port; 2115 enum mlxsw_reg_pmtdb_status status; 2116 char pmtdb_pl[MLXSW_REG_PMTDB_LEN]; 2117 int i; 2118 int err; 2119 2120 mlxsw_sp_port = mlxsw_sp_port_get_by_local_port(mlxsw_sp, local_port); 2121 if (!mlxsw_sp_port) { 2122 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n", 2123 local_port); 2124 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist"); 2125 return -EINVAL; 2126 } 2127 2128 if (mlxsw_sp_port->split) { 2129 NL_SET_ERR_MSG_MOD(extack, "Port is already split"); 2130 return -EINVAL; 2131 } 2132 2133 mlxsw_reg_pmtdb_pack(pmtdb_pl, mlxsw_sp_port->mapping.slot_index, 2134 mlxsw_sp_port->mapping.module, 2135 mlxsw_sp_port->mapping.module_width / count, 2136 count); 2137 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(pmtdb), pmtdb_pl); 2138 if (err) { 2139 NL_SET_ERR_MSG_MOD(extack, "Failed to query split info"); 2140 return err; 2141 } 2142 2143 status = mlxsw_reg_pmtdb_status_get(pmtdb_pl); 2144 if (status != MLXSW_REG_PMTDB_STATUS_SUCCESS) { 2145 NL_SET_ERR_MSG_MOD(extack, "Unsupported split configuration"); 2146 return -EINVAL; 2147 } 2148 2149 port_mapping = mlxsw_sp_port->mapping; 2150 2151 for (i = 0; i < count; i++) { 2152 u16 s_local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i); 2153 2154 if (mlxsw_sp_port_created(mlxsw_sp, s_local_port)) 2155 mlxsw_sp_port_remove(mlxsw_sp, s_local_port); 2156 } 2157 2158 err = mlxsw_sp_port_split_create(mlxsw_sp, &port_mapping, 2159 count, pmtdb_pl); 2160 if (err) { 2161 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n"); 2162 goto err_port_split_create; 2163 } 2164 2165 return 0; 2166 2167 err_port_split_create: 2168 mlxsw_sp_port_unsplit_create(mlxsw_sp, count, pmtdb_pl); 2169 2170 return err; 2171 } 2172 2173 static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u16 local_port, 2174 struct netlink_ext_ack *extack) 2175 { 2176 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 2177 struct mlxsw_sp_port *mlxsw_sp_port; 2178 char pmtdb_pl[MLXSW_REG_PMTDB_LEN]; 2179 unsigned int count; 2180 int i; 2181 int err; 2182 2183 mlxsw_sp_port = mlxsw_sp_port_get_by_local_port(mlxsw_sp, local_port); 2184 if (!mlxsw_sp_port) { 2185 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n", 2186 local_port); 2187 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist"); 2188 return -EINVAL; 2189 } 2190 2191 if (!mlxsw_sp_port->split) { 2192 NL_SET_ERR_MSG_MOD(extack, "Port was not split"); 2193 return -EINVAL; 2194 } 2195 2196 count = mlxsw_sp_port->mapping.module_width / 2197 mlxsw_sp_port->mapping.width; 2198 2199 mlxsw_reg_pmtdb_pack(pmtdb_pl, mlxsw_sp_port->mapping.slot_index, 2200 mlxsw_sp_port->mapping.module, 2201 mlxsw_sp_port->mapping.module_width / count, 2202 count); 2203 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(pmtdb), pmtdb_pl); 2204 if (err) { 2205 NL_SET_ERR_MSG_MOD(extack, "Failed to query split info"); 2206 return err; 2207 } 2208 2209 for (i = 0; i < count; i++) { 2210 u16 s_local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i); 2211 2212 if (mlxsw_sp_port_created(mlxsw_sp, s_local_port)) 2213 mlxsw_sp_port_remove(mlxsw_sp, s_local_port); 2214 } 2215 2216 mlxsw_sp_port_unsplit_create(mlxsw_sp, count, pmtdb_pl); 2217 2218 return 0; 2219 } 2220 2221 static void 2222 mlxsw_sp_port_down_wipe_counters(struct mlxsw_sp_port *mlxsw_sp_port) 2223 { 2224 int i; 2225 2226 for (i = 0; i < TC_MAX_QUEUE; i++) 2227 mlxsw_sp_port->periodic_hw_stats.xstats.backlog[i] = 0; 2228 } 2229 2230 static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg, 2231 char *pude_pl, void *priv) 2232 { 2233 struct mlxsw_sp *mlxsw_sp = priv; 2234 struct mlxsw_sp_port *mlxsw_sp_port; 2235 enum mlxsw_reg_pude_oper_status status; 2236 u16 local_port; 2237 2238 local_port = mlxsw_reg_pude_local_port_get(pude_pl); 2239 2240 if (WARN_ON_ONCE(!mlxsw_sp_local_port_is_valid(mlxsw_sp, local_port))) 2241 return; 2242 mlxsw_sp_port = mlxsw_sp->ports[local_port]; 2243 if (!mlxsw_sp_port) 2244 return; 2245 2246 status = mlxsw_reg_pude_oper_status_get(pude_pl); 2247 if (status == MLXSW_PORT_OPER_STATUS_UP) { 2248 netdev_info(mlxsw_sp_port->dev, "link up\n"); 2249 netif_carrier_on(mlxsw_sp_port->dev); 2250 mlxsw_core_schedule_dw(&mlxsw_sp_port->ptp.shaper_dw, 0); 2251 } else { 2252 netdev_info(mlxsw_sp_port->dev, "link down\n"); 2253 netif_carrier_off(mlxsw_sp_port->dev); 2254 mlxsw_sp_port_down_wipe_counters(mlxsw_sp_port); 2255 } 2256 } 2257 2258 static void mlxsw_sp1_ptp_fifo_event_func(struct mlxsw_sp *mlxsw_sp, 2259 char *mtpptr_pl, bool ingress) 2260 { 2261 u16 local_port; 2262 u8 num_rec; 2263 int i; 2264 2265 local_port = mlxsw_reg_mtpptr_local_port_get(mtpptr_pl); 2266 num_rec = mlxsw_reg_mtpptr_num_rec_get(mtpptr_pl); 2267 for (i = 0; i < num_rec; i++) { 2268 u8 domain_number; 2269 u8 message_type; 2270 u16 sequence_id; 2271 u64 timestamp; 2272 2273 mlxsw_reg_mtpptr_unpack(mtpptr_pl, i, &message_type, 2274 &domain_number, &sequence_id, 2275 ×tamp); 2276 mlxsw_sp1_ptp_got_timestamp(mlxsw_sp, ingress, local_port, 2277 message_type, domain_number, 2278 sequence_id, timestamp); 2279 } 2280 } 2281 2282 static void mlxsw_sp1_ptp_ing_fifo_event_func(const struct mlxsw_reg_info *reg, 2283 char *mtpptr_pl, void *priv) 2284 { 2285 struct mlxsw_sp *mlxsw_sp = priv; 2286 2287 mlxsw_sp1_ptp_fifo_event_func(mlxsw_sp, mtpptr_pl, true); 2288 } 2289 2290 static void mlxsw_sp1_ptp_egr_fifo_event_func(const struct mlxsw_reg_info *reg, 2291 char *mtpptr_pl, void *priv) 2292 { 2293 struct mlxsw_sp *mlxsw_sp = priv; 2294 2295 mlxsw_sp1_ptp_fifo_event_func(mlxsw_sp, mtpptr_pl, false); 2296 } 2297 2298 void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb, 2299 u16 local_port, void *priv) 2300 { 2301 struct mlxsw_sp *mlxsw_sp = priv; 2302 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port]; 2303 struct mlxsw_sp_port_pcpu_stats *pcpu_stats; 2304 2305 if (unlikely(!mlxsw_sp_port)) { 2306 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n", 2307 local_port); 2308 return; 2309 } 2310 2311 skb->dev = mlxsw_sp_port->dev; 2312 2313 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats); 2314 u64_stats_update_begin(&pcpu_stats->syncp); 2315 pcpu_stats->rx_packets++; 2316 pcpu_stats->rx_bytes += skb->len; 2317 u64_stats_update_end(&pcpu_stats->syncp); 2318 2319 skb->protocol = eth_type_trans(skb, skb->dev); 2320 napi_gro_receive(mlxsw_skb_cb(skb)->rx_md_info.napi, skb); 2321 } 2322 2323 static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u16 local_port, 2324 void *priv) 2325 { 2326 skb->offload_fwd_mark = 1; 2327 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv); 2328 } 2329 2330 static void mlxsw_sp_rx_listener_l3_mark_func(struct sk_buff *skb, 2331 u16 local_port, void *priv) 2332 { 2333 skb->offload_l3_fwd_mark = 1; 2334 skb->offload_fwd_mark = 1; 2335 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv); 2336 } 2337 2338 void mlxsw_sp_ptp_receive(struct mlxsw_sp *mlxsw_sp, struct sk_buff *skb, 2339 u16 local_port) 2340 { 2341 mlxsw_sp->ptp_ops->receive(mlxsw_sp, skb, local_port); 2342 } 2343 2344 #define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \ 2345 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \ 2346 _is_ctrl, SP_##_trap_group, DISCARD) 2347 2348 #define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \ 2349 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \ 2350 _is_ctrl, SP_##_trap_group, DISCARD) 2351 2352 #define MLXSW_SP_RXL_L3_MARK(_trap_id, _action, _trap_group, _is_ctrl) \ 2353 MLXSW_RXL(mlxsw_sp_rx_listener_l3_mark_func, _trap_id, _action, \ 2354 _is_ctrl, SP_##_trap_group, DISCARD) 2355 2356 #define MLXSW_SP_EVENTL(_func, _trap_id) \ 2357 MLXSW_EVENTL(_func, _trap_id, SP_EVENT) 2358 2359 static const struct mlxsw_listener mlxsw_sp_listener[] = { 2360 /* Events */ 2361 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE), 2362 /* L2 traps */ 2363 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, FID_MISS, false), 2364 /* L3 traps */ 2365 MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP, 2366 false), 2367 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false), 2368 MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, 2369 false), 2370 MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_SIP_CLASS_E, FORWARD, 2371 ROUTER_EXP, false), 2372 MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_MC_DMAC, FORWARD, 2373 ROUTER_EXP, false), 2374 MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_SIP_DIP, FORWARD, 2375 ROUTER_EXP, false), 2376 MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_DIP_LINK_LOCAL, FORWARD, 2377 ROUTER_EXP, false), 2378 /* Multicast Router Traps */ 2379 MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false), 2380 MLXSW_SP_RXL_L3_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false), 2381 }; 2382 2383 static const struct mlxsw_listener mlxsw_sp1_listener[] = { 2384 /* Events */ 2385 MLXSW_EVENTL(mlxsw_sp1_ptp_egr_fifo_event_func, PTP_EGR_FIFO, SP_PTP0), 2386 MLXSW_EVENTL(mlxsw_sp1_ptp_ing_fifo_event_func, PTP_ING_FIFO, SP_PTP0), 2387 }; 2388 2389 static const struct mlxsw_listener mlxsw_sp2_listener[] = { 2390 /* Events */ 2391 MLXSW_SP_EVENTL(mlxsw_sp_port_mapping_listener_func, PMLPE), 2392 }; 2393 2394 static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core) 2395 { 2396 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 2397 char qpcr_pl[MLXSW_REG_QPCR_LEN]; 2398 enum mlxsw_reg_qpcr_ir_units ir_units; 2399 int max_cpu_policers; 2400 bool is_bytes; 2401 u8 burst_size; 2402 u32 rate; 2403 int i, err; 2404 2405 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS)) 2406 return -EIO; 2407 2408 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS); 2409 2410 ir_units = MLXSW_REG_QPCR_IR_UNITS_M; 2411 for (i = 0; i < max_cpu_policers; i++) { 2412 is_bytes = false; 2413 switch (i) { 2414 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP: 2415 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST: 2416 case MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS: 2417 rate = 1024; 2418 burst_size = 7; 2419 break; 2420 default: 2421 continue; 2422 } 2423 2424 __set_bit(i, mlxsw_sp->trap->policers_usage); 2425 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate, 2426 burst_size); 2427 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl); 2428 if (err) 2429 return err; 2430 } 2431 2432 return 0; 2433 } 2434 2435 static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core) 2436 { 2437 char htgt_pl[MLXSW_REG_HTGT_LEN]; 2438 enum mlxsw_reg_htgt_trap_group i; 2439 int max_cpu_policers; 2440 int max_trap_groups; 2441 u8 priority, tc; 2442 u16 policer_id; 2443 int err; 2444 2445 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS)) 2446 return -EIO; 2447 2448 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS); 2449 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS); 2450 2451 for (i = 0; i < max_trap_groups; i++) { 2452 policer_id = i; 2453 switch (i) { 2454 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP: 2455 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST: 2456 case MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS: 2457 priority = 1; 2458 tc = 1; 2459 break; 2460 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT: 2461 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY; 2462 tc = MLXSW_REG_HTGT_DEFAULT_TC; 2463 policer_id = MLXSW_REG_HTGT_INVALID_POLICER; 2464 break; 2465 default: 2466 continue; 2467 } 2468 2469 if (max_cpu_policers <= policer_id && 2470 policer_id != MLXSW_REG_HTGT_INVALID_POLICER) 2471 return -EIO; 2472 2473 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc); 2474 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl); 2475 if (err) 2476 return err; 2477 } 2478 2479 return 0; 2480 } 2481 2482 static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp) 2483 { 2484 struct mlxsw_sp_trap *trap; 2485 u64 max_policers; 2486 int err; 2487 2488 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_CPU_POLICERS)) 2489 return -EIO; 2490 max_policers = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_CPU_POLICERS); 2491 trap = kzalloc(struct_size(trap, policers_usage, 2492 BITS_TO_LONGS(max_policers)), GFP_KERNEL); 2493 if (!trap) 2494 return -ENOMEM; 2495 trap->max_policers = max_policers; 2496 mlxsw_sp->trap = trap; 2497 2498 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core); 2499 if (err) 2500 goto err_cpu_policers_set; 2501 2502 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core); 2503 if (err) 2504 goto err_trap_groups_set; 2505 2506 err = mlxsw_core_traps_register(mlxsw_sp->core, mlxsw_sp_listener, 2507 ARRAY_SIZE(mlxsw_sp_listener), 2508 mlxsw_sp); 2509 if (err) 2510 goto err_traps_register; 2511 2512 err = mlxsw_core_traps_register(mlxsw_sp->core, mlxsw_sp->listeners, 2513 mlxsw_sp->listeners_count, mlxsw_sp); 2514 if (err) 2515 goto err_extra_traps_init; 2516 2517 return 0; 2518 2519 err_extra_traps_init: 2520 mlxsw_core_traps_unregister(mlxsw_sp->core, mlxsw_sp_listener, 2521 ARRAY_SIZE(mlxsw_sp_listener), 2522 mlxsw_sp); 2523 err_traps_register: 2524 err_trap_groups_set: 2525 err_cpu_policers_set: 2526 kfree(trap); 2527 return err; 2528 } 2529 2530 static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp) 2531 { 2532 mlxsw_core_traps_unregister(mlxsw_sp->core, mlxsw_sp->listeners, 2533 mlxsw_sp->listeners_count, 2534 mlxsw_sp); 2535 mlxsw_core_traps_unregister(mlxsw_sp->core, mlxsw_sp_listener, 2536 ARRAY_SIZE(mlxsw_sp_listener), mlxsw_sp); 2537 kfree(mlxsw_sp->trap); 2538 } 2539 2540 static int mlxsw_sp_lag_pgt_init(struct mlxsw_sp *mlxsw_sp) 2541 { 2542 char sgcr_pl[MLXSW_REG_SGCR_LEN]; 2543 int err; 2544 2545 if (mlxsw_core_lag_mode(mlxsw_sp->core) != 2546 MLXSW_CMD_MBOX_CONFIG_PROFILE_LAG_MODE_SW) 2547 return 0; 2548 2549 /* In DDD mode, which we by default use, each LAG entry is 8 PGT 2550 * entries. The LAG table address needs to be 8-aligned, but that ought 2551 * to be the case, since the LAG table is allocated first. 2552 */ 2553 err = mlxsw_sp_pgt_mid_alloc_range(mlxsw_sp, &mlxsw_sp->lag_pgt_base, 2554 mlxsw_sp->max_lag * 8); 2555 if (err) 2556 return err; 2557 if (WARN_ON_ONCE(mlxsw_sp->lag_pgt_base % 8)) { 2558 err = -EINVAL; 2559 goto err_mid_alloc_range; 2560 } 2561 2562 mlxsw_reg_sgcr_pack(sgcr_pl, mlxsw_sp->lag_pgt_base); 2563 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sgcr), sgcr_pl); 2564 if (err) 2565 goto err_mid_alloc_range; 2566 2567 return 0; 2568 2569 err_mid_alloc_range: 2570 mlxsw_sp_pgt_mid_free_range(mlxsw_sp, mlxsw_sp->lag_pgt_base, 2571 mlxsw_sp->max_lag * 8); 2572 return err; 2573 } 2574 2575 static void mlxsw_sp_lag_pgt_fini(struct mlxsw_sp *mlxsw_sp) 2576 { 2577 if (mlxsw_core_lag_mode(mlxsw_sp->core) != 2578 MLXSW_CMD_MBOX_CONFIG_PROFILE_LAG_MODE_SW) 2579 return; 2580 2581 mlxsw_sp_pgt_mid_free_range(mlxsw_sp, mlxsw_sp->lag_pgt_base, 2582 mlxsw_sp->max_lag * 8); 2583 } 2584 2585 #define MLXSW_SP_LAG_SEED_INIT 0xcafecafe 2586 2587 struct mlxsw_sp_lag { 2588 struct net_device *dev; 2589 refcount_t ref_count; 2590 u16 lag_id; 2591 }; 2592 2593 static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp) 2594 { 2595 char slcr_pl[MLXSW_REG_SLCR_LEN]; 2596 u32 seed; 2597 int err; 2598 2599 seed = jhash(mlxsw_sp->base_mac, sizeof(mlxsw_sp->base_mac), 2600 MLXSW_SP_LAG_SEED_INIT); 2601 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC | 2602 MLXSW_REG_SLCR_LAG_HASH_DMAC | 2603 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE | 2604 MLXSW_REG_SLCR_LAG_HASH_VLANID | 2605 MLXSW_REG_SLCR_LAG_HASH_SIP | 2606 MLXSW_REG_SLCR_LAG_HASH_DIP | 2607 MLXSW_REG_SLCR_LAG_HASH_SPORT | 2608 MLXSW_REG_SLCR_LAG_HASH_DPORT | 2609 MLXSW_REG_SLCR_LAG_HASH_IPPROTO, seed); 2610 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl); 2611 if (err) 2612 return err; 2613 2614 err = mlxsw_core_max_lag(mlxsw_sp->core, &mlxsw_sp->max_lag); 2615 if (err) 2616 return err; 2617 2618 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS)) 2619 return -EIO; 2620 2621 err = mlxsw_sp_lag_pgt_init(mlxsw_sp); 2622 if (err) 2623 return err; 2624 2625 mlxsw_sp->lags = kcalloc(mlxsw_sp->max_lag, sizeof(struct mlxsw_sp_lag), 2626 GFP_KERNEL); 2627 if (!mlxsw_sp->lags) { 2628 err = -ENOMEM; 2629 goto err_kcalloc; 2630 } 2631 2632 return 0; 2633 2634 err_kcalloc: 2635 mlxsw_sp_lag_pgt_fini(mlxsw_sp); 2636 return err; 2637 } 2638 2639 static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp) 2640 { 2641 mlxsw_sp_lag_pgt_fini(mlxsw_sp); 2642 kfree(mlxsw_sp->lags); 2643 } 2644 2645 static const struct mlxsw_sp_ptp_ops mlxsw_sp1_ptp_ops = { 2646 .clock_init = mlxsw_sp1_ptp_clock_init, 2647 .clock_fini = mlxsw_sp1_ptp_clock_fini, 2648 .init = mlxsw_sp1_ptp_init, 2649 .fini = mlxsw_sp1_ptp_fini, 2650 .receive = mlxsw_sp1_ptp_receive, 2651 .transmitted = mlxsw_sp1_ptp_transmitted, 2652 .hwtstamp_get = mlxsw_sp1_ptp_hwtstamp_get, 2653 .hwtstamp_set = mlxsw_sp1_ptp_hwtstamp_set, 2654 .shaper_work = mlxsw_sp1_ptp_shaper_work, 2655 #if IS_REACHABLE(CONFIG_PTP_1588_CLOCK) 2656 .get_ts_info = mlxsw_sp1_ptp_get_ts_info, 2657 #endif 2658 .get_stats_count = mlxsw_sp1_get_stats_count, 2659 .get_stats_strings = mlxsw_sp1_get_stats_strings, 2660 .get_stats = mlxsw_sp1_get_stats, 2661 }; 2662 2663 static const struct mlxsw_sp_ptp_ops mlxsw_sp2_ptp_ops = { 2664 .clock_init = mlxsw_sp2_ptp_clock_init, 2665 .clock_fini = mlxsw_sp2_ptp_clock_fini, 2666 .init = mlxsw_sp2_ptp_init, 2667 .fini = mlxsw_sp2_ptp_fini, 2668 .receive = mlxsw_sp2_ptp_receive, 2669 .transmitted = mlxsw_sp2_ptp_transmitted, 2670 .hwtstamp_get = mlxsw_sp2_ptp_hwtstamp_get, 2671 .hwtstamp_set = mlxsw_sp2_ptp_hwtstamp_set, 2672 .shaper_work = mlxsw_sp2_ptp_shaper_work, 2673 #if IS_REACHABLE(CONFIG_PTP_1588_CLOCK) 2674 .get_ts_info = mlxsw_sp2_ptp_get_ts_info, 2675 #endif 2676 .get_stats_count = mlxsw_sp2_get_stats_count, 2677 .get_stats_strings = mlxsw_sp2_get_stats_strings, 2678 .get_stats = mlxsw_sp2_get_stats, 2679 .tx_as_data = true, 2680 }; 2681 2682 static const struct mlxsw_sp_ptp_ops mlxsw_sp4_ptp_ops = { 2683 .clock_init = mlxsw_sp2_ptp_clock_init, 2684 .clock_fini = mlxsw_sp2_ptp_clock_fini, 2685 .init = mlxsw_sp2_ptp_init, 2686 .fini = mlxsw_sp2_ptp_fini, 2687 .receive = mlxsw_sp2_ptp_receive, 2688 .transmitted = mlxsw_sp2_ptp_transmitted, 2689 .hwtstamp_get = mlxsw_sp2_ptp_hwtstamp_get, 2690 .hwtstamp_set = mlxsw_sp2_ptp_hwtstamp_set, 2691 .shaper_work = mlxsw_sp2_ptp_shaper_work, 2692 #if IS_REACHABLE(CONFIG_PTP_1588_CLOCK) 2693 .get_ts_info = mlxsw_sp2_ptp_get_ts_info, 2694 #endif 2695 .get_stats_count = mlxsw_sp2_get_stats_count, 2696 .get_stats_strings = mlxsw_sp2_get_stats_strings, 2697 .get_stats = mlxsw_sp2_get_stats, 2698 }; 2699 2700 struct mlxsw_sp_sample_trigger_node { 2701 struct mlxsw_sp_sample_trigger trigger; 2702 struct mlxsw_sp_sample_params params; 2703 struct rhash_head ht_node; 2704 struct rcu_head rcu; 2705 refcount_t refcount; 2706 }; 2707 2708 static const struct rhashtable_params mlxsw_sp_sample_trigger_ht_params = { 2709 .key_offset = offsetof(struct mlxsw_sp_sample_trigger_node, trigger), 2710 .head_offset = offsetof(struct mlxsw_sp_sample_trigger_node, ht_node), 2711 .key_len = sizeof(struct mlxsw_sp_sample_trigger), 2712 .automatic_shrinking = true, 2713 }; 2714 2715 static void 2716 mlxsw_sp_sample_trigger_key_init(struct mlxsw_sp_sample_trigger *key, 2717 const struct mlxsw_sp_sample_trigger *trigger) 2718 { 2719 memset(key, 0, sizeof(*key)); 2720 key->type = trigger->type; 2721 key->local_port = trigger->local_port; 2722 } 2723 2724 /* RCU read lock must be held */ 2725 struct mlxsw_sp_sample_params * 2726 mlxsw_sp_sample_trigger_params_lookup(struct mlxsw_sp *mlxsw_sp, 2727 const struct mlxsw_sp_sample_trigger *trigger) 2728 { 2729 struct mlxsw_sp_sample_trigger_node *trigger_node; 2730 struct mlxsw_sp_sample_trigger key; 2731 2732 mlxsw_sp_sample_trigger_key_init(&key, trigger); 2733 trigger_node = rhashtable_lookup(&mlxsw_sp->sample_trigger_ht, &key, 2734 mlxsw_sp_sample_trigger_ht_params); 2735 if (!trigger_node) 2736 return NULL; 2737 2738 return &trigger_node->params; 2739 } 2740 2741 static int 2742 mlxsw_sp_sample_trigger_node_init(struct mlxsw_sp *mlxsw_sp, 2743 const struct mlxsw_sp_sample_trigger *trigger, 2744 const struct mlxsw_sp_sample_params *params) 2745 { 2746 struct mlxsw_sp_sample_trigger_node *trigger_node; 2747 int err; 2748 2749 trigger_node = kzalloc(sizeof(*trigger_node), GFP_KERNEL); 2750 if (!trigger_node) 2751 return -ENOMEM; 2752 2753 trigger_node->trigger = *trigger; 2754 trigger_node->params = *params; 2755 refcount_set(&trigger_node->refcount, 1); 2756 2757 err = rhashtable_insert_fast(&mlxsw_sp->sample_trigger_ht, 2758 &trigger_node->ht_node, 2759 mlxsw_sp_sample_trigger_ht_params); 2760 if (err) 2761 goto err_rhashtable_insert; 2762 2763 return 0; 2764 2765 err_rhashtable_insert: 2766 kfree(trigger_node); 2767 return err; 2768 } 2769 2770 static void 2771 mlxsw_sp_sample_trigger_node_fini(struct mlxsw_sp *mlxsw_sp, 2772 struct mlxsw_sp_sample_trigger_node *trigger_node) 2773 { 2774 rhashtable_remove_fast(&mlxsw_sp->sample_trigger_ht, 2775 &trigger_node->ht_node, 2776 mlxsw_sp_sample_trigger_ht_params); 2777 kfree_rcu(trigger_node, rcu); 2778 } 2779 2780 int 2781 mlxsw_sp_sample_trigger_params_set(struct mlxsw_sp *mlxsw_sp, 2782 const struct mlxsw_sp_sample_trigger *trigger, 2783 const struct mlxsw_sp_sample_params *params, 2784 struct netlink_ext_ack *extack) 2785 { 2786 struct mlxsw_sp_sample_trigger_node *trigger_node; 2787 struct mlxsw_sp_sample_trigger key; 2788 2789 ASSERT_RTNL(); 2790 2791 mlxsw_sp_sample_trigger_key_init(&key, trigger); 2792 2793 trigger_node = rhashtable_lookup_fast(&mlxsw_sp->sample_trigger_ht, 2794 &key, 2795 mlxsw_sp_sample_trigger_ht_params); 2796 if (!trigger_node) 2797 return mlxsw_sp_sample_trigger_node_init(mlxsw_sp, &key, 2798 params); 2799 2800 if (trigger_node->trigger.local_port) { 2801 NL_SET_ERR_MSG_MOD(extack, "Sampling already enabled on port"); 2802 return -EINVAL; 2803 } 2804 2805 if (trigger_node->params.psample_group != params->psample_group || 2806 trigger_node->params.truncate != params->truncate || 2807 trigger_node->params.rate != params->rate || 2808 trigger_node->params.trunc_size != params->trunc_size) { 2809 NL_SET_ERR_MSG_MOD(extack, "Sampling parameters do not match for an existing sampling trigger"); 2810 return -EINVAL; 2811 } 2812 2813 refcount_inc(&trigger_node->refcount); 2814 2815 return 0; 2816 } 2817 2818 void 2819 mlxsw_sp_sample_trigger_params_unset(struct mlxsw_sp *mlxsw_sp, 2820 const struct mlxsw_sp_sample_trigger *trigger) 2821 { 2822 struct mlxsw_sp_sample_trigger_node *trigger_node; 2823 struct mlxsw_sp_sample_trigger key; 2824 2825 ASSERT_RTNL(); 2826 2827 mlxsw_sp_sample_trigger_key_init(&key, trigger); 2828 2829 trigger_node = rhashtable_lookup_fast(&mlxsw_sp->sample_trigger_ht, 2830 &key, 2831 mlxsw_sp_sample_trigger_ht_params); 2832 if (!trigger_node) 2833 return; 2834 2835 if (!refcount_dec_and_test(&trigger_node->refcount)) 2836 return; 2837 2838 mlxsw_sp_sample_trigger_node_fini(mlxsw_sp, trigger_node); 2839 } 2840 2841 static int mlxsw_sp_netdevice_event(struct notifier_block *unused, 2842 unsigned long event, void *ptr); 2843 2844 #define MLXSW_SP_DEFAULT_PARSING_DEPTH 96 2845 #define MLXSW_SP_INCREASED_PARSING_DEPTH 128 2846 #define MLXSW_SP_DEFAULT_VXLAN_UDP_DPORT 4789 2847 2848 static void mlxsw_sp_parsing_init(struct mlxsw_sp *mlxsw_sp) 2849 { 2850 refcount_set(&mlxsw_sp->parsing.parsing_depth_ref, 0); 2851 mlxsw_sp->parsing.parsing_depth = MLXSW_SP_DEFAULT_PARSING_DEPTH; 2852 mlxsw_sp->parsing.vxlan_udp_dport = MLXSW_SP_DEFAULT_VXLAN_UDP_DPORT; 2853 mutex_init(&mlxsw_sp->parsing.lock); 2854 } 2855 2856 static void mlxsw_sp_parsing_fini(struct mlxsw_sp *mlxsw_sp) 2857 { 2858 mutex_destroy(&mlxsw_sp->parsing.lock); 2859 WARN_ON_ONCE(refcount_read(&mlxsw_sp->parsing.parsing_depth_ref)); 2860 } 2861 2862 struct mlxsw_sp_ipv6_addr_node { 2863 struct in6_addr key; 2864 struct rhash_head ht_node; 2865 u32 kvdl_index; 2866 refcount_t refcount; 2867 }; 2868 2869 static const struct rhashtable_params mlxsw_sp_ipv6_addr_ht_params = { 2870 .key_offset = offsetof(struct mlxsw_sp_ipv6_addr_node, key), 2871 .head_offset = offsetof(struct mlxsw_sp_ipv6_addr_node, ht_node), 2872 .key_len = sizeof(struct in6_addr), 2873 .automatic_shrinking = true, 2874 }; 2875 2876 static int 2877 mlxsw_sp_ipv6_addr_init(struct mlxsw_sp *mlxsw_sp, const struct in6_addr *addr6, 2878 u32 *p_kvdl_index) 2879 { 2880 struct mlxsw_sp_ipv6_addr_node *node; 2881 char rips_pl[MLXSW_REG_RIPS_LEN]; 2882 int err; 2883 2884 err = mlxsw_sp_kvdl_alloc(mlxsw_sp, 2885 MLXSW_SP_KVDL_ENTRY_TYPE_IPV6_ADDRESS, 1, 2886 p_kvdl_index); 2887 if (err) 2888 return err; 2889 2890 mlxsw_reg_rips_pack(rips_pl, *p_kvdl_index, addr6); 2891 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(rips), rips_pl); 2892 if (err) 2893 goto err_rips_write; 2894 2895 node = kzalloc(sizeof(*node), GFP_KERNEL); 2896 if (!node) { 2897 err = -ENOMEM; 2898 goto err_node_alloc; 2899 } 2900 2901 node->key = *addr6; 2902 node->kvdl_index = *p_kvdl_index; 2903 refcount_set(&node->refcount, 1); 2904 2905 err = rhashtable_insert_fast(&mlxsw_sp->ipv6_addr_ht, 2906 &node->ht_node, 2907 mlxsw_sp_ipv6_addr_ht_params); 2908 if (err) 2909 goto err_rhashtable_insert; 2910 2911 return 0; 2912 2913 err_rhashtable_insert: 2914 kfree(node); 2915 err_node_alloc: 2916 err_rips_write: 2917 mlxsw_sp_kvdl_free(mlxsw_sp, MLXSW_SP_KVDL_ENTRY_TYPE_IPV6_ADDRESS, 1, 2918 *p_kvdl_index); 2919 return err; 2920 } 2921 2922 static void mlxsw_sp_ipv6_addr_fini(struct mlxsw_sp *mlxsw_sp, 2923 struct mlxsw_sp_ipv6_addr_node *node) 2924 { 2925 u32 kvdl_index = node->kvdl_index; 2926 2927 rhashtable_remove_fast(&mlxsw_sp->ipv6_addr_ht, &node->ht_node, 2928 mlxsw_sp_ipv6_addr_ht_params); 2929 kfree(node); 2930 mlxsw_sp_kvdl_free(mlxsw_sp, MLXSW_SP_KVDL_ENTRY_TYPE_IPV6_ADDRESS, 1, 2931 kvdl_index); 2932 } 2933 2934 int mlxsw_sp_ipv6_addr_kvdl_index_get(struct mlxsw_sp *mlxsw_sp, 2935 const struct in6_addr *addr6, 2936 u32 *p_kvdl_index) 2937 { 2938 struct mlxsw_sp_ipv6_addr_node *node; 2939 int err = 0; 2940 2941 mutex_lock(&mlxsw_sp->ipv6_addr_ht_lock); 2942 node = rhashtable_lookup_fast(&mlxsw_sp->ipv6_addr_ht, addr6, 2943 mlxsw_sp_ipv6_addr_ht_params); 2944 if (node) { 2945 refcount_inc(&node->refcount); 2946 *p_kvdl_index = node->kvdl_index; 2947 goto out_unlock; 2948 } 2949 2950 err = mlxsw_sp_ipv6_addr_init(mlxsw_sp, addr6, p_kvdl_index); 2951 2952 out_unlock: 2953 mutex_unlock(&mlxsw_sp->ipv6_addr_ht_lock); 2954 return err; 2955 } 2956 2957 void 2958 mlxsw_sp_ipv6_addr_put(struct mlxsw_sp *mlxsw_sp, const struct in6_addr *addr6) 2959 { 2960 struct mlxsw_sp_ipv6_addr_node *node; 2961 2962 mutex_lock(&mlxsw_sp->ipv6_addr_ht_lock); 2963 node = rhashtable_lookup_fast(&mlxsw_sp->ipv6_addr_ht, addr6, 2964 mlxsw_sp_ipv6_addr_ht_params); 2965 if (WARN_ON(!node)) 2966 goto out_unlock; 2967 2968 if (!refcount_dec_and_test(&node->refcount)) 2969 goto out_unlock; 2970 2971 mlxsw_sp_ipv6_addr_fini(mlxsw_sp, node); 2972 2973 out_unlock: 2974 mutex_unlock(&mlxsw_sp->ipv6_addr_ht_lock); 2975 } 2976 2977 static int mlxsw_sp_ipv6_addr_ht_init(struct mlxsw_sp *mlxsw_sp) 2978 { 2979 int err; 2980 2981 err = rhashtable_init(&mlxsw_sp->ipv6_addr_ht, 2982 &mlxsw_sp_ipv6_addr_ht_params); 2983 if (err) 2984 return err; 2985 2986 mutex_init(&mlxsw_sp->ipv6_addr_ht_lock); 2987 return 0; 2988 } 2989 2990 static void mlxsw_sp_ipv6_addr_ht_fini(struct mlxsw_sp *mlxsw_sp) 2991 { 2992 mutex_destroy(&mlxsw_sp->ipv6_addr_ht_lock); 2993 rhashtable_destroy(&mlxsw_sp->ipv6_addr_ht); 2994 } 2995 2996 static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core, 2997 const struct mlxsw_bus_info *mlxsw_bus_info, 2998 struct netlink_ext_ack *extack) 2999 { 3000 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3001 int err; 3002 3003 mlxsw_sp->core = mlxsw_core; 3004 mlxsw_sp->bus_info = mlxsw_bus_info; 3005 3006 mlxsw_sp_parsing_init(mlxsw_sp); 3007 3008 err = mlxsw_sp_base_mac_get(mlxsw_sp); 3009 if (err) { 3010 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n"); 3011 return err; 3012 } 3013 3014 err = mlxsw_sp_kvdl_init(mlxsw_sp); 3015 if (err) { 3016 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n"); 3017 return err; 3018 } 3019 3020 err = mlxsw_sp_pgt_init(mlxsw_sp); 3021 if (err) { 3022 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize PGT\n"); 3023 goto err_pgt_init; 3024 } 3025 3026 /* Initialize before FIDs so that the LAG table is at the start of PGT 3027 * and 8-aligned without overallocation. 3028 */ 3029 err = mlxsw_sp_lag_init(mlxsw_sp); 3030 if (err) { 3031 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n"); 3032 goto err_lag_init; 3033 } 3034 3035 err = mlxsw_sp->fid_core_ops->init(mlxsw_sp); 3036 if (err) { 3037 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n"); 3038 goto err_fid_core_init; 3039 } 3040 3041 err = mlxsw_sp_policers_init(mlxsw_sp); 3042 if (err) { 3043 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize policers\n"); 3044 goto err_policers_init; 3045 } 3046 3047 err = mlxsw_sp_traps_init(mlxsw_sp); 3048 if (err) { 3049 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n"); 3050 goto err_traps_init; 3051 } 3052 3053 err = mlxsw_sp_devlink_traps_init(mlxsw_sp); 3054 if (err) { 3055 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize devlink traps\n"); 3056 goto err_devlink_traps_init; 3057 } 3058 3059 err = mlxsw_sp_buffers_init(mlxsw_sp); 3060 if (err) { 3061 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n"); 3062 goto err_buffers_init; 3063 } 3064 3065 /* Initialize SPAN before router and switchdev, so that those components 3066 * can call mlxsw_sp_span_respin(). 3067 */ 3068 err = mlxsw_sp_span_init(mlxsw_sp); 3069 if (err) { 3070 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n"); 3071 goto err_span_init; 3072 } 3073 3074 err = mlxsw_sp_switchdev_init(mlxsw_sp); 3075 if (err) { 3076 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n"); 3077 goto err_switchdev_init; 3078 } 3079 3080 err = mlxsw_sp_counter_pool_init(mlxsw_sp); 3081 if (err) { 3082 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n"); 3083 goto err_counter_pool_init; 3084 } 3085 3086 err = mlxsw_sp_afa_init(mlxsw_sp); 3087 if (err) { 3088 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n"); 3089 goto err_afa_init; 3090 } 3091 3092 err = mlxsw_sp_ipv6_addr_ht_init(mlxsw_sp); 3093 if (err) { 3094 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize hash table for IPv6 addresses\n"); 3095 goto err_ipv6_addr_ht_init; 3096 } 3097 3098 err = mlxsw_sp_nve_init(mlxsw_sp); 3099 if (err) { 3100 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize NVE\n"); 3101 goto err_nve_init; 3102 } 3103 3104 err = mlxsw_sp_port_range_init(mlxsw_sp); 3105 if (err) { 3106 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize port ranges\n"); 3107 goto err_port_range_init; 3108 } 3109 3110 err = mlxsw_sp_acl_init(mlxsw_sp); 3111 if (err) { 3112 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n"); 3113 goto err_acl_init; 3114 } 3115 3116 err = mlxsw_sp_router_init(mlxsw_sp, extack); 3117 if (err) { 3118 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n"); 3119 goto err_router_init; 3120 } 3121 3122 if (mlxsw_sp->bus_info->read_clock_capable) { 3123 /* NULL is a valid return value from clock_init */ 3124 mlxsw_sp->clock = 3125 mlxsw_sp->ptp_ops->clock_init(mlxsw_sp, 3126 mlxsw_sp->bus_info->dev); 3127 if (IS_ERR(mlxsw_sp->clock)) { 3128 err = PTR_ERR(mlxsw_sp->clock); 3129 dev_err(mlxsw_sp->bus_info->dev, "Failed to init ptp clock\n"); 3130 goto err_ptp_clock_init; 3131 } 3132 } 3133 3134 if (mlxsw_sp->clock) { 3135 /* NULL is a valid return value from ptp_ops->init */ 3136 mlxsw_sp->ptp_state = mlxsw_sp->ptp_ops->init(mlxsw_sp); 3137 if (IS_ERR(mlxsw_sp->ptp_state)) { 3138 err = PTR_ERR(mlxsw_sp->ptp_state); 3139 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize PTP\n"); 3140 goto err_ptp_init; 3141 } 3142 } 3143 3144 /* Initialize netdevice notifier after SPAN is initialized, so that the 3145 * event handler can call SPAN respin. 3146 */ 3147 mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event; 3148 err = register_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp), 3149 &mlxsw_sp->netdevice_nb); 3150 if (err) { 3151 dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n"); 3152 goto err_netdev_notifier; 3153 } 3154 3155 err = mlxsw_sp_dpipe_init(mlxsw_sp); 3156 if (err) { 3157 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n"); 3158 goto err_dpipe_init; 3159 } 3160 3161 err = mlxsw_sp_port_module_info_init(mlxsw_sp); 3162 if (err) { 3163 dev_err(mlxsw_sp->bus_info->dev, "Failed to init port module info\n"); 3164 goto err_port_module_info_init; 3165 } 3166 3167 err = rhashtable_init(&mlxsw_sp->sample_trigger_ht, 3168 &mlxsw_sp_sample_trigger_ht_params); 3169 if (err) { 3170 dev_err(mlxsw_sp->bus_info->dev, "Failed to init sampling trigger hashtable\n"); 3171 goto err_sample_trigger_init; 3172 } 3173 3174 err = mlxsw_sp_ports_create(mlxsw_sp); 3175 if (err) { 3176 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n"); 3177 goto err_ports_create; 3178 } 3179 3180 return 0; 3181 3182 err_ports_create: 3183 rhashtable_destroy(&mlxsw_sp->sample_trigger_ht); 3184 err_sample_trigger_init: 3185 mlxsw_sp_port_module_info_fini(mlxsw_sp); 3186 err_port_module_info_init: 3187 mlxsw_sp_dpipe_fini(mlxsw_sp); 3188 err_dpipe_init: 3189 unregister_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp), 3190 &mlxsw_sp->netdevice_nb); 3191 err_netdev_notifier: 3192 if (mlxsw_sp->clock) 3193 mlxsw_sp->ptp_ops->fini(mlxsw_sp->ptp_state); 3194 err_ptp_init: 3195 if (mlxsw_sp->clock) 3196 mlxsw_sp->ptp_ops->clock_fini(mlxsw_sp->clock); 3197 err_ptp_clock_init: 3198 mlxsw_sp_router_fini(mlxsw_sp); 3199 err_router_init: 3200 mlxsw_sp_acl_fini(mlxsw_sp); 3201 err_acl_init: 3202 mlxsw_sp_port_range_fini(mlxsw_sp); 3203 err_port_range_init: 3204 mlxsw_sp_nve_fini(mlxsw_sp); 3205 err_nve_init: 3206 mlxsw_sp_ipv6_addr_ht_fini(mlxsw_sp); 3207 err_ipv6_addr_ht_init: 3208 mlxsw_sp_afa_fini(mlxsw_sp); 3209 err_afa_init: 3210 mlxsw_sp_counter_pool_fini(mlxsw_sp); 3211 err_counter_pool_init: 3212 mlxsw_sp_switchdev_fini(mlxsw_sp); 3213 err_switchdev_init: 3214 mlxsw_sp_span_fini(mlxsw_sp); 3215 err_span_init: 3216 mlxsw_sp_buffers_fini(mlxsw_sp); 3217 err_buffers_init: 3218 mlxsw_sp_devlink_traps_fini(mlxsw_sp); 3219 err_devlink_traps_init: 3220 mlxsw_sp_traps_fini(mlxsw_sp); 3221 err_traps_init: 3222 mlxsw_sp_policers_fini(mlxsw_sp); 3223 err_policers_init: 3224 mlxsw_sp->fid_core_ops->fini(mlxsw_sp); 3225 err_fid_core_init: 3226 mlxsw_sp_lag_fini(mlxsw_sp); 3227 err_lag_init: 3228 mlxsw_sp_pgt_fini(mlxsw_sp); 3229 err_pgt_init: 3230 mlxsw_sp_kvdl_fini(mlxsw_sp); 3231 mlxsw_sp_parsing_fini(mlxsw_sp); 3232 return err; 3233 } 3234 3235 static int mlxsw_sp1_init(struct mlxsw_core *mlxsw_core, 3236 const struct mlxsw_bus_info *mlxsw_bus_info, 3237 struct netlink_ext_ack *extack) 3238 { 3239 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3240 3241 mlxsw_sp->switchdev_ops = &mlxsw_sp1_switchdev_ops; 3242 mlxsw_sp->kvdl_ops = &mlxsw_sp1_kvdl_ops; 3243 mlxsw_sp->afa_ops = &mlxsw_sp1_act_afa_ops; 3244 mlxsw_sp->afk_ops = &mlxsw_sp1_afk_ops; 3245 mlxsw_sp->mr_tcam_ops = &mlxsw_sp1_mr_tcam_ops; 3246 mlxsw_sp->acl_rulei_ops = &mlxsw_sp1_acl_rulei_ops; 3247 mlxsw_sp->acl_tcam_ops = &mlxsw_sp1_acl_tcam_ops; 3248 mlxsw_sp->nve_ops_arr = mlxsw_sp1_nve_ops_arr; 3249 mlxsw_sp->mac_mask = mlxsw_sp1_mac_mask; 3250 mlxsw_sp->sb_vals = &mlxsw_sp1_sb_vals; 3251 mlxsw_sp->sb_ops = &mlxsw_sp1_sb_ops; 3252 mlxsw_sp->port_type_speed_ops = &mlxsw_sp1_port_type_speed_ops; 3253 mlxsw_sp->ptp_ops = &mlxsw_sp1_ptp_ops; 3254 mlxsw_sp->span_ops = &mlxsw_sp1_span_ops; 3255 mlxsw_sp->policer_core_ops = &mlxsw_sp1_policer_core_ops; 3256 mlxsw_sp->trap_ops = &mlxsw_sp1_trap_ops; 3257 mlxsw_sp->mall_ops = &mlxsw_sp1_mall_ops; 3258 mlxsw_sp->router_ops = &mlxsw_sp1_router_ops; 3259 mlxsw_sp->listeners = mlxsw_sp1_listener; 3260 mlxsw_sp->listeners_count = ARRAY_SIZE(mlxsw_sp1_listener); 3261 mlxsw_sp->fid_core_ops = &mlxsw_sp1_fid_core_ops; 3262 mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1; 3263 mlxsw_sp->pgt_smpe_index_valid = true; 3264 3265 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack); 3266 } 3267 3268 static int mlxsw_sp2_init(struct mlxsw_core *mlxsw_core, 3269 const struct mlxsw_bus_info *mlxsw_bus_info, 3270 struct netlink_ext_ack *extack) 3271 { 3272 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3273 3274 mlxsw_sp->switchdev_ops = &mlxsw_sp2_switchdev_ops; 3275 mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops; 3276 mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops; 3277 mlxsw_sp->afk_ops = &mlxsw_sp2_afk_ops; 3278 mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops; 3279 mlxsw_sp->acl_rulei_ops = &mlxsw_sp2_acl_rulei_ops; 3280 mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops; 3281 mlxsw_sp->acl_bf_ops = &mlxsw_sp2_acl_bf_ops; 3282 mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr; 3283 mlxsw_sp->mac_mask = mlxsw_sp2_mac_mask; 3284 mlxsw_sp->sb_vals = &mlxsw_sp2_sb_vals; 3285 mlxsw_sp->sb_ops = &mlxsw_sp2_sb_ops; 3286 mlxsw_sp->port_type_speed_ops = &mlxsw_sp2_port_type_speed_ops; 3287 mlxsw_sp->ptp_ops = &mlxsw_sp2_ptp_ops; 3288 mlxsw_sp->span_ops = &mlxsw_sp2_span_ops; 3289 mlxsw_sp->policer_core_ops = &mlxsw_sp2_policer_core_ops; 3290 mlxsw_sp->trap_ops = &mlxsw_sp2_trap_ops; 3291 mlxsw_sp->mall_ops = &mlxsw_sp2_mall_ops; 3292 mlxsw_sp->router_ops = &mlxsw_sp2_router_ops; 3293 mlxsw_sp->listeners = mlxsw_sp2_listener; 3294 mlxsw_sp->listeners_count = ARRAY_SIZE(mlxsw_sp2_listener); 3295 mlxsw_sp->fid_core_ops = &mlxsw_sp2_fid_core_ops; 3296 mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2; 3297 mlxsw_sp->pgt_smpe_index_valid = false; 3298 3299 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack); 3300 } 3301 3302 static int mlxsw_sp3_init(struct mlxsw_core *mlxsw_core, 3303 const struct mlxsw_bus_info *mlxsw_bus_info, 3304 struct netlink_ext_ack *extack) 3305 { 3306 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3307 3308 mlxsw_sp->switchdev_ops = &mlxsw_sp2_switchdev_ops; 3309 mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops; 3310 mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops; 3311 mlxsw_sp->afk_ops = &mlxsw_sp2_afk_ops; 3312 mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops; 3313 mlxsw_sp->acl_rulei_ops = &mlxsw_sp2_acl_rulei_ops; 3314 mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops; 3315 mlxsw_sp->acl_bf_ops = &mlxsw_sp2_acl_bf_ops; 3316 mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr; 3317 mlxsw_sp->mac_mask = mlxsw_sp2_mac_mask; 3318 mlxsw_sp->sb_vals = &mlxsw_sp2_sb_vals; 3319 mlxsw_sp->sb_ops = &mlxsw_sp3_sb_ops; 3320 mlxsw_sp->port_type_speed_ops = &mlxsw_sp2_port_type_speed_ops; 3321 mlxsw_sp->ptp_ops = &mlxsw_sp2_ptp_ops; 3322 mlxsw_sp->span_ops = &mlxsw_sp3_span_ops; 3323 mlxsw_sp->policer_core_ops = &mlxsw_sp2_policer_core_ops; 3324 mlxsw_sp->trap_ops = &mlxsw_sp2_trap_ops; 3325 mlxsw_sp->mall_ops = &mlxsw_sp2_mall_ops; 3326 mlxsw_sp->router_ops = &mlxsw_sp2_router_ops; 3327 mlxsw_sp->listeners = mlxsw_sp2_listener; 3328 mlxsw_sp->listeners_count = ARRAY_SIZE(mlxsw_sp2_listener); 3329 mlxsw_sp->fid_core_ops = &mlxsw_sp2_fid_core_ops; 3330 mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3; 3331 mlxsw_sp->pgt_smpe_index_valid = false; 3332 3333 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack); 3334 } 3335 3336 static int mlxsw_sp4_init(struct mlxsw_core *mlxsw_core, 3337 const struct mlxsw_bus_info *mlxsw_bus_info, 3338 struct netlink_ext_ack *extack) 3339 { 3340 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3341 3342 mlxsw_sp->switchdev_ops = &mlxsw_sp2_switchdev_ops; 3343 mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops; 3344 mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops; 3345 mlxsw_sp->afk_ops = &mlxsw_sp4_afk_ops; 3346 mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops; 3347 mlxsw_sp->acl_rulei_ops = &mlxsw_sp2_acl_rulei_ops; 3348 mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops; 3349 mlxsw_sp->acl_bf_ops = &mlxsw_sp4_acl_bf_ops; 3350 mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr; 3351 mlxsw_sp->mac_mask = mlxsw_sp2_mac_mask; 3352 mlxsw_sp->sb_vals = &mlxsw_sp2_sb_vals; 3353 mlxsw_sp->sb_ops = &mlxsw_sp3_sb_ops; 3354 mlxsw_sp->port_type_speed_ops = &mlxsw_sp2_port_type_speed_ops; 3355 mlxsw_sp->ptp_ops = &mlxsw_sp4_ptp_ops; 3356 mlxsw_sp->span_ops = &mlxsw_sp3_span_ops; 3357 mlxsw_sp->policer_core_ops = &mlxsw_sp2_policer_core_ops; 3358 mlxsw_sp->trap_ops = &mlxsw_sp2_trap_ops; 3359 mlxsw_sp->mall_ops = &mlxsw_sp2_mall_ops; 3360 mlxsw_sp->router_ops = &mlxsw_sp2_router_ops; 3361 mlxsw_sp->listeners = mlxsw_sp2_listener; 3362 mlxsw_sp->listeners_count = ARRAY_SIZE(mlxsw_sp2_listener); 3363 mlxsw_sp->fid_core_ops = &mlxsw_sp2_fid_core_ops; 3364 mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP4; 3365 mlxsw_sp->pgt_smpe_index_valid = false; 3366 3367 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack); 3368 } 3369 3370 static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core) 3371 { 3372 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3373 3374 mlxsw_sp_ports_remove(mlxsw_sp); 3375 rhashtable_destroy(&mlxsw_sp->sample_trigger_ht); 3376 mlxsw_sp_port_module_info_fini(mlxsw_sp); 3377 mlxsw_sp_dpipe_fini(mlxsw_sp); 3378 unregister_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp), 3379 &mlxsw_sp->netdevice_nb); 3380 if (mlxsw_sp->clock) { 3381 mlxsw_sp->ptp_ops->fini(mlxsw_sp->ptp_state); 3382 mlxsw_sp->ptp_ops->clock_fini(mlxsw_sp->clock); 3383 } 3384 mlxsw_sp_router_fini(mlxsw_sp); 3385 mlxsw_sp_acl_fini(mlxsw_sp); 3386 mlxsw_sp_port_range_fini(mlxsw_sp); 3387 mlxsw_sp_nve_fini(mlxsw_sp); 3388 mlxsw_sp_ipv6_addr_ht_fini(mlxsw_sp); 3389 mlxsw_sp_afa_fini(mlxsw_sp); 3390 mlxsw_sp_counter_pool_fini(mlxsw_sp); 3391 mlxsw_sp_switchdev_fini(mlxsw_sp); 3392 mlxsw_sp_span_fini(mlxsw_sp); 3393 mlxsw_sp_buffers_fini(mlxsw_sp); 3394 mlxsw_sp_devlink_traps_fini(mlxsw_sp); 3395 mlxsw_sp_traps_fini(mlxsw_sp); 3396 mlxsw_sp_policers_fini(mlxsw_sp); 3397 mlxsw_sp->fid_core_ops->fini(mlxsw_sp); 3398 mlxsw_sp_lag_fini(mlxsw_sp); 3399 mlxsw_sp_pgt_fini(mlxsw_sp); 3400 mlxsw_sp_kvdl_fini(mlxsw_sp); 3401 mlxsw_sp_parsing_fini(mlxsw_sp); 3402 } 3403 3404 static const struct mlxsw_config_profile mlxsw_sp1_config_profile = { 3405 .used_flood_mode = 1, 3406 .flood_mode = MLXSW_CMD_MBOX_CONFIG_PROFILE_FLOOD_MODE_CONTROLLED, 3407 .used_max_ib_mc = 1, 3408 .max_ib_mc = 0, 3409 .used_max_pkey = 1, 3410 .max_pkey = 0, 3411 .used_ubridge = 1, 3412 .ubridge = 1, 3413 .used_kvd_sizes = 1, 3414 .kvd_hash_single_parts = 59, 3415 .kvd_hash_double_parts = 41, 3416 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE, 3417 .swid_config = { 3418 { 3419 .used_type = 1, 3420 .type = MLXSW_PORT_SWID_TYPE_ETH, 3421 } 3422 }, 3423 }; 3424 3425 static const struct mlxsw_config_profile mlxsw_sp2_config_profile = { 3426 .used_flood_mode = 1, 3427 .flood_mode = MLXSW_CMD_MBOX_CONFIG_PROFILE_FLOOD_MODE_CONTROLLED, 3428 .used_max_ib_mc = 1, 3429 .max_ib_mc = 0, 3430 .used_max_pkey = 1, 3431 .max_pkey = 0, 3432 .used_ubridge = 1, 3433 .ubridge = 1, 3434 .swid_config = { 3435 { 3436 .used_type = 1, 3437 .type = MLXSW_PORT_SWID_TYPE_ETH, 3438 } 3439 }, 3440 .used_cqe_time_stamp_type = 1, 3441 .cqe_time_stamp_type = MLXSW_CMD_MBOX_CONFIG_PROFILE_CQE_TIME_STAMP_TYPE_UTC, 3442 .lag_mode_prefer_sw = true, 3443 .flood_mode_prefer_cff = true, 3444 }; 3445 3446 /* Reduce number of LAGs from full capacity (256) to the maximum supported LAGs 3447 * in Spectrum-2/3, to avoid regression in number of free entries in the PGT 3448 * table. 3449 */ 3450 #define MLXSW_SP4_CONFIG_PROFILE_MAX_LAG 128 3451 3452 static const struct mlxsw_config_profile mlxsw_sp4_config_profile = { 3453 .used_max_lag = 1, 3454 .max_lag = MLXSW_SP4_CONFIG_PROFILE_MAX_LAG, 3455 .used_flood_mode = 1, 3456 .flood_mode = MLXSW_CMD_MBOX_CONFIG_PROFILE_FLOOD_MODE_CONTROLLED, 3457 .used_max_ib_mc = 1, 3458 .max_ib_mc = 0, 3459 .used_max_pkey = 1, 3460 .max_pkey = 0, 3461 .used_ubridge = 1, 3462 .ubridge = 1, 3463 .swid_config = { 3464 { 3465 .used_type = 1, 3466 .type = MLXSW_PORT_SWID_TYPE_ETH, 3467 } 3468 }, 3469 .used_cqe_time_stamp_type = 1, 3470 .cqe_time_stamp_type = MLXSW_CMD_MBOX_CONFIG_PROFILE_CQE_TIME_STAMP_TYPE_UTC, 3471 .lag_mode_prefer_sw = true, 3472 .flood_mode_prefer_cff = true, 3473 }; 3474 3475 static void 3476 mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core, 3477 struct devlink_resource_size_params *kvd_size_params, 3478 struct devlink_resource_size_params *linear_size_params, 3479 struct devlink_resource_size_params *hash_double_size_params, 3480 struct devlink_resource_size_params *hash_single_size_params) 3481 { 3482 u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core, 3483 KVD_SINGLE_MIN_SIZE); 3484 u32 double_size_min = MLXSW_CORE_RES_GET(mlxsw_core, 3485 KVD_DOUBLE_MIN_SIZE); 3486 u32 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE); 3487 u32 linear_size_min = 0; 3488 3489 devlink_resource_size_params_init(kvd_size_params, kvd_size, kvd_size, 3490 MLXSW_SP_KVD_GRANULARITY, 3491 DEVLINK_RESOURCE_UNIT_ENTRY); 3492 devlink_resource_size_params_init(linear_size_params, linear_size_min, 3493 kvd_size - single_size_min - 3494 double_size_min, 3495 MLXSW_SP_KVD_GRANULARITY, 3496 DEVLINK_RESOURCE_UNIT_ENTRY); 3497 devlink_resource_size_params_init(hash_double_size_params, 3498 double_size_min, 3499 kvd_size - single_size_min - 3500 linear_size_min, 3501 MLXSW_SP_KVD_GRANULARITY, 3502 DEVLINK_RESOURCE_UNIT_ENTRY); 3503 devlink_resource_size_params_init(hash_single_size_params, 3504 single_size_min, 3505 kvd_size - double_size_min - 3506 linear_size_min, 3507 MLXSW_SP_KVD_GRANULARITY, 3508 DEVLINK_RESOURCE_UNIT_ENTRY); 3509 } 3510 3511 static int mlxsw_sp1_resources_kvd_register(struct mlxsw_core *mlxsw_core) 3512 { 3513 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3514 struct devlink_resource_size_params hash_single_size_params; 3515 struct devlink_resource_size_params hash_double_size_params; 3516 struct devlink_resource_size_params linear_size_params; 3517 struct devlink_resource_size_params kvd_size_params; 3518 u32 kvd_size, single_size, double_size, linear_size; 3519 const struct mlxsw_config_profile *profile; 3520 int err; 3521 3522 profile = &mlxsw_sp1_config_profile; 3523 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE)) 3524 return -EIO; 3525 3526 mlxsw_sp_resource_size_params_prepare(mlxsw_core, &kvd_size_params, 3527 &linear_size_params, 3528 &hash_double_size_params, 3529 &hash_single_size_params); 3530 3531 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE); 3532 err = devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD, 3533 kvd_size, MLXSW_SP_RESOURCE_KVD, 3534 DEVLINK_RESOURCE_ID_PARENT_TOP, 3535 &kvd_size_params); 3536 if (err) 3537 return err; 3538 3539 linear_size = profile->kvd_linear_size; 3540 err = devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_LINEAR, 3541 linear_size, 3542 MLXSW_SP_RESOURCE_KVD_LINEAR, 3543 MLXSW_SP_RESOURCE_KVD, 3544 &linear_size_params); 3545 if (err) 3546 return err; 3547 3548 err = mlxsw_sp1_kvdl_resources_register(mlxsw_core); 3549 if (err) 3550 return err; 3551 3552 double_size = kvd_size - linear_size; 3553 double_size *= profile->kvd_hash_double_parts; 3554 double_size /= profile->kvd_hash_double_parts + 3555 profile->kvd_hash_single_parts; 3556 double_size = rounddown(double_size, MLXSW_SP_KVD_GRANULARITY); 3557 err = devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_DOUBLE, 3558 double_size, 3559 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE, 3560 MLXSW_SP_RESOURCE_KVD, 3561 &hash_double_size_params); 3562 if (err) 3563 return err; 3564 3565 single_size = kvd_size - double_size - linear_size; 3566 err = devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_SINGLE, 3567 single_size, 3568 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE, 3569 MLXSW_SP_RESOURCE_KVD, 3570 &hash_single_size_params); 3571 if (err) 3572 return err; 3573 3574 return 0; 3575 } 3576 3577 static int mlxsw_sp2_resources_kvd_register(struct mlxsw_core *mlxsw_core) 3578 { 3579 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3580 struct devlink_resource_size_params kvd_size_params; 3581 u32 kvd_size; 3582 3583 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE)) 3584 return -EIO; 3585 3586 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE); 3587 devlink_resource_size_params_init(&kvd_size_params, kvd_size, kvd_size, 3588 MLXSW_SP_KVD_GRANULARITY, 3589 DEVLINK_RESOURCE_UNIT_ENTRY); 3590 3591 return devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD, 3592 kvd_size, MLXSW_SP_RESOURCE_KVD, 3593 DEVLINK_RESOURCE_ID_PARENT_TOP, 3594 &kvd_size_params); 3595 } 3596 3597 static int mlxsw_sp_resources_span_register(struct mlxsw_core *mlxsw_core) 3598 { 3599 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3600 struct devlink_resource_size_params span_size_params; 3601 u32 max_span; 3602 3603 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_SPAN)) 3604 return -EIO; 3605 3606 max_span = MLXSW_CORE_RES_GET(mlxsw_core, MAX_SPAN); 3607 devlink_resource_size_params_init(&span_size_params, max_span, max_span, 3608 1, DEVLINK_RESOURCE_UNIT_ENTRY); 3609 3610 return devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_SPAN, 3611 max_span, MLXSW_SP_RESOURCE_SPAN, 3612 DEVLINK_RESOURCE_ID_PARENT_TOP, 3613 &span_size_params); 3614 } 3615 3616 static int 3617 mlxsw_sp_resources_rif_mac_profile_register(struct mlxsw_core *mlxsw_core) 3618 { 3619 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3620 struct devlink_resource_size_params size_params; 3621 u8 max_rif_mac_profiles; 3622 3623 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_RIF_MAC_PROFILES)) 3624 max_rif_mac_profiles = 1; 3625 else 3626 max_rif_mac_profiles = MLXSW_CORE_RES_GET(mlxsw_core, 3627 MAX_RIF_MAC_PROFILES); 3628 devlink_resource_size_params_init(&size_params, max_rif_mac_profiles, 3629 max_rif_mac_profiles, 1, 3630 DEVLINK_RESOURCE_UNIT_ENTRY); 3631 3632 return devl_resource_register(devlink, 3633 "rif_mac_profiles", 3634 max_rif_mac_profiles, 3635 MLXSW_SP_RESOURCE_RIF_MAC_PROFILES, 3636 DEVLINK_RESOURCE_ID_PARENT_TOP, 3637 &size_params); 3638 } 3639 3640 static int mlxsw_sp_resources_rifs_register(struct mlxsw_core *mlxsw_core) 3641 { 3642 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3643 struct devlink_resource_size_params size_params; 3644 u64 max_rifs; 3645 3646 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_RIFS)) 3647 return -EIO; 3648 3649 max_rifs = MLXSW_CORE_RES_GET(mlxsw_core, MAX_RIFS); 3650 devlink_resource_size_params_init(&size_params, max_rifs, max_rifs, 3651 1, DEVLINK_RESOURCE_UNIT_ENTRY); 3652 3653 return devl_resource_register(devlink, "rifs", max_rifs, 3654 MLXSW_SP_RESOURCE_RIFS, 3655 DEVLINK_RESOURCE_ID_PARENT_TOP, 3656 &size_params); 3657 } 3658 3659 static int 3660 mlxsw_sp_resources_port_range_register(struct mlxsw_core *mlxsw_core) 3661 { 3662 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3663 struct devlink_resource_size_params size_params; 3664 u64 max; 3665 3666 if (!MLXSW_CORE_RES_VALID(mlxsw_core, ACL_MAX_L4_PORT_RANGE)) 3667 return -EIO; 3668 3669 max = MLXSW_CORE_RES_GET(mlxsw_core, ACL_MAX_L4_PORT_RANGE); 3670 devlink_resource_size_params_init(&size_params, max, max, 1, 3671 DEVLINK_RESOURCE_UNIT_ENTRY); 3672 3673 return devl_resource_register(devlink, "port_range_registers", max, 3674 MLXSW_SP_RESOURCE_PORT_RANGE_REGISTERS, 3675 DEVLINK_RESOURCE_ID_PARENT_TOP, 3676 &size_params); 3677 } 3678 3679 static int mlxsw_sp1_resources_register(struct mlxsw_core *mlxsw_core) 3680 { 3681 int err; 3682 3683 err = mlxsw_sp1_resources_kvd_register(mlxsw_core); 3684 if (err) 3685 return err; 3686 3687 err = mlxsw_sp_resources_span_register(mlxsw_core); 3688 if (err) 3689 goto err_resources_span_register; 3690 3691 err = mlxsw_sp_counter_resources_register(mlxsw_core); 3692 if (err) 3693 goto err_resources_counter_register; 3694 3695 err = mlxsw_sp_policer_resources_register(mlxsw_core); 3696 if (err) 3697 goto err_policer_resources_register; 3698 3699 err = mlxsw_sp_resources_rif_mac_profile_register(mlxsw_core); 3700 if (err) 3701 goto err_resources_rif_mac_profile_register; 3702 3703 err = mlxsw_sp_resources_rifs_register(mlxsw_core); 3704 if (err) 3705 goto err_resources_rifs_register; 3706 3707 err = mlxsw_sp_resources_port_range_register(mlxsw_core); 3708 if (err) 3709 goto err_resources_port_range_register; 3710 3711 return 0; 3712 3713 err_resources_port_range_register: 3714 err_resources_rifs_register: 3715 err_resources_rif_mac_profile_register: 3716 err_policer_resources_register: 3717 err_resources_counter_register: 3718 err_resources_span_register: 3719 devl_resources_unregister(priv_to_devlink(mlxsw_core)); 3720 return err; 3721 } 3722 3723 static int mlxsw_sp2_resources_register(struct mlxsw_core *mlxsw_core) 3724 { 3725 int err; 3726 3727 err = mlxsw_sp2_resources_kvd_register(mlxsw_core); 3728 if (err) 3729 return err; 3730 3731 err = mlxsw_sp_resources_span_register(mlxsw_core); 3732 if (err) 3733 goto err_resources_span_register; 3734 3735 err = mlxsw_sp_counter_resources_register(mlxsw_core); 3736 if (err) 3737 goto err_resources_counter_register; 3738 3739 err = mlxsw_sp_policer_resources_register(mlxsw_core); 3740 if (err) 3741 goto err_policer_resources_register; 3742 3743 err = mlxsw_sp_resources_rif_mac_profile_register(mlxsw_core); 3744 if (err) 3745 goto err_resources_rif_mac_profile_register; 3746 3747 err = mlxsw_sp_resources_rifs_register(mlxsw_core); 3748 if (err) 3749 goto err_resources_rifs_register; 3750 3751 err = mlxsw_sp_resources_port_range_register(mlxsw_core); 3752 if (err) 3753 goto err_resources_port_range_register; 3754 3755 return 0; 3756 3757 err_resources_port_range_register: 3758 err_resources_rifs_register: 3759 err_resources_rif_mac_profile_register: 3760 err_policer_resources_register: 3761 err_resources_counter_register: 3762 err_resources_span_register: 3763 devl_resources_unregister(priv_to_devlink(mlxsw_core)); 3764 return err; 3765 } 3766 3767 static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core, 3768 const struct mlxsw_config_profile *profile, 3769 u64 *p_single_size, u64 *p_double_size, 3770 u64 *p_linear_size) 3771 { 3772 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3773 u32 double_size; 3774 int err; 3775 3776 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SINGLE_MIN_SIZE) || 3777 !MLXSW_CORE_RES_VALID(mlxsw_core, KVD_DOUBLE_MIN_SIZE)) 3778 return -EIO; 3779 3780 /* The hash part is what left of the kvd without the 3781 * linear part. It is split to the single size and 3782 * double size by the parts ratio from the profile. 3783 * Both sizes must be a multiplications of the 3784 * granularity from the profile. In case the user 3785 * provided the sizes they are obtained via devlink. 3786 */ 3787 err = devl_resource_size_get(devlink, 3788 MLXSW_SP_RESOURCE_KVD_LINEAR, 3789 p_linear_size); 3790 if (err) 3791 *p_linear_size = profile->kvd_linear_size; 3792 3793 err = devl_resource_size_get(devlink, 3794 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE, 3795 p_double_size); 3796 if (err) { 3797 double_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) - 3798 *p_linear_size; 3799 double_size *= profile->kvd_hash_double_parts; 3800 double_size /= profile->kvd_hash_double_parts + 3801 profile->kvd_hash_single_parts; 3802 *p_double_size = rounddown(double_size, 3803 MLXSW_SP_KVD_GRANULARITY); 3804 } 3805 3806 err = devl_resource_size_get(devlink, 3807 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE, 3808 p_single_size); 3809 if (err) 3810 *p_single_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) - 3811 *p_double_size - *p_linear_size; 3812 3813 /* Check results are legal. */ 3814 if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) || 3815 *p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) || 3816 MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size) 3817 return -EIO; 3818 3819 return 0; 3820 } 3821 3822 static void mlxsw_sp_ptp_transmitted(struct mlxsw_core *mlxsw_core, 3823 struct sk_buff *skb, u16 local_port) 3824 { 3825 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3826 3827 skb_pull(skb, MLXSW_TXHDR_LEN); 3828 mlxsw_sp->ptp_ops->transmitted(mlxsw_sp, skb, local_port); 3829 } 3830 3831 static struct mlxsw_driver mlxsw_sp1_driver = { 3832 .kind = mlxsw_sp1_driver_name, 3833 .priv_size = sizeof(struct mlxsw_sp), 3834 .fw_req_rev = &mlxsw_sp1_fw_rev, 3835 .fw_filename = MLXSW_SP1_FW_FILENAME, 3836 .init = mlxsw_sp1_init, 3837 .fini = mlxsw_sp_fini, 3838 .port_split = mlxsw_sp_port_split, 3839 .port_unsplit = mlxsw_sp_port_unsplit, 3840 .sb_pool_get = mlxsw_sp_sb_pool_get, 3841 .sb_pool_set = mlxsw_sp_sb_pool_set, 3842 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get, 3843 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set, 3844 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get, 3845 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set, 3846 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot, 3847 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear, 3848 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get, 3849 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get, 3850 .trap_init = mlxsw_sp_trap_init, 3851 .trap_fini = mlxsw_sp_trap_fini, 3852 .trap_action_set = mlxsw_sp_trap_action_set, 3853 .trap_group_init = mlxsw_sp_trap_group_init, 3854 .trap_group_set = mlxsw_sp_trap_group_set, 3855 .trap_policer_init = mlxsw_sp_trap_policer_init, 3856 .trap_policer_fini = mlxsw_sp_trap_policer_fini, 3857 .trap_policer_set = mlxsw_sp_trap_policer_set, 3858 .trap_policer_counter_get = mlxsw_sp_trap_policer_counter_get, 3859 .resources_register = mlxsw_sp1_resources_register, 3860 .kvd_sizes_get = mlxsw_sp_kvd_sizes_get, 3861 .ptp_transmitted = mlxsw_sp_ptp_transmitted, 3862 .profile = &mlxsw_sp1_config_profile, 3863 .sdq_supports_cqe_v2 = false, 3864 }; 3865 3866 static struct mlxsw_driver mlxsw_sp2_driver = { 3867 .kind = mlxsw_sp2_driver_name, 3868 .priv_size = sizeof(struct mlxsw_sp), 3869 .fw_req_rev = &mlxsw_sp2_fw_rev, 3870 .fw_filename = MLXSW_SP2_FW_FILENAME, 3871 .init = mlxsw_sp2_init, 3872 .fini = mlxsw_sp_fini, 3873 .port_split = mlxsw_sp_port_split, 3874 .port_unsplit = mlxsw_sp_port_unsplit, 3875 .ports_remove_selected = mlxsw_sp_ports_remove_selected, 3876 .sb_pool_get = mlxsw_sp_sb_pool_get, 3877 .sb_pool_set = mlxsw_sp_sb_pool_set, 3878 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get, 3879 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set, 3880 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get, 3881 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set, 3882 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot, 3883 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear, 3884 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get, 3885 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get, 3886 .trap_init = mlxsw_sp_trap_init, 3887 .trap_fini = mlxsw_sp_trap_fini, 3888 .trap_action_set = mlxsw_sp_trap_action_set, 3889 .trap_group_init = mlxsw_sp_trap_group_init, 3890 .trap_group_set = mlxsw_sp_trap_group_set, 3891 .trap_policer_init = mlxsw_sp_trap_policer_init, 3892 .trap_policer_fini = mlxsw_sp_trap_policer_fini, 3893 .trap_policer_set = mlxsw_sp_trap_policer_set, 3894 .trap_policer_counter_get = mlxsw_sp_trap_policer_counter_get, 3895 .resources_register = mlxsw_sp2_resources_register, 3896 .ptp_transmitted = mlxsw_sp_ptp_transmitted, 3897 .profile = &mlxsw_sp2_config_profile, 3898 .sdq_supports_cqe_v2 = true, 3899 }; 3900 3901 static struct mlxsw_driver mlxsw_sp3_driver = { 3902 .kind = mlxsw_sp3_driver_name, 3903 .priv_size = sizeof(struct mlxsw_sp), 3904 .fw_req_rev = &mlxsw_sp3_fw_rev, 3905 .fw_filename = MLXSW_SP3_FW_FILENAME, 3906 .init = mlxsw_sp3_init, 3907 .fini = mlxsw_sp_fini, 3908 .port_split = mlxsw_sp_port_split, 3909 .port_unsplit = mlxsw_sp_port_unsplit, 3910 .ports_remove_selected = mlxsw_sp_ports_remove_selected, 3911 .sb_pool_get = mlxsw_sp_sb_pool_get, 3912 .sb_pool_set = mlxsw_sp_sb_pool_set, 3913 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get, 3914 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set, 3915 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get, 3916 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set, 3917 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot, 3918 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear, 3919 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get, 3920 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get, 3921 .trap_init = mlxsw_sp_trap_init, 3922 .trap_fini = mlxsw_sp_trap_fini, 3923 .trap_action_set = mlxsw_sp_trap_action_set, 3924 .trap_group_init = mlxsw_sp_trap_group_init, 3925 .trap_group_set = mlxsw_sp_trap_group_set, 3926 .trap_policer_init = mlxsw_sp_trap_policer_init, 3927 .trap_policer_fini = mlxsw_sp_trap_policer_fini, 3928 .trap_policer_set = mlxsw_sp_trap_policer_set, 3929 .trap_policer_counter_get = mlxsw_sp_trap_policer_counter_get, 3930 .resources_register = mlxsw_sp2_resources_register, 3931 .ptp_transmitted = mlxsw_sp_ptp_transmitted, 3932 .profile = &mlxsw_sp2_config_profile, 3933 .sdq_supports_cqe_v2 = true, 3934 }; 3935 3936 static struct mlxsw_driver mlxsw_sp4_driver = { 3937 .kind = mlxsw_sp4_driver_name, 3938 .priv_size = sizeof(struct mlxsw_sp), 3939 .init = mlxsw_sp4_init, 3940 .fini = mlxsw_sp_fini, 3941 .port_split = mlxsw_sp_port_split, 3942 .port_unsplit = mlxsw_sp_port_unsplit, 3943 .ports_remove_selected = mlxsw_sp_ports_remove_selected, 3944 .sb_pool_get = mlxsw_sp_sb_pool_get, 3945 .sb_pool_set = mlxsw_sp_sb_pool_set, 3946 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get, 3947 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set, 3948 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get, 3949 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set, 3950 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot, 3951 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear, 3952 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get, 3953 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get, 3954 .trap_init = mlxsw_sp_trap_init, 3955 .trap_fini = mlxsw_sp_trap_fini, 3956 .trap_action_set = mlxsw_sp_trap_action_set, 3957 .trap_group_init = mlxsw_sp_trap_group_init, 3958 .trap_group_set = mlxsw_sp_trap_group_set, 3959 .trap_policer_init = mlxsw_sp_trap_policer_init, 3960 .trap_policer_fini = mlxsw_sp_trap_policer_fini, 3961 .trap_policer_set = mlxsw_sp_trap_policer_set, 3962 .trap_policer_counter_get = mlxsw_sp_trap_policer_counter_get, 3963 .resources_register = mlxsw_sp2_resources_register, 3964 .ptp_transmitted = mlxsw_sp_ptp_transmitted, 3965 .profile = &mlxsw_sp4_config_profile, 3966 .sdq_supports_cqe_v2 = true, 3967 }; 3968 3969 bool mlxsw_sp_port_dev_check(const struct net_device *dev) 3970 { 3971 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops; 3972 } 3973 3974 static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, 3975 struct netdev_nested_priv *priv) 3976 { 3977 int ret = 0; 3978 3979 if (mlxsw_sp_port_dev_check(lower_dev)) { 3980 priv->data = (void *)netdev_priv(lower_dev); 3981 ret = 1; 3982 } 3983 3984 return ret; 3985 } 3986 3987 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev) 3988 { 3989 struct netdev_nested_priv priv = { 3990 .data = NULL, 3991 }; 3992 3993 if (mlxsw_sp_port_dev_check(dev)) 3994 return netdev_priv(dev); 3995 3996 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &priv); 3997 3998 return (struct mlxsw_sp_port *)priv.data; 3999 } 4000 4001 struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev) 4002 { 4003 struct mlxsw_sp_port *mlxsw_sp_port; 4004 4005 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev); 4006 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL; 4007 } 4008 4009 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev) 4010 { 4011 struct netdev_nested_priv priv = { 4012 .data = NULL, 4013 }; 4014 4015 if (mlxsw_sp_port_dev_check(dev)) 4016 return netdev_priv(dev); 4017 4018 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk, 4019 &priv); 4020 4021 return (struct mlxsw_sp_port *)priv.data; 4022 } 4023 4024 int mlxsw_sp_parsing_depth_inc(struct mlxsw_sp *mlxsw_sp) 4025 { 4026 char mprs_pl[MLXSW_REG_MPRS_LEN]; 4027 int err = 0; 4028 4029 mutex_lock(&mlxsw_sp->parsing.lock); 4030 4031 if (refcount_inc_not_zero(&mlxsw_sp->parsing.parsing_depth_ref)) 4032 goto out_unlock; 4033 4034 mlxsw_reg_mprs_pack(mprs_pl, MLXSW_SP_INCREASED_PARSING_DEPTH, 4035 mlxsw_sp->parsing.vxlan_udp_dport); 4036 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mprs), mprs_pl); 4037 if (err) 4038 goto out_unlock; 4039 4040 mlxsw_sp->parsing.parsing_depth = MLXSW_SP_INCREASED_PARSING_DEPTH; 4041 refcount_set(&mlxsw_sp->parsing.parsing_depth_ref, 1); 4042 4043 out_unlock: 4044 mutex_unlock(&mlxsw_sp->parsing.lock); 4045 return err; 4046 } 4047 4048 void mlxsw_sp_parsing_depth_dec(struct mlxsw_sp *mlxsw_sp) 4049 { 4050 char mprs_pl[MLXSW_REG_MPRS_LEN]; 4051 4052 mutex_lock(&mlxsw_sp->parsing.lock); 4053 4054 if (!refcount_dec_and_test(&mlxsw_sp->parsing.parsing_depth_ref)) 4055 goto out_unlock; 4056 4057 mlxsw_reg_mprs_pack(mprs_pl, MLXSW_SP_DEFAULT_PARSING_DEPTH, 4058 mlxsw_sp->parsing.vxlan_udp_dport); 4059 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mprs), mprs_pl); 4060 mlxsw_sp->parsing.parsing_depth = MLXSW_SP_DEFAULT_PARSING_DEPTH; 4061 4062 out_unlock: 4063 mutex_unlock(&mlxsw_sp->parsing.lock); 4064 } 4065 4066 int mlxsw_sp_parsing_vxlan_udp_dport_set(struct mlxsw_sp *mlxsw_sp, 4067 __be16 udp_dport) 4068 { 4069 char mprs_pl[MLXSW_REG_MPRS_LEN]; 4070 int err; 4071 4072 mutex_lock(&mlxsw_sp->parsing.lock); 4073 4074 mlxsw_reg_mprs_pack(mprs_pl, mlxsw_sp->parsing.parsing_depth, 4075 be16_to_cpu(udp_dport)); 4076 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mprs), mprs_pl); 4077 if (err) 4078 goto out_unlock; 4079 4080 mlxsw_sp->parsing.vxlan_udp_dport = be16_to_cpu(udp_dport); 4081 4082 out_unlock: 4083 mutex_unlock(&mlxsw_sp->parsing.lock); 4084 return err; 4085 } 4086 4087 static void 4088 mlxsw_sp_port_lag_uppers_cleanup(struct mlxsw_sp_port *mlxsw_sp_port, 4089 struct net_device *lag_dev) 4090 { 4091 struct net_device *br_dev = netdev_master_upper_dev_get(lag_dev); 4092 struct net_device *upper_dev; 4093 struct list_head *iter; 4094 4095 if (netif_is_bridge_port(lag_dev)) 4096 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, lag_dev, br_dev); 4097 4098 netdev_for_each_upper_dev_rcu(lag_dev, upper_dev, iter) { 4099 if (!netif_is_bridge_port(upper_dev)) 4100 continue; 4101 br_dev = netdev_master_upper_dev_get(upper_dev); 4102 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev, br_dev); 4103 } 4104 } 4105 4106 static struct mlxsw_sp_lag * 4107 mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, struct net_device *lag_dev, 4108 struct netlink_ext_ack *extack) 4109 { 4110 char sldr_pl[MLXSW_REG_SLDR_LEN]; 4111 struct mlxsw_sp_lag *lag; 4112 u16 lag_id; 4113 int i, err; 4114 4115 for (i = 0; i < mlxsw_sp->max_lag; i++) { 4116 if (!mlxsw_sp->lags[i].dev) 4117 break; 4118 } 4119 4120 if (i == mlxsw_sp->max_lag) { 4121 NL_SET_ERR_MSG_MOD(extack, 4122 "Exceeded number of supported LAG devices"); 4123 return ERR_PTR(-EBUSY); 4124 } 4125 4126 lag_id = i; 4127 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id); 4128 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 4129 if (err) 4130 return ERR_PTR(err); 4131 4132 lag = &mlxsw_sp->lags[lag_id]; 4133 lag->lag_id = lag_id; 4134 lag->dev = lag_dev; 4135 refcount_set(&lag->ref_count, 1); 4136 4137 return lag; 4138 } 4139 4140 static int 4141 mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, struct mlxsw_sp_lag *lag) 4142 { 4143 char sldr_pl[MLXSW_REG_SLDR_LEN]; 4144 4145 lag->dev = NULL; 4146 4147 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag->lag_id); 4148 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 4149 } 4150 4151 static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port, 4152 u16 lag_id, u8 port_index) 4153 { 4154 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4155 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 4156 4157 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port, 4158 lag_id, port_index); 4159 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 4160 } 4161 4162 static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port, 4163 u16 lag_id) 4164 { 4165 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4166 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 4167 4168 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port, 4169 lag_id); 4170 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 4171 } 4172 4173 static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port, 4174 u16 lag_id) 4175 { 4176 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4177 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 4178 4179 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port, 4180 lag_id); 4181 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 4182 } 4183 4184 static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port, 4185 u16 lag_id) 4186 { 4187 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4188 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 4189 4190 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port, 4191 lag_id); 4192 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 4193 } 4194 4195 static struct mlxsw_sp_lag * 4196 mlxsw_sp_lag_find(struct mlxsw_sp *mlxsw_sp, struct net_device *lag_dev) 4197 { 4198 int i; 4199 4200 for (i = 0; i < mlxsw_sp->max_lag; i++) { 4201 if (!mlxsw_sp->lags[i].dev) 4202 continue; 4203 4204 if (mlxsw_sp->lags[i].dev == lag_dev) 4205 return &mlxsw_sp->lags[i]; 4206 } 4207 4208 return NULL; 4209 } 4210 4211 static struct mlxsw_sp_lag * 4212 mlxsw_sp_lag_get(struct mlxsw_sp *mlxsw_sp, struct net_device *lag_dev, 4213 struct netlink_ext_ack *extack) 4214 { 4215 struct mlxsw_sp_lag *lag; 4216 4217 lag = mlxsw_sp_lag_find(mlxsw_sp, lag_dev); 4218 if (lag) { 4219 refcount_inc(&lag->ref_count); 4220 return lag; 4221 } 4222 4223 return mlxsw_sp_lag_create(mlxsw_sp, lag_dev, extack); 4224 } 4225 4226 static void 4227 mlxsw_sp_lag_put(struct mlxsw_sp *mlxsw_sp, struct mlxsw_sp_lag *lag) 4228 { 4229 if (!refcount_dec_and_test(&lag->ref_count)) 4230 return; 4231 4232 mlxsw_sp_lag_destroy(mlxsw_sp, lag); 4233 } 4234 4235 static bool 4236 mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp, 4237 struct net_device *lag_dev, 4238 struct netdev_lag_upper_info *lag_upper_info, 4239 struct netlink_ext_ack *extack) 4240 { 4241 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 4242 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type"); 4243 return false; 4244 } 4245 return true; 4246 } 4247 4248 static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp, 4249 u16 lag_id, u8 *p_port_index) 4250 { 4251 u64 max_lag_members; 4252 int i; 4253 4254 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core, 4255 MAX_LAG_MEMBERS); 4256 for (i = 0; i < max_lag_members; i++) { 4257 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) { 4258 *p_port_index = i; 4259 return 0; 4260 } 4261 } 4262 return -EBUSY; 4263 } 4264 4265 static int mlxsw_sp_lag_uppers_bridge_join(struct mlxsw_sp_port *mlxsw_sp_port, 4266 struct net_device *lag_dev, 4267 struct netlink_ext_ack *extack) 4268 { 4269 struct net_device *upper_dev; 4270 struct net_device *master; 4271 struct list_head *iter; 4272 int done = 0; 4273 int err; 4274 4275 master = netdev_master_upper_dev_get(lag_dev); 4276 if (master && netif_is_bridge_master(master)) { 4277 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port, lag_dev, master, 4278 extack); 4279 if (err) 4280 return err; 4281 } 4282 4283 netdev_for_each_upper_dev_rcu(lag_dev, upper_dev, iter) { 4284 if (!is_vlan_dev(upper_dev)) 4285 continue; 4286 4287 master = netdev_master_upper_dev_get(upper_dev); 4288 if (master && netif_is_bridge_master(master)) { 4289 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port, 4290 upper_dev, master, 4291 extack); 4292 if (err) 4293 goto err_port_bridge_join; 4294 } 4295 4296 ++done; 4297 } 4298 4299 return 0; 4300 4301 err_port_bridge_join: 4302 netdev_for_each_upper_dev_rcu(lag_dev, upper_dev, iter) { 4303 if (!is_vlan_dev(upper_dev)) 4304 continue; 4305 4306 master = netdev_master_upper_dev_get(upper_dev); 4307 if (!master || !netif_is_bridge_master(master)) 4308 continue; 4309 4310 if (!done--) 4311 break; 4312 4313 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev, master); 4314 } 4315 4316 master = netdev_master_upper_dev_get(lag_dev); 4317 if (master && netif_is_bridge_master(master)) 4318 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, lag_dev, master); 4319 4320 return err; 4321 } 4322 4323 static void 4324 mlxsw_sp_lag_uppers_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_port, 4325 struct net_device *lag_dev) 4326 { 4327 struct net_device *upper_dev; 4328 struct net_device *master; 4329 struct list_head *iter; 4330 4331 netdev_for_each_upper_dev_rcu(lag_dev, upper_dev, iter) { 4332 if (!is_vlan_dev(upper_dev)) 4333 continue; 4334 4335 master = netdev_master_upper_dev_get(upper_dev); 4336 if (!master) 4337 continue; 4338 4339 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev, master); 4340 } 4341 4342 master = netdev_master_upper_dev_get(lag_dev); 4343 if (master) 4344 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, lag_dev, master); 4345 } 4346 4347 static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port, 4348 struct net_device *lag_dev, 4349 struct netlink_ext_ack *extack) 4350 { 4351 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4352 struct mlxsw_sp_lag *lag; 4353 u16 lag_id; 4354 u8 port_index; 4355 int err; 4356 4357 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_dev, extack); 4358 if (IS_ERR(lag)) 4359 return PTR_ERR(lag); 4360 4361 lag_id = lag->lag_id; 4362 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index); 4363 if (err) 4364 return err; 4365 4366 err = mlxsw_sp_lag_uppers_bridge_join(mlxsw_sp_port, lag_dev, 4367 extack); 4368 if (err) 4369 goto err_lag_uppers_bridge_join; 4370 4371 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index); 4372 if (err) 4373 goto err_col_port_add; 4374 4375 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index, 4376 mlxsw_sp_port->local_port); 4377 mlxsw_sp_port->lag_id = lag_id; 4378 mlxsw_sp_port->lagged = 1; 4379 4380 err = mlxsw_sp_fid_port_join_lag(mlxsw_sp_port); 4381 if (err) 4382 goto err_fid_port_join_lag; 4383 4384 /* Port is no longer usable as a router interface */ 4385 if (mlxsw_sp_port->default_vlan->fid) 4386 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port->default_vlan); 4387 4388 /* Join a router interface configured on the LAG, if exists */ 4389 err = mlxsw_sp_router_port_join_lag(mlxsw_sp_port, lag_dev, 4390 extack); 4391 if (err) 4392 goto err_router_join; 4393 4394 err = mlxsw_sp_netdevice_enslavement_replay(mlxsw_sp, lag_dev, extack); 4395 if (err) 4396 goto err_replay; 4397 4398 return 0; 4399 4400 err_replay: 4401 mlxsw_sp_router_port_leave_lag(mlxsw_sp_port, lag_dev); 4402 err_router_join: 4403 mlxsw_sp_fid_port_leave_lag(mlxsw_sp_port); 4404 err_fid_port_join_lag: 4405 mlxsw_sp_port->lagged = 0; 4406 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id, 4407 mlxsw_sp_port->local_port); 4408 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id); 4409 err_col_port_add: 4410 mlxsw_sp_lag_uppers_bridge_leave(mlxsw_sp_port, lag_dev); 4411 err_lag_uppers_bridge_join: 4412 mlxsw_sp_lag_put(mlxsw_sp, lag); 4413 return err; 4414 } 4415 4416 static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port, 4417 struct net_device *lag_dev) 4418 { 4419 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4420 u16 lag_id = mlxsw_sp_port->lag_id; 4421 struct mlxsw_sp_lag *lag; 4422 4423 if (!mlxsw_sp_port->lagged) 4424 return; 4425 lag = &mlxsw_sp->lags[lag_id]; 4426 4427 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id); 4428 4429 /* Any VLANs configured on the port are no longer valid */ 4430 mlxsw_sp_port_vlan_flush(mlxsw_sp_port, false); 4431 mlxsw_sp_port_vlan_cleanup(mlxsw_sp_port->default_vlan); 4432 /* Make the LAG and its directly linked uppers leave bridges they 4433 * are memeber in 4434 */ 4435 mlxsw_sp_port_lag_uppers_cleanup(mlxsw_sp_port, lag_dev); 4436 4437 mlxsw_sp_fid_port_leave_lag(mlxsw_sp_port); 4438 4439 mlxsw_sp_lag_put(mlxsw_sp, lag); 4440 4441 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id, 4442 mlxsw_sp_port->local_port); 4443 mlxsw_sp_port->lagged = 0; 4444 4445 /* Make sure untagged frames are allowed to ingress */ 4446 mlxsw_sp_port_pvid_set(mlxsw_sp_port, MLXSW_SP_DEFAULT_VID, 4447 ETH_P_8021Q); 4448 } 4449 4450 static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port, 4451 u16 lag_id) 4452 { 4453 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4454 char sldr_pl[MLXSW_REG_SLDR_LEN]; 4455 4456 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id, 4457 mlxsw_sp_port->local_port); 4458 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 4459 } 4460 4461 static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port, 4462 u16 lag_id) 4463 { 4464 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4465 char sldr_pl[MLXSW_REG_SLDR_LEN]; 4466 4467 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id, 4468 mlxsw_sp_port->local_port); 4469 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 4470 } 4471 4472 static int 4473 mlxsw_sp_port_lag_col_dist_enable(struct mlxsw_sp_port *mlxsw_sp_port) 4474 { 4475 int err; 4476 4477 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, 4478 mlxsw_sp_port->lag_id); 4479 if (err) 4480 return err; 4481 4482 err = mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, mlxsw_sp_port->lag_id); 4483 if (err) 4484 goto err_dist_port_add; 4485 4486 return 0; 4487 4488 err_dist_port_add: 4489 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, mlxsw_sp_port->lag_id); 4490 return err; 4491 } 4492 4493 static int 4494 mlxsw_sp_port_lag_col_dist_disable(struct mlxsw_sp_port *mlxsw_sp_port) 4495 { 4496 int err; 4497 4498 err = mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port, 4499 mlxsw_sp_port->lag_id); 4500 if (err) 4501 return err; 4502 4503 err = mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, 4504 mlxsw_sp_port->lag_id); 4505 if (err) 4506 goto err_col_port_disable; 4507 4508 return 0; 4509 4510 err_col_port_disable: 4511 mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, mlxsw_sp_port->lag_id); 4512 return err; 4513 } 4514 4515 static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port, 4516 struct netdev_lag_lower_state_info *info) 4517 { 4518 if (info->tx_enabled) 4519 return mlxsw_sp_port_lag_col_dist_enable(mlxsw_sp_port); 4520 else 4521 return mlxsw_sp_port_lag_col_dist_disable(mlxsw_sp_port); 4522 } 4523 4524 static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, 4525 bool enable) 4526 { 4527 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4528 enum mlxsw_reg_spms_state spms_state; 4529 char *spms_pl; 4530 u16 vid; 4531 int err; 4532 4533 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING : 4534 MLXSW_REG_SPMS_STATE_DISCARDING; 4535 4536 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL); 4537 if (!spms_pl) 4538 return -ENOMEM; 4539 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port); 4540 4541 for (vid = 0; vid < VLAN_N_VID; vid++) 4542 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state); 4543 4544 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl); 4545 kfree(spms_pl); 4546 return err; 4547 } 4548 4549 static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port) 4550 { 4551 u16 vid = 1; 4552 int err; 4553 4554 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true); 4555 if (err) 4556 return err; 4557 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true); 4558 if (err) 4559 goto err_port_stp_set; 4560 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 1, VLAN_N_VID - 2, 4561 true, false); 4562 if (err) 4563 goto err_port_vlan_set; 4564 4565 for (; vid <= VLAN_N_VID - 1; vid++) { 4566 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, 4567 vid, false); 4568 if (err) 4569 goto err_vid_learning_set; 4570 } 4571 4572 return 0; 4573 4574 err_vid_learning_set: 4575 for (vid--; vid >= 1; vid--) 4576 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true); 4577 err_port_vlan_set: 4578 mlxsw_sp_port_stp_set(mlxsw_sp_port, false); 4579 err_port_stp_set: 4580 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false); 4581 return err; 4582 } 4583 4584 static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port) 4585 { 4586 u16 vid; 4587 4588 for (vid = VLAN_N_VID - 1; vid >= 1; vid--) 4589 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, 4590 vid, true); 4591 4592 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 1, VLAN_N_VID - 2, 4593 false, false); 4594 mlxsw_sp_port_stp_set(mlxsw_sp_port, false); 4595 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false); 4596 } 4597 4598 static bool mlxsw_sp_bridge_has_multiple_vxlans(struct net_device *br_dev) 4599 { 4600 unsigned int num_vxlans = 0; 4601 struct net_device *dev; 4602 struct list_head *iter; 4603 4604 netdev_for_each_lower_dev(br_dev, dev, iter) { 4605 if (netif_is_vxlan(dev)) 4606 num_vxlans++; 4607 } 4608 4609 return num_vxlans > 1; 4610 } 4611 4612 static bool mlxsw_sp_bridge_vxlan_vlan_is_valid(struct net_device *br_dev) 4613 { 4614 DECLARE_BITMAP(vlans, VLAN_N_VID) = {0}; 4615 struct net_device *dev; 4616 struct list_head *iter; 4617 4618 netdev_for_each_lower_dev(br_dev, dev, iter) { 4619 u16 pvid; 4620 int err; 4621 4622 if (!netif_is_vxlan(dev)) 4623 continue; 4624 4625 err = mlxsw_sp_vxlan_mapped_vid(dev, &pvid); 4626 if (err || !pvid) 4627 continue; 4628 4629 if (test_and_set_bit(pvid, vlans)) 4630 return false; 4631 } 4632 4633 return true; 4634 } 4635 4636 static bool mlxsw_sp_bridge_vxlan_is_valid(struct net_device *br_dev, 4637 struct netlink_ext_ack *extack) 4638 { 4639 if (br_multicast_enabled(br_dev)) { 4640 NL_SET_ERR_MSG_MOD(extack, "Multicast can not be enabled on a bridge with a VxLAN device"); 4641 return false; 4642 } 4643 4644 if (!br_vlan_enabled(br_dev) && 4645 mlxsw_sp_bridge_has_multiple_vxlans(br_dev)) { 4646 NL_SET_ERR_MSG_MOD(extack, "Multiple VxLAN devices are not supported in a VLAN-unaware bridge"); 4647 return false; 4648 } 4649 4650 if (br_vlan_enabled(br_dev) && 4651 !mlxsw_sp_bridge_vxlan_vlan_is_valid(br_dev)) { 4652 NL_SET_ERR_MSG_MOD(extack, "Multiple VxLAN devices cannot have the same VLAN as PVID and egress untagged"); 4653 return false; 4654 } 4655 4656 return true; 4657 } 4658 4659 static bool mlxsw_sp_netdev_is_master(struct net_device *upper_dev, 4660 struct net_device *dev) 4661 { 4662 return upper_dev == netdev_master_upper_dev_get(dev); 4663 } 4664 4665 static int __mlxsw_sp_netdevice_event(struct mlxsw_sp *mlxsw_sp, 4666 unsigned long event, void *ptr, 4667 bool process_foreign); 4668 4669 static int mlxsw_sp_netdevice_validate_uppers(struct mlxsw_sp *mlxsw_sp, 4670 struct net_device *dev, 4671 struct netlink_ext_ack *extack) 4672 { 4673 struct net_device *upper_dev; 4674 struct list_head *iter; 4675 int err; 4676 4677 netdev_for_each_upper_dev_rcu(dev, upper_dev, iter) { 4678 struct netdev_notifier_changeupper_info info = { 4679 .info = { 4680 .dev = dev, 4681 .extack = extack, 4682 }, 4683 .master = mlxsw_sp_netdev_is_master(upper_dev, dev), 4684 .upper_dev = upper_dev, 4685 .linking = true, 4686 4687 /* upper_info is relevant for LAG devices. But we would 4688 * only need this if LAG were a valid upper above 4689 * another upper (e.g. a bridge that is a member of a 4690 * LAG), and that is never a valid configuration. So we 4691 * can keep this as NULL. 4692 */ 4693 .upper_info = NULL, 4694 }; 4695 4696 err = __mlxsw_sp_netdevice_event(mlxsw_sp, 4697 NETDEV_PRECHANGEUPPER, 4698 &info, true); 4699 if (err) 4700 return err; 4701 4702 err = mlxsw_sp_netdevice_validate_uppers(mlxsw_sp, upper_dev, 4703 extack); 4704 if (err) 4705 return err; 4706 } 4707 4708 return 0; 4709 } 4710 4711 static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev, 4712 struct net_device *dev, 4713 unsigned long event, void *ptr, 4714 bool replay_deslavement) 4715 { 4716 struct netdev_notifier_changeupper_info *info; 4717 struct mlxsw_sp_port *mlxsw_sp_port; 4718 struct netlink_ext_ack *extack; 4719 struct net_device *upper_dev; 4720 struct mlxsw_sp *mlxsw_sp; 4721 int err = 0; 4722 u16 proto; 4723 4724 mlxsw_sp_port = netdev_priv(dev); 4725 mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4726 info = ptr; 4727 extack = netdev_notifier_info_to_extack(&info->info); 4728 4729 switch (event) { 4730 case NETDEV_PRECHANGEUPPER: 4731 upper_dev = info->upper_dev; 4732 if (!is_vlan_dev(upper_dev) && 4733 !netif_is_lag_master(upper_dev) && 4734 !netif_is_bridge_master(upper_dev) && 4735 !netif_is_ovs_master(upper_dev) && 4736 !netif_is_macvlan(upper_dev) && 4737 !netif_is_l3_master(upper_dev)) { 4738 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 4739 return -EINVAL; 4740 } 4741 if (!info->linking) 4742 break; 4743 if (netif_is_bridge_master(upper_dev) && 4744 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) && 4745 mlxsw_sp_bridge_has_vxlan(upper_dev) && 4746 !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack)) 4747 return -EOPNOTSUPP; 4748 if (netdev_has_any_upper_dev(upper_dev) && 4749 (!netif_is_bridge_master(upper_dev) || 4750 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, 4751 upper_dev))) { 4752 err = mlxsw_sp_netdevice_validate_uppers(mlxsw_sp, 4753 upper_dev, 4754 extack); 4755 if (err) 4756 return err; 4757 } 4758 if (netif_is_lag_master(upper_dev) && 4759 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev, 4760 info->upper_info, extack)) 4761 return -EINVAL; 4762 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) { 4763 NL_SET_ERR_MSG_MOD(extack, "Master device is a LAG master and this device has a VLAN"); 4764 return -EINVAL; 4765 } 4766 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) && 4767 !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) { 4768 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on a LAG port"); 4769 return -EINVAL; 4770 } 4771 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) { 4772 NL_SET_ERR_MSG_MOD(extack, "Master device is an OVS master and this device has a VLAN"); 4773 return -EINVAL; 4774 } 4775 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) { 4776 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on an OVS port"); 4777 return -EINVAL; 4778 } 4779 if (netif_is_bridge_master(upper_dev)) { 4780 br_vlan_get_proto(upper_dev, &proto); 4781 if (br_vlan_enabled(upper_dev) && 4782 proto != ETH_P_8021Q && proto != ETH_P_8021AD) { 4783 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a bridge with unknown VLAN protocol is not supported"); 4784 return -EOPNOTSUPP; 4785 } 4786 if (vlan_uses_dev(lower_dev) && 4787 br_vlan_enabled(upper_dev) && 4788 proto == ETH_P_8021AD) { 4789 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port that already has a VLAN upper to an 802.1ad bridge is not supported"); 4790 return -EOPNOTSUPP; 4791 } 4792 } 4793 if (netif_is_bridge_port(lower_dev) && is_vlan_dev(upper_dev)) { 4794 struct net_device *br_dev = netdev_master_upper_dev_get(lower_dev); 4795 4796 if (br_vlan_enabled(br_dev)) { 4797 br_vlan_get_proto(br_dev, &proto); 4798 if (proto == ETH_P_8021AD) { 4799 NL_SET_ERR_MSG_MOD(extack, "VLAN uppers are not supported on a port enslaved to an 802.1ad bridge"); 4800 return -EOPNOTSUPP; 4801 } 4802 } 4803 } 4804 if (is_vlan_dev(upper_dev) && 4805 ntohs(vlan_dev_vlan_proto(upper_dev)) != ETH_P_8021Q) { 4806 NL_SET_ERR_MSG_MOD(extack, "VLAN uppers are only supported with 802.1q VLAN protocol"); 4807 return -EOPNOTSUPP; 4808 } 4809 if (is_vlan_dev(upper_dev) && mlxsw_sp_port->security) { 4810 NL_SET_ERR_MSG_MOD(extack, "VLAN uppers are not supported on a locked port"); 4811 return -EOPNOTSUPP; 4812 } 4813 break; 4814 case NETDEV_CHANGEUPPER: 4815 upper_dev = info->upper_dev; 4816 if (netif_is_bridge_master(upper_dev)) { 4817 if (info->linking) { 4818 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port, 4819 lower_dev, 4820 upper_dev, 4821 extack); 4822 } else { 4823 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, 4824 lower_dev, 4825 upper_dev); 4826 if (!replay_deslavement) 4827 break; 4828 mlxsw_sp_netdevice_deslavement_replay(mlxsw_sp, 4829 lower_dev); 4830 } 4831 } else if (netif_is_lag_master(upper_dev)) { 4832 if (info->linking) { 4833 err = mlxsw_sp_port_lag_join(mlxsw_sp_port, 4834 upper_dev, extack); 4835 } else { 4836 mlxsw_sp_port_lag_col_dist_disable(mlxsw_sp_port); 4837 mlxsw_sp_port_lag_leave(mlxsw_sp_port, 4838 upper_dev); 4839 mlxsw_sp_netdevice_deslavement_replay(mlxsw_sp, 4840 dev); 4841 } 4842 } else if (netif_is_ovs_master(upper_dev)) { 4843 if (info->linking) 4844 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port); 4845 else 4846 mlxsw_sp_port_ovs_leave(mlxsw_sp_port); 4847 } else if (netif_is_macvlan(upper_dev)) { 4848 if (!info->linking) 4849 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev); 4850 } else if (is_vlan_dev(upper_dev)) { 4851 struct net_device *br_dev; 4852 4853 if (!netif_is_bridge_port(upper_dev)) 4854 break; 4855 if (info->linking) 4856 break; 4857 br_dev = netdev_master_upper_dev_get(upper_dev); 4858 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev, 4859 br_dev); 4860 } 4861 break; 4862 } 4863 4864 return err; 4865 } 4866 4867 static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev, 4868 unsigned long event, void *ptr) 4869 { 4870 struct netdev_notifier_changelowerstate_info *info; 4871 struct mlxsw_sp_port *mlxsw_sp_port; 4872 int err; 4873 4874 mlxsw_sp_port = netdev_priv(dev); 4875 info = ptr; 4876 4877 switch (event) { 4878 case NETDEV_CHANGELOWERSTATE: 4879 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) { 4880 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port, 4881 info->lower_state_info); 4882 if (err) 4883 netdev_err(dev, "Failed to reflect link aggregation lower state change\n"); 4884 } 4885 break; 4886 } 4887 4888 return 0; 4889 } 4890 4891 static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev, 4892 struct net_device *port_dev, 4893 unsigned long event, void *ptr, 4894 bool replay_deslavement) 4895 { 4896 switch (event) { 4897 case NETDEV_PRECHANGEUPPER: 4898 case NETDEV_CHANGEUPPER: 4899 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev, 4900 event, ptr, 4901 replay_deslavement); 4902 case NETDEV_CHANGELOWERSTATE: 4903 return mlxsw_sp_netdevice_port_lower_event(port_dev, event, 4904 ptr); 4905 } 4906 4907 return 0; 4908 } 4909 4910 /* Called for LAG or its upper VLAN after the per-LAG-lower processing was done, 4911 * to do any per-LAG / per-LAG-upper processing. 4912 */ 4913 static int mlxsw_sp_netdevice_post_lag_event(struct net_device *dev, 4914 unsigned long event, 4915 void *ptr) 4916 { 4917 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(dev); 4918 struct netdev_notifier_changeupper_info *info = ptr; 4919 4920 if (!mlxsw_sp) 4921 return 0; 4922 4923 switch (event) { 4924 case NETDEV_CHANGEUPPER: 4925 if (info->linking) 4926 break; 4927 if (netif_is_bridge_master(info->upper_dev)) 4928 mlxsw_sp_netdevice_deslavement_replay(mlxsw_sp, dev); 4929 break; 4930 } 4931 return 0; 4932 } 4933 4934 static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev, 4935 unsigned long event, void *ptr) 4936 { 4937 struct net_device *dev; 4938 struct list_head *iter; 4939 int ret; 4940 4941 netdev_for_each_lower_dev(lag_dev, dev, iter) { 4942 if (mlxsw_sp_port_dev_check(dev)) { 4943 ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event, 4944 ptr, false); 4945 if (ret) 4946 return ret; 4947 } 4948 } 4949 4950 return mlxsw_sp_netdevice_post_lag_event(lag_dev, event, ptr); 4951 } 4952 4953 static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev, 4954 struct net_device *dev, 4955 unsigned long event, void *ptr, 4956 u16 vid, bool replay_deslavement) 4957 { 4958 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 4959 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4960 struct netdev_notifier_changeupper_info *info = ptr; 4961 struct netlink_ext_ack *extack; 4962 struct net_device *upper_dev; 4963 int err = 0; 4964 4965 extack = netdev_notifier_info_to_extack(&info->info); 4966 4967 switch (event) { 4968 case NETDEV_PRECHANGEUPPER: 4969 upper_dev = info->upper_dev; 4970 if (!netif_is_bridge_master(upper_dev) && 4971 !netif_is_macvlan(upper_dev) && 4972 !netif_is_l3_master(upper_dev)) { 4973 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 4974 return -EINVAL; 4975 } 4976 if (!info->linking) 4977 break; 4978 if (netif_is_bridge_master(upper_dev) && 4979 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) && 4980 mlxsw_sp_bridge_has_vxlan(upper_dev) && 4981 !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack)) 4982 return -EOPNOTSUPP; 4983 if (netdev_has_any_upper_dev(upper_dev) && 4984 (!netif_is_bridge_master(upper_dev) || 4985 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, 4986 upper_dev))) { 4987 err = mlxsw_sp_netdevice_validate_uppers(mlxsw_sp, 4988 upper_dev, 4989 extack); 4990 if (err) 4991 return err; 4992 } 4993 break; 4994 case NETDEV_CHANGEUPPER: 4995 upper_dev = info->upper_dev; 4996 if (netif_is_bridge_master(upper_dev)) { 4997 if (info->linking) { 4998 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port, 4999 vlan_dev, 5000 upper_dev, 5001 extack); 5002 } else { 5003 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, 5004 vlan_dev, 5005 upper_dev); 5006 if (!replay_deslavement) 5007 break; 5008 mlxsw_sp_netdevice_deslavement_replay(mlxsw_sp, 5009 vlan_dev); 5010 } 5011 } else if (netif_is_macvlan(upper_dev)) { 5012 if (!info->linking) 5013 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev); 5014 } 5015 break; 5016 } 5017 5018 return err; 5019 } 5020 5021 static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev, 5022 struct net_device *lag_dev, 5023 unsigned long event, 5024 void *ptr, u16 vid) 5025 { 5026 struct net_device *dev; 5027 struct list_head *iter; 5028 int ret; 5029 5030 netdev_for_each_lower_dev(lag_dev, dev, iter) { 5031 if (mlxsw_sp_port_dev_check(dev)) { 5032 ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev, 5033 event, ptr, 5034 vid, false); 5035 if (ret) 5036 return ret; 5037 } 5038 } 5039 5040 return mlxsw_sp_netdevice_post_lag_event(vlan_dev, event, ptr); 5041 } 5042 5043 static int mlxsw_sp_netdevice_bridge_vlan_event(struct mlxsw_sp *mlxsw_sp, 5044 struct net_device *vlan_dev, 5045 struct net_device *br_dev, 5046 unsigned long event, void *ptr, 5047 u16 vid, bool process_foreign) 5048 { 5049 struct netdev_notifier_changeupper_info *info = ptr; 5050 struct netlink_ext_ack *extack; 5051 struct net_device *upper_dev; 5052 5053 if (!process_foreign && !mlxsw_sp_lower_get(vlan_dev)) 5054 return 0; 5055 5056 extack = netdev_notifier_info_to_extack(&info->info); 5057 5058 switch (event) { 5059 case NETDEV_PRECHANGEUPPER: 5060 upper_dev = info->upper_dev; 5061 if (!netif_is_macvlan(upper_dev) && 5062 !netif_is_l3_master(upper_dev)) { 5063 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 5064 return -EOPNOTSUPP; 5065 } 5066 break; 5067 case NETDEV_CHANGEUPPER: 5068 upper_dev = info->upper_dev; 5069 if (info->linking) 5070 break; 5071 if (netif_is_macvlan(upper_dev)) 5072 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev); 5073 break; 5074 } 5075 5076 return 0; 5077 } 5078 5079 static int mlxsw_sp_netdevice_vlan_event(struct mlxsw_sp *mlxsw_sp, 5080 struct net_device *vlan_dev, 5081 unsigned long event, void *ptr, 5082 bool process_foreign) 5083 { 5084 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev); 5085 u16 vid = vlan_dev_vlan_id(vlan_dev); 5086 5087 if (mlxsw_sp_port_dev_check(real_dev)) 5088 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev, 5089 event, ptr, vid, 5090 true); 5091 else if (netif_is_lag_master(real_dev)) 5092 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev, 5093 real_dev, event, 5094 ptr, vid); 5095 else if (netif_is_bridge_master(real_dev)) 5096 return mlxsw_sp_netdevice_bridge_vlan_event(mlxsw_sp, vlan_dev, 5097 real_dev, event, 5098 ptr, vid, 5099 process_foreign); 5100 5101 return 0; 5102 } 5103 5104 static int mlxsw_sp_netdevice_bridge_event(struct mlxsw_sp *mlxsw_sp, 5105 struct net_device *br_dev, 5106 unsigned long event, void *ptr, 5107 bool process_foreign) 5108 { 5109 struct netdev_notifier_changeupper_info *info = ptr; 5110 struct netlink_ext_ack *extack; 5111 struct net_device *upper_dev; 5112 u16 proto; 5113 5114 if (!process_foreign && !mlxsw_sp_lower_get(br_dev)) 5115 return 0; 5116 5117 extack = netdev_notifier_info_to_extack(&info->info); 5118 5119 switch (event) { 5120 case NETDEV_PRECHANGEUPPER: 5121 upper_dev = info->upper_dev; 5122 if (!is_vlan_dev(upper_dev) && 5123 !netif_is_macvlan(upper_dev) && 5124 !netif_is_l3_master(upper_dev)) { 5125 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 5126 return -EOPNOTSUPP; 5127 } 5128 if (!info->linking) 5129 break; 5130 if (br_vlan_enabled(br_dev)) { 5131 br_vlan_get_proto(br_dev, &proto); 5132 if (proto == ETH_P_8021AD) { 5133 NL_SET_ERR_MSG_MOD(extack, "Upper devices are not supported on top of an 802.1ad bridge"); 5134 return -EOPNOTSUPP; 5135 } 5136 } 5137 if (is_vlan_dev(upper_dev) && 5138 ntohs(vlan_dev_vlan_proto(upper_dev)) != ETH_P_8021Q) { 5139 NL_SET_ERR_MSG_MOD(extack, "VLAN uppers are only supported with 802.1q VLAN protocol"); 5140 return -EOPNOTSUPP; 5141 } 5142 break; 5143 case NETDEV_CHANGEUPPER: 5144 upper_dev = info->upper_dev; 5145 if (info->linking) 5146 break; 5147 if (is_vlan_dev(upper_dev)) 5148 mlxsw_sp_rif_destroy_by_dev(mlxsw_sp, upper_dev); 5149 if (netif_is_macvlan(upper_dev)) 5150 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev); 5151 break; 5152 } 5153 5154 return 0; 5155 } 5156 5157 static int mlxsw_sp_netdevice_macvlan_event(struct net_device *macvlan_dev, 5158 unsigned long event, void *ptr) 5159 { 5160 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(macvlan_dev); 5161 struct netdev_notifier_changeupper_info *info = ptr; 5162 struct netlink_ext_ack *extack; 5163 struct net_device *upper_dev; 5164 5165 if (!mlxsw_sp || event != NETDEV_PRECHANGEUPPER) 5166 return 0; 5167 5168 extack = netdev_notifier_info_to_extack(&info->info); 5169 upper_dev = info->upper_dev; 5170 5171 if (!netif_is_l3_master(upper_dev)) { 5172 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 5173 return -EOPNOTSUPP; 5174 } 5175 5176 return 0; 5177 } 5178 5179 static int mlxsw_sp_netdevice_vxlan_event(struct mlxsw_sp *mlxsw_sp, 5180 struct net_device *dev, 5181 unsigned long event, void *ptr) 5182 { 5183 struct netdev_notifier_changeupper_info *cu_info; 5184 struct netdev_notifier_info *info = ptr; 5185 struct netlink_ext_ack *extack; 5186 struct net_device *upper_dev; 5187 5188 extack = netdev_notifier_info_to_extack(info); 5189 5190 switch (event) { 5191 case NETDEV_CHANGEUPPER: 5192 cu_info = container_of(info, 5193 struct netdev_notifier_changeupper_info, 5194 info); 5195 upper_dev = cu_info->upper_dev; 5196 if (!netif_is_bridge_master(upper_dev)) 5197 return 0; 5198 if (!mlxsw_sp_lower_get(upper_dev)) 5199 return 0; 5200 if (!mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack)) 5201 return -EOPNOTSUPP; 5202 if (!netif_running(dev)) 5203 return 0; 5204 if (cu_info->linking) 5205 return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev, 5206 dev, 0, extack); 5207 else 5208 mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, dev); 5209 break; 5210 case NETDEV_PRE_UP: 5211 upper_dev = netdev_master_upper_dev_get(dev); 5212 if (!upper_dev) 5213 return 0; 5214 if (!netif_is_bridge_master(upper_dev)) 5215 return 0; 5216 if (!mlxsw_sp_lower_get(upper_dev)) 5217 return 0; 5218 return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev, dev, 0, 5219 extack); 5220 case NETDEV_DOWN: 5221 upper_dev = netdev_master_upper_dev_get(dev); 5222 if (!upper_dev) 5223 return 0; 5224 if (!netif_is_bridge_master(upper_dev)) 5225 return 0; 5226 if (!mlxsw_sp_lower_get(upper_dev)) 5227 return 0; 5228 mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, dev); 5229 break; 5230 } 5231 5232 return 0; 5233 } 5234 5235 static int __mlxsw_sp_netdevice_event(struct mlxsw_sp *mlxsw_sp, 5236 unsigned long event, void *ptr, 5237 bool process_foreign) 5238 { 5239 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 5240 struct mlxsw_sp_span_entry *span_entry; 5241 int err = 0; 5242 5243 if (event == NETDEV_UNREGISTER) { 5244 span_entry = mlxsw_sp_span_entry_find_by_port(mlxsw_sp, dev); 5245 if (span_entry) 5246 mlxsw_sp_span_entry_invalidate(mlxsw_sp, span_entry); 5247 } 5248 5249 if (netif_is_vxlan(dev)) 5250 err = mlxsw_sp_netdevice_vxlan_event(mlxsw_sp, dev, event, ptr); 5251 else if (mlxsw_sp_port_dev_check(dev)) 5252 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr, true); 5253 else if (netif_is_lag_master(dev)) 5254 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr); 5255 else if (is_vlan_dev(dev)) 5256 err = mlxsw_sp_netdevice_vlan_event(mlxsw_sp, dev, event, ptr, 5257 process_foreign); 5258 else if (netif_is_bridge_master(dev)) 5259 err = mlxsw_sp_netdevice_bridge_event(mlxsw_sp, dev, event, ptr, 5260 process_foreign); 5261 else if (netif_is_macvlan(dev)) 5262 err = mlxsw_sp_netdevice_macvlan_event(dev, event, ptr); 5263 5264 return err; 5265 } 5266 5267 static int mlxsw_sp_netdevice_event(struct notifier_block *nb, 5268 unsigned long event, void *ptr) 5269 { 5270 struct mlxsw_sp *mlxsw_sp; 5271 int err; 5272 5273 mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb); 5274 mlxsw_sp_span_respin(mlxsw_sp); 5275 err = __mlxsw_sp_netdevice_event(mlxsw_sp, event, ptr, false); 5276 5277 return notifier_from_errno(err); 5278 } 5279 5280 static const struct pci_device_id mlxsw_sp1_pci_id_table[] = { 5281 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0}, 5282 {0, }, 5283 }; 5284 5285 static struct pci_driver mlxsw_sp1_pci_driver = { 5286 .name = mlxsw_sp1_driver_name, 5287 .id_table = mlxsw_sp1_pci_id_table, 5288 }; 5289 5290 static const struct pci_device_id mlxsw_sp2_pci_id_table[] = { 5291 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM2), 0}, 5292 {0, }, 5293 }; 5294 5295 static struct pci_driver mlxsw_sp2_pci_driver = { 5296 .name = mlxsw_sp2_driver_name, 5297 .id_table = mlxsw_sp2_pci_id_table, 5298 }; 5299 5300 static const struct pci_device_id mlxsw_sp3_pci_id_table[] = { 5301 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM3), 0}, 5302 {0, }, 5303 }; 5304 5305 static struct pci_driver mlxsw_sp3_pci_driver = { 5306 .name = mlxsw_sp3_driver_name, 5307 .id_table = mlxsw_sp3_pci_id_table, 5308 }; 5309 5310 static const struct pci_device_id mlxsw_sp4_pci_id_table[] = { 5311 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM4), 0}, 5312 {0, }, 5313 }; 5314 5315 static struct pci_driver mlxsw_sp4_pci_driver = { 5316 .name = mlxsw_sp4_driver_name, 5317 .id_table = mlxsw_sp4_pci_id_table, 5318 }; 5319 5320 static int __init mlxsw_sp_module_init(void) 5321 { 5322 int err; 5323 5324 err = mlxsw_core_driver_register(&mlxsw_sp1_driver); 5325 if (err) 5326 return err; 5327 5328 err = mlxsw_core_driver_register(&mlxsw_sp2_driver); 5329 if (err) 5330 goto err_sp2_core_driver_register; 5331 5332 err = mlxsw_core_driver_register(&mlxsw_sp3_driver); 5333 if (err) 5334 goto err_sp3_core_driver_register; 5335 5336 err = mlxsw_core_driver_register(&mlxsw_sp4_driver); 5337 if (err) 5338 goto err_sp4_core_driver_register; 5339 5340 err = mlxsw_pci_driver_register(&mlxsw_sp1_pci_driver); 5341 if (err) 5342 goto err_sp1_pci_driver_register; 5343 5344 err = mlxsw_pci_driver_register(&mlxsw_sp2_pci_driver); 5345 if (err) 5346 goto err_sp2_pci_driver_register; 5347 5348 err = mlxsw_pci_driver_register(&mlxsw_sp3_pci_driver); 5349 if (err) 5350 goto err_sp3_pci_driver_register; 5351 5352 err = mlxsw_pci_driver_register(&mlxsw_sp4_pci_driver); 5353 if (err) 5354 goto err_sp4_pci_driver_register; 5355 5356 return 0; 5357 5358 err_sp4_pci_driver_register: 5359 mlxsw_pci_driver_unregister(&mlxsw_sp3_pci_driver); 5360 err_sp3_pci_driver_register: 5361 mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver); 5362 err_sp2_pci_driver_register: 5363 mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver); 5364 err_sp1_pci_driver_register: 5365 mlxsw_core_driver_unregister(&mlxsw_sp4_driver); 5366 err_sp4_core_driver_register: 5367 mlxsw_core_driver_unregister(&mlxsw_sp3_driver); 5368 err_sp3_core_driver_register: 5369 mlxsw_core_driver_unregister(&mlxsw_sp2_driver); 5370 err_sp2_core_driver_register: 5371 mlxsw_core_driver_unregister(&mlxsw_sp1_driver); 5372 return err; 5373 } 5374 5375 static void __exit mlxsw_sp_module_exit(void) 5376 { 5377 mlxsw_pci_driver_unregister(&mlxsw_sp4_pci_driver); 5378 mlxsw_pci_driver_unregister(&mlxsw_sp3_pci_driver); 5379 mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver); 5380 mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver); 5381 mlxsw_core_driver_unregister(&mlxsw_sp4_driver); 5382 mlxsw_core_driver_unregister(&mlxsw_sp3_driver); 5383 mlxsw_core_driver_unregister(&mlxsw_sp2_driver); 5384 mlxsw_core_driver_unregister(&mlxsw_sp1_driver); 5385 } 5386 5387 module_init(mlxsw_sp_module_init); 5388 module_exit(mlxsw_sp_module_exit); 5389 5390 MODULE_LICENSE("Dual BSD/GPL"); 5391 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>"); 5392 MODULE_DESCRIPTION("Mellanox Spectrum driver"); 5393 MODULE_DEVICE_TABLE(pci, mlxsw_sp1_pci_id_table); 5394 MODULE_DEVICE_TABLE(pci, mlxsw_sp2_pci_id_table); 5395 MODULE_DEVICE_TABLE(pci, mlxsw_sp3_pci_id_table); 5396 MODULE_DEVICE_TABLE(pci, mlxsw_sp4_pci_id_table); 5397 MODULE_FIRMWARE(MLXSW_SP1_FW_FILENAME); 5398 MODULE_FIRMWARE(MLXSW_SP2_FW_FILENAME); 5399 MODULE_FIRMWARE(MLXSW_SP3_FW_FILENAME); 5400 MODULE_FIRMWARE(MLXSW_SP_LINECARDS_INI_BUNDLE_FILENAME); 5401