1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/types.h> 7 #include <linux/pci.h> 8 #include <linux/netdevice.h> 9 #include <linux/etherdevice.h> 10 #include <linux/ethtool.h> 11 #include <linux/slab.h> 12 #include <linux/device.h> 13 #include <linux/skbuff.h> 14 #include <linux/if_vlan.h> 15 #include <linux/if_bridge.h> 16 #include <linux/workqueue.h> 17 #include <linux/jiffies.h> 18 #include <linux/bitops.h> 19 #include <linux/list.h> 20 #include <linux/notifier.h> 21 #include <linux/dcbnl.h> 22 #include <linux/inetdevice.h> 23 #include <linux/netlink.h> 24 #include <linux/random.h> 25 #include <net/switchdev.h> 26 #include <net/pkt_cls.h> 27 #include <net/tc_act/tc_mirred.h> 28 #include <net/netevent.h> 29 #include <net/tc_act/tc_sample.h> 30 #include <net/addrconf.h> 31 32 #include "spectrum.h" 33 #include "pci.h" 34 #include "core.h" 35 #include "reg.h" 36 #include "port.h" 37 #include "trap.h" 38 #include "txheader.h" 39 #include "spectrum_cnt.h" 40 #include "spectrum_dpipe.h" 41 #include "spectrum_acl_flex_actions.h" 42 #include "spectrum_span.h" 43 #include "../mlxfw/mlxfw.h" 44 45 #define MLXSW_SP_FWREV_MINOR_TO_BRANCH(minor) ((minor) / 100) 46 47 #define MLXSW_SP1_FWREV_MAJOR 13 48 #define MLXSW_SP1_FWREV_MINOR 1703 49 #define MLXSW_SP1_FWREV_SUBMINOR 4 50 #define MLXSW_SP1_FWREV_CAN_RESET_MINOR 1702 51 52 static const struct mlxsw_fw_rev mlxsw_sp1_fw_rev = { 53 .major = MLXSW_SP1_FWREV_MAJOR, 54 .minor = MLXSW_SP1_FWREV_MINOR, 55 .subminor = MLXSW_SP1_FWREV_SUBMINOR, 56 .can_reset_minor = MLXSW_SP1_FWREV_CAN_RESET_MINOR, 57 }; 58 59 #define MLXSW_SP1_FW_FILENAME \ 60 "mellanox/mlxsw_spectrum-" __stringify(MLXSW_SP1_FWREV_MAJOR) \ 61 "." __stringify(MLXSW_SP1_FWREV_MINOR) \ 62 "." __stringify(MLXSW_SP1_FWREV_SUBMINOR) ".mfa2" 63 64 static const char mlxsw_sp1_driver_name[] = "mlxsw_spectrum"; 65 static const char mlxsw_sp2_driver_name[] = "mlxsw_spectrum2"; 66 static const char mlxsw_sp_driver_version[] = "1.0"; 67 68 /* tx_hdr_version 69 * Tx header version. 70 * Must be set to 1. 71 */ 72 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4); 73 74 /* tx_hdr_ctl 75 * Packet control type. 76 * 0 - Ethernet control (e.g. EMADs, LACP) 77 * 1 - Ethernet data 78 */ 79 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2); 80 81 /* tx_hdr_proto 82 * Packet protocol type. Must be set to 1 (Ethernet). 83 */ 84 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3); 85 86 /* tx_hdr_rx_is_router 87 * Packet is sent from the router. Valid for data packets only. 88 */ 89 MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1); 90 91 /* tx_hdr_fid_valid 92 * Indicates if the 'fid' field is valid and should be used for 93 * forwarding lookup. Valid for data packets only. 94 */ 95 MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1); 96 97 /* tx_hdr_swid 98 * Switch partition ID. Must be set to 0. 99 */ 100 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3); 101 102 /* tx_hdr_control_tclass 103 * Indicates if the packet should use the control TClass and not one 104 * of the data TClasses. 105 */ 106 MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1); 107 108 /* tx_hdr_etclass 109 * Egress TClass to be used on the egress device on the egress port. 110 */ 111 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4); 112 113 /* tx_hdr_port_mid 114 * Destination local port for unicast packets. 115 * Destination multicast ID for multicast packets. 116 * 117 * Control packets are directed to a specific egress port, while data 118 * packets are transmitted through the CPU port (0) into the switch partition, 119 * where forwarding rules are applied. 120 */ 121 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16); 122 123 /* tx_hdr_fid 124 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is 125 * set, otherwise calculated based on the packet's VID using VID to FID mapping. 126 * Valid for data packets only. 127 */ 128 MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16); 129 130 /* tx_hdr_type 131 * 0 - Data packets 132 * 6 - Control packets 133 */ 134 MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4); 135 136 struct mlxsw_sp_mlxfw_dev { 137 struct mlxfw_dev mlxfw_dev; 138 struct mlxsw_sp *mlxsw_sp; 139 }; 140 141 static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev, 142 u16 component_index, u32 *p_max_size, 143 u8 *p_align_bits, u16 *p_max_write_size) 144 { 145 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 146 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 147 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 148 char mcqi_pl[MLXSW_REG_MCQI_LEN]; 149 int err; 150 151 mlxsw_reg_mcqi_pack(mcqi_pl, component_index); 152 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl); 153 if (err) 154 return err; 155 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits, 156 p_max_write_size); 157 158 *p_align_bits = max_t(u8, *p_align_bits, 2); 159 *p_max_write_size = min_t(u16, *p_max_write_size, 160 MLXSW_REG_MCDA_MAX_DATA_LEN); 161 return 0; 162 } 163 164 static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle) 165 { 166 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 167 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 168 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 169 char mcc_pl[MLXSW_REG_MCC_LEN]; 170 u8 control_state; 171 int err; 172 173 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0); 174 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 175 if (err) 176 return err; 177 178 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state); 179 if (control_state != MLXFW_FSM_STATE_IDLE) 180 return -EBUSY; 181 182 mlxsw_reg_mcc_pack(mcc_pl, 183 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE, 184 0, *fwhandle, 0); 185 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 186 } 187 188 static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev, 189 u32 fwhandle, u16 component_index, 190 u32 component_size) 191 { 192 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 193 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 194 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 195 char mcc_pl[MLXSW_REG_MCC_LEN]; 196 197 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT, 198 component_index, fwhandle, component_size); 199 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 200 } 201 202 static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev, 203 u32 fwhandle, u8 *data, u16 size, 204 u32 offset) 205 { 206 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 207 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 208 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 209 char mcda_pl[MLXSW_REG_MCDA_LEN]; 210 211 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data); 212 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl); 213 } 214 215 static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev, 216 u32 fwhandle, u16 component_index) 217 { 218 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 219 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 220 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 221 char mcc_pl[MLXSW_REG_MCC_LEN]; 222 223 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT, 224 component_index, fwhandle, 0); 225 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 226 } 227 228 static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 229 { 230 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 231 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 232 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 233 char mcc_pl[MLXSW_REG_MCC_LEN]; 234 235 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0, 236 fwhandle, 0); 237 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 238 } 239 240 static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 241 enum mlxfw_fsm_state *fsm_state, 242 enum mlxfw_fsm_state_err *fsm_state_err) 243 { 244 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 245 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 246 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 247 char mcc_pl[MLXSW_REG_MCC_LEN]; 248 u8 control_state; 249 u8 error_code; 250 int err; 251 252 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0); 253 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 254 if (err) 255 return err; 256 257 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state); 258 *fsm_state = control_state; 259 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code, 260 MLXFW_FSM_STATE_ERR_MAX); 261 return 0; 262 } 263 264 static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 265 { 266 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 267 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 268 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 269 char mcc_pl[MLXSW_REG_MCC_LEN]; 270 271 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0, 272 fwhandle, 0); 273 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 274 } 275 276 static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 277 { 278 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev = 279 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev); 280 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp; 281 char mcc_pl[MLXSW_REG_MCC_LEN]; 282 283 mlxsw_reg_mcc_pack(mcc_pl, 284 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0, 285 fwhandle, 0); 286 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl); 287 } 288 289 static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = { 290 .component_query = mlxsw_sp_component_query, 291 .fsm_lock = mlxsw_sp_fsm_lock, 292 .fsm_component_update = mlxsw_sp_fsm_component_update, 293 .fsm_block_download = mlxsw_sp_fsm_block_download, 294 .fsm_component_verify = mlxsw_sp_fsm_component_verify, 295 .fsm_activate = mlxsw_sp_fsm_activate, 296 .fsm_query_state = mlxsw_sp_fsm_query_state, 297 .fsm_cancel = mlxsw_sp_fsm_cancel, 298 .fsm_release = mlxsw_sp_fsm_release 299 }; 300 301 static int mlxsw_sp_firmware_flash(struct mlxsw_sp *mlxsw_sp, 302 const struct firmware *firmware) 303 { 304 struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = { 305 .mlxfw_dev = { 306 .ops = &mlxsw_sp_mlxfw_dev_ops, 307 .psid = mlxsw_sp->bus_info->psid, 308 .psid_size = strlen(mlxsw_sp->bus_info->psid), 309 }, 310 .mlxsw_sp = mlxsw_sp 311 }; 312 int err; 313 314 mlxsw_core_fw_flash_start(mlxsw_sp->core); 315 err = mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev, firmware); 316 mlxsw_core_fw_flash_end(mlxsw_sp->core); 317 318 return err; 319 } 320 321 static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp) 322 { 323 const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev; 324 const struct mlxsw_fw_rev *req_rev = mlxsw_sp->req_rev; 325 const char *fw_filename = mlxsw_sp->fw_filename; 326 const struct firmware *firmware; 327 int err; 328 329 /* Don't check if driver does not require it */ 330 if (!req_rev || !fw_filename) 331 return 0; 332 333 /* Validate driver & FW are compatible */ 334 if (rev->major != req_rev->major) { 335 WARN(1, "Mismatch in major FW version [%d:%d] is never expected; Please contact support\n", 336 rev->major, req_rev->major); 337 return -EINVAL; 338 } 339 if (MLXSW_SP_FWREV_MINOR_TO_BRANCH(rev->minor) == 340 MLXSW_SP_FWREV_MINOR_TO_BRANCH(req_rev->minor) && 341 (rev->minor > req_rev->minor || 342 (rev->minor == req_rev->minor && 343 rev->subminor >= req_rev->subminor))) 344 return 0; 345 346 dev_info(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d is incompatible with the driver\n", 347 rev->major, rev->minor, rev->subminor); 348 dev_info(mlxsw_sp->bus_info->dev, "Flashing firmware using file %s\n", 349 fw_filename); 350 351 err = request_firmware_direct(&firmware, fw_filename, 352 mlxsw_sp->bus_info->dev); 353 if (err) { 354 dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n", 355 fw_filename); 356 return err; 357 } 358 359 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware); 360 release_firmware(firmware); 361 if (err) 362 dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n"); 363 364 /* On FW flash success, tell the caller FW reset is needed 365 * if current FW supports it. 366 */ 367 if (rev->minor >= req_rev->can_reset_minor) 368 return err ? err : -EAGAIN; 369 else 370 return 0; 371 } 372 373 int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp, 374 unsigned int counter_index, u64 *packets, 375 u64 *bytes) 376 { 377 char mgpc_pl[MLXSW_REG_MGPC_LEN]; 378 int err; 379 380 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP, 381 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 382 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl); 383 if (err) 384 return err; 385 if (packets) 386 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl); 387 if (bytes) 388 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl); 389 return 0; 390 } 391 392 static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp, 393 unsigned int counter_index) 394 { 395 char mgpc_pl[MLXSW_REG_MGPC_LEN]; 396 397 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR, 398 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 399 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl); 400 } 401 402 int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp, 403 unsigned int *p_counter_index) 404 { 405 int err; 406 407 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW, 408 p_counter_index); 409 if (err) 410 return err; 411 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index); 412 if (err) 413 goto err_counter_clear; 414 return 0; 415 416 err_counter_clear: 417 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW, 418 *p_counter_index); 419 return err; 420 } 421 422 void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp, 423 unsigned int counter_index) 424 { 425 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW, 426 counter_index); 427 } 428 429 static void mlxsw_sp_txhdr_construct(struct sk_buff *skb, 430 const struct mlxsw_tx_info *tx_info) 431 { 432 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN); 433 434 memset(txhdr, 0, MLXSW_TXHDR_LEN); 435 436 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1); 437 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL); 438 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH); 439 mlxsw_tx_hdr_swid_set(txhdr, 0); 440 mlxsw_tx_hdr_control_tclass_set(txhdr, 1); 441 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port); 442 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL); 443 } 444 445 enum mlxsw_reg_spms_state mlxsw_sp_stp_spms_state(u8 state) 446 { 447 switch (state) { 448 case BR_STATE_FORWARDING: 449 return MLXSW_REG_SPMS_STATE_FORWARDING; 450 case BR_STATE_LEARNING: 451 return MLXSW_REG_SPMS_STATE_LEARNING; 452 case BR_STATE_LISTENING: /* fall-through */ 453 case BR_STATE_DISABLED: /* fall-through */ 454 case BR_STATE_BLOCKING: 455 return MLXSW_REG_SPMS_STATE_DISCARDING; 456 default: 457 BUG(); 458 } 459 } 460 461 int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid, 462 u8 state) 463 { 464 enum mlxsw_reg_spms_state spms_state = mlxsw_sp_stp_spms_state(state); 465 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 466 char *spms_pl; 467 int err; 468 469 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL); 470 if (!spms_pl) 471 return -ENOMEM; 472 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port); 473 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state); 474 475 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl); 476 kfree(spms_pl); 477 return err; 478 } 479 480 static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp) 481 { 482 char spad_pl[MLXSW_REG_SPAD_LEN] = {0}; 483 int err; 484 485 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl); 486 if (err) 487 return err; 488 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac); 489 return 0; 490 } 491 492 static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port, 493 bool enable, u32 rate) 494 { 495 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 496 char mpsc_pl[MLXSW_REG_MPSC_LEN]; 497 498 mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate); 499 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl); 500 } 501 502 static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port, 503 bool is_up) 504 { 505 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 506 char paos_pl[MLXSW_REG_PAOS_LEN]; 507 508 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port, 509 is_up ? MLXSW_PORT_ADMIN_STATUS_UP : 510 MLXSW_PORT_ADMIN_STATUS_DOWN); 511 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl); 512 } 513 514 static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port, 515 unsigned char *addr) 516 { 517 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 518 char ppad_pl[MLXSW_REG_PPAD_LEN]; 519 520 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port); 521 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr); 522 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl); 523 } 524 525 static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port) 526 { 527 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 528 unsigned char *addr = mlxsw_sp_port->dev->dev_addr; 529 530 ether_addr_copy(addr, mlxsw_sp->base_mac); 531 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port; 532 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr); 533 } 534 535 static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu) 536 { 537 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 538 char pmtu_pl[MLXSW_REG_PMTU_LEN]; 539 int max_mtu; 540 int err; 541 542 mtu += MLXSW_TXHDR_LEN + ETH_HLEN; 543 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0); 544 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl); 545 if (err) 546 return err; 547 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl); 548 549 if (mtu > max_mtu) 550 return -EINVAL; 551 552 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu); 553 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl); 554 } 555 556 static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid) 557 { 558 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 559 char pspa_pl[MLXSW_REG_PSPA_LEN]; 560 561 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port); 562 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl); 563 } 564 565 int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable) 566 { 567 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 568 char svpe_pl[MLXSW_REG_SVPE_LEN]; 569 570 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable); 571 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl); 572 } 573 574 int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid, 575 bool learn_enable) 576 { 577 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 578 char *spvmlr_pl; 579 int err; 580 581 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL); 582 if (!spvmlr_pl) 583 return -ENOMEM; 584 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid, 585 learn_enable); 586 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl); 587 kfree(spvmlr_pl); 588 return err; 589 } 590 591 static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, 592 u16 vid) 593 { 594 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 595 char spvid_pl[MLXSW_REG_SPVID_LEN]; 596 597 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid); 598 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl); 599 } 600 601 static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port, 602 bool allow) 603 { 604 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 605 char spaft_pl[MLXSW_REG_SPAFT_LEN]; 606 607 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow); 608 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl); 609 } 610 611 int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid) 612 { 613 int err; 614 615 if (!vid) { 616 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false); 617 if (err) 618 return err; 619 } else { 620 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid); 621 if (err) 622 return err; 623 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true); 624 if (err) 625 goto err_port_allow_untagged_set; 626 } 627 628 mlxsw_sp_port->pvid = vid; 629 return 0; 630 631 err_port_allow_untagged_set: 632 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid); 633 return err; 634 } 635 636 static int 637 mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port) 638 { 639 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 640 char sspr_pl[MLXSW_REG_SSPR_LEN]; 641 642 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port); 643 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl); 644 } 645 646 static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp, 647 u8 local_port, u8 *p_module, 648 u8 *p_width, u8 *p_lane) 649 { 650 char pmlp_pl[MLXSW_REG_PMLP_LEN]; 651 int err; 652 653 mlxsw_reg_pmlp_pack(pmlp_pl, local_port); 654 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl); 655 if (err) 656 return err; 657 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0); 658 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl); 659 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0); 660 return 0; 661 } 662 663 static int mlxsw_sp_port_module_map(struct mlxsw_sp_port *mlxsw_sp_port, 664 u8 module, u8 width, u8 lane) 665 { 666 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 667 char pmlp_pl[MLXSW_REG_PMLP_LEN]; 668 int i; 669 670 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port); 671 mlxsw_reg_pmlp_width_set(pmlp_pl, width); 672 for (i = 0; i < width; i++) { 673 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module); 674 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */ 675 } 676 677 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl); 678 } 679 680 static int mlxsw_sp_port_module_unmap(struct mlxsw_sp_port *mlxsw_sp_port) 681 { 682 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 683 char pmlp_pl[MLXSW_REG_PMLP_LEN]; 684 685 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port); 686 mlxsw_reg_pmlp_width_set(pmlp_pl, 0); 687 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl); 688 } 689 690 static int mlxsw_sp_port_open(struct net_device *dev) 691 { 692 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 693 int err; 694 695 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true); 696 if (err) 697 return err; 698 netif_start_queue(dev); 699 return 0; 700 } 701 702 static int mlxsw_sp_port_stop(struct net_device *dev) 703 { 704 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 705 706 netif_stop_queue(dev); 707 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false); 708 } 709 710 static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb, 711 struct net_device *dev) 712 { 713 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 714 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 715 struct mlxsw_sp_port_pcpu_stats *pcpu_stats; 716 const struct mlxsw_tx_info tx_info = { 717 .local_port = mlxsw_sp_port->local_port, 718 .is_emad = false, 719 }; 720 u64 len; 721 int err; 722 723 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info)) 724 return NETDEV_TX_BUSY; 725 726 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) { 727 struct sk_buff *skb_orig = skb; 728 729 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN); 730 if (!skb) { 731 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped); 732 dev_kfree_skb_any(skb_orig); 733 return NETDEV_TX_OK; 734 } 735 dev_consume_skb_any(skb_orig); 736 } 737 738 if (eth_skb_pad(skb)) { 739 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped); 740 return NETDEV_TX_OK; 741 } 742 743 mlxsw_sp_txhdr_construct(skb, &tx_info); 744 /* TX header is consumed by HW on the way so we shouldn't count its 745 * bytes as being sent. 746 */ 747 len = skb->len - MLXSW_TXHDR_LEN; 748 749 /* Due to a race we might fail here because of a full queue. In that 750 * unlikely case we simply drop the packet. 751 */ 752 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info); 753 754 if (!err) { 755 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats); 756 u64_stats_update_begin(&pcpu_stats->syncp); 757 pcpu_stats->tx_packets++; 758 pcpu_stats->tx_bytes += len; 759 u64_stats_update_end(&pcpu_stats->syncp); 760 } else { 761 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped); 762 dev_kfree_skb_any(skb); 763 } 764 return NETDEV_TX_OK; 765 } 766 767 static void mlxsw_sp_set_rx_mode(struct net_device *dev) 768 { 769 } 770 771 static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p) 772 { 773 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 774 struct sockaddr *addr = p; 775 int err; 776 777 if (!is_valid_ether_addr(addr->sa_data)) 778 return -EADDRNOTAVAIL; 779 780 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data); 781 if (err) 782 return err; 783 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 784 return 0; 785 } 786 787 static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp, 788 int mtu) 789 { 790 return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu); 791 } 792 793 #define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */ 794 795 static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu, 796 u16 delay) 797 { 798 delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay, 799 BITS_PER_BYTE)); 800 return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp, 801 mtu); 802 } 803 804 /* Maximum delay buffer needed in case of PAUSE frames, in bytes. 805 * Assumes 100m cable and maximum MTU. 806 */ 807 #define MLXSW_SP_PAUSE_DELAY 58752 808 809 static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu, 810 u16 delay, bool pfc, bool pause) 811 { 812 if (pfc) 813 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay); 814 else if (pause) 815 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY); 816 else 817 return 0; 818 } 819 820 static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres, 821 bool lossy) 822 { 823 if (lossy) 824 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size); 825 else 826 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size, 827 thres); 828 } 829 830 int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu, 831 u8 *prio_tc, bool pause_en, 832 struct ieee_pfc *my_pfc) 833 { 834 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 835 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0; 836 u16 delay = !!my_pfc ? my_pfc->delay : 0; 837 char pbmc_pl[MLXSW_REG_PBMC_LEN]; 838 int i, j, err; 839 840 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0); 841 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl); 842 if (err) 843 return err; 844 845 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 846 bool configure = false; 847 bool pfc = false; 848 bool lossy; 849 u16 thres; 850 851 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) { 852 if (prio_tc[j] == i) { 853 pfc = pfc_en & BIT(j); 854 configure = true; 855 break; 856 } 857 } 858 859 if (!configure) 860 continue; 861 862 lossy = !(pfc || pause_en); 863 thres = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu); 864 delay = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay, pfc, 865 pause_en); 866 mlxsw_sp_pg_buf_pack(pbmc_pl, i, thres + delay, thres, lossy); 867 } 868 869 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl); 870 } 871 872 static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, 873 int mtu, bool pause_en) 874 { 875 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0}; 876 bool dcb_en = !!mlxsw_sp_port->dcb.ets; 877 struct ieee_pfc *my_pfc; 878 u8 *prio_tc; 879 880 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc; 881 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL; 882 883 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc, 884 pause_en, my_pfc); 885 } 886 887 static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu) 888 { 889 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 890 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port); 891 int err; 892 893 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en); 894 if (err) 895 return err; 896 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu); 897 if (err) 898 goto err_span_port_mtu_update; 899 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu); 900 if (err) 901 goto err_port_mtu_set; 902 dev->mtu = mtu; 903 return 0; 904 905 err_port_mtu_set: 906 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu); 907 err_span_port_mtu_update: 908 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en); 909 return err; 910 } 911 912 static int 913 mlxsw_sp_port_get_sw_stats64(const struct net_device *dev, 914 struct rtnl_link_stats64 *stats) 915 { 916 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 917 struct mlxsw_sp_port_pcpu_stats *p; 918 u64 rx_packets, rx_bytes, tx_packets, tx_bytes; 919 u32 tx_dropped = 0; 920 unsigned int start; 921 int i; 922 923 for_each_possible_cpu(i) { 924 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i); 925 do { 926 start = u64_stats_fetch_begin_irq(&p->syncp); 927 rx_packets = p->rx_packets; 928 rx_bytes = p->rx_bytes; 929 tx_packets = p->tx_packets; 930 tx_bytes = p->tx_bytes; 931 } while (u64_stats_fetch_retry_irq(&p->syncp, start)); 932 933 stats->rx_packets += rx_packets; 934 stats->rx_bytes += rx_bytes; 935 stats->tx_packets += tx_packets; 936 stats->tx_bytes += tx_bytes; 937 /* tx_dropped is u32, updated without syncp protection. */ 938 tx_dropped += p->tx_dropped; 939 } 940 stats->tx_dropped = tx_dropped; 941 return 0; 942 } 943 944 static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id) 945 { 946 switch (attr_id) { 947 case IFLA_OFFLOAD_XSTATS_CPU_HIT: 948 return true; 949 } 950 951 return false; 952 } 953 954 static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev, 955 void *sp) 956 { 957 switch (attr_id) { 958 case IFLA_OFFLOAD_XSTATS_CPU_HIT: 959 return mlxsw_sp_port_get_sw_stats64(dev, sp); 960 } 961 962 return -EINVAL; 963 } 964 965 static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp, 966 int prio, char *ppcnt_pl) 967 { 968 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 969 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 970 971 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio); 972 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl); 973 } 974 975 static int mlxsw_sp_port_get_hw_stats(struct net_device *dev, 976 struct rtnl_link_stats64 *stats) 977 { 978 char ppcnt_pl[MLXSW_REG_PPCNT_LEN]; 979 int err; 980 981 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 982 0, ppcnt_pl); 983 if (err) 984 goto out; 985 986 stats->tx_packets = 987 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl); 988 stats->rx_packets = 989 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl); 990 stats->tx_bytes = 991 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl); 992 stats->rx_bytes = 993 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl); 994 stats->multicast = 995 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl); 996 997 stats->rx_crc_errors = 998 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl); 999 stats->rx_frame_errors = 1000 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl); 1001 1002 stats->rx_length_errors = ( 1003 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) + 1004 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) + 1005 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl)); 1006 1007 stats->rx_errors = (stats->rx_crc_errors + 1008 stats->rx_frame_errors + stats->rx_length_errors); 1009 1010 out: 1011 return err; 1012 } 1013 1014 static void 1015 mlxsw_sp_port_get_hw_xstats(struct net_device *dev, 1016 struct mlxsw_sp_port_xstats *xstats) 1017 { 1018 char ppcnt_pl[MLXSW_REG_PPCNT_LEN]; 1019 int err, i; 1020 1021 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0, 1022 ppcnt_pl); 1023 if (!err) 1024 xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl); 1025 1026 for (i = 0; i < TC_MAX_QUEUE; i++) { 1027 err = mlxsw_sp_port_get_stats_raw(dev, 1028 MLXSW_REG_PPCNT_TC_CONG_TC, 1029 i, ppcnt_pl); 1030 if (!err) 1031 xstats->wred_drop[i] = 1032 mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl); 1033 1034 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT, 1035 i, ppcnt_pl); 1036 if (err) 1037 continue; 1038 1039 xstats->backlog[i] = 1040 mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl); 1041 xstats->tail_drop[i] = 1042 mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl); 1043 } 1044 1045 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 1046 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_PRIO_CNT, 1047 i, ppcnt_pl); 1048 if (err) 1049 continue; 1050 1051 xstats->tx_packets[i] = mlxsw_reg_ppcnt_tx_frames_get(ppcnt_pl); 1052 xstats->tx_bytes[i] = mlxsw_reg_ppcnt_tx_octets_get(ppcnt_pl); 1053 } 1054 } 1055 1056 static void update_stats_cache(struct work_struct *work) 1057 { 1058 struct mlxsw_sp_port *mlxsw_sp_port = 1059 container_of(work, struct mlxsw_sp_port, 1060 periodic_hw_stats.update_dw.work); 1061 1062 if (!netif_carrier_ok(mlxsw_sp_port->dev)) 1063 goto out; 1064 1065 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev, 1066 &mlxsw_sp_port->periodic_hw_stats.stats); 1067 mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev, 1068 &mlxsw_sp_port->periodic_hw_stats.xstats); 1069 1070 out: 1071 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 1072 MLXSW_HW_STATS_UPDATE_TIME); 1073 } 1074 1075 /* Return the stats from a cache that is updated periodically, 1076 * as this function might get called in an atomic context. 1077 */ 1078 static void 1079 mlxsw_sp_port_get_stats64(struct net_device *dev, 1080 struct rtnl_link_stats64 *stats) 1081 { 1082 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1083 1084 memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats)); 1085 } 1086 1087 static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, 1088 u16 vid_begin, u16 vid_end, 1089 bool is_member, bool untagged) 1090 { 1091 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1092 char *spvm_pl; 1093 int err; 1094 1095 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL); 1096 if (!spvm_pl) 1097 return -ENOMEM; 1098 1099 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin, 1100 vid_end, is_member, untagged); 1101 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl); 1102 kfree(spvm_pl); 1103 return err; 1104 } 1105 1106 int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin, 1107 u16 vid_end, bool is_member, bool untagged) 1108 { 1109 u16 vid, vid_e; 1110 int err; 1111 1112 for (vid = vid_begin; vid <= vid_end; 1113 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) { 1114 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1), 1115 vid_end); 1116 1117 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e, 1118 is_member, untagged); 1119 if (err) 1120 return err; 1121 } 1122 1123 return 0; 1124 } 1125 1126 static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port) 1127 { 1128 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp; 1129 1130 list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp, 1131 &mlxsw_sp_port->vlans_list, list) 1132 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan); 1133 } 1134 1135 static struct mlxsw_sp_port_vlan * 1136 mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid) 1137 { 1138 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 1139 bool untagged = vid == 1; 1140 int err; 1141 1142 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged); 1143 if (err) 1144 return ERR_PTR(err); 1145 1146 mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL); 1147 if (!mlxsw_sp_port_vlan) { 1148 err = -ENOMEM; 1149 goto err_port_vlan_alloc; 1150 } 1151 1152 mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port; 1153 mlxsw_sp_port_vlan->ref_count = 1; 1154 mlxsw_sp_port_vlan->vid = vid; 1155 list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list); 1156 1157 return mlxsw_sp_port_vlan; 1158 1159 err_port_vlan_alloc: 1160 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false); 1161 return ERR_PTR(err); 1162 } 1163 1164 static void 1165 mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan) 1166 { 1167 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port; 1168 u16 vid = mlxsw_sp_port_vlan->vid; 1169 1170 list_del(&mlxsw_sp_port_vlan->list); 1171 kfree(mlxsw_sp_port_vlan); 1172 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false); 1173 } 1174 1175 struct mlxsw_sp_port_vlan * 1176 mlxsw_sp_port_vlan_get(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid) 1177 { 1178 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 1179 1180 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid); 1181 if (mlxsw_sp_port_vlan) { 1182 mlxsw_sp_port_vlan->ref_count++; 1183 return mlxsw_sp_port_vlan; 1184 } 1185 1186 return mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid); 1187 } 1188 1189 void mlxsw_sp_port_vlan_put(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan) 1190 { 1191 struct mlxsw_sp_fid *fid = mlxsw_sp_port_vlan->fid; 1192 1193 if (--mlxsw_sp_port_vlan->ref_count != 0) 1194 return; 1195 1196 if (mlxsw_sp_port_vlan->bridge_port) 1197 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan); 1198 else if (fid) 1199 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan); 1200 1201 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan); 1202 } 1203 1204 static int mlxsw_sp_port_add_vid(struct net_device *dev, 1205 __be16 __always_unused proto, u16 vid) 1206 { 1207 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1208 1209 /* VLAN 0 is added to HW filter when device goes up, but it is 1210 * reserved in our case, so simply return. 1211 */ 1212 if (!vid) 1213 return 0; 1214 1215 return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_get(mlxsw_sp_port, vid)); 1216 } 1217 1218 static int mlxsw_sp_port_kill_vid(struct net_device *dev, 1219 __be16 __always_unused proto, u16 vid) 1220 { 1221 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1222 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 1223 1224 /* VLAN 0 is removed from HW filter when device goes down, but 1225 * it is reserved in our case, so simply return. 1226 */ 1227 if (!vid) 1228 return 0; 1229 1230 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid); 1231 if (!mlxsw_sp_port_vlan) 1232 return 0; 1233 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan); 1234 1235 return 0; 1236 } 1237 1238 static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name, 1239 size_t len) 1240 { 1241 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1242 1243 return mlxsw_core_port_get_phys_port_name(mlxsw_sp_port->mlxsw_sp->core, 1244 mlxsw_sp_port->local_port, 1245 name, len); 1246 } 1247 1248 static struct mlxsw_sp_port_mall_tc_entry * 1249 mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port, 1250 unsigned long cookie) { 1251 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry; 1252 1253 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list) 1254 if (mall_tc_entry->cookie == cookie) 1255 return mall_tc_entry; 1256 1257 return NULL; 1258 } 1259 1260 static int 1261 mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port, 1262 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror, 1263 const struct tc_action *a, 1264 bool ingress) 1265 { 1266 enum mlxsw_sp_span_type span_type; 1267 struct net_device *to_dev; 1268 1269 to_dev = tcf_mirred_dev(a); 1270 if (!to_dev) { 1271 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n"); 1272 return -EINVAL; 1273 } 1274 1275 mirror->ingress = ingress; 1276 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS; 1277 return mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_dev, span_type, 1278 true, &mirror->span_id); 1279 } 1280 1281 static void 1282 mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port, 1283 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror) 1284 { 1285 enum mlxsw_sp_span_type span_type; 1286 1287 span_type = mirror->ingress ? 1288 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS; 1289 mlxsw_sp_span_mirror_del(mlxsw_sp_port, mirror->span_id, 1290 span_type, true); 1291 } 1292 1293 static int 1294 mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port, 1295 struct tc_cls_matchall_offload *cls, 1296 const struct tc_action *a, 1297 bool ingress) 1298 { 1299 int err; 1300 1301 if (!mlxsw_sp_port->sample) 1302 return -EOPNOTSUPP; 1303 if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) { 1304 netdev_err(mlxsw_sp_port->dev, "sample already active\n"); 1305 return -EEXIST; 1306 } 1307 if (tcf_sample_rate(a) > MLXSW_REG_MPSC_RATE_MAX) { 1308 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n"); 1309 return -EOPNOTSUPP; 1310 } 1311 1312 rcu_assign_pointer(mlxsw_sp_port->sample->psample_group, 1313 tcf_sample_psample_group(a)); 1314 mlxsw_sp_port->sample->truncate = tcf_sample_truncate(a); 1315 mlxsw_sp_port->sample->trunc_size = tcf_sample_trunc_size(a); 1316 mlxsw_sp_port->sample->rate = tcf_sample_rate(a); 1317 1318 err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, tcf_sample_rate(a)); 1319 if (err) 1320 goto err_port_sample_set; 1321 return 0; 1322 1323 err_port_sample_set: 1324 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL); 1325 return err; 1326 } 1327 1328 static void 1329 mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port) 1330 { 1331 if (!mlxsw_sp_port->sample) 1332 return; 1333 1334 mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1); 1335 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL); 1336 } 1337 1338 static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port, 1339 struct tc_cls_matchall_offload *f, 1340 bool ingress) 1341 { 1342 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry; 1343 __be16 protocol = f->common.protocol; 1344 const struct tc_action *a; 1345 LIST_HEAD(actions); 1346 int err; 1347 1348 if (!tcf_exts_has_one_action(f->exts)) { 1349 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n"); 1350 return -EOPNOTSUPP; 1351 } 1352 1353 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL); 1354 if (!mall_tc_entry) 1355 return -ENOMEM; 1356 mall_tc_entry->cookie = f->cookie; 1357 1358 a = tcf_exts_first_action(f->exts); 1359 1360 if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) { 1361 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror; 1362 1363 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR; 1364 mirror = &mall_tc_entry->mirror; 1365 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port, 1366 mirror, a, ingress); 1367 } else if (is_tcf_sample(a) && protocol == htons(ETH_P_ALL)) { 1368 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE; 1369 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, f, 1370 a, ingress); 1371 } else { 1372 err = -EOPNOTSUPP; 1373 } 1374 1375 if (err) 1376 goto err_add_action; 1377 1378 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list); 1379 return 0; 1380 1381 err_add_action: 1382 kfree(mall_tc_entry); 1383 return err; 1384 } 1385 1386 static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port, 1387 struct tc_cls_matchall_offload *f) 1388 { 1389 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry; 1390 1391 mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port, 1392 f->cookie); 1393 if (!mall_tc_entry) { 1394 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n"); 1395 return; 1396 } 1397 list_del(&mall_tc_entry->list); 1398 1399 switch (mall_tc_entry->type) { 1400 case MLXSW_SP_PORT_MALL_MIRROR: 1401 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port, 1402 &mall_tc_entry->mirror); 1403 break; 1404 case MLXSW_SP_PORT_MALL_SAMPLE: 1405 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port); 1406 break; 1407 default: 1408 WARN_ON(1); 1409 } 1410 1411 kfree(mall_tc_entry); 1412 } 1413 1414 static int mlxsw_sp_setup_tc_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port, 1415 struct tc_cls_matchall_offload *f, 1416 bool ingress) 1417 { 1418 switch (f->command) { 1419 case TC_CLSMATCHALL_REPLACE: 1420 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port, f, 1421 ingress); 1422 case TC_CLSMATCHALL_DESTROY: 1423 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port, f); 1424 return 0; 1425 default: 1426 return -EOPNOTSUPP; 1427 } 1428 } 1429 1430 static int 1431 mlxsw_sp_setup_tc_cls_flower(struct mlxsw_sp_acl_block *acl_block, 1432 struct tc_cls_flower_offload *f) 1433 { 1434 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_acl_block_mlxsw_sp(acl_block); 1435 1436 switch (f->command) { 1437 case TC_CLSFLOWER_REPLACE: 1438 return mlxsw_sp_flower_replace(mlxsw_sp, acl_block, f); 1439 case TC_CLSFLOWER_DESTROY: 1440 mlxsw_sp_flower_destroy(mlxsw_sp, acl_block, f); 1441 return 0; 1442 case TC_CLSFLOWER_STATS: 1443 return mlxsw_sp_flower_stats(mlxsw_sp, acl_block, f); 1444 case TC_CLSFLOWER_TMPLT_CREATE: 1445 return mlxsw_sp_flower_tmplt_create(mlxsw_sp, acl_block, f); 1446 case TC_CLSFLOWER_TMPLT_DESTROY: 1447 mlxsw_sp_flower_tmplt_destroy(mlxsw_sp, acl_block, f); 1448 return 0; 1449 default: 1450 return -EOPNOTSUPP; 1451 } 1452 } 1453 1454 static int mlxsw_sp_setup_tc_block_cb_matchall(enum tc_setup_type type, 1455 void *type_data, 1456 void *cb_priv, bool ingress) 1457 { 1458 struct mlxsw_sp_port *mlxsw_sp_port = cb_priv; 1459 1460 switch (type) { 1461 case TC_SETUP_CLSMATCHALL: 1462 if (!tc_cls_can_offload_and_chain0(mlxsw_sp_port->dev, 1463 type_data)) 1464 return -EOPNOTSUPP; 1465 1466 return mlxsw_sp_setup_tc_cls_matchall(mlxsw_sp_port, type_data, 1467 ingress); 1468 case TC_SETUP_CLSFLOWER: 1469 return 0; 1470 default: 1471 return -EOPNOTSUPP; 1472 } 1473 } 1474 1475 static int mlxsw_sp_setup_tc_block_cb_matchall_ig(enum tc_setup_type type, 1476 void *type_data, 1477 void *cb_priv) 1478 { 1479 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data, 1480 cb_priv, true); 1481 } 1482 1483 static int mlxsw_sp_setup_tc_block_cb_matchall_eg(enum tc_setup_type type, 1484 void *type_data, 1485 void *cb_priv) 1486 { 1487 return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data, 1488 cb_priv, false); 1489 } 1490 1491 static int mlxsw_sp_setup_tc_block_cb_flower(enum tc_setup_type type, 1492 void *type_data, void *cb_priv) 1493 { 1494 struct mlxsw_sp_acl_block *acl_block = cb_priv; 1495 1496 switch (type) { 1497 case TC_SETUP_CLSMATCHALL: 1498 return 0; 1499 case TC_SETUP_CLSFLOWER: 1500 if (mlxsw_sp_acl_block_disabled(acl_block)) 1501 return -EOPNOTSUPP; 1502 1503 return mlxsw_sp_setup_tc_cls_flower(acl_block, type_data); 1504 default: 1505 return -EOPNOTSUPP; 1506 } 1507 } 1508 1509 static int 1510 mlxsw_sp_setup_tc_block_flower_bind(struct mlxsw_sp_port *mlxsw_sp_port, 1511 struct tcf_block *block, bool ingress, 1512 struct netlink_ext_ack *extack) 1513 { 1514 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1515 struct mlxsw_sp_acl_block *acl_block; 1516 struct tcf_block_cb *block_cb; 1517 int err; 1518 1519 block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower, 1520 mlxsw_sp); 1521 if (!block_cb) { 1522 acl_block = mlxsw_sp_acl_block_create(mlxsw_sp, block->net); 1523 if (!acl_block) 1524 return -ENOMEM; 1525 block_cb = __tcf_block_cb_register(block, 1526 mlxsw_sp_setup_tc_block_cb_flower, 1527 mlxsw_sp, acl_block, extack); 1528 if (IS_ERR(block_cb)) { 1529 err = PTR_ERR(block_cb); 1530 goto err_cb_register; 1531 } 1532 } else { 1533 acl_block = tcf_block_cb_priv(block_cb); 1534 } 1535 tcf_block_cb_incref(block_cb); 1536 err = mlxsw_sp_acl_block_bind(mlxsw_sp, acl_block, 1537 mlxsw_sp_port, ingress); 1538 if (err) 1539 goto err_block_bind; 1540 1541 if (ingress) 1542 mlxsw_sp_port->ing_acl_block = acl_block; 1543 else 1544 mlxsw_sp_port->eg_acl_block = acl_block; 1545 1546 return 0; 1547 1548 err_block_bind: 1549 if (!tcf_block_cb_decref(block_cb)) { 1550 __tcf_block_cb_unregister(block, block_cb); 1551 err_cb_register: 1552 mlxsw_sp_acl_block_destroy(acl_block); 1553 } 1554 return err; 1555 } 1556 1557 static void 1558 mlxsw_sp_setup_tc_block_flower_unbind(struct mlxsw_sp_port *mlxsw_sp_port, 1559 struct tcf_block *block, bool ingress) 1560 { 1561 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1562 struct mlxsw_sp_acl_block *acl_block; 1563 struct tcf_block_cb *block_cb; 1564 int err; 1565 1566 block_cb = tcf_block_cb_lookup(block, mlxsw_sp_setup_tc_block_cb_flower, 1567 mlxsw_sp); 1568 if (!block_cb) 1569 return; 1570 1571 if (ingress) 1572 mlxsw_sp_port->ing_acl_block = NULL; 1573 else 1574 mlxsw_sp_port->eg_acl_block = NULL; 1575 1576 acl_block = tcf_block_cb_priv(block_cb); 1577 err = mlxsw_sp_acl_block_unbind(mlxsw_sp, acl_block, 1578 mlxsw_sp_port, ingress); 1579 if (!err && !tcf_block_cb_decref(block_cb)) { 1580 __tcf_block_cb_unregister(block, block_cb); 1581 mlxsw_sp_acl_block_destroy(acl_block); 1582 } 1583 } 1584 1585 static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port, 1586 struct tc_block_offload *f) 1587 { 1588 tc_setup_cb_t *cb; 1589 bool ingress; 1590 int err; 1591 1592 if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) { 1593 cb = mlxsw_sp_setup_tc_block_cb_matchall_ig; 1594 ingress = true; 1595 } else if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_EGRESS) { 1596 cb = mlxsw_sp_setup_tc_block_cb_matchall_eg; 1597 ingress = false; 1598 } else { 1599 return -EOPNOTSUPP; 1600 } 1601 1602 switch (f->command) { 1603 case TC_BLOCK_BIND: 1604 err = tcf_block_cb_register(f->block, cb, mlxsw_sp_port, 1605 mlxsw_sp_port, f->extack); 1606 if (err) 1607 return err; 1608 err = mlxsw_sp_setup_tc_block_flower_bind(mlxsw_sp_port, 1609 f->block, ingress, 1610 f->extack); 1611 if (err) { 1612 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port); 1613 return err; 1614 } 1615 return 0; 1616 case TC_BLOCK_UNBIND: 1617 mlxsw_sp_setup_tc_block_flower_unbind(mlxsw_sp_port, 1618 f->block, ingress); 1619 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port); 1620 return 0; 1621 default: 1622 return -EOPNOTSUPP; 1623 } 1624 } 1625 1626 static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type, 1627 void *type_data) 1628 { 1629 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1630 1631 switch (type) { 1632 case TC_SETUP_BLOCK: 1633 return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data); 1634 case TC_SETUP_QDISC_RED: 1635 return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data); 1636 case TC_SETUP_QDISC_PRIO: 1637 return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data); 1638 default: 1639 return -EOPNOTSUPP; 1640 } 1641 } 1642 1643 1644 static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable) 1645 { 1646 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1647 1648 if (!enable) { 1649 if (mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->ing_acl_block) || 1650 mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->eg_acl_block) || 1651 !list_empty(&mlxsw_sp_port->mall_tc_list)) { 1652 netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n"); 1653 return -EINVAL; 1654 } 1655 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->ing_acl_block); 1656 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->eg_acl_block); 1657 } else { 1658 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->ing_acl_block); 1659 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->eg_acl_block); 1660 } 1661 return 0; 1662 } 1663 1664 typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable); 1665 1666 static int mlxsw_sp_handle_feature(struct net_device *dev, 1667 netdev_features_t wanted_features, 1668 netdev_features_t feature, 1669 mlxsw_sp_feature_handler feature_handler) 1670 { 1671 netdev_features_t changes = wanted_features ^ dev->features; 1672 bool enable = !!(wanted_features & feature); 1673 int err; 1674 1675 if (!(changes & feature)) 1676 return 0; 1677 1678 err = feature_handler(dev, enable); 1679 if (err) { 1680 netdev_err(dev, "%s feature %pNF failed, err %d\n", 1681 enable ? "Enable" : "Disable", &feature, err); 1682 return err; 1683 } 1684 1685 if (enable) 1686 dev->features |= feature; 1687 else 1688 dev->features &= ~feature; 1689 1690 return 0; 1691 } 1692 static int mlxsw_sp_set_features(struct net_device *dev, 1693 netdev_features_t features) 1694 { 1695 return mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC, 1696 mlxsw_sp_feature_hw_tc); 1697 } 1698 1699 static const struct net_device_ops mlxsw_sp_port_netdev_ops = { 1700 .ndo_open = mlxsw_sp_port_open, 1701 .ndo_stop = mlxsw_sp_port_stop, 1702 .ndo_start_xmit = mlxsw_sp_port_xmit, 1703 .ndo_setup_tc = mlxsw_sp_setup_tc, 1704 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode, 1705 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address, 1706 .ndo_change_mtu = mlxsw_sp_port_change_mtu, 1707 .ndo_get_stats64 = mlxsw_sp_port_get_stats64, 1708 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats, 1709 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats, 1710 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid, 1711 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid, 1712 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name, 1713 .ndo_set_features = mlxsw_sp_set_features, 1714 }; 1715 1716 static void mlxsw_sp_port_get_drvinfo(struct net_device *dev, 1717 struct ethtool_drvinfo *drvinfo) 1718 { 1719 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1720 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 1721 1722 strlcpy(drvinfo->driver, mlxsw_sp->bus_info->device_kind, 1723 sizeof(drvinfo->driver)); 1724 strlcpy(drvinfo->version, mlxsw_sp_driver_version, 1725 sizeof(drvinfo->version)); 1726 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), 1727 "%d.%d.%d", 1728 mlxsw_sp->bus_info->fw_rev.major, 1729 mlxsw_sp->bus_info->fw_rev.minor, 1730 mlxsw_sp->bus_info->fw_rev.subminor); 1731 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name, 1732 sizeof(drvinfo->bus_info)); 1733 } 1734 1735 static void mlxsw_sp_port_get_pauseparam(struct net_device *dev, 1736 struct ethtool_pauseparam *pause) 1737 { 1738 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1739 1740 pause->rx_pause = mlxsw_sp_port->link.rx_pause; 1741 pause->tx_pause = mlxsw_sp_port->link.tx_pause; 1742 } 1743 1744 static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port, 1745 struct ethtool_pauseparam *pause) 1746 { 1747 char pfcc_pl[MLXSW_REG_PFCC_LEN]; 1748 1749 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port); 1750 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause); 1751 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause); 1752 1753 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc), 1754 pfcc_pl); 1755 } 1756 1757 static int mlxsw_sp_port_set_pauseparam(struct net_device *dev, 1758 struct ethtool_pauseparam *pause) 1759 { 1760 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 1761 bool pause_en = pause->tx_pause || pause->rx_pause; 1762 int err; 1763 1764 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) { 1765 netdev_err(dev, "PFC already enabled on port\n"); 1766 return -EINVAL; 1767 } 1768 1769 if (pause->autoneg) { 1770 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n"); 1771 return -EINVAL; 1772 } 1773 1774 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en); 1775 if (err) { 1776 netdev_err(dev, "Failed to configure port's headroom\n"); 1777 return err; 1778 } 1779 1780 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause); 1781 if (err) { 1782 netdev_err(dev, "Failed to set PAUSE parameters\n"); 1783 goto err_port_pause_configure; 1784 } 1785 1786 mlxsw_sp_port->link.rx_pause = pause->rx_pause; 1787 mlxsw_sp_port->link.tx_pause = pause->tx_pause; 1788 1789 return 0; 1790 1791 err_port_pause_configure: 1792 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port); 1793 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en); 1794 return err; 1795 } 1796 1797 struct mlxsw_sp_port_hw_stats { 1798 char str[ETH_GSTRING_LEN]; 1799 u64 (*getter)(const char *payload); 1800 bool cells_bytes; 1801 }; 1802 1803 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = { 1804 { 1805 .str = "a_frames_transmitted_ok", 1806 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get, 1807 }, 1808 { 1809 .str = "a_frames_received_ok", 1810 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get, 1811 }, 1812 { 1813 .str = "a_frame_check_sequence_errors", 1814 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get, 1815 }, 1816 { 1817 .str = "a_alignment_errors", 1818 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get, 1819 }, 1820 { 1821 .str = "a_octets_transmitted_ok", 1822 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get, 1823 }, 1824 { 1825 .str = "a_octets_received_ok", 1826 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get, 1827 }, 1828 { 1829 .str = "a_multicast_frames_xmitted_ok", 1830 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get, 1831 }, 1832 { 1833 .str = "a_broadcast_frames_xmitted_ok", 1834 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get, 1835 }, 1836 { 1837 .str = "a_multicast_frames_received_ok", 1838 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get, 1839 }, 1840 { 1841 .str = "a_broadcast_frames_received_ok", 1842 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get, 1843 }, 1844 { 1845 .str = "a_in_range_length_errors", 1846 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get, 1847 }, 1848 { 1849 .str = "a_out_of_range_length_field", 1850 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get, 1851 }, 1852 { 1853 .str = "a_frame_too_long_errors", 1854 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get, 1855 }, 1856 { 1857 .str = "a_symbol_error_during_carrier", 1858 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get, 1859 }, 1860 { 1861 .str = "a_mac_control_frames_transmitted", 1862 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get, 1863 }, 1864 { 1865 .str = "a_mac_control_frames_received", 1866 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get, 1867 }, 1868 { 1869 .str = "a_unsupported_opcodes_received", 1870 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get, 1871 }, 1872 { 1873 .str = "a_pause_mac_ctrl_frames_received", 1874 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get, 1875 }, 1876 { 1877 .str = "a_pause_mac_ctrl_frames_xmitted", 1878 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get, 1879 }, 1880 }; 1881 1882 #define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats) 1883 1884 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_rfc_2819_stats[] = { 1885 { 1886 .str = "ether_pkts64octets", 1887 .getter = mlxsw_reg_ppcnt_ether_stats_pkts64octets_get, 1888 }, 1889 { 1890 .str = "ether_pkts65to127octets", 1891 .getter = mlxsw_reg_ppcnt_ether_stats_pkts65to127octets_get, 1892 }, 1893 { 1894 .str = "ether_pkts128to255octets", 1895 .getter = mlxsw_reg_ppcnt_ether_stats_pkts128to255octets_get, 1896 }, 1897 { 1898 .str = "ether_pkts256to511octets", 1899 .getter = mlxsw_reg_ppcnt_ether_stats_pkts256to511octets_get, 1900 }, 1901 { 1902 .str = "ether_pkts512to1023octets", 1903 .getter = mlxsw_reg_ppcnt_ether_stats_pkts512to1023octets_get, 1904 }, 1905 { 1906 .str = "ether_pkts1024to1518octets", 1907 .getter = mlxsw_reg_ppcnt_ether_stats_pkts1024to1518octets_get, 1908 }, 1909 { 1910 .str = "ether_pkts1519to2047octets", 1911 .getter = mlxsw_reg_ppcnt_ether_stats_pkts1519to2047octets_get, 1912 }, 1913 { 1914 .str = "ether_pkts2048to4095octets", 1915 .getter = mlxsw_reg_ppcnt_ether_stats_pkts2048to4095octets_get, 1916 }, 1917 { 1918 .str = "ether_pkts4096to8191octets", 1919 .getter = mlxsw_reg_ppcnt_ether_stats_pkts4096to8191octets_get, 1920 }, 1921 { 1922 .str = "ether_pkts8192to10239octets", 1923 .getter = mlxsw_reg_ppcnt_ether_stats_pkts8192to10239octets_get, 1924 }, 1925 }; 1926 1927 #define MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN \ 1928 ARRAY_SIZE(mlxsw_sp_port_hw_rfc_2819_stats) 1929 1930 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = { 1931 { 1932 .str = "rx_octets_prio", 1933 .getter = mlxsw_reg_ppcnt_rx_octets_get, 1934 }, 1935 { 1936 .str = "rx_frames_prio", 1937 .getter = mlxsw_reg_ppcnt_rx_frames_get, 1938 }, 1939 { 1940 .str = "tx_octets_prio", 1941 .getter = mlxsw_reg_ppcnt_tx_octets_get, 1942 }, 1943 { 1944 .str = "tx_frames_prio", 1945 .getter = mlxsw_reg_ppcnt_tx_frames_get, 1946 }, 1947 { 1948 .str = "rx_pause_prio", 1949 .getter = mlxsw_reg_ppcnt_rx_pause_get, 1950 }, 1951 { 1952 .str = "rx_pause_duration_prio", 1953 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get, 1954 }, 1955 { 1956 .str = "tx_pause_prio", 1957 .getter = mlxsw_reg_ppcnt_tx_pause_get, 1958 }, 1959 { 1960 .str = "tx_pause_duration_prio", 1961 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get, 1962 }, 1963 }; 1964 1965 #define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats) 1966 1967 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = { 1968 { 1969 .str = "tc_transmit_queue_tc", 1970 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get, 1971 .cells_bytes = true, 1972 }, 1973 { 1974 .str = "tc_no_buffer_discard_uc_tc", 1975 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get, 1976 }, 1977 }; 1978 1979 #define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats) 1980 1981 #define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \ 1982 MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN + \ 1983 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN * \ 1984 IEEE_8021QAZ_MAX_TCS) + \ 1985 (MLXSW_SP_PORT_HW_TC_STATS_LEN * \ 1986 TC_MAX_QUEUE)) 1987 1988 static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio) 1989 { 1990 int i; 1991 1992 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) { 1993 snprintf(*p, ETH_GSTRING_LEN, "%s_%d", 1994 mlxsw_sp_port_hw_prio_stats[i].str, prio); 1995 *p += ETH_GSTRING_LEN; 1996 } 1997 } 1998 1999 static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc) 2000 { 2001 int i; 2002 2003 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) { 2004 snprintf(*p, ETH_GSTRING_LEN, "%s_%d", 2005 mlxsw_sp_port_hw_tc_stats[i].str, tc); 2006 *p += ETH_GSTRING_LEN; 2007 } 2008 } 2009 2010 static void mlxsw_sp_port_get_strings(struct net_device *dev, 2011 u32 stringset, u8 *data) 2012 { 2013 u8 *p = data; 2014 int i; 2015 2016 switch (stringset) { 2017 case ETH_SS_STATS: 2018 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) { 2019 memcpy(p, mlxsw_sp_port_hw_stats[i].str, 2020 ETH_GSTRING_LEN); 2021 p += ETH_GSTRING_LEN; 2022 } 2023 for (i = 0; i < MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN; i++) { 2024 memcpy(p, mlxsw_sp_port_hw_rfc_2819_stats[i].str, 2025 ETH_GSTRING_LEN); 2026 p += ETH_GSTRING_LEN; 2027 } 2028 2029 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) 2030 mlxsw_sp_port_get_prio_strings(&p, i); 2031 2032 for (i = 0; i < TC_MAX_QUEUE; i++) 2033 mlxsw_sp_port_get_tc_strings(&p, i); 2034 2035 break; 2036 } 2037 } 2038 2039 static int mlxsw_sp_port_set_phys_id(struct net_device *dev, 2040 enum ethtool_phys_id_state state) 2041 { 2042 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 2043 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2044 char mlcr_pl[MLXSW_REG_MLCR_LEN]; 2045 bool active; 2046 2047 switch (state) { 2048 case ETHTOOL_ID_ACTIVE: 2049 active = true; 2050 break; 2051 case ETHTOOL_ID_INACTIVE: 2052 active = false; 2053 break; 2054 default: 2055 return -EOPNOTSUPP; 2056 } 2057 2058 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active); 2059 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl); 2060 } 2061 2062 static int 2063 mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats, 2064 int *p_len, enum mlxsw_reg_ppcnt_grp grp) 2065 { 2066 switch (grp) { 2067 case MLXSW_REG_PPCNT_IEEE_8023_CNT: 2068 *p_hw_stats = mlxsw_sp_port_hw_stats; 2069 *p_len = MLXSW_SP_PORT_HW_STATS_LEN; 2070 break; 2071 case MLXSW_REG_PPCNT_RFC_2819_CNT: 2072 *p_hw_stats = mlxsw_sp_port_hw_rfc_2819_stats; 2073 *p_len = MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN; 2074 break; 2075 case MLXSW_REG_PPCNT_PRIO_CNT: 2076 *p_hw_stats = mlxsw_sp_port_hw_prio_stats; 2077 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN; 2078 break; 2079 case MLXSW_REG_PPCNT_TC_CNT: 2080 *p_hw_stats = mlxsw_sp_port_hw_tc_stats; 2081 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN; 2082 break; 2083 default: 2084 WARN_ON(1); 2085 return -EOPNOTSUPP; 2086 } 2087 return 0; 2088 } 2089 2090 static void __mlxsw_sp_port_get_stats(struct net_device *dev, 2091 enum mlxsw_reg_ppcnt_grp grp, int prio, 2092 u64 *data, int data_index) 2093 { 2094 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 2095 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2096 struct mlxsw_sp_port_hw_stats *hw_stats; 2097 char ppcnt_pl[MLXSW_REG_PPCNT_LEN]; 2098 int i, len; 2099 int err; 2100 2101 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp); 2102 if (err) 2103 return; 2104 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl); 2105 for (i = 0; i < len; i++) { 2106 data[data_index + i] = hw_stats[i].getter(ppcnt_pl); 2107 if (!hw_stats[i].cells_bytes) 2108 continue; 2109 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp, 2110 data[data_index + i]); 2111 } 2112 } 2113 2114 static void mlxsw_sp_port_get_stats(struct net_device *dev, 2115 struct ethtool_stats *stats, u64 *data) 2116 { 2117 int i, data_index = 0; 2118 2119 /* IEEE 802.3 Counters */ 2120 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0, 2121 data, data_index); 2122 data_index = MLXSW_SP_PORT_HW_STATS_LEN; 2123 2124 /* RFC 2819 Counters */ 2125 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_RFC_2819_CNT, 0, 2126 data, data_index); 2127 data_index += MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN; 2128 2129 /* Per-Priority Counters */ 2130 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 2131 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i, 2132 data, data_index); 2133 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN; 2134 } 2135 2136 /* Per-TC Counters */ 2137 for (i = 0; i < TC_MAX_QUEUE; i++) { 2138 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i, 2139 data, data_index); 2140 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN; 2141 } 2142 } 2143 2144 static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset) 2145 { 2146 switch (sset) { 2147 case ETH_SS_STATS: 2148 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN; 2149 default: 2150 return -EOPNOTSUPP; 2151 } 2152 } 2153 2154 struct mlxsw_sp_port_link_mode { 2155 enum ethtool_link_mode_bit_indices mask_ethtool; 2156 u32 mask; 2157 u32 speed; 2158 }; 2159 2160 static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = { 2161 { 2162 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T, 2163 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT, 2164 .speed = SPEED_100, 2165 }, 2166 { 2167 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII | 2168 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX, 2169 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 2170 .speed = SPEED_1000, 2171 }, 2172 { 2173 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T, 2174 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 2175 .speed = SPEED_10000, 2176 }, 2177 { 2178 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 | 2179 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4, 2180 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, 2181 .speed = SPEED_10000, 2182 }, 2183 { 2184 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR | 2185 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR | 2186 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR | 2187 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR, 2188 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 2189 .speed = SPEED_10000, 2190 }, 2191 { 2192 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2, 2193 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT, 2194 .speed = SPEED_20000, 2195 }, 2196 { 2197 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4, 2198 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 2199 .speed = SPEED_40000, 2200 }, 2201 { 2202 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4, 2203 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 2204 .speed = SPEED_40000, 2205 }, 2206 { 2207 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4, 2208 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 2209 .speed = SPEED_40000, 2210 }, 2211 { 2212 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4, 2213 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, 2214 .speed = SPEED_40000, 2215 }, 2216 { 2217 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR, 2218 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 2219 .speed = SPEED_25000, 2220 }, 2221 { 2222 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR, 2223 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 2224 .speed = SPEED_25000, 2225 }, 2226 { 2227 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR, 2228 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 2229 .speed = SPEED_25000, 2230 }, 2231 { 2232 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR, 2233 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 2234 .speed = SPEED_25000, 2235 }, 2236 { 2237 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2, 2238 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, 2239 .speed = SPEED_50000, 2240 }, 2241 { 2242 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2, 2243 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, 2244 .speed = SPEED_50000, 2245 }, 2246 { 2247 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2, 2248 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, 2249 .speed = SPEED_50000, 2250 }, 2251 { 2252 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4, 2253 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT, 2254 .speed = SPEED_56000, 2255 }, 2256 { 2257 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4, 2258 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT, 2259 .speed = SPEED_56000, 2260 }, 2261 { 2262 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4, 2263 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT, 2264 .speed = SPEED_56000, 2265 }, 2266 { 2267 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4, 2268 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT, 2269 .speed = SPEED_56000, 2270 }, 2271 { 2272 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4, 2273 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 2274 .speed = SPEED_100000, 2275 }, 2276 { 2277 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4, 2278 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 2279 .speed = SPEED_100000, 2280 }, 2281 { 2282 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4, 2283 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, 2284 .speed = SPEED_100000, 2285 }, 2286 { 2287 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4, 2288 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, 2289 .speed = SPEED_100000, 2290 }, 2291 }; 2292 2293 #define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode) 2294 2295 static void 2296 mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto, 2297 struct ethtool_link_ksettings *cmd) 2298 { 2299 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR | 2300 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR | 2301 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 | 2302 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 | 2303 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 | 2304 MLXSW_REG_PTYS_ETH_SPEED_SGMII)) 2305 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE); 2306 2307 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR | 2308 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 | 2309 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 | 2310 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 | 2311 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX)) 2312 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane); 2313 } 2314 2315 static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode) 2316 { 2317 int i; 2318 2319 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) { 2320 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) 2321 __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool, 2322 mode); 2323 } 2324 } 2325 2326 static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto, 2327 struct ethtool_link_ksettings *cmd) 2328 { 2329 u32 speed = SPEED_UNKNOWN; 2330 u8 duplex = DUPLEX_UNKNOWN; 2331 int i; 2332 2333 if (!carrier_ok) 2334 goto out; 2335 2336 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) { 2337 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) { 2338 speed = mlxsw_sp_port_link_mode[i].speed; 2339 duplex = DUPLEX_FULL; 2340 break; 2341 } 2342 } 2343 out: 2344 cmd->base.speed = speed; 2345 cmd->base.duplex = duplex; 2346 } 2347 2348 static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto) 2349 { 2350 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR | 2351 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 | 2352 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 | 2353 MLXSW_REG_PTYS_ETH_SPEED_SGMII)) 2354 return PORT_FIBRE; 2355 2356 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR | 2357 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 | 2358 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4)) 2359 return PORT_DA; 2360 2361 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR | 2362 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 | 2363 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 | 2364 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4)) 2365 return PORT_NONE; 2366 2367 return PORT_OTHER; 2368 } 2369 2370 static u32 2371 mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd) 2372 { 2373 u32 ptys_proto = 0; 2374 int i; 2375 2376 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) { 2377 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool, 2378 cmd->link_modes.advertising)) 2379 ptys_proto |= mlxsw_sp_port_link_mode[i].mask; 2380 } 2381 return ptys_proto; 2382 } 2383 2384 static u32 mlxsw_sp_to_ptys_speed(u32 speed) 2385 { 2386 u32 ptys_proto = 0; 2387 int i; 2388 2389 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) { 2390 if (speed == mlxsw_sp_port_link_mode[i].speed) 2391 ptys_proto |= mlxsw_sp_port_link_mode[i].mask; 2392 } 2393 return ptys_proto; 2394 } 2395 2396 static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed) 2397 { 2398 u32 ptys_proto = 0; 2399 int i; 2400 2401 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) { 2402 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed) 2403 ptys_proto |= mlxsw_sp_port_link_mode[i].mask; 2404 } 2405 return ptys_proto; 2406 } 2407 2408 static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap, 2409 struct ethtool_link_ksettings *cmd) 2410 { 2411 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause); 2412 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg); 2413 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause); 2414 2415 mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd); 2416 mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported); 2417 } 2418 2419 static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg, 2420 struct ethtool_link_ksettings *cmd) 2421 { 2422 if (!autoneg) 2423 return; 2424 2425 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg); 2426 mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising); 2427 } 2428 2429 static void 2430 mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status, 2431 struct ethtool_link_ksettings *cmd) 2432 { 2433 if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp) 2434 return; 2435 2436 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg); 2437 mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising); 2438 } 2439 2440 static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev, 2441 struct ethtool_link_ksettings *cmd) 2442 { 2443 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp; 2444 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 2445 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2446 char ptys_pl[MLXSW_REG_PTYS_LEN]; 2447 u8 autoneg_status; 2448 bool autoneg; 2449 int err; 2450 2451 autoneg = mlxsw_sp_port->link.autoneg; 2452 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0, false); 2453 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 2454 if (err) 2455 return err; 2456 mlxsw_reg_ptys_eth_unpack(ptys_pl, ð_proto_cap, ð_proto_admin, 2457 ð_proto_oper); 2458 2459 mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd); 2460 2461 mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd); 2462 2463 eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl); 2464 autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl); 2465 mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd); 2466 2467 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE; 2468 cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper); 2469 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper, 2470 cmd); 2471 2472 return 0; 2473 } 2474 2475 static int 2476 mlxsw_sp_port_set_link_ksettings(struct net_device *dev, 2477 const struct ethtool_link_ksettings *cmd) 2478 { 2479 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 2480 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2481 char ptys_pl[MLXSW_REG_PTYS_LEN]; 2482 u32 eth_proto_cap, eth_proto_new; 2483 bool autoneg; 2484 int err; 2485 2486 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0, false); 2487 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 2488 if (err) 2489 return err; 2490 mlxsw_reg_ptys_eth_unpack(ptys_pl, ð_proto_cap, NULL, NULL); 2491 2492 autoneg = cmd->base.autoneg == AUTONEG_ENABLE; 2493 eth_proto_new = autoneg ? 2494 mlxsw_sp_to_ptys_advert_link(cmd) : 2495 mlxsw_sp_to_ptys_speed(cmd->base.speed); 2496 2497 eth_proto_new = eth_proto_new & eth_proto_cap; 2498 if (!eth_proto_new) { 2499 netdev_err(dev, "No supported speed requested\n"); 2500 return -EINVAL; 2501 } 2502 2503 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 2504 eth_proto_new, autoneg); 2505 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 2506 if (err) 2507 return err; 2508 2509 if (!netif_running(dev)) 2510 return 0; 2511 2512 mlxsw_sp_port->link.autoneg = autoneg; 2513 2514 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false); 2515 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true); 2516 2517 return 0; 2518 } 2519 2520 static int mlxsw_sp_flash_device(struct net_device *dev, 2521 struct ethtool_flash *flash) 2522 { 2523 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 2524 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2525 const struct firmware *firmware; 2526 int err; 2527 2528 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS) 2529 return -EOPNOTSUPP; 2530 2531 dev_hold(dev); 2532 rtnl_unlock(); 2533 2534 err = request_firmware_direct(&firmware, flash->data, &dev->dev); 2535 if (err) 2536 goto out; 2537 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware); 2538 release_firmware(firmware); 2539 out: 2540 rtnl_lock(); 2541 dev_put(dev); 2542 return err; 2543 } 2544 2545 #define MLXSW_SP_I2C_ADDR_LOW 0x50 2546 #define MLXSW_SP_I2C_ADDR_HIGH 0x51 2547 #define MLXSW_SP_EEPROM_PAGE_LENGTH 256 2548 2549 static int mlxsw_sp_query_module_eeprom(struct mlxsw_sp_port *mlxsw_sp_port, 2550 u16 offset, u16 size, void *data, 2551 unsigned int *p_read_size) 2552 { 2553 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2554 char eeprom_tmp[MLXSW_SP_REG_MCIA_EEPROM_SIZE]; 2555 char mcia_pl[MLXSW_REG_MCIA_LEN]; 2556 u16 i2c_addr; 2557 int status; 2558 int err; 2559 2560 size = min_t(u16, size, MLXSW_SP_REG_MCIA_EEPROM_SIZE); 2561 2562 if (offset < MLXSW_SP_EEPROM_PAGE_LENGTH && 2563 offset + size > MLXSW_SP_EEPROM_PAGE_LENGTH) 2564 /* Cross pages read, read until offset 256 in low page */ 2565 size = MLXSW_SP_EEPROM_PAGE_LENGTH - offset; 2566 2567 i2c_addr = MLXSW_SP_I2C_ADDR_LOW; 2568 if (offset >= MLXSW_SP_EEPROM_PAGE_LENGTH) { 2569 i2c_addr = MLXSW_SP_I2C_ADDR_HIGH; 2570 offset -= MLXSW_SP_EEPROM_PAGE_LENGTH; 2571 } 2572 2573 mlxsw_reg_mcia_pack(mcia_pl, mlxsw_sp_port->mapping.module, 2574 0, 0, offset, size, i2c_addr); 2575 2576 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcia), mcia_pl); 2577 if (err) 2578 return err; 2579 2580 status = mlxsw_reg_mcia_status_get(mcia_pl); 2581 if (status) 2582 return -EIO; 2583 2584 mlxsw_reg_mcia_eeprom_memcpy_from(mcia_pl, eeprom_tmp); 2585 memcpy(data, eeprom_tmp, size); 2586 *p_read_size = size; 2587 2588 return 0; 2589 } 2590 2591 enum mlxsw_sp_eeprom_module_info_rev_id { 2592 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00, 2593 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01, 2594 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03, 2595 }; 2596 2597 enum mlxsw_sp_eeprom_module_info_id { 2598 MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP = 0x03, 2599 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP = 0x0C, 2600 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D, 2601 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11, 2602 }; 2603 2604 enum mlxsw_sp_eeprom_module_info { 2605 MLXSW_SP_EEPROM_MODULE_INFO_ID, 2606 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID, 2607 MLXSW_SP_EEPROM_MODULE_INFO_SIZE, 2608 }; 2609 2610 static int mlxsw_sp_get_module_info(struct net_device *netdev, 2611 struct ethtool_modinfo *modinfo) 2612 { 2613 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev); 2614 u8 module_info[MLXSW_SP_EEPROM_MODULE_INFO_SIZE]; 2615 u8 module_rev_id, module_id; 2616 unsigned int read_size; 2617 int err; 2618 2619 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, 0, 2620 MLXSW_SP_EEPROM_MODULE_INFO_SIZE, 2621 module_info, &read_size); 2622 if (err) 2623 return err; 2624 2625 if (read_size < MLXSW_SP_EEPROM_MODULE_INFO_SIZE) 2626 return -EIO; 2627 2628 module_rev_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_REV_ID]; 2629 module_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_ID]; 2630 2631 switch (module_id) { 2632 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP: 2633 modinfo->type = ETH_MODULE_SFF_8436; 2634 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 2635 break; 2636 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS: 2637 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28: 2638 if (module_id == MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 || 2639 module_rev_id >= MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636) { 2640 modinfo->type = ETH_MODULE_SFF_8636; 2641 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; 2642 } else { 2643 modinfo->type = ETH_MODULE_SFF_8436; 2644 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; 2645 } 2646 break; 2647 case MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP: 2648 modinfo->type = ETH_MODULE_SFF_8472; 2649 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 2650 break; 2651 default: 2652 return -EINVAL; 2653 } 2654 2655 return 0; 2656 } 2657 2658 static int mlxsw_sp_get_module_eeprom(struct net_device *netdev, 2659 struct ethtool_eeprom *ee, 2660 u8 *data) 2661 { 2662 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev); 2663 int offset = ee->offset; 2664 unsigned int read_size; 2665 int i = 0; 2666 int err; 2667 2668 if (!ee->len) 2669 return -EINVAL; 2670 2671 memset(data, 0, ee->len); 2672 2673 while (i < ee->len) { 2674 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, offset, 2675 ee->len - i, data + i, 2676 &read_size); 2677 if (err) { 2678 netdev_err(mlxsw_sp_port->dev, "Eeprom query failed\n"); 2679 return err; 2680 } 2681 2682 i += read_size; 2683 offset += read_size; 2684 } 2685 2686 return 0; 2687 } 2688 2689 static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = { 2690 .get_drvinfo = mlxsw_sp_port_get_drvinfo, 2691 .get_link = ethtool_op_get_link, 2692 .get_pauseparam = mlxsw_sp_port_get_pauseparam, 2693 .set_pauseparam = mlxsw_sp_port_set_pauseparam, 2694 .get_strings = mlxsw_sp_port_get_strings, 2695 .set_phys_id = mlxsw_sp_port_set_phys_id, 2696 .get_ethtool_stats = mlxsw_sp_port_get_stats, 2697 .get_sset_count = mlxsw_sp_port_get_sset_count, 2698 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings, 2699 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings, 2700 .flash_device = mlxsw_sp_flash_device, 2701 .get_module_info = mlxsw_sp_get_module_info, 2702 .get_module_eeprom = mlxsw_sp_get_module_eeprom, 2703 }; 2704 2705 static int 2706 mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width) 2707 { 2708 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2709 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width; 2710 char ptys_pl[MLXSW_REG_PTYS_LEN]; 2711 u32 eth_proto_admin; 2712 2713 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed); 2714 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 2715 eth_proto_admin, mlxsw_sp_port->link.autoneg); 2716 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl); 2717 } 2718 2719 int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port, 2720 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index, 2721 bool dwrr, u8 dwrr_weight) 2722 { 2723 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2724 char qeec_pl[MLXSW_REG_QEEC_LEN]; 2725 2726 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index, 2727 next_index); 2728 mlxsw_reg_qeec_de_set(qeec_pl, true); 2729 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr); 2730 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight); 2731 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl); 2732 } 2733 2734 int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port, 2735 enum mlxsw_reg_qeec_hr hr, u8 index, 2736 u8 next_index, u32 maxrate) 2737 { 2738 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2739 char qeec_pl[MLXSW_REG_QEEC_LEN]; 2740 2741 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index, 2742 next_index); 2743 mlxsw_reg_qeec_mase_set(qeec_pl, true); 2744 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate); 2745 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl); 2746 } 2747 2748 static int mlxsw_sp_port_min_bw_set(struct mlxsw_sp_port *mlxsw_sp_port, 2749 enum mlxsw_reg_qeec_hr hr, u8 index, 2750 u8 next_index, u32 minrate) 2751 { 2752 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2753 char qeec_pl[MLXSW_REG_QEEC_LEN]; 2754 2755 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index, 2756 next_index); 2757 mlxsw_reg_qeec_mise_set(qeec_pl, true); 2758 mlxsw_reg_qeec_min_shaper_rate_set(qeec_pl, minrate); 2759 2760 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl); 2761 } 2762 2763 int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port, 2764 u8 switch_prio, u8 tclass) 2765 { 2766 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2767 char qtct_pl[MLXSW_REG_QTCT_LEN]; 2768 2769 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio, 2770 tclass); 2771 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl); 2772 } 2773 2774 static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port) 2775 { 2776 int err, i; 2777 2778 /* Setup the elements hierarcy, so that each TC is linked to 2779 * one subgroup, which are all member in the same group. 2780 */ 2781 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 2782 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false, 2783 0); 2784 if (err) 2785 return err; 2786 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 2787 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 2788 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i, 2789 0, false, 0); 2790 if (err) 2791 return err; 2792 } 2793 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 2794 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 2795 MLXSW_REG_QEEC_HIERARCY_TC, i, i, 2796 false, 0); 2797 if (err) 2798 return err; 2799 2800 err = mlxsw_sp_port_ets_set(mlxsw_sp_port, 2801 MLXSW_REG_QEEC_HIERARCY_TC, 2802 i + 8, i, 2803 false, 0); 2804 if (err) 2805 return err; 2806 } 2807 2808 /* Make sure the max shaper is disabled in all hierarchies that 2809 * support it. 2810 */ 2811 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 2812 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0, 2813 MLXSW_REG_QEEC_MAS_DIS); 2814 if (err) 2815 return err; 2816 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 2817 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 2818 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, 2819 i, 0, 2820 MLXSW_REG_QEEC_MAS_DIS); 2821 if (err) 2822 return err; 2823 } 2824 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 2825 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 2826 MLXSW_REG_QEEC_HIERARCY_TC, 2827 i, i, 2828 MLXSW_REG_QEEC_MAS_DIS); 2829 if (err) 2830 return err; 2831 2832 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port, 2833 MLXSW_REG_QEEC_HIERARCY_TC, 2834 i + 8, i, 2835 MLXSW_REG_QEEC_MAS_DIS); 2836 if (err) 2837 return err; 2838 } 2839 2840 /* Configure the min shaper for multicast TCs. */ 2841 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 2842 err = mlxsw_sp_port_min_bw_set(mlxsw_sp_port, 2843 MLXSW_REG_QEEC_HIERARCY_TC, 2844 i + 8, i, 2845 MLXSW_REG_QEEC_MIS_MIN); 2846 if (err) 2847 return err; 2848 } 2849 2850 /* Map all priorities to traffic class 0. */ 2851 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { 2852 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0); 2853 if (err) 2854 return err; 2855 } 2856 2857 return 0; 2858 } 2859 2860 static int mlxsw_sp_port_tc_mc_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, 2861 bool enable) 2862 { 2863 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 2864 char qtctm_pl[MLXSW_REG_QTCTM_LEN]; 2865 2866 mlxsw_reg_qtctm_pack(qtctm_pl, mlxsw_sp_port->local_port, enable); 2867 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtctm), qtctm_pl); 2868 } 2869 2870 static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port, 2871 bool split, u8 module, u8 width, u8 lane) 2872 { 2873 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 2874 struct mlxsw_sp_port *mlxsw_sp_port; 2875 struct net_device *dev; 2876 int err; 2877 2878 err = mlxsw_core_port_init(mlxsw_sp->core, local_port); 2879 if (err) { 2880 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n", 2881 local_port); 2882 return err; 2883 } 2884 2885 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port)); 2886 if (!dev) { 2887 err = -ENOMEM; 2888 goto err_alloc_etherdev; 2889 } 2890 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev); 2891 mlxsw_sp_port = netdev_priv(dev); 2892 mlxsw_sp_port->dev = dev; 2893 mlxsw_sp_port->mlxsw_sp = mlxsw_sp; 2894 mlxsw_sp_port->local_port = local_port; 2895 mlxsw_sp_port->pvid = 1; 2896 mlxsw_sp_port->split = split; 2897 mlxsw_sp_port->mapping.module = module; 2898 mlxsw_sp_port->mapping.width = width; 2899 mlxsw_sp_port->mapping.lane = lane; 2900 mlxsw_sp_port->link.autoneg = 1; 2901 INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list); 2902 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list); 2903 2904 mlxsw_sp_port->pcpu_stats = 2905 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats); 2906 if (!mlxsw_sp_port->pcpu_stats) { 2907 err = -ENOMEM; 2908 goto err_alloc_stats; 2909 } 2910 2911 mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample), 2912 GFP_KERNEL); 2913 if (!mlxsw_sp_port->sample) { 2914 err = -ENOMEM; 2915 goto err_alloc_sample; 2916 } 2917 2918 INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw, 2919 &update_stats_cache); 2920 2921 dev->netdev_ops = &mlxsw_sp_port_netdev_ops; 2922 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops; 2923 2924 err = mlxsw_sp_port_module_map(mlxsw_sp_port, module, width, lane); 2925 if (err) { 2926 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n", 2927 mlxsw_sp_port->local_port); 2928 goto err_port_module_map; 2929 } 2930 2931 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0); 2932 if (err) { 2933 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n", 2934 mlxsw_sp_port->local_port); 2935 goto err_port_swid_set; 2936 } 2937 2938 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port); 2939 if (err) { 2940 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n", 2941 mlxsw_sp_port->local_port); 2942 goto err_dev_addr_init; 2943 } 2944 2945 netif_carrier_off(dev); 2946 2947 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG | 2948 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC; 2949 dev->hw_features |= NETIF_F_HW_TC; 2950 2951 dev->min_mtu = 0; 2952 dev->max_mtu = ETH_MAX_MTU; 2953 2954 /* Each packet needs to have a Tx header (metadata) on top all other 2955 * headers. 2956 */ 2957 dev->needed_headroom = MLXSW_TXHDR_LEN; 2958 2959 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port); 2960 if (err) { 2961 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n", 2962 mlxsw_sp_port->local_port); 2963 goto err_port_system_port_mapping_set; 2964 } 2965 2966 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width); 2967 if (err) { 2968 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n", 2969 mlxsw_sp_port->local_port); 2970 goto err_port_speed_by_width_set; 2971 } 2972 2973 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN); 2974 if (err) { 2975 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n", 2976 mlxsw_sp_port->local_port); 2977 goto err_port_mtu_set; 2978 } 2979 2980 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false); 2981 if (err) 2982 goto err_port_admin_status_set; 2983 2984 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port); 2985 if (err) { 2986 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n", 2987 mlxsw_sp_port->local_port); 2988 goto err_port_buffers_init; 2989 } 2990 2991 err = mlxsw_sp_port_ets_init(mlxsw_sp_port); 2992 if (err) { 2993 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n", 2994 mlxsw_sp_port->local_port); 2995 goto err_port_ets_init; 2996 } 2997 2998 err = mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, true); 2999 if (err) { 3000 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC MC mode\n", 3001 mlxsw_sp_port->local_port); 3002 goto err_port_tc_mc_mode; 3003 } 3004 3005 /* ETS and buffers must be initialized before DCB. */ 3006 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port); 3007 if (err) { 3008 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n", 3009 mlxsw_sp_port->local_port); 3010 goto err_port_dcb_init; 3011 } 3012 3013 err = mlxsw_sp_port_fids_init(mlxsw_sp_port); 3014 if (err) { 3015 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n", 3016 mlxsw_sp_port->local_port); 3017 goto err_port_fids_init; 3018 } 3019 3020 err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port); 3021 if (err) { 3022 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n", 3023 mlxsw_sp_port->local_port); 3024 goto err_port_qdiscs_init; 3025 } 3026 3027 err = mlxsw_sp_port_nve_init(mlxsw_sp_port); 3028 if (err) { 3029 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize NVE\n", 3030 mlxsw_sp_port->local_port); 3031 goto err_port_nve_init; 3032 } 3033 3034 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1); 3035 if (IS_ERR(mlxsw_sp_port_vlan)) { 3036 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n", 3037 mlxsw_sp_port->local_port); 3038 err = PTR_ERR(mlxsw_sp_port_vlan); 3039 goto err_port_vlan_get; 3040 } 3041 3042 mlxsw_sp_port_switchdev_init(mlxsw_sp_port); 3043 mlxsw_sp->ports[local_port] = mlxsw_sp_port; 3044 err = register_netdev(dev); 3045 if (err) { 3046 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n", 3047 mlxsw_sp_port->local_port); 3048 goto err_register_netdev; 3049 } 3050 3051 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port, 3052 mlxsw_sp_port, dev, module + 1, 3053 mlxsw_sp_port->split, lane / width); 3054 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0); 3055 return 0; 3056 3057 err_register_netdev: 3058 mlxsw_sp->ports[local_port] = NULL; 3059 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port); 3060 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan); 3061 err_port_vlan_get: 3062 mlxsw_sp_port_nve_fini(mlxsw_sp_port); 3063 err_port_nve_init: 3064 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port); 3065 err_port_qdiscs_init: 3066 mlxsw_sp_port_fids_fini(mlxsw_sp_port); 3067 err_port_fids_init: 3068 mlxsw_sp_port_dcb_fini(mlxsw_sp_port); 3069 err_port_dcb_init: 3070 mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false); 3071 err_port_tc_mc_mode: 3072 err_port_ets_init: 3073 err_port_buffers_init: 3074 err_port_admin_status_set: 3075 err_port_mtu_set: 3076 err_port_speed_by_width_set: 3077 err_port_system_port_mapping_set: 3078 err_dev_addr_init: 3079 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT); 3080 err_port_swid_set: 3081 mlxsw_sp_port_module_unmap(mlxsw_sp_port); 3082 err_port_module_map: 3083 kfree(mlxsw_sp_port->sample); 3084 err_alloc_sample: 3085 free_percpu(mlxsw_sp_port->pcpu_stats); 3086 err_alloc_stats: 3087 free_netdev(dev); 3088 err_alloc_etherdev: 3089 mlxsw_core_port_fini(mlxsw_sp->core, local_port); 3090 return err; 3091 } 3092 3093 static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port) 3094 { 3095 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port]; 3096 3097 cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw); 3098 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp); 3099 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */ 3100 mlxsw_sp->ports[local_port] = NULL; 3101 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port); 3102 mlxsw_sp_port_vlan_flush(mlxsw_sp_port); 3103 mlxsw_sp_port_nve_fini(mlxsw_sp_port); 3104 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port); 3105 mlxsw_sp_port_fids_fini(mlxsw_sp_port); 3106 mlxsw_sp_port_dcb_fini(mlxsw_sp_port); 3107 mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false); 3108 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT); 3109 mlxsw_sp_port_module_unmap(mlxsw_sp_port); 3110 kfree(mlxsw_sp_port->sample); 3111 free_percpu(mlxsw_sp_port->pcpu_stats); 3112 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list)); 3113 free_netdev(mlxsw_sp_port->dev); 3114 mlxsw_core_port_fini(mlxsw_sp->core, local_port); 3115 } 3116 3117 static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port) 3118 { 3119 return mlxsw_sp->ports[local_port] != NULL; 3120 } 3121 3122 static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp) 3123 { 3124 int i; 3125 3126 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++) 3127 if (mlxsw_sp_port_created(mlxsw_sp, i)) 3128 mlxsw_sp_port_remove(mlxsw_sp, i); 3129 kfree(mlxsw_sp->port_to_module); 3130 kfree(mlxsw_sp->ports); 3131 } 3132 3133 static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp) 3134 { 3135 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core); 3136 u8 module, width, lane; 3137 size_t alloc_size; 3138 int i; 3139 int err; 3140 3141 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports; 3142 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL); 3143 if (!mlxsw_sp->ports) 3144 return -ENOMEM; 3145 3146 mlxsw_sp->port_to_module = kmalloc_array(max_ports, sizeof(int), 3147 GFP_KERNEL); 3148 if (!mlxsw_sp->port_to_module) { 3149 err = -ENOMEM; 3150 goto err_port_to_module_alloc; 3151 } 3152 3153 for (i = 1; i < max_ports; i++) { 3154 /* Mark as invalid */ 3155 mlxsw_sp->port_to_module[i] = -1; 3156 3157 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module, 3158 &width, &lane); 3159 if (err) 3160 goto err_port_module_info_get; 3161 if (!width) 3162 continue; 3163 mlxsw_sp->port_to_module[i] = module; 3164 err = mlxsw_sp_port_create(mlxsw_sp, i, false, 3165 module, width, lane); 3166 if (err) 3167 goto err_port_create; 3168 } 3169 return 0; 3170 3171 err_port_create: 3172 err_port_module_info_get: 3173 for (i--; i >= 1; i--) 3174 if (mlxsw_sp_port_created(mlxsw_sp, i)) 3175 mlxsw_sp_port_remove(mlxsw_sp, i); 3176 kfree(mlxsw_sp->port_to_module); 3177 err_port_to_module_alloc: 3178 kfree(mlxsw_sp->ports); 3179 return err; 3180 } 3181 3182 static u8 mlxsw_sp_cluster_base_port_get(u8 local_port) 3183 { 3184 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX; 3185 3186 return local_port - offset; 3187 } 3188 3189 static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port, 3190 u8 module, unsigned int count) 3191 { 3192 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count; 3193 int err, i; 3194 3195 for (i = 0; i < count; i++) { 3196 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true, 3197 module, width, i * width); 3198 if (err) 3199 goto err_port_create; 3200 } 3201 3202 return 0; 3203 3204 err_port_create: 3205 for (i--; i >= 0; i--) 3206 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i)) 3207 mlxsw_sp_port_remove(mlxsw_sp, base_port + i); 3208 return err; 3209 } 3210 3211 static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp, 3212 u8 base_port, unsigned int count) 3213 { 3214 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH; 3215 int i; 3216 3217 /* Split by four means we need to re-create two ports, otherwise 3218 * only one. 3219 */ 3220 count = count / 2; 3221 3222 for (i = 0; i < count; i++) { 3223 local_port = base_port + i * 2; 3224 if (mlxsw_sp->port_to_module[local_port] < 0) 3225 continue; 3226 module = mlxsw_sp->port_to_module[local_port]; 3227 3228 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module, 3229 width, 0); 3230 } 3231 } 3232 3233 static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port, 3234 unsigned int count, 3235 struct netlink_ext_ack *extack) 3236 { 3237 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3238 struct mlxsw_sp_port *mlxsw_sp_port; 3239 u8 module, cur_width, base_port; 3240 int i; 3241 int err; 3242 3243 mlxsw_sp_port = mlxsw_sp->ports[local_port]; 3244 if (!mlxsw_sp_port) { 3245 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n", 3246 local_port); 3247 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist"); 3248 return -EINVAL; 3249 } 3250 3251 module = mlxsw_sp_port->mapping.module; 3252 cur_width = mlxsw_sp_port->mapping.width; 3253 3254 if (count != 2 && count != 4) { 3255 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n"); 3256 NL_SET_ERR_MSG_MOD(extack, "Port can only be split into 2 or 4 ports"); 3257 return -EINVAL; 3258 } 3259 3260 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) { 3261 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n"); 3262 NL_SET_ERR_MSG_MOD(extack, "Port cannot be split further"); 3263 return -EINVAL; 3264 } 3265 3266 /* Make sure we have enough slave (even) ports for the split. */ 3267 if (count == 2) { 3268 base_port = local_port; 3269 if (mlxsw_sp->ports[base_port + 1]) { 3270 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n"); 3271 NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration"); 3272 return -EINVAL; 3273 } 3274 } else { 3275 base_port = mlxsw_sp_cluster_base_port_get(local_port); 3276 if (mlxsw_sp->ports[base_port + 1] || 3277 mlxsw_sp->ports[base_port + 3]) { 3278 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n"); 3279 NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration"); 3280 return -EINVAL; 3281 } 3282 } 3283 3284 for (i = 0; i < count; i++) 3285 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i)) 3286 mlxsw_sp_port_remove(mlxsw_sp, base_port + i); 3287 3288 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count); 3289 if (err) { 3290 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n"); 3291 goto err_port_split_create; 3292 } 3293 3294 return 0; 3295 3296 err_port_split_create: 3297 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count); 3298 return err; 3299 } 3300 3301 static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port, 3302 struct netlink_ext_ack *extack) 3303 { 3304 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3305 struct mlxsw_sp_port *mlxsw_sp_port; 3306 u8 cur_width, base_port; 3307 unsigned int count; 3308 int i; 3309 3310 mlxsw_sp_port = mlxsw_sp->ports[local_port]; 3311 if (!mlxsw_sp_port) { 3312 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n", 3313 local_port); 3314 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist"); 3315 return -EINVAL; 3316 } 3317 3318 if (!mlxsw_sp_port->split) { 3319 netdev_err(mlxsw_sp_port->dev, "Port was not split\n"); 3320 NL_SET_ERR_MSG_MOD(extack, "Port was not split"); 3321 return -EINVAL; 3322 } 3323 3324 cur_width = mlxsw_sp_port->mapping.width; 3325 count = cur_width == 1 ? 4 : 2; 3326 3327 base_port = mlxsw_sp_cluster_base_port_get(local_port); 3328 3329 /* Determine which ports to remove. */ 3330 if (count == 2 && local_port >= base_port + 2) 3331 base_port = base_port + 2; 3332 3333 for (i = 0; i < count; i++) 3334 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i)) 3335 mlxsw_sp_port_remove(mlxsw_sp, base_port + i); 3336 3337 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count); 3338 3339 return 0; 3340 } 3341 3342 static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg, 3343 char *pude_pl, void *priv) 3344 { 3345 struct mlxsw_sp *mlxsw_sp = priv; 3346 struct mlxsw_sp_port *mlxsw_sp_port; 3347 enum mlxsw_reg_pude_oper_status status; 3348 u8 local_port; 3349 3350 local_port = mlxsw_reg_pude_local_port_get(pude_pl); 3351 mlxsw_sp_port = mlxsw_sp->ports[local_port]; 3352 if (!mlxsw_sp_port) 3353 return; 3354 3355 status = mlxsw_reg_pude_oper_status_get(pude_pl); 3356 if (status == MLXSW_PORT_OPER_STATUS_UP) { 3357 netdev_info(mlxsw_sp_port->dev, "link up\n"); 3358 netif_carrier_on(mlxsw_sp_port->dev); 3359 } else { 3360 netdev_info(mlxsw_sp_port->dev, "link down\n"); 3361 netif_carrier_off(mlxsw_sp_port->dev); 3362 } 3363 } 3364 3365 static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb, 3366 u8 local_port, void *priv) 3367 { 3368 struct mlxsw_sp *mlxsw_sp = priv; 3369 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port]; 3370 struct mlxsw_sp_port_pcpu_stats *pcpu_stats; 3371 3372 if (unlikely(!mlxsw_sp_port)) { 3373 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n", 3374 local_port); 3375 return; 3376 } 3377 3378 skb->dev = mlxsw_sp_port->dev; 3379 3380 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats); 3381 u64_stats_update_begin(&pcpu_stats->syncp); 3382 pcpu_stats->rx_packets++; 3383 pcpu_stats->rx_bytes += skb->len; 3384 u64_stats_update_end(&pcpu_stats->syncp); 3385 3386 skb->protocol = eth_type_trans(skb, skb->dev); 3387 netif_receive_skb(skb); 3388 } 3389 3390 static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port, 3391 void *priv) 3392 { 3393 skb->offload_fwd_mark = 1; 3394 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv); 3395 } 3396 3397 static void mlxsw_sp_rx_listener_mr_mark_func(struct sk_buff *skb, 3398 u8 local_port, void *priv) 3399 { 3400 skb->offload_mr_fwd_mark = 1; 3401 skb->offload_fwd_mark = 1; 3402 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv); 3403 } 3404 3405 static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port, 3406 void *priv) 3407 { 3408 struct mlxsw_sp *mlxsw_sp = priv; 3409 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port]; 3410 struct psample_group *psample_group; 3411 u32 size; 3412 3413 if (unlikely(!mlxsw_sp_port)) { 3414 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n", 3415 local_port); 3416 goto out; 3417 } 3418 if (unlikely(!mlxsw_sp_port->sample)) { 3419 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n", 3420 local_port); 3421 goto out; 3422 } 3423 3424 size = mlxsw_sp_port->sample->truncate ? 3425 mlxsw_sp_port->sample->trunc_size : skb->len; 3426 3427 rcu_read_lock(); 3428 psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group); 3429 if (!psample_group) 3430 goto out_unlock; 3431 psample_sample_packet(psample_group, skb, size, 3432 mlxsw_sp_port->dev->ifindex, 0, 3433 mlxsw_sp_port->sample->rate); 3434 out_unlock: 3435 rcu_read_unlock(); 3436 out: 3437 consume_skb(skb); 3438 } 3439 3440 #define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \ 3441 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \ 3442 _is_ctrl, SP_##_trap_group, DISCARD) 3443 3444 #define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \ 3445 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \ 3446 _is_ctrl, SP_##_trap_group, DISCARD) 3447 3448 #define MLXSW_SP_RXL_MR_MARK(_trap_id, _action, _trap_group, _is_ctrl) \ 3449 MLXSW_RXL(mlxsw_sp_rx_listener_mr_mark_func, _trap_id, _action, \ 3450 _is_ctrl, SP_##_trap_group, DISCARD) 3451 3452 #define MLXSW_SP_EVENTL(_func, _trap_id) \ 3453 MLXSW_EVENTL(_func, _trap_id, SP_EVENT) 3454 3455 static const struct mlxsw_listener mlxsw_sp_listener[] = { 3456 /* Events */ 3457 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE), 3458 /* L2 traps */ 3459 MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true), 3460 MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true), 3461 MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true), 3462 MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false), 3463 MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false), 3464 MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false), 3465 MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false), 3466 MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false), 3467 MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false), 3468 MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false), 3469 MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false), 3470 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false), 3471 MLXSW_SP_RXL_MARK(IPV6_MLDV12_LISTENER_QUERY, MIRROR_TO_CPU, IPV6_MLD, 3472 false), 3473 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD, 3474 false), 3475 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_DONE, TRAP_TO_CPU, IPV6_MLD, 3476 false), 3477 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV2_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD, 3478 false), 3479 /* L3 traps */ 3480 MLXSW_SP_RXL_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false), 3481 MLXSW_SP_RXL_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false), 3482 MLXSW_SP_RXL_MARK(LBERROR, TRAP_TO_CPU, ROUTER_EXP, false), 3483 MLXSW_SP_RXL_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false), 3484 MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP, 3485 false), 3486 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, false), 3487 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false), 3488 MLXSW_SP_RXL_MARK(IPV6_ALL_NODES_LINK, TRAP_TO_CPU, ROUTER_EXP, false), 3489 MLXSW_SP_RXL_MARK(IPV6_ALL_ROUTERS_LINK, TRAP_TO_CPU, ROUTER_EXP, 3490 false), 3491 MLXSW_SP_RXL_MARK(IPV4_OSPF, TRAP_TO_CPU, OSPF, false), 3492 MLXSW_SP_RXL_MARK(IPV6_OSPF, TRAP_TO_CPU, OSPF, false), 3493 MLXSW_SP_RXL_MARK(IPV6_DHCP, TRAP_TO_CPU, DHCP, false), 3494 MLXSW_SP_RXL_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false), 3495 MLXSW_SP_RXL_MARK(IPV4_BGP, TRAP_TO_CPU, BGP, false), 3496 MLXSW_SP_RXL_MARK(IPV6_BGP, TRAP_TO_CPU, BGP, false), 3497 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_SOLICITATION, TRAP_TO_CPU, IPV6_ND, 3498 false), 3499 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND, 3500 false), 3501 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_SOLICITATION, TRAP_TO_CPU, IPV6_ND, 3502 false), 3503 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND, 3504 false), 3505 MLXSW_SP_RXL_MARK(L3_IPV6_REDIRECTION, TRAP_TO_CPU, IPV6_ND, false), 3506 MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, 3507 false), 3508 MLXSW_SP_RXL_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, HOST_MISS, false), 3509 MLXSW_SP_RXL_MARK(HOST_MISS_IPV6, TRAP_TO_CPU, HOST_MISS, false), 3510 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV4, TRAP_TO_CPU, ROUTER_EXP, false), 3511 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV6, TRAP_TO_CPU, ROUTER_EXP, false), 3512 MLXSW_SP_RXL_MARK(IPIP_DECAP_ERROR, TRAP_TO_CPU, ROUTER_EXP, false), 3513 MLXSW_SP_RXL_MARK(DECAP_ECN0, TRAP_TO_CPU, ROUTER_EXP, false), 3514 MLXSW_SP_RXL_MARK(IPV4_VRRP, TRAP_TO_CPU, ROUTER_EXP, false), 3515 MLXSW_SP_RXL_MARK(IPV6_VRRP, TRAP_TO_CPU, ROUTER_EXP, false), 3516 /* PKT Sample trap */ 3517 MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU, 3518 false, SP_IP2ME, DISCARD), 3519 /* ACL trap */ 3520 MLXSW_SP_RXL_NO_MARK(ACL0, TRAP_TO_CPU, IP2ME, false), 3521 /* Multicast Router Traps */ 3522 MLXSW_SP_RXL_MARK(IPV4_PIM, TRAP_TO_CPU, PIM, false), 3523 MLXSW_SP_RXL_MARK(IPV6_PIM, TRAP_TO_CPU, PIM, false), 3524 MLXSW_SP_RXL_MARK(RPF, TRAP_TO_CPU, RPF, false), 3525 MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false), 3526 MLXSW_SP_RXL_MR_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false), 3527 /* NVE traps */ 3528 MLXSW_SP_RXL_MARK(NVE_ENCAP_ARP, TRAP_TO_CPU, ARP, false), 3529 MLXSW_SP_RXL_NO_MARK(NVE_DECAP_ARP, TRAP_TO_CPU, ARP, false), 3530 }; 3531 3532 static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core) 3533 { 3534 char qpcr_pl[MLXSW_REG_QPCR_LEN]; 3535 enum mlxsw_reg_qpcr_ir_units ir_units; 3536 int max_cpu_policers; 3537 bool is_bytes; 3538 u8 burst_size; 3539 u32 rate; 3540 int i, err; 3541 3542 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS)) 3543 return -EIO; 3544 3545 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS); 3546 3547 ir_units = MLXSW_REG_QPCR_IR_UNITS_M; 3548 for (i = 0; i < max_cpu_policers; i++) { 3549 is_bytes = false; 3550 switch (i) { 3551 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP: 3552 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP: 3553 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP: 3554 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF: 3555 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM: 3556 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF: 3557 rate = 128; 3558 burst_size = 7; 3559 break; 3560 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP: 3561 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD: 3562 rate = 16 * 1024; 3563 burst_size = 10; 3564 break; 3565 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP: 3566 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP: 3567 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP: 3568 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS: 3569 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP: 3570 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE: 3571 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND: 3572 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST: 3573 rate = 1024; 3574 burst_size = 7; 3575 break; 3576 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME: 3577 rate = 4 * 1024; 3578 burst_size = 4; 3579 break; 3580 default: 3581 continue; 3582 } 3583 3584 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate, 3585 burst_size); 3586 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl); 3587 if (err) 3588 return err; 3589 } 3590 3591 return 0; 3592 } 3593 3594 static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core) 3595 { 3596 char htgt_pl[MLXSW_REG_HTGT_LEN]; 3597 enum mlxsw_reg_htgt_trap_group i; 3598 int max_cpu_policers; 3599 int max_trap_groups; 3600 u8 priority, tc; 3601 u16 policer_id; 3602 int err; 3603 3604 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS)) 3605 return -EIO; 3606 3607 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS); 3608 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS); 3609 3610 for (i = 0; i < max_trap_groups; i++) { 3611 policer_id = i; 3612 switch (i) { 3613 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP: 3614 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP: 3615 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP: 3616 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF: 3617 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM: 3618 priority = 5; 3619 tc = 5; 3620 break; 3621 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP: 3622 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP: 3623 priority = 4; 3624 tc = 4; 3625 break; 3626 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP: 3627 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME: 3628 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD: 3629 priority = 3; 3630 tc = 3; 3631 break; 3632 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP: 3633 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND: 3634 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF: 3635 priority = 2; 3636 tc = 2; 3637 break; 3638 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS: 3639 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP: 3640 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE: 3641 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST: 3642 priority = 1; 3643 tc = 1; 3644 break; 3645 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT: 3646 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY; 3647 tc = MLXSW_REG_HTGT_DEFAULT_TC; 3648 policer_id = MLXSW_REG_HTGT_INVALID_POLICER; 3649 break; 3650 default: 3651 continue; 3652 } 3653 3654 if (max_cpu_policers <= policer_id && 3655 policer_id != MLXSW_REG_HTGT_INVALID_POLICER) 3656 return -EIO; 3657 3658 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc); 3659 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl); 3660 if (err) 3661 return err; 3662 } 3663 3664 return 0; 3665 } 3666 3667 static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp) 3668 { 3669 int i; 3670 int err; 3671 3672 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core); 3673 if (err) 3674 return err; 3675 3676 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core); 3677 if (err) 3678 return err; 3679 3680 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) { 3681 err = mlxsw_core_trap_register(mlxsw_sp->core, 3682 &mlxsw_sp_listener[i], 3683 mlxsw_sp); 3684 if (err) 3685 goto err_listener_register; 3686 3687 } 3688 return 0; 3689 3690 err_listener_register: 3691 for (i--; i >= 0; i--) { 3692 mlxsw_core_trap_unregister(mlxsw_sp->core, 3693 &mlxsw_sp_listener[i], 3694 mlxsw_sp); 3695 } 3696 return err; 3697 } 3698 3699 static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp) 3700 { 3701 int i; 3702 3703 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) { 3704 mlxsw_core_trap_unregister(mlxsw_sp->core, 3705 &mlxsw_sp_listener[i], 3706 mlxsw_sp); 3707 } 3708 } 3709 3710 static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp) 3711 { 3712 char slcr_pl[MLXSW_REG_SLCR_LEN]; 3713 u32 seed; 3714 int err; 3715 3716 get_random_bytes(&seed, sizeof(seed)); 3717 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC | 3718 MLXSW_REG_SLCR_LAG_HASH_DMAC | 3719 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE | 3720 MLXSW_REG_SLCR_LAG_HASH_VLANID | 3721 MLXSW_REG_SLCR_LAG_HASH_SIP | 3722 MLXSW_REG_SLCR_LAG_HASH_DIP | 3723 MLXSW_REG_SLCR_LAG_HASH_SPORT | 3724 MLXSW_REG_SLCR_LAG_HASH_DPORT | 3725 MLXSW_REG_SLCR_LAG_HASH_IPPROTO, seed); 3726 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl); 3727 if (err) 3728 return err; 3729 3730 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) || 3731 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS)) 3732 return -EIO; 3733 3734 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG), 3735 sizeof(struct mlxsw_sp_upper), 3736 GFP_KERNEL); 3737 if (!mlxsw_sp->lags) 3738 return -ENOMEM; 3739 3740 return 0; 3741 } 3742 3743 static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp) 3744 { 3745 kfree(mlxsw_sp->lags); 3746 } 3747 3748 static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core) 3749 { 3750 char htgt_pl[MLXSW_REG_HTGT_LEN]; 3751 3752 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 3753 MLXSW_REG_HTGT_INVALID_POLICER, 3754 MLXSW_REG_HTGT_DEFAULT_PRIORITY, 3755 MLXSW_REG_HTGT_DEFAULT_TC); 3756 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl); 3757 } 3758 3759 static int mlxsw_sp_netdevice_event(struct notifier_block *unused, 3760 unsigned long event, void *ptr); 3761 3762 static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core, 3763 const struct mlxsw_bus_info *mlxsw_bus_info) 3764 { 3765 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3766 int err; 3767 3768 mlxsw_sp->core = mlxsw_core; 3769 mlxsw_sp->bus_info = mlxsw_bus_info; 3770 3771 err = mlxsw_sp_fw_rev_validate(mlxsw_sp); 3772 if (err) 3773 return err; 3774 3775 err = mlxsw_sp_base_mac_get(mlxsw_sp); 3776 if (err) { 3777 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n"); 3778 return err; 3779 } 3780 3781 err = mlxsw_sp_kvdl_init(mlxsw_sp); 3782 if (err) { 3783 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n"); 3784 return err; 3785 } 3786 3787 err = mlxsw_sp_fids_init(mlxsw_sp); 3788 if (err) { 3789 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n"); 3790 goto err_fids_init; 3791 } 3792 3793 err = mlxsw_sp_traps_init(mlxsw_sp); 3794 if (err) { 3795 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n"); 3796 goto err_traps_init; 3797 } 3798 3799 err = mlxsw_sp_buffers_init(mlxsw_sp); 3800 if (err) { 3801 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n"); 3802 goto err_buffers_init; 3803 } 3804 3805 err = mlxsw_sp_lag_init(mlxsw_sp); 3806 if (err) { 3807 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n"); 3808 goto err_lag_init; 3809 } 3810 3811 /* Initialize SPAN before router and switchdev, so that those components 3812 * can call mlxsw_sp_span_respin(). 3813 */ 3814 err = mlxsw_sp_span_init(mlxsw_sp); 3815 if (err) { 3816 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n"); 3817 goto err_span_init; 3818 } 3819 3820 err = mlxsw_sp_switchdev_init(mlxsw_sp); 3821 if (err) { 3822 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n"); 3823 goto err_switchdev_init; 3824 } 3825 3826 err = mlxsw_sp_counter_pool_init(mlxsw_sp); 3827 if (err) { 3828 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n"); 3829 goto err_counter_pool_init; 3830 } 3831 3832 err = mlxsw_sp_afa_init(mlxsw_sp); 3833 if (err) { 3834 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n"); 3835 goto err_afa_init; 3836 } 3837 3838 err = mlxsw_sp_nve_init(mlxsw_sp); 3839 if (err) { 3840 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize NVE\n"); 3841 goto err_nve_init; 3842 } 3843 3844 err = mlxsw_sp_router_init(mlxsw_sp); 3845 if (err) { 3846 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n"); 3847 goto err_router_init; 3848 } 3849 3850 /* Initialize netdevice notifier after router and SPAN is initialized, 3851 * so that the event handler can use router structures and call SPAN 3852 * respin. 3853 */ 3854 mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event; 3855 err = register_netdevice_notifier(&mlxsw_sp->netdevice_nb); 3856 if (err) { 3857 dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n"); 3858 goto err_netdev_notifier; 3859 } 3860 3861 err = mlxsw_sp_acl_init(mlxsw_sp); 3862 if (err) { 3863 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n"); 3864 goto err_acl_init; 3865 } 3866 3867 err = mlxsw_sp_dpipe_init(mlxsw_sp); 3868 if (err) { 3869 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n"); 3870 goto err_dpipe_init; 3871 } 3872 3873 err = mlxsw_sp_ports_create(mlxsw_sp); 3874 if (err) { 3875 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n"); 3876 goto err_ports_create; 3877 } 3878 3879 return 0; 3880 3881 err_ports_create: 3882 mlxsw_sp_dpipe_fini(mlxsw_sp); 3883 err_dpipe_init: 3884 mlxsw_sp_acl_fini(mlxsw_sp); 3885 err_acl_init: 3886 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb); 3887 err_netdev_notifier: 3888 mlxsw_sp_router_fini(mlxsw_sp); 3889 err_router_init: 3890 mlxsw_sp_nve_fini(mlxsw_sp); 3891 err_nve_init: 3892 mlxsw_sp_afa_fini(mlxsw_sp); 3893 err_afa_init: 3894 mlxsw_sp_counter_pool_fini(mlxsw_sp); 3895 err_counter_pool_init: 3896 mlxsw_sp_switchdev_fini(mlxsw_sp); 3897 err_switchdev_init: 3898 mlxsw_sp_span_fini(mlxsw_sp); 3899 err_span_init: 3900 mlxsw_sp_lag_fini(mlxsw_sp); 3901 err_lag_init: 3902 mlxsw_sp_buffers_fini(mlxsw_sp); 3903 err_buffers_init: 3904 mlxsw_sp_traps_fini(mlxsw_sp); 3905 err_traps_init: 3906 mlxsw_sp_fids_fini(mlxsw_sp); 3907 err_fids_init: 3908 mlxsw_sp_kvdl_fini(mlxsw_sp); 3909 return err; 3910 } 3911 3912 static int mlxsw_sp1_init(struct mlxsw_core *mlxsw_core, 3913 const struct mlxsw_bus_info *mlxsw_bus_info) 3914 { 3915 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3916 3917 mlxsw_sp->req_rev = &mlxsw_sp1_fw_rev; 3918 mlxsw_sp->fw_filename = MLXSW_SP1_FW_FILENAME; 3919 mlxsw_sp->kvdl_ops = &mlxsw_sp1_kvdl_ops; 3920 mlxsw_sp->afa_ops = &mlxsw_sp1_act_afa_ops; 3921 mlxsw_sp->afk_ops = &mlxsw_sp1_afk_ops; 3922 mlxsw_sp->mr_tcam_ops = &mlxsw_sp1_mr_tcam_ops; 3923 mlxsw_sp->acl_tcam_ops = &mlxsw_sp1_acl_tcam_ops; 3924 mlxsw_sp->nve_ops_arr = mlxsw_sp1_nve_ops_arr; 3925 3926 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info); 3927 } 3928 3929 static int mlxsw_sp2_init(struct mlxsw_core *mlxsw_core, 3930 const struct mlxsw_bus_info *mlxsw_bus_info) 3931 { 3932 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3933 3934 mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops; 3935 mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops; 3936 mlxsw_sp->afk_ops = &mlxsw_sp2_afk_ops; 3937 mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops; 3938 mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops; 3939 mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr; 3940 3941 return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info); 3942 } 3943 3944 static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core) 3945 { 3946 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core); 3947 3948 mlxsw_sp_ports_remove(mlxsw_sp); 3949 mlxsw_sp_dpipe_fini(mlxsw_sp); 3950 mlxsw_sp_acl_fini(mlxsw_sp); 3951 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb); 3952 mlxsw_sp_router_fini(mlxsw_sp); 3953 mlxsw_sp_nve_fini(mlxsw_sp); 3954 mlxsw_sp_afa_fini(mlxsw_sp); 3955 mlxsw_sp_counter_pool_fini(mlxsw_sp); 3956 mlxsw_sp_switchdev_fini(mlxsw_sp); 3957 mlxsw_sp_span_fini(mlxsw_sp); 3958 mlxsw_sp_lag_fini(mlxsw_sp); 3959 mlxsw_sp_buffers_fini(mlxsw_sp); 3960 mlxsw_sp_traps_fini(mlxsw_sp); 3961 mlxsw_sp_fids_fini(mlxsw_sp); 3962 mlxsw_sp_kvdl_fini(mlxsw_sp); 3963 } 3964 3965 static const struct mlxsw_config_profile mlxsw_sp1_config_profile = { 3966 .used_max_mid = 1, 3967 .max_mid = MLXSW_SP_MID_MAX, 3968 .used_flood_tables = 1, 3969 .used_flood_mode = 1, 3970 .flood_mode = 3, 3971 .max_fid_offset_flood_tables = 3, 3972 .fid_offset_flood_table_size = VLAN_N_VID - 1, 3973 .max_fid_flood_tables = 3, 3974 .fid_flood_table_size = MLXSW_SP_FID_8021D_MAX, 3975 .used_max_ib_mc = 1, 3976 .max_ib_mc = 0, 3977 .used_max_pkey = 1, 3978 .max_pkey = 0, 3979 .used_kvd_sizes = 1, 3980 .kvd_hash_single_parts = 59, 3981 .kvd_hash_double_parts = 41, 3982 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE, 3983 .swid_config = { 3984 { 3985 .used_type = 1, 3986 .type = MLXSW_PORT_SWID_TYPE_ETH, 3987 } 3988 }, 3989 }; 3990 3991 static const struct mlxsw_config_profile mlxsw_sp2_config_profile = { 3992 .used_max_mid = 1, 3993 .max_mid = MLXSW_SP_MID_MAX, 3994 .used_flood_tables = 1, 3995 .used_flood_mode = 1, 3996 .flood_mode = 3, 3997 .max_fid_offset_flood_tables = 3, 3998 .fid_offset_flood_table_size = VLAN_N_VID - 1, 3999 .max_fid_flood_tables = 3, 4000 .fid_flood_table_size = MLXSW_SP_FID_8021D_MAX, 4001 .used_max_ib_mc = 1, 4002 .max_ib_mc = 0, 4003 .used_max_pkey = 1, 4004 .max_pkey = 0, 4005 .swid_config = { 4006 { 4007 .used_type = 1, 4008 .type = MLXSW_PORT_SWID_TYPE_ETH, 4009 } 4010 }, 4011 }; 4012 4013 static void 4014 mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core, 4015 struct devlink_resource_size_params *kvd_size_params, 4016 struct devlink_resource_size_params *linear_size_params, 4017 struct devlink_resource_size_params *hash_double_size_params, 4018 struct devlink_resource_size_params *hash_single_size_params) 4019 { 4020 u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core, 4021 KVD_SINGLE_MIN_SIZE); 4022 u32 double_size_min = MLXSW_CORE_RES_GET(mlxsw_core, 4023 KVD_DOUBLE_MIN_SIZE); 4024 u32 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE); 4025 u32 linear_size_min = 0; 4026 4027 devlink_resource_size_params_init(kvd_size_params, kvd_size, kvd_size, 4028 MLXSW_SP_KVD_GRANULARITY, 4029 DEVLINK_RESOURCE_UNIT_ENTRY); 4030 devlink_resource_size_params_init(linear_size_params, linear_size_min, 4031 kvd_size - single_size_min - 4032 double_size_min, 4033 MLXSW_SP_KVD_GRANULARITY, 4034 DEVLINK_RESOURCE_UNIT_ENTRY); 4035 devlink_resource_size_params_init(hash_double_size_params, 4036 double_size_min, 4037 kvd_size - single_size_min - 4038 linear_size_min, 4039 MLXSW_SP_KVD_GRANULARITY, 4040 DEVLINK_RESOURCE_UNIT_ENTRY); 4041 devlink_resource_size_params_init(hash_single_size_params, 4042 single_size_min, 4043 kvd_size - double_size_min - 4044 linear_size_min, 4045 MLXSW_SP_KVD_GRANULARITY, 4046 DEVLINK_RESOURCE_UNIT_ENTRY); 4047 } 4048 4049 static int mlxsw_sp1_resources_kvd_register(struct mlxsw_core *mlxsw_core) 4050 { 4051 struct devlink *devlink = priv_to_devlink(mlxsw_core); 4052 struct devlink_resource_size_params hash_single_size_params; 4053 struct devlink_resource_size_params hash_double_size_params; 4054 struct devlink_resource_size_params linear_size_params; 4055 struct devlink_resource_size_params kvd_size_params; 4056 u32 kvd_size, single_size, double_size, linear_size; 4057 const struct mlxsw_config_profile *profile; 4058 int err; 4059 4060 profile = &mlxsw_sp1_config_profile; 4061 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE)) 4062 return -EIO; 4063 4064 mlxsw_sp_resource_size_params_prepare(mlxsw_core, &kvd_size_params, 4065 &linear_size_params, 4066 &hash_double_size_params, 4067 &hash_single_size_params); 4068 4069 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE); 4070 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD, 4071 kvd_size, MLXSW_SP_RESOURCE_KVD, 4072 DEVLINK_RESOURCE_ID_PARENT_TOP, 4073 &kvd_size_params); 4074 if (err) 4075 return err; 4076 4077 linear_size = profile->kvd_linear_size; 4078 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_LINEAR, 4079 linear_size, 4080 MLXSW_SP_RESOURCE_KVD_LINEAR, 4081 MLXSW_SP_RESOURCE_KVD, 4082 &linear_size_params); 4083 if (err) 4084 return err; 4085 4086 err = mlxsw_sp1_kvdl_resources_register(mlxsw_core); 4087 if (err) 4088 return err; 4089 4090 double_size = kvd_size - linear_size; 4091 double_size *= profile->kvd_hash_double_parts; 4092 double_size /= profile->kvd_hash_double_parts + 4093 profile->kvd_hash_single_parts; 4094 double_size = rounddown(double_size, MLXSW_SP_KVD_GRANULARITY); 4095 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_DOUBLE, 4096 double_size, 4097 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE, 4098 MLXSW_SP_RESOURCE_KVD, 4099 &hash_double_size_params); 4100 if (err) 4101 return err; 4102 4103 single_size = kvd_size - double_size - linear_size; 4104 err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_SINGLE, 4105 single_size, 4106 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE, 4107 MLXSW_SP_RESOURCE_KVD, 4108 &hash_single_size_params); 4109 if (err) 4110 return err; 4111 4112 return 0; 4113 } 4114 4115 static int mlxsw_sp1_resources_register(struct mlxsw_core *mlxsw_core) 4116 { 4117 return mlxsw_sp1_resources_kvd_register(mlxsw_core); 4118 } 4119 4120 static int mlxsw_sp2_resources_register(struct mlxsw_core *mlxsw_core) 4121 { 4122 return 0; 4123 } 4124 4125 static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core, 4126 const struct mlxsw_config_profile *profile, 4127 u64 *p_single_size, u64 *p_double_size, 4128 u64 *p_linear_size) 4129 { 4130 struct devlink *devlink = priv_to_devlink(mlxsw_core); 4131 u32 double_size; 4132 int err; 4133 4134 if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SINGLE_MIN_SIZE) || 4135 !MLXSW_CORE_RES_VALID(mlxsw_core, KVD_DOUBLE_MIN_SIZE)) 4136 return -EIO; 4137 4138 /* The hash part is what left of the kvd without the 4139 * linear part. It is split to the single size and 4140 * double size by the parts ratio from the profile. 4141 * Both sizes must be a multiplications of the 4142 * granularity from the profile. In case the user 4143 * provided the sizes they are obtained via devlink. 4144 */ 4145 err = devlink_resource_size_get(devlink, 4146 MLXSW_SP_RESOURCE_KVD_LINEAR, 4147 p_linear_size); 4148 if (err) 4149 *p_linear_size = profile->kvd_linear_size; 4150 4151 err = devlink_resource_size_get(devlink, 4152 MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE, 4153 p_double_size); 4154 if (err) { 4155 double_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) - 4156 *p_linear_size; 4157 double_size *= profile->kvd_hash_double_parts; 4158 double_size /= profile->kvd_hash_double_parts + 4159 profile->kvd_hash_single_parts; 4160 *p_double_size = rounddown(double_size, 4161 MLXSW_SP_KVD_GRANULARITY); 4162 } 4163 4164 err = devlink_resource_size_get(devlink, 4165 MLXSW_SP_RESOURCE_KVD_HASH_SINGLE, 4166 p_single_size); 4167 if (err) 4168 *p_single_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) - 4169 *p_double_size - *p_linear_size; 4170 4171 /* Check results are legal. */ 4172 if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) || 4173 *p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) || 4174 MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size) 4175 return -EIO; 4176 4177 return 0; 4178 } 4179 4180 static struct mlxsw_driver mlxsw_sp1_driver = { 4181 .kind = mlxsw_sp1_driver_name, 4182 .priv_size = sizeof(struct mlxsw_sp), 4183 .init = mlxsw_sp1_init, 4184 .fini = mlxsw_sp_fini, 4185 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set, 4186 .port_split = mlxsw_sp_port_split, 4187 .port_unsplit = mlxsw_sp_port_unsplit, 4188 .sb_pool_get = mlxsw_sp_sb_pool_get, 4189 .sb_pool_set = mlxsw_sp_sb_pool_set, 4190 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get, 4191 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set, 4192 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get, 4193 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set, 4194 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot, 4195 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear, 4196 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get, 4197 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get, 4198 .txhdr_construct = mlxsw_sp_txhdr_construct, 4199 .resources_register = mlxsw_sp1_resources_register, 4200 .kvd_sizes_get = mlxsw_sp_kvd_sizes_get, 4201 .txhdr_len = MLXSW_TXHDR_LEN, 4202 .profile = &mlxsw_sp1_config_profile, 4203 .res_query_enabled = true, 4204 }; 4205 4206 static struct mlxsw_driver mlxsw_sp2_driver = { 4207 .kind = mlxsw_sp2_driver_name, 4208 .priv_size = sizeof(struct mlxsw_sp), 4209 .init = mlxsw_sp2_init, 4210 .fini = mlxsw_sp_fini, 4211 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set, 4212 .port_split = mlxsw_sp_port_split, 4213 .port_unsplit = mlxsw_sp_port_unsplit, 4214 .sb_pool_get = mlxsw_sp_sb_pool_get, 4215 .sb_pool_set = mlxsw_sp_sb_pool_set, 4216 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get, 4217 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set, 4218 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get, 4219 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set, 4220 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot, 4221 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear, 4222 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get, 4223 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get, 4224 .txhdr_construct = mlxsw_sp_txhdr_construct, 4225 .resources_register = mlxsw_sp2_resources_register, 4226 .txhdr_len = MLXSW_TXHDR_LEN, 4227 .profile = &mlxsw_sp2_config_profile, 4228 .res_query_enabled = true, 4229 }; 4230 4231 bool mlxsw_sp_port_dev_check(const struct net_device *dev) 4232 { 4233 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops; 4234 } 4235 4236 static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data) 4237 { 4238 struct mlxsw_sp_port **p_mlxsw_sp_port = data; 4239 int ret = 0; 4240 4241 if (mlxsw_sp_port_dev_check(lower_dev)) { 4242 *p_mlxsw_sp_port = netdev_priv(lower_dev); 4243 ret = 1; 4244 } 4245 4246 return ret; 4247 } 4248 4249 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev) 4250 { 4251 struct mlxsw_sp_port *mlxsw_sp_port; 4252 4253 if (mlxsw_sp_port_dev_check(dev)) 4254 return netdev_priv(dev); 4255 4256 mlxsw_sp_port = NULL; 4257 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port); 4258 4259 return mlxsw_sp_port; 4260 } 4261 4262 struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev) 4263 { 4264 struct mlxsw_sp_port *mlxsw_sp_port; 4265 4266 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev); 4267 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL; 4268 } 4269 4270 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev) 4271 { 4272 struct mlxsw_sp_port *mlxsw_sp_port; 4273 4274 if (mlxsw_sp_port_dev_check(dev)) 4275 return netdev_priv(dev); 4276 4277 mlxsw_sp_port = NULL; 4278 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk, 4279 &mlxsw_sp_port); 4280 4281 return mlxsw_sp_port; 4282 } 4283 4284 struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev) 4285 { 4286 struct mlxsw_sp_port *mlxsw_sp_port; 4287 4288 rcu_read_lock(); 4289 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev); 4290 if (mlxsw_sp_port) 4291 dev_hold(mlxsw_sp_port->dev); 4292 rcu_read_unlock(); 4293 return mlxsw_sp_port; 4294 } 4295 4296 void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port) 4297 { 4298 dev_put(mlxsw_sp_port->dev); 4299 } 4300 4301 static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id) 4302 { 4303 char sldr_pl[MLXSW_REG_SLDR_LEN]; 4304 4305 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id); 4306 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 4307 } 4308 4309 static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id) 4310 { 4311 char sldr_pl[MLXSW_REG_SLDR_LEN]; 4312 4313 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id); 4314 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 4315 } 4316 4317 static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port, 4318 u16 lag_id, u8 port_index) 4319 { 4320 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4321 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 4322 4323 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port, 4324 lag_id, port_index); 4325 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 4326 } 4327 4328 static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port, 4329 u16 lag_id) 4330 { 4331 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4332 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 4333 4334 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port, 4335 lag_id); 4336 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 4337 } 4338 4339 static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port, 4340 u16 lag_id) 4341 { 4342 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4343 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 4344 4345 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port, 4346 lag_id); 4347 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 4348 } 4349 4350 static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port, 4351 u16 lag_id) 4352 { 4353 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4354 char slcor_pl[MLXSW_REG_SLCOR_LEN]; 4355 4356 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port, 4357 lag_id); 4358 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl); 4359 } 4360 4361 static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp, 4362 struct net_device *lag_dev, 4363 u16 *p_lag_id) 4364 { 4365 struct mlxsw_sp_upper *lag; 4366 int free_lag_id = -1; 4367 u64 max_lag; 4368 int i; 4369 4370 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG); 4371 for (i = 0; i < max_lag; i++) { 4372 lag = mlxsw_sp_lag_get(mlxsw_sp, i); 4373 if (lag->ref_count) { 4374 if (lag->dev == lag_dev) { 4375 *p_lag_id = i; 4376 return 0; 4377 } 4378 } else if (free_lag_id < 0) { 4379 free_lag_id = i; 4380 } 4381 } 4382 if (free_lag_id < 0) 4383 return -EBUSY; 4384 *p_lag_id = free_lag_id; 4385 return 0; 4386 } 4387 4388 static bool 4389 mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp, 4390 struct net_device *lag_dev, 4391 struct netdev_lag_upper_info *lag_upper_info, 4392 struct netlink_ext_ack *extack) 4393 { 4394 u16 lag_id; 4395 4396 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0) { 4397 NL_SET_ERR_MSG_MOD(extack, "Exceeded number of supported LAG devices"); 4398 return false; 4399 } 4400 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 4401 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type"); 4402 return false; 4403 } 4404 return true; 4405 } 4406 4407 static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp, 4408 u16 lag_id, u8 *p_port_index) 4409 { 4410 u64 max_lag_members; 4411 int i; 4412 4413 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core, 4414 MAX_LAG_MEMBERS); 4415 for (i = 0; i < max_lag_members; i++) { 4416 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) { 4417 *p_port_index = i; 4418 return 0; 4419 } 4420 } 4421 return -EBUSY; 4422 } 4423 4424 static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port, 4425 struct net_device *lag_dev) 4426 { 4427 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4428 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan; 4429 struct mlxsw_sp_upper *lag; 4430 u16 lag_id; 4431 u8 port_index; 4432 int err; 4433 4434 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id); 4435 if (err) 4436 return err; 4437 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id); 4438 if (!lag->ref_count) { 4439 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id); 4440 if (err) 4441 return err; 4442 lag->dev = lag_dev; 4443 } 4444 4445 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index); 4446 if (err) 4447 return err; 4448 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index); 4449 if (err) 4450 goto err_col_port_add; 4451 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id); 4452 if (err) 4453 goto err_col_port_enable; 4454 4455 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index, 4456 mlxsw_sp_port->local_port); 4457 mlxsw_sp_port->lag_id = lag_id; 4458 mlxsw_sp_port->lagged = 1; 4459 lag->ref_count++; 4460 4461 /* Port is no longer usable as a router interface */ 4462 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, 1); 4463 if (mlxsw_sp_port_vlan->fid) 4464 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan); 4465 4466 return 0; 4467 4468 err_col_port_enable: 4469 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id); 4470 err_col_port_add: 4471 if (!lag->ref_count) 4472 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id); 4473 return err; 4474 } 4475 4476 static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port, 4477 struct net_device *lag_dev) 4478 { 4479 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4480 u16 lag_id = mlxsw_sp_port->lag_id; 4481 struct mlxsw_sp_upper *lag; 4482 4483 if (!mlxsw_sp_port->lagged) 4484 return; 4485 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id); 4486 WARN_ON(lag->ref_count == 0); 4487 4488 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id); 4489 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id); 4490 4491 /* Any VLANs configured on the port are no longer valid */ 4492 mlxsw_sp_port_vlan_flush(mlxsw_sp_port); 4493 4494 if (lag->ref_count == 1) 4495 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id); 4496 4497 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id, 4498 mlxsw_sp_port->local_port); 4499 mlxsw_sp_port->lagged = 0; 4500 lag->ref_count--; 4501 4502 mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1); 4503 /* Make sure untagged frames are allowed to ingress */ 4504 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1); 4505 } 4506 4507 static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port, 4508 u16 lag_id) 4509 { 4510 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4511 char sldr_pl[MLXSW_REG_SLDR_LEN]; 4512 4513 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id, 4514 mlxsw_sp_port->local_port); 4515 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 4516 } 4517 4518 static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port, 4519 u16 lag_id) 4520 { 4521 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4522 char sldr_pl[MLXSW_REG_SLDR_LEN]; 4523 4524 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id, 4525 mlxsw_sp_port->local_port); 4526 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl); 4527 } 4528 4529 static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port, 4530 bool lag_tx_enabled) 4531 { 4532 if (lag_tx_enabled) 4533 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, 4534 mlxsw_sp_port->lag_id); 4535 else 4536 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port, 4537 mlxsw_sp_port->lag_id); 4538 } 4539 4540 static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port, 4541 struct netdev_lag_lower_state_info *info) 4542 { 4543 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled); 4544 } 4545 4546 static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, 4547 bool enable) 4548 { 4549 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4550 enum mlxsw_reg_spms_state spms_state; 4551 char *spms_pl; 4552 u16 vid; 4553 int err; 4554 4555 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING : 4556 MLXSW_REG_SPMS_STATE_DISCARDING; 4557 4558 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL); 4559 if (!spms_pl) 4560 return -ENOMEM; 4561 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port); 4562 4563 for (vid = 0; vid < VLAN_N_VID; vid++) 4564 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state); 4565 4566 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl); 4567 kfree(spms_pl); 4568 return err; 4569 } 4570 4571 static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port) 4572 { 4573 u16 vid = 1; 4574 int err; 4575 4576 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true); 4577 if (err) 4578 return err; 4579 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true); 4580 if (err) 4581 goto err_port_stp_set; 4582 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1, 4583 true, false); 4584 if (err) 4585 goto err_port_vlan_set; 4586 4587 for (; vid <= VLAN_N_VID - 1; vid++) { 4588 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, 4589 vid, false); 4590 if (err) 4591 goto err_vid_learning_set; 4592 } 4593 4594 return 0; 4595 4596 err_vid_learning_set: 4597 for (vid--; vid >= 1; vid--) 4598 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true); 4599 err_port_vlan_set: 4600 mlxsw_sp_port_stp_set(mlxsw_sp_port, false); 4601 err_port_stp_set: 4602 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false); 4603 return err; 4604 } 4605 4606 static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port) 4607 { 4608 u16 vid; 4609 4610 for (vid = VLAN_N_VID - 1; vid >= 1; vid--) 4611 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, 4612 vid, true); 4613 4614 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1, 4615 false, false); 4616 mlxsw_sp_port_stp_set(mlxsw_sp_port, false); 4617 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false); 4618 } 4619 4620 static bool mlxsw_sp_bridge_has_multiple_vxlans(struct net_device *br_dev) 4621 { 4622 unsigned int num_vxlans = 0; 4623 struct net_device *dev; 4624 struct list_head *iter; 4625 4626 netdev_for_each_lower_dev(br_dev, dev, iter) { 4627 if (netif_is_vxlan(dev)) 4628 num_vxlans++; 4629 } 4630 4631 return num_vxlans > 1; 4632 } 4633 4634 static bool mlxsw_sp_bridge_vxlan_is_valid(struct net_device *br_dev, 4635 struct netlink_ext_ack *extack) 4636 { 4637 if (br_multicast_enabled(br_dev)) { 4638 NL_SET_ERR_MSG_MOD(extack, "Multicast can not be enabled on a bridge with a VxLAN device"); 4639 return false; 4640 } 4641 4642 if (br_vlan_enabled(br_dev)) { 4643 NL_SET_ERR_MSG_MOD(extack, "VLAN filtering can not be enabled on a bridge with a VxLAN device"); 4644 return false; 4645 } 4646 4647 if (mlxsw_sp_bridge_has_multiple_vxlans(br_dev)) { 4648 NL_SET_ERR_MSG_MOD(extack, "Multiple VxLAN devices are not supported in a VLAN-unaware bridge"); 4649 return false; 4650 } 4651 4652 return true; 4653 } 4654 4655 static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev, 4656 struct net_device *dev, 4657 unsigned long event, void *ptr) 4658 { 4659 struct netdev_notifier_changeupper_info *info; 4660 struct mlxsw_sp_port *mlxsw_sp_port; 4661 struct netlink_ext_ack *extack; 4662 struct net_device *upper_dev; 4663 struct mlxsw_sp *mlxsw_sp; 4664 int err = 0; 4665 4666 mlxsw_sp_port = netdev_priv(dev); 4667 mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4668 info = ptr; 4669 extack = netdev_notifier_info_to_extack(&info->info); 4670 4671 switch (event) { 4672 case NETDEV_PRECHANGEUPPER: 4673 upper_dev = info->upper_dev; 4674 if (!is_vlan_dev(upper_dev) && 4675 !netif_is_lag_master(upper_dev) && 4676 !netif_is_bridge_master(upper_dev) && 4677 !netif_is_ovs_master(upper_dev) && 4678 !netif_is_macvlan(upper_dev)) { 4679 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 4680 return -EINVAL; 4681 } 4682 if (!info->linking) 4683 break; 4684 if (netif_is_bridge_master(upper_dev) && 4685 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) && 4686 mlxsw_sp_bridge_has_vxlan(upper_dev) && 4687 !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack)) 4688 return -EOPNOTSUPP; 4689 if (netdev_has_any_upper_dev(upper_dev) && 4690 (!netif_is_bridge_master(upper_dev) || 4691 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, 4692 upper_dev))) { 4693 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported"); 4694 return -EINVAL; 4695 } 4696 if (netif_is_lag_master(upper_dev) && 4697 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev, 4698 info->upper_info, extack)) 4699 return -EINVAL; 4700 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) { 4701 NL_SET_ERR_MSG_MOD(extack, "Master device is a LAG master and this device has a VLAN"); 4702 return -EINVAL; 4703 } 4704 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) && 4705 !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) { 4706 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on a LAG port"); 4707 return -EINVAL; 4708 } 4709 if (netif_is_macvlan(upper_dev) && 4710 !mlxsw_sp_rif_find_by_dev(mlxsw_sp, lower_dev)) { 4711 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces"); 4712 return -EOPNOTSUPP; 4713 } 4714 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) { 4715 NL_SET_ERR_MSG_MOD(extack, "Master device is an OVS master and this device has a VLAN"); 4716 return -EINVAL; 4717 } 4718 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) { 4719 NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on an OVS port"); 4720 return -EINVAL; 4721 } 4722 if (is_vlan_dev(upper_dev) && 4723 vlan_dev_vlan_id(upper_dev) == 1) { 4724 NL_SET_ERR_MSG_MOD(extack, "Creating a VLAN device with VID 1 is unsupported: VLAN 1 carries untagged traffic"); 4725 return -EINVAL; 4726 } 4727 break; 4728 case NETDEV_CHANGEUPPER: 4729 upper_dev = info->upper_dev; 4730 if (netif_is_bridge_master(upper_dev)) { 4731 if (info->linking) 4732 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port, 4733 lower_dev, 4734 upper_dev, 4735 extack); 4736 else 4737 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, 4738 lower_dev, 4739 upper_dev); 4740 } else if (netif_is_lag_master(upper_dev)) { 4741 if (info->linking) 4742 err = mlxsw_sp_port_lag_join(mlxsw_sp_port, 4743 upper_dev); 4744 else 4745 mlxsw_sp_port_lag_leave(mlxsw_sp_port, 4746 upper_dev); 4747 } else if (netif_is_ovs_master(upper_dev)) { 4748 if (info->linking) 4749 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port); 4750 else 4751 mlxsw_sp_port_ovs_leave(mlxsw_sp_port); 4752 } else if (netif_is_macvlan(upper_dev)) { 4753 if (!info->linking) 4754 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev); 4755 } 4756 break; 4757 } 4758 4759 return err; 4760 } 4761 4762 static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev, 4763 unsigned long event, void *ptr) 4764 { 4765 struct netdev_notifier_changelowerstate_info *info; 4766 struct mlxsw_sp_port *mlxsw_sp_port; 4767 int err; 4768 4769 mlxsw_sp_port = netdev_priv(dev); 4770 info = ptr; 4771 4772 switch (event) { 4773 case NETDEV_CHANGELOWERSTATE: 4774 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) { 4775 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port, 4776 info->lower_state_info); 4777 if (err) 4778 netdev_err(dev, "Failed to reflect link aggregation lower state change\n"); 4779 } 4780 break; 4781 } 4782 4783 return 0; 4784 } 4785 4786 static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev, 4787 struct net_device *port_dev, 4788 unsigned long event, void *ptr) 4789 { 4790 switch (event) { 4791 case NETDEV_PRECHANGEUPPER: 4792 case NETDEV_CHANGEUPPER: 4793 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev, 4794 event, ptr); 4795 case NETDEV_CHANGELOWERSTATE: 4796 return mlxsw_sp_netdevice_port_lower_event(port_dev, event, 4797 ptr); 4798 } 4799 4800 return 0; 4801 } 4802 4803 static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev, 4804 unsigned long event, void *ptr) 4805 { 4806 struct net_device *dev; 4807 struct list_head *iter; 4808 int ret; 4809 4810 netdev_for_each_lower_dev(lag_dev, dev, iter) { 4811 if (mlxsw_sp_port_dev_check(dev)) { 4812 ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event, 4813 ptr); 4814 if (ret) 4815 return ret; 4816 } 4817 } 4818 4819 return 0; 4820 } 4821 4822 static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev, 4823 struct net_device *dev, 4824 unsigned long event, void *ptr, 4825 u16 vid) 4826 { 4827 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev); 4828 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp; 4829 struct netdev_notifier_changeupper_info *info = ptr; 4830 struct netlink_ext_ack *extack; 4831 struct net_device *upper_dev; 4832 int err = 0; 4833 4834 extack = netdev_notifier_info_to_extack(&info->info); 4835 4836 switch (event) { 4837 case NETDEV_PRECHANGEUPPER: 4838 upper_dev = info->upper_dev; 4839 if (!netif_is_bridge_master(upper_dev) && 4840 !netif_is_macvlan(upper_dev)) { 4841 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 4842 return -EINVAL; 4843 } 4844 if (!info->linking) 4845 break; 4846 if (netif_is_bridge_master(upper_dev) && 4847 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) && 4848 mlxsw_sp_bridge_has_vxlan(upper_dev) && 4849 !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack)) 4850 return -EOPNOTSUPP; 4851 if (netdev_has_any_upper_dev(upper_dev) && 4852 (!netif_is_bridge_master(upper_dev) || 4853 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, 4854 upper_dev))) { 4855 NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported"); 4856 return -EINVAL; 4857 } 4858 if (netif_is_macvlan(upper_dev) && 4859 !mlxsw_sp_rif_find_by_dev(mlxsw_sp, vlan_dev)) { 4860 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces"); 4861 return -EOPNOTSUPP; 4862 } 4863 break; 4864 case NETDEV_CHANGEUPPER: 4865 upper_dev = info->upper_dev; 4866 if (netif_is_bridge_master(upper_dev)) { 4867 if (info->linking) 4868 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port, 4869 vlan_dev, 4870 upper_dev, 4871 extack); 4872 else 4873 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, 4874 vlan_dev, 4875 upper_dev); 4876 } else if (netif_is_macvlan(upper_dev)) { 4877 if (!info->linking) 4878 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev); 4879 } else { 4880 err = -EINVAL; 4881 WARN_ON(1); 4882 } 4883 break; 4884 } 4885 4886 return err; 4887 } 4888 4889 static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev, 4890 struct net_device *lag_dev, 4891 unsigned long event, 4892 void *ptr, u16 vid) 4893 { 4894 struct net_device *dev; 4895 struct list_head *iter; 4896 int ret; 4897 4898 netdev_for_each_lower_dev(lag_dev, dev, iter) { 4899 if (mlxsw_sp_port_dev_check(dev)) { 4900 ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev, 4901 event, ptr, 4902 vid); 4903 if (ret) 4904 return ret; 4905 } 4906 } 4907 4908 return 0; 4909 } 4910 4911 static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev, 4912 unsigned long event, void *ptr) 4913 { 4914 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev); 4915 u16 vid = vlan_dev_vlan_id(vlan_dev); 4916 4917 if (mlxsw_sp_port_dev_check(real_dev)) 4918 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev, 4919 event, ptr, vid); 4920 else if (netif_is_lag_master(real_dev)) 4921 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev, 4922 real_dev, event, 4923 ptr, vid); 4924 4925 return 0; 4926 } 4927 4928 static int mlxsw_sp_netdevice_bridge_event(struct net_device *br_dev, 4929 unsigned long event, void *ptr) 4930 { 4931 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(br_dev); 4932 struct netdev_notifier_changeupper_info *info = ptr; 4933 struct netlink_ext_ack *extack; 4934 struct net_device *upper_dev; 4935 4936 if (!mlxsw_sp) 4937 return 0; 4938 4939 extack = netdev_notifier_info_to_extack(&info->info); 4940 4941 switch (event) { 4942 case NETDEV_PRECHANGEUPPER: 4943 upper_dev = info->upper_dev; 4944 if (!is_vlan_dev(upper_dev) && !netif_is_macvlan(upper_dev)) { 4945 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 4946 return -EOPNOTSUPP; 4947 } 4948 if (!info->linking) 4949 break; 4950 if (netif_is_macvlan(upper_dev) && 4951 !mlxsw_sp_rif_find_by_dev(mlxsw_sp, br_dev)) { 4952 NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces"); 4953 return -EOPNOTSUPP; 4954 } 4955 break; 4956 case NETDEV_CHANGEUPPER: 4957 upper_dev = info->upper_dev; 4958 if (info->linking) 4959 break; 4960 if (is_vlan_dev(upper_dev)) 4961 mlxsw_sp_rif_destroy_by_dev(mlxsw_sp, upper_dev); 4962 if (netif_is_macvlan(upper_dev)) 4963 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev); 4964 break; 4965 } 4966 4967 return 0; 4968 } 4969 4970 static int mlxsw_sp_netdevice_macvlan_event(struct net_device *macvlan_dev, 4971 unsigned long event, void *ptr) 4972 { 4973 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(macvlan_dev); 4974 struct netdev_notifier_changeupper_info *info = ptr; 4975 struct netlink_ext_ack *extack; 4976 4977 if (!mlxsw_sp || event != NETDEV_PRECHANGEUPPER) 4978 return 0; 4979 4980 extack = netdev_notifier_info_to_extack(&info->info); 4981 4982 /* VRF enslavement is handled in mlxsw_sp_netdevice_vrf_event() */ 4983 NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type"); 4984 4985 return -EOPNOTSUPP; 4986 } 4987 4988 static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr) 4989 { 4990 struct netdev_notifier_changeupper_info *info = ptr; 4991 4992 if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER) 4993 return false; 4994 return netif_is_l3_master(info->upper_dev); 4995 } 4996 4997 static int mlxsw_sp_netdevice_vxlan_event(struct mlxsw_sp *mlxsw_sp, 4998 struct net_device *dev, 4999 unsigned long event, void *ptr) 5000 { 5001 struct netdev_notifier_changeupper_info *cu_info; 5002 struct netdev_notifier_info *info = ptr; 5003 struct netlink_ext_ack *extack; 5004 struct net_device *upper_dev; 5005 5006 extack = netdev_notifier_info_to_extack(info); 5007 5008 switch (event) { 5009 case NETDEV_CHANGEUPPER: 5010 cu_info = container_of(info, 5011 struct netdev_notifier_changeupper_info, 5012 info); 5013 upper_dev = cu_info->upper_dev; 5014 if (!netif_is_bridge_master(upper_dev)) 5015 return 0; 5016 if (!mlxsw_sp_lower_get(upper_dev)) 5017 return 0; 5018 if (!mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack)) 5019 return -EOPNOTSUPP; 5020 if (cu_info->linking) { 5021 if (!netif_running(dev)) 5022 return 0; 5023 return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev, 5024 dev, extack); 5025 } else { 5026 mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, upper_dev, dev); 5027 } 5028 break; 5029 case NETDEV_PRE_UP: 5030 upper_dev = netdev_master_upper_dev_get(dev); 5031 if (!upper_dev) 5032 return 0; 5033 if (!netif_is_bridge_master(upper_dev)) 5034 return 0; 5035 if (!mlxsw_sp_lower_get(upper_dev)) 5036 return 0; 5037 return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev, dev, 5038 extack); 5039 case NETDEV_DOWN: 5040 upper_dev = netdev_master_upper_dev_get(dev); 5041 if (!upper_dev) 5042 return 0; 5043 if (!netif_is_bridge_master(upper_dev)) 5044 return 0; 5045 if (!mlxsw_sp_lower_get(upper_dev)) 5046 return 0; 5047 mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, upper_dev, dev); 5048 break; 5049 } 5050 5051 return 0; 5052 } 5053 5054 static int mlxsw_sp_netdevice_event(struct notifier_block *nb, 5055 unsigned long event, void *ptr) 5056 { 5057 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 5058 struct mlxsw_sp_span_entry *span_entry; 5059 struct mlxsw_sp *mlxsw_sp; 5060 int err = 0; 5061 5062 mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb); 5063 if (event == NETDEV_UNREGISTER) { 5064 span_entry = mlxsw_sp_span_entry_find_by_port(mlxsw_sp, dev); 5065 if (span_entry) 5066 mlxsw_sp_span_entry_invalidate(mlxsw_sp, span_entry); 5067 } 5068 mlxsw_sp_span_respin(mlxsw_sp); 5069 5070 if (netif_is_vxlan(dev)) 5071 err = mlxsw_sp_netdevice_vxlan_event(mlxsw_sp, dev, event, ptr); 5072 if (mlxsw_sp_netdev_is_ipip_ol(mlxsw_sp, dev)) 5073 err = mlxsw_sp_netdevice_ipip_ol_event(mlxsw_sp, dev, 5074 event, ptr); 5075 else if (mlxsw_sp_netdev_is_ipip_ul(mlxsw_sp, dev)) 5076 err = mlxsw_sp_netdevice_ipip_ul_event(mlxsw_sp, dev, 5077 event, ptr); 5078 else if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU) 5079 err = mlxsw_sp_netdevice_router_port_event(dev); 5080 else if (mlxsw_sp_is_vrf_event(event, ptr)) 5081 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr); 5082 else if (mlxsw_sp_port_dev_check(dev)) 5083 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr); 5084 else if (netif_is_lag_master(dev)) 5085 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr); 5086 else if (is_vlan_dev(dev)) 5087 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr); 5088 else if (netif_is_bridge_master(dev)) 5089 err = mlxsw_sp_netdevice_bridge_event(dev, event, ptr); 5090 else if (netif_is_macvlan(dev)) 5091 err = mlxsw_sp_netdevice_macvlan_event(dev, event, ptr); 5092 5093 return notifier_from_errno(err); 5094 } 5095 5096 static struct notifier_block mlxsw_sp_inetaddr_valid_nb __read_mostly = { 5097 .notifier_call = mlxsw_sp_inetaddr_valid_event, 5098 }; 5099 5100 static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = { 5101 .notifier_call = mlxsw_sp_inetaddr_event, 5102 }; 5103 5104 static struct notifier_block mlxsw_sp_inet6addr_valid_nb __read_mostly = { 5105 .notifier_call = mlxsw_sp_inet6addr_valid_event, 5106 }; 5107 5108 static struct notifier_block mlxsw_sp_inet6addr_nb __read_mostly = { 5109 .notifier_call = mlxsw_sp_inet6addr_event, 5110 }; 5111 5112 static const struct pci_device_id mlxsw_sp1_pci_id_table[] = { 5113 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0}, 5114 {0, }, 5115 }; 5116 5117 static struct pci_driver mlxsw_sp1_pci_driver = { 5118 .name = mlxsw_sp1_driver_name, 5119 .id_table = mlxsw_sp1_pci_id_table, 5120 }; 5121 5122 static const struct pci_device_id mlxsw_sp2_pci_id_table[] = { 5123 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM2), 0}, 5124 {0, }, 5125 }; 5126 5127 static struct pci_driver mlxsw_sp2_pci_driver = { 5128 .name = mlxsw_sp2_driver_name, 5129 .id_table = mlxsw_sp2_pci_id_table, 5130 }; 5131 5132 static int __init mlxsw_sp_module_init(void) 5133 { 5134 int err; 5135 5136 register_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb); 5137 register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb); 5138 register_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb); 5139 register_inet6addr_notifier(&mlxsw_sp_inet6addr_nb); 5140 5141 err = mlxsw_core_driver_register(&mlxsw_sp1_driver); 5142 if (err) 5143 goto err_sp1_core_driver_register; 5144 5145 err = mlxsw_core_driver_register(&mlxsw_sp2_driver); 5146 if (err) 5147 goto err_sp2_core_driver_register; 5148 5149 err = mlxsw_pci_driver_register(&mlxsw_sp1_pci_driver); 5150 if (err) 5151 goto err_sp1_pci_driver_register; 5152 5153 err = mlxsw_pci_driver_register(&mlxsw_sp2_pci_driver); 5154 if (err) 5155 goto err_sp2_pci_driver_register; 5156 5157 return 0; 5158 5159 err_sp2_pci_driver_register: 5160 mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver); 5161 err_sp1_pci_driver_register: 5162 mlxsw_core_driver_unregister(&mlxsw_sp2_driver); 5163 err_sp2_core_driver_register: 5164 mlxsw_core_driver_unregister(&mlxsw_sp1_driver); 5165 err_sp1_core_driver_register: 5166 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb); 5167 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb); 5168 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb); 5169 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb); 5170 return err; 5171 } 5172 5173 static void __exit mlxsw_sp_module_exit(void) 5174 { 5175 mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver); 5176 mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver); 5177 mlxsw_core_driver_unregister(&mlxsw_sp2_driver); 5178 mlxsw_core_driver_unregister(&mlxsw_sp1_driver); 5179 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb); 5180 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb); 5181 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb); 5182 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb); 5183 } 5184 5185 module_init(mlxsw_sp_module_init); 5186 module_exit(mlxsw_sp_module_exit); 5187 5188 MODULE_LICENSE("Dual BSD/GPL"); 5189 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>"); 5190 MODULE_DESCRIPTION("Mellanox Spectrum driver"); 5191 MODULE_DEVICE_TABLE(pci, mlxsw_sp1_pci_id_table); 5192 MODULE_DEVICE_TABLE(pci, mlxsw_sp2_pci_id_table); 5193 MODULE_FIRMWARE(MLXSW_SP1_FW_FILENAME); 5194