1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ 2 /* Copyright (c) 2016-2018 Mellanox Technologies. All rights reserved */ 3 4 #ifndef _MLXSW_RESOURCES_H 5 #define _MLXSW_RESOURCES_H 6 7 #include <linux/kernel.h> 8 #include <linux/types.h> 9 10 enum mlxsw_res_id { 11 MLXSW_RES_ID_KVD_SIZE, 12 MLXSW_RES_ID_KVD_SINGLE_MIN_SIZE, 13 MLXSW_RES_ID_KVD_DOUBLE_MIN_SIZE, 14 MLXSW_RES_ID_MAX_KVD_LINEAR_RANGE, 15 MLXSW_RES_ID_MAX_KVD_ACTION_SETS, 16 MLXSW_RES_ID_MAX_TRAP_GROUPS, 17 MLXSW_RES_ID_CQE_V0, 18 MLXSW_RES_ID_CQE_V1, 19 MLXSW_RES_ID_CQE_V2, 20 MLXSW_RES_ID_COUNTER_POOL_SIZE, 21 MLXSW_RES_ID_COUNTER_BANK_SIZE, 22 MLXSW_RES_ID_MAX_SPAN, 23 MLXSW_RES_ID_COUNTER_SIZE_PACKETS_BYTES, 24 MLXSW_RES_ID_COUNTER_SIZE_ROUTER_BASIC, 25 MLXSW_RES_ID_MAX_SYSTEM_PORT, 26 MLXSW_RES_ID_MAX_LAG, 27 MLXSW_RES_ID_MAX_LAG_MEMBERS, 28 MLXSW_RES_ID_GUARANTEED_SHARED_BUFFER, 29 MLXSW_RES_ID_CELL_SIZE, 30 MLXSW_RES_ID_MAX_HEADROOM_SIZE, 31 MLXSW_RES_ID_ACL_MAX_TCAM_REGIONS, 32 MLXSW_RES_ID_ACL_MAX_TCAM_RULES, 33 MLXSW_RES_ID_ACL_MAX_REGIONS, 34 MLXSW_RES_ID_ACL_MAX_GROUPS, 35 MLXSW_RES_ID_ACL_MAX_GROUP_SIZE, 36 MLXSW_RES_ID_ACL_MAX_DEFAULT_ACTIONS, 37 MLXSW_RES_ID_ACL_FLEX_KEYS, 38 MLXSW_RES_ID_ACL_MAX_ACTION_PER_RULE, 39 MLXSW_RES_ID_ACL_ACTIONS_PER_SET, 40 MLXSW_RES_ID_ACL_MAX_ERPT_BANKS, 41 MLXSW_RES_ID_ACL_MAX_ERPT_BANK_SIZE, 42 MLXSW_RES_ID_ACL_MAX_LARGE_KEY_ID, 43 MLXSW_RES_ID_ACL_ERPT_ENTRIES_2KB, 44 MLXSW_RES_ID_ACL_ERPT_ENTRIES_4KB, 45 MLXSW_RES_ID_ACL_ERPT_ENTRIES_8KB, 46 MLXSW_RES_ID_ACL_ERPT_ENTRIES_12KB, 47 MLXSW_RES_ID_ACL_MAX_BF_LOG, 48 MLXSW_RES_ID_MAX_GLOBAL_POLICERS, 49 MLXSW_RES_ID_MAX_CPU_POLICERS, 50 MLXSW_RES_ID_MAX_VRS, 51 MLXSW_RES_ID_MAX_RIFS, 52 MLXSW_RES_ID_MC_ERIF_LIST_ENTRIES, 53 MLXSW_RES_ID_MAX_RIF_MAC_PROFILES, 54 MLXSW_RES_ID_MAX_LPM_TREES, 55 MLXSW_RES_ID_MAX_NVE_MC_ENTRIES_IPV4, 56 MLXSW_RES_ID_MAX_NVE_MC_ENTRIES_IPV6, 57 58 /* Internal resources. 59 * Determined by the SW, not queried from the HW. 60 */ 61 MLXSW_RES_ID_KVD_SINGLE_SIZE, 62 MLXSW_RES_ID_KVD_DOUBLE_SIZE, 63 MLXSW_RES_ID_KVD_LINEAR_SIZE, 64 65 __MLXSW_RES_ID_MAX, 66 }; 67 68 static u16 mlxsw_res_ids[] = { 69 [MLXSW_RES_ID_KVD_SIZE] = 0x1001, 70 [MLXSW_RES_ID_KVD_SINGLE_MIN_SIZE] = 0x1002, 71 [MLXSW_RES_ID_KVD_DOUBLE_MIN_SIZE] = 0x1003, 72 [MLXSW_RES_ID_MAX_KVD_LINEAR_RANGE] = 0x1005, 73 [MLXSW_RES_ID_MAX_KVD_ACTION_SETS] = 0x1007, 74 [MLXSW_RES_ID_MAX_TRAP_GROUPS] = 0x2201, 75 [MLXSW_RES_ID_CQE_V0] = 0x2210, 76 [MLXSW_RES_ID_CQE_V1] = 0x2211, 77 [MLXSW_RES_ID_CQE_V2] = 0x2212, 78 [MLXSW_RES_ID_COUNTER_POOL_SIZE] = 0x2410, 79 [MLXSW_RES_ID_COUNTER_BANK_SIZE] = 0x2411, 80 [MLXSW_RES_ID_MAX_SPAN] = 0x2420, 81 [MLXSW_RES_ID_COUNTER_SIZE_PACKETS_BYTES] = 0x2443, 82 [MLXSW_RES_ID_COUNTER_SIZE_ROUTER_BASIC] = 0x2449, 83 [MLXSW_RES_ID_MAX_SYSTEM_PORT] = 0x2502, 84 [MLXSW_RES_ID_MAX_LAG] = 0x2520, 85 [MLXSW_RES_ID_MAX_LAG_MEMBERS] = 0x2521, 86 [MLXSW_RES_ID_GUARANTEED_SHARED_BUFFER] = 0x2805, /* Bytes */ 87 [MLXSW_RES_ID_CELL_SIZE] = 0x2803, /* Bytes */ 88 [MLXSW_RES_ID_MAX_HEADROOM_SIZE] = 0x2811, /* Bytes */ 89 [MLXSW_RES_ID_ACL_MAX_TCAM_REGIONS] = 0x2901, 90 [MLXSW_RES_ID_ACL_MAX_TCAM_RULES] = 0x2902, 91 [MLXSW_RES_ID_ACL_MAX_REGIONS] = 0x2903, 92 [MLXSW_RES_ID_ACL_MAX_GROUPS] = 0x2904, 93 [MLXSW_RES_ID_ACL_MAX_GROUP_SIZE] = 0x2905, 94 [MLXSW_RES_ID_ACL_MAX_DEFAULT_ACTIONS] = 0x2908, 95 [MLXSW_RES_ID_ACL_FLEX_KEYS] = 0x2910, 96 [MLXSW_RES_ID_ACL_MAX_ACTION_PER_RULE] = 0x2911, 97 [MLXSW_RES_ID_ACL_ACTIONS_PER_SET] = 0x2912, 98 [MLXSW_RES_ID_ACL_MAX_ERPT_BANKS] = 0x2940, 99 [MLXSW_RES_ID_ACL_MAX_ERPT_BANK_SIZE] = 0x2941, 100 [MLXSW_RES_ID_ACL_MAX_LARGE_KEY_ID] = 0x2942, 101 [MLXSW_RES_ID_ACL_ERPT_ENTRIES_2KB] = 0x2950, 102 [MLXSW_RES_ID_ACL_ERPT_ENTRIES_4KB] = 0x2951, 103 [MLXSW_RES_ID_ACL_ERPT_ENTRIES_8KB] = 0x2952, 104 [MLXSW_RES_ID_ACL_ERPT_ENTRIES_12KB] = 0x2953, 105 [MLXSW_RES_ID_ACL_MAX_BF_LOG] = 0x2960, 106 [MLXSW_RES_ID_MAX_GLOBAL_POLICERS] = 0x2A10, 107 [MLXSW_RES_ID_MAX_CPU_POLICERS] = 0x2A13, 108 [MLXSW_RES_ID_MAX_VRS] = 0x2C01, 109 [MLXSW_RES_ID_MAX_RIFS] = 0x2C02, 110 [MLXSW_RES_ID_MC_ERIF_LIST_ENTRIES] = 0x2C10, 111 [MLXSW_RES_ID_MAX_RIF_MAC_PROFILES] = 0x2C14, 112 [MLXSW_RES_ID_MAX_LPM_TREES] = 0x2C30, 113 [MLXSW_RES_ID_MAX_NVE_MC_ENTRIES_IPV4] = 0x2E02, 114 [MLXSW_RES_ID_MAX_NVE_MC_ENTRIES_IPV6] = 0x2E03, 115 }; 116 117 struct mlxsw_res { 118 bool valid[__MLXSW_RES_ID_MAX]; 119 u64 values[__MLXSW_RES_ID_MAX]; 120 }; 121 122 static inline bool mlxsw_res_valid(struct mlxsw_res *res, 123 enum mlxsw_res_id res_id) 124 { 125 return res->valid[res_id]; 126 } 127 128 #define MLXSW_RES_VALID(res, short_res_id) \ 129 mlxsw_res_valid(res, MLXSW_RES_ID_##short_res_id) 130 131 static inline u64 mlxsw_res_get(struct mlxsw_res *res, 132 enum mlxsw_res_id res_id) 133 { 134 if (WARN_ON(!res->valid[res_id])) 135 return 0; 136 return res->values[res_id]; 137 } 138 139 #define MLXSW_RES_GET(res, short_res_id) \ 140 mlxsw_res_get(res, MLXSW_RES_ID_##short_res_id) 141 142 static inline void mlxsw_res_set(struct mlxsw_res *res, 143 enum mlxsw_res_id res_id, u64 value) 144 { 145 res->valid[res_id] = true; 146 res->values[res_id] = value; 147 } 148 149 #define MLXSW_RES_SET(res, short_res_id, value) \ 150 mlxsw_res_set(res, MLXSW_RES_ID_##short_res_id, value) 151 152 static inline void mlxsw_res_parse(struct mlxsw_res *res, u16 id, u64 value) 153 { 154 int i; 155 156 for (i = 0; i < ARRAY_SIZE(mlxsw_res_ids); i++) { 157 if (mlxsw_res_ids[i] == id) { 158 mlxsw_res_set(res, i, value); 159 return; 160 } 161 } 162 } 163 164 #endif 165