1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ 2 /* Copyright (c) 2016-2018 Mellanox Technologies. All rights reserved */ 3 4 #ifndef _MLXSW_RESOURCES_H 5 #define _MLXSW_RESOURCES_H 6 7 #include <linux/kernel.h> 8 #include <linux/types.h> 9 10 enum mlxsw_res_id { 11 MLXSW_RES_ID_KVD_SIZE, 12 MLXSW_RES_ID_KVD_SINGLE_MIN_SIZE, 13 MLXSW_RES_ID_KVD_DOUBLE_MIN_SIZE, 14 MLXSW_RES_ID_MAX_KVD_LINEAR_RANGE, 15 MLXSW_RES_ID_MAX_KVD_ACTION_SETS, 16 MLXSW_RES_ID_MAX_TRAP_GROUPS, 17 MLXSW_RES_ID_CQE_V0, 18 MLXSW_RES_ID_CQE_V1, 19 MLXSW_RES_ID_CQE_V2, 20 MLXSW_RES_ID_COUNTER_POOL_SIZE, 21 MLXSW_RES_ID_COUNTER_BANK_SIZE, 22 MLXSW_RES_ID_MAX_SPAN, 23 MLXSW_RES_ID_COUNTER_SIZE_PACKETS_BYTES, 24 MLXSW_RES_ID_COUNTER_SIZE_ROUTER_BASIC, 25 MLXSW_RES_ID_MAX_SYSTEM_PORT, 26 MLXSW_RES_ID_MAX_LAG, 27 MLXSW_RES_ID_MAX_LAG_MEMBERS, 28 MLXSW_RES_ID_LOCAL_PORTS_IN_1X, 29 MLXSW_RES_ID_LOCAL_PORTS_IN_2X, 30 MLXSW_RES_ID_LOCAL_PORTS_IN_4X, 31 MLXSW_RES_ID_GUARANTEED_SHARED_BUFFER, 32 MLXSW_RES_ID_CELL_SIZE, 33 MLXSW_RES_ID_MAX_HEADROOM_SIZE, 34 MLXSW_RES_ID_ACL_MAX_TCAM_REGIONS, 35 MLXSW_RES_ID_ACL_MAX_TCAM_RULES, 36 MLXSW_RES_ID_ACL_MAX_REGIONS, 37 MLXSW_RES_ID_ACL_MAX_GROUPS, 38 MLXSW_RES_ID_ACL_MAX_GROUP_SIZE, 39 MLXSW_RES_ID_ACL_FLEX_KEYS, 40 MLXSW_RES_ID_ACL_MAX_ACTION_PER_RULE, 41 MLXSW_RES_ID_ACL_ACTIONS_PER_SET, 42 MLXSW_RES_ID_ACL_MAX_ERPT_BANKS, 43 MLXSW_RES_ID_ACL_MAX_ERPT_BANK_SIZE, 44 MLXSW_RES_ID_ACL_MAX_LARGE_KEY_ID, 45 MLXSW_RES_ID_ACL_ERPT_ENTRIES_2KB, 46 MLXSW_RES_ID_ACL_ERPT_ENTRIES_4KB, 47 MLXSW_RES_ID_ACL_ERPT_ENTRIES_8KB, 48 MLXSW_RES_ID_ACL_ERPT_ENTRIES_12KB, 49 MLXSW_RES_ID_ACL_MAX_BF_LOG, 50 MLXSW_RES_ID_MAX_GLOBAL_POLICERS, 51 MLXSW_RES_ID_MAX_CPU_POLICERS, 52 MLXSW_RES_ID_MAX_VRS, 53 MLXSW_RES_ID_MAX_RIFS, 54 MLXSW_RES_ID_MC_ERIF_LIST_ENTRIES, 55 MLXSW_RES_ID_MAX_LPM_TREES, 56 MLXSW_RES_ID_MAX_NVE_MC_ENTRIES_IPV4, 57 MLXSW_RES_ID_MAX_NVE_MC_ENTRIES_IPV6, 58 59 /* Internal resources. 60 * Determined by the SW, not queried from the HW. 61 */ 62 MLXSW_RES_ID_KVD_SINGLE_SIZE, 63 MLXSW_RES_ID_KVD_DOUBLE_SIZE, 64 MLXSW_RES_ID_KVD_LINEAR_SIZE, 65 66 __MLXSW_RES_ID_MAX, 67 }; 68 69 static u16 mlxsw_res_ids[] = { 70 [MLXSW_RES_ID_KVD_SIZE] = 0x1001, 71 [MLXSW_RES_ID_KVD_SINGLE_MIN_SIZE] = 0x1002, 72 [MLXSW_RES_ID_KVD_DOUBLE_MIN_SIZE] = 0x1003, 73 [MLXSW_RES_ID_MAX_KVD_LINEAR_RANGE] = 0x1005, 74 [MLXSW_RES_ID_MAX_KVD_ACTION_SETS] = 0x1007, 75 [MLXSW_RES_ID_MAX_TRAP_GROUPS] = 0x2201, 76 [MLXSW_RES_ID_CQE_V0] = 0x2210, 77 [MLXSW_RES_ID_CQE_V1] = 0x2211, 78 [MLXSW_RES_ID_CQE_V2] = 0x2212, 79 [MLXSW_RES_ID_COUNTER_POOL_SIZE] = 0x2410, 80 [MLXSW_RES_ID_COUNTER_BANK_SIZE] = 0x2411, 81 [MLXSW_RES_ID_MAX_SPAN] = 0x2420, 82 [MLXSW_RES_ID_COUNTER_SIZE_PACKETS_BYTES] = 0x2443, 83 [MLXSW_RES_ID_COUNTER_SIZE_ROUTER_BASIC] = 0x2449, 84 [MLXSW_RES_ID_MAX_SYSTEM_PORT] = 0x2502, 85 [MLXSW_RES_ID_MAX_LAG] = 0x2520, 86 [MLXSW_RES_ID_MAX_LAG_MEMBERS] = 0x2521, 87 [MLXSW_RES_ID_LOCAL_PORTS_IN_1X] = 0x2610, 88 [MLXSW_RES_ID_LOCAL_PORTS_IN_2X] = 0x2611, 89 [MLXSW_RES_ID_LOCAL_PORTS_IN_4X] = 0x2612, 90 [MLXSW_RES_ID_GUARANTEED_SHARED_BUFFER] = 0x2805, /* Bytes */ 91 [MLXSW_RES_ID_CELL_SIZE] = 0x2803, /* Bytes */ 92 [MLXSW_RES_ID_MAX_HEADROOM_SIZE] = 0x2811, /* Bytes */ 93 [MLXSW_RES_ID_ACL_MAX_TCAM_REGIONS] = 0x2901, 94 [MLXSW_RES_ID_ACL_MAX_TCAM_RULES] = 0x2902, 95 [MLXSW_RES_ID_ACL_MAX_REGIONS] = 0x2903, 96 [MLXSW_RES_ID_ACL_MAX_GROUPS] = 0x2904, 97 [MLXSW_RES_ID_ACL_MAX_GROUP_SIZE] = 0x2905, 98 [MLXSW_RES_ID_ACL_FLEX_KEYS] = 0x2910, 99 [MLXSW_RES_ID_ACL_MAX_ACTION_PER_RULE] = 0x2911, 100 [MLXSW_RES_ID_ACL_ACTIONS_PER_SET] = 0x2912, 101 [MLXSW_RES_ID_ACL_MAX_ERPT_BANKS] = 0x2940, 102 [MLXSW_RES_ID_ACL_MAX_ERPT_BANK_SIZE] = 0x2941, 103 [MLXSW_RES_ID_ACL_MAX_LARGE_KEY_ID] = 0x2942, 104 [MLXSW_RES_ID_ACL_ERPT_ENTRIES_2KB] = 0x2950, 105 [MLXSW_RES_ID_ACL_ERPT_ENTRIES_4KB] = 0x2951, 106 [MLXSW_RES_ID_ACL_ERPT_ENTRIES_8KB] = 0x2952, 107 [MLXSW_RES_ID_ACL_ERPT_ENTRIES_12KB] = 0x2953, 108 [MLXSW_RES_ID_ACL_MAX_BF_LOG] = 0x2960, 109 [MLXSW_RES_ID_MAX_GLOBAL_POLICERS] = 0x2A10, 110 [MLXSW_RES_ID_MAX_CPU_POLICERS] = 0x2A13, 111 [MLXSW_RES_ID_MAX_VRS] = 0x2C01, 112 [MLXSW_RES_ID_MAX_RIFS] = 0x2C02, 113 [MLXSW_RES_ID_MC_ERIF_LIST_ENTRIES] = 0x2C10, 114 [MLXSW_RES_ID_MAX_LPM_TREES] = 0x2C30, 115 [MLXSW_RES_ID_MAX_NVE_MC_ENTRIES_IPV4] = 0x2E02, 116 [MLXSW_RES_ID_MAX_NVE_MC_ENTRIES_IPV6] = 0x2E03, 117 }; 118 119 struct mlxsw_res { 120 bool valid[__MLXSW_RES_ID_MAX]; 121 u64 values[__MLXSW_RES_ID_MAX]; 122 }; 123 124 static inline bool mlxsw_res_valid(struct mlxsw_res *res, 125 enum mlxsw_res_id res_id) 126 { 127 return res->valid[res_id]; 128 } 129 130 #define MLXSW_RES_VALID(res, short_res_id) \ 131 mlxsw_res_valid(res, MLXSW_RES_ID_##short_res_id) 132 133 static inline u64 mlxsw_res_get(struct mlxsw_res *res, 134 enum mlxsw_res_id res_id) 135 { 136 if (WARN_ON(!res->valid[res_id])) 137 return 0; 138 return res->values[res_id]; 139 } 140 141 #define MLXSW_RES_GET(res, short_res_id) \ 142 mlxsw_res_get(res, MLXSW_RES_ID_##short_res_id) 143 144 static inline void mlxsw_res_set(struct mlxsw_res *res, 145 enum mlxsw_res_id res_id, u64 value) 146 { 147 res->valid[res_id] = true; 148 res->values[res_id] = value; 149 } 150 151 #define MLXSW_RES_SET(res, short_res_id, value) \ 152 mlxsw_res_set(res, MLXSW_RES_ID_##short_res_id, value) 153 154 static inline void mlxsw_res_parse(struct mlxsw_res *res, u16 id, u64 value) 155 { 156 int i; 157 158 for (i = 0; i < ARRAY_SIZE(mlxsw_res_ids); i++) { 159 if (mlxsw_res_ids[i] == id) { 160 mlxsw_res_set(res, i, value); 161 return; 162 } 163 } 164 } 165 166 #endif 167