1 /* 2 * drivers/net/ethernet/mellanox/mlxsw/reg.h 3 * Copyright (c) 2015-2017 Mellanox Technologies. All rights reserved. 4 * Copyright (c) 2015-2016 Ido Schimmel <idosch@mellanox.com> 5 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com> 6 * Copyright (c) 2015-2017 Jiri Pirko <jiri@mellanox.com> 7 * Copyright (c) 2016 Yotam Gigi <yotamg@mellanox.com> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the names of the copyright holders nor the names of its 18 * contributors may be used to endorse or promote products derived from 19 * this software without specific prior written permission. 20 * 21 * Alternatively, this software may be distributed under the terms of the 22 * GNU General Public License ("GPL") version 2 as published by the Free 23 * Software Foundation. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 29 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #ifndef _MLXSW_REG_H 39 #define _MLXSW_REG_H 40 41 #include <linux/string.h> 42 #include <linux/bitops.h> 43 #include <linux/if_vlan.h> 44 45 #include "item.h" 46 #include "port.h" 47 48 struct mlxsw_reg_info { 49 u16 id; 50 u16 len; /* In u8 */ 51 const char *name; 52 }; 53 54 #define MLXSW_REG_DEFINE(_name, _id, _len) \ 55 static const struct mlxsw_reg_info mlxsw_reg_##_name = { \ 56 .id = _id, \ 57 .len = _len, \ 58 .name = #_name, \ 59 } 60 61 #define MLXSW_REG(type) (&mlxsw_reg_##type) 62 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len 63 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len) 64 65 /* SGCR - Switch General Configuration Register 66 * -------------------------------------------- 67 * This register is used for configuration of the switch capabilities. 68 */ 69 #define MLXSW_REG_SGCR_ID 0x2000 70 #define MLXSW_REG_SGCR_LEN 0x10 71 72 MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN); 73 74 /* reg_sgcr_llb 75 * Link Local Broadcast (Default=0) 76 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast 77 * packets and ignore the IGMP snooping entries. 78 * Access: RW 79 */ 80 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1); 81 82 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb) 83 { 84 MLXSW_REG_ZERO(sgcr, payload); 85 mlxsw_reg_sgcr_llb_set(payload, !!llb); 86 } 87 88 /* SPAD - Switch Physical Address Register 89 * --------------------------------------- 90 * The SPAD register configures the switch physical MAC address. 91 */ 92 #define MLXSW_REG_SPAD_ID 0x2002 93 #define MLXSW_REG_SPAD_LEN 0x10 94 95 MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN); 96 97 /* reg_spad_base_mac 98 * Base MAC address for the switch partitions. 99 * Per switch partition MAC address is equal to: 100 * base_mac + swid 101 * Access: RW 102 */ 103 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6); 104 105 /* SMID - Switch Multicast ID 106 * -------------------------- 107 * The MID record maps from a MID (Multicast ID), which is a unique identifier 108 * of the multicast group within the stacking domain, into a list of local 109 * ports into which the packet is replicated. 110 */ 111 #define MLXSW_REG_SMID_ID 0x2007 112 #define MLXSW_REG_SMID_LEN 0x240 113 114 MLXSW_REG_DEFINE(smid, MLXSW_REG_SMID_ID, MLXSW_REG_SMID_LEN); 115 116 /* reg_smid_swid 117 * Switch partition ID. 118 * Access: Index 119 */ 120 MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8); 121 122 /* reg_smid_mid 123 * Multicast identifier - global identifier that represents the multicast group 124 * across all devices. 125 * Access: Index 126 */ 127 MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16); 128 129 /* reg_smid_port 130 * Local port memebership (1 bit per port). 131 * Access: RW 132 */ 133 MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1); 134 135 /* reg_smid_port_mask 136 * Local port mask (1 bit per port). 137 * Access: W 138 */ 139 MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1); 140 141 static inline void mlxsw_reg_smid_pack(char *payload, u16 mid, 142 u8 port, bool set) 143 { 144 MLXSW_REG_ZERO(smid, payload); 145 mlxsw_reg_smid_swid_set(payload, 0); 146 mlxsw_reg_smid_mid_set(payload, mid); 147 mlxsw_reg_smid_port_set(payload, port, set); 148 mlxsw_reg_smid_port_mask_set(payload, port, 1); 149 } 150 151 /* SSPR - Switch System Port Record Register 152 * ----------------------------------------- 153 * Configures the system port to local port mapping. 154 */ 155 #define MLXSW_REG_SSPR_ID 0x2008 156 #define MLXSW_REG_SSPR_LEN 0x8 157 158 MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN); 159 160 /* reg_sspr_m 161 * Master - if set, then the record describes the master system port. 162 * This is needed in case a local port is mapped into several system ports 163 * (for multipathing). That number will be reported as the source system 164 * port when packets are forwarded to the CPU. Only one master port is allowed 165 * per local port. 166 * 167 * Note: Must be set for Spectrum. 168 * Access: RW 169 */ 170 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1); 171 172 /* reg_sspr_local_port 173 * Local port number. 174 * 175 * Access: RW 176 */ 177 MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8); 178 179 /* reg_sspr_sub_port 180 * Virtual port within the physical port. 181 * Should be set to 0 when virtual ports are not enabled on the port. 182 * 183 * Access: RW 184 */ 185 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8); 186 187 /* reg_sspr_system_port 188 * Unique identifier within the stacking domain that represents all the ports 189 * that are available in the system (external ports). 190 * 191 * Currently, only single-ASIC configurations are supported, so we default to 192 * 1:1 mapping between system ports and local ports. 193 * Access: Index 194 */ 195 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16); 196 197 static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port) 198 { 199 MLXSW_REG_ZERO(sspr, payload); 200 mlxsw_reg_sspr_m_set(payload, 1); 201 mlxsw_reg_sspr_local_port_set(payload, local_port); 202 mlxsw_reg_sspr_sub_port_set(payload, 0); 203 mlxsw_reg_sspr_system_port_set(payload, local_port); 204 } 205 206 /* SFDAT - Switch Filtering Database Aging Time 207 * -------------------------------------------- 208 * Controls the Switch aging time. Aging time is able to be set per Switch 209 * Partition. 210 */ 211 #define MLXSW_REG_SFDAT_ID 0x2009 212 #define MLXSW_REG_SFDAT_LEN 0x8 213 214 MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN); 215 216 /* reg_sfdat_swid 217 * Switch partition ID. 218 * Access: Index 219 */ 220 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8); 221 222 /* reg_sfdat_age_time 223 * Aging time in seconds 224 * Min - 10 seconds 225 * Max - 1,000,000 seconds 226 * Default is 300 seconds. 227 * Access: RW 228 */ 229 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20); 230 231 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time) 232 { 233 MLXSW_REG_ZERO(sfdat, payload); 234 mlxsw_reg_sfdat_swid_set(payload, 0); 235 mlxsw_reg_sfdat_age_time_set(payload, age_time); 236 } 237 238 /* SFD - Switch Filtering Database 239 * ------------------------------- 240 * The following register defines the access to the filtering database. 241 * The register supports querying, adding, removing and modifying the database. 242 * The access is optimized for bulk updates in which case more than one 243 * FDB record is present in the same command. 244 */ 245 #define MLXSW_REG_SFD_ID 0x200A 246 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */ 247 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */ 248 #define MLXSW_REG_SFD_REC_MAX_COUNT 64 249 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \ 250 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT) 251 252 MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN); 253 254 /* reg_sfd_swid 255 * Switch partition ID for queries. Reserved on Write. 256 * Access: Index 257 */ 258 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8); 259 260 enum mlxsw_reg_sfd_op { 261 /* Dump entire FDB a (process according to record_locator) */ 262 MLXSW_REG_SFD_OP_QUERY_DUMP = 0, 263 /* Query records by {MAC, VID/FID} value */ 264 MLXSW_REG_SFD_OP_QUERY_QUERY = 1, 265 /* Query and clear activity. Query records by {MAC, VID/FID} value */ 266 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2, 267 /* Test. Response indicates if each of the records could be 268 * added to the FDB. 269 */ 270 MLXSW_REG_SFD_OP_WRITE_TEST = 0, 271 /* Add/modify. Aged-out records cannot be added. This command removes 272 * the learning notification of the {MAC, VID/FID}. Response includes 273 * the entries that were added to the FDB. 274 */ 275 MLXSW_REG_SFD_OP_WRITE_EDIT = 1, 276 /* Remove record by {MAC, VID/FID}. This command also removes 277 * the learning notification and aged-out notifications 278 * of the {MAC, VID/FID}. The response provides current (pre-removal) 279 * entries as non-aged-out. 280 */ 281 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2, 282 /* Remove learned notification by {MAC, VID/FID}. The response provides 283 * the removed learning notification. 284 */ 285 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2, 286 }; 287 288 /* reg_sfd_op 289 * Operation. 290 * Access: OP 291 */ 292 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2); 293 294 /* reg_sfd_record_locator 295 * Used for querying the FDB. Use record_locator=0 to initiate the 296 * query. When a record is returned, a new record_locator is 297 * returned to be used in the subsequent query. 298 * Reserved for database update. 299 * Access: Index 300 */ 301 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30); 302 303 /* reg_sfd_num_rec 304 * Request: Number of records to read/add/modify/remove 305 * Response: Number of records read/added/replaced/removed 306 * See above description for more details. 307 * Ranges 0..64 308 * Access: RW 309 */ 310 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8); 311 312 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op, 313 u32 record_locator) 314 { 315 MLXSW_REG_ZERO(sfd, payload); 316 mlxsw_reg_sfd_op_set(payload, op); 317 mlxsw_reg_sfd_record_locator_set(payload, record_locator); 318 } 319 320 /* reg_sfd_rec_swid 321 * Switch partition ID. 322 * Access: Index 323 */ 324 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8, 325 MLXSW_REG_SFD_REC_LEN, 0x00, false); 326 327 enum mlxsw_reg_sfd_rec_type { 328 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0, 329 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1, 330 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2, 331 }; 332 333 /* reg_sfd_rec_type 334 * FDB record type. 335 * Access: RW 336 */ 337 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4, 338 MLXSW_REG_SFD_REC_LEN, 0x00, false); 339 340 enum mlxsw_reg_sfd_rec_policy { 341 /* Replacement disabled, aging disabled. */ 342 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0, 343 /* (mlag remote): Replacement enabled, aging disabled, 344 * learning notification enabled on this port. 345 */ 346 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1, 347 /* (ingress device): Replacement enabled, aging enabled. */ 348 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3, 349 }; 350 351 /* reg_sfd_rec_policy 352 * Policy. 353 * Access: RW 354 */ 355 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2, 356 MLXSW_REG_SFD_REC_LEN, 0x00, false); 357 358 /* reg_sfd_rec_a 359 * Activity. Set for new static entries. Set for static entries if a frame SMAC 360 * lookup hits on the entry. 361 * To clear the a bit, use "query and clear activity" op. 362 * Access: RO 363 */ 364 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1, 365 MLXSW_REG_SFD_REC_LEN, 0x00, false); 366 367 /* reg_sfd_rec_mac 368 * MAC address. 369 * Access: Index 370 */ 371 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6, 372 MLXSW_REG_SFD_REC_LEN, 0x02); 373 374 enum mlxsw_reg_sfd_rec_action { 375 /* forward */ 376 MLXSW_REG_SFD_REC_ACTION_NOP = 0, 377 /* forward and trap, trap_id is FDB_TRAP */ 378 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1, 379 /* trap and do not forward, trap_id is FDB_TRAP */ 380 MLXSW_REG_SFD_REC_ACTION_TRAP = 2, 381 /* forward to IP router */ 382 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3, 383 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15, 384 }; 385 386 /* reg_sfd_rec_action 387 * Action to apply on the packet. 388 * Note: Dynamic entries can only be configured with NOP action. 389 * Access: RW 390 */ 391 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4, 392 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 393 394 /* reg_sfd_uc_sub_port 395 * VEPA channel on local port. 396 * Valid only if local port is a non-stacking port. Must be 0 if multichannel 397 * VEPA is not enabled. 398 * Access: RW 399 */ 400 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 401 MLXSW_REG_SFD_REC_LEN, 0x08, false); 402 403 /* reg_sfd_uc_fid_vid 404 * Filtering ID or VLAN ID 405 * For SwitchX and SwitchX-2: 406 * - Dynamic entries (policy 2,3) use FID 407 * - Static entries (policy 0) use VID 408 * - When independent learning is configured, VID=FID 409 * For Spectrum: use FID for both Dynamic and Static entries. 410 * VID should not be used. 411 * Access: Index 412 */ 413 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 414 MLXSW_REG_SFD_REC_LEN, 0x08, false); 415 416 /* reg_sfd_uc_system_port 417 * Unique port identifier for the final destination of the packet. 418 * Access: RW 419 */ 420 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16, 421 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 422 423 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index, 424 enum mlxsw_reg_sfd_rec_type rec_type, 425 const char *mac, 426 enum mlxsw_reg_sfd_rec_action action) 427 { 428 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload); 429 430 if (rec_index >= num_rec) 431 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1); 432 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0); 433 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type); 434 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac); 435 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action); 436 } 437 438 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index, 439 enum mlxsw_reg_sfd_rec_policy policy, 440 const char *mac, u16 fid_vid, 441 enum mlxsw_reg_sfd_rec_action action, 442 u8 local_port) 443 { 444 mlxsw_reg_sfd_rec_pack(payload, rec_index, 445 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action); 446 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 447 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0); 448 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid); 449 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port); 450 } 451 452 static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index, 453 char *mac, u16 *p_fid_vid, 454 u8 *p_local_port) 455 { 456 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 457 *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index); 458 *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index); 459 } 460 461 /* reg_sfd_uc_lag_sub_port 462 * LAG sub port. 463 * Must be 0 if multichannel VEPA is not enabled. 464 * Access: RW 465 */ 466 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 467 MLXSW_REG_SFD_REC_LEN, 0x08, false); 468 469 /* reg_sfd_uc_lag_fid_vid 470 * Filtering ID or VLAN ID 471 * For SwitchX and SwitchX-2: 472 * - Dynamic entries (policy 2,3) use FID 473 * - Static entries (policy 0) use VID 474 * - When independent learning is configured, VID=FID 475 * For Spectrum: use FID for both Dynamic and Static entries. 476 * VID should not be used. 477 * Access: Index 478 */ 479 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 480 MLXSW_REG_SFD_REC_LEN, 0x08, false); 481 482 /* reg_sfd_uc_lag_lag_vid 483 * Indicates VID in case of vFIDs. Reserved for FIDs. 484 * Access: RW 485 */ 486 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, 487 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 488 489 /* reg_sfd_uc_lag_lag_id 490 * LAG Identifier - pointer into the LAG descriptor table. 491 * Access: RW 492 */ 493 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10, 494 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 495 496 static inline void 497 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index, 498 enum mlxsw_reg_sfd_rec_policy policy, 499 const char *mac, u16 fid_vid, 500 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid, 501 u16 lag_id) 502 { 503 mlxsw_reg_sfd_rec_pack(payload, rec_index, 504 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG, 505 mac, action); 506 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 507 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0); 508 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid); 509 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid); 510 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id); 511 } 512 513 static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index, 514 char *mac, u16 *p_vid, 515 u16 *p_lag_id) 516 { 517 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 518 *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index); 519 *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index); 520 } 521 522 /* reg_sfd_mc_pgi 523 * 524 * Multicast port group index - index into the port group table. 525 * Value 0x1FFF indicates the pgi should point to the MID entry. 526 * For Spectrum this value must be set to 0x1FFF 527 * Access: RW 528 */ 529 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13, 530 MLXSW_REG_SFD_REC_LEN, 0x08, false); 531 532 /* reg_sfd_mc_fid_vid 533 * 534 * Filtering ID or VLAN ID 535 * Access: Index 536 */ 537 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 538 MLXSW_REG_SFD_REC_LEN, 0x08, false); 539 540 /* reg_sfd_mc_mid 541 * 542 * Multicast identifier - global identifier that represents the multicast 543 * group across all devices. 544 * Access: RW 545 */ 546 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 547 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 548 549 static inline void 550 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index, 551 const char *mac, u16 fid_vid, 552 enum mlxsw_reg_sfd_rec_action action, u16 mid) 553 { 554 mlxsw_reg_sfd_rec_pack(payload, rec_index, 555 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action); 556 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF); 557 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid); 558 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid); 559 } 560 561 /* SFN - Switch FDB Notification Register 562 * ------------------------------------------- 563 * The switch provides notifications on newly learned FDB entries and 564 * aged out entries. The notifications can be polled by software. 565 */ 566 #define MLXSW_REG_SFN_ID 0x200B 567 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */ 568 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */ 569 #define MLXSW_REG_SFN_REC_MAX_COUNT 64 570 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \ 571 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT) 572 573 MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN); 574 575 /* reg_sfn_swid 576 * Switch partition ID. 577 * Access: Index 578 */ 579 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8); 580 581 /* reg_sfn_end 582 * Forces the current session to end. 583 * Access: OP 584 */ 585 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1); 586 587 /* reg_sfn_num_rec 588 * Request: Number of learned notifications and aged-out notification 589 * records requested. 590 * Response: Number of notification records returned (must be smaller 591 * than or equal to the value requested) 592 * Ranges 0..64 593 * Access: OP 594 */ 595 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8); 596 597 static inline void mlxsw_reg_sfn_pack(char *payload) 598 { 599 MLXSW_REG_ZERO(sfn, payload); 600 mlxsw_reg_sfn_swid_set(payload, 0); 601 mlxsw_reg_sfn_end_set(payload, 1); 602 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT); 603 } 604 605 /* reg_sfn_rec_swid 606 * Switch partition ID. 607 * Access: RO 608 */ 609 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8, 610 MLXSW_REG_SFN_REC_LEN, 0x00, false); 611 612 enum mlxsw_reg_sfn_rec_type { 613 /* MAC addresses learned on a regular port. */ 614 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5, 615 /* MAC addresses learned on a LAG port. */ 616 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6, 617 /* Aged-out MAC address on a regular port. */ 618 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7, 619 /* Aged-out MAC address on a LAG port. */ 620 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8, 621 }; 622 623 /* reg_sfn_rec_type 624 * Notification record type. 625 * Access: RO 626 */ 627 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4, 628 MLXSW_REG_SFN_REC_LEN, 0x00, false); 629 630 /* reg_sfn_rec_mac 631 * MAC address. 632 * Access: RO 633 */ 634 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6, 635 MLXSW_REG_SFN_REC_LEN, 0x02); 636 637 /* reg_sfn_mac_sub_port 638 * VEPA channel on the local port. 639 * 0 if multichannel VEPA is not enabled. 640 * Access: RO 641 */ 642 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8, 643 MLXSW_REG_SFN_REC_LEN, 0x08, false); 644 645 /* reg_sfn_mac_fid 646 * Filtering identifier. 647 * Access: RO 648 */ 649 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16, 650 MLXSW_REG_SFN_REC_LEN, 0x08, false); 651 652 /* reg_sfn_mac_system_port 653 * Unique port identifier for the final destination of the packet. 654 * Access: RO 655 */ 656 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16, 657 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 658 659 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index, 660 char *mac, u16 *p_vid, 661 u8 *p_local_port) 662 { 663 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 664 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 665 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index); 666 } 667 668 /* reg_sfn_mac_lag_lag_id 669 * LAG ID (pointer into the LAG descriptor table). 670 * Access: RO 671 */ 672 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10, 673 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 674 675 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index, 676 char *mac, u16 *p_vid, 677 u16 *p_lag_id) 678 { 679 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 680 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 681 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index); 682 } 683 684 /* SPMS - Switch Port MSTP/RSTP State Register 685 * ------------------------------------------- 686 * Configures the spanning tree state of a physical port. 687 */ 688 #define MLXSW_REG_SPMS_ID 0x200D 689 #define MLXSW_REG_SPMS_LEN 0x404 690 691 MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN); 692 693 /* reg_spms_local_port 694 * Local port number. 695 * Access: Index 696 */ 697 MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8); 698 699 enum mlxsw_reg_spms_state { 700 MLXSW_REG_SPMS_STATE_NO_CHANGE, 701 MLXSW_REG_SPMS_STATE_DISCARDING, 702 MLXSW_REG_SPMS_STATE_LEARNING, 703 MLXSW_REG_SPMS_STATE_FORWARDING, 704 }; 705 706 /* reg_spms_state 707 * Spanning tree state of each VLAN ID (VID) of the local port. 708 * 0 - Do not change spanning tree state (used only when writing). 709 * 1 - Discarding. No learning or forwarding to/from this port (default). 710 * 2 - Learning. Port is learning, but not forwarding. 711 * 3 - Forwarding. Port is learning and forwarding. 712 * Access: RW 713 */ 714 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2); 715 716 static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port) 717 { 718 MLXSW_REG_ZERO(spms, payload); 719 mlxsw_reg_spms_local_port_set(payload, local_port); 720 } 721 722 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid, 723 enum mlxsw_reg_spms_state state) 724 { 725 mlxsw_reg_spms_state_set(payload, vid, state); 726 } 727 728 /* SPVID - Switch Port VID 729 * ----------------------- 730 * The switch port VID configures the default VID for a port. 731 */ 732 #define MLXSW_REG_SPVID_ID 0x200E 733 #define MLXSW_REG_SPVID_LEN 0x08 734 735 MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN); 736 737 /* reg_spvid_local_port 738 * Local port number. 739 * Access: Index 740 */ 741 MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8); 742 743 /* reg_spvid_sub_port 744 * Virtual port within the physical port. 745 * Should be set to 0 when virtual ports are not enabled on the port. 746 * Access: Index 747 */ 748 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8); 749 750 /* reg_spvid_pvid 751 * Port default VID 752 * Access: RW 753 */ 754 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12); 755 756 static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid) 757 { 758 MLXSW_REG_ZERO(spvid, payload); 759 mlxsw_reg_spvid_local_port_set(payload, local_port); 760 mlxsw_reg_spvid_pvid_set(payload, pvid); 761 } 762 763 /* SPVM - Switch Port VLAN Membership 764 * ---------------------------------- 765 * The Switch Port VLAN Membership register configures the VLAN membership 766 * of a port in a VLAN denoted by VID. VLAN membership is managed per 767 * virtual port. The register can be used to add and remove VID(s) from a port. 768 */ 769 #define MLXSW_REG_SPVM_ID 0x200F 770 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */ 771 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */ 772 #define MLXSW_REG_SPVM_REC_MAX_COUNT 255 773 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \ 774 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT) 775 776 MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN); 777 778 /* reg_spvm_pt 779 * Priority tagged. If this bit is set, packets forwarded to the port with 780 * untagged VLAN membership (u bit is set) will be tagged with priority tag 781 * (VID=0) 782 * Access: RW 783 */ 784 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1); 785 786 /* reg_spvm_pte 787 * Priority Tagged Update Enable. On Write operations, if this bit is cleared, 788 * the pt bit will NOT be updated. To update the pt bit, pte must be set. 789 * Access: WO 790 */ 791 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1); 792 793 /* reg_spvm_local_port 794 * Local port number. 795 * Access: Index 796 */ 797 MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8); 798 799 /* reg_spvm_sub_port 800 * Virtual port within the physical port. 801 * Should be set to 0 when virtual ports are not enabled on the port. 802 * Access: Index 803 */ 804 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8); 805 806 /* reg_spvm_num_rec 807 * Number of records to update. Each record contains: i, e, u, vid. 808 * Access: OP 809 */ 810 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8); 811 812 /* reg_spvm_rec_i 813 * Ingress membership in VLAN ID. 814 * Access: Index 815 */ 816 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i, 817 MLXSW_REG_SPVM_BASE_LEN, 14, 1, 818 MLXSW_REG_SPVM_REC_LEN, 0, false); 819 820 /* reg_spvm_rec_e 821 * Egress membership in VLAN ID. 822 * Access: Index 823 */ 824 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e, 825 MLXSW_REG_SPVM_BASE_LEN, 13, 1, 826 MLXSW_REG_SPVM_REC_LEN, 0, false); 827 828 /* reg_spvm_rec_u 829 * Untagged - port is an untagged member - egress transmission uses untagged 830 * frames on VID<n> 831 * Access: Index 832 */ 833 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u, 834 MLXSW_REG_SPVM_BASE_LEN, 12, 1, 835 MLXSW_REG_SPVM_REC_LEN, 0, false); 836 837 /* reg_spvm_rec_vid 838 * Egress membership in VLAN ID. 839 * Access: Index 840 */ 841 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid, 842 MLXSW_REG_SPVM_BASE_LEN, 0, 12, 843 MLXSW_REG_SPVM_REC_LEN, 0, false); 844 845 static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port, 846 u16 vid_begin, u16 vid_end, 847 bool is_member, bool untagged) 848 { 849 int size = vid_end - vid_begin + 1; 850 int i; 851 852 MLXSW_REG_ZERO(spvm, payload); 853 mlxsw_reg_spvm_local_port_set(payload, local_port); 854 mlxsw_reg_spvm_num_rec_set(payload, size); 855 856 for (i = 0; i < size; i++) { 857 mlxsw_reg_spvm_rec_i_set(payload, i, is_member); 858 mlxsw_reg_spvm_rec_e_set(payload, i, is_member); 859 mlxsw_reg_spvm_rec_u_set(payload, i, untagged); 860 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i); 861 } 862 } 863 864 /* SPAFT - Switch Port Acceptable Frame Types 865 * ------------------------------------------ 866 * The Switch Port Acceptable Frame Types register configures the frame 867 * admittance of the port. 868 */ 869 #define MLXSW_REG_SPAFT_ID 0x2010 870 #define MLXSW_REG_SPAFT_LEN 0x08 871 872 MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN); 873 874 /* reg_spaft_local_port 875 * Local port number. 876 * Access: Index 877 * 878 * Note: CPU port is not supported (all tag types are allowed). 879 */ 880 MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8); 881 882 /* reg_spaft_sub_port 883 * Virtual port within the physical port. 884 * Should be set to 0 when virtual ports are not enabled on the port. 885 * Access: RW 886 */ 887 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8); 888 889 /* reg_spaft_allow_untagged 890 * When set, untagged frames on the ingress are allowed (default). 891 * Access: RW 892 */ 893 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1); 894 895 /* reg_spaft_allow_prio_tagged 896 * When set, priority tagged frames on the ingress are allowed (default). 897 * Access: RW 898 */ 899 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1); 900 901 /* reg_spaft_allow_tagged 902 * When set, tagged frames on the ingress are allowed (default). 903 * Access: RW 904 */ 905 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1); 906 907 static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port, 908 bool allow_untagged) 909 { 910 MLXSW_REG_ZERO(spaft, payload); 911 mlxsw_reg_spaft_local_port_set(payload, local_port); 912 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged); 913 mlxsw_reg_spaft_allow_prio_tagged_set(payload, true); 914 mlxsw_reg_spaft_allow_tagged_set(payload, true); 915 } 916 917 /* SFGC - Switch Flooding Group Configuration 918 * ------------------------------------------ 919 * The following register controls the association of flooding tables and MIDs 920 * to packet types used for flooding. 921 */ 922 #define MLXSW_REG_SFGC_ID 0x2011 923 #define MLXSW_REG_SFGC_LEN 0x10 924 925 MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN); 926 927 enum mlxsw_reg_sfgc_type { 928 MLXSW_REG_SFGC_TYPE_BROADCAST, 929 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST, 930 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4, 931 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6, 932 MLXSW_REG_SFGC_TYPE_RESERVED, 933 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP, 934 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL, 935 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST, 936 MLXSW_REG_SFGC_TYPE_MAX, 937 }; 938 939 /* reg_sfgc_type 940 * The traffic type to reach the flooding table. 941 * Access: Index 942 */ 943 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4); 944 945 enum mlxsw_reg_sfgc_bridge_type { 946 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0, 947 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1, 948 }; 949 950 /* reg_sfgc_bridge_type 951 * Access: Index 952 * 953 * Note: SwitchX-2 only supports 802.1Q mode. 954 */ 955 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3); 956 957 enum mlxsw_flood_table_type { 958 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1, 959 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2, 960 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0, 961 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST = 3, 962 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4, 963 }; 964 965 /* reg_sfgc_table_type 966 * See mlxsw_flood_table_type 967 * Access: RW 968 * 969 * Note: FID offset and FID types are not supported in SwitchX-2. 970 */ 971 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3); 972 973 /* reg_sfgc_flood_table 974 * Flooding table index to associate with the specific type on the specific 975 * switch partition. 976 * Access: RW 977 */ 978 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6); 979 980 /* reg_sfgc_mid 981 * The multicast ID for the swid. Not supported for Spectrum 982 * Access: RW 983 */ 984 MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16); 985 986 /* reg_sfgc_counter_set_type 987 * Counter Set Type for flow counters. 988 * Access: RW 989 */ 990 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8); 991 992 /* reg_sfgc_counter_index 993 * Counter Index for flow counters. 994 * Access: RW 995 */ 996 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24); 997 998 static inline void 999 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type, 1000 enum mlxsw_reg_sfgc_bridge_type bridge_type, 1001 enum mlxsw_flood_table_type table_type, 1002 unsigned int flood_table) 1003 { 1004 MLXSW_REG_ZERO(sfgc, payload); 1005 mlxsw_reg_sfgc_type_set(payload, type); 1006 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type); 1007 mlxsw_reg_sfgc_table_type_set(payload, table_type); 1008 mlxsw_reg_sfgc_flood_table_set(payload, flood_table); 1009 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID); 1010 } 1011 1012 /* SFTR - Switch Flooding Table Register 1013 * ------------------------------------- 1014 * The switch flooding table is used for flooding packet replication. The table 1015 * defines a bit mask of ports for packet replication. 1016 */ 1017 #define MLXSW_REG_SFTR_ID 0x2012 1018 #define MLXSW_REG_SFTR_LEN 0x420 1019 1020 MLXSW_REG_DEFINE(sftr, MLXSW_REG_SFTR_ID, MLXSW_REG_SFTR_LEN); 1021 1022 /* reg_sftr_swid 1023 * Switch partition ID with which to associate the port. 1024 * Access: Index 1025 */ 1026 MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8); 1027 1028 /* reg_sftr_flood_table 1029 * Flooding table index to associate with the specific type on the specific 1030 * switch partition. 1031 * Access: Index 1032 */ 1033 MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6); 1034 1035 /* reg_sftr_index 1036 * Index. Used as an index into the Flooding Table in case the table is 1037 * configured to use VID / FID or FID Offset. 1038 * Access: Index 1039 */ 1040 MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16); 1041 1042 /* reg_sftr_table_type 1043 * See mlxsw_flood_table_type 1044 * Access: RW 1045 */ 1046 MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3); 1047 1048 /* reg_sftr_range 1049 * Range of entries to update 1050 * Access: Index 1051 */ 1052 MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16); 1053 1054 /* reg_sftr_port 1055 * Local port membership (1 bit per port). 1056 * Access: RW 1057 */ 1058 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1); 1059 1060 /* reg_sftr_cpu_port_mask 1061 * CPU port mask (1 bit per port). 1062 * Access: W 1063 */ 1064 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1); 1065 1066 static inline void mlxsw_reg_sftr_pack(char *payload, 1067 unsigned int flood_table, 1068 unsigned int index, 1069 enum mlxsw_flood_table_type table_type, 1070 unsigned int range, u8 port, bool set) 1071 { 1072 MLXSW_REG_ZERO(sftr, payload); 1073 mlxsw_reg_sftr_swid_set(payload, 0); 1074 mlxsw_reg_sftr_flood_table_set(payload, flood_table); 1075 mlxsw_reg_sftr_index_set(payload, index); 1076 mlxsw_reg_sftr_table_type_set(payload, table_type); 1077 mlxsw_reg_sftr_range_set(payload, range); 1078 mlxsw_reg_sftr_port_set(payload, port, set); 1079 mlxsw_reg_sftr_port_mask_set(payload, port, 1); 1080 } 1081 1082 /* SFDF - Switch Filtering DB Flush 1083 * -------------------------------- 1084 * The switch filtering DB flush register is used to flush the FDB. 1085 * Note that FDB notifications are flushed as well. 1086 */ 1087 #define MLXSW_REG_SFDF_ID 0x2013 1088 #define MLXSW_REG_SFDF_LEN 0x14 1089 1090 MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN); 1091 1092 /* reg_sfdf_swid 1093 * Switch partition ID. 1094 * Access: Index 1095 */ 1096 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8); 1097 1098 enum mlxsw_reg_sfdf_flush_type { 1099 MLXSW_REG_SFDF_FLUSH_PER_SWID, 1100 MLXSW_REG_SFDF_FLUSH_PER_FID, 1101 MLXSW_REG_SFDF_FLUSH_PER_PORT, 1102 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID, 1103 MLXSW_REG_SFDF_FLUSH_PER_LAG, 1104 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID, 1105 }; 1106 1107 /* reg_sfdf_flush_type 1108 * Flush type. 1109 * 0 - All SWID dynamic entries are flushed. 1110 * 1 - All FID dynamic entries are flushed. 1111 * 2 - All dynamic entries pointing to port are flushed. 1112 * 3 - All FID dynamic entries pointing to port are flushed. 1113 * 4 - All dynamic entries pointing to LAG are flushed. 1114 * 5 - All FID dynamic entries pointing to LAG are flushed. 1115 * Access: RW 1116 */ 1117 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4); 1118 1119 /* reg_sfdf_flush_static 1120 * Static. 1121 * 0 - Flush only dynamic entries. 1122 * 1 - Flush both dynamic and static entries. 1123 * Access: RW 1124 */ 1125 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1); 1126 1127 static inline void mlxsw_reg_sfdf_pack(char *payload, 1128 enum mlxsw_reg_sfdf_flush_type type) 1129 { 1130 MLXSW_REG_ZERO(sfdf, payload); 1131 mlxsw_reg_sfdf_flush_type_set(payload, type); 1132 mlxsw_reg_sfdf_flush_static_set(payload, true); 1133 } 1134 1135 /* reg_sfdf_fid 1136 * FID to flush. 1137 * Access: RW 1138 */ 1139 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16); 1140 1141 /* reg_sfdf_system_port 1142 * Port to flush. 1143 * Access: RW 1144 */ 1145 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16); 1146 1147 /* reg_sfdf_port_fid_system_port 1148 * Port to flush, pointed to by FID. 1149 * Access: RW 1150 */ 1151 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16); 1152 1153 /* reg_sfdf_lag_id 1154 * LAG ID to flush. 1155 * Access: RW 1156 */ 1157 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10); 1158 1159 /* reg_sfdf_lag_fid_lag_id 1160 * LAG ID to flush, pointed to by FID. 1161 * Access: RW 1162 */ 1163 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10); 1164 1165 /* SLDR - Switch LAG Descriptor Register 1166 * ----------------------------------------- 1167 * The switch LAG descriptor register is populated by LAG descriptors. 1168 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to 1169 * max_lag-1. 1170 */ 1171 #define MLXSW_REG_SLDR_ID 0x2014 1172 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */ 1173 1174 MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN); 1175 1176 enum mlxsw_reg_sldr_op { 1177 /* Indicates a creation of a new LAG-ID, lag_id must be valid */ 1178 MLXSW_REG_SLDR_OP_LAG_CREATE, 1179 MLXSW_REG_SLDR_OP_LAG_DESTROY, 1180 /* Ports that appear in the list have the Distributor enabled */ 1181 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST, 1182 /* Removes ports from the disributor list */ 1183 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST, 1184 }; 1185 1186 /* reg_sldr_op 1187 * Operation. 1188 * Access: RW 1189 */ 1190 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3); 1191 1192 /* reg_sldr_lag_id 1193 * LAG identifier. The lag_id is the index into the LAG descriptor table. 1194 * Access: Index 1195 */ 1196 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10); 1197 1198 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id) 1199 { 1200 MLXSW_REG_ZERO(sldr, payload); 1201 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE); 1202 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1203 } 1204 1205 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id) 1206 { 1207 MLXSW_REG_ZERO(sldr, payload); 1208 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY); 1209 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1210 } 1211 1212 /* reg_sldr_num_ports 1213 * The number of member ports of the LAG. 1214 * Reserved for Create / Destroy operations 1215 * For Add / Remove operations - indicates the number of ports in the list. 1216 * Access: RW 1217 */ 1218 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8); 1219 1220 /* reg_sldr_system_port 1221 * System port. 1222 * Access: RW 1223 */ 1224 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false); 1225 1226 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id, 1227 u8 local_port) 1228 { 1229 MLXSW_REG_ZERO(sldr, payload); 1230 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST); 1231 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1232 mlxsw_reg_sldr_num_ports_set(payload, 1); 1233 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1234 } 1235 1236 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id, 1237 u8 local_port) 1238 { 1239 MLXSW_REG_ZERO(sldr, payload); 1240 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST); 1241 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1242 mlxsw_reg_sldr_num_ports_set(payload, 1); 1243 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1244 } 1245 1246 /* SLCR - Switch LAG Configuration 2 Register 1247 * ------------------------------------------- 1248 * The Switch LAG Configuration register is used for configuring the 1249 * LAG properties of the switch. 1250 */ 1251 #define MLXSW_REG_SLCR_ID 0x2015 1252 #define MLXSW_REG_SLCR_LEN 0x10 1253 1254 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN); 1255 1256 enum mlxsw_reg_slcr_pp { 1257 /* Global Configuration (for all ports) */ 1258 MLXSW_REG_SLCR_PP_GLOBAL, 1259 /* Per port configuration, based on local_port field */ 1260 MLXSW_REG_SLCR_PP_PER_PORT, 1261 }; 1262 1263 /* reg_slcr_pp 1264 * Per Port Configuration 1265 * Note: Reading at Global mode results in reading port 1 configuration. 1266 * Access: Index 1267 */ 1268 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1); 1269 1270 /* reg_slcr_local_port 1271 * Local port number 1272 * Supported from CPU port 1273 * Not supported from router port 1274 * Reserved when pp = Global Configuration 1275 * Access: Index 1276 */ 1277 MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8); 1278 1279 enum mlxsw_reg_slcr_type { 1280 MLXSW_REG_SLCR_TYPE_CRC, /* default */ 1281 MLXSW_REG_SLCR_TYPE_XOR, 1282 MLXSW_REG_SLCR_TYPE_RANDOM, 1283 }; 1284 1285 /* reg_slcr_type 1286 * Hash type 1287 * Access: RW 1288 */ 1289 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4); 1290 1291 /* Ingress port */ 1292 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0) 1293 /* SMAC - for IPv4 and IPv6 packets */ 1294 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1) 1295 /* SMAC - for non-IP packets */ 1296 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2) 1297 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \ 1298 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \ 1299 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP) 1300 /* DMAC - for IPv4 and IPv6 packets */ 1301 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3) 1302 /* DMAC - for non-IP packets */ 1303 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4) 1304 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \ 1305 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \ 1306 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP) 1307 /* Ethertype - for IPv4 and IPv6 packets */ 1308 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5) 1309 /* Ethertype - for non-IP packets */ 1310 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6) 1311 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \ 1312 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \ 1313 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP) 1314 /* VLAN ID - for IPv4 and IPv6 packets */ 1315 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7) 1316 /* VLAN ID - for non-IP packets */ 1317 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8) 1318 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \ 1319 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \ 1320 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP) 1321 /* Source IP address (can be IPv4 or IPv6) */ 1322 #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9) 1323 /* Destination IP address (can be IPv4 or IPv6) */ 1324 #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10) 1325 /* TCP/UDP source port */ 1326 #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11) 1327 /* TCP/UDP destination port*/ 1328 #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12) 1329 /* IPv4 Protocol/IPv6 Next Header */ 1330 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13) 1331 /* IPv6 Flow label */ 1332 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14) 1333 /* SID - FCoE source ID */ 1334 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15) 1335 /* DID - FCoE destination ID */ 1336 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16) 1337 /* OXID - FCoE originator exchange ID */ 1338 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17) 1339 /* Destination QP number - for RoCE packets */ 1340 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19) 1341 1342 /* reg_slcr_lag_hash 1343 * LAG hashing configuration. This is a bitmask, in which each set 1344 * bit includes the corresponding item in the LAG hash calculation. 1345 * The default lag_hash contains SMAC, DMAC, VLANID and 1346 * Ethertype (for all packet types). 1347 * Access: RW 1348 */ 1349 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20); 1350 1351 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash) 1352 { 1353 MLXSW_REG_ZERO(slcr, payload); 1354 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL); 1355 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC); 1356 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash); 1357 } 1358 1359 /* SLCOR - Switch LAG Collector Register 1360 * ------------------------------------- 1361 * The Switch LAG Collector register controls the Local Port membership 1362 * in a LAG and enablement of the collector. 1363 */ 1364 #define MLXSW_REG_SLCOR_ID 0x2016 1365 #define MLXSW_REG_SLCOR_LEN 0x10 1366 1367 MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN); 1368 1369 enum mlxsw_reg_slcor_col { 1370 /* Port is added with collector disabled */ 1371 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT, 1372 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED, 1373 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED, 1374 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT, 1375 }; 1376 1377 /* reg_slcor_col 1378 * Collector configuration 1379 * Access: RW 1380 */ 1381 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2); 1382 1383 /* reg_slcor_local_port 1384 * Local port number 1385 * Not supported for CPU port 1386 * Access: Index 1387 */ 1388 MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8); 1389 1390 /* reg_slcor_lag_id 1391 * LAG Identifier. Index into the LAG descriptor table. 1392 * Access: Index 1393 */ 1394 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10); 1395 1396 /* reg_slcor_port_index 1397 * Port index in the LAG list. Only valid on Add Port to LAG col. 1398 * Valid range is from 0 to cap_max_lag_members-1 1399 * Access: RW 1400 */ 1401 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10); 1402 1403 static inline void mlxsw_reg_slcor_pack(char *payload, 1404 u8 local_port, u16 lag_id, 1405 enum mlxsw_reg_slcor_col col) 1406 { 1407 MLXSW_REG_ZERO(slcor, payload); 1408 mlxsw_reg_slcor_col_set(payload, col); 1409 mlxsw_reg_slcor_local_port_set(payload, local_port); 1410 mlxsw_reg_slcor_lag_id_set(payload, lag_id); 1411 } 1412 1413 static inline void mlxsw_reg_slcor_port_add_pack(char *payload, 1414 u8 local_port, u16 lag_id, 1415 u8 port_index) 1416 { 1417 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1418 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT); 1419 mlxsw_reg_slcor_port_index_set(payload, port_index); 1420 } 1421 1422 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload, 1423 u8 local_port, u16 lag_id) 1424 { 1425 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1426 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT); 1427 } 1428 1429 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload, 1430 u8 local_port, u16 lag_id) 1431 { 1432 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1433 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1434 } 1435 1436 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload, 1437 u8 local_port, u16 lag_id) 1438 { 1439 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1440 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1441 } 1442 1443 /* SPMLR - Switch Port MAC Learning Register 1444 * ----------------------------------------- 1445 * Controls the Switch MAC learning policy per port. 1446 */ 1447 #define MLXSW_REG_SPMLR_ID 0x2018 1448 #define MLXSW_REG_SPMLR_LEN 0x8 1449 1450 MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN); 1451 1452 /* reg_spmlr_local_port 1453 * Local port number. 1454 * Access: Index 1455 */ 1456 MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8); 1457 1458 /* reg_spmlr_sub_port 1459 * Virtual port within the physical port. 1460 * Should be set to 0 when virtual ports are not enabled on the port. 1461 * Access: Index 1462 */ 1463 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8); 1464 1465 enum mlxsw_reg_spmlr_learn_mode { 1466 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0, 1467 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2, 1468 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3, 1469 }; 1470 1471 /* reg_spmlr_learn_mode 1472 * Learning mode on the port. 1473 * 0 - Learning disabled. 1474 * 2 - Learning enabled. 1475 * 3 - Security mode. 1476 * 1477 * In security mode the switch does not learn MACs on the port, but uses the 1478 * SMAC to see if it exists on another ingress port. If so, the packet is 1479 * classified as a bad packet and is discarded unless the software registers 1480 * to receive port security error packets usign HPKT. 1481 */ 1482 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2); 1483 1484 static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port, 1485 enum mlxsw_reg_spmlr_learn_mode mode) 1486 { 1487 MLXSW_REG_ZERO(spmlr, payload); 1488 mlxsw_reg_spmlr_local_port_set(payload, local_port); 1489 mlxsw_reg_spmlr_sub_port_set(payload, 0); 1490 mlxsw_reg_spmlr_learn_mode_set(payload, mode); 1491 } 1492 1493 /* SVFA - Switch VID to FID Allocation Register 1494 * -------------------------------------------- 1495 * Controls the VID to FID mapping and {Port, VID} to FID mapping for 1496 * virtualized ports. 1497 */ 1498 #define MLXSW_REG_SVFA_ID 0x201C 1499 #define MLXSW_REG_SVFA_LEN 0x10 1500 1501 MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN); 1502 1503 /* reg_svfa_swid 1504 * Switch partition ID. 1505 * Access: Index 1506 */ 1507 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8); 1508 1509 /* reg_svfa_local_port 1510 * Local port number. 1511 * Access: Index 1512 * 1513 * Note: Reserved for 802.1Q FIDs. 1514 */ 1515 MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8); 1516 1517 enum mlxsw_reg_svfa_mt { 1518 MLXSW_REG_SVFA_MT_VID_TO_FID, 1519 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, 1520 }; 1521 1522 /* reg_svfa_mapping_table 1523 * Mapping table: 1524 * 0 - VID to FID 1525 * 1 - {Port, VID} to FID 1526 * Access: Index 1527 * 1528 * Note: Reserved for SwitchX-2. 1529 */ 1530 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3); 1531 1532 /* reg_svfa_v 1533 * Valid. 1534 * Valid if set. 1535 * Access: RW 1536 * 1537 * Note: Reserved for SwitchX-2. 1538 */ 1539 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1); 1540 1541 /* reg_svfa_fid 1542 * Filtering ID. 1543 * Access: RW 1544 */ 1545 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16); 1546 1547 /* reg_svfa_vid 1548 * VLAN ID. 1549 * Access: Index 1550 */ 1551 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12); 1552 1553 /* reg_svfa_counter_set_type 1554 * Counter set type for flow counters. 1555 * Access: RW 1556 * 1557 * Note: Reserved for SwitchX-2. 1558 */ 1559 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8); 1560 1561 /* reg_svfa_counter_index 1562 * Counter index for flow counters. 1563 * Access: RW 1564 * 1565 * Note: Reserved for SwitchX-2. 1566 */ 1567 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24); 1568 1569 static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port, 1570 enum mlxsw_reg_svfa_mt mt, bool valid, 1571 u16 fid, u16 vid) 1572 { 1573 MLXSW_REG_ZERO(svfa, payload); 1574 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port; 1575 mlxsw_reg_svfa_swid_set(payload, 0); 1576 mlxsw_reg_svfa_local_port_set(payload, local_port); 1577 mlxsw_reg_svfa_mapping_table_set(payload, mt); 1578 mlxsw_reg_svfa_v_set(payload, valid); 1579 mlxsw_reg_svfa_fid_set(payload, fid); 1580 mlxsw_reg_svfa_vid_set(payload, vid); 1581 } 1582 1583 /* SVPE - Switch Virtual-Port Enabling Register 1584 * -------------------------------------------- 1585 * Enables port virtualization. 1586 */ 1587 #define MLXSW_REG_SVPE_ID 0x201E 1588 #define MLXSW_REG_SVPE_LEN 0x4 1589 1590 MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN); 1591 1592 /* reg_svpe_local_port 1593 * Local port number 1594 * Access: Index 1595 * 1596 * Note: CPU port is not supported (uses VLAN mode only). 1597 */ 1598 MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8); 1599 1600 /* reg_svpe_vp_en 1601 * Virtual port enable. 1602 * 0 - Disable, VLAN mode (VID to FID). 1603 * 1 - Enable, Virtual port mode ({Port, VID} to FID). 1604 * Access: RW 1605 */ 1606 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1); 1607 1608 static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port, 1609 bool enable) 1610 { 1611 MLXSW_REG_ZERO(svpe, payload); 1612 mlxsw_reg_svpe_local_port_set(payload, local_port); 1613 mlxsw_reg_svpe_vp_en_set(payload, enable); 1614 } 1615 1616 /* SFMR - Switch FID Management Register 1617 * ------------------------------------- 1618 * Creates and configures FIDs. 1619 */ 1620 #define MLXSW_REG_SFMR_ID 0x201F 1621 #define MLXSW_REG_SFMR_LEN 0x18 1622 1623 MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN); 1624 1625 enum mlxsw_reg_sfmr_op { 1626 MLXSW_REG_SFMR_OP_CREATE_FID, 1627 MLXSW_REG_SFMR_OP_DESTROY_FID, 1628 }; 1629 1630 /* reg_sfmr_op 1631 * Operation. 1632 * 0 - Create or edit FID. 1633 * 1 - Destroy FID. 1634 * Access: WO 1635 */ 1636 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4); 1637 1638 /* reg_sfmr_fid 1639 * Filtering ID. 1640 * Access: Index 1641 */ 1642 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16); 1643 1644 /* reg_sfmr_fid_offset 1645 * FID offset. 1646 * Used to point into the flooding table selected by SFGC register if 1647 * the table is of type FID-Offset. Otherwise, this field is reserved. 1648 * Access: RW 1649 */ 1650 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16); 1651 1652 /* reg_sfmr_vtfp 1653 * Valid Tunnel Flood Pointer. 1654 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL. 1655 * Access: RW 1656 * 1657 * Note: Reserved for 802.1Q FIDs. 1658 */ 1659 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1); 1660 1661 /* reg_sfmr_nve_tunnel_flood_ptr 1662 * Underlay Flooding and BC Pointer. 1663 * Used as a pointer to the first entry of the group based link lists of 1664 * flooding or BC entries (for NVE tunnels). 1665 * Access: RW 1666 */ 1667 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24); 1668 1669 /* reg_sfmr_vv 1670 * VNI Valid. 1671 * If not set, then vni is reserved. 1672 * Access: RW 1673 * 1674 * Note: Reserved for 802.1Q FIDs. 1675 */ 1676 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1); 1677 1678 /* reg_sfmr_vni 1679 * Virtual Network Identifier. 1680 * Access: RW 1681 * 1682 * Note: A given VNI can only be assigned to one FID. 1683 */ 1684 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24); 1685 1686 static inline void mlxsw_reg_sfmr_pack(char *payload, 1687 enum mlxsw_reg_sfmr_op op, u16 fid, 1688 u16 fid_offset) 1689 { 1690 MLXSW_REG_ZERO(sfmr, payload); 1691 mlxsw_reg_sfmr_op_set(payload, op); 1692 mlxsw_reg_sfmr_fid_set(payload, fid); 1693 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset); 1694 mlxsw_reg_sfmr_vtfp_set(payload, false); 1695 mlxsw_reg_sfmr_vv_set(payload, false); 1696 } 1697 1698 /* SPVMLR - Switch Port VLAN MAC Learning Register 1699 * ----------------------------------------------- 1700 * Controls the switch MAC learning policy per {Port, VID}. 1701 */ 1702 #define MLXSW_REG_SPVMLR_ID 0x2020 1703 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */ 1704 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */ 1705 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255 1706 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \ 1707 MLXSW_REG_SPVMLR_REC_LEN * \ 1708 MLXSW_REG_SPVMLR_REC_MAX_COUNT) 1709 1710 MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN); 1711 1712 /* reg_spvmlr_local_port 1713 * Local ingress port. 1714 * Access: Index 1715 * 1716 * Note: CPU port is not supported. 1717 */ 1718 MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8); 1719 1720 /* reg_spvmlr_num_rec 1721 * Number of records to update. 1722 * Access: OP 1723 */ 1724 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8); 1725 1726 /* reg_spvmlr_rec_learn_enable 1727 * 0 - Disable learning for {Port, VID}. 1728 * 1 - Enable learning for {Port, VID}. 1729 * Access: RW 1730 */ 1731 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN, 1732 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1733 1734 /* reg_spvmlr_rec_vid 1735 * VLAN ID to be added/removed from port or for querying. 1736 * Access: Index 1737 */ 1738 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12, 1739 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1740 1741 static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port, 1742 u16 vid_begin, u16 vid_end, 1743 bool learn_enable) 1744 { 1745 int num_rec = vid_end - vid_begin + 1; 1746 int i; 1747 1748 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT); 1749 1750 MLXSW_REG_ZERO(spvmlr, payload); 1751 mlxsw_reg_spvmlr_local_port_set(payload, local_port); 1752 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec); 1753 1754 for (i = 0; i < num_rec; i++) { 1755 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable); 1756 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i); 1757 } 1758 } 1759 1760 /* PPBT - Policy-Engine Port Binding Table 1761 * --------------------------------------- 1762 * This register is used for configuration of the Port Binding Table. 1763 */ 1764 #define MLXSW_REG_PPBT_ID 0x3002 1765 #define MLXSW_REG_PPBT_LEN 0x14 1766 1767 MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN); 1768 1769 enum mlxsw_reg_pxbt_e { 1770 MLXSW_REG_PXBT_E_IACL, 1771 MLXSW_REG_PXBT_E_EACL, 1772 }; 1773 1774 /* reg_ppbt_e 1775 * Access: Index 1776 */ 1777 MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1); 1778 1779 enum mlxsw_reg_pxbt_op { 1780 MLXSW_REG_PXBT_OP_BIND, 1781 MLXSW_REG_PXBT_OP_UNBIND, 1782 }; 1783 1784 /* reg_ppbt_op 1785 * Access: RW 1786 */ 1787 MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3); 1788 1789 /* reg_ppbt_local_port 1790 * Local port. Not including CPU port. 1791 * Access: Index 1792 */ 1793 MLXSW_ITEM32(reg, ppbt, local_port, 0x00, 16, 8); 1794 1795 /* reg_ppbt_g 1796 * group - When set, the binding is of an ACL group. When cleared, 1797 * the binding is of an ACL. 1798 * Must be set to 1 for Spectrum. 1799 * Access: RW 1800 */ 1801 MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1); 1802 1803 /* reg_ppbt_acl_info 1804 * ACL/ACL group identifier. If the g bit is set, this field should hold 1805 * the acl_group_id, else it should hold the acl_id. 1806 * Access: RW 1807 */ 1808 MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16); 1809 1810 static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e, 1811 enum mlxsw_reg_pxbt_op op, 1812 u8 local_port, u16 acl_info) 1813 { 1814 MLXSW_REG_ZERO(ppbt, payload); 1815 mlxsw_reg_ppbt_e_set(payload, e); 1816 mlxsw_reg_ppbt_op_set(payload, op); 1817 mlxsw_reg_ppbt_local_port_set(payload, local_port); 1818 mlxsw_reg_ppbt_g_set(payload, true); 1819 mlxsw_reg_ppbt_acl_info_set(payload, acl_info); 1820 } 1821 1822 /* PACL - Policy-Engine ACL Register 1823 * --------------------------------- 1824 * This register is used for configuration of the ACL. 1825 */ 1826 #define MLXSW_REG_PACL_ID 0x3004 1827 #define MLXSW_REG_PACL_LEN 0x70 1828 1829 MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN); 1830 1831 /* reg_pacl_v 1832 * Valid. Setting the v bit makes the ACL valid. It should not be cleared 1833 * while the ACL is bounded to either a port, VLAN or ACL rule. 1834 * Access: RW 1835 */ 1836 MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1); 1837 1838 /* reg_pacl_acl_id 1839 * An identifier representing the ACL (managed by software) 1840 * Range 0 .. cap_max_acl_regions - 1 1841 * Access: Index 1842 */ 1843 MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16); 1844 1845 #define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16 1846 1847 /* reg_pacl_tcam_region_info 1848 * Opaque object that represents a TCAM region. 1849 * Obtained through PTAR register. 1850 * Access: RW 1851 */ 1852 MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30, 1853 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 1854 1855 static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id, 1856 bool valid, const char *tcam_region_info) 1857 { 1858 MLXSW_REG_ZERO(pacl, payload); 1859 mlxsw_reg_pacl_acl_id_set(payload, acl_id); 1860 mlxsw_reg_pacl_v_set(payload, valid); 1861 mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info); 1862 } 1863 1864 /* PAGT - Policy-Engine ACL Group Table 1865 * ------------------------------------ 1866 * This register is used for configuration of the ACL Group Table. 1867 */ 1868 #define MLXSW_REG_PAGT_ID 0x3005 1869 #define MLXSW_REG_PAGT_BASE_LEN 0x30 1870 #define MLXSW_REG_PAGT_ACL_LEN 4 1871 #define MLXSW_REG_PAGT_ACL_MAX_NUM 16 1872 #define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \ 1873 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN) 1874 1875 MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN); 1876 1877 /* reg_pagt_size 1878 * Number of ACLs in the group. 1879 * Size 0 invalidates a group. 1880 * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now) 1881 * Total number of ACLs in all groups must be lower or equal 1882 * to cap_max_acl_tot_groups 1883 * Note: a group which is binded must not be invalidated 1884 * Access: Index 1885 */ 1886 MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8); 1887 1888 /* reg_pagt_acl_group_id 1889 * An identifier (numbered from 0..cap_max_acl_groups-1) representing 1890 * the ACL Group identifier (managed by software). 1891 * Access: Index 1892 */ 1893 MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16); 1894 1895 /* reg_pagt_acl_id 1896 * ACL identifier 1897 * Access: RW 1898 */ 1899 MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false); 1900 1901 static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id) 1902 { 1903 MLXSW_REG_ZERO(pagt, payload); 1904 mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id); 1905 } 1906 1907 static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index, 1908 u16 acl_id) 1909 { 1910 u8 size = mlxsw_reg_pagt_size_get(payload); 1911 1912 if (index >= size) 1913 mlxsw_reg_pagt_size_set(payload, index + 1); 1914 mlxsw_reg_pagt_acl_id_set(payload, index, acl_id); 1915 } 1916 1917 /* PTAR - Policy-Engine TCAM Allocation Register 1918 * --------------------------------------------- 1919 * This register is used for allocation of regions in the TCAM. 1920 * Note: Query method is not supported on this register. 1921 */ 1922 #define MLXSW_REG_PTAR_ID 0x3006 1923 #define MLXSW_REG_PTAR_BASE_LEN 0x20 1924 #define MLXSW_REG_PTAR_KEY_ID_LEN 1 1925 #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16 1926 #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \ 1927 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN) 1928 1929 MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN); 1930 1931 enum mlxsw_reg_ptar_op { 1932 /* allocate a TCAM region */ 1933 MLXSW_REG_PTAR_OP_ALLOC, 1934 /* resize a TCAM region */ 1935 MLXSW_REG_PTAR_OP_RESIZE, 1936 /* deallocate TCAM region */ 1937 MLXSW_REG_PTAR_OP_FREE, 1938 /* test allocation */ 1939 MLXSW_REG_PTAR_OP_TEST, 1940 }; 1941 1942 /* reg_ptar_op 1943 * Access: OP 1944 */ 1945 MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4); 1946 1947 /* reg_ptar_action_set_type 1948 * Type of action set to be used on this region. 1949 * For Spectrum, this is always type 2 - "flexible" 1950 * Access: WO 1951 */ 1952 MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8); 1953 1954 /* reg_ptar_key_type 1955 * TCAM key type for the region. 1956 * For Spectrum, this is always type 0x50 - "FLEX_KEY" 1957 * Access: WO 1958 */ 1959 MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8); 1960 1961 /* reg_ptar_region_size 1962 * TCAM region size. When allocating/resizing this is the requested size, 1963 * the response is the actual size. Note that actual size may be 1964 * larger than requested. 1965 * Allowed range 1 .. cap_max_rules-1 1966 * Reserved during op deallocate. 1967 * Access: WO 1968 */ 1969 MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16); 1970 1971 /* reg_ptar_region_id 1972 * Region identifier 1973 * Range 0 .. cap_max_regions-1 1974 * Access: Index 1975 */ 1976 MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16); 1977 1978 /* reg_ptar_tcam_region_info 1979 * Opaque object that represents the TCAM region. 1980 * Returned when allocating a region. 1981 * Provided by software for ACL generation and region deallocation and resize. 1982 * Access: RW 1983 */ 1984 MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10, 1985 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 1986 1987 /* reg_ptar_flexible_key_id 1988 * Identifier of the Flexible Key. 1989 * Only valid if key_type == "FLEX_KEY" 1990 * The key size will be rounded up to one of the following values: 1991 * 9B, 18B, 36B, 54B. 1992 * This field is reserved for in resize operation. 1993 * Access: WO 1994 */ 1995 MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8, 1996 MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false); 1997 1998 static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op, 1999 u16 region_size, u16 region_id, 2000 const char *tcam_region_info) 2001 { 2002 MLXSW_REG_ZERO(ptar, payload); 2003 mlxsw_reg_ptar_op_set(payload, op); 2004 mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */ 2005 mlxsw_reg_ptar_key_type_set(payload, 0x50); /* "FLEX_KEY" */ 2006 mlxsw_reg_ptar_region_size_set(payload, region_size); 2007 mlxsw_reg_ptar_region_id_set(payload, region_id); 2008 mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info); 2009 } 2010 2011 static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index, 2012 u16 key_id) 2013 { 2014 mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id); 2015 } 2016 2017 static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info) 2018 { 2019 mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info); 2020 } 2021 2022 /* PPBS - Policy-Engine Policy Based Switching Register 2023 * ---------------------------------------------------- 2024 * This register retrieves and sets Policy Based Switching Table entries. 2025 */ 2026 #define MLXSW_REG_PPBS_ID 0x300C 2027 #define MLXSW_REG_PPBS_LEN 0x14 2028 2029 MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN); 2030 2031 /* reg_ppbs_pbs_ptr 2032 * Index into the PBS table. 2033 * For Spectrum, the index points to the KVD Linear. 2034 * Access: Index 2035 */ 2036 MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24); 2037 2038 /* reg_ppbs_system_port 2039 * Unique port identifier for the final destination of the packet. 2040 * Access: RW 2041 */ 2042 MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16); 2043 2044 static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr, 2045 u16 system_port) 2046 { 2047 MLXSW_REG_ZERO(ppbs, payload); 2048 mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr); 2049 mlxsw_reg_ppbs_system_port_set(payload, system_port); 2050 } 2051 2052 /* PRCR - Policy-Engine Rules Copy Register 2053 * ---------------------------------------- 2054 * This register is used for accessing rules within a TCAM region. 2055 */ 2056 #define MLXSW_REG_PRCR_ID 0x300D 2057 #define MLXSW_REG_PRCR_LEN 0x40 2058 2059 MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN); 2060 2061 enum mlxsw_reg_prcr_op { 2062 /* Move rules. Moves the rules from "tcam_region_info" starting 2063 * at offset "offset" to "dest_tcam_region_info" 2064 * at offset "dest_offset." 2065 */ 2066 MLXSW_REG_PRCR_OP_MOVE, 2067 /* Copy rules. Copies the rules from "tcam_region_info" starting 2068 * at offset "offset" to "dest_tcam_region_info" 2069 * at offset "dest_offset." 2070 */ 2071 MLXSW_REG_PRCR_OP_COPY, 2072 }; 2073 2074 /* reg_prcr_op 2075 * Access: OP 2076 */ 2077 MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4); 2078 2079 /* reg_prcr_offset 2080 * Offset within the source region to copy/move from. 2081 * Access: Index 2082 */ 2083 MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16); 2084 2085 /* reg_prcr_size 2086 * The number of rules to copy/move. 2087 * Access: WO 2088 */ 2089 MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16); 2090 2091 /* reg_prcr_tcam_region_info 2092 * Opaque object that represents the source TCAM region. 2093 * Access: Index 2094 */ 2095 MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10, 2096 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2097 2098 /* reg_prcr_dest_offset 2099 * Offset within the source region to copy/move to. 2100 * Access: Index 2101 */ 2102 MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16); 2103 2104 /* reg_prcr_dest_tcam_region_info 2105 * Opaque object that represents the destination TCAM region. 2106 * Access: Index 2107 */ 2108 MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30, 2109 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2110 2111 static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op, 2112 const char *src_tcam_region_info, 2113 u16 src_offset, 2114 const char *dest_tcam_region_info, 2115 u16 dest_offset, u16 size) 2116 { 2117 MLXSW_REG_ZERO(prcr, payload); 2118 mlxsw_reg_prcr_op_set(payload, op); 2119 mlxsw_reg_prcr_offset_set(payload, src_offset); 2120 mlxsw_reg_prcr_size_set(payload, size); 2121 mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload, 2122 src_tcam_region_info); 2123 mlxsw_reg_prcr_dest_offset_set(payload, dest_offset); 2124 mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload, 2125 dest_tcam_region_info); 2126 } 2127 2128 /* PEFA - Policy-Engine Extended Flexible Action Register 2129 * ------------------------------------------------------ 2130 * This register is used for accessing an extended flexible action entry 2131 * in the central KVD Linear Database. 2132 */ 2133 #define MLXSW_REG_PEFA_ID 0x300F 2134 #define MLXSW_REG_PEFA_LEN 0xB0 2135 2136 MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN); 2137 2138 /* reg_pefa_index 2139 * Index in the KVD Linear Centralized Database. 2140 * Access: Index 2141 */ 2142 MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24); 2143 2144 #define MLXSW_REG_PXXX_FLEX_ACTION_SET_LEN 0xA8 2145 2146 /* reg_pefa_flex_action_set 2147 * Action-set to perform when rule is matched. 2148 * Must be zero padded if action set is shorter. 2149 * Access: RW 2150 */ 2151 MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, 2152 MLXSW_REG_PXXX_FLEX_ACTION_SET_LEN); 2153 2154 static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, 2155 const char *flex_action_set) 2156 { 2157 MLXSW_REG_ZERO(pefa, payload); 2158 mlxsw_reg_pefa_index_set(payload, index); 2159 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload, flex_action_set); 2160 } 2161 2162 /* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2 2163 * ----------------------------------------------------- 2164 * This register is used for accessing rules within a TCAM region. 2165 * It is a new version of PTCE in order to support wider key, 2166 * mask and action within a TCAM region. This register is not supported 2167 * by SwitchX and SwitchX-2. 2168 */ 2169 #define MLXSW_REG_PTCE2_ID 0x3017 2170 #define MLXSW_REG_PTCE2_LEN 0x1D8 2171 2172 MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN); 2173 2174 /* reg_ptce2_v 2175 * Valid. 2176 * Access: RW 2177 */ 2178 MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1); 2179 2180 /* reg_ptce2_a 2181 * Activity. Set if a packet lookup has hit on the specific entry. 2182 * To clear the "a" bit, use "clear activity" op or "clear on read" op. 2183 * Access: RO 2184 */ 2185 MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1); 2186 2187 enum mlxsw_reg_ptce2_op { 2188 /* Read operation. */ 2189 MLXSW_REG_PTCE2_OP_QUERY_READ = 0, 2190 /* clear on read operation. Used to read entry 2191 * and clear Activity bit. 2192 */ 2193 MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1, 2194 /* Write operation. Used to write a new entry to the table. 2195 * All R/W fields are relevant for new entry. Activity bit is set 2196 * for new entries - Note write with v = 0 will delete the entry. 2197 */ 2198 MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0, 2199 /* Update action. Only action set will be updated. */ 2200 MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1, 2201 /* Clear activity. A bit is cleared for the entry. */ 2202 MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2, 2203 }; 2204 2205 /* reg_ptce2_op 2206 * Access: OP 2207 */ 2208 MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3); 2209 2210 /* reg_ptce2_offset 2211 * Access: Index 2212 */ 2213 MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16); 2214 2215 /* reg_ptce2_tcam_region_info 2216 * Opaque object that represents the TCAM region. 2217 * Access: Index 2218 */ 2219 MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10, 2220 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2221 2222 #define MLXSW_REG_PTCE2_FLEX_KEY_BLOCKS_LEN 96 2223 2224 /* reg_ptce2_flex_key_blocks 2225 * ACL Key. 2226 * Access: RW 2227 */ 2228 MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20, 2229 MLXSW_REG_PTCE2_FLEX_KEY_BLOCKS_LEN); 2230 2231 /* reg_ptce2_mask 2232 * mask- in the same size as key. A bit that is set directs the TCAM 2233 * to compare the corresponding bit in key. A bit that is clear directs 2234 * the TCAM to ignore the corresponding bit in key. 2235 * Access: RW 2236 */ 2237 MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80, 2238 MLXSW_REG_PTCE2_FLEX_KEY_BLOCKS_LEN); 2239 2240 /* reg_ptce2_flex_action_set 2241 * ACL action set. 2242 * Access: RW 2243 */ 2244 MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0, 2245 MLXSW_REG_PXXX_FLEX_ACTION_SET_LEN); 2246 2247 static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid, 2248 enum mlxsw_reg_ptce2_op op, 2249 const char *tcam_region_info, 2250 u16 offset) 2251 { 2252 MLXSW_REG_ZERO(ptce2, payload); 2253 mlxsw_reg_ptce2_v_set(payload, valid); 2254 mlxsw_reg_ptce2_op_set(payload, op); 2255 mlxsw_reg_ptce2_offset_set(payload, offset); 2256 mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info); 2257 } 2258 2259 /* QPCR - QoS Policer Configuration Register 2260 * ----------------------------------------- 2261 * The QPCR register is used to create policers - that limit 2262 * the rate of bytes or packets via some trap group. 2263 */ 2264 #define MLXSW_REG_QPCR_ID 0x4004 2265 #define MLXSW_REG_QPCR_LEN 0x28 2266 2267 MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN); 2268 2269 enum mlxsw_reg_qpcr_g { 2270 MLXSW_REG_QPCR_G_GLOBAL = 2, 2271 MLXSW_REG_QPCR_G_STORM_CONTROL = 3, 2272 }; 2273 2274 /* reg_qpcr_g 2275 * The policer type. 2276 * Access: Index 2277 */ 2278 MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2); 2279 2280 /* reg_qpcr_pid 2281 * Policer ID. 2282 * Access: Index 2283 */ 2284 MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14); 2285 2286 /* reg_qpcr_color_aware 2287 * Is the policer aware of colors. 2288 * Must be 0 (unaware) for cpu port. 2289 * Access: RW for unbounded policer. RO for bounded policer. 2290 */ 2291 MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1); 2292 2293 /* reg_qpcr_bytes 2294 * Is policer limit is for bytes per sec or packets per sec. 2295 * 0 - packets 2296 * 1 - bytes 2297 * Access: RW for unbounded policer. RO for bounded policer. 2298 */ 2299 MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1); 2300 2301 enum mlxsw_reg_qpcr_ir_units { 2302 MLXSW_REG_QPCR_IR_UNITS_M, 2303 MLXSW_REG_QPCR_IR_UNITS_K, 2304 }; 2305 2306 /* reg_qpcr_ir_units 2307 * Policer's units for cir and eir fields (for bytes limits only) 2308 * 1 - 10^3 2309 * 0 - 10^6 2310 * Access: OP 2311 */ 2312 MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1); 2313 2314 enum mlxsw_reg_qpcr_rate_type { 2315 MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1, 2316 MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2, 2317 }; 2318 2319 /* reg_qpcr_rate_type 2320 * Policer can have one limit (single rate) or 2 limits with specific operation 2321 * for packets that exceed the lower rate but not the upper one. 2322 * (For cpu port must be single rate) 2323 * Access: RW for unbounded policer. RO for bounded policer. 2324 */ 2325 MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2); 2326 2327 /* reg_qpc_cbs 2328 * Policer's committed burst size. 2329 * The policer is working with time slices of 50 nano sec. By default every 2330 * slice is granted the proportionate share of the committed rate. If we want to 2331 * allow a slice to exceed that share (while still keeping the rate per sec) we 2332 * can allow burst. The burst size is between the default proportionate share 2333 * (and no lower than 8) to 32Gb. (Even though giving a number higher than the 2334 * committed rate will result in exceeding the rate). The burst size must be a 2335 * log of 2 and will be determined by 2^cbs. 2336 * Access: RW 2337 */ 2338 MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6); 2339 2340 /* reg_qpcr_cir 2341 * Policer's committed rate. 2342 * The rate used for sungle rate, the lower rate for double rate. 2343 * For bytes limits, the rate will be this value * the unit from ir_units. 2344 * (Resolution error is up to 1%). 2345 * Access: RW 2346 */ 2347 MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32); 2348 2349 /* reg_qpcr_eir 2350 * Policer's exceed rate. 2351 * The higher rate for double rate, reserved for single rate. 2352 * Lower rate for double rate policer. 2353 * For bytes limits, the rate will be this value * the unit from ir_units. 2354 * (Resolution error is up to 1%). 2355 * Access: RW 2356 */ 2357 MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32); 2358 2359 #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2 2360 2361 /* reg_qpcr_exceed_action. 2362 * What to do with packets between the 2 limits for double rate. 2363 * Access: RW for unbounded policer. RO for bounded policer. 2364 */ 2365 MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4); 2366 2367 enum mlxsw_reg_qpcr_action { 2368 /* Discard */ 2369 MLXSW_REG_QPCR_ACTION_DISCARD = 1, 2370 /* Forward and set color to red. 2371 * If the packet is intended to cpu port, it will be dropped. 2372 */ 2373 MLXSW_REG_QPCR_ACTION_FORWARD = 2, 2374 }; 2375 2376 /* reg_qpcr_violate_action 2377 * What to do with packets that cross the cir limit (for single rate) or the eir 2378 * limit (for double rate). 2379 * Access: RW for unbounded policer. RO for bounded policer. 2380 */ 2381 MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4); 2382 2383 static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid, 2384 enum mlxsw_reg_qpcr_ir_units ir_units, 2385 bool bytes, u32 cir, u16 cbs) 2386 { 2387 MLXSW_REG_ZERO(qpcr, payload); 2388 mlxsw_reg_qpcr_pid_set(payload, pid); 2389 mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL); 2390 mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE); 2391 mlxsw_reg_qpcr_violate_action_set(payload, 2392 MLXSW_REG_QPCR_ACTION_DISCARD); 2393 mlxsw_reg_qpcr_cir_set(payload, cir); 2394 mlxsw_reg_qpcr_ir_units_set(payload, ir_units); 2395 mlxsw_reg_qpcr_bytes_set(payload, bytes); 2396 mlxsw_reg_qpcr_cbs_set(payload, cbs); 2397 } 2398 2399 /* QTCT - QoS Switch Traffic Class Table 2400 * ------------------------------------- 2401 * Configures the mapping between the packet switch priority and the 2402 * traffic class on the transmit port. 2403 */ 2404 #define MLXSW_REG_QTCT_ID 0x400A 2405 #define MLXSW_REG_QTCT_LEN 0x08 2406 2407 MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN); 2408 2409 /* reg_qtct_local_port 2410 * Local port number. 2411 * Access: Index 2412 * 2413 * Note: CPU port is not supported. 2414 */ 2415 MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8); 2416 2417 /* reg_qtct_sub_port 2418 * Virtual port within the physical port. 2419 * Should be set to 0 when virtual ports are not enabled on the port. 2420 * Access: Index 2421 */ 2422 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8); 2423 2424 /* reg_qtct_switch_prio 2425 * Switch priority. 2426 * Access: Index 2427 */ 2428 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4); 2429 2430 /* reg_qtct_tclass 2431 * Traffic class. 2432 * Default values: 2433 * switch_prio 0 : tclass 1 2434 * switch_prio 1 : tclass 0 2435 * switch_prio i : tclass i, for i > 1 2436 * Access: RW 2437 */ 2438 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4); 2439 2440 static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port, 2441 u8 switch_prio, u8 tclass) 2442 { 2443 MLXSW_REG_ZERO(qtct, payload); 2444 mlxsw_reg_qtct_local_port_set(payload, local_port); 2445 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio); 2446 mlxsw_reg_qtct_tclass_set(payload, tclass); 2447 } 2448 2449 /* QEEC - QoS ETS Element Configuration Register 2450 * --------------------------------------------- 2451 * Configures the ETS elements. 2452 */ 2453 #define MLXSW_REG_QEEC_ID 0x400D 2454 #define MLXSW_REG_QEEC_LEN 0x1C 2455 2456 MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN); 2457 2458 /* reg_qeec_local_port 2459 * Local port number. 2460 * Access: Index 2461 * 2462 * Note: CPU port is supported. 2463 */ 2464 MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8); 2465 2466 enum mlxsw_reg_qeec_hr { 2467 MLXSW_REG_QEEC_HIERARCY_PORT, 2468 MLXSW_REG_QEEC_HIERARCY_GROUP, 2469 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, 2470 MLXSW_REG_QEEC_HIERARCY_TC, 2471 }; 2472 2473 /* reg_qeec_element_hierarchy 2474 * 0 - Port 2475 * 1 - Group 2476 * 2 - Subgroup 2477 * 3 - Traffic Class 2478 * Access: Index 2479 */ 2480 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4); 2481 2482 /* reg_qeec_element_index 2483 * The index of the element in the hierarchy. 2484 * Access: Index 2485 */ 2486 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8); 2487 2488 /* reg_qeec_next_element_index 2489 * The index of the next (lower) element in the hierarchy. 2490 * Access: RW 2491 * 2492 * Note: Reserved for element_hierarchy 0. 2493 */ 2494 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8); 2495 2496 enum { 2497 MLXSW_REG_QEEC_BYTES_MODE, 2498 MLXSW_REG_QEEC_PACKETS_MODE, 2499 }; 2500 2501 /* reg_qeec_pb 2502 * Packets or bytes mode. 2503 * 0 - Bytes mode 2504 * 1 - Packets mode 2505 * Access: RW 2506 * 2507 * Note: Used for max shaper configuration. For Spectrum, packets mode 2508 * is supported only for traffic classes of CPU port. 2509 */ 2510 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1); 2511 2512 /* reg_qeec_mase 2513 * Max shaper configuration enable. Enables configuration of the max 2514 * shaper on this ETS element. 2515 * 0 - Disable 2516 * 1 - Enable 2517 * Access: RW 2518 */ 2519 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1); 2520 2521 /* A large max rate will disable the max shaper. */ 2522 #define MLXSW_REG_QEEC_MAS_DIS 200000000 /* Kbps */ 2523 2524 /* reg_qeec_max_shaper_rate 2525 * Max shaper information rate. 2526 * For CPU port, can only be configured for port hierarchy. 2527 * When in bytes mode, value is specified in units of 1000bps. 2528 * Access: RW 2529 */ 2530 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 28); 2531 2532 /* reg_qeec_de 2533 * DWRR configuration enable. Enables configuration of the dwrr and 2534 * dwrr_weight. 2535 * 0 - Disable 2536 * 1 - Enable 2537 * Access: RW 2538 */ 2539 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1); 2540 2541 /* reg_qeec_dwrr 2542 * Transmission selection algorithm to use on the link going down from 2543 * the ETS element. 2544 * 0 - Strict priority 2545 * 1 - DWRR 2546 * Access: RW 2547 */ 2548 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1); 2549 2550 /* reg_qeec_dwrr_weight 2551 * DWRR weight on the link going down from the ETS element. The 2552 * percentage of bandwidth guaranteed to an ETS element within 2553 * its hierarchy. The sum of all weights across all ETS elements 2554 * within one hierarchy should be equal to 100. Reserved when 2555 * transmission selection algorithm is strict priority. 2556 * Access: RW 2557 */ 2558 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8); 2559 2560 static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port, 2561 enum mlxsw_reg_qeec_hr hr, u8 index, 2562 u8 next_index) 2563 { 2564 MLXSW_REG_ZERO(qeec, payload); 2565 mlxsw_reg_qeec_local_port_set(payload, local_port); 2566 mlxsw_reg_qeec_element_hierarchy_set(payload, hr); 2567 mlxsw_reg_qeec_element_index_set(payload, index); 2568 mlxsw_reg_qeec_next_element_index_set(payload, next_index); 2569 } 2570 2571 /* PMLP - Ports Module to Local Port Register 2572 * ------------------------------------------ 2573 * Configures the assignment of modules to local ports. 2574 */ 2575 #define MLXSW_REG_PMLP_ID 0x5002 2576 #define MLXSW_REG_PMLP_LEN 0x40 2577 2578 MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN); 2579 2580 /* reg_pmlp_rxtx 2581 * 0 - Tx value is used for both Tx and Rx. 2582 * 1 - Rx value is taken from a separte field. 2583 * Access: RW 2584 */ 2585 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1); 2586 2587 /* reg_pmlp_local_port 2588 * Local port number. 2589 * Access: Index 2590 */ 2591 MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8); 2592 2593 /* reg_pmlp_width 2594 * 0 - Unmap local port. 2595 * 1 - Lane 0 is used. 2596 * 2 - Lanes 0 and 1 are used. 2597 * 4 - Lanes 0, 1, 2 and 3 are used. 2598 * Access: RW 2599 */ 2600 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8); 2601 2602 /* reg_pmlp_module 2603 * Module number. 2604 * Access: RW 2605 */ 2606 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false); 2607 2608 /* reg_pmlp_tx_lane 2609 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well. 2610 * Access: RW 2611 */ 2612 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 0x00, false); 2613 2614 /* reg_pmlp_rx_lane 2615 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is 2616 * equal to Tx lane. 2617 * Access: RW 2618 */ 2619 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 0x00, false); 2620 2621 static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port) 2622 { 2623 MLXSW_REG_ZERO(pmlp, payload); 2624 mlxsw_reg_pmlp_local_port_set(payload, local_port); 2625 } 2626 2627 /* PMTU - Port MTU Register 2628 * ------------------------ 2629 * Configures and reports the port MTU. 2630 */ 2631 #define MLXSW_REG_PMTU_ID 0x5003 2632 #define MLXSW_REG_PMTU_LEN 0x10 2633 2634 MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN); 2635 2636 /* reg_pmtu_local_port 2637 * Local port number. 2638 * Access: Index 2639 */ 2640 MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8); 2641 2642 /* reg_pmtu_max_mtu 2643 * Maximum MTU. 2644 * When port type (e.g. Ethernet) is configured, the relevant MTU is 2645 * reported, otherwise the minimum between the max_mtu of the different 2646 * types is reported. 2647 * Access: RO 2648 */ 2649 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16); 2650 2651 /* reg_pmtu_admin_mtu 2652 * MTU value to set port to. Must be smaller or equal to max_mtu. 2653 * Note: If port type is Infiniband, then port must be disabled, when its 2654 * MTU is set. 2655 * Access: RW 2656 */ 2657 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16); 2658 2659 /* reg_pmtu_oper_mtu 2660 * The actual MTU configured on the port. Packets exceeding this size 2661 * will be dropped. 2662 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband 2663 * oper_mtu might be smaller than admin_mtu. 2664 * Access: RO 2665 */ 2666 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16); 2667 2668 static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port, 2669 u16 new_mtu) 2670 { 2671 MLXSW_REG_ZERO(pmtu, payload); 2672 mlxsw_reg_pmtu_local_port_set(payload, local_port); 2673 mlxsw_reg_pmtu_max_mtu_set(payload, 0); 2674 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu); 2675 mlxsw_reg_pmtu_oper_mtu_set(payload, 0); 2676 } 2677 2678 /* PTYS - Port Type and Speed Register 2679 * ----------------------------------- 2680 * Configures and reports the port speed type. 2681 * 2682 * Note: When set while the link is up, the changes will not take effect 2683 * until the port transitions from down to up state. 2684 */ 2685 #define MLXSW_REG_PTYS_ID 0x5004 2686 #define MLXSW_REG_PTYS_LEN 0x40 2687 2688 MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN); 2689 2690 /* reg_ptys_local_port 2691 * Local port number. 2692 * Access: Index 2693 */ 2694 MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8); 2695 2696 #define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0) 2697 #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2) 2698 2699 /* reg_ptys_proto_mask 2700 * Protocol mask. Indicates which protocol is used. 2701 * 0 - Infiniband. 2702 * 1 - Fibre Channel. 2703 * 2 - Ethernet. 2704 * Access: Index 2705 */ 2706 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3); 2707 2708 enum { 2709 MLXSW_REG_PTYS_AN_STATUS_NA, 2710 MLXSW_REG_PTYS_AN_STATUS_OK, 2711 MLXSW_REG_PTYS_AN_STATUS_FAIL, 2712 }; 2713 2714 /* reg_ptys_an_status 2715 * Autonegotiation status. 2716 * Access: RO 2717 */ 2718 MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4); 2719 2720 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0) 2721 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1) 2722 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2) 2723 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3) 2724 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4) 2725 #define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2 BIT(5) 2726 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6) 2727 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7) 2728 #define MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4 BIT(8) 2729 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12) 2730 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13) 2731 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14) 2732 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15) 2733 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16) 2734 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18) 2735 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19) 2736 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20) 2737 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21) 2738 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22) 2739 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23) 2740 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX BIT(24) 2741 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(25) 2742 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T BIT(26) 2743 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27) 2744 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28) 2745 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29) 2746 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30) 2747 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31) 2748 2749 /* reg_ptys_eth_proto_cap 2750 * Ethernet port supported speeds and protocols. 2751 * Access: RO 2752 */ 2753 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32); 2754 2755 /* reg_ptys_ib_link_width_cap 2756 * IB port supported widths. 2757 * Access: RO 2758 */ 2759 MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16); 2760 2761 #define MLXSW_REG_PTYS_IB_SPEED_SDR BIT(0) 2762 #define MLXSW_REG_PTYS_IB_SPEED_DDR BIT(1) 2763 #define MLXSW_REG_PTYS_IB_SPEED_QDR BIT(2) 2764 #define MLXSW_REG_PTYS_IB_SPEED_FDR10 BIT(3) 2765 #define MLXSW_REG_PTYS_IB_SPEED_FDR BIT(4) 2766 #define MLXSW_REG_PTYS_IB_SPEED_EDR BIT(5) 2767 2768 /* reg_ptys_ib_proto_cap 2769 * IB port supported speeds and protocols. 2770 * Access: RO 2771 */ 2772 MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16); 2773 2774 /* reg_ptys_eth_proto_admin 2775 * Speed and protocol to set port to. 2776 * Access: RW 2777 */ 2778 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32); 2779 2780 /* reg_ptys_ib_link_width_admin 2781 * IB width to set port to. 2782 * Access: RW 2783 */ 2784 MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16); 2785 2786 /* reg_ptys_ib_proto_admin 2787 * IB speeds and protocols to set port to. 2788 * Access: RW 2789 */ 2790 MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16); 2791 2792 /* reg_ptys_eth_proto_oper 2793 * The current speed and protocol configured for the port. 2794 * Access: RO 2795 */ 2796 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32); 2797 2798 /* reg_ptys_ib_link_width_oper 2799 * The current IB width to set port to. 2800 * Access: RO 2801 */ 2802 MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16); 2803 2804 /* reg_ptys_ib_proto_oper 2805 * The current IB speed and protocol. 2806 * Access: RO 2807 */ 2808 MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16); 2809 2810 /* reg_ptys_eth_proto_lp_advertise 2811 * The protocols that were advertised by the link partner during 2812 * autonegotiation. 2813 * Access: RO 2814 */ 2815 MLXSW_ITEM32(reg, ptys, eth_proto_lp_advertise, 0x30, 0, 32); 2816 2817 static inline void mlxsw_reg_ptys_eth_pack(char *payload, u8 local_port, 2818 u32 proto_admin) 2819 { 2820 MLXSW_REG_ZERO(ptys, payload); 2821 mlxsw_reg_ptys_local_port_set(payload, local_port); 2822 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 2823 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin); 2824 } 2825 2826 static inline void mlxsw_reg_ptys_eth_unpack(char *payload, 2827 u32 *p_eth_proto_cap, 2828 u32 *p_eth_proto_adm, 2829 u32 *p_eth_proto_oper) 2830 { 2831 if (p_eth_proto_cap) 2832 *p_eth_proto_cap = mlxsw_reg_ptys_eth_proto_cap_get(payload); 2833 if (p_eth_proto_adm) 2834 *p_eth_proto_adm = mlxsw_reg_ptys_eth_proto_admin_get(payload); 2835 if (p_eth_proto_oper) 2836 *p_eth_proto_oper = mlxsw_reg_ptys_eth_proto_oper_get(payload); 2837 } 2838 2839 static inline void mlxsw_reg_ptys_ib_pack(char *payload, u8 local_port, 2840 u16 proto_admin, u16 link_width) 2841 { 2842 MLXSW_REG_ZERO(ptys, payload); 2843 mlxsw_reg_ptys_local_port_set(payload, local_port); 2844 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB); 2845 mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin); 2846 mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width); 2847 } 2848 2849 static inline void mlxsw_reg_ptys_ib_unpack(char *payload, u16 *p_ib_proto_cap, 2850 u16 *p_ib_link_width_cap, 2851 u16 *p_ib_proto_oper, 2852 u16 *p_ib_link_width_oper) 2853 { 2854 if (p_ib_proto_cap) 2855 *p_ib_proto_cap = mlxsw_reg_ptys_ib_proto_cap_get(payload); 2856 if (p_ib_link_width_cap) 2857 *p_ib_link_width_cap = 2858 mlxsw_reg_ptys_ib_link_width_cap_get(payload); 2859 if (p_ib_proto_oper) 2860 *p_ib_proto_oper = mlxsw_reg_ptys_ib_proto_oper_get(payload); 2861 if (p_ib_link_width_oper) 2862 *p_ib_link_width_oper = 2863 mlxsw_reg_ptys_ib_link_width_oper_get(payload); 2864 } 2865 2866 /* PPAD - Port Physical Address Register 2867 * ------------------------------------- 2868 * The PPAD register configures the per port physical MAC address. 2869 */ 2870 #define MLXSW_REG_PPAD_ID 0x5005 2871 #define MLXSW_REG_PPAD_LEN 0x10 2872 2873 MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN); 2874 2875 /* reg_ppad_single_base_mac 2876 * 0: base_mac, local port should be 0 and mac[7:0] is 2877 * reserved. HW will set incremental 2878 * 1: single_mac - mac of the local_port 2879 * Access: RW 2880 */ 2881 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1); 2882 2883 /* reg_ppad_local_port 2884 * port number, if single_base_mac = 0 then local_port is reserved 2885 * Access: RW 2886 */ 2887 MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8); 2888 2889 /* reg_ppad_mac 2890 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved. 2891 * If single_base_mac = 1 - the per port MAC address 2892 * Access: RW 2893 */ 2894 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6); 2895 2896 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac, 2897 u8 local_port) 2898 { 2899 MLXSW_REG_ZERO(ppad, payload); 2900 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac); 2901 mlxsw_reg_ppad_local_port_set(payload, local_port); 2902 } 2903 2904 /* PAOS - Ports Administrative and Operational Status Register 2905 * ----------------------------------------------------------- 2906 * Configures and retrieves per port administrative and operational status. 2907 */ 2908 #define MLXSW_REG_PAOS_ID 0x5006 2909 #define MLXSW_REG_PAOS_LEN 0x10 2910 2911 MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN); 2912 2913 /* reg_paos_swid 2914 * Switch partition ID with which to associate the port. 2915 * Note: while external ports uses unique local port numbers (and thus swid is 2916 * redundant), router ports use the same local port number where swid is the 2917 * only indication for the relevant port. 2918 * Access: Index 2919 */ 2920 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8); 2921 2922 /* reg_paos_local_port 2923 * Local port number. 2924 * Access: Index 2925 */ 2926 MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8); 2927 2928 /* reg_paos_admin_status 2929 * Port administrative state (the desired state of the port): 2930 * 1 - Up. 2931 * 2 - Down. 2932 * 3 - Up once. This means that in case of link failure, the port won't go 2933 * into polling mode, but will wait to be re-enabled by software. 2934 * 4 - Disabled by system. Can only be set by hardware. 2935 * Access: RW 2936 */ 2937 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4); 2938 2939 /* reg_paos_oper_status 2940 * Port operational state (the current state): 2941 * 1 - Up. 2942 * 2 - Down. 2943 * 3 - Down by port failure. This means that the device will not let the 2944 * port up again until explicitly specified by software. 2945 * Access: RO 2946 */ 2947 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4); 2948 2949 /* reg_paos_ase 2950 * Admin state update enabled. 2951 * Access: WO 2952 */ 2953 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1); 2954 2955 /* reg_paos_ee 2956 * Event update enable. If this bit is set, event generation will be 2957 * updated based on the e field. 2958 * Access: WO 2959 */ 2960 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1); 2961 2962 /* reg_paos_e 2963 * Event generation on operational state change: 2964 * 0 - Do not generate event. 2965 * 1 - Generate Event. 2966 * 2 - Generate Single Event. 2967 * Access: RW 2968 */ 2969 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2); 2970 2971 static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port, 2972 enum mlxsw_port_admin_status status) 2973 { 2974 MLXSW_REG_ZERO(paos, payload); 2975 mlxsw_reg_paos_swid_set(payload, 0); 2976 mlxsw_reg_paos_local_port_set(payload, local_port); 2977 mlxsw_reg_paos_admin_status_set(payload, status); 2978 mlxsw_reg_paos_oper_status_set(payload, 0); 2979 mlxsw_reg_paos_ase_set(payload, 1); 2980 mlxsw_reg_paos_ee_set(payload, 1); 2981 mlxsw_reg_paos_e_set(payload, 1); 2982 } 2983 2984 /* PFCC - Ports Flow Control Configuration Register 2985 * ------------------------------------------------ 2986 * Configures and retrieves the per port flow control configuration. 2987 */ 2988 #define MLXSW_REG_PFCC_ID 0x5007 2989 #define MLXSW_REG_PFCC_LEN 0x20 2990 2991 MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN); 2992 2993 /* reg_pfcc_local_port 2994 * Local port number. 2995 * Access: Index 2996 */ 2997 MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8); 2998 2999 /* reg_pfcc_pnat 3000 * Port number access type. Determines the way local_port is interpreted: 3001 * 0 - Local port number. 3002 * 1 - IB / label port number. 3003 * Access: Index 3004 */ 3005 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2); 3006 3007 /* reg_pfcc_shl_cap 3008 * Send to higher layers capabilities: 3009 * 0 - No capability of sending Pause and PFC frames to higher layers. 3010 * 1 - Device has capability of sending Pause and PFC frames to higher 3011 * layers. 3012 * Access: RO 3013 */ 3014 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1); 3015 3016 /* reg_pfcc_shl_opr 3017 * Send to higher layers operation: 3018 * 0 - Pause and PFC frames are handled by the port (default). 3019 * 1 - Pause and PFC frames are handled by the port and also sent to 3020 * higher layers. Only valid if shl_cap = 1. 3021 * Access: RW 3022 */ 3023 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1); 3024 3025 /* reg_pfcc_ppan 3026 * Pause policy auto negotiation. 3027 * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx. 3028 * 1 - Enabled. When auto-negotiation is performed, set the Pause policy 3029 * based on the auto-negotiation resolution. 3030 * Access: RW 3031 * 3032 * Note: The auto-negotiation advertisement is set according to pptx and 3033 * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0. 3034 */ 3035 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4); 3036 3037 /* reg_pfcc_prio_mask_tx 3038 * Bit per priority indicating if Tx flow control policy should be 3039 * updated based on bit pfctx. 3040 * Access: WO 3041 */ 3042 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8); 3043 3044 /* reg_pfcc_prio_mask_rx 3045 * Bit per priority indicating if Rx flow control policy should be 3046 * updated based on bit pfcrx. 3047 * Access: WO 3048 */ 3049 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8); 3050 3051 /* reg_pfcc_pptx 3052 * Admin Pause policy on Tx. 3053 * 0 - Never generate Pause frames (default). 3054 * 1 - Generate Pause frames according to Rx buffer threshold. 3055 * Access: RW 3056 */ 3057 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1); 3058 3059 /* reg_pfcc_aptx 3060 * Active (operational) Pause policy on Tx. 3061 * 0 - Never generate Pause frames. 3062 * 1 - Generate Pause frames according to Rx buffer threshold. 3063 * Access: RO 3064 */ 3065 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1); 3066 3067 /* reg_pfcc_pfctx 3068 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask: 3069 * 0 - Never generate priority Pause frames on the specified priority 3070 * (default). 3071 * 1 - Generate priority Pause frames according to Rx buffer threshold on 3072 * the specified priority. 3073 * Access: RW 3074 * 3075 * Note: pfctx and pptx must be mutually exclusive. 3076 */ 3077 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8); 3078 3079 /* reg_pfcc_pprx 3080 * Admin Pause policy on Rx. 3081 * 0 - Ignore received Pause frames (default). 3082 * 1 - Respect received Pause frames. 3083 * Access: RW 3084 */ 3085 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1); 3086 3087 /* reg_pfcc_aprx 3088 * Active (operational) Pause policy on Rx. 3089 * 0 - Ignore received Pause frames. 3090 * 1 - Respect received Pause frames. 3091 * Access: RO 3092 */ 3093 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1); 3094 3095 /* reg_pfcc_pfcrx 3096 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask: 3097 * 0 - Ignore incoming priority Pause frames on the specified priority 3098 * (default). 3099 * 1 - Respect incoming priority Pause frames on the specified priority. 3100 * Access: RW 3101 */ 3102 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8); 3103 3104 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF 3105 3106 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en) 3107 { 3108 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 3109 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 3110 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en); 3111 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en); 3112 } 3113 3114 static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port) 3115 { 3116 MLXSW_REG_ZERO(pfcc, payload); 3117 mlxsw_reg_pfcc_local_port_set(payload, local_port); 3118 } 3119 3120 /* PPCNT - Ports Performance Counters Register 3121 * ------------------------------------------- 3122 * The PPCNT register retrieves per port performance counters. 3123 */ 3124 #define MLXSW_REG_PPCNT_ID 0x5008 3125 #define MLXSW_REG_PPCNT_LEN 0x100 3126 3127 MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN); 3128 3129 /* reg_ppcnt_swid 3130 * For HCA: must be always 0. 3131 * Switch partition ID to associate port with. 3132 * Switch partitions are numbered from 0 to 7 inclusively. 3133 * Switch partition 254 indicates stacking ports. 3134 * Switch partition 255 indicates all switch partitions. 3135 * Only valid on Set() operation with local_port=255. 3136 * Access: Index 3137 */ 3138 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8); 3139 3140 /* reg_ppcnt_local_port 3141 * Local port number. 3142 * 255 indicates all ports on the device, and is only allowed 3143 * for Set() operation. 3144 * Access: Index 3145 */ 3146 MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8); 3147 3148 /* reg_ppcnt_pnat 3149 * Port number access type: 3150 * 0 - Local port number 3151 * 1 - IB port number 3152 * Access: Index 3153 */ 3154 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2); 3155 3156 enum mlxsw_reg_ppcnt_grp { 3157 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0, 3158 MLXSW_REG_PPCNT_PRIO_CNT = 0x10, 3159 MLXSW_REG_PPCNT_TC_CNT = 0x11, 3160 }; 3161 3162 /* reg_ppcnt_grp 3163 * Performance counter group. 3164 * Group 63 indicates all groups. Only valid on Set() operation with 3165 * clr bit set. 3166 * 0x0: IEEE 802.3 Counters 3167 * 0x1: RFC 2863 Counters 3168 * 0x2: RFC 2819 Counters 3169 * 0x3: RFC 3635 Counters 3170 * 0x5: Ethernet Extended Counters 3171 * 0x8: Link Level Retransmission Counters 3172 * 0x10: Per Priority Counters 3173 * 0x11: Per Traffic Class Counters 3174 * 0x12: Physical Layer Counters 3175 * Access: Index 3176 */ 3177 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6); 3178 3179 /* reg_ppcnt_clr 3180 * Clear counters. Setting the clr bit will reset the counter value 3181 * for all counters in the counter group. This bit can be set 3182 * for both Set() and Get() operation. 3183 * Access: OP 3184 */ 3185 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1); 3186 3187 /* reg_ppcnt_prio_tc 3188 * Priority for counter set that support per priority, valid values: 0-7. 3189 * Traffic class for counter set that support per traffic class, 3190 * valid values: 0- cap_max_tclass-1 . 3191 * For HCA: cap_max_tclass is always 8. 3192 * Otherwise must be 0. 3193 * Access: Index 3194 */ 3195 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5); 3196 3197 /* Ethernet IEEE 802.3 Counter Group */ 3198 3199 /* reg_ppcnt_a_frames_transmitted_ok 3200 * Access: RO 3201 */ 3202 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok, 3203 0x08 + 0x00, 0, 64); 3204 3205 /* reg_ppcnt_a_frames_received_ok 3206 * Access: RO 3207 */ 3208 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok, 3209 0x08 + 0x08, 0, 64); 3210 3211 /* reg_ppcnt_a_frame_check_sequence_errors 3212 * Access: RO 3213 */ 3214 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors, 3215 0x08 + 0x10, 0, 64); 3216 3217 /* reg_ppcnt_a_alignment_errors 3218 * Access: RO 3219 */ 3220 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors, 3221 0x08 + 0x18, 0, 64); 3222 3223 /* reg_ppcnt_a_octets_transmitted_ok 3224 * Access: RO 3225 */ 3226 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok, 3227 0x08 + 0x20, 0, 64); 3228 3229 /* reg_ppcnt_a_octets_received_ok 3230 * Access: RO 3231 */ 3232 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok, 3233 0x08 + 0x28, 0, 64); 3234 3235 /* reg_ppcnt_a_multicast_frames_xmitted_ok 3236 * Access: RO 3237 */ 3238 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok, 3239 0x08 + 0x30, 0, 64); 3240 3241 /* reg_ppcnt_a_broadcast_frames_xmitted_ok 3242 * Access: RO 3243 */ 3244 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok, 3245 0x08 + 0x38, 0, 64); 3246 3247 /* reg_ppcnt_a_multicast_frames_received_ok 3248 * Access: RO 3249 */ 3250 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok, 3251 0x08 + 0x40, 0, 64); 3252 3253 /* reg_ppcnt_a_broadcast_frames_received_ok 3254 * Access: RO 3255 */ 3256 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok, 3257 0x08 + 0x48, 0, 64); 3258 3259 /* reg_ppcnt_a_in_range_length_errors 3260 * Access: RO 3261 */ 3262 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors, 3263 0x08 + 0x50, 0, 64); 3264 3265 /* reg_ppcnt_a_out_of_range_length_field 3266 * Access: RO 3267 */ 3268 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field, 3269 0x08 + 0x58, 0, 64); 3270 3271 /* reg_ppcnt_a_frame_too_long_errors 3272 * Access: RO 3273 */ 3274 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors, 3275 0x08 + 0x60, 0, 64); 3276 3277 /* reg_ppcnt_a_symbol_error_during_carrier 3278 * Access: RO 3279 */ 3280 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier, 3281 0x08 + 0x68, 0, 64); 3282 3283 /* reg_ppcnt_a_mac_control_frames_transmitted 3284 * Access: RO 3285 */ 3286 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted, 3287 0x08 + 0x70, 0, 64); 3288 3289 /* reg_ppcnt_a_mac_control_frames_received 3290 * Access: RO 3291 */ 3292 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received, 3293 0x08 + 0x78, 0, 64); 3294 3295 /* reg_ppcnt_a_unsupported_opcodes_received 3296 * Access: RO 3297 */ 3298 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received, 3299 0x08 + 0x80, 0, 64); 3300 3301 /* reg_ppcnt_a_pause_mac_ctrl_frames_received 3302 * Access: RO 3303 */ 3304 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received, 3305 0x08 + 0x88, 0, 64); 3306 3307 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted 3308 * Access: RO 3309 */ 3310 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted, 3311 0x08 + 0x90, 0, 64); 3312 3313 /* Ethernet Per Priority Group Counters */ 3314 3315 /* reg_ppcnt_rx_octets 3316 * Access: RO 3317 */ 3318 MLXSW_ITEM64(reg, ppcnt, rx_octets, 0x08 + 0x00, 0, 64); 3319 3320 /* reg_ppcnt_rx_frames 3321 * Access: RO 3322 */ 3323 MLXSW_ITEM64(reg, ppcnt, rx_frames, 0x08 + 0x20, 0, 64); 3324 3325 /* reg_ppcnt_tx_octets 3326 * Access: RO 3327 */ 3328 MLXSW_ITEM64(reg, ppcnt, tx_octets, 0x08 + 0x28, 0, 64); 3329 3330 /* reg_ppcnt_tx_frames 3331 * Access: RO 3332 */ 3333 MLXSW_ITEM64(reg, ppcnt, tx_frames, 0x08 + 0x48, 0, 64); 3334 3335 /* reg_ppcnt_rx_pause 3336 * Access: RO 3337 */ 3338 MLXSW_ITEM64(reg, ppcnt, rx_pause, 0x08 + 0x50, 0, 64); 3339 3340 /* reg_ppcnt_rx_pause_duration 3341 * Access: RO 3342 */ 3343 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration, 0x08 + 0x58, 0, 64); 3344 3345 /* reg_ppcnt_tx_pause 3346 * Access: RO 3347 */ 3348 MLXSW_ITEM64(reg, ppcnt, tx_pause, 0x08 + 0x60, 0, 64); 3349 3350 /* reg_ppcnt_tx_pause_duration 3351 * Access: RO 3352 */ 3353 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration, 0x08 + 0x68, 0, 64); 3354 3355 /* reg_ppcnt_rx_pause_transition 3356 * Access: RO 3357 */ 3358 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition, 0x08 + 0x70, 0, 64); 3359 3360 /* Ethernet Per Traffic Group Counters */ 3361 3362 /* reg_ppcnt_tc_transmit_queue 3363 * Contains the transmit queue depth in cells of traffic class 3364 * selected by prio_tc and the port selected by local_port. 3365 * The field cannot be cleared. 3366 * Access: RO 3367 */ 3368 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue, 0x08 + 0x00, 0, 64); 3369 3370 /* reg_ppcnt_tc_no_buffer_discard_uc 3371 * The number of unicast packets dropped due to lack of shared 3372 * buffer resources. 3373 * Access: RO 3374 */ 3375 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc, 0x08 + 0x08, 0, 64); 3376 3377 static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port, 3378 enum mlxsw_reg_ppcnt_grp grp, 3379 u8 prio_tc) 3380 { 3381 MLXSW_REG_ZERO(ppcnt, payload); 3382 mlxsw_reg_ppcnt_swid_set(payload, 0); 3383 mlxsw_reg_ppcnt_local_port_set(payload, local_port); 3384 mlxsw_reg_ppcnt_pnat_set(payload, 0); 3385 mlxsw_reg_ppcnt_grp_set(payload, grp); 3386 mlxsw_reg_ppcnt_clr_set(payload, 0); 3387 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc); 3388 } 3389 3390 /* PLIB - Port Local to InfiniBand Port 3391 * ------------------------------------ 3392 * The PLIB register performs mapping from Local Port into InfiniBand Port. 3393 */ 3394 #define MLXSW_REG_PLIB_ID 0x500A 3395 #define MLXSW_REG_PLIB_LEN 0x10 3396 3397 MLXSW_REG_DEFINE(plib, MLXSW_REG_PLIB_ID, MLXSW_REG_PLIB_LEN); 3398 3399 /* reg_plib_local_port 3400 * Local port number. 3401 * Access: Index 3402 */ 3403 MLXSW_ITEM32(reg, plib, local_port, 0x00, 16, 8); 3404 3405 /* reg_plib_ib_port 3406 * InfiniBand port remapping for local_port. 3407 * Access: RW 3408 */ 3409 MLXSW_ITEM32(reg, plib, ib_port, 0x00, 0, 8); 3410 3411 /* PPTB - Port Prio To Buffer Register 3412 * ----------------------------------- 3413 * Configures the switch priority to buffer table. 3414 */ 3415 #define MLXSW_REG_PPTB_ID 0x500B 3416 #define MLXSW_REG_PPTB_LEN 0x10 3417 3418 MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN); 3419 3420 enum { 3421 MLXSW_REG_PPTB_MM_UM, 3422 MLXSW_REG_PPTB_MM_UNICAST, 3423 MLXSW_REG_PPTB_MM_MULTICAST, 3424 }; 3425 3426 /* reg_pptb_mm 3427 * Mapping mode. 3428 * 0 - Map both unicast and multicast packets to the same buffer. 3429 * 1 - Map only unicast packets. 3430 * 2 - Map only multicast packets. 3431 * Access: Index 3432 * 3433 * Note: SwitchX-2 only supports the first option. 3434 */ 3435 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2); 3436 3437 /* reg_pptb_local_port 3438 * Local port number. 3439 * Access: Index 3440 */ 3441 MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8); 3442 3443 /* reg_pptb_um 3444 * Enables the update of the untagged_buf field. 3445 * Access: RW 3446 */ 3447 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1); 3448 3449 /* reg_pptb_pm 3450 * Enables the update of the prio_to_buff field. 3451 * Bit <i> is a flag for updating the mapping for switch priority <i>. 3452 * Access: RW 3453 */ 3454 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8); 3455 3456 /* reg_pptb_prio_to_buff 3457 * Mapping of switch priority <i> to one of the allocated receive port 3458 * buffers. 3459 * Access: RW 3460 */ 3461 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4); 3462 3463 /* reg_pptb_pm_msb 3464 * Enables the update of the prio_to_buff field. 3465 * Bit <i> is a flag for updating the mapping for switch priority <i+8>. 3466 * Access: RW 3467 */ 3468 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8); 3469 3470 /* reg_pptb_untagged_buff 3471 * Mapping of untagged frames to one of the allocated receive port buffers. 3472 * Access: RW 3473 * 3474 * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for 3475 * Spectrum, as it maps untagged packets based on the default switch priority. 3476 */ 3477 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4); 3478 3479 /* reg_pptb_prio_to_buff_msb 3480 * Mapping of switch priority <i+8> to one of the allocated receive port 3481 * buffers. 3482 * Access: RW 3483 */ 3484 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4); 3485 3486 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF 3487 3488 static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port) 3489 { 3490 MLXSW_REG_ZERO(pptb, payload); 3491 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM); 3492 mlxsw_reg_pptb_local_port_set(payload, local_port); 3493 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 3494 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 3495 } 3496 3497 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio, 3498 u8 buff) 3499 { 3500 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff); 3501 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff); 3502 } 3503 3504 /* PBMC - Port Buffer Management Control Register 3505 * ---------------------------------------------- 3506 * The PBMC register configures and retrieves the port packet buffer 3507 * allocation for different Prios, and the Pause threshold management. 3508 */ 3509 #define MLXSW_REG_PBMC_ID 0x500C 3510 #define MLXSW_REG_PBMC_LEN 0x6C 3511 3512 MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN); 3513 3514 /* reg_pbmc_local_port 3515 * Local port number. 3516 * Access: Index 3517 */ 3518 MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8); 3519 3520 /* reg_pbmc_xoff_timer_value 3521 * When device generates a pause frame, it uses this value as the pause 3522 * timer (time for the peer port to pause in quota-512 bit time). 3523 * Access: RW 3524 */ 3525 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16); 3526 3527 /* reg_pbmc_xoff_refresh 3528 * The time before a new pause frame should be sent to refresh the pause RW 3529 * state. Using the same units as xoff_timer_value above (in quota-512 bit 3530 * time). 3531 * Access: RW 3532 */ 3533 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16); 3534 3535 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11 3536 3537 /* reg_pbmc_buf_lossy 3538 * The field indicates if the buffer is lossy. 3539 * 0 - Lossless 3540 * 1 - Lossy 3541 * Access: RW 3542 */ 3543 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false); 3544 3545 /* reg_pbmc_buf_epsb 3546 * Eligible for Port Shared buffer. 3547 * If epsb is set, packets assigned to buffer are allowed to insert the port 3548 * shared buffer. 3549 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved. 3550 * Access: RW 3551 */ 3552 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false); 3553 3554 /* reg_pbmc_buf_size 3555 * The part of the packet buffer array is allocated for the specific buffer. 3556 * Units are represented in cells. 3557 * Access: RW 3558 */ 3559 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false); 3560 3561 /* reg_pbmc_buf_xoff_threshold 3562 * Once the amount of data in the buffer goes above this value, device 3563 * starts sending PFC frames for all priorities associated with the 3564 * buffer. Units are represented in cells. Reserved in case of lossy 3565 * buffer. 3566 * Access: RW 3567 * 3568 * Note: In Spectrum, reserved for buffer[9]. 3569 */ 3570 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16, 3571 0x08, 0x04, false); 3572 3573 /* reg_pbmc_buf_xon_threshold 3574 * When the amount of data in the buffer goes below this value, device 3575 * stops sending PFC frames for the priorities associated with the 3576 * buffer. Units are represented in cells. Reserved in case of lossy 3577 * buffer. 3578 * Access: RW 3579 * 3580 * Note: In Spectrum, reserved for buffer[9]. 3581 */ 3582 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16, 3583 0x08, 0x04, false); 3584 3585 static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port, 3586 u16 xoff_timer_value, u16 xoff_refresh) 3587 { 3588 MLXSW_REG_ZERO(pbmc, payload); 3589 mlxsw_reg_pbmc_local_port_set(payload, local_port); 3590 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value); 3591 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh); 3592 } 3593 3594 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload, 3595 int buf_index, 3596 u16 size) 3597 { 3598 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1); 3599 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 3600 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 3601 } 3602 3603 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload, 3604 int buf_index, u16 size, 3605 u16 threshold) 3606 { 3607 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0); 3608 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 3609 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 3610 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold); 3611 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold); 3612 } 3613 3614 /* PSPA - Port Switch Partition Allocation 3615 * --------------------------------------- 3616 * Controls the association of a port with a switch partition and enables 3617 * configuring ports as stacking ports. 3618 */ 3619 #define MLXSW_REG_PSPA_ID 0x500D 3620 #define MLXSW_REG_PSPA_LEN 0x8 3621 3622 MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN); 3623 3624 /* reg_pspa_swid 3625 * Switch partition ID. 3626 * Access: RW 3627 */ 3628 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8); 3629 3630 /* reg_pspa_local_port 3631 * Local port number. 3632 * Access: Index 3633 */ 3634 MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8); 3635 3636 /* reg_pspa_sub_port 3637 * Virtual port within the local port. Set to 0 when virtual ports are 3638 * disabled on the local port. 3639 * Access: Index 3640 */ 3641 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8); 3642 3643 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port) 3644 { 3645 MLXSW_REG_ZERO(pspa, payload); 3646 mlxsw_reg_pspa_swid_set(payload, swid); 3647 mlxsw_reg_pspa_local_port_set(payload, local_port); 3648 mlxsw_reg_pspa_sub_port_set(payload, 0); 3649 } 3650 3651 /* HTGT - Host Trap Group Table 3652 * ---------------------------- 3653 * Configures the properties for forwarding to CPU. 3654 */ 3655 #define MLXSW_REG_HTGT_ID 0x7002 3656 #define MLXSW_REG_HTGT_LEN 0x20 3657 3658 MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN); 3659 3660 /* reg_htgt_swid 3661 * Switch partition ID. 3662 * Access: Index 3663 */ 3664 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8); 3665 3666 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */ 3667 3668 /* reg_htgt_type 3669 * CPU path type. 3670 * Access: RW 3671 */ 3672 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4); 3673 3674 enum mlxsw_reg_htgt_trap_group { 3675 MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 3676 MLXSW_REG_HTGT_TRAP_GROUP_SX2_RX, 3677 MLXSW_REG_HTGT_TRAP_GROUP_SX2_CTRL, 3678 MLXSW_REG_HTGT_TRAP_GROUP_SP_STP, 3679 MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP, 3680 MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP, 3681 MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP, 3682 MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP_IPV4, 3683 MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF, 3684 MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP, 3685 MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP_MISS, 3686 MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP, 3687 MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE, 3688 MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME, 3689 MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP, 3690 MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT, 3691 }; 3692 3693 /* reg_htgt_trap_group 3694 * Trap group number. User defined number specifying which trap groups 3695 * should be forwarded to the CPU. The mapping between trap IDs and trap 3696 * groups is configured using HPKT register. 3697 * Access: Index 3698 */ 3699 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8); 3700 3701 enum { 3702 MLXSW_REG_HTGT_POLICER_DISABLE, 3703 MLXSW_REG_HTGT_POLICER_ENABLE, 3704 }; 3705 3706 /* reg_htgt_pide 3707 * Enable policer ID specified using 'pid' field. 3708 * Access: RW 3709 */ 3710 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1); 3711 3712 #define MLXSW_REG_HTGT_INVALID_POLICER 0xff 3713 3714 /* reg_htgt_pid 3715 * Policer ID for the trap group. 3716 * Access: RW 3717 */ 3718 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8); 3719 3720 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0 3721 3722 /* reg_htgt_mirror_action 3723 * Mirror action to use. 3724 * 0 - Trap to CPU. 3725 * 1 - Trap to CPU and mirror to a mirroring agent. 3726 * 2 - Mirror to a mirroring agent and do not trap to CPU. 3727 * Access: RW 3728 * 3729 * Note: Mirroring to a mirroring agent is only supported in Spectrum. 3730 */ 3731 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2); 3732 3733 /* reg_htgt_mirroring_agent 3734 * Mirroring agent. 3735 * Access: RW 3736 */ 3737 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3); 3738 3739 #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0 3740 3741 /* reg_htgt_priority 3742 * Trap group priority. 3743 * In case a packet matches multiple classification rules, the packet will 3744 * only be trapped once, based on the trap ID associated with the group (via 3745 * register HPKT) with the highest priority. 3746 * Supported values are 0-7, with 7 represnting the highest priority. 3747 * Access: RW 3748 * 3749 * Note: In SwitchX-2 this field is ignored and the priority value is replaced 3750 * by the 'trap_group' field. 3751 */ 3752 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4); 3753 3754 #define MLXSW_REG_HTGT_DEFAULT_TC 7 3755 3756 /* reg_htgt_local_path_cpu_tclass 3757 * CPU ingress traffic class for the trap group. 3758 * Access: RW 3759 */ 3760 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6); 3761 3762 enum mlxsw_reg_htgt_local_path_rdq { 3763 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13, 3764 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14, 3765 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15, 3766 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15, 3767 }; 3768 /* reg_htgt_local_path_rdq 3769 * Receive descriptor queue (RDQ) to use for the trap group. 3770 * Access: RW 3771 */ 3772 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6); 3773 3774 static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id, 3775 u8 priority, u8 tc) 3776 { 3777 MLXSW_REG_ZERO(htgt, payload); 3778 3779 if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) { 3780 mlxsw_reg_htgt_pide_set(payload, 3781 MLXSW_REG_HTGT_POLICER_DISABLE); 3782 } else { 3783 mlxsw_reg_htgt_pide_set(payload, 3784 MLXSW_REG_HTGT_POLICER_ENABLE); 3785 mlxsw_reg_htgt_pid_set(payload, policer_id); 3786 } 3787 3788 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL); 3789 mlxsw_reg_htgt_trap_group_set(payload, group); 3790 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU); 3791 mlxsw_reg_htgt_mirroring_agent_set(payload, 0); 3792 mlxsw_reg_htgt_priority_set(payload, priority); 3793 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc); 3794 mlxsw_reg_htgt_local_path_rdq_set(payload, group); 3795 } 3796 3797 /* HPKT - Host Packet Trap 3798 * ----------------------- 3799 * Configures trap IDs inside trap groups. 3800 */ 3801 #define MLXSW_REG_HPKT_ID 0x7003 3802 #define MLXSW_REG_HPKT_LEN 0x10 3803 3804 MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN); 3805 3806 enum { 3807 MLXSW_REG_HPKT_ACK_NOT_REQUIRED, 3808 MLXSW_REG_HPKT_ACK_REQUIRED, 3809 }; 3810 3811 /* reg_hpkt_ack 3812 * Require acknowledgements from the host for events. 3813 * If set, then the device will wait for the event it sent to be acknowledged 3814 * by the host. This option is only relevant for event trap IDs. 3815 * Access: RW 3816 * 3817 * Note: Currently not supported by firmware. 3818 */ 3819 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1); 3820 3821 enum mlxsw_reg_hpkt_action { 3822 MLXSW_REG_HPKT_ACTION_FORWARD, 3823 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU, 3824 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU, 3825 MLXSW_REG_HPKT_ACTION_DISCARD, 3826 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD, 3827 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD, 3828 }; 3829 3830 /* reg_hpkt_action 3831 * Action to perform on packet when trapped. 3832 * 0 - No action. Forward to CPU based on switching rules. 3833 * 1 - Trap to CPU (CPU receives sole copy). 3834 * 2 - Mirror to CPU (CPU receives a replica of the packet). 3835 * 3 - Discard. 3836 * 4 - Soft discard (allow other traps to act on the packet). 3837 * 5 - Trap and soft discard (allow other traps to overwrite this trap). 3838 * Access: RW 3839 * 3840 * Note: Must be set to 0 (forward) for event trap IDs, as they are already 3841 * addressed to the CPU. 3842 */ 3843 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3); 3844 3845 /* reg_hpkt_trap_group 3846 * Trap group to associate the trap with. 3847 * Access: RW 3848 */ 3849 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6); 3850 3851 /* reg_hpkt_trap_id 3852 * Trap ID. 3853 * Access: Index 3854 * 3855 * Note: A trap ID can only be associated with a single trap group. The device 3856 * will associate the trap ID with the last trap group configured. 3857 */ 3858 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9); 3859 3860 enum { 3861 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT, 3862 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER, 3863 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER, 3864 }; 3865 3866 /* reg_hpkt_ctrl 3867 * Configure dedicated buffer resources for control packets. 3868 * Ignored by SwitchX-2. 3869 * 0 - Keep factory defaults. 3870 * 1 - Do not use control buffer for this trap ID. 3871 * 2 - Use control buffer for this trap ID. 3872 * Access: RW 3873 */ 3874 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2); 3875 3876 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id, 3877 enum mlxsw_reg_htgt_trap_group trap_group, 3878 bool is_ctrl) 3879 { 3880 MLXSW_REG_ZERO(hpkt, payload); 3881 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED); 3882 mlxsw_reg_hpkt_action_set(payload, action); 3883 mlxsw_reg_hpkt_trap_group_set(payload, trap_group); 3884 mlxsw_reg_hpkt_trap_id_set(payload, trap_id); 3885 mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ? 3886 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER : 3887 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER); 3888 } 3889 3890 /* RGCR - Router General Configuration Register 3891 * -------------------------------------------- 3892 * The register is used for setting up the router configuration. 3893 */ 3894 #define MLXSW_REG_RGCR_ID 0x8001 3895 #define MLXSW_REG_RGCR_LEN 0x28 3896 3897 MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN); 3898 3899 /* reg_rgcr_ipv4_en 3900 * IPv4 router enable. 3901 * Access: RW 3902 */ 3903 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1); 3904 3905 /* reg_rgcr_ipv6_en 3906 * IPv6 router enable. 3907 * Access: RW 3908 */ 3909 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1); 3910 3911 /* reg_rgcr_max_router_interfaces 3912 * Defines the maximum number of active router interfaces for all virtual 3913 * routers. 3914 * Access: RW 3915 */ 3916 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16); 3917 3918 /* reg_rgcr_usp 3919 * Update switch priority and packet color. 3920 * 0 - Preserve the value of Switch Priority and packet color. 3921 * 1 - Recalculate the value of Switch Priority and packet color. 3922 * Access: RW 3923 * 3924 * Note: Not supported by SwitchX and SwitchX-2. 3925 */ 3926 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1); 3927 3928 /* reg_rgcr_pcp_rw 3929 * Indicates how to handle the pcp_rewrite_en value: 3930 * 0 - Preserve the value of pcp_rewrite_en. 3931 * 2 - Disable PCP rewrite. 3932 * 3 - Enable PCP rewrite. 3933 * Access: RW 3934 * 3935 * Note: Not supported by SwitchX and SwitchX-2. 3936 */ 3937 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2); 3938 3939 /* reg_rgcr_activity_dis 3940 * Activity disable: 3941 * 0 - Activity will be set when an entry is hit (default). 3942 * 1 - Activity will not be set when an entry is hit. 3943 * 3944 * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry 3945 * (RALUE). 3946 * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host 3947 * Entry (RAUHT). 3948 * Bits 2:7 are reserved. 3949 * Access: RW 3950 * 3951 * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB. 3952 */ 3953 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8); 3954 3955 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en) 3956 { 3957 MLXSW_REG_ZERO(rgcr, payload); 3958 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en); 3959 } 3960 3961 /* RITR - Router Interface Table Register 3962 * -------------------------------------- 3963 * The register is used to configure the router interface table. 3964 */ 3965 #define MLXSW_REG_RITR_ID 0x8002 3966 #define MLXSW_REG_RITR_LEN 0x40 3967 3968 MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN); 3969 3970 /* reg_ritr_enable 3971 * Enables routing on the router interface. 3972 * Access: RW 3973 */ 3974 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1); 3975 3976 /* reg_ritr_ipv4 3977 * IPv4 routing enable. Enables routing of IPv4 traffic on the router 3978 * interface. 3979 * Access: RW 3980 */ 3981 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1); 3982 3983 /* reg_ritr_ipv6 3984 * IPv6 routing enable. Enables routing of IPv6 traffic on the router 3985 * interface. 3986 * Access: RW 3987 */ 3988 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1); 3989 3990 enum mlxsw_reg_ritr_if_type { 3991 MLXSW_REG_RITR_VLAN_IF, 3992 MLXSW_REG_RITR_FID_IF, 3993 MLXSW_REG_RITR_SP_IF, 3994 }; 3995 3996 /* reg_ritr_type 3997 * Router interface type. 3998 * 0 - VLAN interface. 3999 * 1 - FID interface. 4000 * 2 - Sub-port interface. 4001 * Access: RW 4002 */ 4003 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3); 4004 4005 enum { 4006 MLXSW_REG_RITR_RIF_CREATE, 4007 MLXSW_REG_RITR_RIF_DEL, 4008 }; 4009 4010 /* reg_ritr_op 4011 * Opcode: 4012 * 0 - Create or edit RIF. 4013 * 1 - Delete RIF. 4014 * Reserved for SwitchX-2. For Spectrum, editing of interface properties 4015 * is not supported. An interface must be deleted and re-created in order 4016 * to update properties. 4017 * Access: WO 4018 */ 4019 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2); 4020 4021 /* reg_ritr_rif 4022 * Router interface index. A pointer to the Router Interface Table. 4023 * Access: Index 4024 */ 4025 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16); 4026 4027 /* reg_ritr_ipv4_fe 4028 * IPv4 Forwarding Enable. 4029 * Enables routing of IPv4 traffic on the router interface. When disabled, 4030 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 4031 * Not supported in SwitchX-2. 4032 * Access: RW 4033 */ 4034 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1); 4035 4036 /* reg_ritr_ipv6_fe 4037 * IPv6 Forwarding Enable. 4038 * Enables routing of IPv6 traffic on the router interface. When disabled, 4039 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 4040 * Not supported in SwitchX-2. 4041 * Access: RW 4042 */ 4043 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1); 4044 4045 /* reg_ritr_lb_en 4046 * Loop-back filter enable for unicast packets. 4047 * If the flag is set then loop-back filter for unicast packets is 4048 * implemented on the RIF. Multicast packets are always subject to 4049 * loop-back filtering. 4050 * Access: RW 4051 */ 4052 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1); 4053 4054 /* reg_ritr_virtual_router 4055 * Virtual router ID associated with the router interface. 4056 * Access: RW 4057 */ 4058 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16); 4059 4060 /* reg_ritr_mtu 4061 * Router interface MTU. 4062 * Access: RW 4063 */ 4064 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16); 4065 4066 /* reg_ritr_if_swid 4067 * Switch partition ID. 4068 * Access: RW 4069 */ 4070 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8); 4071 4072 /* reg_ritr_if_mac 4073 * Router interface MAC address. 4074 * In Spectrum, all MAC addresses must have the same 38 MSBits. 4075 * Access: RW 4076 */ 4077 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6); 4078 4079 /* VLAN Interface */ 4080 4081 /* reg_ritr_vlan_if_vid 4082 * VLAN ID. 4083 * Access: RW 4084 */ 4085 MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12); 4086 4087 /* FID Interface */ 4088 4089 /* reg_ritr_fid_if_fid 4090 * Filtering ID. Used to connect a bridge to the router. Only FIDs from 4091 * the vFID range are supported. 4092 * Access: RW 4093 */ 4094 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16); 4095 4096 static inline void mlxsw_reg_ritr_fid_set(char *payload, 4097 enum mlxsw_reg_ritr_if_type rif_type, 4098 u16 fid) 4099 { 4100 if (rif_type == MLXSW_REG_RITR_FID_IF) 4101 mlxsw_reg_ritr_fid_if_fid_set(payload, fid); 4102 else 4103 mlxsw_reg_ritr_vlan_if_vid_set(payload, fid); 4104 } 4105 4106 /* Sub-port Interface */ 4107 4108 /* reg_ritr_sp_if_lag 4109 * LAG indication. When this bit is set the system_port field holds the 4110 * LAG identifier. 4111 * Access: RW 4112 */ 4113 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1); 4114 4115 /* reg_ritr_sp_system_port 4116 * Port unique indentifier. When lag bit is set, this field holds the 4117 * lag_id in bits 0:9. 4118 * Access: RW 4119 */ 4120 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16); 4121 4122 /* reg_ritr_sp_if_vid 4123 * VLAN ID. 4124 * Access: RW 4125 */ 4126 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12); 4127 4128 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif) 4129 { 4130 MLXSW_REG_ZERO(ritr, payload); 4131 mlxsw_reg_ritr_rif_set(payload, rif); 4132 } 4133 4134 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag, 4135 u16 system_port, u16 vid) 4136 { 4137 mlxsw_reg_ritr_sp_if_lag_set(payload, lag); 4138 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port); 4139 mlxsw_reg_ritr_sp_if_vid_set(payload, vid); 4140 } 4141 4142 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable, 4143 enum mlxsw_reg_ritr_if_type type, 4144 u16 rif, u16 mtu, const char *mac) 4145 { 4146 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL; 4147 4148 MLXSW_REG_ZERO(ritr, payload); 4149 mlxsw_reg_ritr_enable_set(payload, enable); 4150 mlxsw_reg_ritr_ipv4_set(payload, 1); 4151 mlxsw_reg_ritr_type_set(payload, type); 4152 mlxsw_reg_ritr_op_set(payload, op); 4153 mlxsw_reg_ritr_rif_set(payload, rif); 4154 mlxsw_reg_ritr_ipv4_fe_set(payload, 1); 4155 mlxsw_reg_ritr_lb_en_set(payload, 1); 4156 mlxsw_reg_ritr_mtu_set(payload, mtu); 4157 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac); 4158 } 4159 4160 /* RATR - Router Adjacency Table Register 4161 * -------------------------------------- 4162 * The RATR register is used to configure the Router Adjacency (next-hop) 4163 * Table. 4164 */ 4165 #define MLXSW_REG_RATR_ID 0x8008 4166 #define MLXSW_REG_RATR_LEN 0x2C 4167 4168 MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN); 4169 4170 enum mlxsw_reg_ratr_op { 4171 /* Read */ 4172 MLXSW_REG_RATR_OP_QUERY_READ = 0, 4173 /* Read and clear activity */ 4174 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2, 4175 /* Write Adjacency entry */ 4176 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1, 4177 /* Write Adjacency entry only if the activity is cleared. 4178 * The write may not succeed if the activity is set. There is not 4179 * direct feedback if the write has succeeded or not, however 4180 * the get will reveal the actual entry (SW can compare the get 4181 * response to the set command). 4182 */ 4183 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3, 4184 }; 4185 4186 /* reg_ratr_op 4187 * Note that Write operation may also be used for updating 4188 * counter_set_type and counter_index. In this case all other 4189 * fields must not be updated. 4190 * Access: OP 4191 */ 4192 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4); 4193 4194 /* reg_ratr_v 4195 * Valid bit. Indicates if the adjacency entry is valid. 4196 * Note: the device may need some time before reusing an invalidated 4197 * entry. During this time the entry can not be reused. It is 4198 * recommended to use another entry before reusing an invalidated 4199 * entry (e.g. software can put it at the end of the list for 4200 * reusing). Trying to access an invalidated entry not yet cleared 4201 * by the device results with failure indicating "Try Again" status. 4202 * When valid is '0' then egress_router_interface,trap_action, 4203 * adjacency_parameters and counters are reserved 4204 * Access: RW 4205 */ 4206 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1); 4207 4208 /* reg_ratr_a 4209 * Activity. Set for new entries. Set if a packet lookup has hit on 4210 * the specific entry. To clear the a bit, use "clear activity". 4211 * Access: RO 4212 */ 4213 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1); 4214 4215 /* reg_ratr_adjacency_index_low 4216 * Bits 15:0 of index into the adjacency table. 4217 * For SwitchX and SwitchX-2, the adjacency table is linear and 4218 * used for adjacency entries only. 4219 * For Spectrum, the index is to the KVD linear. 4220 * Access: Index 4221 */ 4222 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16); 4223 4224 /* reg_ratr_egress_router_interface 4225 * Range is 0 .. cap_max_router_interfaces - 1 4226 * Access: RW 4227 */ 4228 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16); 4229 4230 enum mlxsw_reg_ratr_trap_action { 4231 MLXSW_REG_RATR_TRAP_ACTION_NOP, 4232 MLXSW_REG_RATR_TRAP_ACTION_TRAP, 4233 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU, 4234 MLXSW_REG_RATR_TRAP_ACTION_MIRROR, 4235 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS, 4236 }; 4237 4238 /* reg_ratr_trap_action 4239 * see mlxsw_reg_ratr_trap_action 4240 * Access: RW 4241 */ 4242 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4); 4243 4244 enum mlxsw_reg_ratr_trap_id { 4245 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0 = 0, 4246 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1 = 1, 4247 }; 4248 4249 /* reg_ratr_adjacency_index_high 4250 * Bits 23:16 of the adjacency_index. 4251 * Access: Index 4252 */ 4253 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8); 4254 4255 /* reg_ratr_trap_id 4256 * Trap ID to be reported to CPU. 4257 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 4258 * For trap_action of NOP, MIRROR and DISCARD_ERROR 4259 * Access: RW 4260 */ 4261 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8); 4262 4263 /* reg_ratr_eth_destination_mac 4264 * MAC address of the destination next-hop. 4265 * Access: RW 4266 */ 4267 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6); 4268 4269 static inline void 4270 mlxsw_reg_ratr_pack(char *payload, 4271 enum mlxsw_reg_ratr_op op, bool valid, 4272 u32 adjacency_index, u16 egress_rif) 4273 { 4274 MLXSW_REG_ZERO(ratr, payload); 4275 mlxsw_reg_ratr_op_set(payload, op); 4276 mlxsw_reg_ratr_v_set(payload, valid); 4277 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index); 4278 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16); 4279 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif); 4280 } 4281 4282 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload, 4283 const char *dest_mac) 4284 { 4285 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac); 4286 } 4287 4288 /* RALTA - Router Algorithmic LPM Tree Allocation Register 4289 * ------------------------------------------------------- 4290 * RALTA is used to allocate the LPM trees of the SHSPM method. 4291 */ 4292 #define MLXSW_REG_RALTA_ID 0x8010 4293 #define MLXSW_REG_RALTA_LEN 0x04 4294 4295 MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN); 4296 4297 /* reg_ralta_op 4298 * opcode (valid for Write, must be 0 on Read) 4299 * 0 - allocate a tree 4300 * 1 - deallocate a tree 4301 * Access: OP 4302 */ 4303 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2); 4304 4305 enum mlxsw_reg_ralxx_protocol { 4306 MLXSW_REG_RALXX_PROTOCOL_IPV4, 4307 MLXSW_REG_RALXX_PROTOCOL_IPV6, 4308 }; 4309 4310 /* reg_ralta_protocol 4311 * Protocol. 4312 * Deallocation opcode: Reserved. 4313 * Access: RW 4314 */ 4315 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4); 4316 4317 /* reg_ralta_tree_id 4318 * An identifier (numbered from 1..cap_shspm_max_trees-1) representing 4319 * the tree identifier (managed by software). 4320 * Note that tree_id 0 is allocated for a default-route tree. 4321 * Access: Index 4322 */ 4323 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8); 4324 4325 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc, 4326 enum mlxsw_reg_ralxx_protocol protocol, 4327 u8 tree_id) 4328 { 4329 MLXSW_REG_ZERO(ralta, payload); 4330 mlxsw_reg_ralta_op_set(payload, !alloc); 4331 mlxsw_reg_ralta_protocol_set(payload, protocol); 4332 mlxsw_reg_ralta_tree_id_set(payload, tree_id); 4333 } 4334 4335 /* RALST - Router Algorithmic LPM Structure Tree Register 4336 * ------------------------------------------------------ 4337 * RALST is used to set and query the structure of an LPM tree. 4338 * The structure of the tree must be sorted as a sorted binary tree, while 4339 * each node is a bin that is tagged as the length of the prefixes the lookup 4340 * will refer to. Therefore, bin X refers to a set of entries with prefixes 4341 * of X bits to match with the destination address. The bin 0 indicates 4342 * the default action, when there is no match of any prefix. 4343 */ 4344 #define MLXSW_REG_RALST_ID 0x8011 4345 #define MLXSW_REG_RALST_LEN 0x104 4346 4347 MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN); 4348 4349 /* reg_ralst_root_bin 4350 * The bin number of the root bin. 4351 * 0<root_bin=<(length of IP address) 4352 * For a default-route tree configure 0xff 4353 * Access: RW 4354 */ 4355 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8); 4356 4357 /* reg_ralst_tree_id 4358 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 4359 * Access: Index 4360 */ 4361 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8); 4362 4363 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff 4364 #define MLXSW_REG_RALST_BIN_OFFSET 0x04 4365 #define MLXSW_REG_RALST_BIN_COUNT 128 4366 4367 /* reg_ralst_left_child_bin 4368 * Holding the children of the bin according to the stored tree's structure. 4369 * For trees composed of less than 4 blocks, the bins in excess are reserved. 4370 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 4371 * Access: RW 4372 */ 4373 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false); 4374 4375 /* reg_ralst_right_child_bin 4376 * Holding the children of the bin according to the stored tree's structure. 4377 * For trees composed of less than 4 blocks, the bins in excess are reserved. 4378 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 4379 * Access: RW 4380 */ 4381 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00, 4382 false); 4383 4384 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id) 4385 { 4386 MLXSW_REG_ZERO(ralst, payload); 4387 4388 /* Initialize all bins to have no left or right child */ 4389 memset(payload + MLXSW_REG_RALST_BIN_OFFSET, 4390 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2); 4391 4392 mlxsw_reg_ralst_root_bin_set(payload, root_bin); 4393 mlxsw_reg_ralst_tree_id_set(payload, tree_id); 4394 } 4395 4396 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number, 4397 u8 left_child_bin, 4398 u8 right_child_bin) 4399 { 4400 int bin_index = bin_number - 1; 4401 4402 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin); 4403 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index, 4404 right_child_bin); 4405 } 4406 4407 /* RALTB - Router Algorithmic LPM Tree Binding Register 4408 * ---------------------------------------------------- 4409 * RALTB is used to bind virtual router and protocol to an allocated LPM tree. 4410 */ 4411 #define MLXSW_REG_RALTB_ID 0x8012 4412 #define MLXSW_REG_RALTB_LEN 0x04 4413 4414 MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN); 4415 4416 /* reg_raltb_virtual_router 4417 * Virtual Router ID 4418 * Range is 0..cap_max_virtual_routers-1 4419 * Access: Index 4420 */ 4421 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16); 4422 4423 /* reg_raltb_protocol 4424 * Protocol. 4425 * Access: Index 4426 */ 4427 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4); 4428 4429 /* reg_raltb_tree_id 4430 * Tree to be used for the {virtual_router, protocol} 4431 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 4432 * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0. 4433 * Access: RW 4434 */ 4435 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8); 4436 4437 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router, 4438 enum mlxsw_reg_ralxx_protocol protocol, 4439 u8 tree_id) 4440 { 4441 MLXSW_REG_ZERO(raltb, payload); 4442 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router); 4443 mlxsw_reg_raltb_protocol_set(payload, protocol); 4444 mlxsw_reg_raltb_tree_id_set(payload, tree_id); 4445 } 4446 4447 /* RALUE - Router Algorithmic LPM Unicast Entry Register 4448 * ----------------------------------------------------- 4449 * RALUE is used to configure and query LPM entries that serve 4450 * the Unicast protocols. 4451 */ 4452 #define MLXSW_REG_RALUE_ID 0x8013 4453 #define MLXSW_REG_RALUE_LEN 0x38 4454 4455 MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN); 4456 4457 /* reg_ralue_protocol 4458 * Protocol. 4459 * Access: Index 4460 */ 4461 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4); 4462 4463 enum mlxsw_reg_ralue_op { 4464 /* Read operation. If entry doesn't exist, the operation fails. */ 4465 MLXSW_REG_RALUE_OP_QUERY_READ = 0, 4466 /* Clear on read operation. Used to read entry and 4467 * clear Activity bit. 4468 */ 4469 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1, 4470 /* Write operation. Used to write a new entry to the table. All RW 4471 * fields are written for new entry. Activity bit is set 4472 * for new entries. 4473 */ 4474 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0, 4475 /* Update operation. Used to update an existing route entry and 4476 * only update the RW fields that are detailed in the field 4477 * op_u_mask. If entry doesn't exist, the operation fails. 4478 */ 4479 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1, 4480 /* Clear activity. The Activity bit (the field a) is cleared 4481 * for the entry. 4482 */ 4483 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2, 4484 /* Delete operation. Used to delete an existing entry. If entry 4485 * doesn't exist, the operation fails. 4486 */ 4487 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3, 4488 }; 4489 4490 /* reg_ralue_op 4491 * Operation. 4492 * Access: OP 4493 */ 4494 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3); 4495 4496 /* reg_ralue_a 4497 * Activity. Set for new entries. Set if a packet lookup has hit on the 4498 * specific entry, only if the entry is a route. To clear the a bit, use 4499 * "clear activity" op. 4500 * Enabled by activity_dis in RGCR 4501 * Access: RO 4502 */ 4503 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1); 4504 4505 /* reg_ralue_virtual_router 4506 * Virtual Router ID 4507 * Range is 0..cap_max_virtual_routers-1 4508 * Access: Index 4509 */ 4510 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16); 4511 4512 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0) 4513 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1) 4514 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2) 4515 4516 /* reg_ralue_op_u_mask 4517 * opcode update mask. 4518 * On read operation, this field is reserved. 4519 * This field is valid for update opcode, otherwise - reserved. 4520 * This field is a bitmask of the fields that should be updated. 4521 * Access: WO 4522 */ 4523 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3); 4524 4525 /* reg_ralue_prefix_len 4526 * Number of bits in the prefix of the LPM route. 4527 * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes 4528 * two entries in the physical HW table. 4529 * Access: Index 4530 */ 4531 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8); 4532 4533 /* reg_ralue_dip* 4534 * The prefix of the route or of the marker that the object of the LPM 4535 * is compared with. The most significant bits of the dip are the prefix. 4536 * The list significant bits must be '0' if the prefix_len is smaller 4537 * than 128 for IPv6 or smaller than 32 for IPv4. 4538 * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved. 4539 * Access: Index 4540 */ 4541 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32); 4542 4543 enum mlxsw_reg_ralue_entry_type { 4544 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1, 4545 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2, 4546 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3, 4547 }; 4548 4549 /* reg_ralue_entry_type 4550 * Entry type. 4551 * Note - for Marker entries, the action_type and action fields are reserved. 4552 * Access: RW 4553 */ 4554 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2); 4555 4556 /* reg_ralue_bmp_len 4557 * The best match prefix length in the case that there is no match for 4558 * longer prefixes. 4559 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len 4560 * Note for any update operation with entry_type modification this 4561 * field must be set. 4562 * Access: RW 4563 */ 4564 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8); 4565 4566 enum mlxsw_reg_ralue_action_type { 4567 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE, 4568 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL, 4569 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME, 4570 }; 4571 4572 /* reg_ralue_action_type 4573 * Action Type 4574 * Indicates how the IP address is connected. 4575 * It can be connected to a local subnet through local_erif or can be 4576 * on a remote subnet connected through a next-hop router, 4577 * or transmitted to the CPU. 4578 * Reserved when entry_type = MARKER_ENTRY 4579 * Access: RW 4580 */ 4581 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2); 4582 4583 enum mlxsw_reg_ralue_trap_action { 4584 MLXSW_REG_RALUE_TRAP_ACTION_NOP, 4585 MLXSW_REG_RALUE_TRAP_ACTION_TRAP, 4586 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU, 4587 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR, 4588 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR, 4589 }; 4590 4591 /* reg_ralue_trap_action 4592 * Trap action. 4593 * For IP2ME action, only NOP and MIRROR are possible. 4594 * Access: RW 4595 */ 4596 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4); 4597 4598 /* reg_ralue_trap_id 4599 * Trap ID to be reported to CPU. 4600 * Trap ID is RTR_INGRESS0 or RTR_INGRESS1. 4601 * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved. 4602 * Access: RW 4603 */ 4604 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9); 4605 4606 /* reg_ralue_adjacency_index 4607 * Points to the first entry of the group-based ECMP. 4608 * Only relevant in case of REMOTE action. 4609 * Access: RW 4610 */ 4611 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24); 4612 4613 /* reg_ralue_ecmp_size 4614 * Amount of sequential entries starting 4615 * from the adjacency_index (the number of ECMPs). 4616 * The valid range is 1-64, 512, 1024, 2048 and 4096. 4617 * Reserved when trap_action is TRAP or DISCARD_ERROR. 4618 * Only relevant in case of REMOTE action. 4619 * Access: RW 4620 */ 4621 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13); 4622 4623 /* reg_ralue_local_erif 4624 * Egress Router Interface. 4625 * Only relevant in case of LOCAL action. 4626 * Access: RW 4627 */ 4628 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16); 4629 4630 /* reg_ralue_v 4631 * Valid bit for the tunnel_ptr field. 4632 * If valid = 0 then trap to CPU as IP2ME trap ID. 4633 * If valid = 1 and the packet format allows NVE or IPinIP tunnel 4634 * decapsulation then tunnel decapsulation is done. 4635 * If valid = 1 and packet format does not allow NVE or IPinIP tunnel 4636 * decapsulation then trap as IP2ME trap ID. 4637 * Only relevant in case of IP2ME action. 4638 * Access: RW 4639 */ 4640 MLXSW_ITEM32(reg, ralue, v, 0x24, 31, 1); 4641 4642 /* reg_ralue_tunnel_ptr 4643 * Tunnel Pointer for NVE or IPinIP tunnel decapsulation. 4644 * For Spectrum, pointer to KVD Linear. 4645 * Only relevant in case of IP2ME action. 4646 * Access: RW 4647 */ 4648 MLXSW_ITEM32(reg, ralue, tunnel_ptr, 0x24, 0, 24); 4649 4650 static inline void mlxsw_reg_ralue_pack(char *payload, 4651 enum mlxsw_reg_ralxx_protocol protocol, 4652 enum mlxsw_reg_ralue_op op, 4653 u16 virtual_router, u8 prefix_len) 4654 { 4655 MLXSW_REG_ZERO(ralue, payload); 4656 mlxsw_reg_ralue_protocol_set(payload, protocol); 4657 mlxsw_reg_ralue_op_set(payload, op); 4658 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router); 4659 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len); 4660 mlxsw_reg_ralue_entry_type_set(payload, 4661 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY); 4662 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len); 4663 } 4664 4665 static inline void mlxsw_reg_ralue_pack4(char *payload, 4666 enum mlxsw_reg_ralxx_protocol protocol, 4667 enum mlxsw_reg_ralue_op op, 4668 u16 virtual_router, u8 prefix_len, 4669 u32 dip) 4670 { 4671 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 4672 mlxsw_reg_ralue_dip4_set(payload, dip); 4673 } 4674 4675 static inline void 4676 mlxsw_reg_ralue_act_remote_pack(char *payload, 4677 enum mlxsw_reg_ralue_trap_action trap_action, 4678 u16 trap_id, u32 adjacency_index, u16 ecmp_size) 4679 { 4680 mlxsw_reg_ralue_action_type_set(payload, 4681 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE); 4682 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 4683 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 4684 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index); 4685 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size); 4686 } 4687 4688 static inline void 4689 mlxsw_reg_ralue_act_local_pack(char *payload, 4690 enum mlxsw_reg_ralue_trap_action trap_action, 4691 u16 trap_id, u16 local_erif) 4692 { 4693 mlxsw_reg_ralue_action_type_set(payload, 4694 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL); 4695 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 4696 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 4697 mlxsw_reg_ralue_local_erif_set(payload, local_erif); 4698 } 4699 4700 static inline void 4701 mlxsw_reg_ralue_act_ip2me_pack(char *payload) 4702 { 4703 mlxsw_reg_ralue_action_type_set(payload, 4704 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 4705 } 4706 4707 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register 4708 * ---------------------------------------------------------- 4709 * The RAUHT register is used to configure and query the Unicast Host table in 4710 * devices that implement the Algorithmic LPM. 4711 */ 4712 #define MLXSW_REG_RAUHT_ID 0x8014 4713 #define MLXSW_REG_RAUHT_LEN 0x74 4714 4715 MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN); 4716 4717 enum mlxsw_reg_rauht_type { 4718 MLXSW_REG_RAUHT_TYPE_IPV4, 4719 MLXSW_REG_RAUHT_TYPE_IPV6, 4720 }; 4721 4722 /* reg_rauht_type 4723 * Access: Index 4724 */ 4725 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2); 4726 4727 enum mlxsw_reg_rauht_op { 4728 MLXSW_REG_RAUHT_OP_QUERY_READ = 0, 4729 /* Read operation */ 4730 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1, 4731 /* Clear on read operation. Used to read entry and clear 4732 * activity bit. 4733 */ 4734 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0, 4735 /* Add. Used to write a new entry to the table. All R/W fields are 4736 * relevant for new entry. Activity bit is set for new entries. 4737 */ 4738 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1, 4739 /* Update action. Used to update an existing route entry and 4740 * only update the following fields: 4741 * trap_action, trap_id, mac, counter_set_type, counter_index 4742 */ 4743 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2, 4744 /* Clear activity. A bit is cleared for the entry. */ 4745 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3, 4746 /* Delete entry */ 4747 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4, 4748 /* Delete all host entries on a RIF. In this command, dip 4749 * field is reserved. 4750 */ 4751 }; 4752 4753 /* reg_rauht_op 4754 * Access: OP 4755 */ 4756 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3); 4757 4758 /* reg_rauht_a 4759 * Activity. Set for new entries. Set if a packet lookup has hit on 4760 * the specific entry. 4761 * To clear the a bit, use "clear activity" op. 4762 * Enabled by activity_dis in RGCR 4763 * Access: RO 4764 */ 4765 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1); 4766 4767 /* reg_rauht_rif 4768 * Router Interface 4769 * Access: Index 4770 */ 4771 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16); 4772 4773 /* reg_rauht_dip* 4774 * Destination address. 4775 * Access: Index 4776 */ 4777 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32); 4778 4779 enum mlxsw_reg_rauht_trap_action { 4780 MLXSW_REG_RAUHT_TRAP_ACTION_NOP, 4781 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP, 4782 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU, 4783 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR, 4784 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS, 4785 }; 4786 4787 /* reg_rauht_trap_action 4788 * Access: RW 4789 */ 4790 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4); 4791 4792 enum mlxsw_reg_rauht_trap_id { 4793 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0, 4794 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1, 4795 }; 4796 4797 /* reg_rauht_trap_id 4798 * Trap ID to be reported to CPU. 4799 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 4800 * For trap_action of NOP, MIRROR and DISCARD_ERROR, 4801 * trap_id is reserved. 4802 * Access: RW 4803 */ 4804 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9); 4805 4806 /* reg_rauht_counter_set_type 4807 * Counter set type for flow counters 4808 * Access: RW 4809 */ 4810 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8); 4811 4812 /* reg_rauht_counter_index 4813 * Counter index for flow counters 4814 * Access: RW 4815 */ 4816 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24); 4817 4818 /* reg_rauht_mac 4819 * MAC address. 4820 * Access: RW 4821 */ 4822 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6); 4823 4824 static inline void mlxsw_reg_rauht_pack(char *payload, 4825 enum mlxsw_reg_rauht_op op, u16 rif, 4826 const char *mac) 4827 { 4828 MLXSW_REG_ZERO(rauht, payload); 4829 mlxsw_reg_rauht_op_set(payload, op); 4830 mlxsw_reg_rauht_rif_set(payload, rif); 4831 mlxsw_reg_rauht_mac_memcpy_to(payload, mac); 4832 } 4833 4834 static inline void mlxsw_reg_rauht_pack4(char *payload, 4835 enum mlxsw_reg_rauht_op op, u16 rif, 4836 const char *mac, u32 dip) 4837 { 4838 mlxsw_reg_rauht_pack(payload, op, rif, mac); 4839 mlxsw_reg_rauht_dip4_set(payload, dip); 4840 } 4841 4842 /* RALEU - Router Algorithmic LPM ECMP Update Register 4843 * --------------------------------------------------- 4844 * The register enables updating the ECMP section in the action for multiple 4845 * LPM Unicast entries in a single operation. The update is executed to 4846 * all entries of a {virtual router, protocol} tuple using the same ECMP group. 4847 */ 4848 #define MLXSW_REG_RALEU_ID 0x8015 4849 #define MLXSW_REG_RALEU_LEN 0x28 4850 4851 MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN); 4852 4853 /* reg_raleu_protocol 4854 * Protocol. 4855 * Access: Index 4856 */ 4857 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4); 4858 4859 /* reg_raleu_virtual_router 4860 * Virtual Router ID 4861 * Range is 0..cap_max_virtual_routers-1 4862 * Access: Index 4863 */ 4864 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16); 4865 4866 /* reg_raleu_adjacency_index 4867 * Adjacency Index used for matching on the existing entries. 4868 * Access: Index 4869 */ 4870 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24); 4871 4872 /* reg_raleu_ecmp_size 4873 * ECMP Size used for matching on the existing entries. 4874 * Access: Index 4875 */ 4876 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13); 4877 4878 /* reg_raleu_new_adjacency_index 4879 * New Adjacency Index. 4880 * Access: WO 4881 */ 4882 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24); 4883 4884 /* reg_raleu_new_ecmp_size 4885 * New ECMP Size. 4886 * Access: WO 4887 */ 4888 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13); 4889 4890 static inline void mlxsw_reg_raleu_pack(char *payload, 4891 enum mlxsw_reg_ralxx_protocol protocol, 4892 u16 virtual_router, 4893 u32 adjacency_index, u16 ecmp_size, 4894 u32 new_adjacency_index, 4895 u16 new_ecmp_size) 4896 { 4897 MLXSW_REG_ZERO(raleu, payload); 4898 mlxsw_reg_raleu_protocol_set(payload, protocol); 4899 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router); 4900 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index); 4901 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size); 4902 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index); 4903 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size); 4904 } 4905 4906 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register 4907 * ---------------------------------------------------------------- 4908 * The RAUHTD register allows dumping entries from the Router Unicast Host 4909 * Table. For a given session an entry is dumped no more than one time. The 4910 * first RAUHTD access after reset is a new session. A session ends when the 4911 * num_rec response is smaller than num_rec request or for IPv4 when the 4912 * num_entries is smaller than 4. The clear activity affect the current session 4913 * or the last session if a new session has not started. 4914 */ 4915 #define MLXSW_REG_RAUHTD_ID 0x8018 4916 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20 4917 #define MLXSW_REG_RAUHTD_REC_LEN 0x20 4918 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32 4919 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \ 4920 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN) 4921 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4 4922 4923 MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN); 4924 4925 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0) 4926 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3) 4927 4928 /* reg_rauhtd_filter_fields 4929 * if a bit is '0' then the relevant field is ignored and dump is done 4930 * regardless of the field value 4931 * Bit0 - filter by activity: entry_a 4932 * Bit3 - filter by entry rip: entry_rif 4933 * Access: Index 4934 */ 4935 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8); 4936 4937 enum mlxsw_reg_rauhtd_op { 4938 MLXSW_REG_RAUHTD_OP_DUMP, 4939 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR, 4940 }; 4941 4942 /* reg_rauhtd_op 4943 * Access: OP 4944 */ 4945 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2); 4946 4947 /* reg_rauhtd_num_rec 4948 * At request: number of records requested 4949 * At response: number of records dumped 4950 * For IPv4, each record has 4 entries at request and up to 4 entries 4951 * at response 4952 * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM 4953 * Access: Index 4954 */ 4955 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8); 4956 4957 /* reg_rauhtd_entry_a 4958 * Dump only if activity has value of entry_a 4959 * Reserved if filter_fields bit0 is '0' 4960 * Access: Index 4961 */ 4962 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1); 4963 4964 enum mlxsw_reg_rauhtd_type { 4965 MLXSW_REG_RAUHTD_TYPE_IPV4, 4966 MLXSW_REG_RAUHTD_TYPE_IPV6, 4967 }; 4968 4969 /* reg_rauhtd_type 4970 * Dump only if record type is: 4971 * 0 - IPv4 4972 * 1 - IPv6 4973 * Access: Index 4974 */ 4975 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4); 4976 4977 /* reg_rauhtd_entry_rif 4978 * Dump only if RIF has value of entry_rif 4979 * Reserved if filter_fields bit3 is '0' 4980 * Access: Index 4981 */ 4982 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16); 4983 4984 static inline void mlxsw_reg_rauhtd_pack(char *payload, 4985 enum mlxsw_reg_rauhtd_type type) 4986 { 4987 MLXSW_REG_ZERO(rauhtd, payload); 4988 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A); 4989 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR); 4990 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM); 4991 mlxsw_reg_rauhtd_entry_a_set(payload, 1); 4992 mlxsw_reg_rauhtd_type_set(payload, type); 4993 } 4994 4995 /* reg_rauhtd_ipv4_rec_num_entries 4996 * Number of valid entries in this record: 4997 * 0 - 1 valid entry 4998 * 1 - 2 valid entries 4999 * 2 - 3 valid entries 5000 * 3 - 4 valid entries 5001 * Access: RO 5002 */ 5003 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries, 5004 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2, 5005 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 5006 5007 /* reg_rauhtd_rec_type 5008 * Record type. 5009 * 0 - IPv4 5010 * 1 - IPv6 5011 * Access: RO 5012 */ 5013 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2, 5014 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 5015 5016 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8 5017 5018 /* reg_rauhtd_ipv4_ent_a 5019 * Activity. Set for new entries. Set if a packet lookup has hit on the 5020 * specific entry. 5021 * Access: RO 5022 */ 5023 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 5024 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 5025 5026 /* reg_rauhtd_ipv4_ent_rif 5027 * Router interface. 5028 * Access: RO 5029 */ 5030 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 5031 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 5032 5033 /* reg_rauhtd_ipv4_ent_dip 5034 * Destination IPv4 address. 5035 * Access: RO 5036 */ 5037 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0, 5038 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false); 5039 5040 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload, 5041 int ent_index, u16 *p_rif, 5042 u32 *p_dip) 5043 { 5044 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index); 5045 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index); 5046 } 5047 5048 /* MFCR - Management Fan Control Register 5049 * -------------------------------------- 5050 * This register controls the settings of the Fan Speed PWM mechanism. 5051 */ 5052 #define MLXSW_REG_MFCR_ID 0x9001 5053 #define MLXSW_REG_MFCR_LEN 0x08 5054 5055 MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN); 5056 5057 enum mlxsw_reg_mfcr_pwm_frequency { 5058 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00, 5059 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01, 5060 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02, 5061 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40, 5062 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41, 5063 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42, 5064 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43, 5065 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44, 5066 }; 5067 5068 /* reg_mfcr_pwm_frequency 5069 * Controls the frequency of the PWM signal. 5070 * Access: RW 5071 */ 5072 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7); 5073 5074 #define MLXSW_MFCR_TACHOS_MAX 10 5075 5076 /* reg_mfcr_tacho_active 5077 * Indicates which of the tachometer is active (bit per tachometer). 5078 * Access: RO 5079 */ 5080 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX); 5081 5082 #define MLXSW_MFCR_PWMS_MAX 5 5083 5084 /* reg_mfcr_pwm_active 5085 * Indicates which of the PWM control is active (bit per PWM). 5086 * Access: RO 5087 */ 5088 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX); 5089 5090 static inline void 5091 mlxsw_reg_mfcr_pack(char *payload, 5092 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency) 5093 { 5094 MLXSW_REG_ZERO(mfcr, payload); 5095 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency); 5096 } 5097 5098 static inline void 5099 mlxsw_reg_mfcr_unpack(char *payload, 5100 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency, 5101 u16 *p_tacho_active, u8 *p_pwm_active) 5102 { 5103 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload); 5104 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload); 5105 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload); 5106 } 5107 5108 /* MFSC - Management Fan Speed Control Register 5109 * -------------------------------------------- 5110 * This register controls the settings of the Fan Speed PWM mechanism. 5111 */ 5112 #define MLXSW_REG_MFSC_ID 0x9002 5113 #define MLXSW_REG_MFSC_LEN 0x08 5114 5115 MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN); 5116 5117 /* reg_mfsc_pwm 5118 * Fan pwm to control / monitor. 5119 * Access: Index 5120 */ 5121 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3); 5122 5123 /* reg_mfsc_pwm_duty_cycle 5124 * Controls the duty cycle of the PWM. Value range from 0..255 to 5125 * represent duty cycle of 0%...100%. 5126 * Access: RW 5127 */ 5128 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8); 5129 5130 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm, 5131 u8 pwm_duty_cycle) 5132 { 5133 MLXSW_REG_ZERO(mfsc, payload); 5134 mlxsw_reg_mfsc_pwm_set(payload, pwm); 5135 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle); 5136 } 5137 5138 /* MFSM - Management Fan Speed Measurement 5139 * --------------------------------------- 5140 * This register controls the settings of the Tacho measurements and 5141 * enables reading the Tachometer measurements. 5142 */ 5143 #define MLXSW_REG_MFSM_ID 0x9003 5144 #define MLXSW_REG_MFSM_LEN 0x08 5145 5146 MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN); 5147 5148 /* reg_mfsm_tacho 5149 * Fan tachometer index. 5150 * Access: Index 5151 */ 5152 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4); 5153 5154 /* reg_mfsm_rpm 5155 * Fan speed (round per minute). 5156 * Access: RO 5157 */ 5158 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16); 5159 5160 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho) 5161 { 5162 MLXSW_REG_ZERO(mfsm, payload); 5163 mlxsw_reg_mfsm_tacho_set(payload, tacho); 5164 } 5165 5166 /* MFSL - Management Fan Speed Limit Register 5167 * ------------------------------------------ 5168 * The Fan Speed Limit register is used to configure the fan speed 5169 * event / interrupt notification mechanism. Fan speed threshold are 5170 * defined for both under-speed and over-speed. 5171 */ 5172 #define MLXSW_REG_MFSL_ID 0x9004 5173 #define MLXSW_REG_MFSL_LEN 0x0C 5174 5175 MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN); 5176 5177 /* reg_mfsl_tacho 5178 * Fan tachometer index. 5179 * Access: Index 5180 */ 5181 MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4); 5182 5183 /* reg_mfsl_tach_min 5184 * Tachometer minimum value (minimum RPM). 5185 * Access: RW 5186 */ 5187 MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16); 5188 5189 /* reg_mfsl_tach_max 5190 * Tachometer maximum value (maximum RPM). 5191 * Access: RW 5192 */ 5193 MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16); 5194 5195 static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho, 5196 u16 tach_min, u16 tach_max) 5197 { 5198 MLXSW_REG_ZERO(mfsl, payload); 5199 mlxsw_reg_mfsl_tacho_set(payload, tacho); 5200 mlxsw_reg_mfsl_tach_min_set(payload, tach_min); 5201 mlxsw_reg_mfsl_tach_max_set(payload, tach_max); 5202 } 5203 5204 static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho, 5205 u16 *p_tach_min, u16 *p_tach_max) 5206 { 5207 if (p_tach_min) 5208 *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload); 5209 5210 if (p_tach_max) 5211 *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload); 5212 } 5213 5214 /* MTCAP - Management Temperature Capabilities 5215 * ------------------------------------------- 5216 * This register exposes the capabilities of the device and 5217 * system temperature sensing. 5218 */ 5219 #define MLXSW_REG_MTCAP_ID 0x9009 5220 #define MLXSW_REG_MTCAP_LEN 0x08 5221 5222 MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN); 5223 5224 /* reg_mtcap_sensor_count 5225 * Number of sensors supported by the device. 5226 * This includes the QSFP module sensors (if exists in the QSFP module). 5227 * Access: RO 5228 */ 5229 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7); 5230 5231 /* MTMP - Management Temperature 5232 * ----------------------------- 5233 * This register controls the settings of the temperature measurements 5234 * and enables reading the temperature measurements. Note that temperature 5235 * is in 0.125 degrees Celsius. 5236 */ 5237 #define MLXSW_REG_MTMP_ID 0x900A 5238 #define MLXSW_REG_MTMP_LEN 0x20 5239 5240 MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN); 5241 5242 /* reg_mtmp_sensor_index 5243 * Sensors index to access. 5244 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially 5245 * (module 0 is mapped to sensor_index 64). 5246 * Access: Index 5247 */ 5248 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 7); 5249 5250 /* Convert to milli degrees Celsius */ 5251 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) (val * 125) 5252 5253 /* reg_mtmp_temperature 5254 * Temperature reading from the sensor. Reading is in 0.125 Celsius 5255 * degrees units. 5256 * Access: RO 5257 */ 5258 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16); 5259 5260 /* reg_mtmp_mte 5261 * Max Temperature Enable - enables measuring the max temperature on a sensor. 5262 * Access: RW 5263 */ 5264 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1); 5265 5266 /* reg_mtmp_mtr 5267 * Max Temperature Reset - clears the value of the max temperature register. 5268 * Access: WO 5269 */ 5270 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1); 5271 5272 /* reg_mtmp_max_temperature 5273 * The highest measured temperature from the sensor. 5274 * When the bit mte is cleared, the field max_temperature is reserved. 5275 * Access: RO 5276 */ 5277 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16); 5278 5279 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8 5280 5281 /* reg_mtmp_sensor_name 5282 * Sensor Name 5283 * Access: RO 5284 */ 5285 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE); 5286 5287 static inline void mlxsw_reg_mtmp_pack(char *payload, u8 sensor_index, 5288 bool max_temp_enable, 5289 bool max_temp_reset) 5290 { 5291 MLXSW_REG_ZERO(mtmp, payload); 5292 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index); 5293 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable); 5294 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset); 5295 } 5296 5297 static inline void mlxsw_reg_mtmp_unpack(char *payload, unsigned int *p_temp, 5298 unsigned int *p_max_temp, 5299 char *sensor_name) 5300 { 5301 u16 temp; 5302 5303 if (p_temp) { 5304 temp = mlxsw_reg_mtmp_temperature_get(payload); 5305 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 5306 } 5307 if (p_max_temp) { 5308 temp = mlxsw_reg_mtmp_max_temperature_get(payload); 5309 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 5310 } 5311 if (sensor_name) 5312 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name); 5313 } 5314 5315 /* MPAT - Monitoring Port Analyzer Table 5316 * ------------------------------------- 5317 * MPAT Register is used to query and configure the Switch PortAnalyzer Table. 5318 * For an enabled analyzer, all fields except e (enable) cannot be modified. 5319 */ 5320 #define MLXSW_REG_MPAT_ID 0x901A 5321 #define MLXSW_REG_MPAT_LEN 0x78 5322 5323 MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN); 5324 5325 /* reg_mpat_pa_id 5326 * Port Analyzer ID. 5327 * Access: Index 5328 */ 5329 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4); 5330 5331 /* reg_mpat_system_port 5332 * A unique port identifier for the final destination of the packet. 5333 * Access: RW 5334 */ 5335 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16); 5336 5337 /* reg_mpat_e 5338 * Enable. Indicating the Port Analyzer is enabled. 5339 * Access: RW 5340 */ 5341 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1); 5342 5343 /* reg_mpat_qos 5344 * Quality Of Service Mode. 5345 * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation 5346 * PCP, DEI, DSCP or VL) are configured. 5347 * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the 5348 * same as in the original packet that has triggered the mirroring. For 5349 * SPAN also the pcp,dei are maintained. 5350 * Access: RW 5351 */ 5352 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1); 5353 5354 /* reg_mpat_be 5355 * Best effort mode. Indicates mirroring traffic should not cause packet 5356 * drop or back pressure, but will discard the mirrored packets. Mirrored 5357 * packets will be forwarded on a best effort manner. 5358 * 0: Do not discard mirrored packets 5359 * 1: Discard mirrored packets if causing congestion 5360 * Access: RW 5361 */ 5362 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1); 5363 5364 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id, 5365 u16 system_port, bool e) 5366 { 5367 MLXSW_REG_ZERO(mpat, payload); 5368 mlxsw_reg_mpat_pa_id_set(payload, pa_id); 5369 mlxsw_reg_mpat_system_port_set(payload, system_port); 5370 mlxsw_reg_mpat_e_set(payload, e); 5371 mlxsw_reg_mpat_qos_set(payload, 1); 5372 mlxsw_reg_mpat_be_set(payload, 1); 5373 } 5374 5375 /* MPAR - Monitoring Port Analyzer Register 5376 * ---------------------------------------- 5377 * MPAR register is used to query and configure the port analyzer port mirroring 5378 * properties. 5379 */ 5380 #define MLXSW_REG_MPAR_ID 0x901B 5381 #define MLXSW_REG_MPAR_LEN 0x08 5382 5383 MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN); 5384 5385 /* reg_mpar_local_port 5386 * The local port to mirror the packets from. 5387 * Access: Index 5388 */ 5389 MLXSW_ITEM32(reg, mpar, local_port, 0x00, 16, 8); 5390 5391 enum mlxsw_reg_mpar_i_e { 5392 MLXSW_REG_MPAR_TYPE_EGRESS, 5393 MLXSW_REG_MPAR_TYPE_INGRESS, 5394 }; 5395 5396 /* reg_mpar_i_e 5397 * Ingress/Egress 5398 * Access: Index 5399 */ 5400 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4); 5401 5402 /* reg_mpar_enable 5403 * Enable mirroring 5404 * By default, port mirroring is disabled for all ports. 5405 * Access: RW 5406 */ 5407 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1); 5408 5409 /* reg_mpar_pa_id 5410 * Port Analyzer ID. 5411 * Access: RW 5412 */ 5413 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4); 5414 5415 static inline void mlxsw_reg_mpar_pack(char *payload, u8 local_port, 5416 enum mlxsw_reg_mpar_i_e i_e, 5417 bool enable, u8 pa_id) 5418 { 5419 MLXSW_REG_ZERO(mpar, payload); 5420 mlxsw_reg_mpar_local_port_set(payload, local_port); 5421 mlxsw_reg_mpar_enable_set(payload, enable); 5422 mlxsw_reg_mpar_i_e_set(payload, i_e); 5423 mlxsw_reg_mpar_pa_id_set(payload, pa_id); 5424 } 5425 5426 /* MLCR - Management LED Control Register 5427 * -------------------------------------- 5428 * Controls the system LEDs. 5429 */ 5430 #define MLXSW_REG_MLCR_ID 0x902B 5431 #define MLXSW_REG_MLCR_LEN 0x0C 5432 5433 MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN); 5434 5435 /* reg_mlcr_local_port 5436 * Local port number. 5437 * Access: RW 5438 */ 5439 MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8); 5440 5441 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF 5442 5443 /* reg_mlcr_beacon_duration 5444 * Duration of the beacon to be active, in seconds. 5445 * 0x0 - Will turn off the beacon. 5446 * 0xFFFF - Will turn on the beacon until explicitly turned off. 5447 * Access: RW 5448 */ 5449 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16); 5450 5451 /* reg_mlcr_beacon_remain 5452 * Remaining duration of the beacon, in seconds. 5453 * 0xFFFF indicates an infinite amount of time. 5454 * Access: RO 5455 */ 5456 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16); 5457 5458 static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port, 5459 bool active) 5460 { 5461 MLXSW_REG_ZERO(mlcr, payload); 5462 mlxsw_reg_mlcr_local_port_set(payload, local_port); 5463 mlxsw_reg_mlcr_beacon_duration_set(payload, active ? 5464 MLXSW_REG_MLCR_DURATION_MAX : 0); 5465 } 5466 5467 /* MPSC - Monitoring Packet Sampling Configuration Register 5468 * -------------------------------------------------------- 5469 * MPSC Register is used to configure the Packet Sampling mechanism. 5470 */ 5471 #define MLXSW_REG_MPSC_ID 0x9080 5472 #define MLXSW_REG_MPSC_LEN 0x1C 5473 5474 MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN); 5475 5476 /* reg_mpsc_local_port 5477 * Local port number 5478 * Not supported for CPU port 5479 * Access: Index 5480 */ 5481 MLXSW_ITEM32(reg, mpsc, local_port, 0x00, 16, 8); 5482 5483 /* reg_mpsc_e 5484 * Enable sampling on port local_port 5485 * Access: RW 5486 */ 5487 MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1); 5488 5489 #define MLXSW_REG_MPSC_RATE_MAX 3500000000UL 5490 5491 /* reg_mpsc_rate 5492 * Sampling rate = 1 out of rate packets (with randomization around 5493 * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX 5494 * Access: RW 5495 */ 5496 MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32); 5497 5498 static inline void mlxsw_reg_mpsc_pack(char *payload, u8 local_port, bool e, 5499 u32 rate) 5500 { 5501 MLXSW_REG_ZERO(mpsc, payload); 5502 mlxsw_reg_mpsc_local_port_set(payload, local_port); 5503 mlxsw_reg_mpsc_e_set(payload, e); 5504 mlxsw_reg_mpsc_rate_set(payload, rate); 5505 } 5506 5507 /* SBPR - Shared Buffer Pools Register 5508 * ----------------------------------- 5509 * The SBPR configures and retrieves the shared buffer pools and configuration. 5510 */ 5511 #define MLXSW_REG_SBPR_ID 0xB001 5512 #define MLXSW_REG_SBPR_LEN 0x14 5513 5514 MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN); 5515 5516 /* shared direstion enum for SBPR, SBCM, SBPM */ 5517 enum mlxsw_reg_sbxx_dir { 5518 MLXSW_REG_SBXX_DIR_INGRESS, 5519 MLXSW_REG_SBXX_DIR_EGRESS, 5520 }; 5521 5522 /* reg_sbpr_dir 5523 * Direction. 5524 * Access: Index 5525 */ 5526 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2); 5527 5528 /* reg_sbpr_pool 5529 * Pool index. 5530 * Access: Index 5531 */ 5532 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4); 5533 5534 /* reg_sbpr_size 5535 * Pool size in buffer cells. 5536 * Access: RW 5537 */ 5538 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24); 5539 5540 enum mlxsw_reg_sbpr_mode { 5541 MLXSW_REG_SBPR_MODE_STATIC, 5542 MLXSW_REG_SBPR_MODE_DYNAMIC, 5543 }; 5544 5545 /* reg_sbpr_mode 5546 * Pool quota calculation mode. 5547 * Access: RW 5548 */ 5549 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4); 5550 5551 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool, 5552 enum mlxsw_reg_sbxx_dir dir, 5553 enum mlxsw_reg_sbpr_mode mode, u32 size) 5554 { 5555 MLXSW_REG_ZERO(sbpr, payload); 5556 mlxsw_reg_sbpr_pool_set(payload, pool); 5557 mlxsw_reg_sbpr_dir_set(payload, dir); 5558 mlxsw_reg_sbpr_mode_set(payload, mode); 5559 mlxsw_reg_sbpr_size_set(payload, size); 5560 } 5561 5562 /* SBCM - Shared Buffer Class Management Register 5563 * ---------------------------------------------- 5564 * The SBCM register configures and retrieves the shared buffer allocation 5565 * and configuration according to Port-PG, including the binding to pool 5566 * and definition of the associated quota. 5567 */ 5568 #define MLXSW_REG_SBCM_ID 0xB002 5569 #define MLXSW_REG_SBCM_LEN 0x28 5570 5571 MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN); 5572 5573 /* reg_sbcm_local_port 5574 * Local port number. 5575 * For Ingress: excludes CPU port and Router port 5576 * For Egress: excludes IP Router 5577 * Access: Index 5578 */ 5579 MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8); 5580 5581 /* reg_sbcm_pg_buff 5582 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress) 5583 * For PG buffer: range is 0..cap_max_pg_buffers - 1 5584 * For traffic class: range is 0..cap_max_tclass - 1 5585 * Note that when traffic class is in MC aware mode then the traffic 5586 * classes which are MC aware cannot be configured. 5587 * Access: Index 5588 */ 5589 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6); 5590 5591 /* reg_sbcm_dir 5592 * Direction. 5593 * Access: Index 5594 */ 5595 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2); 5596 5597 /* reg_sbcm_min_buff 5598 * Minimum buffer size for the limiter, in cells. 5599 * Access: RW 5600 */ 5601 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24); 5602 5603 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */ 5604 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1 5605 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14 5606 5607 /* reg_sbcm_max_buff 5608 * When the pool associated to the port-pg/tclass is configured to 5609 * static, Maximum buffer size for the limiter configured in cells. 5610 * When the pool associated to the port-pg/tclass is configured to 5611 * dynamic, the max_buff holds the "alpha" parameter, supporting 5612 * the following values: 5613 * 0: 0 5614 * i: (1/128)*2^(i-1), for i=1..14 5615 * 0xFF: Infinity 5616 * Access: RW 5617 */ 5618 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24); 5619 5620 /* reg_sbcm_pool 5621 * Association of the port-priority to a pool. 5622 * Access: RW 5623 */ 5624 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4); 5625 5626 static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff, 5627 enum mlxsw_reg_sbxx_dir dir, 5628 u32 min_buff, u32 max_buff, u8 pool) 5629 { 5630 MLXSW_REG_ZERO(sbcm, payload); 5631 mlxsw_reg_sbcm_local_port_set(payload, local_port); 5632 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff); 5633 mlxsw_reg_sbcm_dir_set(payload, dir); 5634 mlxsw_reg_sbcm_min_buff_set(payload, min_buff); 5635 mlxsw_reg_sbcm_max_buff_set(payload, max_buff); 5636 mlxsw_reg_sbcm_pool_set(payload, pool); 5637 } 5638 5639 /* SBPM - Shared Buffer Port Management Register 5640 * --------------------------------------------- 5641 * The SBPM register configures and retrieves the shared buffer allocation 5642 * and configuration according to Port-Pool, including the definition 5643 * of the associated quota. 5644 */ 5645 #define MLXSW_REG_SBPM_ID 0xB003 5646 #define MLXSW_REG_SBPM_LEN 0x28 5647 5648 MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN); 5649 5650 /* reg_sbpm_local_port 5651 * Local port number. 5652 * For Ingress: excludes CPU port and Router port 5653 * For Egress: excludes IP Router 5654 * Access: Index 5655 */ 5656 MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8); 5657 5658 /* reg_sbpm_pool 5659 * The pool associated to quota counting on the local_port. 5660 * Access: Index 5661 */ 5662 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4); 5663 5664 /* reg_sbpm_dir 5665 * Direction. 5666 * Access: Index 5667 */ 5668 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2); 5669 5670 /* reg_sbpm_buff_occupancy 5671 * Current buffer occupancy in cells. 5672 * Access: RO 5673 */ 5674 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24); 5675 5676 /* reg_sbpm_clr 5677 * Clear Max Buffer Occupancy 5678 * When this bit is set, max_buff_occupancy field is cleared (and a 5679 * new max value is tracked from the time the clear was performed). 5680 * Access: OP 5681 */ 5682 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1); 5683 5684 /* reg_sbpm_max_buff_occupancy 5685 * Maximum value of buffer occupancy in cells monitored. Cleared by 5686 * writing to the clr field. 5687 * Access: RO 5688 */ 5689 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24); 5690 5691 /* reg_sbpm_min_buff 5692 * Minimum buffer size for the limiter, in cells. 5693 * Access: RW 5694 */ 5695 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24); 5696 5697 /* reg_sbpm_max_buff 5698 * When the pool associated to the port-pg/tclass is configured to 5699 * static, Maximum buffer size for the limiter configured in cells. 5700 * When the pool associated to the port-pg/tclass is configured to 5701 * dynamic, the max_buff holds the "alpha" parameter, supporting 5702 * the following values: 5703 * 0: 0 5704 * i: (1/128)*2^(i-1), for i=1..14 5705 * 0xFF: Infinity 5706 * Access: RW 5707 */ 5708 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24); 5709 5710 static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool, 5711 enum mlxsw_reg_sbxx_dir dir, bool clr, 5712 u32 min_buff, u32 max_buff) 5713 { 5714 MLXSW_REG_ZERO(sbpm, payload); 5715 mlxsw_reg_sbpm_local_port_set(payload, local_port); 5716 mlxsw_reg_sbpm_pool_set(payload, pool); 5717 mlxsw_reg_sbpm_dir_set(payload, dir); 5718 mlxsw_reg_sbpm_clr_set(payload, clr); 5719 mlxsw_reg_sbpm_min_buff_set(payload, min_buff); 5720 mlxsw_reg_sbpm_max_buff_set(payload, max_buff); 5721 } 5722 5723 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy, 5724 u32 *p_max_buff_occupancy) 5725 { 5726 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload); 5727 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload); 5728 } 5729 5730 /* SBMM - Shared Buffer Multicast Management Register 5731 * -------------------------------------------------- 5732 * The SBMM register configures and retrieves the shared buffer allocation 5733 * and configuration for MC packets according to Switch-Priority, including 5734 * the binding to pool and definition of the associated quota. 5735 */ 5736 #define MLXSW_REG_SBMM_ID 0xB004 5737 #define MLXSW_REG_SBMM_LEN 0x28 5738 5739 MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN); 5740 5741 /* reg_sbmm_prio 5742 * Switch Priority. 5743 * Access: Index 5744 */ 5745 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4); 5746 5747 /* reg_sbmm_min_buff 5748 * Minimum buffer size for the limiter, in cells. 5749 * Access: RW 5750 */ 5751 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24); 5752 5753 /* reg_sbmm_max_buff 5754 * When the pool associated to the port-pg/tclass is configured to 5755 * static, Maximum buffer size for the limiter configured in cells. 5756 * When the pool associated to the port-pg/tclass is configured to 5757 * dynamic, the max_buff holds the "alpha" parameter, supporting 5758 * the following values: 5759 * 0: 0 5760 * i: (1/128)*2^(i-1), for i=1..14 5761 * 0xFF: Infinity 5762 * Access: RW 5763 */ 5764 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24); 5765 5766 /* reg_sbmm_pool 5767 * Association of the port-priority to a pool. 5768 * Access: RW 5769 */ 5770 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4); 5771 5772 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff, 5773 u32 max_buff, u8 pool) 5774 { 5775 MLXSW_REG_ZERO(sbmm, payload); 5776 mlxsw_reg_sbmm_prio_set(payload, prio); 5777 mlxsw_reg_sbmm_min_buff_set(payload, min_buff); 5778 mlxsw_reg_sbmm_max_buff_set(payload, max_buff); 5779 mlxsw_reg_sbmm_pool_set(payload, pool); 5780 } 5781 5782 /* SBSR - Shared Buffer Status Register 5783 * ------------------------------------ 5784 * The SBSR register retrieves the shared buffer occupancy according to 5785 * Port-Pool. Note that this register enables reading a large amount of data. 5786 * It is the user's responsibility to limit the amount of data to ensure the 5787 * response can match the maximum transfer unit. In case the response exceeds 5788 * the maximum transport unit, it will be truncated with no special notice. 5789 */ 5790 #define MLXSW_REG_SBSR_ID 0xB005 5791 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */ 5792 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */ 5793 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120 5794 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \ 5795 MLXSW_REG_SBSR_REC_LEN * \ 5796 MLXSW_REG_SBSR_REC_MAX_COUNT) 5797 5798 MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN); 5799 5800 /* reg_sbsr_clr 5801 * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy 5802 * field is cleared (and a new max value is tracked from the time the clear 5803 * was performed). 5804 * Access: OP 5805 */ 5806 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1); 5807 5808 /* reg_sbsr_ingress_port_mask 5809 * Bit vector for all ingress network ports. 5810 * Indicates which of the ports (for which the relevant bit is set) 5811 * are affected by the set operation. Configuration of any other port 5812 * does not change. 5813 * Access: Index 5814 */ 5815 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1); 5816 5817 /* reg_sbsr_pg_buff_mask 5818 * Bit vector for all switch priority groups. 5819 * Indicates which of the priorities (for which the relevant bit is set) 5820 * are affected by the set operation. Configuration of any other priority 5821 * does not change. 5822 * Range is 0..cap_max_pg_buffers - 1 5823 * Access: Index 5824 */ 5825 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1); 5826 5827 /* reg_sbsr_egress_port_mask 5828 * Bit vector for all egress network ports. 5829 * Indicates which of the ports (for which the relevant bit is set) 5830 * are affected by the set operation. Configuration of any other port 5831 * does not change. 5832 * Access: Index 5833 */ 5834 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1); 5835 5836 /* reg_sbsr_tclass_mask 5837 * Bit vector for all traffic classes. 5838 * Indicates which of the traffic classes (for which the relevant bit is 5839 * set) are affected by the set operation. Configuration of any other 5840 * traffic class does not change. 5841 * Range is 0..cap_max_tclass - 1 5842 * Access: Index 5843 */ 5844 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1); 5845 5846 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr) 5847 { 5848 MLXSW_REG_ZERO(sbsr, payload); 5849 mlxsw_reg_sbsr_clr_set(payload, clr); 5850 } 5851 5852 /* reg_sbsr_rec_buff_occupancy 5853 * Current buffer occupancy in cells. 5854 * Access: RO 5855 */ 5856 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 5857 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false); 5858 5859 /* reg_sbsr_rec_max_buff_occupancy 5860 * Maximum value of buffer occupancy in cells monitored. Cleared by 5861 * writing to the clr field. 5862 * Access: RO 5863 */ 5864 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 5865 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false); 5866 5867 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index, 5868 u32 *p_buff_occupancy, 5869 u32 *p_max_buff_occupancy) 5870 { 5871 *p_buff_occupancy = 5872 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index); 5873 *p_max_buff_occupancy = 5874 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index); 5875 } 5876 5877 /* SBIB - Shared Buffer Internal Buffer Register 5878 * --------------------------------------------- 5879 * The SBIB register configures per port buffers for internal use. The internal 5880 * buffers consume memory on the port buffers (note that the port buffers are 5881 * used also by PBMC). 5882 * 5883 * For Spectrum this is used for egress mirroring. 5884 */ 5885 #define MLXSW_REG_SBIB_ID 0xB006 5886 #define MLXSW_REG_SBIB_LEN 0x10 5887 5888 MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN); 5889 5890 /* reg_sbib_local_port 5891 * Local port number 5892 * Not supported for CPU port and router port 5893 * Access: Index 5894 */ 5895 MLXSW_ITEM32(reg, sbib, local_port, 0x00, 16, 8); 5896 5897 /* reg_sbib_buff_size 5898 * Units represented in cells 5899 * Allowed range is 0 to (cap_max_headroom_size - 1) 5900 * Default is 0 5901 * Access: RW 5902 */ 5903 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24); 5904 5905 static inline void mlxsw_reg_sbib_pack(char *payload, u8 local_port, 5906 u32 buff_size) 5907 { 5908 MLXSW_REG_ZERO(sbib, payload); 5909 mlxsw_reg_sbib_local_port_set(payload, local_port); 5910 mlxsw_reg_sbib_buff_size_set(payload, buff_size); 5911 } 5912 5913 static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { 5914 MLXSW_REG(sgcr), 5915 MLXSW_REG(spad), 5916 MLXSW_REG(smid), 5917 MLXSW_REG(sspr), 5918 MLXSW_REG(sfdat), 5919 MLXSW_REG(sfd), 5920 MLXSW_REG(sfn), 5921 MLXSW_REG(spms), 5922 MLXSW_REG(spvid), 5923 MLXSW_REG(spvm), 5924 MLXSW_REG(spaft), 5925 MLXSW_REG(sfgc), 5926 MLXSW_REG(sftr), 5927 MLXSW_REG(sfdf), 5928 MLXSW_REG(sldr), 5929 MLXSW_REG(slcr), 5930 MLXSW_REG(slcor), 5931 MLXSW_REG(spmlr), 5932 MLXSW_REG(svfa), 5933 MLXSW_REG(svpe), 5934 MLXSW_REG(sfmr), 5935 MLXSW_REG(spvmlr), 5936 MLXSW_REG(ppbt), 5937 MLXSW_REG(pacl), 5938 MLXSW_REG(pagt), 5939 MLXSW_REG(ptar), 5940 MLXSW_REG(ppbs), 5941 MLXSW_REG(prcr), 5942 MLXSW_REG(pefa), 5943 MLXSW_REG(ptce2), 5944 MLXSW_REG(qpcr), 5945 MLXSW_REG(qtct), 5946 MLXSW_REG(qeec), 5947 MLXSW_REG(pmlp), 5948 MLXSW_REG(pmtu), 5949 MLXSW_REG(ptys), 5950 MLXSW_REG(ppad), 5951 MLXSW_REG(paos), 5952 MLXSW_REG(pfcc), 5953 MLXSW_REG(ppcnt), 5954 MLXSW_REG(plib), 5955 MLXSW_REG(pptb), 5956 MLXSW_REG(pbmc), 5957 MLXSW_REG(pspa), 5958 MLXSW_REG(htgt), 5959 MLXSW_REG(hpkt), 5960 MLXSW_REG(rgcr), 5961 MLXSW_REG(ritr), 5962 MLXSW_REG(ratr), 5963 MLXSW_REG(ralta), 5964 MLXSW_REG(ralst), 5965 MLXSW_REG(raltb), 5966 MLXSW_REG(ralue), 5967 MLXSW_REG(rauht), 5968 MLXSW_REG(raleu), 5969 MLXSW_REG(rauhtd), 5970 MLXSW_REG(mfcr), 5971 MLXSW_REG(mfsc), 5972 MLXSW_REG(mfsm), 5973 MLXSW_REG(mfsl), 5974 MLXSW_REG(mtcap), 5975 MLXSW_REG(mtmp), 5976 MLXSW_REG(mpat), 5977 MLXSW_REG(mpar), 5978 MLXSW_REG(mlcr), 5979 MLXSW_REG(mpsc), 5980 MLXSW_REG(sbpr), 5981 MLXSW_REG(sbcm), 5982 MLXSW_REG(sbpm), 5983 MLXSW_REG(sbmm), 5984 MLXSW_REG(sbsr), 5985 MLXSW_REG(sbib), 5986 }; 5987 5988 static inline const char *mlxsw_reg_id_str(u16 reg_id) 5989 { 5990 const struct mlxsw_reg_info *reg_info; 5991 int i; 5992 5993 for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) { 5994 reg_info = mlxsw_reg_infos[i]; 5995 if (reg_info->id == reg_id) 5996 return reg_info->name; 5997 } 5998 return "*UNKNOWN*"; 5999 } 6000 6001 /* PUDE - Port Up / Down Event 6002 * --------------------------- 6003 * Reports the operational state change of a port. 6004 */ 6005 #define MLXSW_REG_PUDE_LEN 0x10 6006 6007 /* reg_pude_swid 6008 * Switch partition ID with which to associate the port. 6009 * Access: Index 6010 */ 6011 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8); 6012 6013 /* reg_pude_local_port 6014 * Local port number. 6015 * Access: Index 6016 */ 6017 MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8); 6018 6019 /* reg_pude_admin_status 6020 * Port administrative state (the desired state). 6021 * 1 - Up. 6022 * 2 - Down. 6023 * 3 - Up once. This means that in case of link failure, the port won't go 6024 * into polling mode, but will wait to be re-enabled by software. 6025 * 4 - Disabled by system. Can only be set by hardware. 6026 * Access: RO 6027 */ 6028 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4); 6029 6030 /* reg_pude_oper_status 6031 * Port operatioanl state. 6032 * 1 - Up. 6033 * 2 - Down. 6034 * 3 - Down by port failure. This means that the device will not let the 6035 * port up again until explicitly specified by software. 6036 * Access: RO 6037 */ 6038 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4); 6039 6040 #endif 6041