1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #ifndef _MLXSW_REG_H 5 #define _MLXSW_REG_H 6 7 #include <linux/kernel.h> 8 #include <linux/string.h> 9 #include <linux/bitops.h> 10 #include <linux/if_vlan.h> 11 12 #include "item.h" 13 #include "port.h" 14 15 struct mlxsw_reg_info { 16 u16 id; 17 u16 len; /* In u8 */ 18 const char *name; 19 }; 20 21 #define MLXSW_REG_DEFINE(_name, _id, _len) \ 22 static const struct mlxsw_reg_info mlxsw_reg_##_name = { \ 23 .id = _id, \ 24 .len = _len, \ 25 .name = #_name, \ 26 } 27 28 #define MLXSW_REG(type) (&mlxsw_reg_##type) 29 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len 30 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len) 31 32 /* SGCR - Switch General Configuration Register 33 * -------------------------------------------- 34 * This register is used for configuration of the switch capabilities. 35 */ 36 #define MLXSW_REG_SGCR_ID 0x2000 37 #define MLXSW_REG_SGCR_LEN 0x10 38 39 MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN); 40 41 /* reg_sgcr_llb 42 * Link Local Broadcast (Default=0) 43 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast 44 * packets and ignore the IGMP snooping entries. 45 * Access: RW 46 */ 47 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1); 48 49 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb) 50 { 51 MLXSW_REG_ZERO(sgcr, payload); 52 mlxsw_reg_sgcr_llb_set(payload, !!llb); 53 } 54 55 /* SPAD - Switch Physical Address Register 56 * --------------------------------------- 57 * The SPAD register configures the switch physical MAC address. 58 */ 59 #define MLXSW_REG_SPAD_ID 0x2002 60 #define MLXSW_REG_SPAD_LEN 0x10 61 62 MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN); 63 64 /* reg_spad_base_mac 65 * Base MAC address for the switch partitions. 66 * Per switch partition MAC address is equal to: 67 * base_mac + swid 68 * Access: RW 69 */ 70 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6); 71 72 /* SMID - Switch Multicast ID 73 * -------------------------- 74 * The MID record maps from a MID (Multicast ID), which is a unique identifier 75 * of the multicast group within the stacking domain, into a list of local 76 * ports into which the packet is replicated. 77 */ 78 #define MLXSW_REG_SMID_ID 0x2007 79 #define MLXSW_REG_SMID_LEN 0x240 80 81 MLXSW_REG_DEFINE(smid, MLXSW_REG_SMID_ID, MLXSW_REG_SMID_LEN); 82 83 /* reg_smid_swid 84 * Switch partition ID. 85 * Access: Index 86 */ 87 MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8); 88 89 /* reg_smid_mid 90 * Multicast identifier - global identifier that represents the multicast group 91 * across all devices. 92 * Access: Index 93 */ 94 MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16); 95 96 /* reg_smid_port 97 * Local port memebership (1 bit per port). 98 * Access: RW 99 */ 100 MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1); 101 102 /* reg_smid_port_mask 103 * Local port mask (1 bit per port). 104 * Access: W 105 */ 106 MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1); 107 108 static inline void mlxsw_reg_smid_pack(char *payload, u16 mid, 109 u8 port, bool set) 110 { 111 MLXSW_REG_ZERO(smid, payload); 112 mlxsw_reg_smid_swid_set(payload, 0); 113 mlxsw_reg_smid_mid_set(payload, mid); 114 mlxsw_reg_smid_port_set(payload, port, set); 115 mlxsw_reg_smid_port_mask_set(payload, port, 1); 116 } 117 118 /* SSPR - Switch System Port Record Register 119 * ----------------------------------------- 120 * Configures the system port to local port mapping. 121 */ 122 #define MLXSW_REG_SSPR_ID 0x2008 123 #define MLXSW_REG_SSPR_LEN 0x8 124 125 MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN); 126 127 /* reg_sspr_m 128 * Master - if set, then the record describes the master system port. 129 * This is needed in case a local port is mapped into several system ports 130 * (for multipathing). That number will be reported as the source system 131 * port when packets are forwarded to the CPU. Only one master port is allowed 132 * per local port. 133 * 134 * Note: Must be set for Spectrum. 135 * Access: RW 136 */ 137 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1); 138 139 /* reg_sspr_local_port 140 * Local port number. 141 * 142 * Access: RW 143 */ 144 MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8); 145 146 /* reg_sspr_sub_port 147 * Virtual port within the physical port. 148 * Should be set to 0 when virtual ports are not enabled on the port. 149 * 150 * Access: RW 151 */ 152 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8); 153 154 /* reg_sspr_system_port 155 * Unique identifier within the stacking domain that represents all the ports 156 * that are available in the system (external ports). 157 * 158 * Currently, only single-ASIC configurations are supported, so we default to 159 * 1:1 mapping between system ports and local ports. 160 * Access: Index 161 */ 162 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16); 163 164 static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port) 165 { 166 MLXSW_REG_ZERO(sspr, payload); 167 mlxsw_reg_sspr_m_set(payload, 1); 168 mlxsw_reg_sspr_local_port_set(payload, local_port); 169 mlxsw_reg_sspr_sub_port_set(payload, 0); 170 mlxsw_reg_sspr_system_port_set(payload, local_port); 171 } 172 173 /* SFDAT - Switch Filtering Database Aging Time 174 * -------------------------------------------- 175 * Controls the Switch aging time. Aging time is able to be set per Switch 176 * Partition. 177 */ 178 #define MLXSW_REG_SFDAT_ID 0x2009 179 #define MLXSW_REG_SFDAT_LEN 0x8 180 181 MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN); 182 183 /* reg_sfdat_swid 184 * Switch partition ID. 185 * Access: Index 186 */ 187 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8); 188 189 /* reg_sfdat_age_time 190 * Aging time in seconds 191 * Min - 10 seconds 192 * Max - 1,000,000 seconds 193 * Default is 300 seconds. 194 * Access: RW 195 */ 196 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20); 197 198 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time) 199 { 200 MLXSW_REG_ZERO(sfdat, payload); 201 mlxsw_reg_sfdat_swid_set(payload, 0); 202 mlxsw_reg_sfdat_age_time_set(payload, age_time); 203 } 204 205 /* SFD - Switch Filtering Database 206 * ------------------------------- 207 * The following register defines the access to the filtering database. 208 * The register supports querying, adding, removing and modifying the database. 209 * The access is optimized for bulk updates in which case more than one 210 * FDB record is present in the same command. 211 */ 212 #define MLXSW_REG_SFD_ID 0x200A 213 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */ 214 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */ 215 #define MLXSW_REG_SFD_REC_MAX_COUNT 64 216 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \ 217 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT) 218 219 MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN); 220 221 /* reg_sfd_swid 222 * Switch partition ID for queries. Reserved on Write. 223 * Access: Index 224 */ 225 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8); 226 227 enum mlxsw_reg_sfd_op { 228 /* Dump entire FDB a (process according to record_locator) */ 229 MLXSW_REG_SFD_OP_QUERY_DUMP = 0, 230 /* Query records by {MAC, VID/FID} value */ 231 MLXSW_REG_SFD_OP_QUERY_QUERY = 1, 232 /* Query and clear activity. Query records by {MAC, VID/FID} value */ 233 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2, 234 /* Test. Response indicates if each of the records could be 235 * added to the FDB. 236 */ 237 MLXSW_REG_SFD_OP_WRITE_TEST = 0, 238 /* Add/modify. Aged-out records cannot be added. This command removes 239 * the learning notification of the {MAC, VID/FID}. Response includes 240 * the entries that were added to the FDB. 241 */ 242 MLXSW_REG_SFD_OP_WRITE_EDIT = 1, 243 /* Remove record by {MAC, VID/FID}. This command also removes 244 * the learning notification and aged-out notifications 245 * of the {MAC, VID/FID}. The response provides current (pre-removal) 246 * entries as non-aged-out. 247 */ 248 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2, 249 /* Remove learned notification by {MAC, VID/FID}. The response provides 250 * the removed learning notification. 251 */ 252 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2, 253 }; 254 255 /* reg_sfd_op 256 * Operation. 257 * Access: OP 258 */ 259 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2); 260 261 /* reg_sfd_record_locator 262 * Used for querying the FDB. Use record_locator=0 to initiate the 263 * query. When a record is returned, a new record_locator is 264 * returned to be used in the subsequent query. 265 * Reserved for database update. 266 * Access: Index 267 */ 268 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30); 269 270 /* reg_sfd_num_rec 271 * Request: Number of records to read/add/modify/remove 272 * Response: Number of records read/added/replaced/removed 273 * See above description for more details. 274 * Ranges 0..64 275 * Access: RW 276 */ 277 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8); 278 279 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op, 280 u32 record_locator) 281 { 282 MLXSW_REG_ZERO(sfd, payload); 283 mlxsw_reg_sfd_op_set(payload, op); 284 mlxsw_reg_sfd_record_locator_set(payload, record_locator); 285 } 286 287 /* reg_sfd_rec_swid 288 * Switch partition ID. 289 * Access: Index 290 */ 291 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8, 292 MLXSW_REG_SFD_REC_LEN, 0x00, false); 293 294 enum mlxsw_reg_sfd_rec_type { 295 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0, 296 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1, 297 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2, 298 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL = 0xC, 299 }; 300 301 /* reg_sfd_rec_type 302 * FDB record type. 303 * Access: RW 304 */ 305 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4, 306 MLXSW_REG_SFD_REC_LEN, 0x00, false); 307 308 enum mlxsw_reg_sfd_rec_policy { 309 /* Replacement disabled, aging disabled. */ 310 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0, 311 /* (mlag remote): Replacement enabled, aging disabled, 312 * learning notification enabled on this port. 313 */ 314 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1, 315 /* (ingress device): Replacement enabled, aging enabled. */ 316 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3, 317 }; 318 319 /* reg_sfd_rec_policy 320 * Policy. 321 * Access: RW 322 */ 323 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2, 324 MLXSW_REG_SFD_REC_LEN, 0x00, false); 325 326 /* reg_sfd_rec_a 327 * Activity. Set for new static entries. Set for static entries if a frame SMAC 328 * lookup hits on the entry. 329 * To clear the a bit, use "query and clear activity" op. 330 * Access: RO 331 */ 332 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1, 333 MLXSW_REG_SFD_REC_LEN, 0x00, false); 334 335 /* reg_sfd_rec_mac 336 * MAC address. 337 * Access: Index 338 */ 339 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6, 340 MLXSW_REG_SFD_REC_LEN, 0x02); 341 342 enum mlxsw_reg_sfd_rec_action { 343 /* forward */ 344 MLXSW_REG_SFD_REC_ACTION_NOP = 0, 345 /* forward and trap, trap_id is FDB_TRAP */ 346 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1, 347 /* trap and do not forward, trap_id is FDB_TRAP */ 348 MLXSW_REG_SFD_REC_ACTION_TRAP = 2, 349 /* forward to IP router */ 350 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3, 351 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15, 352 }; 353 354 /* reg_sfd_rec_action 355 * Action to apply on the packet. 356 * Note: Dynamic entries can only be configured with NOP action. 357 * Access: RW 358 */ 359 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4, 360 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 361 362 /* reg_sfd_uc_sub_port 363 * VEPA channel on local port. 364 * Valid only if local port is a non-stacking port. Must be 0 if multichannel 365 * VEPA is not enabled. 366 * Access: RW 367 */ 368 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 369 MLXSW_REG_SFD_REC_LEN, 0x08, false); 370 371 /* reg_sfd_uc_fid_vid 372 * Filtering ID or VLAN ID 373 * For SwitchX and SwitchX-2: 374 * - Dynamic entries (policy 2,3) use FID 375 * - Static entries (policy 0) use VID 376 * - When independent learning is configured, VID=FID 377 * For Spectrum: use FID for both Dynamic and Static entries. 378 * VID should not be used. 379 * Access: Index 380 */ 381 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 382 MLXSW_REG_SFD_REC_LEN, 0x08, false); 383 384 /* reg_sfd_uc_system_port 385 * Unique port identifier for the final destination of the packet. 386 * Access: RW 387 */ 388 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16, 389 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 390 391 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index, 392 enum mlxsw_reg_sfd_rec_type rec_type, 393 const char *mac, 394 enum mlxsw_reg_sfd_rec_action action) 395 { 396 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload); 397 398 if (rec_index >= num_rec) 399 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1); 400 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0); 401 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type); 402 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac); 403 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action); 404 } 405 406 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index, 407 enum mlxsw_reg_sfd_rec_policy policy, 408 const char *mac, u16 fid_vid, 409 enum mlxsw_reg_sfd_rec_action action, 410 u8 local_port) 411 { 412 mlxsw_reg_sfd_rec_pack(payload, rec_index, 413 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action); 414 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 415 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0); 416 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid); 417 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port); 418 } 419 420 static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index, 421 char *mac, u16 *p_fid_vid, 422 u8 *p_local_port) 423 { 424 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 425 *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index); 426 *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index); 427 } 428 429 /* reg_sfd_uc_lag_sub_port 430 * LAG sub port. 431 * Must be 0 if multichannel VEPA is not enabled. 432 * Access: RW 433 */ 434 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 435 MLXSW_REG_SFD_REC_LEN, 0x08, false); 436 437 /* reg_sfd_uc_lag_fid_vid 438 * Filtering ID or VLAN ID 439 * For SwitchX and SwitchX-2: 440 * - Dynamic entries (policy 2,3) use FID 441 * - Static entries (policy 0) use VID 442 * - When independent learning is configured, VID=FID 443 * For Spectrum: use FID for both Dynamic and Static entries. 444 * VID should not be used. 445 * Access: Index 446 */ 447 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 448 MLXSW_REG_SFD_REC_LEN, 0x08, false); 449 450 /* reg_sfd_uc_lag_lag_vid 451 * Indicates VID in case of vFIDs. Reserved for FIDs. 452 * Access: RW 453 */ 454 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, 455 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 456 457 /* reg_sfd_uc_lag_lag_id 458 * LAG Identifier - pointer into the LAG descriptor table. 459 * Access: RW 460 */ 461 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10, 462 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 463 464 static inline void 465 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index, 466 enum mlxsw_reg_sfd_rec_policy policy, 467 const char *mac, u16 fid_vid, 468 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid, 469 u16 lag_id) 470 { 471 mlxsw_reg_sfd_rec_pack(payload, rec_index, 472 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG, 473 mac, action); 474 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 475 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0); 476 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid); 477 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid); 478 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id); 479 } 480 481 static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index, 482 char *mac, u16 *p_vid, 483 u16 *p_lag_id) 484 { 485 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 486 *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index); 487 *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index); 488 } 489 490 /* reg_sfd_mc_pgi 491 * 492 * Multicast port group index - index into the port group table. 493 * Value 0x1FFF indicates the pgi should point to the MID entry. 494 * For Spectrum this value must be set to 0x1FFF 495 * Access: RW 496 */ 497 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13, 498 MLXSW_REG_SFD_REC_LEN, 0x08, false); 499 500 /* reg_sfd_mc_fid_vid 501 * 502 * Filtering ID or VLAN ID 503 * Access: Index 504 */ 505 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 506 MLXSW_REG_SFD_REC_LEN, 0x08, false); 507 508 /* reg_sfd_mc_mid 509 * 510 * Multicast identifier - global identifier that represents the multicast 511 * group across all devices. 512 * Access: RW 513 */ 514 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 515 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 516 517 static inline void 518 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index, 519 const char *mac, u16 fid_vid, 520 enum mlxsw_reg_sfd_rec_action action, u16 mid) 521 { 522 mlxsw_reg_sfd_rec_pack(payload, rec_index, 523 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action); 524 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF); 525 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid); 526 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid); 527 } 528 529 /* reg_sfd_uc_tunnel_uip_msb 530 * When protocol is IPv4, the most significant byte of the underlay IPv4 531 * destination IP. 532 * When protocol is IPv6, reserved. 533 * Access: RW 534 */ 535 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24, 536 8, MLXSW_REG_SFD_REC_LEN, 0x08, false); 537 538 /* reg_sfd_uc_tunnel_fid 539 * Filtering ID. 540 * Access: Index 541 */ 542 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 543 MLXSW_REG_SFD_REC_LEN, 0x08, false); 544 545 enum mlxsw_reg_sfd_uc_tunnel_protocol { 546 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4, 547 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6, 548 }; 549 550 /* reg_sfd_uc_tunnel_protocol 551 * IP protocol. 552 * Access: RW 553 */ 554 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27, 555 1, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 556 557 /* reg_sfd_uc_tunnel_uip_lsb 558 * When protocol is IPv4, the least significant bytes of the underlay 559 * IPv4 destination IP. 560 * When protocol is IPv6, pointer to the underlay IPv6 destination IP 561 * which is configured by RIPS. 562 * Access: RW 563 */ 564 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0, 565 24, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 566 567 static inline void 568 mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index, 569 enum mlxsw_reg_sfd_rec_policy policy, 570 const char *mac, u16 fid, 571 enum mlxsw_reg_sfd_rec_action action, u32 uip, 572 enum mlxsw_reg_sfd_uc_tunnel_protocol proto) 573 { 574 mlxsw_reg_sfd_rec_pack(payload, rec_index, 575 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL, mac, 576 action); 577 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 578 mlxsw_reg_sfd_uc_tunnel_uip_msb_set(payload, rec_index, uip >> 24); 579 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip); 580 mlxsw_reg_sfd_uc_tunnel_fid_set(payload, rec_index, fid); 581 mlxsw_reg_sfd_uc_tunnel_protocol_set(payload, rec_index, proto); 582 } 583 584 enum mlxsw_reg_tunnel_port { 585 MLXSW_REG_TUNNEL_PORT_NVE, 586 MLXSW_REG_TUNNEL_PORT_VPLS, 587 MLXSW_REG_TUNNEL_PORT_FLEX_TUNNEL0, 588 MLXSW_REG_TUNNEL_PORT_FLEX_TUNNEL1, 589 }; 590 591 /* SFN - Switch FDB Notification Register 592 * ------------------------------------------- 593 * The switch provides notifications on newly learned FDB entries and 594 * aged out entries. The notifications can be polled by software. 595 */ 596 #define MLXSW_REG_SFN_ID 0x200B 597 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */ 598 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */ 599 #define MLXSW_REG_SFN_REC_MAX_COUNT 64 600 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \ 601 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT) 602 603 MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN); 604 605 /* reg_sfn_swid 606 * Switch partition ID. 607 * Access: Index 608 */ 609 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8); 610 611 /* reg_sfn_end 612 * Forces the current session to end. 613 * Access: OP 614 */ 615 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1); 616 617 /* reg_sfn_num_rec 618 * Request: Number of learned notifications and aged-out notification 619 * records requested. 620 * Response: Number of notification records returned (must be smaller 621 * than or equal to the value requested) 622 * Ranges 0..64 623 * Access: OP 624 */ 625 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8); 626 627 static inline void mlxsw_reg_sfn_pack(char *payload) 628 { 629 MLXSW_REG_ZERO(sfn, payload); 630 mlxsw_reg_sfn_swid_set(payload, 0); 631 mlxsw_reg_sfn_end_set(payload, 0); 632 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT); 633 } 634 635 /* reg_sfn_rec_swid 636 * Switch partition ID. 637 * Access: RO 638 */ 639 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8, 640 MLXSW_REG_SFN_REC_LEN, 0x00, false); 641 642 enum mlxsw_reg_sfn_rec_type { 643 /* MAC addresses learned on a regular port. */ 644 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5, 645 /* MAC addresses learned on a LAG port. */ 646 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6, 647 /* Aged-out MAC address on a regular port. */ 648 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7, 649 /* Aged-out MAC address on a LAG port. */ 650 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8, 651 /* Learned unicast tunnel record. */ 652 MLXSW_REG_SFN_REC_TYPE_LEARNED_UNICAST_TUNNEL = 0xD, 653 /* Aged-out unicast tunnel record. */ 654 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_UNICAST_TUNNEL = 0xE, 655 }; 656 657 /* reg_sfn_rec_type 658 * Notification record type. 659 * Access: RO 660 */ 661 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4, 662 MLXSW_REG_SFN_REC_LEN, 0x00, false); 663 664 /* reg_sfn_rec_mac 665 * MAC address. 666 * Access: RO 667 */ 668 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6, 669 MLXSW_REG_SFN_REC_LEN, 0x02); 670 671 /* reg_sfn_mac_sub_port 672 * VEPA channel on the local port. 673 * 0 if multichannel VEPA is not enabled. 674 * Access: RO 675 */ 676 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8, 677 MLXSW_REG_SFN_REC_LEN, 0x08, false); 678 679 /* reg_sfn_mac_fid 680 * Filtering identifier. 681 * Access: RO 682 */ 683 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16, 684 MLXSW_REG_SFN_REC_LEN, 0x08, false); 685 686 /* reg_sfn_mac_system_port 687 * Unique port identifier for the final destination of the packet. 688 * Access: RO 689 */ 690 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16, 691 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 692 693 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index, 694 char *mac, u16 *p_vid, 695 u8 *p_local_port) 696 { 697 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 698 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 699 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index); 700 } 701 702 /* reg_sfn_mac_lag_lag_id 703 * LAG ID (pointer into the LAG descriptor table). 704 * Access: RO 705 */ 706 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10, 707 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 708 709 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index, 710 char *mac, u16 *p_vid, 711 u16 *p_lag_id) 712 { 713 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 714 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 715 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index); 716 } 717 718 /* reg_sfn_uc_tunnel_uip_msb 719 * When protocol is IPv4, the most significant byte of the underlay IPv4 720 * address of the remote VTEP. 721 * When protocol is IPv6, reserved. 722 * Access: RO 723 */ 724 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_msb, MLXSW_REG_SFN_BASE_LEN, 24, 725 8, MLXSW_REG_SFN_REC_LEN, 0x08, false); 726 727 enum mlxsw_reg_sfn_uc_tunnel_protocol { 728 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV4, 729 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV6, 730 }; 731 732 /* reg_sfn_uc_tunnel_protocol 733 * IP protocol. 734 * Access: RO 735 */ 736 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_protocol, MLXSW_REG_SFN_BASE_LEN, 27, 737 1, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 738 739 /* reg_sfn_uc_tunnel_uip_lsb 740 * When protocol is IPv4, the least significant bytes of the underlay 741 * IPv4 address of the remote VTEP. 742 * When protocol is IPv6, ipv6_id to be queried from TNIPSD. 743 * Access: RO 744 */ 745 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0, 746 24, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 747 748 /* reg_sfn_uc_tunnel_port 749 * Tunnel port. 750 * Reserved on Spectrum. 751 * Access: RO 752 */ 753 MLXSW_ITEM32_INDEXED(reg, sfn, tunnel_port, MLXSW_REG_SFN_BASE_LEN, 0, 4, 754 MLXSW_REG_SFN_REC_LEN, 0x10, false); 755 756 static inline void 757 mlxsw_reg_sfn_uc_tunnel_unpack(char *payload, int rec_index, char *mac, 758 u16 *p_fid, u32 *p_uip, 759 enum mlxsw_reg_sfn_uc_tunnel_protocol *p_proto) 760 { 761 u32 uip_msb, uip_lsb; 762 763 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 764 *p_fid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 765 uip_msb = mlxsw_reg_sfn_uc_tunnel_uip_msb_get(payload, rec_index); 766 uip_lsb = mlxsw_reg_sfn_uc_tunnel_uip_lsb_get(payload, rec_index); 767 *p_uip = uip_msb << 24 | uip_lsb; 768 *p_proto = mlxsw_reg_sfn_uc_tunnel_protocol_get(payload, rec_index); 769 } 770 771 /* SPMS - Switch Port MSTP/RSTP State Register 772 * ------------------------------------------- 773 * Configures the spanning tree state of a physical port. 774 */ 775 #define MLXSW_REG_SPMS_ID 0x200D 776 #define MLXSW_REG_SPMS_LEN 0x404 777 778 MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN); 779 780 /* reg_spms_local_port 781 * Local port number. 782 * Access: Index 783 */ 784 MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8); 785 786 enum mlxsw_reg_spms_state { 787 MLXSW_REG_SPMS_STATE_NO_CHANGE, 788 MLXSW_REG_SPMS_STATE_DISCARDING, 789 MLXSW_REG_SPMS_STATE_LEARNING, 790 MLXSW_REG_SPMS_STATE_FORWARDING, 791 }; 792 793 /* reg_spms_state 794 * Spanning tree state of each VLAN ID (VID) of the local port. 795 * 0 - Do not change spanning tree state (used only when writing). 796 * 1 - Discarding. No learning or forwarding to/from this port (default). 797 * 2 - Learning. Port is learning, but not forwarding. 798 * 3 - Forwarding. Port is learning and forwarding. 799 * Access: RW 800 */ 801 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2); 802 803 static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port) 804 { 805 MLXSW_REG_ZERO(spms, payload); 806 mlxsw_reg_spms_local_port_set(payload, local_port); 807 } 808 809 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid, 810 enum mlxsw_reg_spms_state state) 811 { 812 mlxsw_reg_spms_state_set(payload, vid, state); 813 } 814 815 /* SPVID - Switch Port VID 816 * ----------------------- 817 * The switch port VID configures the default VID for a port. 818 */ 819 #define MLXSW_REG_SPVID_ID 0x200E 820 #define MLXSW_REG_SPVID_LEN 0x08 821 822 MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN); 823 824 /* reg_spvid_tport 825 * Port is tunnel port. 826 * Reserved when SwitchX/-2 or Spectrum-1. 827 * Access: Index 828 */ 829 MLXSW_ITEM32(reg, spvid, tport, 0x00, 24, 1); 830 831 /* reg_spvid_local_port 832 * When tport = 0: Local port number. Not supported for CPU port. 833 * When tport = 1: Tunnel port. 834 * Access: Index 835 */ 836 MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8); 837 838 /* reg_spvid_sub_port 839 * Virtual port within the physical port. 840 * Should be set to 0 when virtual ports are not enabled on the port. 841 * Access: Index 842 */ 843 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8); 844 845 /* reg_spvid_et_vlan 846 * EtherType used for when VLAN is pushed at ingress (for untagged 847 * packets or for QinQ push mode). 848 * 0: ether_type0 - (default) 849 * 1: ether_type1 850 * 2: ether_type2 - Reserved when Spectrum-1, supported by Spectrum-2 851 * Ethertype IDs are configured by SVER. 852 * Access: RW 853 */ 854 MLXSW_ITEM32(reg, spvid, et_vlan, 0x04, 16, 2); 855 856 /* reg_spvid_pvid 857 * Port default VID 858 * Access: RW 859 */ 860 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12); 861 862 static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid, 863 u8 et_vlan) 864 { 865 MLXSW_REG_ZERO(spvid, payload); 866 mlxsw_reg_spvid_local_port_set(payload, local_port); 867 mlxsw_reg_spvid_pvid_set(payload, pvid); 868 mlxsw_reg_spvid_et_vlan_set(payload, et_vlan); 869 } 870 871 /* SPVM - Switch Port VLAN Membership 872 * ---------------------------------- 873 * The Switch Port VLAN Membership register configures the VLAN membership 874 * of a port in a VLAN denoted by VID. VLAN membership is managed per 875 * virtual port. The register can be used to add and remove VID(s) from a port. 876 */ 877 #define MLXSW_REG_SPVM_ID 0x200F 878 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */ 879 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */ 880 #define MLXSW_REG_SPVM_REC_MAX_COUNT 255 881 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \ 882 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT) 883 884 MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN); 885 886 /* reg_spvm_pt 887 * Priority tagged. If this bit is set, packets forwarded to the port with 888 * untagged VLAN membership (u bit is set) will be tagged with priority tag 889 * (VID=0) 890 * Access: RW 891 */ 892 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1); 893 894 /* reg_spvm_pte 895 * Priority Tagged Update Enable. On Write operations, if this bit is cleared, 896 * the pt bit will NOT be updated. To update the pt bit, pte must be set. 897 * Access: WO 898 */ 899 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1); 900 901 /* reg_spvm_local_port 902 * Local port number. 903 * Access: Index 904 */ 905 MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8); 906 907 /* reg_spvm_sub_port 908 * Virtual port within the physical port. 909 * Should be set to 0 when virtual ports are not enabled on the port. 910 * Access: Index 911 */ 912 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8); 913 914 /* reg_spvm_num_rec 915 * Number of records to update. Each record contains: i, e, u, vid. 916 * Access: OP 917 */ 918 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8); 919 920 /* reg_spvm_rec_i 921 * Ingress membership in VLAN ID. 922 * Access: Index 923 */ 924 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i, 925 MLXSW_REG_SPVM_BASE_LEN, 14, 1, 926 MLXSW_REG_SPVM_REC_LEN, 0, false); 927 928 /* reg_spvm_rec_e 929 * Egress membership in VLAN ID. 930 * Access: Index 931 */ 932 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e, 933 MLXSW_REG_SPVM_BASE_LEN, 13, 1, 934 MLXSW_REG_SPVM_REC_LEN, 0, false); 935 936 /* reg_spvm_rec_u 937 * Untagged - port is an untagged member - egress transmission uses untagged 938 * frames on VID<n> 939 * Access: Index 940 */ 941 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u, 942 MLXSW_REG_SPVM_BASE_LEN, 12, 1, 943 MLXSW_REG_SPVM_REC_LEN, 0, false); 944 945 /* reg_spvm_rec_vid 946 * Egress membership in VLAN ID. 947 * Access: Index 948 */ 949 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid, 950 MLXSW_REG_SPVM_BASE_LEN, 0, 12, 951 MLXSW_REG_SPVM_REC_LEN, 0, false); 952 953 static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port, 954 u16 vid_begin, u16 vid_end, 955 bool is_member, bool untagged) 956 { 957 int size = vid_end - vid_begin + 1; 958 int i; 959 960 MLXSW_REG_ZERO(spvm, payload); 961 mlxsw_reg_spvm_local_port_set(payload, local_port); 962 mlxsw_reg_spvm_num_rec_set(payload, size); 963 964 for (i = 0; i < size; i++) { 965 mlxsw_reg_spvm_rec_i_set(payload, i, is_member); 966 mlxsw_reg_spvm_rec_e_set(payload, i, is_member); 967 mlxsw_reg_spvm_rec_u_set(payload, i, untagged); 968 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i); 969 } 970 } 971 972 /* SPAFT - Switch Port Acceptable Frame Types 973 * ------------------------------------------ 974 * The Switch Port Acceptable Frame Types register configures the frame 975 * admittance of the port. 976 */ 977 #define MLXSW_REG_SPAFT_ID 0x2010 978 #define MLXSW_REG_SPAFT_LEN 0x08 979 980 MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN); 981 982 /* reg_spaft_local_port 983 * Local port number. 984 * Access: Index 985 * 986 * Note: CPU port is not supported (all tag types are allowed). 987 */ 988 MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8); 989 990 /* reg_spaft_sub_port 991 * Virtual port within the physical port. 992 * Should be set to 0 when virtual ports are not enabled on the port. 993 * Access: RW 994 */ 995 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8); 996 997 /* reg_spaft_allow_untagged 998 * When set, untagged frames on the ingress are allowed (default). 999 * Access: RW 1000 */ 1001 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1); 1002 1003 /* reg_spaft_allow_prio_tagged 1004 * When set, priority tagged frames on the ingress are allowed (default). 1005 * Access: RW 1006 */ 1007 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1); 1008 1009 /* reg_spaft_allow_tagged 1010 * When set, tagged frames on the ingress are allowed (default). 1011 * Access: RW 1012 */ 1013 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1); 1014 1015 static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port, 1016 bool allow_untagged) 1017 { 1018 MLXSW_REG_ZERO(spaft, payload); 1019 mlxsw_reg_spaft_local_port_set(payload, local_port); 1020 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged); 1021 mlxsw_reg_spaft_allow_prio_tagged_set(payload, allow_untagged); 1022 mlxsw_reg_spaft_allow_tagged_set(payload, true); 1023 } 1024 1025 /* SFGC - Switch Flooding Group Configuration 1026 * ------------------------------------------ 1027 * The following register controls the association of flooding tables and MIDs 1028 * to packet types used for flooding. 1029 */ 1030 #define MLXSW_REG_SFGC_ID 0x2011 1031 #define MLXSW_REG_SFGC_LEN 0x10 1032 1033 MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN); 1034 1035 enum mlxsw_reg_sfgc_type { 1036 MLXSW_REG_SFGC_TYPE_BROADCAST, 1037 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST, 1038 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4, 1039 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6, 1040 MLXSW_REG_SFGC_TYPE_RESERVED, 1041 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP, 1042 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL, 1043 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST, 1044 MLXSW_REG_SFGC_TYPE_MAX, 1045 }; 1046 1047 /* reg_sfgc_type 1048 * The traffic type to reach the flooding table. 1049 * Access: Index 1050 */ 1051 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4); 1052 1053 enum mlxsw_reg_sfgc_bridge_type { 1054 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0, 1055 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1, 1056 }; 1057 1058 /* reg_sfgc_bridge_type 1059 * Access: Index 1060 * 1061 * Note: SwitchX-2 only supports 802.1Q mode. 1062 */ 1063 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3); 1064 1065 enum mlxsw_flood_table_type { 1066 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1, 1067 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2, 1068 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0, 1069 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3, 1070 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4, 1071 }; 1072 1073 /* reg_sfgc_table_type 1074 * See mlxsw_flood_table_type 1075 * Access: RW 1076 * 1077 * Note: FID offset and FID types are not supported in SwitchX-2. 1078 */ 1079 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3); 1080 1081 /* reg_sfgc_flood_table 1082 * Flooding table index to associate with the specific type on the specific 1083 * switch partition. 1084 * Access: RW 1085 */ 1086 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6); 1087 1088 /* reg_sfgc_mid 1089 * The multicast ID for the swid. Not supported for Spectrum 1090 * Access: RW 1091 */ 1092 MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16); 1093 1094 /* reg_sfgc_counter_set_type 1095 * Counter Set Type for flow counters. 1096 * Access: RW 1097 */ 1098 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8); 1099 1100 /* reg_sfgc_counter_index 1101 * Counter Index for flow counters. 1102 * Access: RW 1103 */ 1104 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24); 1105 1106 static inline void 1107 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type, 1108 enum mlxsw_reg_sfgc_bridge_type bridge_type, 1109 enum mlxsw_flood_table_type table_type, 1110 unsigned int flood_table) 1111 { 1112 MLXSW_REG_ZERO(sfgc, payload); 1113 mlxsw_reg_sfgc_type_set(payload, type); 1114 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type); 1115 mlxsw_reg_sfgc_table_type_set(payload, table_type); 1116 mlxsw_reg_sfgc_flood_table_set(payload, flood_table); 1117 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID); 1118 } 1119 1120 /* SFTR - Switch Flooding Table Register 1121 * ------------------------------------- 1122 * The switch flooding table is used for flooding packet replication. The table 1123 * defines a bit mask of ports for packet replication. 1124 */ 1125 #define MLXSW_REG_SFTR_ID 0x2012 1126 #define MLXSW_REG_SFTR_LEN 0x420 1127 1128 MLXSW_REG_DEFINE(sftr, MLXSW_REG_SFTR_ID, MLXSW_REG_SFTR_LEN); 1129 1130 /* reg_sftr_swid 1131 * Switch partition ID with which to associate the port. 1132 * Access: Index 1133 */ 1134 MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8); 1135 1136 /* reg_sftr_flood_table 1137 * Flooding table index to associate with the specific type on the specific 1138 * switch partition. 1139 * Access: Index 1140 */ 1141 MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6); 1142 1143 /* reg_sftr_index 1144 * Index. Used as an index into the Flooding Table in case the table is 1145 * configured to use VID / FID or FID Offset. 1146 * Access: Index 1147 */ 1148 MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16); 1149 1150 /* reg_sftr_table_type 1151 * See mlxsw_flood_table_type 1152 * Access: RW 1153 */ 1154 MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3); 1155 1156 /* reg_sftr_range 1157 * Range of entries to update 1158 * Access: Index 1159 */ 1160 MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16); 1161 1162 /* reg_sftr_port 1163 * Local port membership (1 bit per port). 1164 * Access: RW 1165 */ 1166 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1); 1167 1168 /* reg_sftr_cpu_port_mask 1169 * CPU port mask (1 bit per port). 1170 * Access: W 1171 */ 1172 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1); 1173 1174 static inline void mlxsw_reg_sftr_pack(char *payload, 1175 unsigned int flood_table, 1176 unsigned int index, 1177 enum mlxsw_flood_table_type table_type, 1178 unsigned int range, u8 port, bool set) 1179 { 1180 MLXSW_REG_ZERO(sftr, payload); 1181 mlxsw_reg_sftr_swid_set(payload, 0); 1182 mlxsw_reg_sftr_flood_table_set(payload, flood_table); 1183 mlxsw_reg_sftr_index_set(payload, index); 1184 mlxsw_reg_sftr_table_type_set(payload, table_type); 1185 mlxsw_reg_sftr_range_set(payload, range); 1186 mlxsw_reg_sftr_port_set(payload, port, set); 1187 mlxsw_reg_sftr_port_mask_set(payload, port, 1); 1188 } 1189 1190 /* SFDF - Switch Filtering DB Flush 1191 * -------------------------------- 1192 * The switch filtering DB flush register is used to flush the FDB. 1193 * Note that FDB notifications are flushed as well. 1194 */ 1195 #define MLXSW_REG_SFDF_ID 0x2013 1196 #define MLXSW_REG_SFDF_LEN 0x14 1197 1198 MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN); 1199 1200 /* reg_sfdf_swid 1201 * Switch partition ID. 1202 * Access: Index 1203 */ 1204 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8); 1205 1206 enum mlxsw_reg_sfdf_flush_type { 1207 MLXSW_REG_SFDF_FLUSH_PER_SWID, 1208 MLXSW_REG_SFDF_FLUSH_PER_FID, 1209 MLXSW_REG_SFDF_FLUSH_PER_PORT, 1210 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID, 1211 MLXSW_REG_SFDF_FLUSH_PER_LAG, 1212 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID, 1213 MLXSW_REG_SFDF_FLUSH_PER_NVE, 1214 MLXSW_REG_SFDF_FLUSH_PER_NVE_AND_FID, 1215 }; 1216 1217 /* reg_sfdf_flush_type 1218 * Flush type. 1219 * 0 - All SWID dynamic entries are flushed. 1220 * 1 - All FID dynamic entries are flushed. 1221 * 2 - All dynamic entries pointing to port are flushed. 1222 * 3 - All FID dynamic entries pointing to port are flushed. 1223 * 4 - All dynamic entries pointing to LAG are flushed. 1224 * 5 - All FID dynamic entries pointing to LAG are flushed. 1225 * 6 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1226 * flushed. 1227 * 7 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1228 * flushed, per FID. 1229 * Access: RW 1230 */ 1231 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4); 1232 1233 /* reg_sfdf_flush_static 1234 * Static. 1235 * 0 - Flush only dynamic entries. 1236 * 1 - Flush both dynamic and static entries. 1237 * Access: RW 1238 */ 1239 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1); 1240 1241 static inline void mlxsw_reg_sfdf_pack(char *payload, 1242 enum mlxsw_reg_sfdf_flush_type type) 1243 { 1244 MLXSW_REG_ZERO(sfdf, payload); 1245 mlxsw_reg_sfdf_flush_type_set(payload, type); 1246 mlxsw_reg_sfdf_flush_static_set(payload, true); 1247 } 1248 1249 /* reg_sfdf_fid 1250 * FID to flush. 1251 * Access: RW 1252 */ 1253 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16); 1254 1255 /* reg_sfdf_system_port 1256 * Port to flush. 1257 * Access: RW 1258 */ 1259 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16); 1260 1261 /* reg_sfdf_port_fid_system_port 1262 * Port to flush, pointed to by FID. 1263 * Access: RW 1264 */ 1265 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16); 1266 1267 /* reg_sfdf_lag_id 1268 * LAG ID to flush. 1269 * Access: RW 1270 */ 1271 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10); 1272 1273 /* reg_sfdf_lag_fid_lag_id 1274 * LAG ID to flush, pointed to by FID. 1275 * Access: RW 1276 */ 1277 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10); 1278 1279 /* SLDR - Switch LAG Descriptor Register 1280 * ----------------------------------------- 1281 * The switch LAG descriptor register is populated by LAG descriptors. 1282 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to 1283 * max_lag-1. 1284 */ 1285 #define MLXSW_REG_SLDR_ID 0x2014 1286 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */ 1287 1288 MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN); 1289 1290 enum mlxsw_reg_sldr_op { 1291 /* Indicates a creation of a new LAG-ID, lag_id must be valid */ 1292 MLXSW_REG_SLDR_OP_LAG_CREATE, 1293 MLXSW_REG_SLDR_OP_LAG_DESTROY, 1294 /* Ports that appear in the list have the Distributor enabled */ 1295 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST, 1296 /* Removes ports from the disributor list */ 1297 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST, 1298 }; 1299 1300 /* reg_sldr_op 1301 * Operation. 1302 * Access: RW 1303 */ 1304 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3); 1305 1306 /* reg_sldr_lag_id 1307 * LAG identifier. The lag_id is the index into the LAG descriptor table. 1308 * Access: Index 1309 */ 1310 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10); 1311 1312 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id) 1313 { 1314 MLXSW_REG_ZERO(sldr, payload); 1315 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE); 1316 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1317 } 1318 1319 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id) 1320 { 1321 MLXSW_REG_ZERO(sldr, payload); 1322 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY); 1323 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1324 } 1325 1326 /* reg_sldr_num_ports 1327 * The number of member ports of the LAG. 1328 * Reserved for Create / Destroy operations 1329 * For Add / Remove operations - indicates the number of ports in the list. 1330 * Access: RW 1331 */ 1332 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8); 1333 1334 /* reg_sldr_system_port 1335 * System port. 1336 * Access: RW 1337 */ 1338 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false); 1339 1340 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id, 1341 u8 local_port) 1342 { 1343 MLXSW_REG_ZERO(sldr, payload); 1344 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST); 1345 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1346 mlxsw_reg_sldr_num_ports_set(payload, 1); 1347 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1348 } 1349 1350 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id, 1351 u8 local_port) 1352 { 1353 MLXSW_REG_ZERO(sldr, payload); 1354 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST); 1355 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1356 mlxsw_reg_sldr_num_ports_set(payload, 1); 1357 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1358 } 1359 1360 /* SLCR - Switch LAG Configuration 2 Register 1361 * ------------------------------------------- 1362 * The Switch LAG Configuration register is used for configuring the 1363 * LAG properties of the switch. 1364 */ 1365 #define MLXSW_REG_SLCR_ID 0x2015 1366 #define MLXSW_REG_SLCR_LEN 0x10 1367 1368 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN); 1369 1370 enum mlxsw_reg_slcr_pp { 1371 /* Global Configuration (for all ports) */ 1372 MLXSW_REG_SLCR_PP_GLOBAL, 1373 /* Per port configuration, based on local_port field */ 1374 MLXSW_REG_SLCR_PP_PER_PORT, 1375 }; 1376 1377 /* reg_slcr_pp 1378 * Per Port Configuration 1379 * Note: Reading at Global mode results in reading port 1 configuration. 1380 * Access: Index 1381 */ 1382 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1); 1383 1384 /* reg_slcr_local_port 1385 * Local port number 1386 * Supported from CPU port 1387 * Not supported from router port 1388 * Reserved when pp = Global Configuration 1389 * Access: Index 1390 */ 1391 MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8); 1392 1393 enum mlxsw_reg_slcr_type { 1394 MLXSW_REG_SLCR_TYPE_CRC, /* default */ 1395 MLXSW_REG_SLCR_TYPE_XOR, 1396 MLXSW_REG_SLCR_TYPE_RANDOM, 1397 }; 1398 1399 /* reg_slcr_type 1400 * Hash type 1401 * Access: RW 1402 */ 1403 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4); 1404 1405 /* Ingress port */ 1406 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0) 1407 /* SMAC - for IPv4 and IPv6 packets */ 1408 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1) 1409 /* SMAC - for non-IP packets */ 1410 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2) 1411 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \ 1412 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \ 1413 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP) 1414 /* DMAC - for IPv4 and IPv6 packets */ 1415 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3) 1416 /* DMAC - for non-IP packets */ 1417 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4) 1418 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \ 1419 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \ 1420 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP) 1421 /* Ethertype - for IPv4 and IPv6 packets */ 1422 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5) 1423 /* Ethertype - for non-IP packets */ 1424 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6) 1425 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \ 1426 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \ 1427 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP) 1428 /* VLAN ID - for IPv4 and IPv6 packets */ 1429 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7) 1430 /* VLAN ID - for non-IP packets */ 1431 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8) 1432 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \ 1433 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \ 1434 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP) 1435 /* Source IP address (can be IPv4 or IPv6) */ 1436 #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9) 1437 /* Destination IP address (can be IPv4 or IPv6) */ 1438 #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10) 1439 /* TCP/UDP source port */ 1440 #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11) 1441 /* TCP/UDP destination port*/ 1442 #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12) 1443 /* IPv4 Protocol/IPv6 Next Header */ 1444 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13) 1445 /* IPv6 Flow label */ 1446 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14) 1447 /* SID - FCoE source ID */ 1448 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15) 1449 /* DID - FCoE destination ID */ 1450 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16) 1451 /* OXID - FCoE originator exchange ID */ 1452 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17) 1453 /* Destination QP number - for RoCE packets */ 1454 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19) 1455 1456 /* reg_slcr_lag_hash 1457 * LAG hashing configuration. This is a bitmask, in which each set 1458 * bit includes the corresponding item in the LAG hash calculation. 1459 * The default lag_hash contains SMAC, DMAC, VLANID and 1460 * Ethertype (for all packet types). 1461 * Access: RW 1462 */ 1463 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20); 1464 1465 /* reg_slcr_seed 1466 * LAG seed value. The seed is the same for all ports. 1467 * Access: RW 1468 */ 1469 MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32); 1470 1471 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed) 1472 { 1473 MLXSW_REG_ZERO(slcr, payload); 1474 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL); 1475 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC); 1476 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash); 1477 mlxsw_reg_slcr_seed_set(payload, seed); 1478 } 1479 1480 /* SLCOR - Switch LAG Collector Register 1481 * ------------------------------------- 1482 * The Switch LAG Collector register controls the Local Port membership 1483 * in a LAG and enablement of the collector. 1484 */ 1485 #define MLXSW_REG_SLCOR_ID 0x2016 1486 #define MLXSW_REG_SLCOR_LEN 0x10 1487 1488 MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN); 1489 1490 enum mlxsw_reg_slcor_col { 1491 /* Port is added with collector disabled */ 1492 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT, 1493 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED, 1494 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED, 1495 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT, 1496 }; 1497 1498 /* reg_slcor_col 1499 * Collector configuration 1500 * Access: RW 1501 */ 1502 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2); 1503 1504 /* reg_slcor_local_port 1505 * Local port number 1506 * Not supported for CPU port 1507 * Access: Index 1508 */ 1509 MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8); 1510 1511 /* reg_slcor_lag_id 1512 * LAG Identifier. Index into the LAG descriptor table. 1513 * Access: Index 1514 */ 1515 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10); 1516 1517 /* reg_slcor_port_index 1518 * Port index in the LAG list. Only valid on Add Port to LAG col. 1519 * Valid range is from 0 to cap_max_lag_members-1 1520 * Access: RW 1521 */ 1522 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10); 1523 1524 static inline void mlxsw_reg_slcor_pack(char *payload, 1525 u8 local_port, u16 lag_id, 1526 enum mlxsw_reg_slcor_col col) 1527 { 1528 MLXSW_REG_ZERO(slcor, payload); 1529 mlxsw_reg_slcor_col_set(payload, col); 1530 mlxsw_reg_slcor_local_port_set(payload, local_port); 1531 mlxsw_reg_slcor_lag_id_set(payload, lag_id); 1532 } 1533 1534 static inline void mlxsw_reg_slcor_port_add_pack(char *payload, 1535 u8 local_port, u16 lag_id, 1536 u8 port_index) 1537 { 1538 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1539 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT); 1540 mlxsw_reg_slcor_port_index_set(payload, port_index); 1541 } 1542 1543 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload, 1544 u8 local_port, u16 lag_id) 1545 { 1546 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1547 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT); 1548 } 1549 1550 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload, 1551 u8 local_port, u16 lag_id) 1552 { 1553 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1554 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1555 } 1556 1557 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload, 1558 u8 local_port, u16 lag_id) 1559 { 1560 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1561 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1562 } 1563 1564 /* SPMLR - Switch Port MAC Learning Register 1565 * ----------------------------------------- 1566 * Controls the Switch MAC learning policy per port. 1567 */ 1568 #define MLXSW_REG_SPMLR_ID 0x2018 1569 #define MLXSW_REG_SPMLR_LEN 0x8 1570 1571 MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN); 1572 1573 /* reg_spmlr_local_port 1574 * Local port number. 1575 * Access: Index 1576 */ 1577 MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8); 1578 1579 /* reg_spmlr_sub_port 1580 * Virtual port within the physical port. 1581 * Should be set to 0 when virtual ports are not enabled on the port. 1582 * Access: Index 1583 */ 1584 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8); 1585 1586 enum mlxsw_reg_spmlr_learn_mode { 1587 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0, 1588 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2, 1589 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3, 1590 }; 1591 1592 /* reg_spmlr_learn_mode 1593 * Learning mode on the port. 1594 * 0 - Learning disabled. 1595 * 2 - Learning enabled. 1596 * 3 - Security mode. 1597 * 1598 * In security mode the switch does not learn MACs on the port, but uses the 1599 * SMAC to see if it exists on another ingress port. If so, the packet is 1600 * classified as a bad packet and is discarded unless the software registers 1601 * to receive port security error packets usign HPKT. 1602 */ 1603 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2); 1604 1605 static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port, 1606 enum mlxsw_reg_spmlr_learn_mode mode) 1607 { 1608 MLXSW_REG_ZERO(spmlr, payload); 1609 mlxsw_reg_spmlr_local_port_set(payload, local_port); 1610 mlxsw_reg_spmlr_sub_port_set(payload, 0); 1611 mlxsw_reg_spmlr_learn_mode_set(payload, mode); 1612 } 1613 1614 /* SVFA - Switch VID to FID Allocation Register 1615 * -------------------------------------------- 1616 * Controls the VID to FID mapping and {Port, VID} to FID mapping for 1617 * virtualized ports. 1618 */ 1619 #define MLXSW_REG_SVFA_ID 0x201C 1620 #define MLXSW_REG_SVFA_LEN 0x10 1621 1622 MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN); 1623 1624 /* reg_svfa_swid 1625 * Switch partition ID. 1626 * Access: Index 1627 */ 1628 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8); 1629 1630 /* reg_svfa_local_port 1631 * Local port number. 1632 * Access: Index 1633 * 1634 * Note: Reserved for 802.1Q FIDs. 1635 */ 1636 MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8); 1637 1638 enum mlxsw_reg_svfa_mt { 1639 MLXSW_REG_SVFA_MT_VID_TO_FID, 1640 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, 1641 }; 1642 1643 /* reg_svfa_mapping_table 1644 * Mapping table: 1645 * 0 - VID to FID 1646 * 1 - {Port, VID} to FID 1647 * Access: Index 1648 * 1649 * Note: Reserved for SwitchX-2. 1650 */ 1651 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3); 1652 1653 /* reg_svfa_v 1654 * Valid. 1655 * Valid if set. 1656 * Access: RW 1657 * 1658 * Note: Reserved for SwitchX-2. 1659 */ 1660 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1); 1661 1662 /* reg_svfa_fid 1663 * Filtering ID. 1664 * Access: RW 1665 */ 1666 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16); 1667 1668 /* reg_svfa_vid 1669 * VLAN ID. 1670 * Access: Index 1671 */ 1672 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12); 1673 1674 /* reg_svfa_counter_set_type 1675 * Counter set type for flow counters. 1676 * Access: RW 1677 * 1678 * Note: Reserved for SwitchX-2. 1679 */ 1680 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8); 1681 1682 /* reg_svfa_counter_index 1683 * Counter index for flow counters. 1684 * Access: RW 1685 * 1686 * Note: Reserved for SwitchX-2. 1687 */ 1688 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24); 1689 1690 static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port, 1691 enum mlxsw_reg_svfa_mt mt, bool valid, 1692 u16 fid, u16 vid) 1693 { 1694 MLXSW_REG_ZERO(svfa, payload); 1695 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port; 1696 mlxsw_reg_svfa_swid_set(payload, 0); 1697 mlxsw_reg_svfa_local_port_set(payload, local_port); 1698 mlxsw_reg_svfa_mapping_table_set(payload, mt); 1699 mlxsw_reg_svfa_v_set(payload, valid); 1700 mlxsw_reg_svfa_fid_set(payload, fid); 1701 mlxsw_reg_svfa_vid_set(payload, vid); 1702 } 1703 1704 /* SPVTR - Switch Port VLAN Stacking Register 1705 * ------------------------------------------ 1706 * The Switch Port VLAN Stacking register configures the VLAN mode of the port 1707 * to enable VLAN stacking. 1708 */ 1709 #define MLXSW_REG_SPVTR_ID 0x201D 1710 #define MLXSW_REG_SPVTR_LEN 0x10 1711 1712 MLXSW_REG_DEFINE(spvtr, MLXSW_REG_SPVTR_ID, MLXSW_REG_SPVTR_LEN); 1713 1714 /* reg_spvtr_tport 1715 * Port is tunnel port. 1716 * Access: Index 1717 * 1718 * Note: Reserved when SwitchX/-2 or Spectrum-1. 1719 */ 1720 MLXSW_ITEM32(reg, spvtr, tport, 0x00, 24, 1); 1721 1722 /* reg_spvtr_local_port 1723 * When tport = 0: local port number (Not supported from/to CPU). 1724 * When tport = 1: tunnel port. 1725 * Access: Index 1726 */ 1727 MLXSW_ITEM32(reg, spvtr, local_port, 0x00, 16, 8); 1728 1729 /* reg_spvtr_ippe 1730 * Ingress Port Prio Mode Update Enable. 1731 * When set, the Port Prio Mode is updated with the provided ipprio_mode field. 1732 * Reserved on Get operations. 1733 * Access: OP 1734 */ 1735 MLXSW_ITEM32(reg, spvtr, ippe, 0x04, 31, 1); 1736 1737 /* reg_spvtr_ipve 1738 * Ingress Port VID Mode Update Enable. 1739 * When set, the Ingress Port VID Mode is updated with the provided ipvid_mode 1740 * field. 1741 * Reserved on Get operations. 1742 * Access: OP 1743 */ 1744 MLXSW_ITEM32(reg, spvtr, ipve, 0x04, 30, 1); 1745 1746 /* reg_spvtr_epve 1747 * Egress Port VID Mode Update Enable. 1748 * When set, the Egress Port VID Mode is updated with the provided epvid_mode 1749 * field. 1750 * Access: OP 1751 */ 1752 MLXSW_ITEM32(reg, spvtr, epve, 0x04, 29, 1); 1753 1754 /* reg_spvtr_ipprio_mode 1755 * Ingress Port Priority Mode. 1756 * This controls the PCP and DEI of the new outer VLAN 1757 * Note: for SwitchX/-2 the DEI is not affected. 1758 * 0: use port default PCP and DEI (configured by QPDPC). 1759 * 1: use C-VLAN PCP and DEI. 1760 * Has no effect when ipvid_mode = 0. 1761 * Reserved when tport = 1. 1762 * Access: RW 1763 */ 1764 MLXSW_ITEM32(reg, spvtr, ipprio_mode, 0x04, 20, 4); 1765 1766 enum mlxsw_reg_spvtr_ipvid_mode { 1767 /* IEEE Compliant PVID (default) */ 1768 MLXSW_REG_SPVTR_IPVID_MODE_IEEE_COMPLIANT_PVID, 1769 /* Push VLAN (for VLAN stacking, except prio tagged packets) */ 1770 MLXSW_REG_SPVTR_IPVID_MODE_PUSH_VLAN_FOR_UNTAGGED_PACKET, 1771 /* Always push VLAN (also for prio tagged packets) */ 1772 MLXSW_REG_SPVTR_IPVID_MODE_ALWAYS_PUSH_VLAN, 1773 }; 1774 1775 /* reg_spvtr_ipvid_mode 1776 * Ingress Port VLAN-ID Mode. 1777 * For Spectrum family, this affects the values of SPVM.i 1778 * Access: RW 1779 */ 1780 MLXSW_ITEM32(reg, spvtr, ipvid_mode, 0x04, 16, 4); 1781 1782 enum mlxsw_reg_spvtr_epvid_mode { 1783 /* IEEE Compliant VLAN membership */ 1784 MLXSW_REG_SPVTR_EPVID_MODE_IEEE_COMPLIANT_VLAN_MEMBERSHIP, 1785 /* Pop VLAN (for VLAN stacking) */ 1786 MLXSW_REG_SPVTR_EPVID_MODE_POP_VLAN, 1787 }; 1788 1789 /* reg_spvtr_epvid_mode 1790 * Egress Port VLAN-ID Mode. 1791 * For Spectrum family, this affects the values of SPVM.e,u,pt. 1792 * Access: WO 1793 */ 1794 MLXSW_ITEM32(reg, spvtr, epvid_mode, 0x04, 0, 4); 1795 1796 static inline void mlxsw_reg_spvtr_pack(char *payload, bool tport, 1797 u8 local_port, 1798 enum mlxsw_reg_spvtr_ipvid_mode ipvid_mode) 1799 { 1800 MLXSW_REG_ZERO(spvtr, payload); 1801 mlxsw_reg_spvtr_tport_set(payload, tport); 1802 mlxsw_reg_spvtr_local_port_set(payload, local_port); 1803 mlxsw_reg_spvtr_ipvid_mode_set(payload, ipvid_mode); 1804 mlxsw_reg_spvtr_ipve_set(payload, true); 1805 } 1806 1807 /* SVPE - Switch Virtual-Port Enabling Register 1808 * -------------------------------------------- 1809 * Enables port virtualization. 1810 */ 1811 #define MLXSW_REG_SVPE_ID 0x201E 1812 #define MLXSW_REG_SVPE_LEN 0x4 1813 1814 MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN); 1815 1816 /* reg_svpe_local_port 1817 * Local port number 1818 * Access: Index 1819 * 1820 * Note: CPU port is not supported (uses VLAN mode only). 1821 */ 1822 MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8); 1823 1824 /* reg_svpe_vp_en 1825 * Virtual port enable. 1826 * 0 - Disable, VLAN mode (VID to FID). 1827 * 1 - Enable, Virtual port mode ({Port, VID} to FID). 1828 * Access: RW 1829 */ 1830 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1); 1831 1832 static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port, 1833 bool enable) 1834 { 1835 MLXSW_REG_ZERO(svpe, payload); 1836 mlxsw_reg_svpe_local_port_set(payload, local_port); 1837 mlxsw_reg_svpe_vp_en_set(payload, enable); 1838 } 1839 1840 /* SFMR - Switch FID Management Register 1841 * ------------------------------------- 1842 * Creates and configures FIDs. 1843 */ 1844 #define MLXSW_REG_SFMR_ID 0x201F 1845 #define MLXSW_REG_SFMR_LEN 0x18 1846 1847 MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN); 1848 1849 enum mlxsw_reg_sfmr_op { 1850 MLXSW_REG_SFMR_OP_CREATE_FID, 1851 MLXSW_REG_SFMR_OP_DESTROY_FID, 1852 }; 1853 1854 /* reg_sfmr_op 1855 * Operation. 1856 * 0 - Create or edit FID. 1857 * 1 - Destroy FID. 1858 * Access: WO 1859 */ 1860 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4); 1861 1862 /* reg_sfmr_fid 1863 * Filtering ID. 1864 * Access: Index 1865 */ 1866 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16); 1867 1868 /* reg_sfmr_fid_offset 1869 * FID offset. 1870 * Used to point into the flooding table selected by SFGC register if 1871 * the table is of type FID-Offset. Otherwise, this field is reserved. 1872 * Access: RW 1873 */ 1874 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16); 1875 1876 /* reg_sfmr_vtfp 1877 * Valid Tunnel Flood Pointer. 1878 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL. 1879 * Access: RW 1880 * 1881 * Note: Reserved for 802.1Q FIDs. 1882 */ 1883 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1); 1884 1885 /* reg_sfmr_nve_tunnel_flood_ptr 1886 * Underlay Flooding and BC Pointer. 1887 * Used as a pointer to the first entry of the group based link lists of 1888 * flooding or BC entries (for NVE tunnels). 1889 * Access: RW 1890 */ 1891 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24); 1892 1893 /* reg_sfmr_vv 1894 * VNI Valid. 1895 * If not set, then vni is reserved. 1896 * Access: RW 1897 * 1898 * Note: Reserved for 802.1Q FIDs. 1899 */ 1900 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1); 1901 1902 /* reg_sfmr_vni 1903 * Virtual Network Identifier. 1904 * Access: RW 1905 * 1906 * Note: A given VNI can only be assigned to one FID. 1907 */ 1908 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24); 1909 1910 static inline void mlxsw_reg_sfmr_pack(char *payload, 1911 enum mlxsw_reg_sfmr_op op, u16 fid, 1912 u16 fid_offset) 1913 { 1914 MLXSW_REG_ZERO(sfmr, payload); 1915 mlxsw_reg_sfmr_op_set(payload, op); 1916 mlxsw_reg_sfmr_fid_set(payload, fid); 1917 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset); 1918 mlxsw_reg_sfmr_vtfp_set(payload, false); 1919 mlxsw_reg_sfmr_vv_set(payload, false); 1920 } 1921 1922 /* SPVMLR - Switch Port VLAN MAC Learning Register 1923 * ----------------------------------------------- 1924 * Controls the switch MAC learning policy per {Port, VID}. 1925 */ 1926 #define MLXSW_REG_SPVMLR_ID 0x2020 1927 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */ 1928 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */ 1929 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255 1930 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \ 1931 MLXSW_REG_SPVMLR_REC_LEN * \ 1932 MLXSW_REG_SPVMLR_REC_MAX_COUNT) 1933 1934 MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN); 1935 1936 /* reg_spvmlr_local_port 1937 * Local ingress port. 1938 * Access: Index 1939 * 1940 * Note: CPU port is not supported. 1941 */ 1942 MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8); 1943 1944 /* reg_spvmlr_num_rec 1945 * Number of records to update. 1946 * Access: OP 1947 */ 1948 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8); 1949 1950 /* reg_spvmlr_rec_learn_enable 1951 * 0 - Disable learning for {Port, VID}. 1952 * 1 - Enable learning for {Port, VID}. 1953 * Access: RW 1954 */ 1955 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN, 1956 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1957 1958 /* reg_spvmlr_rec_vid 1959 * VLAN ID to be added/removed from port or for querying. 1960 * Access: Index 1961 */ 1962 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12, 1963 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1964 1965 static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port, 1966 u16 vid_begin, u16 vid_end, 1967 bool learn_enable) 1968 { 1969 int num_rec = vid_end - vid_begin + 1; 1970 int i; 1971 1972 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT); 1973 1974 MLXSW_REG_ZERO(spvmlr, payload); 1975 mlxsw_reg_spvmlr_local_port_set(payload, local_port); 1976 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec); 1977 1978 for (i = 0; i < num_rec; i++) { 1979 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable); 1980 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i); 1981 } 1982 } 1983 1984 /* SPVC - Switch Port VLAN Classification Register 1985 * ----------------------------------------------- 1986 * Configures the port to identify packets as untagged / single tagged / 1987 * double packets based on the packet EtherTypes. 1988 * Ethertype IDs are configured by SVER. 1989 */ 1990 #define MLXSW_REG_SPVC_ID 0x2026 1991 #define MLXSW_REG_SPVC_LEN 0x0C 1992 1993 MLXSW_REG_DEFINE(spvc, MLXSW_REG_SPVC_ID, MLXSW_REG_SPVC_LEN); 1994 1995 /* reg_spvc_local_port 1996 * Local port. 1997 * Access: Index 1998 * 1999 * Note: applies both to Rx port and Tx port, so if a packet traverses 2000 * through Rx port i and a Tx port j then port i and port j must have the 2001 * same configuration. 2002 */ 2003 MLXSW_ITEM32(reg, spvc, local_port, 0x00, 16, 8); 2004 2005 /* reg_spvc_inner_et2 2006 * Vlan Tag1 EtherType2 enable. 2007 * Packet is initially classified as double VLAN Tag if in addition to 2008 * being classified with a tag0 VLAN Tag its tag1 EtherType value is 2009 * equal to ether_type2. 2010 * 0: disable (default) 2011 * 1: enable 2012 * Access: RW 2013 */ 2014 MLXSW_ITEM32(reg, spvc, inner_et2, 0x08, 17, 1); 2015 2016 /* reg_spvc_et2 2017 * Vlan Tag0 EtherType2 enable. 2018 * Packet is initially classified as VLAN Tag if its tag0 EtherType is 2019 * equal to ether_type2. 2020 * 0: disable (default) 2021 * 1: enable 2022 * Access: RW 2023 */ 2024 MLXSW_ITEM32(reg, spvc, et2, 0x08, 16, 1); 2025 2026 /* reg_spvc_inner_et1 2027 * Vlan Tag1 EtherType1 enable. 2028 * Packet is initially classified as double VLAN Tag if in addition to 2029 * being classified with a tag0 VLAN Tag its tag1 EtherType value is 2030 * equal to ether_type1. 2031 * 0: disable 2032 * 1: enable (default) 2033 * Access: RW 2034 */ 2035 MLXSW_ITEM32(reg, spvc, inner_et1, 0x08, 9, 1); 2036 2037 /* reg_spvc_et1 2038 * Vlan Tag0 EtherType1 enable. 2039 * Packet is initially classified as VLAN Tag if its tag0 EtherType is 2040 * equal to ether_type1. 2041 * 0: disable 2042 * 1: enable (default) 2043 * Access: RW 2044 */ 2045 MLXSW_ITEM32(reg, spvc, et1, 0x08, 8, 1); 2046 2047 /* reg_inner_et0 2048 * Vlan Tag1 EtherType0 enable. 2049 * Packet is initially classified as double VLAN Tag if in addition to 2050 * being classified with a tag0 VLAN Tag its tag1 EtherType value is 2051 * equal to ether_type0. 2052 * 0: disable 2053 * 1: enable (default) 2054 * Access: RW 2055 */ 2056 MLXSW_ITEM32(reg, spvc, inner_et0, 0x08, 1, 1); 2057 2058 /* reg_et0 2059 * Vlan Tag0 EtherType0 enable. 2060 * Packet is initially classified as VLAN Tag if its tag0 EtherType is 2061 * equal to ether_type0. 2062 * 0: disable 2063 * 1: enable (default) 2064 * Access: RW 2065 */ 2066 MLXSW_ITEM32(reg, spvc, et0, 0x08, 0, 1); 2067 2068 static inline void mlxsw_reg_spvc_pack(char *payload, u8 local_port, bool et1, 2069 bool et0) 2070 { 2071 MLXSW_REG_ZERO(spvc, payload); 2072 mlxsw_reg_spvc_local_port_set(payload, local_port); 2073 /* Enable inner_et1 and inner_et0 to enable identification of double 2074 * tagged packets. 2075 */ 2076 mlxsw_reg_spvc_inner_et1_set(payload, 1); 2077 mlxsw_reg_spvc_inner_et0_set(payload, 1); 2078 mlxsw_reg_spvc_et1_set(payload, et1); 2079 mlxsw_reg_spvc_et0_set(payload, et0); 2080 } 2081 2082 /* CWTP - Congetion WRED ECN TClass Profile 2083 * ---------------------------------------- 2084 * Configures the profiles for queues of egress port and traffic class 2085 */ 2086 #define MLXSW_REG_CWTP_ID 0x2802 2087 #define MLXSW_REG_CWTP_BASE_LEN 0x28 2088 #define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08 2089 #define MLXSW_REG_CWTP_LEN 0x40 2090 2091 MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN); 2092 2093 /* reg_cwtp_local_port 2094 * Local port number 2095 * Not supported for CPU port 2096 * Access: Index 2097 */ 2098 MLXSW_ITEM32(reg, cwtp, local_port, 0, 16, 8); 2099 2100 /* reg_cwtp_traffic_class 2101 * Traffic Class to configure 2102 * Access: Index 2103 */ 2104 MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8); 2105 2106 /* reg_cwtp_profile_min 2107 * Minimum Average Queue Size of the profile in cells. 2108 * Access: RW 2109 */ 2110 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN, 2111 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false); 2112 2113 /* reg_cwtp_profile_percent 2114 * Percentage of WRED and ECN marking for maximum Average Queue size 2115 * Range is 0 to 100, units of integer percentage 2116 * Access: RW 2117 */ 2118 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN, 2119 24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 2120 2121 /* reg_cwtp_profile_max 2122 * Maximum Average Queue size of the profile in cells 2123 * Access: RW 2124 */ 2125 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN, 2126 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 2127 2128 #define MLXSW_REG_CWTP_MIN_VALUE 64 2129 #define MLXSW_REG_CWTP_MAX_PROFILE 2 2130 #define MLXSW_REG_CWTP_DEFAULT_PROFILE 1 2131 2132 static inline void mlxsw_reg_cwtp_pack(char *payload, u8 local_port, 2133 u8 traffic_class) 2134 { 2135 int i; 2136 2137 MLXSW_REG_ZERO(cwtp, payload); 2138 mlxsw_reg_cwtp_local_port_set(payload, local_port); 2139 mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class); 2140 2141 for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) { 2142 mlxsw_reg_cwtp_profile_min_set(payload, i, 2143 MLXSW_REG_CWTP_MIN_VALUE); 2144 mlxsw_reg_cwtp_profile_max_set(payload, i, 2145 MLXSW_REG_CWTP_MIN_VALUE); 2146 } 2147 } 2148 2149 #define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1) 2150 2151 static inline void 2152 mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max, 2153 u32 probability) 2154 { 2155 u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile); 2156 2157 mlxsw_reg_cwtp_profile_min_set(payload, index, min); 2158 mlxsw_reg_cwtp_profile_max_set(payload, index, max); 2159 mlxsw_reg_cwtp_profile_percent_set(payload, index, probability); 2160 } 2161 2162 /* CWTPM - Congestion WRED ECN TClass and Pool Mapping 2163 * --------------------------------------------------- 2164 * The CWTPM register maps each egress port and traffic class to profile num. 2165 */ 2166 #define MLXSW_REG_CWTPM_ID 0x2803 2167 #define MLXSW_REG_CWTPM_LEN 0x44 2168 2169 MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN); 2170 2171 /* reg_cwtpm_local_port 2172 * Local port number 2173 * Not supported for CPU port 2174 * Access: Index 2175 */ 2176 MLXSW_ITEM32(reg, cwtpm, local_port, 0, 16, 8); 2177 2178 /* reg_cwtpm_traffic_class 2179 * Traffic Class to configure 2180 * Access: Index 2181 */ 2182 MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8); 2183 2184 /* reg_cwtpm_ew 2185 * Control enablement of WRED for traffic class: 2186 * 0 - Disable 2187 * 1 - Enable 2188 * Access: RW 2189 */ 2190 MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1); 2191 2192 /* reg_cwtpm_ee 2193 * Control enablement of ECN for traffic class: 2194 * 0 - Disable 2195 * 1 - Enable 2196 * Access: RW 2197 */ 2198 MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1); 2199 2200 /* reg_cwtpm_tcp_g 2201 * TCP Green Profile. 2202 * Index of the profile within {port, traffic class} to use. 2203 * 0 for disabling both WRED and ECN for this type of traffic. 2204 * Access: RW 2205 */ 2206 MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2); 2207 2208 /* reg_cwtpm_tcp_y 2209 * TCP Yellow Profile. 2210 * Index of the profile within {port, traffic class} to use. 2211 * 0 for disabling both WRED and ECN for this type of traffic. 2212 * Access: RW 2213 */ 2214 MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2); 2215 2216 /* reg_cwtpm_tcp_r 2217 * TCP Red Profile. 2218 * Index of the profile within {port, traffic class} to use. 2219 * 0 for disabling both WRED and ECN for this type of traffic. 2220 * Access: RW 2221 */ 2222 MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2); 2223 2224 /* reg_cwtpm_ntcp_g 2225 * Non-TCP Green Profile. 2226 * Index of the profile within {port, traffic class} to use. 2227 * 0 for disabling both WRED and ECN for this type of traffic. 2228 * Access: RW 2229 */ 2230 MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2); 2231 2232 /* reg_cwtpm_ntcp_y 2233 * Non-TCP Yellow Profile. 2234 * Index of the profile within {port, traffic class} to use. 2235 * 0 for disabling both WRED and ECN for this type of traffic. 2236 * Access: RW 2237 */ 2238 MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2); 2239 2240 /* reg_cwtpm_ntcp_r 2241 * Non-TCP Red Profile. 2242 * Index of the profile within {port, traffic class} to use. 2243 * 0 for disabling both WRED and ECN for this type of traffic. 2244 * Access: RW 2245 */ 2246 MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2); 2247 2248 #define MLXSW_REG_CWTPM_RESET_PROFILE 0 2249 2250 static inline void mlxsw_reg_cwtpm_pack(char *payload, u8 local_port, 2251 u8 traffic_class, u8 profile, 2252 bool wred, bool ecn) 2253 { 2254 MLXSW_REG_ZERO(cwtpm, payload); 2255 mlxsw_reg_cwtpm_local_port_set(payload, local_port); 2256 mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class); 2257 mlxsw_reg_cwtpm_ew_set(payload, wred); 2258 mlxsw_reg_cwtpm_ee_set(payload, ecn); 2259 mlxsw_reg_cwtpm_tcp_g_set(payload, profile); 2260 mlxsw_reg_cwtpm_tcp_y_set(payload, profile); 2261 mlxsw_reg_cwtpm_tcp_r_set(payload, profile); 2262 mlxsw_reg_cwtpm_ntcp_g_set(payload, profile); 2263 mlxsw_reg_cwtpm_ntcp_y_set(payload, profile); 2264 mlxsw_reg_cwtpm_ntcp_r_set(payload, profile); 2265 } 2266 2267 /* PGCR - Policy-Engine General Configuration Register 2268 * --------------------------------------------------- 2269 * This register configures general Policy-Engine settings. 2270 */ 2271 #define MLXSW_REG_PGCR_ID 0x3001 2272 #define MLXSW_REG_PGCR_LEN 0x20 2273 2274 MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN); 2275 2276 /* reg_pgcr_default_action_pointer_base 2277 * Default action pointer base. Each region has a default action pointer 2278 * which is equal to default_action_pointer_base + region_id. 2279 * Access: RW 2280 */ 2281 MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24); 2282 2283 static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base) 2284 { 2285 MLXSW_REG_ZERO(pgcr, payload); 2286 mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base); 2287 } 2288 2289 /* PPBT - Policy-Engine Port Binding Table 2290 * --------------------------------------- 2291 * This register is used for configuration of the Port Binding Table. 2292 */ 2293 #define MLXSW_REG_PPBT_ID 0x3002 2294 #define MLXSW_REG_PPBT_LEN 0x14 2295 2296 MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN); 2297 2298 enum mlxsw_reg_pxbt_e { 2299 MLXSW_REG_PXBT_E_IACL, 2300 MLXSW_REG_PXBT_E_EACL, 2301 }; 2302 2303 /* reg_ppbt_e 2304 * Access: Index 2305 */ 2306 MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1); 2307 2308 enum mlxsw_reg_pxbt_op { 2309 MLXSW_REG_PXBT_OP_BIND, 2310 MLXSW_REG_PXBT_OP_UNBIND, 2311 }; 2312 2313 /* reg_ppbt_op 2314 * Access: RW 2315 */ 2316 MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3); 2317 2318 /* reg_ppbt_local_port 2319 * Local port. Not including CPU port. 2320 * Access: Index 2321 */ 2322 MLXSW_ITEM32(reg, ppbt, local_port, 0x00, 16, 8); 2323 2324 /* reg_ppbt_g 2325 * group - When set, the binding is of an ACL group. When cleared, 2326 * the binding is of an ACL. 2327 * Must be set to 1 for Spectrum. 2328 * Access: RW 2329 */ 2330 MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1); 2331 2332 /* reg_ppbt_acl_info 2333 * ACL/ACL group identifier. If the g bit is set, this field should hold 2334 * the acl_group_id, else it should hold the acl_id. 2335 * Access: RW 2336 */ 2337 MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16); 2338 2339 static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e, 2340 enum mlxsw_reg_pxbt_op op, 2341 u8 local_port, u16 acl_info) 2342 { 2343 MLXSW_REG_ZERO(ppbt, payload); 2344 mlxsw_reg_ppbt_e_set(payload, e); 2345 mlxsw_reg_ppbt_op_set(payload, op); 2346 mlxsw_reg_ppbt_local_port_set(payload, local_port); 2347 mlxsw_reg_ppbt_g_set(payload, true); 2348 mlxsw_reg_ppbt_acl_info_set(payload, acl_info); 2349 } 2350 2351 /* PACL - Policy-Engine ACL Register 2352 * --------------------------------- 2353 * This register is used for configuration of the ACL. 2354 */ 2355 #define MLXSW_REG_PACL_ID 0x3004 2356 #define MLXSW_REG_PACL_LEN 0x70 2357 2358 MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN); 2359 2360 /* reg_pacl_v 2361 * Valid. Setting the v bit makes the ACL valid. It should not be cleared 2362 * while the ACL is bounded to either a port, VLAN or ACL rule. 2363 * Access: RW 2364 */ 2365 MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1); 2366 2367 /* reg_pacl_acl_id 2368 * An identifier representing the ACL (managed by software) 2369 * Range 0 .. cap_max_acl_regions - 1 2370 * Access: Index 2371 */ 2372 MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16); 2373 2374 #define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16 2375 2376 /* reg_pacl_tcam_region_info 2377 * Opaque object that represents a TCAM region. 2378 * Obtained through PTAR register. 2379 * Access: RW 2380 */ 2381 MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30, 2382 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2383 2384 static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id, 2385 bool valid, const char *tcam_region_info) 2386 { 2387 MLXSW_REG_ZERO(pacl, payload); 2388 mlxsw_reg_pacl_acl_id_set(payload, acl_id); 2389 mlxsw_reg_pacl_v_set(payload, valid); 2390 mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info); 2391 } 2392 2393 /* PAGT - Policy-Engine ACL Group Table 2394 * ------------------------------------ 2395 * This register is used for configuration of the ACL Group Table. 2396 */ 2397 #define MLXSW_REG_PAGT_ID 0x3005 2398 #define MLXSW_REG_PAGT_BASE_LEN 0x30 2399 #define MLXSW_REG_PAGT_ACL_LEN 4 2400 #define MLXSW_REG_PAGT_ACL_MAX_NUM 16 2401 #define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \ 2402 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN) 2403 2404 MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN); 2405 2406 /* reg_pagt_size 2407 * Number of ACLs in the group. 2408 * Size 0 invalidates a group. 2409 * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now) 2410 * Total number of ACLs in all groups must be lower or equal 2411 * to cap_max_acl_tot_groups 2412 * Note: a group which is binded must not be invalidated 2413 * Access: Index 2414 */ 2415 MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8); 2416 2417 /* reg_pagt_acl_group_id 2418 * An identifier (numbered from 0..cap_max_acl_groups-1) representing 2419 * the ACL Group identifier (managed by software). 2420 * Access: Index 2421 */ 2422 MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16); 2423 2424 /* reg_pagt_multi 2425 * Multi-ACL 2426 * 0 - This ACL is the last ACL in the multi-ACL 2427 * 1 - This ACL is part of a multi-ACL 2428 * Access: RW 2429 */ 2430 MLXSW_ITEM32_INDEXED(reg, pagt, multi, 0x30, 31, 1, 0x04, 0x00, false); 2431 2432 /* reg_pagt_acl_id 2433 * ACL identifier 2434 * Access: RW 2435 */ 2436 MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false); 2437 2438 static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id) 2439 { 2440 MLXSW_REG_ZERO(pagt, payload); 2441 mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id); 2442 } 2443 2444 static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index, 2445 u16 acl_id, bool multi) 2446 { 2447 u8 size = mlxsw_reg_pagt_size_get(payload); 2448 2449 if (index >= size) 2450 mlxsw_reg_pagt_size_set(payload, index + 1); 2451 mlxsw_reg_pagt_multi_set(payload, index, multi); 2452 mlxsw_reg_pagt_acl_id_set(payload, index, acl_id); 2453 } 2454 2455 /* PTAR - Policy-Engine TCAM Allocation Register 2456 * --------------------------------------------- 2457 * This register is used for allocation of regions in the TCAM. 2458 * Note: Query method is not supported on this register. 2459 */ 2460 #define MLXSW_REG_PTAR_ID 0x3006 2461 #define MLXSW_REG_PTAR_BASE_LEN 0x20 2462 #define MLXSW_REG_PTAR_KEY_ID_LEN 1 2463 #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16 2464 #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \ 2465 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN) 2466 2467 MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN); 2468 2469 enum mlxsw_reg_ptar_op { 2470 /* allocate a TCAM region */ 2471 MLXSW_REG_PTAR_OP_ALLOC, 2472 /* resize a TCAM region */ 2473 MLXSW_REG_PTAR_OP_RESIZE, 2474 /* deallocate TCAM region */ 2475 MLXSW_REG_PTAR_OP_FREE, 2476 /* test allocation */ 2477 MLXSW_REG_PTAR_OP_TEST, 2478 }; 2479 2480 /* reg_ptar_op 2481 * Access: OP 2482 */ 2483 MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4); 2484 2485 /* reg_ptar_action_set_type 2486 * Type of action set to be used on this region. 2487 * For Spectrum and Spectrum-2, this is always type 2 - "flexible" 2488 * Access: WO 2489 */ 2490 MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8); 2491 2492 enum mlxsw_reg_ptar_key_type { 2493 MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50, /* Spetrum */ 2494 MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51, /* Spectrum-2 */ 2495 }; 2496 2497 /* reg_ptar_key_type 2498 * TCAM key type for the region. 2499 * Access: WO 2500 */ 2501 MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8); 2502 2503 /* reg_ptar_region_size 2504 * TCAM region size. When allocating/resizing this is the requested size, 2505 * the response is the actual size. Note that actual size may be 2506 * larger than requested. 2507 * Allowed range 1 .. cap_max_rules-1 2508 * Reserved during op deallocate. 2509 * Access: WO 2510 */ 2511 MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16); 2512 2513 /* reg_ptar_region_id 2514 * Region identifier 2515 * Range 0 .. cap_max_regions-1 2516 * Access: Index 2517 */ 2518 MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16); 2519 2520 /* reg_ptar_tcam_region_info 2521 * Opaque object that represents the TCAM region. 2522 * Returned when allocating a region. 2523 * Provided by software for ACL generation and region deallocation and resize. 2524 * Access: RW 2525 */ 2526 MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10, 2527 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2528 2529 /* reg_ptar_flexible_key_id 2530 * Identifier of the Flexible Key. 2531 * Only valid if key_type == "FLEX_KEY" 2532 * The key size will be rounded up to one of the following values: 2533 * 9B, 18B, 36B, 54B. 2534 * This field is reserved for in resize operation. 2535 * Access: WO 2536 */ 2537 MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8, 2538 MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false); 2539 2540 static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op, 2541 enum mlxsw_reg_ptar_key_type key_type, 2542 u16 region_size, u16 region_id, 2543 const char *tcam_region_info) 2544 { 2545 MLXSW_REG_ZERO(ptar, payload); 2546 mlxsw_reg_ptar_op_set(payload, op); 2547 mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */ 2548 mlxsw_reg_ptar_key_type_set(payload, key_type); 2549 mlxsw_reg_ptar_region_size_set(payload, region_size); 2550 mlxsw_reg_ptar_region_id_set(payload, region_id); 2551 mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info); 2552 } 2553 2554 static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index, 2555 u16 key_id) 2556 { 2557 mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id); 2558 } 2559 2560 static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info) 2561 { 2562 mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info); 2563 } 2564 2565 /* PPBS - Policy-Engine Policy Based Switching Register 2566 * ---------------------------------------------------- 2567 * This register retrieves and sets Policy Based Switching Table entries. 2568 */ 2569 #define MLXSW_REG_PPBS_ID 0x300C 2570 #define MLXSW_REG_PPBS_LEN 0x14 2571 2572 MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN); 2573 2574 /* reg_ppbs_pbs_ptr 2575 * Index into the PBS table. 2576 * For Spectrum, the index points to the KVD Linear. 2577 * Access: Index 2578 */ 2579 MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24); 2580 2581 /* reg_ppbs_system_port 2582 * Unique port identifier for the final destination of the packet. 2583 * Access: RW 2584 */ 2585 MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16); 2586 2587 static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr, 2588 u16 system_port) 2589 { 2590 MLXSW_REG_ZERO(ppbs, payload); 2591 mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr); 2592 mlxsw_reg_ppbs_system_port_set(payload, system_port); 2593 } 2594 2595 /* PRCR - Policy-Engine Rules Copy Register 2596 * ---------------------------------------- 2597 * This register is used for accessing rules within a TCAM region. 2598 */ 2599 #define MLXSW_REG_PRCR_ID 0x300D 2600 #define MLXSW_REG_PRCR_LEN 0x40 2601 2602 MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN); 2603 2604 enum mlxsw_reg_prcr_op { 2605 /* Move rules. Moves the rules from "tcam_region_info" starting 2606 * at offset "offset" to "dest_tcam_region_info" 2607 * at offset "dest_offset." 2608 */ 2609 MLXSW_REG_PRCR_OP_MOVE, 2610 /* Copy rules. Copies the rules from "tcam_region_info" starting 2611 * at offset "offset" to "dest_tcam_region_info" 2612 * at offset "dest_offset." 2613 */ 2614 MLXSW_REG_PRCR_OP_COPY, 2615 }; 2616 2617 /* reg_prcr_op 2618 * Access: OP 2619 */ 2620 MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4); 2621 2622 /* reg_prcr_offset 2623 * Offset within the source region to copy/move from. 2624 * Access: Index 2625 */ 2626 MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16); 2627 2628 /* reg_prcr_size 2629 * The number of rules to copy/move. 2630 * Access: WO 2631 */ 2632 MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16); 2633 2634 /* reg_prcr_tcam_region_info 2635 * Opaque object that represents the source TCAM region. 2636 * Access: Index 2637 */ 2638 MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10, 2639 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2640 2641 /* reg_prcr_dest_offset 2642 * Offset within the source region to copy/move to. 2643 * Access: Index 2644 */ 2645 MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16); 2646 2647 /* reg_prcr_dest_tcam_region_info 2648 * Opaque object that represents the destination TCAM region. 2649 * Access: Index 2650 */ 2651 MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30, 2652 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2653 2654 static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op, 2655 const char *src_tcam_region_info, 2656 u16 src_offset, 2657 const char *dest_tcam_region_info, 2658 u16 dest_offset, u16 size) 2659 { 2660 MLXSW_REG_ZERO(prcr, payload); 2661 mlxsw_reg_prcr_op_set(payload, op); 2662 mlxsw_reg_prcr_offset_set(payload, src_offset); 2663 mlxsw_reg_prcr_size_set(payload, size); 2664 mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload, 2665 src_tcam_region_info); 2666 mlxsw_reg_prcr_dest_offset_set(payload, dest_offset); 2667 mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload, 2668 dest_tcam_region_info); 2669 } 2670 2671 /* PEFA - Policy-Engine Extended Flexible Action Register 2672 * ------------------------------------------------------ 2673 * This register is used for accessing an extended flexible action entry 2674 * in the central KVD Linear Database. 2675 */ 2676 #define MLXSW_REG_PEFA_ID 0x300F 2677 #define MLXSW_REG_PEFA_LEN 0xB0 2678 2679 MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN); 2680 2681 /* reg_pefa_index 2682 * Index in the KVD Linear Centralized Database. 2683 * Access: Index 2684 */ 2685 MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24); 2686 2687 /* reg_pefa_a 2688 * Index in the KVD Linear Centralized Database. 2689 * Activity 2690 * For a new entry: set if ca=0, clear if ca=1 2691 * Set if a packet lookup has hit on the specific entry 2692 * Access: RO 2693 */ 2694 MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1); 2695 2696 /* reg_pefa_ca 2697 * Clear activity 2698 * When write: activity is according to this field 2699 * When read: after reading the activity is cleared according to ca 2700 * Access: OP 2701 */ 2702 MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1); 2703 2704 #define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8 2705 2706 /* reg_pefa_flex_action_set 2707 * Action-set to perform when rule is matched. 2708 * Must be zero padded if action set is shorter. 2709 * Access: RW 2710 */ 2711 MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN); 2712 2713 static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca, 2714 const char *flex_action_set) 2715 { 2716 MLXSW_REG_ZERO(pefa, payload); 2717 mlxsw_reg_pefa_index_set(payload, index); 2718 mlxsw_reg_pefa_ca_set(payload, ca); 2719 if (flex_action_set) 2720 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload, 2721 flex_action_set); 2722 } 2723 2724 static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a) 2725 { 2726 *p_a = mlxsw_reg_pefa_a_get(payload); 2727 } 2728 2729 /* PEMRBT - Policy-Engine Multicast Router Binding Table Register 2730 * -------------------------------------------------------------- 2731 * This register is used for binding Multicast router to an ACL group 2732 * that serves the MC router. 2733 * This register is not supported by SwitchX/-2 and Spectrum. 2734 */ 2735 #define MLXSW_REG_PEMRBT_ID 0x3014 2736 #define MLXSW_REG_PEMRBT_LEN 0x14 2737 2738 MLXSW_REG_DEFINE(pemrbt, MLXSW_REG_PEMRBT_ID, MLXSW_REG_PEMRBT_LEN); 2739 2740 enum mlxsw_reg_pemrbt_protocol { 2741 MLXSW_REG_PEMRBT_PROTO_IPV4, 2742 MLXSW_REG_PEMRBT_PROTO_IPV6, 2743 }; 2744 2745 /* reg_pemrbt_protocol 2746 * Access: Index 2747 */ 2748 MLXSW_ITEM32(reg, pemrbt, protocol, 0x00, 0, 1); 2749 2750 /* reg_pemrbt_group_id 2751 * ACL group identifier. 2752 * Range 0..cap_max_acl_groups-1 2753 * Access: RW 2754 */ 2755 MLXSW_ITEM32(reg, pemrbt, group_id, 0x10, 0, 16); 2756 2757 static inline void 2758 mlxsw_reg_pemrbt_pack(char *payload, enum mlxsw_reg_pemrbt_protocol protocol, 2759 u16 group_id) 2760 { 2761 MLXSW_REG_ZERO(pemrbt, payload); 2762 mlxsw_reg_pemrbt_protocol_set(payload, protocol); 2763 mlxsw_reg_pemrbt_group_id_set(payload, group_id); 2764 } 2765 2766 /* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2 2767 * ----------------------------------------------------- 2768 * This register is used for accessing rules within a TCAM region. 2769 * It is a new version of PTCE in order to support wider key, 2770 * mask and action within a TCAM region. This register is not supported 2771 * by SwitchX and SwitchX-2. 2772 */ 2773 #define MLXSW_REG_PTCE2_ID 0x3017 2774 #define MLXSW_REG_PTCE2_LEN 0x1D8 2775 2776 MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN); 2777 2778 /* reg_ptce2_v 2779 * Valid. 2780 * Access: RW 2781 */ 2782 MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1); 2783 2784 /* reg_ptce2_a 2785 * Activity. Set if a packet lookup has hit on the specific entry. 2786 * To clear the "a" bit, use "clear activity" op or "clear on read" op. 2787 * Access: RO 2788 */ 2789 MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1); 2790 2791 enum mlxsw_reg_ptce2_op { 2792 /* Read operation. */ 2793 MLXSW_REG_PTCE2_OP_QUERY_READ = 0, 2794 /* clear on read operation. Used to read entry 2795 * and clear Activity bit. 2796 */ 2797 MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1, 2798 /* Write operation. Used to write a new entry to the table. 2799 * All R/W fields are relevant for new entry. Activity bit is set 2800 * for new entries - Note write with v = 0 will delete the entry. 2801 */ 2802 MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0, 2803 /* Update action. Only action set will be updated. */ 2804 MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1, 2805 /* Clear activity. A bit is cleared for the entry. */ 2806 MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2, 2807 }; 2808 2809 /* reg_ptce2_op 2810 * Access: OP 2811 */ 2812 MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3); 2813 2814 /* reg_ptce2_offset 2815 * Access: Index 2816 */ 2817 MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16); 2818 2819 /* reg_ptce2_priority 2820 * Priority of the rule, higher values win. The range is 1..cap_kvd_size-1. 2821 * Note: priority does not have to be unique per rule. 2822 * Within a region, higher priority should have lower offset (no limitation 2823 * between regions in a multi-region). 2824 * Access: RW 2825 */ 2826 MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24); 2827 2828 /* reg_ptce2_tcam_region_info 2829 * Opaque object that represents the TCAM region. 2830 * Access: Index 2831 */ 2832 MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10, 2833 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2834 2835 #define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 96 2836 2837 /* reg_ptce2_flex_key_blocks 2838 * ACL Key. 2839 * Access: RW 2840 */ 2841 MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20, 2842 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2843 2844 /* reg_ptce2_mask 2845 * mask- in the same size as key. A bit that is set directs the TCAM 2846 * to compare the corresponding bit in key. A bit that is clear directs 2847 * the TCAM to ignore the corresponding bit in key. 2848 * Access: RW 2849 */ 2850 MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80, 2851 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2852 2853 /* reg_ptce2_flex_action_set 2854 * ACL action set. 2855 * Access: RW 2856 */ 2857 MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0, 2858 MLXSW_REG_FLEX_ACTION_SET_LEN); 2859 2860 static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid, 2861 enum mlxsw_reg_ptce2_op op, 2862 const char *tcam_region_info, 2863 u16 offset, u32 priority) 2864 { 2865 MLXSW_REG_ZERO(ptce2, payload); 2866 mlxsw_reg_ptce2_v_set(payload, valid); 2867 mlxsw_reg_ptce2_op_set(payload, op); 2868 mlxsw_reg_ptce2_offset_set(payload, offset); 2869 mlxsw_reg_ptce2_priority_set(payload, priority); 2870 mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info); 2871 } 2872 2873 /* PERPT - Policy-Engine ERP Table Register 2874 * ---------------------------------------- 2875 * This register adds and removes eRPs from the eRP table. 2876 */ 2877 #define MLXSW_REG_PERPT_ID 0x3021 2878 #define MLXSW_REG_PERPT_LEN 0x80 2879 2880 MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN); 2881 2882 /* reg_perpt_erpt_bank 2883 * eRP table bank. 2884 * Range 0 .. cap_max_erp_table_banks - 1 2885 * Access: Index 2886 */ 2887 MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4); 2888 2889 /* reg_perpt_erpt_index 2890 * Index to eRP table within the eRP bank. 2891 * Range is 0 .. cap_max_erp_table_bank_size - 1 2892 * Access: Index 2893 */ 2894 MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8); 2895 2896 enum mlxsw_reg_perpt_key_size { 2897 MLXSW_REG_PERPT_KEY_SIZE_2KB, 2898 MLXSW_REG_PERPT_KEY_SIZE_4KB, 2899 MLXSW_REG_PERPT_KEY_SIZE_8KB, 2900 MLXSW_REG_PERPT_KEY_SIZE_12KB, 2901 }; 2902 2903 /* reg_perpt_key_size 2904 * Access: OP 2905 */ 2906 MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4); 2907 2908 /* reg_perpt_bf_bypass 2909 * 0 - The eRP is used only if bloom filter state is set for the given 2910 * rule. 2911 * 1 - The eRP is used regardless of bloom filter state. 2912 * The bypass is an OR condition of region_id or eRP. See PERCR.bf_bypass 2913 * Access: RW 2914 */ 2915 MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1); 2916 2917 /* reg_perpt_erp_id 2918 * eRP ID for use by the rules. 2919 * Access: RW 2920 */ 2921 MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4); 2922 2923 /* reg_perpt_erpt_base_bank 2924 * Base eRP table bank, points to head of erp_vector 2925 * Range is 0 .. cap_max_erp_table_banks - 1 2926 * Access: OP 2927 */ 2928 MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4); 2929 2930 /* reg_perpt_erpt_base_index 2931 * Base index to eRP table within the eRP bank 2932 * Range is 0 .. cap_max_erp_table_bank_size - 1 2933 * Access: OP 2934 */ 2935 MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8); 2936 2937 /* reg_perpt_erp_index_in_vector 2938 * eRP index in the vector. 2939 * Access: OP 2940 */ 2941 MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4); 2942 2943 /* reg_perpt_erp_vector 2944 * eRP vector. 2945 * Access: OP 2946 */ 2947 MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1); 2948 2949 /* reg_perpt_mask 2950 * Mask 2951 * 0 - A-TCAM will ignore the bit in key 2952 * 1 - A-TCAM will compare the bit in key 2953 * Access: RW 2954 */ 2955 MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2956 2957 static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload, 2958 unsigned long *erp_vector, 2959 unsigned long size) 2960 { 2961 unsigned long bit; 2962 2963 for_each_set_bit(bit, erp_vector, size) 2964 mlxsw_reg_perpt_erp_vector_set(payload, bit, true); 2965 } 2966 2967 static inline void 2968 mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index, 2969 enum mlxsw_reg_perpt_key_size key_size, u8 erp_id, 2970 u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index, 2971 char *mask) 2972 { 2973 MLXSW_REG_ZERO(perpt, payload); 2974 mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank); 2975 mlxsw_reg_perpt_erpt_index_set(payload, erpt_index); 2976 mlxsw_reg_perpt_key_size_set(payload, key_size); 2977 mlxsw_reg_perpt_bf_bypass_set(payload, false); 2978 mlxsw_reg_perpt_erp_id_set(payload, erp_id); 2979 mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank); 2980 mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index); 2981 mlxsw_reg_perpt_erp_index_in_vector_set(payload, erp_index); 2982 mlxsw_reg_perpt_mask_memcpy_to(payload, mask); 2983 } 2984 2985 /* PERAR - Policy-Engine Region Association Register 2986 * ------------------------------------------------- 2987 * This register associates a hw region for region_id's. Changing on the fly 2988 * is supported by the device. 2989 */ 2990 #define MLXSW_REG_PERAR_ID 0x3026 2991 #define MLXSW_REG_PERAR_LEN 0x08 2992 2993 MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN); 2994 2995 /* reg_perar_region_id 2996 * Region identifier 2997 * Range 0 .. cap_max_regions-1 2998 * Access: Index 2999 */ 3000 MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16); 3001 3002 static inline unsigned int 3003 mlxsw_reg_perar_hw_regions_needed(unsigned int block_num) 3004 { 3005 return DIV_ROUND_UP(block_num, 4); 3006 } 3007 3008 /* reg_perar_hw_region 3009 * HW Region 3010 * Range 0 .. cap_max_regions-1 3011 * Default: hw_region = region_id 3012 * For a 8 key block region, 2 consecutive regions are used 3013 * For a 12 key block region, 3 consecutive regions are used 3014 * Access: RW 3015 */ 3016 MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16); 3017 3018 static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id, 3019 u16 hw_region) 3020 { 3021 MLXSW_REG_ZERO(perar, payload); 3022 mlxsw_reg_perar_region_id_set(payload, region_id); 3023 mlxsw_reg_perar_hw_region_set(payload, hw_region); 3024 } 3025 3026 /* PTCE-V3 - Policy-Engine TCAM Entry Register Version 3 3027 * ----------------------------------------------------- 3028 * This register is a new version of PTCE-V2 in order to support the 3029 * A-TCAM. This register is not supported by SwitchX/-2 and Spectrum. 3030 */ 3031 #define MLXSW_REG_PTCE3_ID 0x3027 3032 #define MLXSW_REG_PTCE3_LEN 0xF0 3033 3034 MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN); 3035 3036 /* reg_ptce3_v 3037 * Valid. 3038 * Access: RW 3039 */ 3040 MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1); 3041 3042 enum mlxsw_reg_ptce3_op { 3043 /* Write operation. Used to write a new entry to the table. 3044 * All R/W fields are relevant for new entry. Activity bit is set 3045 * for new entries. Write with v = 0 will delete the entry. Must 3046 * not be used if an entry exists. 3047 */ 3048 MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0, 3049 /* Update operation */ 3050 MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1, 3051 /* Read operation */ 3052 MLXSW_REG_PTCE3_OP_QUERY_READ = 0, 3053 }; 3054 3055 /* reg_ptce3_op 3056 * Access: OP 3057 */ 3058 MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3); 3059 3060 /* reg_ptce3_priority 3061 * Priority of the rule. Higher values win. 3062 * For Spectrum-2 range is 1..cap_kvd_size - 1 3063 * Note: Priority does not have to be unique per rule. 3064 * Access: RW 3065 */ 3066 MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24); 3067 3068 /* reg_ptce3_tcam_region_info 3069 * Opaque object that represents the TCAM region. 3070 * Access: Index 3071 */ 3072 MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10, 3073 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 3074 3075 /* reg_ptce3_flex2_key_blocks 3076 * ACL key. The key must be masked according to eRP (if exists) or 3077 * according to master mask. 3078 * Access: Index 3079 */ 3080 MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20, 3081 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 3082 3083 /* reg_ptce3_erp_id 3084 * eRP ID. 3085 * Access: Index 3086 */ 3087 MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4); 3088 3089 /* reg_ptce3_delta_start 3090 * Start point of delta_value and delta_mask, in bits. Must not exceed 3091 * num_key_blocks * 36 - 8. Reserved when delta_mask = 0. 3092 * Access: Index 3093 */ 3094 MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10); 3095 3096 /* reg_ptce3_delta_mask 3097 * Delta mask. 3098 * 0 - Ignore relevant bit in delta_value 3099 * 1 - Compare relevant bit in delta_value 3100 * Delta mask must not be set for reserved fields in the key blocks. 3101 * Note: No delta when no eRPs. Thus, for regions with 3102 * PERERP.erpt_pointer_valid = 0 the delta mask must be 0. 3103 * Access: Index 3104 */ 3105 MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8); 3106 3107 /* reg_ptce3_delta_value 3108 * Delta value. 3109 * Bits which are masked by delta_mask must be 0. 3110 * Access: Index 3111 */ 3112 MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8); 3113 3114 /* reg_ptce3_prune_vector 3115 * Pruning vector relative to the PERPT.erp_id. 3116 * Used for reducing lookups. 3117 * 0 - NEED: Do a lookup using the eRP. 3118 * 1 - PRUNE: Do not perform a lookup using the eRP. 3119 * Maybe be modified by PEAPBL and PEAPBM. 3120 * Note: In Spectrum-2, a region of 8 key blocks must be set to either 3121 * all 1's or all 0's. 3122 * Access: RW 3123 */ 3124 MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1); 3125 3126 /* reg_ptce3_prune_ctcam 3127 * Pruning on C-TCAM. Used for reducing lookups. 3128 * 0 - NEED: Do a lookup in the C-TCAM. 3129 * 1 - PRUNE: Do not perform a lookup in the C-TCAM. 3130 * Access: RW 3131 */ 3132 MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1); 3133 3134 /* reg_ptce3_large_exists 3135 * Large entry key ID exists. 3136 * Within the region: 3137 * 0 - SINGLE: The large_entry_key_id is not currently in use. 3138 * For rule insert: The MSB of the key (blocks 6..11) will be added. 3139 * For rule delete: The MSB of the key will be removed. 3140 * 1 - NON_SINGLE: The large_entry_key_id is currently in use. 3141 * For rule insert: The MSB of the key (blocks 6..11) will not be added. 3142 * For rule delete: The MSB of the key will not be removed. 3143 * Access: WO 3144 */ 3145 MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1); 3146 3147 /* reg_ptce3_large_entry_key_id 3148 * Large entry key ID. 3149 * A key for 12 key blocks rules. Reserved when region has less than 12 key 3150 * blocks. Must be different for different keys which have the same common 3151 * 6 key blocks (MSB, blocks 6..11) key within a region. 3152 * Range is 0..cap_max_pe_large_key_id - 1 3153 * Access: RW 3154 */ 3155 MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24); 3156 3157 /* reg_ptce3_action_pointer 3158 * Pointer to action. 3159 * Range is 0..cap_max_kvd_action_sets - 1 3160 * Access: RW 3161 */ 3162 MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24); 3163 3164 static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid, 3165 enum mlxsw_reg_ptce3_op op, 3166 u32 priority, 3167 const char *tcam_region_info, 3168 const char *key, u8 erp_id, 3169 u16 delta_start, u8 delta_mask, 3170 u8 delta_value, bool large_exists, 3171 u32 lkey_id, u32 action_pointer) 3172 { 3173 MLXSW_REG_ZERO(ptce3, payload); 3174 mlxsw_reg_ptce3_v_set(payload, valid); 3175 mlxsw_reg_ptce3_op_set(payload, op); 3176 mlxsw_reg_ptce3_priority_set(payload, priority); 3177 mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info); 3178 mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key); 3179 mlxsw_reg_ptce3_erp_id_set(payload, erp_id); 3180 mlxsw_reg_ptce3_delta_start_set(payload, delta_start); 3181 mlxsw_reg_ptce3_delta_mask_set(payload, delta_mask); 3182 mlxsw_reg_ptce3_delta_value_set(payload, delta_value); 3183 mlxsw_reg_ptce3_large_exists_set(payload, large_exists); 3184 mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id); 3185 mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer); 3186 } 3187 3188 /* PERCR - Policy-Engine Region Configuration Register 3189 * --------------------------------------------------- 3190 * This register configures the region parameters. The region_id must be 3191 * allocated. 3192 */ 3193 #define MLXSW_REG_PERCR_ID 0x302A 3194 #define MLXSW_REG_PERCR_LEN 0x80 3195 3196 MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN); 3197 3198 /* reg_percr_region_id 3199 * Region identifier. 3200 * Range 0..cap_max_regions-1 3201 * Access: Index 3202 */ 3203 MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16); 3204 3205 /* reg_percr_atcam_ignore_prune 3206 * Ignore prune_vector by other A-TCAM rules. Used e.g., for a new rule. 3207 * Access: RW 3208 */ 3209 MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1); 3210 3211 /* reg_percr_ctcam_ignore_prune 3212 * Ignore prune_ctcam by other A-TCAM rules. Used e.g., for a new rule. 3213 * Access: RW 3214 */ 3215 MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1); 3216 3217 /* reg_percr_bf_bypass 3218 * Bloom filter bypass. 3219 * 0 - Bloom filter is used (default) 3220 * 1 - Bloom filter is bypassed. The bypass is an OR condition of 3221 * region_id or eRP. See PERPT.bf_bypass 3222 * Access: RW 3223 */ 3224 MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1); 3225 3226 /* reg_percr_master_mask 3227 * Master mask. Logical OR mask of all masks of all rules of a region 3228 * (both A-TCAM and C-TCAM). When there are no eRPs 3229 * (erpt_pointer_valid = 0), then this provides the mask. 3230 * Access: RW 3231 */ 3232 MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96); 3233 3234 static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id) 3235 { 3236 MLXSW_REG_ZERO(percr, payload); 3237 mlxsw_reg_percr_region_id_set(payload, region_id); 3238 mlxsw_reg_percr_atcam_ignore_prune_set(payload, false); 3239 mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false); 3240 mlxsw_reg_percr_bf_bypass_set(payload, false); 3241 } 3242 3243 /* PERERP - Policy-Engine Region eRP Register 3244 * ------------------------------------------ 3245 * This register configures the region eRP. The region_id must be 3246 * allocated. 3247 */ 3248 #define MLXSW_REG_PERERP_ID 0x302B 3249 #define MLXSW_REG_PERERP_LEN 0x1C 3250 3251 MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN); 3252 3253 /* reg_pererp_region_id 3254 * Region identifier. 3255 * Range 0..cap_max_regions-1 3256 * Access: Index 3257 */ 3258 MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16); 3259 3260 /* reg_pererp_ctcam_le 3261 * C-TCAM lookup enable. Reserved when erpt_pointer_valid = 0. 3262 * Access: RW 3263 */ 3264 MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1); 3265 3266 /* reg_pererp_erpt_pointer_valid 3267 * erpt_pointer is valid. 3268 * Access: RW 3269 */ 3270 MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1); 3271 3272 /* reg_pererp_erpt_bank_pointer 3273 * Pointer to eRP table bank. May be modified at any time. 3274 * Range 0..cap_max_erp_table_banks-1 3275 * Reserved when erpt_pointer_valid = 0 3276 */ 3277 MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4); 3278 3279 /* reg_pererp_erpt_pointer 3280 * Pointer to eRP table within the eRP bank. Can be changed for an 3281 * existing region. 3282 * Range 0..cap_max_erp_table_size-1 3283 * Reserved when erpt_pointer_valid = 0 3284 * Access: RW 3285 */ 3286 MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8); 3287 3288 /* reg_pererp_erpt_vector 3289 * Vector of allowed eRP indexes starting from erpt_pointer within the 3290 * erpt_bank_pointer. Next entries will be in next bank. 3291 * Note that eRP index is used and not eRP ID. 3292 * Reserved when erpt_pointer_valid = 0 3293 * Access: RW 3294 */ 3295 MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1); 3296 3297 /* reg_pererp_master_rp_id 3298 * Master RP ID. When there are no eRPs, then this provides the eRP ID 3299 * for the lookup. Can be changed for an existing region. 3300 * Reserved when erpt_pointer_valid = 1 3301 * Access: RW 3302 */ 3303 MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4); 3304 3305 static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload, 3306 unsigned long *erp_vector, 3307 unsigned long size) 3308 { 3309 unsigned long bit; 3310 3311 for_each_set_bit(bit, erp_vector, size) 3312 mlxsw_reg_pererp_erpt_vector_set(payload, bit, true); 3313 } 3314 3315 static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id, 3316 bool ctcam_le, bool erpt_pointer_valid, 3317 u8 erpt_bank_pointer, u8 erpt_pointer, 3318 u8 master_rp_id) 3319 { 3320 MLXSW_REG_ZERO(pererp, payload); 3321 mlxsw_reg_pererp_region_id_set(payload, region_id); 3322 mlxsw_reg_pererp_ctcam_le_set(payload, ctcam_le); 3323 mlxsw_reg_pererp_erpt_pointer_valid_set(payload, erpt_pointer_valid); 3324 mlxsw_reg_pererp_erpt_bank_pointer_set(payload, erpt_bank_pointer); 3325 mlxsw_reg_pererp_erpt_pointer_set(payload, erpt_pointer); 3326 mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id); 3327 } 3328 3329 /* PEABFE - Policy-Engine Algorithmic Bloom Filter Entries Register 3330 * ---------------------------------------------------------------- 3331 * This register configures the Bloom filter entries. 3332 */ 3333 #define MLXSW_REG_PEABFE_ID 0x3022 3334 #define MLXSW_REG_PEABFE_BASE_LEN 0x10 3335 #define MLXSW_REG_PEABFE_BF_REC_LEN 0x4 3336 #define MLXSW_REG_PEABFE_BF_REC_MAX_COUNT 256 3337 #define MLXSW_REG_PEABFE_LEN (MLXSW_REG_PEABFE_BASE_LEN + \ 3338 MLXSW_REG_PEABFE_BF_REC_LEN * \ 3339 MLXSW_REG_PEABFE_BF_REC_MAX_COUNT) 3340 3341 MLXSW_REG_DEFINE(peabfe, MLXSW_REG_PEABFE_ID, MLXSW_REG_PEABFE_LEN); 3342 3343 /* reg_peabfe_size 3344 * Number of BF entries to be updated. 3345 * Range 1..256 3346 * Access: Op 3347 */ 3348 MLXSW_ITEM32(reg, peabfe, size, 0x00, 0, 9); 3349 3350 /* reg_peabfe_bf_entry_state 3351 * Bloom filter state 3352 * 0 - Clear 3353 * 1 - Set 3354 * Access: RW 3355 */ 3356 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_state, 3357 MLXSW_REG_PEABFE_BASE_LEN, 31, 1, 3358 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3359 3360 /* reg_peabfe_bf_entry_bank 3361 * Bloom filter bank ID 3362 * Range 0..cap_max_erp_table_banks-1 3363 * Access: Index 3364 */ 3365 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_bank, 3366 MLXSW_REG_PEABFE_BASE_LEN, 24, 4, 3367 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3368 3369 /* reg_peabfe_bf_entry_index 3370 * Bloom filter entry index 3371 * Range 0..2^cap_max_bf_log-1 3372 * Access: Index 3373 */ 3374 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_index, 3375 MLXSW_REG_PEABFE_BASE_LEN, 0, 24, 3376 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3377 3378 static inline void mlxsw_reg_peabfe_pack(char *payload) 3379 { 3380 MLXSW_REG_ZERO(peabfe, payload); 3381 } 3382 3383 static inline void mlxsw_reg_peabfe_rec_pack(char *payload, int rec_index, 3384 u8 state, u8 bank, u32 bf_index) 3385 { 3386 u8 num_rec = mlxsw_reg_peabfe_size_get(payload); 3387 3388 if (rec_index >= num_rec) 3389 mlxsw_reg_peabfe_size_set(payload, rec_index + 1); 3390 mlxsw_reg_peabfe_bf_entry_state_set(payload, rec_index, state); 3391 mlxsw_reg_peabfe_bf_entry_bank_set(payload, rec_index, bank); 3392 mlxsw_reg_peabfe_bf_entry_index_set(payload, rec_index, bf_index); 3393 } 3394 3395 /* IEDR - Infrastructure Entry Delete Register 3396 * ---------------------------------------------------- 3397 * This register is used for deleting entries from the entry tables. 3398 * It is legitimate to attempt to delete a nonexisting entry (the device will 3399 * respond as a good flow). 3400 */ 3401 #define MLXSW_REG_IEDR_ID 0x3804 3402 #define MLXSW_REG_IEDR_BASE_LEN 0x10 /* base length, without records */ 3403 #define MLXSW_REG_IEDR_REC_LEN 0x8 /* record length */ 3404 #define MLXSW_REG_IEDR_REC_MAX_COUNT 64 3405 #define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN + \ 3406 MLXSW_REG_IEDR_REC_LEN * \ 3407 MLXSW_REG_IEDR_REC_MAX_COUNT) 3408 3409 MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN); 3410 3411 /* reg_iedr_num_rec 3412 * Number of records. 3413 * Access: OP 3414 */ 3415 MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8); 3416 3417 /* reg_iedr_rec_type 3418 * Resource type. 3419 * Access: OP 3420 */ 3421 MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8, 3422 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3423 3424 /* reg_iedr_rec_size 3425 * Size of entries do be deleted. The unit is 1 entry, regardless of entry type. 3426 * Access: OP 3427 */ 3428 MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 13, 3429 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3430 3431 /* reg_iedr_rec_index_start 3432 * Resource index start. 3433 * Access: OP 3434 */ 3435 MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24, 3436 MLXSW_REG_IEDR_REC_LEN, 0x04, false); 3437 3438 static inline void mlxsw_reg_iedr_pack(char *payload) 3439 { 3440 MLXSW_REG_ZERO(iedr, payload); 3441 } 3442 3443 static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index, 3444 u8 rec_type, u16 rec_size, 3445 u32 rec_index_start) 3446 { 3447 u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload); 3448 3449 if (rec_index >= num_rec) 3450 mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1); 3451 mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type); 3452 mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size); 3453 mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start); 3454 } 3455 3456 /* QPTS - QoS Priority Trust State Register 3457 * ---------------------------------------- 3458 * This register controls the port policy to calculate the switch priority and 3459 * packet color based on incoming packet fields. 3460 */ 3461 #define MLXSW_REG_QPTS_ID 0x4002 3462 #define MLXSW_REG_QPTS_LEN 0x8 3463 3464 MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN); 3465 3466 /* reg_qpts_local_port 3467 * Local port number. 3468 * Access: Index 3469 * 3470 * Note: CPU port is supported. 3471 */ 3472 MLXSW_ITEM32(reg, qpts, local_port, 0x00, 16, 8); 3473 3474 enum mlxsw_reg_qpts_trust_state { 3475 MLXSW_REG_QPTS_TRUST_STATE_PCP = 1, 3476 MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2, /* For MPLS, trust EXP. */ 3477 }; 3478 3479 /* reg_qpts_trust_state 3480 * Trust state for a given port. 3481 * Access: RW 3482 */ 3483 MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3); 3484 3485 static inline void mlxsw_reg_qpts_pack(char *payload, u8 local_port, 3486 enum mlxsw_reg_qpts_trust_state ts) 3487 { 3488 MLXSW_REG_ZERO(qpts, payload); 3489 3490 mlxsw_reg_qpts_local_port_set(payload, local_port); 3491 mlxsw_reg_qpts_trust_state_set(payload, ts); 3492 } 3493 3494 /* QPCR - QoS Policer Configuration Register 3495 * ----------------------------------------- 3496 * The QPCR register is used to create policers - that limit 3497 * the rate of bytes or packets via some trap group. 3498 */ 3499 #define MLXSW_REG_QPCR_ID 0x4004 3500 #define MLXSW_REG_QPCR_LEN 0x28 3501 3502 MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN); 3503 3504 enum mlxsw_reg_qpcr_g { 3505 MLXSW_REG_QPCR_G_GLOBAL = 2, 3506 MLXSW_REG_QPCR_G_STORM_CONTROL = 3, 3507 }; 3508 3509 /* reg_qpcr_g 3510 * The policer type. 3511 * Access: Index 3512 */ 3513 MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2); 3514 3515 /* reg_qpcr_pid 3516 * Policer ID. 3517 * Access: Index 3518 */ 3519 MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14); 3520 3521 /* reg_qpcr_clear_counter 3522 * Clear counters. 3523 * Access: OP 3524 */ 3525 MLXSW_ITEM32(reg, qpcr, clear_counter, 0x04, 31, 1); 3526 3527 /* reg_qpcr_color_aware 3528 * Is the policer aware of colors. 3529 * Must be 0 (unaware) for cpu port. 3530 * Access: RW for unbounded policer. RO for bounded policer. 3531 */ 3532 MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1); 3533 3534 /* reg_qpcr_bytes 3535 * Is policer limit is for bytes per sec or packets per sec. 3536 * 0 - packets 3537 * 1 - bytes 3538 * Access: RW for unbounded policer. RO for bounded policer. 3539 */ 3540 MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1); 3541 3542 enum mlxsw_reg_qpcr_ir_units { 3543 MLXSW_REG_QPCR_IR_UNITS_M, 3544 MLXSW_REG_QPCR_IR_UNITS_K, 3545 }; 3546 3547 /* reg_qpcr_ir_units 3548 * Policer's units for cir and eir fields (for bytes limits only) 3549 * 1 - 10^3 3550 * 0 - 10^6 3551 * Access: OP 3552 */ 3553 MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1); 3554 3555 enum mlxsw_reg_qpcr_rate_type { 3556 MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1, 3557 MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2, 3558 }; 3559 3560 /* reg_qpcr_rate_type 3561 * Policer can have one limit (single rate) or 2 limits with specific operation 3562 * for packets that exceed the lower rate but not the upper one. 3563 * (For cpu port must be single rate) 3564 * Access: RW for unbounded policer. RO for bounded policer. 3565 */ 3566 MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2); 3567 3568 /* reg_qpc_cbs 3569 * Policer's committed burst size. 3570 * The policer is working with time slices of 50 nano sec. By default every 3571 * slice is granted the proportionate share of the committed rate. If we want to 3572 * allow a slice to exceed that share (while still keeping the rate per sec) we 3573 * can allow burst. The burst size is between the default proportionate share 3574 * (and no lower than 8) to 32Gb. (Even though giving a number higher than the 3575 * committed rate will result in exceeding the rate). The burst size must be a 3576 * log of 2 and will be determined by 2^cbs. 3577 * Access: RW 3578 */ 3579 MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6); 3580 3581 /* reg_qpcr_cir 3582 * Policer's committed rate. 3583 * The rate used for sungle rate, the lower rate for double rate. 3584 * For bytes limits, the rate will be this value * the unit from ir_units. 3585 * (Resolution error is up to 1%). 3586 * Access: RW 3587 */ 3588 MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32); 3589 3590 /* reg_qpcr_eir 3591 * Policer's exceed rate. 3592 * The higher rate for double rate, reserved for single rate. 3593 * Lower rate for double rate policer. 3594 * For bytes limits, the rate will be this value * the unit from ir_units. 3595 * (Resolution error is up to 1%). 3596 * Access: RW 3597 */ 3598 MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32); 3599 3600 #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2 3601 3602 /* reg_qpcr_exceed_action. 3603 * What to do with packets between the 2 limits for double rate. 3604 * Access: RW for unbounded policer. RO for bounded policer. 3605 */ 3606 MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4); 3607 3608 enum mlxsw_reg_qpcr_action { 3609 /* Discard */ 3610 MLXSW_REG_QPCR_ACTION_DISCARD = 1, 3611 /* Forward and set color to red. 3612 * If the packet is intended to cpu port, it will be dropped. 3613 */ 3614 MLXSW_REG_QPCR_ACTION_FORWARD = 2, 3615 }; 3616 3617 /* reg_qpcr_violate_action 3618 * What to do with packets that cross the cir limit (for single rate) or the eir 3619 * limit (for double rate). 3620 * Access: RW for unbounded policer. RO for bounded policer. 3621 */ 3622 MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4); 3623 3624 /* reg_qpcr_violate_count 3625 * Counts the number of times violate_action happened on this PID. 3626 * Access: RW 3627 */ 3628 MLXSW_ITEM64(reg, qpcr, violate_count, 0x20, 0, 64); 3629 3630 /* Packets */ 3631 #define MLXSW_REG_QPCR_LOWEST_CIR 1 3632 #define MLXSW_REG_QPCR_HIGHEST_CIR (2 * 1000 * 1000 * 1000) /* 2Gpps */ 3633 #define MLXSW_REG_QPCR_LOWEST_CBS 4 3634 #define MLXSW_REG_QPCR_HIGHEST_CBS 24 3635 3636 /* Bandwidth */ 3637 #define MLXSW_REG_QPCR_LOWEST_CIR_BITS 1024 /* bps */ 3638 #define MLXSW_REG_QPCR_HIGHEST_CIR_BITS 2000000000000ULL /* 2Tbps */ 3639 #define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP1 4 3640 #define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP2 4 3641 #define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP1 25 3642 #define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP2 31 3643 3644 static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid, 3645 enum mlxsw_reg_qpcr_ir_units ir_units, 3646 bool bytes, u32 cir, u16 cbs) 3647 { 3648 MLXSW_REG_ZERO(qpcr, payload); 3649 mlxsw_reg_qpcr_pid_set(payload, pid); 3650 mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL); 3651 mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE); 3652 mlxsw_reg_qpcr_violate_action_set(payload, 3653 MLXSW_REG_QPCR_ACTION_DISCARD); 3654 mlxsw_reg_qpcr_cir_set(payload, cir); 3655 mlxsw_reg_qpcr_ir_units_set(payload, ir_units); 3656 mlxsw_reg_qpcr_bytes_set(payload, bytes); 3657 mlxsw_reg_qpcr_cbs_set(payload, cbs); 3658 } 3659 3660 /* QTCT - QoS Switch Traffic Class Table 3661 * ------------------------------------- 3662 * Configures the mapping between the packet switch priority and the 3663 * traffic class on the transmit port. 3664 */ 3665 #define MLXSW_REG_QTCT_ID 0x400A 3666 #define MLXSW_REG_QTCT_LEN 0x08 3667 3668 MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN); 3669 3670 /* reg_qtct_local_port 3671 * Local port number. 3672 * Access: Index 3673 * 3674 * Note: CPU port is not supported. 3675 */ 3676 MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8); 3677 3678 /* reg_qtct_sub_port 3679 * Virtual port within the physical port. 3680 * Should be set to 0 when virtual ports are not enabled on the port. 3681 * Access: Index 3682 */ 3683 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8); 3684 3685 /* reg_qtct_switch_prio 3686 * Switch priority. 3687 * Access: Index 3688 */ 3689 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4); 3690 3691 /* reg_qtct_tclass 3692 * Traffic class. 3693 * Default values: 3694 * switch_prio 0 : tclass 1 3695 * switch_prio 1 : tclass 0 3696 * switch_prio i : tclass i, for i > 1 3697 * Access: RW 3698 */ 3699 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4); 3700 3701 static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port, 3702 u8 switch_prio, u8 tclass) 3703 { 3704 MLXSW_REG_ZERO(qtct, payload); 3705 mlxsw_reg_qtct_local_port_set(payload, local_port); 3706 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio); 3707 mlxsw_reg_qtct_tclass_set(payload, tclass); 3708 } 3709 3710 /* QEEC - QoS ETS Element Configuration Register 3711 * --------------------------------------------- 3712 * Configures the ETS elements. 3713 */ 3714 #define MLXSW_REG_QEEC_ID 0x400D 3715 #define MLXSW_REG_QEEC_LEN 0x20 3716 3717 MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN); 3718 3719 /* reg_qeec_local_port 3720 * Local port number. 3721 * Access: Index 3722 * 3723 * Note: CPU port is supported. 3724 */ 3725 MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8); 3726 3727 enum mlxsw_reg_qeec_hr { 3728 MLXSW_REG_QEEC_HR_PORT, 3729 MLXSW_REG_QEEC_HR_GROUP, 3730 MLXSW_REG_QEEC_HR_SUBGROUP, 3731 MLXSW_REG_QEEC_HR_TC, 3732 }; 3733 3734 /* reg_qeec_element_hierarchy 3735 * 0 - Port 3736 * 1 - Group 3737 * 2 - Subgroup 3738 * 3 - Traffic Class 3739 * Access: Index 3740 */ 3741 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4); 3742 3743 /* reg_qeec_element_index 3744 * The index of the element in the hierarchy. 3745 * Access: Index 3746 */ 3747 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8); 3748 3749 /* reg_qeec_next_element_index 3750 * The index of the next (lower) element in the hierarchy. 3751 * Access: RW 3752 * 3753 * Note: Reserved for element_hierarchy 0. 3754 */ 3755 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8); 3756 3757 /* reg_qeec_mise 3758 * Min shaper configuration enable. Enables configuration of the min 3759 * shaper on this ETS element 3760 * 0 - Disable 3761 * 1 - Enable 3762 * Access: RW 3763 */ 3764 MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1); 3765 3766 /* reg_qeec_ptps 3767 * PTP shaper 3768 * 0: regular shaper mode 3769 * 1: PTP oriented shaper 3770 * Allowed only for hierarchy 0 3771 * Not supported for CPU port 3772 * Note that ptps mode may affect the shaper rates of all hierarchies 3773 * Supported only on Spectrum-1 3774 * Access: RW 3775 */ 3776 MLXSW_ITEM32(reg, qeec, ptps, 0x0C, 29, 1); 3777 3778 enum { 3779 MLXSW_REG_QEEC_BYTES_MODE, 3780 MLXSW_REG_QEEC_PACKETS_MODE, 3781 }; 3782 3783 /* reg_qeec_pb 3784 * Packets or bytes mode. 3785 * 0 - Bytes mode 3786 * 1 - Packets mode 3787 * Access: RW 3788 * 3789 * Note: Used for max shaper configuration. For Spectrum, packets mode 3790 * is supported only for traffic classes of CPU port. 3791 */ 3792 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1); 3793 3794 /* The smallest permitted min shaper rate. */ 3795 #define MLXSW_REG_QEEC_MIS_MIN 200000 /* Kbps */ 3796 3797 /* reg_qeec_min_shaper_rate 3798 * Min shaper information rate. 3799 * For CPU port, can only be configured for port hierarchy. 3800 * When in bytes mode, value is specified in units of 1000bps. 3801 * Access: RW 3802 */ 3803 MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28); 3804 3805 /* reg_qeec_mase 3806 * Max shaper configuration enable. Enables configuration of the max 3807 * shaper on this ETS element. 3808 * 0 - Disable 3809 * 1 - Enable 3810 * Access: RW 3811 */ 3812 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1); 3813 3814 /* The largest max shaper value possible to disable the shaper. */ 3815 #define MLXSW_REG_QEEC_MAS_DIS ((1u << 31) - 1) /* Kbps */ 3816 3817 /* reg_qeec_max_shaper_rate 3818 * Max shaper information rate. 3819 * For CPU port, can only be configured for port hierarchy. 3820 * When in bytes mode, value is specified in units of 1000bps. 3821 * Access: RW 3822 */ 3823 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 31); 3824 3825 /* reg_qeec_de 3826 * DWRR configuration enable. Enables configuration of the dwrr and 3827 * dwrr_weight. 3828 * 0 - Disable 3829 * 1 - Enable 3830 * Access: RW 3831 */ 3832 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1); 3833 3834 /* reg_qeec_dwrr 3835 * Transmission selection algorithm to use on the link going down from 3836 * the ETS element. 3837 * 0 - Strict priority 3838 * 1 - DWRR 3839 * Access: RW 3840 */ 3841 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1); 3842 3843 /* reg_qeec_dwrr_weight 3844 * DWRR weight on the link going down from the ETS element. The 3845 * percentage of bandwidth guaranteed to an ETS element within 3846 * its hierarchy. The sum of all weights across all ETS elements 3847 * within one hierarchy should be equal to 100. Reserved when 3848 * transmission selection algorithm is strict priority. 3849 * Access: RW 3850 */ 3851 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8); 3852 3853 /* reg_qeec_max_shaper_bs 3854 * Max shaper burst size 3855 * Burst size is 2^max_shaper_bs * 512 bits 3856 * For Spectrum-1: Range is: 5..25 3857 * For Spectrum-2: Range is: 11..25 3858 * Reserved when ptps = 1 3859 * Access: RW 3860 */ 3861 MLXSW_ITEM32(reg, qeec, max_shaper_bs, 0x1C, 0, 6); 3862 3863 #define MLXSW_REG_QEEC_HIGHEST_SHAPER_BS 25 3864 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1 5 3865 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2 11 3866 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3 5 3867 3868 static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port, 3869 enum mlxsw_reg_qeec_hr hr, u8 index, 3870 u8 next_index) 3871 { 3872 MLXSW_REG_ZERO(qeec, payload); 3873 mlxsw_reg_qeec_local_port_set(payload, local_port); 3874 mlxsw_reg_qeec_element_hierarchy_set(payload, hr); 3875 mlxsw_reg_qeec_element_index_set(payload, index); 3876 mlxsw_reg_qeec_next_element_index_set(payload, next_index); 3877 } 3878 3879 static inline void mlxsw_reg_qeec_ptps_pack(char *payload, u8 local_port, 3880 bool ptps) 3881 { 3882 MLXSW_REG_ZERO(qeec, payload); 3883 mlxsw_reg_qeec_local_port_set(payload, local_port); 3884 mlxsw_reg_qeec_element_hierarchy_set(payload, MLXSW_REG_QEEC_HR_PORT); 3885 mlxsw_reg_qeec_ptps_set(payload, ptps); 3886 } 3887 3888 /* QRWE - QoS ReWrite Enable 3889 * ------------------------- 3890 * This register configures the rewrite enable per receive port. 3891 */ 3892 #define MLXSW_REG_QRWE_ID 0x400F 3893 #define MLXSW_REG_QRWE_LEN 0x08 3894 3895 MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN); 3896 3897 /* reg_qrwe_local_port 3898 * Local port number. 3899 * Access: Index 3900 * 3901 * Note: CPU port is supported. No support for router port. 3902 */ 3903 MLXSW_ITEM32(reg, qrwe, local_port, 0x00, 16, 8); 3904 3905 /* reg_qrwe_dscp 3906 * Whether to enable DSCP rewrite (default is 0, don't rewrite). 3907 * Access: RW 3908 */ 3909 MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1); 3910 3911 /* reg_qrwe_pcp 3912 * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite). 3913 * Access: RW 3914 */ 3915 MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1); 3916 3917 static inline void mlxsw_reg_qrwe_pack(char *payload, u8 local_port, 3918 bool rewrite_pcp, bool rewrite_dscp) 3919 { 3920 MLXSW_REG_ZERO(qrwe, payload); 3921 mlxsw_reg_qrwe_local_port_set(payload, local_port); 3922 mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp); 3923 mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp); 3924 } 3925 3926 /* QPDSM - QoS Priority to DSCP Mapping 3927 * ------------------------------------ 3928 * QoS Priority to DSCP Mapping Register 3929 */ 3930 #define MLXSW_REG_QPDSM_ID 0x4011 3931 #define MLXSW_REG_QPDSM_BASE_LEN 0x04 /* base length, without records */ 3932 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4 /* record length */ 3933 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 16 3934 #define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN + \ 3935 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN * \ 3936 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT) 3937 3938 MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN); 3939 3940 /* reg_qpdsm_local_port 3941 * Local Port. Supported for data packets from CPU port. 3942 * Access: Index 3943 */ 3944 MLXSW_ITEM32(reg, qpdsm, local_port, 0x00, 16, 8); 3945 3946 /* reg_qpdsm_prio_entry_color0_e 3947 * Enable update of the entry for color 0 and a given port. 3948 * Access: WO 3949 */ 3950 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e, 3951 MLXSW_REG_QPDSM_BASE_LEN, 31, 1, 3952 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3953 3954 /* reg_qpdsm_prio_entry_color0_dscp 3955 * DSCP field in the outer label of the packet for color 0 and a given port. 3956 * Reserved when e=0. 3957 * Access: RW 3958 */ 3959 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp, 3960 MLXSW_REG_QPDSM_BASE_LEN, 24, 6, 3961 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3962 3963 /* reg_qpdsm_prio_entry_color1_e 3964 * Enable update of the entry for color 1 and a given port. 3965 * Access: WO 3966 */ 3967 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e, 3968 MLXSW_REG_QPDSM_BASE_LEN, 23, 1, 3969 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3970 3971 /* reg_qpdsm_prio_entry_color1_dscp 3972 * DSCP field in the outer label of the packet for color 1 and a given port. 3973 * Reserved when e=0. 3974 * Access: RW 3975 */ 3976 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp, 3977 MLXSW_REG_QPDSM_BASE_LEN, 16, 6, 3978 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3979 3980 /* reg_qpdsm_prio_entry_color2_e 3981 * Enable update of the entry for color 2 and a given port. 3982 * Access: WO 3983 */ 3984 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e, 3985 MLXSW_REG_QPDSM_BASE_LEN, 15, 1, 3986 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3987 3988 /* reg_qpdsm_prio_entry_color2_dscp 3989 * DSCP field in the outer label of the packet for color 2 and a given port. 3990 * Reserved when e=0. 3991 * Access: RW 3992 */ 3993 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp, 3994 MLXSW_REG_QPDSM_BASE_LEN, 8, 6, 3995 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3996 3997 static inline void mlxsw_reg_qpdsm_pack(char *payload, u8 local_port) 3998 { 3999 MLXSW_REG_ZERO(qpdsm, payload); 4000 mlxsw_reg_qpdsm_local_port_set(payload, local_port); 4001 } 4002 4003 static inline void 4004 mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp) 4005 { 4006 mlxsw_reg_qpdsm_prio_entry_color0_e_set(payload, prio, 1); 4007 mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(payload, prio, dscp); 4008 mlxsw_reg_qpdsm_prio_entry_color1_e_set(payload, prio, 1); 4009 mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(payload, prio, dscp); 4010 mlxsw_reg_qpdsm_prio_entry_color2_e_set(payload, prio, 1); 4011 mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp); 4012 } 4013 4014 /* QPDP - QoS Port DSCP to Priority Mapping Register 4015 * ------------------------------------------------- 4016 * This register controls the port default Switch Priority and Color. The 4017 * default Switch Priority and Color are used for frames where the trust state 4018 * uses default values. All member ports of a LAG should be configured with the 4019 * same default values. 4020 */ 4021 #define MLXSW_REG_QPDP_ID 0x4007 4022 #define MLXSW_REG_QPDP_LEN 0x8 4023 4024 MLXSW_REG_DEFINE(qpdp, MLXSW_REG_QPDP_ID, MLXSW_REG_QPDP_LEN); 4025 4026 /* reg_qpdp_local_port 4027 * Local Port. Supported for data packets from CPU port. 4028 * Access: Index 4029 */ 4030 MLXSW_ITEM32(reg, qpdp, local_port, 0x00, 16, 8); 4031 4032 /* reg_qpdp_switch_prio 4033 * Default port Switch Priority (default 0) 4034 * Access: RW 4035 */ 4036 MLXSW_ITEM32(reg, qpdp, switch_prio, 0x04, 0, 4); 4037 4038 static inline void mlxsw_reg_qpdp_pack(char *payload, u8 local_port, 4039 u8 switch_prio) 4040 { 4041 MLXSW_REG_ZERO(qpdp, payload); 4042 mlxsw_reg_qpdp_local_port_set(payload, local_port); 4043 mlxsw_reg_qpdp_switch_prio_set(payload, switch_prio); 4044 } 4045 4046 /* QPDPM - QoS Port DSCP to Priority Mapping Register 4047 * -------------------------------------------------- 4048 * This register controls the mapping from DSCP field to 4049 * Switch Priority for IP packets. 4050 */ 4051 #define MLXSW_REG_QPDPM_ID 0x4013 4052 #define MLXSW_REG_QPDPM_BASE_LEN 0x4 /* base length, without records */ 4053 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2 /* record length */ 4054 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64 4055 #define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN + \ 4056 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN * \ 4057 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT) 4058 4059 MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN); 4060 4061 /* reg_qpdpm_local_port 4062 * Local Port. Supported for data packets from CPU port. 4063 * Access: Index 4064 */ 4065 MLXSW_ITEM32(reg, qpdpm, local_port, 0x00, 16, 8); 4066 4067 /* reg_qpdpm_dscp_e 4068 * Enable update of the specific entry. When cleared, the switch_prio and color 4069 * fields are ignored and the previous switch_prio and color values are 4070 * preserved. 4071 * Access: WO 4072 */ 4073 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1, 4074 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 4075 4076 /* reg_qpdpm_dscp_prio 4077 * The new Switch Priority value for the relevant DSCP value. 4078 * Access: RW 4079 */ 4080 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio, 4081 MLXSW_REG_QPDPM_BASE_LEN, 0, 4, 4082 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 4083 4084 static inline void mlxsw_reg_qpdpm_pack(char *payload, u8 local_port) 4085 { 4086 MLXSW_REG_ZERO(qpdpm, payload); 4087 mlxsw_reg_qpdpm_local_port_set(payload, local_port); 4088 } 4089 4090 static inline void 4091 mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio) 4092 { 4093 mlxsw_reg_qpdpm_dscp_entry_e_set(payload, dscp, 1); 4094 mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio); 4095 } 4096 4097 /* QTCTM - QoS Switch Traffic Class Table is Multicast-Aware Register 4098 * ------------------------------------------------------------------ 4099 * This register configures if the Switch Priority to Traffic Class mapping is 4100 * based on Multicast packet indication. If so, then multicast packets will get 4101 * a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by 4102 * QTCT. 4103 * By default, Switch Priority to Traffic Class mapping is not based on 4104 * Multicast packet indication. 4105 */ 4106 #define MLXSW_REG_QTCTM_ID 0x401A 4107 #define MLXSW_REG_QTCTM_LEN 0x08 4108 4109 MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN); 4110 4111 /* reg_qtctm_local_port 4112 * Local port number. 4113 * No support for CPU port. 4114 * Access: Index 4115 */ 4116 MLXSW_ITEM32(reg, qtctm, local_port, 0x00, 16, 8); 4117 4118 /* reg_qtctm_mc 4119 * Multicast Mode 4120 * Whether Switch Priority to Traffic Class mapping is based on Multicast packet 4121 * indication (default is 0, not based on Multicast packet indication). 4122 */ 4123 MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1); 4124 4125 static inline void 4126 mlxsw_reg_qtctm_pack(char *payload, u8 local_port, bool mc) 4127 { 4128 MLXSW_REG_ZERO(qtctm, payload); 4129 mlxsw_reg_qtctm_local_port_set(payload, local_port); 4130 mlxsw_reg_qtctm_mc_set(payload, mc); 4131 } 4132 4133 /* QPSC - QoS PTP Shaper Configuration Register 4134 * -------------------------------------------- 4135 * The QPSC allows advanced configuration of the shapers when QEEC.ptps=1. 4136 * Supported only on Spectrum-1. 4137 */ 4138 #define MLXSW_REG_QPSC_ID 0x401B 4139 #define MLXSW_REG_QPSC_LEN 0x28 4140 4141 MLXSW_REG_DEFINE(qpsc, MLXSW_REG_QPSC_ID, MLXSW_REG_QPSC_LEN); 4142 4143 enum mlxsw_reg_qpsc_port_speed { 4144 MLXSW_REG_QPSC_PORT_SPEED_100M, 4145 MLXSW_REG_QPSC_PORT_SPEED_1G, 4146 MLXSW_REG_QPSC_PORT_SPEED_10G, 4147 MLXSW_REG_QPSC_PORT_SPEED_25G, 4148 }; 4149 4150 /* reg_qpsc_port_speed 4151 * Port speed. 4152 * Access: Index 4153 */ 4154 MLXSW_ITEM32(reg, qpsc, port_speed, 0x00, 0, 4); 4155 4156 /* reg_qpsc_shaper_time_exp 4157 * The base-time-interval for updating the shapers tokens (for all hierarchies). 4158 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec 4159 * shaper_rate = 64bit * shaper_inc / shaper_update_rate 4160 * Access: RW 4161 */ 4162 MLXSW_ITEM32(reg, qpsc, shaper_time_exp, 0x04, 16, 4); 4163 4164 /* reg_qpsc_shaper_time_mantissa 4165 * The base-time-interval for updating the shapers tokens (for all hierarchies). 4166 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec 4167 * shaper_rate = 64bit * shaper_inc / shaper_update_rate 4168 * Access: RW 4169 */ 4170 MLXSW_ITEM32(reg, qpsc, shaper_time_mantissa, 0x04, 0, 5); 4171 4172 /* reg_qpsc_shaper_inc 4173 * Number of tokens added to shaper on each update. 4174 * Units of 8B. 4175 * Access: RW 4176 */ 4177 MLXSW_ITEM32(reg, qpsc, shaper_inc, 0x08, 0, 5); 4178 4179 /* reg_qpsc_shaper_bs 4180 * Max shaper Burst size. 4181 * Burst size is 2 ^ max_shaper_bs * 512 [bits] 4182 * Range is: 5..25 (from 2KB..2GB) 4183 * Access: RW 4184 */ 4185 MLXSW_ITEM32(reg, qpsc, shaper_bs, 0x0C, 0, 6); 4186 4187 /* reg_qpsc_ptsc_we 4188 * Write enable to port_to_shaper_credits. 4189 * Access: WO 4190 */ 4191 MLXSW_ITEM32(reg, qpsc, ptsc_we, 0x10, 31, 1); 4192 4193 /* reg_qpsc_port_to_shaper_credits 4194 * For split ports: range 1..57 4195 * For non-split ports: range 1..112 4196 * Written only when ptsc_we is set. 4197 * Access: RW 4198 */ 4199 MLXSW_ITEM32(reg, qpsc, port_to_shaper_credits, 0x10, 0, 8); 4200 4201 /* reg_qpsc_ing_timestamp_inc 4202 * Ingress timestamp increment. 4203 * 2's complement. 4204 * The timestamp of MTPPTR at ingress will be incremented by this value. Global 4205 * value for all ports. 4206 * Same units as used by MTPPTR. 4207 * Access: RW 4208 */ 4209 MLXSW_ITEM32(reg, qpsc, ing_timestamp_inc, 0x20, 0, 32); 4210 4211 /* reg_qpsc_egr_timestamp_inc 4212 * Egress timestamp increment. 4213 * 2's complement. 4214 * The timestamp of MTPPTR at egress will be incremented by this value. Global 4215 * value for all ports. 4216 * Same units as used by MTPPTR. 4217 * Access: RW 4218 */ 4219 MLXSW_ITEM32(reg, qpsc, egr_timestamp_inc, 0x24, 0, 32); 4220 4221 static inline void 4222 mlxsw_reg_qpsc_pack(char *payload, enum mlxsw_reg_qpsc_port_speed port_speed, 4223 u8 shaper_time_exp, u8 shaper_time_mantissa, u8 shaper_inc, 4224 u8 shaper_bs, u8 port_to_shaper_credits, 4225 int ing_timestamp_inc, int egr_timestamp_inc) 4226 { 4227 MLXSW_REG_ZERO(qpsc, payload); 4228 mlxsw_reg_qpsc_port_speed_set(payload, port_speed); 4229 mlxsw_reg_qpsc_shaper_time_exp_set(payload, shaper_time_exp); 4230 mlxsw_reg_qpsc_shaper_time_mantissa_set(payload, shaper_time_mantissa); 4231 mlxsw_reg_qpsc_shaper_inc_set(payload, shaper_inc); 4232 mlxsw_reg_qpsc_shaper_bs_set(payload, shaper_bs); 4233 mlxsw_reg_qpsc_ptsc_we_set(payload, true); 4234 mlxsw_reg_qpsc_port_to_shaper_credits_set(payload, port_to_shaper_credits); 4235 mlxsw_reg_qpsc_ing_timestamp_inc_set(payload, ing_timestamp_inc); 4236 mlxsw_reg_qpsc_egr_timestamp_inc_set(payload, egr_timestamp_inc); 4237 } 4238 4239 /* PMLP - Ports Module to Local Port Register 4240 * ------------------------------------------ 4241 * Configures the assignment of modules to local ports. 4242 */ 4243 #define MLXSW_REG_PMLP_ID 0x5002 4244 #define MLXSW_REG_PMLP_LEN 0x40 4245 4246 MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN); 4247 4248 /* reg_pmlp_rxtx 4249 * 0 - Tx value is used for both Tx and Rx. 4250 * 1 - Rx value is taken from a separte field. 4251 * Access: RW 4252 */ 4253 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1); 4254 4255 /* reg_pmlp_local_port 4256 * Local port number. 4257 * Access: Index 4258 */ 4259 MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8); 4260 4261 /* reg_pmlp_width 4262 * 0 - Unmap local port. 4263 * 1 - Lane 0 is used. 4264 * 2 - Lanes 0 and 1 are used. 4265 * 4 - Lanes 0, 1, 2 and 3 are used. 4266 * 8 - Lanes 0-7 are used. 4267 * Access: RW 4268 */ 4269 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8); 4270 4271 /* reg_pmlp_module 4272 * Module number. 4273 * Access: RW 4274 */ 4275 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false); 4276 4277 /* reg_pmlp_tx_lane 4278 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well. 4279 * Access: RW 4280 */ 4281 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 4, 0x04, 0x00, false); 4282 4283 /* reg_pmlp_rx_lane 4284 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is 4285 * equal to Tx lane. 4286 * Access: RW 4287 */ 4288 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 4, 0x04, 0x00, false); 4289 4290 static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port) 4291 { 4292 MLXSW_REG_ZERO(pmlp, payload); 4293 mlxsw_reg_pmlp_local_port_set(payload, local_port); 4294 } 4295 4296 /* PMTU - Port MTU Register 4297 * ------------------------ 4298 * Configures and reports the port MTU. 4299 */ 4300 #define MLXSW_REG_PMTU_ID 0x5003 4301 #define MLXSW_REG_PMTU_LEN 0x10 4302 4303 MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN); 4304 4305 /* reg_pmtu_local_port 4306 * Local port number. 4307 * Access: Index 4308 */ 4309 MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8); 4310 4311 /* reg_pmtu_max_mtu 4312 * Maximum MTU. 4313 * When port type (e.g. Ethernet) is configured, the relevant MTU is 4314 * reported, otherwise the minimum between the max_mtu of the different 4315 * types is reported. 4316 * Access: RO 4317 */ 4318 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16); 4319 4320 /* reg_pmtu_admin_mtu 4321 * MTU value to set port to. Must be smaller or equal to max_mtu. 4322 * Note: If port type is Infiniband, then port must be disabled, when its 4323 * MTU is set. 4324 * Access: RW 4325 */ 4326 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16); 4327 4328 /* reg_pmtu_oper_mtu 4329 * The actual MTU configured on the port. Packets exceeding this size 4330 * will be dropped. 4331 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband 4332 * oper_mtu might be smaller than admin_mtu. 4333 * Access: RO 4334 */ 4335 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16); 4336 4337 static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port, 4338 u16 new_mtu) 4339 { 4340 MLXSW_REG_ZERO(pmtu, payload); 4341 mlxsw_reg_pmtu_local_port_set(payload, local_port); 4342 mlxsw_reg_pmtu_max_mtu_set(payload, 0); 4343 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu); 4344 mlxsw_reg_pmtu_oper_mtu_set(payload, 0); 4345 } 4346 4347 /* PTYS - Port Type and Speed Register 4348 * ----------------------------------- 4349 * Configures and reports the port speed type. 4350 * 4351 * Note: When set while the link is up, the changes will not take effect 4352 * until the port transitions from down to up state. 4353 */ 4354 #define MLXSW_REG_PTYS_ID 0x5004 4355 #define MLXSW_REG_PTYS_LEN 0x40 4356 4357 MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN); 4358 4359 /* an_disable_admin 4360 * Auto negotiation disable administrative configuration 4361 * 0 - Device doesn't support AN disable. 4362 * 1 - Device supports AN disable. 4363 * Access: RW 4364 */ 4365 MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1); 4366 4367 /* reg_ptys_local_port 4368 * Local port number. 4369 * Access: Index 4370 */ 4371 MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8); 4372 4373 #define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0) 4374 #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2) 4375 4376 /* reg_ptys_proto_mask 4377 * Protocol mask. Indicates which protocol is used. 4378 * 0 - Infiniband. 4379 * 1 - Fibre Channel. 4380 * 2 - Ethernet. 4381 * Access: Index 4382 */ 4383 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3); 4384 4385 enum { 4386 MLXSW_REG_PTYS_AN_STATUS_NA, 4387 MLXSW_REG_PTYS_AN_STATUS_OK, 4388 MLXSW_REG_PTYS_AN_STATUS_FAIL, 4389 }; 4390 4391 /* reg_ptys_an_status 4392 * Autonegotiation status. 4393 * Access: RO 4394 */ 4395 MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4); 4396 4397 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M BIT(0) 4398 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII BIT(1) 4399 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R BIT(3) 4400 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G BIT(4) 4401 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G BIT(5) 4402 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR BIT(6) 4403 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 BIT(7) 4404 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR BIT(8) 4405 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4 BIT(9) 4406 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2 BIT(10) 4407 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4 BIT(12) 4408 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_8 BIT(15) 4409 4410 /* reg_ptys_ext_eth_proto_cap 4411 * Extended Ethernet port supported speeds and protocols. 4412 * Access: RO 4413 */ 4414 MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32); 4415 4416 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0) 4417 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1) 4418 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2) 4419 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3) 4420 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4) 4421 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6) 4422 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7) 4423 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12) 4424 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13) 4425 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14) 4426 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15) 4427 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16) 4428 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18) 4429 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19) 4430 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20) 4431 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21) 4432 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22) 4433 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27) 4434 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28) 4435 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29) 4436 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30) 4437 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31) 4438 4439 /* reg_ptys_eth_proto_cap 4440 * Ethernet port supported speeds and protocols. 4441 * Access: RO 4442 */ 4443 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32); 4444 4445 /* reg_ptys_ib_link_width_cap 4446 * IB port supported widths. 4447 * Access: RO 4448 */ 4449 MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16); 4450 4451 #define MLXSW_REG_PTYS_IB_SPEED_SDR BIT(0) 4452 #define MLXSW_REG_PTYS_IB_SPEED_DDR BIT(1) 4453 #define MLXSW_REG_PTYS_IB_SPEED_QDR BIT(2) 4454 #define MLXSW_REG_PTYS_IB_SPEED_FDR10 BIT(3) 4455 #define MLXSW_REG_PTYS_IB_SPEED_FDR BIT(4) 4456 #define MLXSW_REG_PTYS_IB_SPEED_EDR BIT(5) 4457 4458 /* reg_ptys_ib_proto_cap 4459 * IB port supported speeds and protocols. 4460 * Access: RO 4461 */ 4462 MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16); 4463 4464 /* reg_ptys_ext_eth_proto_admin 4465 * Extended speed and protocol to set port to. 4466 * Access: RW 4467 */ 4468 MLXSW_ITEM32(reg, ptys, ext_eth_proto_admin, 0x14, 0, 32); 4469 4470 /* reg_ptys_eth_proto_admin 4471 * Speed and protocol to set port to. 4472 * Access: RW 4473 */ 4474 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32); 4475 4476 /* reg_ptys_ib_link_width_admin 4477 * IB width to set port to. 4478 * Access: RW 4479 */ 4480 MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16); 4481 4482 /* reg_ptys_ib_proto_admin 4483 * IB speeds and protocols to set port to. 4484 * Access: RW 4485 */ 4486 MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16); 4487 4488 /* reg_ptys_ext_eth_proto_oper 4489 * The extended current speed and protocol configured for the port. 4490 * Access: RO 4491 */ 4492 MLXSW_ITEM32(reg, ptys, ext_eth_proto_oper, 0x20, 0, 32); 4493 4494 /* reg_ptys_eth_proto_oper 4495 * The current speed and protocol configured for the port. 4496 * Access: RO 4497 */ 4498 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32); 4499 4500 /* reg_ptys_ib_link_width_oper 4501 * The current IB width to set port to. 4502 * Access: RO 4503 */ 4504 MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16); 4505 4506 /* reg_ptys_ib_proto_oper 4507 * The current IB speed and protocol. 4508 * Access: RO 4509 */ 4510 MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16); 4511 4512 enum mlxsw_reg_ptys_connector_type { 4513 MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR, 4514 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE, 4515 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP, 4516 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI, 4517 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC, 4518 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII, 4519 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE, 4520 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA, 4521 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER, 4522 }; 4523 4524 /* reg_ptys_connector_type 4525 * Connector type indication. 4526 * Access: RO 4527 */ 4528 MLXSW_ITEM32(reg, ptys, connector_type, 0x2C, 0, 4); 4529 4530 static inline void mlxsw_reg_ptys_eth_pack(char *payload, u8 local_port, 4531 u32 proto_admin, bool autoneg) 4532 { 4533 MLXSW_REG_ZERO(ptys, payload); 4534 mlxsw_reg_ptys_local_port_set(payload, local_port); 4535 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4536 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin); 4537 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4538 } 4539 4540 static inline void mlxsw_reg_ptys_ext_eth_pack(char *payload, u8 local_port, 4541 u32 proto_admin, bool autoneg) 4542 { 4543 MLXSW_REG_ZERO(ptys, payload); 4544 mlxsw_reg_ptys_local_port_set(payload, local_port); 4545 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4546 mlxsw_reg_ptys_ext_eth_proto_admin_set(payload, proto_admin); 4547 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4548 } 4549 4550 static inline void mlxsw_reg_ptys_eth_unpack(char *payload, 4551 u32 *p_eth_proto_cap, 4552 u32 *p_eth_proto_admin, 4553 u32 *p_eth_proto_oper) 4554 { 4555 if (p_eth_proto_cap) 4556 *p_eth_proto_cap = 4557 mlxsw_reg_ptys_eth_proto_cap_get(payload); 4558 if (p_eth_proto_admin) 4559 *p_eth_proto_admin = 4560 mlxsw_reg_ptys_eth_proto_admin_get(payload); 4561 if (p_eth_proto_oper) 4562 *p_eth_proto_oper = 4563 mlxsw_reg_ptys_eth_proto_oper_get(payload); 4564 } 4565 4566 static inline void mlxsw_reg_ptys_ext_eth_unpack(char *payload, 4567 u32 *p_eth_proto_cap, 4568 u32 *p_eth_proto_admin, 4569 u32 *p_eth_proto_oper) 4570 { 4571 if (p_eth_proto_cap) 4572 *p_eth_proto_cap = 4573 mlxsw_reg_ptys_ext_eth_proto_cap_get(payload); 4574 if (p_eth_proto_admin) 4575 *p_eth_proto_admin = 4576 mlxsw_reg_ptys_ext_eth_proto_admin_get(payload); 4577 if (p_eth_proto_oper) 4578 *p_eth_proto_oper = 4579 mlxsw_reg_ptys_ext_eth_proto_oper_get(payload); 4580 } 4581 4582 static inline void mlxsw_reg_ptys_ib_pack(char *payload, u8 local_port, 4583 u16 proto_admin, u16 link_width) 4584 { 4585 MLXSW_REG_ZERO(ptys, payload); 4586 mlxsw_reg_ptys_local_port_set(payload, local_port); 4587 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB); 4588 mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin); 4589 mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width); 4590 } 4591 4592 static inline void mlxsw_reg_ptys_ib_unpack(char *payload, u16 *p_ib_proto_cap, 4593 u16 *p_ib_link_width_cap, 4594 u16 *p_ib_proto_oper, 4595 u16 *p_ib_link_width_oper) 4596 { 4597 if (p_ib_proto_cap) 4598 *p_ib_proto_cap = mlxsw_reg_ptys_ib_proto_cap_get(payload); 4599 if (p_ib_link_width_cap) 4600 *p_ib_link_width_cap = 4601 mlxsw_reg_ptys_ib_link_width_cap_get(payload); 4602 if (p_ib_proto_oper) 4603 *p_ib_proto_oper = mlxsw_reg_ptys_ib_proto_oper_get(payload); 4604 if (p_ib_link_width_oper) 4605 *p_ib_link_width_oper = 4606 mlxsw_reg_ptys_ib_link_width_oper_get(payload); 4607 } 4608 4609 /* PPAD - Port Physical Address Register 4610 * ------------------------------------- 4611 * The PPAD register configures the per port physical MAC address. 4612 */ 4613 #define MLXSW_REG_PPAD_ID 0x5005 4614 #define MLXSW_REG_PPAD_LEN 0x10 4615 4616 MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN); 4617 4618 /* reg_ppad_single_base_mac 4619 * 0: base_mac, local port should be 0 and mac[7:0] is 4620 * reserved. HW will set incremental 4621 * 1: single_mac - mac of the local_port 4622 * Access: RW 4623 */ 4624 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1); 4625 4626 /* reg_ppad_local_port 4627 * port number, if single_base_mac = 0 then local_port is reserved 4628 * Access: RW 4629 */ 4630 MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8); 4631 4632 /* reg_ppad_mac 4633 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved. 4634 * If single_base_mac = 1 - the per port MAC address 4635 * Access: RW 4636 */ 4637 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6); 4638 4639 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac, 4640 u8 local_port) 4641 { 4642 MLXSW_REG_ZERO(ppad, payload); 4643 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac); 4644 mlxsw_reg_ppad_local_port_set(payload, local_port); 4645 } 4646 4647 /* PAOS - Ports Administrative and Operational Status Register 4648 * ----------------------------------------------------------- 4649 * Configures and retrieves per port administrative and operational status. 4650 */ 4651 #define MLXSW_REG_PAOS_ID 0x5006 4652 #define MLXSW_REG_PAOS_LEN 0x10 4653 4654 MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN); 4655 4656 /* reg_paos_swid 4657 * Switch partition ID with which to associate the port. 4658 * Note: while external ports uses unique local port numbers (and thus swid is 4659 * redundant), router ports use the same local port number where swid is the 4660 * only indication for the relevant port. 4661 * Access: Index 4662 */ 4663 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8); 4664 4665 /* reg_paos_local_port 4666 * Local port number. 4667 * Access: Index 4668 */ 4669 MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8); 4670 4671 /* reg_paos_admin_status 4672 * Port administrative state (the desired state of the port): 4673 * 1 - Up. 4674 * 2 - Down. 4675 * 3 - Up once. This means that in case of link failure, the port won't go 4676 * into polling mode, but will wait to be re-enabled by software. 4677 * 4 - Disabled by system. Can only be set by hardware. 4678 * Access: RW 4679 */ 4680 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4); 4681 4682 /* reg_paos_oper_status 4683 * Port operational state (the current state): 4684 * 1 - Up. 4685 * 2 - Down. 4686 * 3 - Down by port failure. This means that the device will not let the 4687 * port up again until explicitly specified by software. 4688 * Access: RO 4689 */ 4690 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4); 4691 4692 /* reg_paos_ase 4693 * Admin state update enabled. 4694 * Access: WO 4695 */ 4696 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1); 4697 4698 /* reg_paos_ee 4699 * Event update enable. If this bit is set, event generation will be 4700 * updated based on the e field. 4701 * Access: WO 4702 */ 4703 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1); 4704 4705 /* reg_paos_e 4706 * Event generation on operational state change: 4707 * 0 - Do not generate event. 4708 * 1 - Generate Event. 4709 * 2 - Generate Single Event. 4710 * Access: RW 4711 */ 4712 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2); 4713 4714 static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port, 4715 enum mlxsw_port_admin_status status) 4716 { 4717 MLXSW_REG_ZERO(paos, payload); 4718 mlxsw_reg_paos_swid_set(payload, 0); 4719 mlxsw_reg_paos_local_port_set(payload, local_port); 4720 mlxsw_reg_paos_admin_status_set(payload, status); 4721 mlxsw_reg_paos_oper_status_set(payload, 0); 4722 mlxsw_reg_paos_ase_set(payload, 1); 4723 mlxsw_reg_paos_ee_set(payload, 1); 4724 mlxsw_reg_paos_e_set(payload, 1); 4725 } 4726 4727 /* PFCC - Ports Flow Control Configuration Register 4728 * ------------------------------------------------ 4729 * Configures and retrieves the per port flow control configuration. 4730 */ 4731 #define MLXSW_REG_PFCC_ID 0x5007 4732 #define MLXSW_REG_PFCC_LEN 0x20 4733 4734 MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN); 4735 4736 /* reg_pfcc_local_port 4737 * Local port number. 4738 * Access: Index 4739 */ 4740 MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8); 4741 4742 /* reg_pfcc_pnat 4743 * Port number access type. Determines the way local_port is interpreted: 4744 * 0 - Local port number. 4745 * 1 - IB / label port number. 4746 * Access: Index 4747 */ 4748 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2); 4749 4750 /* reg_pfcc_shl_cap 4751 * Send to higher layers capabilities: 4752 * 0 - No capability of sending Pause and PFC frames to higher layers. 4753 * 1 - Device has capability of sending Pause and PFC frames to higher 4754 * layers. 4755 * Access: RO 4756 */ 4757 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1); 4758 4759 /* reg_pfcc_shl_opr 4760 * Send to higher layers operation: 4761 * 0 - Pause and PFC frames are handled by the port (default). 4762 * 1 - Pause and PFC frames are handled by the port and also sent to 4763 * higher layers. Only valid if shl_cap = 1. 4764 * Access: RW 4765 */ 4766 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1); 4767 4768 /* reg_pfcc_ppan 4769 * Pause policy auto negotiation. 4770 * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx. 4771 * 1 - Enabled. When auto-negotiation is performed, set the Pause policy 4772 * based on the auto-negotiation resolution. 4773 * Access: RW 4774 * 4775 * Note: The auto-negotiation advertisement is set according to pptx and 4776 * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0. 4777 */ 4778 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4); 4779 4780 /* reg_pfcc_prio_mask_tx 4781 * Bit per priority indicating if Tx flow control policy should be 4782 * updated based on bit pfctx. 4783 * Access: WO 4784 */ 4785 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8); 4786 4787 /* reg_pfcc_prio_mask_rx 4788 * Bit per priority indicating if Rx flow control policy should be 4789 * updated based on bit pfcrx. 4790 * Access: WO 4791 */ 4792 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8); 4793 4794 /* reg_pfcc_pptx 4795 * Admin Pause policy on Tx. 4796 * 0 - Never generate Pause frames (default). 4797 * 1 - Generate Pause frames according to Rx buffer threshold. 4798 * Access: RW 4799 */ 4800 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1); 4801 4802 /* reg_pfcc_aptx 4803 * Active (operational) Pause policy on Tx. 4804 * 0 - Never generate Pause frames. 4805 * 1 - Generate Pause frames according to Rx buffer threshold. 4806 * Access: RO 4807 */ 4808 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1); 4809 4810 /* reg_pfcc_pfctx 4811 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask: 4812 * 0 - Never generate priority Pause frames on the specified priority 4813 * (default). 4814 * 1 - Generate priority Pause frames according to Rx buffer threshold on 4815 * the specified priority. 4816 * Access: RW 4817 * 4818 * Note: pfctx and pptx must be mutually exclusive. 4819 */ 4820 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8); 4821 4822 /* reg_pfcc_pprx 4823 * Admin Pause policy on Rx. 4824 * 0 - Ignore received Pause frames (default). 4825 * 1 - Respect received Pause frames. 4826 * Access: RW 4827 */ 4828 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1); 4829 4830 /* reg_pfcc_aprx 4831 * Active (operational) Pause policy on Rx. 4832 * 0 - Ignore received Pause frames. 4833 * 1 - Respect received Pause frames. 4834 * Access: RO 4835 */ 4836 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1); 4837 4838 /* reg_pfcc_pfcrx 4839 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask: 4840 * 0 - Ignore incoming priority Pause frames on the specified priority 4841 * (default). 4842 * 1 - Respect incoming priority Pause frames on the specified priority. 4843 * Access: RW 4844 */ 4845 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8); 4846 4847 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF 4848 4849 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en) 4850 { 4851 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 4852 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 4853 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en); 4854 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en); 4855 } 4856 4857 static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port) 4858 { 4859 MLXSW_REG_ZERO(pfcc, payload); 4860 mlxsw_reg_pfcc_local_port_set(payload, local_port); 4861 } 4862 4863 /* PPCNT - Ports Performance Counters Register 4864 * ------------------------------------------- 4865 * The PPCNT register retrieves per port performance counters. 4866 */ 4867 #define MLXSW_REG_PPCNT_ID 0x5008 4868 #define MLXSW_REG_PPCNT_LEN 0x100 4869 #define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08 4870 4871 MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN); 4872 4873 /* reg_ppcnt_swid 4874 * For HCA: must be always 0. 4875 * Switch partition ID to associate port with. 4876 * Switch partitions are numbered from 0 to 7 inclusively. 4877 * Switch partition 254 indicates stacking ports. 4878 * Switch partition 255 indicates all switch partitions. 4879 * Only valid on Set() operation with local_port=255. 4880 * Access: Index 4881 */ 4882 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8); 4883 4884 /* reg_ppcnt_local_port 4885 * Local port number. 4886 * 255 indicates all ports on the device, and is only allowed 4887 * for Set() operation. 4888 * Access: Index 4889 */ 4890 MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8); 4891 4892 /* reg_ppcnt_pnat 4893 * Port number access type: 4894 * 0 - Local port number 4895 * 1 - IB port number 4896 * Access: Index 4897 */ 4898 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2); 4899 4900 enum mlxsw_reg_ppcnt_grp { 4901 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0, 4902 MLXSW_REG_PPCNT_RFC_2863_CNT = 0x1, 4903 MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2, 4904 MLXSW_REG_PPCNT_RFC_3635_CNT = 0x3, 4905 MLXSW_REG_PPCNT_EXT_CNT = 0x5, 4906 MLXSW_REG_PPCNT_DISCARD_CNT = 0x6, 4907 MLXSW_REG_PPCNT_PRIO_CNT = 0x10, 4908 MLXSW_REG_PPCNT_TC_CNT = 0x11, 4909 MLXSW_REG_PPCNT_TC_CONG_TC = 0x13, 4910 }; 4911 4912 /* reg_ppcnt_grp 4913 * Performance counter group. 4914 * Group 63 indicates all groups. Only valid on Set() operation with 4915 * clr bit set. 4916 * 0x0: IEEE 802.3 Counters 4917 * 0x1: RFC 2863 Counters 4918 * 0x2: RFC 2819 Counters 4919 * 0x3: RFC 3635 Counters 4920 * 0x5: Ethernet Extended Counters 4921 * 0x6: Ethernet Discard Counters 4922 * 0x8: Link Level Retransmission Counters 4923 * 0x10: Per Priority Counters 4924 * 0x11: Per Traffic Class Counters 4925 * 0x12: Physical Layer Counters 4926 * 0x13: Per Traffic Class Congestion Counters 4927 * Access: Index 4928 */ 4929 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6); 4930 4931 /* reg_ppcnt_clr 4932 * Clear counters. Setting the clr bit will reset the counter value 4933 * for all counters in the counter group. This bit can be set 4934 * for both Set() and Get() operation. 4935 * Access: OP 4936 */ 4937 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1); 4938 4939 /* reg_ppcnt_prio_tc 4940 * Priority for counter set that support per priority, valid values: 0-7. 4941 * Traffic class for counter set that support per traffic class, 4942 * valid values: 0- cap_max_tclass-1 . 4943 * For HCA: cap_max_tclass is always 8. 4944 * Otherwise must be 0. 4945 * Access: Index 4946 */ 4947 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5); 4948 4949 /* Ethernet IEEE 802.3 Counter Group */ 4950 4951 /* reg_ppcnt_a_frames_transmitted_ok 4952 * Access: RO 4953 */ 4954 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok, 4955 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4956 4957 /* reg_ppcnt_a_frames_received_ok 4958 * Access: RO 4959 */ 4960 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok, 4961 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4962 4963 /* reg_ppcnt_a_frame_check_sequence_errors 4964 * Access: RO 4965 */ 4966 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors, 4967 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 4968 4969 /* reg_ppcnt_a_alignment_errors 4970 * Access: RO 4971 */ 4972 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors, 4973 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 4974 4975 /* reg_ppcnt_a_octets_transmitted_ok 4976 * Access: RO 4977 */ 4978 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok, 4979 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 4980 4981 /* reg_ppcnt_a_octets_received_ok 4982 * Access: RO 4983 */ 4984 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok, 4985 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 4986 4987 /* reg_ppcnt_a_multicast_frames_xmitted_ok 4988 * Access: RO 4989 */ 4990 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok, 4991 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 4992 4993 /* reg_ppcnt_a_broadcast_frames_xmitted_ok 4994 * Access: RO 4995 */ 4996 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok, 4997 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 4998 4999 /* reg_ppcnt_a_multicast_frames_received_ok 5000 * Access: RO 5001 */ 5002 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok, 5003 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5004 5005 /* reg_ppcnt_a_broadcast_frames_received_ok 5006 * Access: RO 5007 */ 5008 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok, 5009 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 5010 5011 /* reg_ppcnt_a_in_range_length_errors 5012 * Access: RO 5013 */ 5014 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors, 5015 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5016 5017 /* reg_ppcnt_a_out_of_range_length_field 5018 * Access: RO 5019 */ 5020 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field, 5021 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5022 5023 /* reg_ppcnt_a_frame_too_long_errors 5024 * Access: RO 5025 */ 5026 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors, 5027 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5028 5029 /* reg_ppcnt_a_symbol_error_during_carrier 5030 * Access: RO 5031 */ 5032 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier, 5033 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5034 5035 /* reg_ppcnt_a_mac_control_frames_transmitted 5036 * Access: RO 5037 */ 5038 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted, 5039 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5040 5041 /* reg_ppcnt_a_mac_control_frames_received 5042 * Access: RO 5043 */ 5044 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received, 5045 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 5046 5047 /* reg_ppcnt_a_unsupported_opcodes_received 5048 * Access: RO 5049 */ 5050 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received, 5051 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 5052 5053 /* reg_ppcnt_a_pause_mac_ctrl_frames_received 5054 * Access: RO 5055 */ 5056 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received, 5057 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 5058 5059 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted 5060 * Access: RO 5061 */ 5062 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted, 5063 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 5064 5065 /* Ethernet RFC 2863 Counter Group */ 5066 5067 /* reg_ppcnt_if_in_discards 5068 * Access: RO 5069 */ 5070 MLXSW_ITEM64(reg, ppcnt, if_in_discards, 5071 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 5072 5073 /* reg_ppcnt_if_out_discards 5074 * Access: RO 5075 */ 5076 MLXSW_ITEM64(reg, ppcnt, if_out_discards, 5077 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 5078 5079 /* reg_ppcnt_if_out_errors 5080 * Access: RO 5081 */ 5082 MLXSW_ITEM64(reg, ppcnt, if_out_errors, 5083 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5084 5085 /* Ethernet RFC 2819 Counter Group */ 5086 5087 /* reg_ppcnt_ether_stats_undersize_pkts 5088 * Access: RO 5089 */ 5090 MLXSW_ITEM64(reg, ppcnt, ether_stats_undersize_pkts, 5091 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 5092 5093 /* reg_ppcnt_ether_stats_oversize_pkts 5094 * Access: RO 5095 */ 5096 MLXSW_ITEM64(reg, ppcnt, ether_stats_oversize_pkts, 5097 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 5098 5099 /* reg_ppcnt_ether_stats_fragments 5100 * Access: RO 5101 */ 5102 MLXSW_ITEM64(reg, ppcnt, ether_stats_fragments, 5103 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5104 5105 /* reg_ppcnt_ether_stats_pkts64octets 5106 * Access: RO 5107 */ 5108 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets, 5109 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5110 5111 /* reg_ppcnt_ether_stats_pkts65to127octets 5112 * Access: RO 5113 */ 5114 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets, 5115 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5116 5117 /* reg_ppcnt_ether_stats_pkts128to255octets 5118 * Access: RO 5119 */ 5120 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets, 5121 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5122 5123 /* reg_ppcnt_ether_stats_pkts256to511octets 5124 * Access: RO 5125 */ 5126 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets, 5127 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5128 5129 /* reg_ppcnt_ether_stats_pkts512to1023octets 5130 * Access: RO 5131 */ 5132 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets, 5133 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 5134 5135 /* reg_ppcnt_ether_stats_pkts1024to1518octets 5136 * Access: RO 5137 */ 5138 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets, 5139 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 5140 5141 /* reg_ppcnt_ether_stats_pkts1519to2047octets 5142 * Access: RO 5143 */ 5144 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets, 5145 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 5146 5147 /* reg_ppcnt_ether_stats_pkts2048to4095octets 5148 * Access: RO 5149 */ 5150 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets, 5151 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 5152 5153 /* reg_ppcnt_ether_stats_pkts4096to8191octets 5154 * Access: RO 5155 */ 5156 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets, 5157 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64); 5158 5159 /* reg_ppcnt_ether_stats_pkts8192to10239octets 5160 * Access: RO 5161 */ 5162 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets, 5163 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64); 5164 5165 /* Ethernet RFC 3635 Counter Group */ 5166 5167 /* reg_ppcnt_dot3stats_fcs_errors 5168 * Access: RO 5169 */ 5170 MLXSW_ITEM64(reg, ppcnt, dot3stats_fcs_errors, 5171 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5172 5173 /* reg_ppcnt_dot3stats_symbol_errors 5174 * Access: RO 5175 */ 5176 MLXSW_ITEM64(reg, ppcnt, dot3stats_symbol_errors, 5177 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5178 5179 /* reg_ppcnt_dot3control_in_unknown_opcodes 5180 * Access: RO 5181 */ 5182 MLXSW_ITEM64(reg, ppcnt, dot3control_in_unknown_opcodes, 5183 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5184 5185 /* reg_ppcnt_dot3in_pause_frames 5186 * Access: RO 5187 */ 5188 MLXSW_ITEM64(reg, ppcnt, dot3in_pause_frames, 5189 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5190 5191 /* Ethernet Extended Counter Group Counters */ 5192 5193 /* reg_ppcnt_ecn_marked 5194 * Access: RO 5195 */ 5196 MLXSW_ITEM64(reg, ppcnt, ecn_marked, 5197 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5198 5199 /* Ethernet Discard Counter Group Counters */ 5200 5201 /* reg_ppcnt_ingress_general 5202 * Access: RO 5203 */ 5204 MLXSW_ITEM64(reg, ppcnt, ingress_general, 5205 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5206 5207 /* reg_ppcnt_ingress_policy_engine 5208 * Access: RO 5209 */ 5210 MLXSW_ITEM64(reg, ppcnt, ingress_policy_engine, 5211 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5212 5213 /* reg_ppcnt_ingress_vlan_membership 5214 * Access: RO 5215 */ 5216 MLXSW_ITEM64(reg, ppcnt, ingress_vlan_membership, 5217 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 5218 5219 /* reg_ppcnt_ingress_tag_frame_type 5220 * Access: RO 5221 */ 5222 MLXSW_ITEM64(reg, ppcnt, ingress_tag_frame_type, 5223 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 5224 5225 /* reg_ppcnt_egress_vlan_membership 5226 * Access: RO 5227 */ 5228 MLXSW_ITEM64(reg, ppcnt, egress_vlan_membership, 5229 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5230 5231 /* reg_ppcnt_loopback_filter 5232 * Access: RO 5233 */ 5234 MLXSW_ITEM64(reg, ppcnt, loopback_filter, 5235 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5236 5237 /* reg_ppcnt_egress_general 5238 * Access: RO 5239 */ 5240 MLXSW_ITEM64(reg, ppcnt, egress_general, 5241 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 5242 5243 /* reg_ppcnt_egress_hoq 5244 * Access: RO 5245 */ 5246 MLXSW_ITEM64(reg, ppcnt, egress_hoq, 5247 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5248 5249 /* reg_ppcnt_egress_policy_engine 5250 * Access: RO 5251 */ 5252 MLXSW_ITEM64(reg, ppcnt, egress_policy_engine, 5253 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5254 5255 /* reg_ppcnt_ingress_tx_link_down 5256 * Access: RO 5257 */ 5258 MLXSW_ITEM64(reg, ppcnt, ingress_tx_link_down, 5259 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5260 5261 /* reg_ppcnt_egress_stp_filter 5262 * Access: RO 5263 */ 5264 MLXSW_ITEM64(reg, ppcnt, egress_stp_filter, 5265 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5266 5267 /* reg_ppcnt_egress_sll 5268 * Access: RO 5269 */ 5270 MLXSW_ITEM64(reg, ppcnt, egress_sll, 5271 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5272 5273 /* Ethernet Per Priority Group Counters */ 5274 5275 /* reg_ppcnt_rx_octets 5276 * Access: RO 5277 */ 5278 MLXSW_ITEM64(reg, ppcnt, rx_octets, 5279 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5280 5281 /* reg_ppcnt_rx_frames 5282 * Access: RO 5283 */ 5284 MLXSW_ITEM64(reg, ppcnt, rx_frames, 5285 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5286 5287 /* reg_ppcnt_tx_octets 5288 * Access: RO 5289 */ 5290 MLXSW_ITEM64(reg, ppcnt, tx_octets, 5291 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5292 5293 /* reg_ppcnt_tx_frames 5294 * Access: RO 5295 */ 5296 MLXSW_ITEM64(reg, ppcnt, tx_frames, 5297 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 5298 5299 /* reg_ppcnt_rx_pause 5300 * Access: RO 5301 */ 5302 MLXSW_ITEM64(reg, ppcnt, rx_pause, 5303 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5304 5305 /* reg_ppcnt_rx_pause_duration 5306 * Access: RO 5307 */ 5308 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration, 5309 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5310 5311 /* reg_ppcnt_tx_pause 5312 * Access: RO 5313 */ 5314 MLXSW_ITEM64(reg, ppcnt, tx_pause, 5315 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5316 5317 /* reg_ppcnt_tx_pause_duration 5318 * Access: RO 5319 */ 5320 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration, 5321 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5322 5323 /* reg_ppcnt_rx_pause_transition 5324 * Access: RO 5325 */ 5326 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition, 5327 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5328 5329 /* Ethernet Per Traffic Group Counters */ 5330 5331 /* reg_ppcnt_tc_transmit_queue 5332 * Contains the transmit queue depth in cells of traffic class 5333 * selected by prio_tc and the port selected by local_port. 5334 * The field cannot be cleared. 5335 * Access: RO 5336 */ 5337 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue, 5338 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5339 5340 /* reg_ppcnt_tc_no_buffer_discard_uc 5341 * The number of unicast packets dropped due to lack of shared 5342 * buffer resources. 5343 * Access: RO 5344 */ 5345 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc, 5346 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5347 5348 /* Ethernet Per Traffic Class Congestion Group Counters */ 5349 5350 /* reg_ppcnt_wred_discard 5351 * Access: RO 5352 */ 5353 MLXSW_ITEM64(reg, ppcnt, wred_discard, 5354 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5355 5356 static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port, 5357 enum mlxsw_reg_ppcnt_grp grp, 5358 u8 prio_tc) 5359 { 5360 MLXSW_REG_ZERO(ppcnt, payload); 5361 mlxsw_reg_ppcnt_swid_set(payload, 0); 5362 mlxsw_reg_ppcnt_local_port_set(payload, local_port); 5363 mlxsw_reg_ppcnt_pnat_set(payload, 0); 5364 mlxsw_reg_ppcnt_grp_set(payload, grp); 5365 mlxsw_reg_ppcnt_clr_set(payload, 0); 5366 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc); 5367 } 5368 5369 /* PLIB - Port Local to InfiniBand Port 5370 * ------------------------------------ 5371 * The PLIB register performs mapping from Local Port into InfiniBand Port. 5372 */ 5373 #define MLXSW_REG_PLIB_ID 0x500A 5374 #define MLXSW_REG_PLIB_LEN 0x10 5375 5376 MLXSW_REG_DEFINE(plib, MLXSW_REG_PLIB_ID, MLXSW_REG_PLIB_LEN); 5377 5378 /* reg_plib_local_port 5379 * Local port number. 5380 * Access: Index 5381 */ 5382 MLXSW_ITEM32(reg, plib, local_port, 0x00, 16, 8); 5383 5384 /* reg_plib_ib_port 5385 * InfiniBand port remapping for local_port. 5386 * Access: RW 5387 */ 5388 MLXSW_ITEM32(reg, plib, ib_port, 0x00, 0, 8); 5389 5390 /* PPTB - Port Prio To Buffer Register 5391 * ----------------------------------- 5392 * Configures the switch priority to buffer table. 5393 */ 5394 #define MLXSW_REG_PPTB_ID 0x500B 5395 #define MLXSW_REG_PPTB_LEN 0x10 5396 5397 MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN); 5398 5399 enum { 5400 MLXSW_REG_PPTB_MM_UM, 5401 MLXSW_REG_PPTB_MM_UNICAST, 5402 MLXSW_REG_PPTB_MM_MULTICAST, 5403 }; 5404 5405 /* reg_pptb_mm 5406 * Mapping mode. 5407 * 0 - Map both unicast and multicast packets to the same buffer. 5408 * 1 - Map only unicast packets. 5409 * 2 - Map only multicast packets. 5410 * Access: Index 5411 * 5412 * Note: SwitchX-2 only supports the first option. 5413 */ 5414 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2); 5415 5416 /* reg_pptb_local_port 5417 * Local port number. 5418 * Access: Index 5419 */ 5420 MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8); 5421 5422 /* reg_pptb_um 5423 * Enables the update of the untagged_buf field. 5424 * Access: RW 5425 */ 5426 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1); 5427 5428 /* reg_pptb_pm 5429 * Enables the update of the prio_to_buff field. 5430 * Bit <i> is a flag for updating the mapping for switch priority <i>. 5431 * Access: RW 5432 */ 5433 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8); 5434 5435 /* reg_pptb_prio_to_buff 5436 * Mapping of switch priority <i> to one of the allocated receive port 5437 * buffers. 5438 * Access: RW 5439 */ 5440 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4); 5441 5442 /* reg_pptb_pm_msb 5443 * Enables the update of the prio_to_buff field. 5444 * Bit <i> is a flag for updating the mapping for switch priority <i+8>. 5445 * Access: RW 5446 */ 5447 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8); 5448 5449 /* reg_pptb_untagged_buff 5450 * Mapping of untagged frames to one of the allocated receive port buffers. 5451 * Access: RW 5452 * 5453 * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for 5454 * Spectrum, as it maps untagged packets based on the default switch priority. 5455 */ 5456 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4); 5457 5458 /* reg_pptb_prio_to_buff_msb 5459 * Mapping of switch priority <i+8> to one of the allocated receive port 5460 * buffers. 5461 * Access: RW 5462 */ 5463 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4); 5464 5465 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF 5466 5467 static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port) 5468 { 5469 MLXSW_REG_ZERO(pptb, payload); 5470 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM); 5471 mlxsw_reg_pptb_local_port_set(payload, local_port); 5472 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 5473 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 5474 } 5475 5476 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio, 5477 u8 buff) 5478 { 5479 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff); 5480 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff); 5481 } 5482 5483 /* PBMC - Port Buffer Management Control Register 5484 * ---------------------------------------------- 5485 * The PBMC register configures and retrieves the port packet buffer 5486 * allocation for different Prios, and the Pause threshold management. 5487 */ 5488 #define MLXSW_REG_PBMC_ID 0x500C 5489 #define MLXSW_REG_PBMC_LEN 0x6C 5490 5491 MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN); 5492 5493 /* reg_pbmc_local_port 5494 * Local port number. 5495 * Access: Index 5496 */ 5497 MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8); 5498 5499 /* reg_pbmc_xoff_timer_value 5500 * When device generates a pause frame, it uses this value as the pause 5501 * timer (time for the peer port to pause in quota-512 bit time). 5502 * Access: RW 5503 */ 5504 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16); 5505 5506 /* reg_pbmc_xoff_refresh 5507 * The time before a new pause frame should be sent to refresh the pause RW 5508 * state. Using the same units as xoff_timer_value above (in quota-512 bit 5509 * time). 5510 * Access: RW 5511 */ 5512 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16); 5513 5514 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11 5515 5516 /* reg_pbmc_buf_lossy 5517 * The field indicates if the buffer is lossy. 5518 * 0 - Lossless 5519 * 1 - Lossy 5520 * Access: RW 5521 */ 5522 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false); 5523 5524 /* reg_pbmc_buf_epsb 5525 * Eligible for Port Shared buffer. 5526 * If epsb is set, packets assigned to buffer are allowed to insert the port 5527 * shared buffer. 5528 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved. 5529 * Access: RW 5530 */ 5531 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false); 5532 5533 /* reg_pbmc_buf_size 5534 * The part of the packet buffer array is allocated for the specific buffer. 5535 * Units are represented in cells. 5536 * Access: RW 5537 */ 5538 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false); 5539 5540 /* reg_pbmc_buf_xoff_threshold 5541 * Once the amount of data in the buffer goes above this value, device 5542 * starts sending PFC frames for all priorities associated with the 5543 * buffer. Units are represented in cells. Reserved in case of lossy 5544 * buffer. 5545 * Access: RW 5546 * 5547 * Note: In Spectrum, reserved for buffer[9]. 5548 */ 5549 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16, 5550 0x08, 0x04, false); 5551 5552 /* reg_pbmc_buf_xon_threshold 5553 * When the amount of data in the buffer goes below this value, device 5554 * stops sending PFC frames for the priorities associated with the 5555 * buffer. Units are represented in cells. Reserved in case of lossy 5556 * buffer. 5557 * Access: RW 5558 * 5559 * Note: In Spectrum, reserved for buffer[9]. 5560 */ 5561 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16, 5562 0x08, 0x04, false); 5563 5564 static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port, 5565 u16 xoff_timer_value, u16 xoff_refresh) 5566 { 5567 MLXSW_REG_ZERO(pbmc, payload); 5568 mlxsw_reg_pbmc_local_port_set(payload, local_port); 5569 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value); 5570 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh); 5571 } 5572 5573 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload, 5574 int buf_index, 5575 u16 size) 5576 { 5577 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1); 5578 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5579 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5580 } 5581 5582 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload, 5583 int buf_index, u16 size, 5584 u16 threshold) 5585 { 5586 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0); 5587 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5588 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5589 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold); 5590 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold); 5591 } 5592 5593 /* PSPA - Port Switch Partition Allocation 5594 * --------------------------------------- 5595 * Controls the association of a port with a switch partition and enables 5596 * configuring ports as stacking ports. 5597 */ 5598 #define MLXSW_REG_PSPA_ID 0x500D 5599 #define MLXSW_REG_PSPA_LEN 0x8 5600 5601 MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN); 5602 5603 /* reg_pspa_swid 5604 * Switch partition ID. 5605 * Access: RW 5606 */ 5607 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8); 5608 5609 /* reg_pspa_local_port 5610 * Local port number. 5611 * Access: Index 5612 */ 5613 MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8); 5614 5615 /* reg_pspa_sub_port 5616 * Virtual port within the local port. Set to 0 when virtual ports are 5617 * disabled on the local port. 5618 * Access: Index 5619 */ 5620 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8); 5621 5622 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port) 5623 { 5624 MLXSW_REG_ZERO(pspa, payload); 5625 mlxsw_reg_pspa_swid_set(payload, swid); 5626 mlxsw_reg_pspa_local_port_set(payload, local_port); 5627 mlxsw_reg_pspa_sub_port_set(payload, 0); 5628 } 5629 5630 /* PMAOS - Ports Module Administrative and Operational Status 5631 * ---------------------------------------------------------- 5632 * This register configures and retrieves the per module status. 5633 */ 5634 #define MLXSW_REG_PMAOS_ID 0x5012 5635 #define MLXSW_REG_PMAOS_LEN 0x10 5636 5637 MLXSW_REG_DEFINE(pmaos, MLXSW_REG_PMAOS_ID, MLXSW_REG_PMAOS_LEN); 5638 5639 /* reg_slot_index 5640 * Slot index. 5641 * Access: Index 5642 */ 5643 MLXSW_ITEM32(reg, pmaos, slot_index, 0x00, 24, 4); 5644 5645 /* reg_pmaos_module 5646 * Module number. 5647 * Access: Index 5648 */ 5649 MLXSW_ITEM32(reg, pmaos, module, 0x00, 16, 8); 5650 5651 /* reg_pmaos_ase 5652 * Admin state update enable. 5653 * If this bit is set, admin state will be updated based on admin_state field. 5654 * Only relevant on Set() operations. 5655 * Access: WO 5656 */ 5657 MLXSW_ITEM32(reg, pmaos, ase, 0x04, 31, 1); 5658 5659 /* reg_pmaos_ee 5660 * Event update enable. 5661 * If this bit is set, event generation will be updated based on the e field. 5662 * Only relevant on Set operations. 5663 * Access: WO 5664 */ 5665 MLXSW_ITEM32(reg, pmaos, ee, 0x04, 30, 1); 5666 5667 enum mlxsw_reg_pmaos_e { 5668 MLXSW_REG_PMAOS_E_DO_NOT_GENERATE_EVENT, 5669 MLXSW_REG_PMAOS_E_GENERATE_EVENT, 5670 MLXSW_REG_PMAOS_E_GENERATE_SINGLE_EVENT, 5671 }; 5672 5673 /* reg_pmaos_e 5674 * Event Generation on operational state change. 5675 * Access: RW 5676 */ 5677 MLXSW_ITEM32(reg, pmaos, e, 0x04, 0, 2); 5678 5679 static inline void mlxsw_reg_pmaos_pack(char *payload, u8 module, 5680 enum mlxsw_reg_pmaos_e e) 5681 { 5682 MLXSW_REG_ZERO(pmaos, payload); 5683 mlxsw_reg_pmaos_module_set(payload, module); 5684 mlxsw_reg_pmaos_e_set(payload, e); 5685 mlxsw_reg_pmaos_ee_set(payload, true); 5686 } 5687 5688 /* PPLR - Port Physical Loopback Register 5689 * -------------------------------------- 5690 * This register allows configuration of the port's loopback mode. 5691 */ 5692 #define MLXSW_REG_PPLR_ID 0x5018 5693 #define MLXSW_REG_PPLR_LEN 0x8 5694 5695 MLXSW_REG_DEFINE(pplr, MLXSW_REG_PPLR_ID, MLXSW_REG_PPLR_LEN); 5696 5697 /* reg_pplr_local_port 5698 * Local port number. 5699 * Access: Index 5700 */ 5701 MLXSW_ITEM32(reg, pplr, local_port, 0x00, 16, 8); 5702 5703 /* Phy local loopback. When set the port's egress traffic is looped back 5704 * to the receiver and the port transmitter is disabled. 5705 */ 5706 #define MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL BIT(1) 5707 5708 /* reg_pplr_lb_en 5709 * Loopback enable. 5710 * Access: RW 5711 */ 5712 MLXSW_ITEM32(reg, pplr, lb_en, 0x04, 0, 8); 5713 5714 static inline void mlxsw_reg_pplr_pack(char *payload, u8 local_port, 5715 bool phy_local) 5716 { 5717 MLXSW_REG_ZERO(pplr, payload); 5718 mlxsw_reg_pplr_local_port_set(payload, local_port); 5719 mlxsw_reg_pplr_lb_en_set(payload, 5720 phy_local ? 5721 MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL : 0); 5722 } 5723 5724 /* PMPE - Port Module Plug/Unplug Event Register 5725 * --------------------------------------------- 5726 * This register reports any operational status change of a module. 5727 * A change in the module’s state will generate an event only if the change 5728 * happens after arming the event mechanism. Any changes to the module state 5729 * while the event mechanism is not armed will not be reported. Software can 5730 * query the PMPE register for module status. 5731 */ 5732 #define MLXSW_REG_PMPE_ID 0x5024 5733 #define MLXSW_REG_PMPE_LEN 0x10 5734 5735 MLXSW_REG_DEFINE(pmpe, MLXSW_REG_PMPE_ID, MLXSW_REG_PMPE_LEN); 5736 5737 /* reg_pmpe_slot_index 5738 * Slot index. 5739 * Access: Index 5740 */ 5741 MLXSW_ITEM32(reg, pmpe, slot_index, 0x00, 24, 4); 5742 5743 /* reg_pmpe_module 5744 * Module number. 5745 * Access: Index 5746 */ 5747 MLXSW_ITEM32(reg, pmpe, module, 0x00, 16, 8); 5748 5749 enum mlxsw_reg_pmpe_module_status { 5750 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_ENABLED = 1, 5751 MLXSW_REG_PMPE_MODULE_STATUS_UNPLUGGED, 5752 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_ERROR, 5753 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_DISABLED, 5754 }; 5755 5756 /* reg_pmpe_module_status 5757 * Module status. 5758 * Access: RO 5759 */ 5760 MLXSW_ITEM32(reg, pmpe, module_status, 0x00, 0, 4); 5761 5762 /* reg_pmpe_error_type 5763 * Module error details. 5764 * Access: RO 5765 */ 5766 MLXSW_ITEM32(reg, pmpe, error_type, 0x04, 8, 4); 5767 5768 /* PDDR - Port Diagnostics Database Register 5769 * ----------------------------------------- 5770 * The PDDR enables to read the Phy debug database 5771 */ 5772 #define MLXSW_REG_PDDR_ID 0x5031 5773 #define MLXSW_REG_PDDR_LEN 0x100 5774 5775 MLXSW_REG_DEFINE(pddr, MLXSW_REG_PDDR_ID, MLXSW_REG_PDDR_LEN); 5776 5777 /* reg_pddr_local_port 5778 * Local port number. 5779 * Access: Index 5780 */ 5781 MLXSW_ITEM32(reg, pddr, local_port, 0x00, 16, 8); 5782 5783 enum mlxsw_reg_pddr_page_select { 5784 MLXSW_REG_PDDR_PAGE_SELECT_TROUBLESHOOTING_INFO = 1, 5785 }; 5786 5787 /* reg_pddr_page_select 5788 * Page select index. 5789 * Access: Index 5790 */ 5791 MLXSW_ITEM32(reg, pddr, page_select, 0x04, 0, 8); 5792 5793 enum mlxsw_reg_pddr_trblsh_group_opcode { 5794 /* Monitor opcodes */ 5795 MLXSW_REG_PDDR_TRBLSH_GROUP_OPCODE_MONITOR, 5796 }; 5797 5798 /* reg_pddr_group_opcode 5799 * Group selector. 5800 * Access: Index 5801 */ 5802 MLXSW_ITEM32(reg, pddr, trblsh_group_opcode, 0x08, 0, 16); 5803 5804 /* reg_pddr_status_opcode 5805 * Group selector. 5806 * Access: RO 5807 */ 5808 MLXSW_ITEM32(reg, pddr, trblsh_status_opcode, 0x0C, 0, 16); 5809 5810 static inline void mlxsw_reg_pddr_pack(char *payload, u8 local_port, 5811 u8 page_select) 5812 { 5813 MLXSW_REG_ZERO(pddr, payload); 5814 mlxsw_reg_pddr_local_port_set(payload, local_port); 5815 mlxsw_reg_pddr_page_select_set(payload, page_select); 5816 } 5817 5818 /* PMTM - Port Module Type Mapping Register 5819 * ---------------------------------------- 5820 * The PMTM allows query or configuration of module types. 5821 */ 5822 #define MLXSW_REG_PMTM_ID 0x5067 5823 #define MLXSW_REG_PMTM_LEN 0x10 5824 5825 MLXSW_REG_DEFINE(pmtm, MLXSW_REG_PMTM_ID, MLXSW_REG_PMTM_LEN); 5826 5827 /* reg_pmtm_module 5828 * Module number. 5829 * Access: Index 5830 */ 5831 MLXSW_ITEM32(reg, pmtm, module, 0x00, 16, 8); 5832 5833 enum mlxsw_reg_pmtm_module_type { 5834 /* Backplane with 4 lanes */ 5835 MLXSW_REG_PMTM_MODULE_TYPE_BP_4X, 5836 /* QSFP */ 5837 MLXSW_REG_PMTM_MODULE_TYPE_QSFP, 5838 /* SFP */ 5839 MLXSW_REG_PMTM_MODULE_TYPE_SFP, 5840 /* Backplane with single lane */ 5841 MLXSW_REG_PMTM_MODULE_TYPE_BP_1X = 4, 5842 /* Backplane with two lane */ 5843 MLXSW_REG_PMTM_MODULE_TYPE_BP_2X = 8, 5844 /* Chip2Chip4x */ 5845 MLXSW_REG_PMTM_MODULE_TYPE_C2C4X = 10, 5846 /* Chip2Chip2x */ 5847 MLXSW_REG_PMTM_MODULE_TYPE_C2C2X, 5848 /* Chip2Chip1x */ 5849 MLXSW_REG_PMTM_MODULE_TYPE_C2C1X, 5850 /* QSFP-DD */ 5851 MLXSW_REG_PMTM_MODULE_TYPE_QSFP_DD = 14, 5852 /* OSFP */ 5853 MLXSW_REG_PMTM_MODULE_TYPE_OSFP, 5854 /* SFP-DD */ 5855 MLXSW_REG_PMTM_MODULE_TYPE_SFP_DD, 5856 /* DSFP */ 5857 MLXSW_REG_PMTM_MODULE_TYPE_DSFP, 5858 /* Chip2Chip8x */ 5859 MLXSW_REG_PMTM_MODULE_TYPE_C2C8X, 5860 }; 5861 5862 /* reg_pmtm_module_type 5863 * Module type. 5864 * Access: RW 5865 */ 5866 MLXSW_ITEM32(reg, pmtm, module_type, 0x04, 0, 4); 5867 5868 static inline void mlxsw_reg_pmtm_pack(char *payload, u8 module) 5869 { 5870 MLXSW_REG_ZERO(pmtm, payload); 5871 mlxsw_reg_pmtm_module_set(payload, module); 5872 } 5873 5874 static inline void 5875 mlxsw_reg_pmtm_unpack(char *payload, 5876 enum mlxsw_reg_pmtm_module_type *module_type) 5877 { 5878 *module_type = mlxsw_reg_pmtm_module_type_get(payload); 5879 } 5880 5881 /* HTGT - Host Trap Group Table 5882 * ---------------------------- 5883 * Configures the properties for forwarding to CPU. 5884 */ 5885 #define MLXSW_REG_HTGT_ID 0x7002 5886 #define MLXSW_REG_HTGT_LEN 0x20 5887 5888 MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN); 5889 5890 /* reg_htgt_swid 5891 * Switch partition ID. 5892 * Access: Index 5893 */ 5894 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8); 5895 5896 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */ 5897 5898 /* reg_htgt_type 5899 * CPU path type. 5900 * Access: RW 5901 */ 5902 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4); 5903 5904 enum mlxsw_reg_htgt_trap_group { 5905 MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 5906 MLXSW_REG_HTGT_TRAP_GROUP_MFDE, 5907 MLXSW_REG_HTGT_TRAP_GROUP_MTWE, 5908 MLXSW_REG_HTGT_TRAP_GROUP_PMPE, 5909 MLXSW_REG_HTGT_TRAP_GROUP_SP_STP, 5910 MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP, 5911 MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP, 5912 MLXSW_REG_HTGT_TRAP_GROUP_SP_MC_SNOOPING, 5913 MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP, 5914 MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF, 5915 MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM, 5916 MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST, 5917 MLXSW_REG_HTGT_TRAP_GROUP_SP_NEIGH_DISCOVERY, 5918 MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP, 5919 MLXSW_REG_HTGT_TRAP_GROUP_SP_EXTERNAL_ROUTE, 5920 MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME, 5921 MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP, 5922 MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT, 5923 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6, 5924 MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR, 5925 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0, 5926 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1, 5927 MLXSW_REG_HTGT_TRAP_GROUP_SP_VRRP, 5928 MLXSW_REG_HTGT_TRAP_GROUP_SP_PKT_SAMPLE, 5929 MLXSW_REG_HTGT_TRAP_GROUP_SP_FLOW_LOGGING, 5930 MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS, 5931 MLXSW_REG_HTGT_TRAP_GROUP_SP_BFD, 5932 MLXSW_REG_HTGT_TRAP_GROUP_SP_DUMMY, 5933 MLXSW_REG_HTGT_TRAP_GROUP_SP_L2_DISCARDS, 5934 MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_DISCARDS, 5935 MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_EXCEPTIONS, 5936 MLXSW_REG_HTGT_TRAP_GROUP_SP_TUNNEL_DISCARDS, 5937 MLXSW_REG_HTGT_TRAP_GROUP_SP_ACL_DISCARDS, 5938 MLXSW_REG_HTGT_TRAP_GROUP_SP_BUFFER_DISCARDS, 5939 5940 __MLXSW_REG_HTGT_TRAP_GROUP_MAX, 5941 MLXSW_REG_HTGT_TRAP_GROUP_MAX = __MLXSW_REG_HTGT_TRAP_GROUP_MAX - 1 5942 }; 5943 5944 /* reg_htgt_trap_group 5945 * Trap group number. User defined number specifying which trap groups 5946 * should be forwarded to the CPU. The mapping between trap IDs and trap 5947 * groups is configured using HPKT register. 5948 * Access: Index 5949 */ 5950 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8); 5951 5952 enum { 5953 MLXSW_REG_HTGT_POLICER_DISABLE, 5954 MLXSW_REG_HTGT_POLICER_ENABLE, 5955 }; 5956 5957 /* reg_htgt_pide 5958 * Enable policer ID specified using 'pid' field. 5959 * Access: RW 5960 */ 5961 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1); 5962 5963 #define MLXSW_REG_HTGT_INVALID_POLICER 0xff 5964 5965 /* reg_htgt_pid 5966 * Policer ID for the trap group. 5967 * Access: RW 5968 */ 5969 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8); 5970 5971 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0 5972 5973 /* reg_htgt_mirror_action 5974 * Mirror action to use. 5975 * 0 - Trap to CPU. 5976 * 1 - Trap to CPU and mirror to a mirroring agent. 5977 * 2 - Mirror to a mirroring agent and do not trap to CPU. 5978 * Access: RW 5979 * 5980 * Note: Mirroring to a mirroring agent is only supported in Spectrum. 5981 */ 5982 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2); 5983 5984 /* reg_htgt_mirroring_agent 5985 * Mirroring agent. 5986 * Access: RW 5987 */ 5988 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3); 5989 5990 #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0 5991 5992 /* reg_htgt_priority 5993 * Trap group priority. 5994 * In case a packet matches multiple classification rules, the packet will 5995 * only be trapped once, based on the trap ID associated with the group (via 5996 * register HPKT) with the highest priority. 5997 * Supported values are 0-7, with 7 represnting the highest priority. 5998 * Access: RW 5999 * 6000 * Note: In SwitchX-2 this field is ignored and the priority value is replaced 6001 * by the 'trap_group' field. 6002 */ 6003 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4); 6004 6005 #define MLXSW_REG_HTGT_DEFAULT_TC 7 6006 6007 /* reg_htgt_local_path_cpu_tclass 6008 * CPU ingress traffic class for the trap group. 6009 * Access: RW 6010 */ 6011 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6); 6012 6013 enum mlxsw_reg_htgt_local_path_rdq { 6014 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13, 6015 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14, 6016 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15, 6017 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15, 6018 }; 6019 /* reg_htgt_local_path_rdq 6020 * Receive descriptor queue (RDQ) to use for the trap group. 6021 * Access: RW 6022 */ 6023 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6); 6024 6025 static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id, 6026 u8 priority, u8 tc) 6027 { 6028 MLXSW_REG_ZERO(htgt, payload); 6029 6030 if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) { 6031 mlxsw_reg_htgt_pide_set(payload, 6032 MLXSW_REG_HTGT_POLICER_DISABLE); 6033 } else { 6034 mlxsw_reg_htgt_pide_set(payload, 6035 MLXSW_REG_HTGT_POLICER_ENABLE); 6036 mlxsw_reg_htgt_pid_set(payload, policer_id); 6037 } 6038 6039 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL); 6040 mlxsw_reg_htgt_trap_group_set(payload, group); 6041 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU); 6042 mlxsw_reg_htgt_mirroring_agent_set(payload, 0); 6043 mlxsw_reg_htgt_priority_set(payload, priority); 6044 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc); 6045 mlxsw_reg_htgt_local_path_rdq_set(payload, group); 6046 } 6047 6048 /* HPKT - Host Packet Trap 6049 * ----------------------- 6050 * Configures trap IDs inside trap groups. 6051 */ 6052 #define MLXSW_REG_HPKT_ID 0x7003 6053 #define MLXSW_REG_HPKT_LEN 0x10 6054 6055 MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN); 6056 6057 enum { 6058 MLXSW_REG_HPKT_ACK_NOT_REQUIRED, 6059 MLXSW_REG_HPKT_ACK_REQUIRED, 6060 }; 6061 6062 /* reg_hpkt_ack 6063 * Require acknowledgements from the host for events. 6064 * If set, then the device will wait for the event it sent to be acknowledged 6065 * by the host. This option is only relevant for event trap IDs. 6066 * Access: RW 6067 * 6068 * Note: Currently not supported by firmware. 6069 */ 6070 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1); 6071 6072 enum mlxsw_reg_hpkt_action { 6073 MLXSW_REG_HPKT_ACTION_FORWARD, 6074 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU, 6075 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU, 6076 MLXSW_REG_HPKT_ACTION_DISCARD, 6077 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD, 6078 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD, 6079 MLXSW_REG_HPKT_ACTION_TRAP_EXCEPTION_TO_CPU, 6080 MLXSW_REG_HPKT_ACTION_SET_FW_DEFAULT = 15, 6081 }; 6082 6083 /* reg_hpkt_action 6084 * Action to perform on packet when trapped. 6085 * 0 - No action. Forward to CPU based on switching rules. 6086 * 1 - Trap to CPU (CPU receives sole copy). 6087 * 2 - Mirror to CPU (CPU receives a replica of the packet). 6088 * 3 - Discard. 6089 * 4 - Soft discard (allow other traps to act on the packet). 6090 * 5 - Trap and soft discard (allow other traps to overwrite this trap). 6091 * 6 - Trap to CPU (CPU receives sole copy) and count it as error. 6092 * 15 - Restore the firmware's default action. 6093 * Access: RW 6094 * 6095 * Note: Must be set to 0 (forward) for event trap IDs, as they are already 6096 * addressed to the CPU. 6097 */ 6098 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3); 6099 6100 /* reg_hpkt_trap_group 6101 * Trap group to associate the trap with. 6102 * Access: RW 6103 */ 6104 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6); 6105 6106 /* reg_hpkt_trap_id 6107 * Trap ID. 6108 * Access: Index 6109 * 6110 * Note: A trap ID can only be associated with a single trap group. The device 6111 * will associate the trap ID with the last trap group configured. 6112 */ 6113 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 10); 6114 6115 enum { 6116 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT, 6117 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER, 6118 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER, 6119 }; 6120 6121 /* reg_hpkt_ctrl 6122 * Configure dedicated buffer resources for control packets. 6123 * Ignored by SwitchX-2. 6124 * 0 - Keep factory defaults. 6125 * 1 - Do not use control buffer for this trap ID. 6126 * 2 - Use control buffer for this trap ID. 6127 * Access: RW 6128 */ 6129 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2); 6130 6131 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id, 6132 enum mlxsw_reg_htgt_trap_group trap_group, 6133 bool is_ctrl) 6134 { 6135 MLXSW_REG_ZERO(hpkt, payload); 6136 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED); 6137 mlxsw_reg_hpkt_action_set(payload, action); 6138 mlxsw_reg_hpkt_trap_group_set(payload, trap_group); 6139 mlxsw_reg_hpkt_trap_id_set(payload, trap_id); 6140 mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ? 6141 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER : 6142 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER); 6143 } 6144 6145 /* RGCR - Router General Configuration Register 6146 * -------------------------------------------- 6147 * The register is used for setting up the router configuration. 6148 */ 6149 #define MLXSW_REG_RGCR_ID 0x8001 6150 #define MLXSW_REG_RGCR_LEN 0x28 6151 6152 MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN); 6153 6154 /* reg_rgcr_ipv4_en 6155 * IPv4 router enable. 6156 * Access: RW 6157 */ 6158 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1); 6159 6160 /* reg_rgcr_ipv6_en 6161 * IPv6 router enable. 6162 * Access: RW 6163 */ 6164 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1); 6165 6166 /* reg_rgcr_max_router_interfaces 6167 * Defines the maximum number of active router interfaces for all virtual 6168 * routers. 6169 * Access: RW 6170 */ 6171 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16); 6172 6173 /* reg_rgcr_usp 6174 * Update switch priority and packet color. 6175 * 0 - Preserve the value of Switch Priority and packet color. 6176 * 1 - Recalculate the value of Switch Priority and packet color. 6177 * Access: RW 6178 * 6179 * Note: Not supported by SwitchX and SwitchX-2. 6180 */ 6181 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1); 6182 6183 /* reg_rgcr_pcp_rw 6184 * Indicates how to handle the pcp_rewrite_en value: 6185 * 0 - Preserve the value of pcp_rewrite_en. 6186 * 2 - Disable PCP rewrite. 6187 * 3 - Enable PCP rewrite. 6188 * Access: RW 6189 * 6190 * Note: Not supported by SwitchX and SwitchX-2. 6191 */ 6192 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2); 6193 6194 /* reg_rgcr_activity_dis 6195 * Activity disable: 6196 * 0 - Activity will be set when an entry is hit (default). 6197 * 1 - Activity will not be set when an entry is hit. 6198 * 6199 * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry 6200 * (RALUE). 6201 * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host 6202 * Entry (RAUHT). 6203 * Bits 2:7 are reserved. 6204 * Access: RW 6205 * 6206 * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB. 6207 */ 6208 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8); 6209 6210 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en, 6211 bool ipv6_en) 6212 { 6213 MLXSW_REG_ZERO(rgcr, payload); 6214 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en); 6215 mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en); 6216 } 6217 6218 /* RITR - Router Interface Table Register 6219 * -------------------------------------- 6220 * The register is used to configure the router interface table. 6221 */ 6222 #define MLXSW_REG_RITR_ID 0x8002 6223 #define MLXSW_REG_RITR_LEN 0x40 6224 6225 MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN); 6226 6227 /* reg_ritr_enable 6228 * Enables routing on the router interface. 6229 * Access: RW 6230 */ 6231 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1); 6232 6233 /* reg_ritr_ipv4 6234 * IPv4 routing enable. Enables routing of IPv4 traffic on the router 6235 * interface. 6236 * Access: RW 6237 */ 6238 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1); 6239 6240 /* reg_ritr_ipv6 6241 * IPv6 routing enable. Enables routing of IPv6 traffic on the router 6242 * interface. 6243 * Access: RW 6244 */ 6245 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1); 6246 6247 /* reg_ritr_ipv4_mc 6248 * IPv4 multicast routing enable. 6249 * Access: RW 6250 */ 6251 MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1); 6252 6253 /* reg_ritr_ipv6_mc 6254 * IPv6 multicast routing enable. 6255 * Access: RW 6256 */ 6257 MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1); 6258 6259 enum mlxsw_reg_ritr_if_type { 6260 /* VLAN interface. */ 6261 MLXSW_REG_RITR_VLAN_IF, 6262 /* FID interface. */ 6263 MLXSW_REG_RITR_FID_IF, 6264 /* Sub-port interface. */ 6265 MLXSW_REG_RITR_SP_IF, 6266 /* Loopback Interface. */ 6267 MLXSW_REG_RITR_LOOPBACK_IF, 6268 }; 6269 6270 /* reg_ritr_type 6271 * Router interface type as per enum mlxsw_reg_ritr_if_type. 6272 * Access: RW 6273 */ 6274 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3); 6275 6276 enum { 6277 MLXSW_REG_RITR_RIF_CREATE, 6278 MLXSW_REG_RITR_RIF_DEL, 6279 }; 6280 6281 /* reg_ritr_op 6282 * Opcode: 6283 * 0 - Create or edit RIF. 6284 * 1 - Delete RIF. 6285 * Reserved for SwitchX-2. For Spectrum, editing of interface properties 6286 * is not supported. An interface must be deleted and re-created in order 6287 * to update properties. 6288 * Access: WO 6289 */ 6290 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2); 6291 6292 /* reg_ritr_rif 6293 * Router interface index. A pointer to the Router Interface Table. 6294 * Access: Index 6295 */ 6296 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16); 6297 6298 /* reg_ritr_ipv4_fe 6299 * IPv4 Forwarding Enable. 6300 * Enables routing of IPv4 traffic on the router interface. When disabled, 6301 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 6302 * Not supported in SwitchX-2. 6303 * Access: RW 6304 */ 6305 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1); 6306 6307 /* reg_ritr_ipv6_fe 6308 * IPv6 Forwarding Enable. 6309 * Enables routing of IPv6 traffic on the router interface. When disabled, 6310 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 6311 * Not supported in SwitchX-2. 6312 * Access: RW 6313 */ 6314 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1); 6315 6316 /* reg_ritr_ipv4_mc_fe 6317 * IPv4 Multicast Forwarding Enable. 6318 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 6319 * will be enabled. 6320 * Access: RW 6321 */ 6322 MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1); 6323 6324 /* reg_ritr_ipv6_mc_fe 6325 * IPv6 Multicast Forwarding Enable. 6326 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 6327 * will be enabled. 6328 * Access: RW 6329 */ 6330 MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1); 6331 6332 /* reg_ritr_lb_en 6333 * Loop-back filter enable for unicast packets. 6334 * If the flag is set then loop-back filter for unicast packets is 6335 * implemented on the RIF. Multicast packets are always subject to 6336 * loop-back filtering. 6337 * Access: RW 6338 */ 6339 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1); 6340 6341 /* reg_ritr_virtual_router 6342 * Virtual router ID associated with the router interface. 6343 * Access: RW 6344 */ 6345 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16); 6346 6347 /* reg_ritr_mtu 6348 * Router interface MTU. 6349 * Access: RW 6350 */ 6351 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16); 6352 6353 /* reg_ritr_if_swid 6354 * Switch partition ID. 6355 * Access: RW 6356 */ 6357 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8); 6358 6359 /* reg_ritr_if_mac 6360 * Router interface MAC address. 6361 * In Spectrum, all MAC addresses must have the same 38 MSBits. 6362 * Access: RW 6363 */ 6364 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6); 6365 6366 /* reg_ritr_if_vrrp_id_ipv6 6367 * VRRP ID for IPv6 6368 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 6369 * Access: RW 6370 */ 6371 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8); 6372 6373 /* reg_ritr_if_vrrp_id_ipv4 6374 * VRRP ID for IPv4 6375 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 6376 * Access: RW 6377 */ 6378 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8); 6379 6380 /* VLAN Interface */ 6381 6382 /* reg_ritr_vlan_if_vid 6383 * VLAN ID. 6384 * Access: RW 6385 */ 6386 MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12); 6387 6388 /* FID Interface */ 6389 6390 /* reg_ritr_fid_if_fid 6391 * Filtering ID. Used to connect a bridge to the router. Only FIDs from 6392 * the vFID range are supported. 6393 * Access: RW 6394 */ 6395 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16); 6396 6397 static inline void mlxsw_reg_ritr_fid_set(char *payload, 6398 enum mlxsw_reg_ritr_if_type rif_type, 6399 u16 fid) 6400 { 6401 if (rif_type == MLXSW_REG_RITR_FID_IF) 6402 mlxsw_reg_ritr_fid_if_fid_set(payload, fid); 6403 else 6404 mlxsw_reg_ritr_vlan_if_vid_set(payload, fid); 6405 } 6406 6407 /* Sub-port Interface */ 6408 6409 /* reg_ritr_sp_if_lag 6410 * LAG indication. When this bit is set the system_port field holds the 6411 * LAG identifier. 6412 * Access: RW 6413 */ 6414 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1); 6415 6416 /* reg_ritr_sp_system_port 6417 * Port unique indentifier. When lag bit is set, this field holds the 6418 * lag_id in bits 0:9. 6419 * Access: RW 6420 */ 6421 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16); 6422 6423 /* reg_ritr_sp_if_vid 6424 * VLAN ID. 6425 * Access: RW 6426 */ 6427 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12); 6428 6429 /* Loopback Interface */ 6430 6431 enum mlxsw_reg_ritr_loopback_protocol { 6432 /* IPinIP IPv4 underlay Unicast */ 6433 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4, 6434 /* IPinIP IPv6 underlay Unicast */ 6435 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6, 6436 /* IPinIP generic - used for Spectrum-2 underlay RIF */ 6437 MLXSW_REG_RITR_LOOPBACK_GENERIC, 6438 }; 6439 6440 /* reg_ritr_loopback_protocol 6441 * Access: RW 6442 */ 6443 MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4); 6444 6445 enum mlxsw_reg_ritr_loopback_ipip_type { 6446 /* Tunnel is IPinIP. */ 6447 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP, 6448 /* Tunnel is GRE, no key. */ 6449 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP, 6450 /* Tunnel is GRE, with a key. */ 6451 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP, 6452 }; 6453 6454 /* reg_ritr_loopback_ipip_type 6455 * Encapsulation type. 6456 * Access: RW 6457 */ 6458 MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4); 6459 6460 enum mlxsw_reg_ritr_loopback_ipip_options { 6461 /* The key is defined by gre_key. */ 6462 MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET, 6463 }; 6464 6465 /* reg_ritr_loopback_ipip_options 6466 * Access: RW 6467 */ 6468 MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4); 6469 6470 /* reg_ritr_loopback_ipip_uvr 6471 * Underlay Virtual Router ID. 6472 * Range is 0..cap_max_virtual_routers-1. 6473 * Reserved for Spectrum-2. 6474 * Access: RW 6475 */ 6476 MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16); 6477 6478 /* reg_ritr_loopback_ipip_underlay_rif 6479 * Underlay ingress router interface. 6480 * Reserved for Spectrum. 6481 * Access: RW 6482 */ 6483 MLXSW_ITEM32(reg, ritr, loopback_ipip_underlay_rif, 0x14, 0, 16); 6484 6485 /* reg_ritr_loopback_ipip_usip* 6486 * Encapsulation Underlay source IP. 6487 * Access: RW 6488 */ 6489 MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16); 6490 MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32); 6491 6492 /* reg_ritr_loopback_ipip_gre_key 6493 * GRE Key. 6494 * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP. 6495 * Access: RW 6496 */ 6497 MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32); 6498 6499 /* Shared between ingress/egress */ 6500 enum mlxsw_reg_ritr_counter_set_type { 6501 /* No Count. */ 6502 MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0, 6503 /* Basic. Used for router interfaces, counting the following: 6504 * - Error and Discard counters. 6505 * - Unicast, Multicast and Broadcast counters. Sharing the 6506 * same set of counters for the different type of traffic 6507 * (IPv4, IPv6 and mpls). 6508 */ 6509 MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9, 6510 }; 6511 6512 /* reg_ritr_ingress_counter_index 6513 * Counter Index for flow counter. 6514 * Access: RW 6515 */ 6516 MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24); 6517 6518 /* reg_ritr_ingress_counter_set_type 6519 * Igress Counter Set Type for router interface counter. 6520 * Access: RW 6521 */ 6522 MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8); 6523 6524 /* reg_ritr_egress_counter_index 6525 * Counter Index for flow counter. 6526 * Access: RW 6527 */ 6528 MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24); 6529 6530 /* reg_ritr_egress_counter_set_type 6531 * Egress Counter Set Type for router interface counter. 6532 * Access: RW 6533 */ 6534 MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8); 6535 6536 static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index, 6537 bool enable, bool egress) 6538 { 6539 enum mlxsw_reg_ritr_counter_set_type set_type; 6540 6541 if (enable) 6542 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC; 6543 else 6544 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT; 6545 mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type); 6546 6547 if (egress) 6548 mlxsw_reg_ritr_egress_counter_index_set(payload, index); 6549 else 6550 mlxsw_reg_ritr_ingress_counter_index_set(payload, index); 6551 } 6552 6553 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif) 6554 { 6555 MLXSW_REG_ZERO(ritr, payload); 6556 mlxsw_reg_ritr_rif_set(payload, rif); 6557 } 6558 6559 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag, 6560 u16 system_port, u16 vid) 6561 { 6562 mlxsw_reg_ritr_sp_if_lag_set(payload, lag); 6563 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port); 6564 mlxsw_reg_ritr_sp_if_vid_set(payload, vid); 6565 } 6566 6567 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable, 6568 enum mlxsw_reg_ritr_if_type type, 6569 u16 rif, u16 vr_id, u16 mtu) 6570 { 6571 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL; 6572 6573 MLXSW_REG_ZERO(ritr, payload); 6574 mlxsw_reg_ritr_enable_set(payload, enable); 6575 mlxsw_reg_ritr_ipv4_set(payload, 1); 6576 mlxsw_reg_ritr_ipv6_set(payload, 1); 6577 mlxsw_reg_ritr_ipv4_mc_set(payload, 1); 6578 mlxsw_reg_ritr_ipv6_mc_set(payload, 1); 6579 mlxsw_reg_ritr_type_set(payload, type); 6580 mlxsw_reg_ritr_op_set(payload, op); 6581 mlxsw_reg_ritr_rif_set(payload, rif); 6582 mlxsw_reg_ritr_ipv4_fe_set(payload, 1); 6583 mlxsw_reg_ritr_ipv6_fe_set(payload, 1); 6584 mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1); 6585 mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1); 6586 mlxsw_reg_ritr_lb_en_set(payload, 1); 6587 mlxsw_reg_ritr_virtual_router_set(payload, vr_id); 6588 mlxsw_reg_ritr_mtu_set(payload, mtu); 6589 } 6590 6591 static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac) 6592 { 6593 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac); 6594 } 6595 6596 static inline void 6597 mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload, 6598 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 6599 enum mlxsw_reg_ritr_loopback_ipip_options options, 6600 u16 uvr_id, u16 underlay_rif, u32 gre_key) 6601 { 6602 mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type); 6603 mlxsw_reg_ritr_loopback_ipip_options_set(payload, options); 6604 mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id); 6605 mlxsw_reg_ritr_loopback_ipip_underlay_rif_set(payload, underlay_rif); 6606 mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key); 6607 } 6608 6609 static inline void 6610 mlxsw_reg_ritr_loopback_ipip4_pack(char *payload, 6611 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 6612 enum mlxsw_reg_ritr_loopback_ipip_options options, 6613 u16 uvr_id, u16 underlay_rif, u32 usip, u32 gre_key) 6614 { 6615 mlxsw_reg_ritr_loopback_protocol_set(payload, 6616 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4); 6617 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options, 6618 uvr_id, underlay_rif, gre_key); 6619 mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip); 6620 } 6621 6622 /* RTAR - Router TCAM Allocation Register 6623 * -------------------------------------- 6624 * This register is used for allocation of regions in the TCAM table. 6625 */ 6626 #define MLXSW_REG_RTAR_ID 0x8004 6627 #define MLXSW_REG_RTAR_LEN 0x20 6628 6629 MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN); 6630 6631 enum mlxsw_reg_rtar_op { 6632 MLXSW_REG_RTAR_OP_ALLOCATE, 6633 MLXSW_REG_RTAR_OP_RESIZE, 6634 MLXSW_REG_RTAR_OP_DEALLOCATE, 6635 }; 6636 6637 /* reg_rtar_op 6638 * Access: WO 6639 */ 6640 MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4); 6641 6642 enum mlxsw_reg_rtar_key_type { 6643 MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1, 6644 MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3 6645 }; 6646 6647 /* reg_rtar_key_type 6648 * TCAM key type for the region. 6649 * Access: WO 6650 */ 6651 MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8); 6652 6653 /* reg_rtar_region_size 6654 * TCAM region size. When allocating/resizing this is the requested 6655 * size, the response is the actual size. 6656 * Note: Actual size may be larger than requested. 6657 * Reserved for op = Deallocate 6658 * Access: WO 6659 */ 6660 MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16); 6661 6662 static inline void mlxsw_reg_rtar_pack(char *payload, 6663 enum mlxsw_reg_rtar_op op, 6664 enum mlxsw_reg_rtar_key_type key_type, 6665 u16 region_size) 6666 { 6667 MLXSW_REG_ZERO(rtar, payload); 6668 mlxsw_reg_rtar_op_set(payload, op); 6669 mlxsw_reg_rtar_key_type_set(payload, key_type); 6670 mlxsw_reg_rtar_region_size_set(payload, region_size); 6671 } 6672 6673 /* RATR - Router Adjacency Table Register 6674 * -------------------------------------- 6675 * The RATR register is used to configure the Router Adjacency (next-hop) 6676 * Table. 6677 */ 6678 #define MLXSW_REG_RATR_ID 0x8008 6679 #define MLXSW_REG_RATR_LEN 0x2C 6680 6681 MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN); 6682 6683 enum mlxsw_reg_ratr_op { 6684 /* Read */ 6685 MLXSW_REG_RATR_OP_QUERY_READ = 0, 6686 /* Read and clear activity */ 6687 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2, 6688 /* Write Adjacency entry */ 6689 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1, 6690 /* Write Adjacency entry only if the activity is cleared. 6691 * The write may not succeed if the activity is set. There is not 6692 * direct feedback if the write has succeeded or not, however 6693 * the get will reveal the actual entry (SW can compare the get 6694 * response to the set command). 6695 */ 6696 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3, 6697 }; 6698 6699 /* reg_ratr_op 6700 * Note that Write operation may also be used for updating 6701 * counter_set_type and counter_index. In this case all other 6702 * fields must not be updated. 6703 * Access: OP 6704 */ 6705 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4); 6706 6707 /* reg_ratr_v 6708 * Valid bit. Indicates if the adjacency entry is valid. 6709 * Note: the device may need some time before reusing an invalidated 6710 * entry. During this time the entry can not be reused. It is 6711 * recommended to use another entry before reusing an invalidated 6712 * entry (e.g. software can put it at the end of the list for 6713 * reusing). Trying to access an invalidated entry not yet cleared 6714 * by the device results with failure indicating "Try Again" status. 6715 * When valid is '0' then egress_router_interface,trap_action, 6716 * adjacency_parameters and counters are reserved 6717 * Access: RW 6718 */ 6719 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1); 6720 6721 /* reg_ratr_a 6722 * Activity. Set for new entries. Set if a packet lookup has hit on 6723 * the specific entry. To clear the a bit, use "clear activity". 6724 * Access: RO 6725 */ 6726 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1); 6727 6728 enum mlxsw_reg_ratr_type { 6729 /* Ethernet */ 6730 MLXSW_REG_RATR_TYPE_ETHERNET, 6731 /* IPoIB Unicast without GRH. 6732 * Reserved for Spectrum. 6733 */ 6734 MLXSW_REG_RATR_TYPE_IPOIB_UC, 6735 /* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast 6736 * adjacency). 6737 * Reserved for Spectrum. 6738 */ 6739 MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH, 6740 /* IPoIB Multicast. 6741 * Reserved for Spectrum. 6742 */ 6743 MLXSW_REG_RATR_TYPE_IPOIB_MC, 6744 /* MPLS. 6745 * Reserved for SwitchX/-2. 6746 */ 6747 MLXSW_REG_RATR_TYPE_MPLS, 6748 /* IPinIP Encap. 6749 * Reserved for SwitchX/-2. 6750 */ 6751 MLXSW_REG_RATR_TYPE_IPIP, 6752 }; 6753 6754 /* reg_ratr_type 6755 * Adjacency entry type. 6756 * Access: RW 6757 */ 6758 MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4); 6759 6760 /* reg_ratr_adjacency_index_low 6761 * Bits 15:0 of index into the adjacency table. 6762 * For SwitchX and SwitchX-2, the adjacency table is linear and 6763 * used for adjacency entries only. 6764 * For Spectrum, the index is to the KVD linear. 6765 * Access: Index 6766 */ 6767 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16); 6768 6769 /* reg_ratr_egress_router_interface 6770 * Range is 0 .. cap_max_router_interfaces - 1 6771 * Access: RW 6772 */ 6773 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16); 6774 6775 enum mlxsw_reg_ratr_trap_action { 6776 MLXSW_REG_RATR_TRAP_ACTION_NOP, 6777 MLXSW_REG_RATR_TRAP_ACTION_TRAP, 6778 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU, 6779 MLXSW_REG_RATR_TRAP_ACTION_MIRROR, 6780 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS, 6781 }; 6782 6783 /* reg_ratr_trap_action 6784 * see mlxsw_reg_ratr_trap_action 6785 * Access: RW 6786 */ 6787 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4); 6788 6789 /* reg_ratr_adjacency_index_high 6790 * Bits 23:16 of the adjacency_index. 6791 * Access: Index 6792 */ 6793 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8); 6794 6795 enum mlxsw_reg_ratr_trap_id { 6796 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0, 6797 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1, 6798 }; 6799 6800 /* reg_ratr_trap_id 6801 * Trap ID to be reported to CPU. 6802 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 6803 * For trap_action of NOP, MIRROR and DISCARD_ERROR 6804 * Access: RW 6805 */ 6806 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8); 6807 6808 /* reg_ratr_eth_destination_mac 6809 * MAC address of the destination next-hop. 6810 * Access: RW 6811 */ 6812 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6); 6813 6814 enum mlxsw_reg_ratr_ipip_type { 6815 /* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */ 6816 MLXSW_REG_RATR_IPIP_TYPE_IPV4, 6817 /* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */ 6818 MLXSW_REG_RATR_IPIP_TYPE_IPV6, 6819 }; 6820 6821 /* reg_ratr_ipip_type 6822 * Underlay destination ip type. 6823 * Note: the type field must match the protocol of the router interface. 6824 * Access: RW 6825 */ 6826 MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4); 6827 6828 /* reg_ratr_ipip_ipv4_udip 6829 * Underlay ipv4 dip. 6830 * Reserved when ipip_type is IPv6. 6831 * Access: RW 6832 */ 6833 MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32); 6834 6835 /* reg_ratr_ipip_ipv6_ptr 6836 * Pointer to IPv6 underlay destination ip address. 6837 * For Spectrum: Pointer to KVD linear space. 6838 * Access: RW 6839 */ 6840 MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24); 6841 6842 enum mlxsw_reg_flow_counter_set_type { 6843 /* No count */ 6844 MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00, 6845 /* Count packets and bytes */ 6846 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03, 6847 /* Count only packets */ 6848 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05, 6849 }; 6850 6851 /* reg_ratr_counter_set_type 6852 * Counter set type for flow counters 6853 * Access: RW 6854 */ 6855 MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8); 6856 6857 /* reg_ratr_counter_index 6858 * Counter index for flow counters 6859 * Access: RW 6860 */ 6861 MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24); 6862 6863 static inline void 6864 mlxsw_reg_ratr_pack(char *payload, 6865 enum mlxsw_reg_ratr_op op, bool valid, 6866 enum mlxsw_reg_ratr_type type, 6867 u32 adjacency_index, u16 egress_rif) 6868 { 6869 MLXSW_REG_ZERO(ratr, payload); 6870 mlxsw_reg_ratr_op_set(payload, op); 6871 mlxsw_reg_ratr_v_set(payload, valid); 6872 mlxsw_reg_ratr_type_set(payload, type); 6873 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index); 6874 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16); 6875 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif); 6876 } 6877 6878 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload, 6879 const char *dest_mac) 6880 { 6881 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac); 6882 } 6883 6884 static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip) 6885 { 6886 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4); 6887 mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip); 6888 } 6889 6890 static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index, 6891 bool counter_enable) 6892 { 6893 enum mlxsw_reg_flow_counter_set_type set_type; 6894 6895 if (counter_enable) 6896 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES; 6897 else 6898 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT; 6899 6900 mlxsw_reg_ratr_counter_index_set(payload, counter_index); 6901 mlxsw_reg_ratr_counter_set_type_set(payload, set_type); 6902 } 6903 6904 /* RDPM - Router DSCP to Priority Mapping 6905 * -------------------------------------- 6906 * Controls the mapping from DSCP field to switch priority on routed packets 6907 */ 6908 #define MLXSW_REG_RDPM_ID 0x8009 6909 #define MLXSW_REG_RDPM_BASE_LEN 0x00 6910 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01 6911 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64 6912 #define MLXSW_REG_RDPM_LEN 0x40 6913 #define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \ 6914 MLXSW_REG_RDPM_LEN - \ 6915 MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN) 6916 6917 MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN); 6918 6919 /* reg_dscp_entry_e 6920 * Enable update of the specific entry 6921 * Access: Index 6922 */ 6923 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1, 6924 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 6925 6926 /* reg_dscp_entry_prio 6927 * Switch Priority 6928 * Access: RW 6929 */ 6930 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4, 6931 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 6932 6933 static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index, 6934 u8 prio) 6935 { 6936 mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1); 6937 mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio); 6938 } 6939 6940 /* RICNT - Router Interface Counter Register 6941 * ----------------------------------------- 6942 * The RICNT register retrieves per port performance counters 6943 */ 6944 #define MLXSW_REG_RICNT_ID 0x800B 6945 #define MLXSW_REG_RICNT_LEN 0x100 6946 6947 MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN); 6948 6949 /* reg_ricnt_counter_index 6950 * Counter index 6951 * Access: RW 6952 */ 6953 MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24); 6954 6955 enum mlxsw_reg_ricnt_counter_set_type { 6956 /* No Count. */ 6957 MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00, 6958 /* Basic. Used for router interfaces, counting the following: 6959 * - Error and Discard counters. 6960 * - Unicast, Multicast and Broadcast counters. Sharing the 6961 * same set of counters for the different type of traffic 6962 * (IPv4, IPv6 and mpls). 6963 */ 6964 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09, 6965 }; 6966 6967 /* reg_ricnt_counter_set_type 6968 * Counter Set Type for router interface counter 6969 * Access: RW 6970 */ 6971 MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8); 6972 6973 enum mlxsw_reg_ricnt_opcode { 6974 /* Nop. Supported only for read access*/ 6975 MLXSW_REG_RICNT_OPCODE_NOP = 0x00, 6976 /* Clear. Setting the clr bit will reset the counter value for 6977 * all counters of the specified Router Interface. 6978 */ 6979 MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08, 6980 }; 6981 6982 /* reg_ricnt_opcode 6983 * Opcode 6984 * Access: RW 6985 */ 6986 MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4); 6987 6988 /* reg_ricnt_good_unicast_packets 6989 * good unicast packets. 6990 * Access: RW 6991 */ 6992 MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64); 6993 6994 /* reg_ricnt_good_multicast_packets 6995 * good multicast packets. 6996 * Access: RW 6997 */ 6998 MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64); 6999 7000 /* reg_ricnt_good_broadcast_packets 7001 * good broadcast packets 7002 * Access: RW 7003 */ 7004 MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64); 7005 7006 /* reg_ricnt_good_unicast_bytes 7007 * A count of L3 data and padding octets not including L2 headers 7008 * for good unicast frames. 7009 * Access: RW 7010 */ 7011 MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64); 7012 7013 /* reg_ricnt_good_multicast_bytes 7014 * A count of L3 data and padding octets not including L2 headers 7015 * for good multicast frames. 7016 * Access: RW 7017 */ 7018 MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64); 7019 7020 /* reg_ritr_good_broadcast_bytes 7021 * A count of L3 data and padding octets not including L2 headers 7022 * for good broadcast frames. 7023 * Access: RW 7024 */ 7025 MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64); 7026 7027 /* reg_ricnt_error_packets 7028 * A count of errored frames that do not pass the router checks. 7029 * Access: RW 7030 */ 7031 MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64); 7032 7033 /* reg_ricnt_discrad_packets 7034 * A count of non-errored frames that do not pass the router checks. 7035 * Access: RW 7036 */ 7037 MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64); 7038 7039 /* reg_ricnt_error_bytes 7040 * A count of L3 data and padding octets not including L2 headers 7041 * for errored frames. 7042 * Access: RW 7043 */ 7044 MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64); 7045 7046 /* reg_ricnt_discard_bytes 7047 * A count of L3 data and padding octets not including L2 headers 7048 * for non-errored frames that do not pass the router checks. 7049 * Access: RW 7050 */ 7051 MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64); 7052 7053 static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index, 7054 enum mlxsw_reg_ricnt_opcode op) 7055 { 7056 MLXSW_REG_ZERO(ricnt, payload); 7057 mlxsw_reg_ricnt_op_set(payload, op); 7058 mlxsw_reg_ricnt_counter_index_set(payload, index); 7059 mlxsw_reg_ricnt_counter_set_type_set(payload, 7060 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC); 7061 } 7062 7063 /* RRCR - Router Rules Copy Register Layout 7064 * ---------------------------------------- 7065 * This register is used for moving and copying route entry rules. 7066 */ 7067 #define MLXSW_REG_RRCR_ID 0x800F 7068 #define MLXSW_REG_RRCR_LEN 0x24 7069 7070 MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN); 7071 7072 enum mlxsw_reg_rrcr_op { 7073 /* Move rules */ 7074 MLXSW_REG_RRCR_OP_MOVE, 7075 /* Copy rules */ 7076 MLXSW_REG_RRCR_OP_COPY, 7077 }; 7078 7079 /* reg_rrcr_op 7080 * Access: WO 7081 */ 7082 MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4); 7083 7084 /* reg_rrcr_offset 7085 * Offset within the region from which to copy/move. 7086 * Access: Index 7087 */ 7088 MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16); 7089 7090 /* reg_rrcr_size 7091 * The number of rules to copy/move. 7092 * Access: WO 7093 */ 7094 MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16); 7095 7096 /* reg_rrcr_table_id 7097 * Identifier of the table on which to perform the operation. Encoding is the 7098 * same as in RTAR.key_type 7099 * Access: Index 7100 */ 7101 MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4); 7102 7103 /* reg_rrcr_dest_offset 7104 * Offset within the region to which to copy/move 7105 * Access: Index 7106 */ 7107 MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16); 7108 7109 static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op, 7110 u16 offset, u16 size, 7111 enum mlxsw_reg_rtar_key_type table_id, 7112 u16 dest_offset) 7113 { 7114 MLXSW_REG_ZERO(rrcr, payload); 7115 mlxsw_reg_rrcr_op_set(payload, op); 7116 mlxsw_reg_rrcr_offset_set(payload, offset); 7117 mlxsw_reg_rrcr_size_set(payload, size); 7118 mlxsw_reg_rrcr_table_id_set(payload, table_id); 7119 mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset); 7120 } 7121 7122 /* RALTA - Router Algorithmic LPM Tree Allocation Register 7123 * ------------------------------------------------------- 7124 * RALTA is used to allocate the LPM trees of the SHSPM method. 7125 */ 7126 #define MLXSW_REG_RALTA_ID 0x8010 7127 #define MLXSW_REG_RALTA_LEN 0x04 7128 7129 MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN); 7130 7131 /* reg_ralta_op 7132 * opcode (valid for Write, must be 0 on Read) 7133 * 0 - allocate a tree 7134 * 1 - deallocate a tree 7135 * Access: OP 7136 */ 7137 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2); 7138 7139 enum mlxsw_reg_ralxx_protocol { 7140 MLXSW_REG_RALXX_PROTOCOL_IPV4, 7141 MLXSW_REG_RALXX_PROTOCOL_IPV6, 7142 }; 7143 7144 /* reg_ralta_protocol 7145 * Protocol. 7146 * Deallocation opcode: Reserved. 7147 * Access: RW 7148 */ 7149 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4); 7150 7151 /* reg_ralta_tree_id 7152 * An identifier (numbered from 1..cap_shspm_max_trees-1) representing 7153 * the tree identifier (managed by software). 7154 * Note that tree_id 0 is allocated for a default-route tree. 7155 * Access: Index 7156 */ 7157 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8); 7158 7159 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc, 7160 enum mlxsw_reg_ralxx_protocol protocol, 7161 u8 tree_id) 7162 { 7163 MLXSW_REG_ZERO(ralta, payload); 7164 mlxsw_reg_ralta_op_set(payload, !alloc); 7165 mlxsw_reg_ralta_protocol_set(payload, protocol); 7166 mlxsw_reg_ralta_tree_id_set(payload, tree_id); 7167 } 7168 7169 /* RALST - Router Algorithmic LPM Structure Tree Register 7170 * ------------------------------------------------------ 7171 * RALST is used to set and query the structure of an LPM tree. 7172 * The structure of the tree must be sorted as a sorted binary tree, while 7173 * each node is a bin that is tagged as the length of the prefixes the lookup 7174 * will refer to. Therefore, bin X refers to a set of entries with prefixes 7175 * of X bits to match with the destination address. The bin 0 indicates 7176 * the default action, when there is no match of any prefix. 7177 */ 7178 #define MLXSW_REG_RALST_ID 0x8011 7179 #define MLXSW_REG_RALST_LEN 0x104 7180 7181 MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN); 7182 7183 /* reg_ralst_root_bin 7184 * The bin number of the root bin. 7185 * 0<root_bin=<(length of IP address) 7186 * For a default-route tree configure 0xff 7187 * Access: RW 7188 */ 7189 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8); 7190 7191 /* reg_ralst_tree_id 7192 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 7193 * Access: Index 7194 */ 7195 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8); 7196 7197 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff 7198 #define MLXSW_REG_RALST_BIN_OFFSET 0x04 7199 #define MLXSW_REG_RALST_BIN_COUNT 128 7200 7201 /* reg_ralst_left_child_bin 7202 * Holding the children of the bin according to the stored tree's structure. 7203 * For trees composed of less than 4 blocks, the bins in excess are reserved. 7204 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 7205 * Access: RW 7206 */ 7207 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false); 7208 7209 /* reg_ralst_right_child_bin 7210 * Holding the children of the bin according to the stored tree's structure. 7211 * For trees composed of less than 4 blocks, the bins in excess are reserved. 7212 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 7213 * Access: RW 7214 */ 7215 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00, 7216 false); 7217 7218 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id) 7219 { 7220 MLXSW_REG_ZERO(ralst, payload); 7221 7222 /* Initialize all bins to have no left or right child */ 7223 memset(payload + MLXSW_REG_RALST_BIN_OFFSET, 7224 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2); 7225 7226 mlxsw_reg_ralst_root_bin_set(payload, root_bin); 7227 mlxsw_reg_ralst_tree_id_set(payload, tree_id); 7228 } 7229 7230 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number, 7231 u8 left_child_bin, 7232 u8 right_child_bin) 7233 { 7234 int bin_index = bin_number - 1; 7235 7236 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin); 7237 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index, 7238 right_child_bin); 7239 } 7240 7241 /* RALTB - Router Algorithmic LPM Tree Binding Register 7242 * ---------------------------------------------------- 7243 * RALTB is used to bind virtual router and protocol to an allocated LPM tree. 7244 */ 7245 #define MLXSW_REG_RALTB_ID 0x8012 7246 #define MLXSW_REG_RALTB_LEN 0x04 7247 7248 MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN); 7249 7250 /* reg_raltb_virtual_router 7251 * Virtual Router ID 7252 * Range is 0..cap_max_virtual_routers-1 7253 * Access: Index 7254 */ 7255 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16); 7256 7257 /* reg_raltb_protocol 7258 * Protocol. 7259 * Access: Index 7260 */ 7261 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4); 7262 7263 /* reg_raltb_tree_id 7264 * Tree to be used for the {virtual_router, protocol} 7265 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 7266 * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0. 7267 * Access: RW 7268 */ 7269 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8); 7270 7271 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router, 7272 enum mlxsw_reg_ralxx_protocol protocol, 7273 u8 tree_id) 7274 { 7275 MLXSW_REG_ZERO(raltb, payload); 7276 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router); 7277 mlxsw_reg_raltb_protocol_set(payload, protocol); 7278 mlxsw_reg_raltb_tree_id_set(payload, tree_id); 7279 } 7280 7281 /* RALUE - Router Algorithmic LPM Unicast Entry Register 7282 * ----------------------------------------------------- 7283 * RALUE is used to configure and query LPM entries that serve 7284 * the Unicast protocols. 7285 */ 7286 #define MLXSW_REG_RALUE_ID 0x8013 7287 #define MLXSW_REG_RALUE_LEN 0x38 7288 7289 MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN); 7290 7291 /* reg_ralue_protocol 7292 * Protocol. 7293 * Access: Index 7294 */ 7295 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4); 7296 7297 enum mlxsw_reg_ralue_op { 7298 /* Read operation. If entry doesn't exist, the operation fails. */ 7299 MLXSW_REG_RALUE_OP_QUERY_READ = 0, 7300 /* Clear on read operation. Used to read entry and 7301 * clear Activity bit. 7302 */ 7303 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1, 7304 /* Write operation. Used to write a new entry to the table. All RW 7305 * fields are written for new entry. Activity bit is set 7306 * for new entries. 7307 */ 7308 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0, 7309 /* Update operation. Used to update an existing route entry and 7310 * only update the RW fields that are detailed in the field 7311 * op_u_mask. If entry doesn't exist, the operation fails. 7312 */ 7313 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1, 7314 /* Clear activity. The Activity bit (the field a) is cleared 7315 * for the entry. 7316 */ 7317 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2, 7318 /* Delete operation. Used to delete an existing entry. If entry 7319 * doesn't exist, the operation fails. 7320 */ 7321 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3, 7322 }; 7323 7324 /* reg_ralue_op 7325 * Operation. 7326 * Access: OP 7327 */ 7328 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3); 7329 7330 /* reg_ralue_a 7331 * Activity. Set for new entries. Set if a packet lookup has hit on the 7332 * specific entry, only if the entry is a route. To clear the a bit, use 7333 * "clear activity" op. 7334 * Enabled by activity_dis in RGCR 7335 * Access: RO 7336 */ 7337 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1); 7338 7339 /* reg_ralue_virtual_router 7340 * Virtual Router ID 7341 * Range is 0..cap_max_virtual_routers-1 7342 * Access: Index 7343 */ 7344 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16); 7345 7346 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0) 7347 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1) 7348 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2) 7349 7350 /* reg_ralue_op_u_mask 7351 * opcode update mask. 7352 * On read operation, this field is reserved. 7353 * This field is valid for update opcode, otherwise - reserved. 7354 * This field is a bitmask of the fields that should be updated. 7355 * Access: WO 7356 */ 7357 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3); 7358 7359 /* reg_ralue_prefix_len 7360 * Number of bits in the prefix of the LPM route. 7361 * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes 7362 * two entries in the physical HW table. 7363 * Access: Index 7364 */ 7365 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8); 7366 7367 /* reg_ralue_dip* 7368 * The prefix of the route or of the marker that the object of the LPM 7369 * is compared with. The most significant bits of the dip are the prefix. 7370 * The least significant bits must be '0' if the prefix_len is smaller 7371 * than 128 for IPv6 or smaller than 32 for IPv4. 7372 * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved. 7373 * Access: Index 7374 */ 7375 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32); 7376 MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16); 7377 7378 enum mlxsw_reg_ralue_entry_type { 7379 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1, 7380 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2, 7381 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3, 7382 }; 7383 7384 /* reg_ralue_entry_type 7385 * Entry type. 7386 * Note - for Marker entries, the action_type and action fields are reserved. 7387 * Access: RW 7388 */ 7389 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2); 7390 7391 /* reg_ralue_bmp_len 7392 * The best match prefix length in the case that there is no match for 7393 * longer prefixes. 7394 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len 7395 * Note for any update operation with entry_type modification this 7396 * field must be set. 7397 * Access: RW 7398 */ 7399 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8); 7400 7401 enum mlxsw_reg_ralue_action_type { 7402 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE, 7403 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL, 7404 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME, 7405 }; 7406 7407 /* reg_ralue_action_type 7408 * Action Type 7409 * Indicates how the IP address is connected. 7410 * It can be connected to a local subnet through local_erif or can be 7411 * on a remote subnet connected through a next-hop router, 7412 * or transmitted to the CPU. 7413 * Reserved when entry_type = MARKER_ENTRY 7414 * Access: RW 7415 */ 7416 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2); 7417 7418 enum mlxsw_reg_ralue_trap_action { 7419 MLXSW_REG_RALUE_TRAP_ACTION_NOP, 7420 MLXSW_REG_RALUE_TRAP_ACTION_TRAP, 7421 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU, 7422 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR, 7423 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR, 7424 }; 7425 7426 /* reg_ralue_trap_action 7427 * Trap action. 7428 * For IP2ME action, only NOP and MIRROR are possible. 7429 * Access: RW 7430 */ 7431 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4); 7432 7433 /* reg_ralue_trap_id 7434 * Trap ID to be reported to CPU. 7435 * Trap ID is RTR_INGRESS0 or RTR_INGRESS1. 7436 * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved. 7437 * Access: RW 7438 */ 7439 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9); 7440 7441 /* reg_ralue_adjacency_index 7442 * Points to the first entry of the group-based ECMP. 7443 * Only relevant in case of REMOTE action. 7444 * Access: RW 7445 */ 7446 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24); 7447 7448 /* reg_ralue_ecmp_size 7449 * Amount of sequential entries starting 7450 * from the adjacency_index (the number of ECMPs). 7451 * The valid range is 1-64, 512, 1024, 2048 and 4096. 7452 * Reserved when trap_action is TRAP or DISCARD_ERROR. 7453 * Only relevant in case of REMOTE action. 7454 * Access: RW 7455 */ 7456 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13); 7457 7458 /* reg_ralue_local_erif 7459 * Egress Router Interface. 7460 * Only relevant in case of LOCAL action. 7461 * Access: RW 7462 */ 7463 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16); 7464 7465 /* reg_ralue_ip2me_v 7466 * Valid bit for the tunnel_ptr field. 7467 * If valid = 0 then trap to CPU as IP2ME trap ID. 7468 * If valid = 1 and the packet format allows NVE or IPinIP tunnel 7469 * decapsulation then tunnel decapsulation is done. 7470 * If valid = 1 and packet format does not allow NVE or IPinIP tunnel 7471 * decapsulation then trap as IP2ME trap ID. 7472 * Only relevant in case of IP2ME action. 7473 * Access: RW 7474 */ 7475 MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1); 7476 7477 /* reg_ralue_ip2me_tunnel_ptr 7478 * Tunnel Pointer for NVE or IPinIP tunnel decapsulation. 7479 * For Spectrum, pointer to KVD Linear. 7480 * Only relevant in case of IP2ME action. 7481 * Access: RW 7482 */ 7483 MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24); 7484 7485 static inline void mlxsw_reg_ralue_pack(char *payload, 7486 enum mlxsw_reg_ralxx_protocol protocol, 7487 enum mlxsw_reg_ralue_op op, 7488 u16 virtual_router, u8 prefix_len) 7489 { 7490 MLXSW_REG_ZERO(ralue, payload); 7491 mlxsw_reg_ralue_protocol_set(payload, protocol); 7492 mlxsw_reg_ralue_op_set(payload, op); 7493 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router); 7494 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len); 7495 mlxsw_reg_ralue_entry_type_set(payload, 7496 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY); 7497 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len); 7498 } 7499 7500 static inline void mlxsw_reg_ralue_pack4(char *payload, 7501 enum mlxsw_reg_ralxx_protocol protocol, 7502 enum mlxsw_reg_ralue_op op, 7503 u16 virtual_router, u8 prefix_len, 7504 u32 *dip) 7505 { 7506 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 7507 if (dip) 7508 mlxsw_reg_ralue_dip4_set(payload, *dip); 7509 } 7510 7511 static inline void mlxsw_reg_ralue_pack6(char *payload, 7512 enum mlxsw_reg_ralxx_protocol protocol, 7513 enum mlxsw_reg_ralue_op op, 7514 u16 virtual_router, u8 prefix_len, 7515 const void *dip) 7516 { 7517 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 7518 if (dip) 7519 mlxsw_reg_ralue_dip6_memcpy_to(payload, dip); 7520 } 7521 7522 static inline void 7523 mlxsw_reg_ralue_act_remote_pack(char *payload, 7524 enum mlxsw_reg_ralue_trap_action trap_action, 7525 u16 trap_id, u32 adjacency_index, u16 ecmp_size) 7526 { 7527 mlxsw_reg_ralue_action_type_set(payload, 7528 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE); 7529 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 7530 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 7531 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index); 7532 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size); 7533 } 7534 7535 static inline void 7536 mlxsw_reg_ralue_act_local_pack(char *payload, 7537 enum mlxsw_reg_ralue_trap_action trap_action, 7538 u16 trap_id, u16 local_erif) 7539 { 7540 mlxsw_reg_ralue_action_type_set(payload, 7541 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL); 7542 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 7543 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 7544 mlxsw_reg_ralue_local_erif_set(payload, local_erif); 7545 } 7546 7547 static inline void 7548 mlxsw_reg_ralue_act_ip2me_pack(char *payload) 7549 { 7550 mlxsw_reg_ralue_action_type_set(payload, 7551 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 7552 } 7553 7554 static inline void 7555 mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr) 7556 { 7557 mlxsw_reg_ralue_action_type_set(payload, 7558 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 7559 mlxsw_reg_ralue_ip2me_v_set(payload, 1); 7560 mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr); 7561 } 7562 7563 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register 7564 * ---------------------------------------------------------- 7565 * The RAUHT register is used to configure and query the Unicast Host table in 7566 * devices that implement the Algorithmic LPM. 7567 */ 7568 #define MLXSW_REG_RAUHT_ID 0x8014 7569 #define MLXSW_REG_RAUHT_LEN 0x74 7570 7571 MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN); 7572 7573 enum mlxsw_reg_rauht_type { 7574 MLXSW_REG_RAUHT_TYPE_IPV4, 7575 MLXSW_REG_RAUHT_TYPE_IPV6, 7576 }; 7577 7578 /* reg_rauht_type 7579 * Access: Index 7580 */ 7581 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2); 7582 7583 enum mlxsw_reg_rauht_op { 7584 MLXSW_REG_RAUHT_OP_QUERY_READ = 0, 7585 /* Read operation */ 7586 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1, 7587 /* Clear on read operation. Used to read entry and clear 7588 * activity bit. 7589 */ 7590 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0, 7591 /* Add. Used to write a new entry to the table. All R/W fields are 7592 * relevant for new entry. Activity bit is set for new entries. 7593 */ 7594 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1, 7595 /* Update action. Used to update an existing route entry and 7596 * only update the following fields: 7597 * trap_action, trap_id, mac, counter_set_type, counter_index 7598 */ 7599 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2, 7600 /* Clear activity. A bit is cleared for the entry. */ 7601 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3, 7602 /* Delete entry */ 7603 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4, 7604 /* Delete all host entries on a RIF. In this command, dip 7605 * field is reserved. 7606 */ 7607 }; 7608 7609 /* reg_rauht_op 7610 * Access: OP 7611 */ 7612 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3); 7613 7614 /* reg_rauht_a 7615 * Activity. Set for new entries. Set if a packet lookup has hit on 7616 * the specific entry. 7617 * To clear the a bit, use "clear activity" op. 7618 * Enabled by activity_dis in RGCR 7619 * Access: RO 7620 */ 7621 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1); 7622 7623 /* reg_rauht_rif 7624 * Router Interface 7625 * Access: Index 7626 */ 7627 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16); 7628 7629 /* reg_rauht_dip* 7630 * Destination address. 7631 * Access: Index 7632 */ 7633 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32); 7634 MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16); 7635 7636 enum mlxsw_reg_rauht_trap_action { 7637 MLXSW_REG_RAUHT_TRAP_ACTION_NOP, 7638 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP, 7639 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU, 7640 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR, 7641 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS, 7642 }; 7643 7644 /* reg_rauht_trap_action 7645 * Access: RW 7646 */ 7647 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4); 7648 7649 enum mlxsw_reg_rauht_trap_id { 7650 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0, 7651 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1, 7652 }; 7653 7654 /* reg_rauht_trap_id 7655 * Trap ID to be reported to CPU. 7656 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 7657 * For trap_action of NOP, MIRROR and DISCARD_ERROR, 7658 * trap_id is reserved. 7659 * Access: RW 7660 */ 7661 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9); 7662 7663 /* reg_rauht_counter_set_type 7664 * Counter set type for flow counters 7665 * Access: RW 7666 */ 7667 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8); 7668 7669 /* reg_rauht_counter_index 7670 * Counter index for flow counters 7671 * Access: RW 7672 */ 7673 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24); 7674 7675 /* reg_rauht_mac 7676 * MAC address. 7677 * Access: RW 7678 */ 7679 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6); 7680 7681 static inline void mlxsw_reg_rauht_pack(char *payload, 7682 enum mlxsw_reg_rauht_op op, u16 rif, 7683 const char *mac) 7684 { 7685 MLXSW_REG_ZERO(rauht, payload); 7686 mlxsw_reg_rauht_op_set(payload, op); 7687 mlxsw_reg_rauht_rif_set(payload, rif); 7688 mlxsw_reg_rauht_mac_memcpy_to(payload, mac); 7689 } 7690 7691 static inline void mlxsw_reg_rauht_pack4(char *payload, 7692 enum mlxsw_reg_rauht_op op, u16 rif, 7693 const char *mac, u32 dip) 7694 { 7695 mlxsw_reg_rauht_pack(payload, op, rif, mac); 7696 mlxsw_reg_rauht_dip4_set(payload, dip); 7697 } 7698 7699 static inline void mlxsw_reg_rauht_pack6(char *payload, 7700 enum mlxsw_reg_rauht_op op, u16 rif, 7701 const char *mac, const char *dip) 7702 { 7703 mlxsw_reg_rauht_pack(payload, op, rif, mac); 7704 mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6); 7705 mlxsw_reg_rauht_dip6_memcpy_to(payload, dip); 7706 } 7707 7708 static inline void mlxsw_reg_rauht_pack_counter(char *payload, 7709 u64 counter_index) 7710 { 7711 mlxsw_reg_rauht_counter_index_set(payload, counter_index); 7712 mlxsw_reg_rauht_counter_set_type_set(payload, 7713 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 7714 } 7715 7716 /* RALEU - Router Algorithmic LPM ECMP Update Register 7717 * --------------------------------------------------- 7718 * The register enables updating the ECMP section in the action for multiple 7719 * LPM Unicast entries in a single operation. The update is executed to 7720 * all entries of a {virtual router, protocol} tuple using the same ECMP group. 7721 */ 7722 #define MLXSW_REG_RALEU_ID 0x8015 7723 #define MLXSW_REG_RALEU_LEN 0x28 7724 7725 MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN); 7726 7727 /* reg_raleu_protocol 7728 * Protocol. 7729 * Access: Index 7730 */ 7731 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4); 7732 7733 /* reg_raleu_virtual_router 7734 * Virtual Router ID 7735 * Range is 0..cap_max_virtual_routers-1 7736 * Access: Index 7737 */ 7738 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16); 7739 7740 /* reg_raleu_adjacency_index 7741 * Adjacency Index used for matching on the existing entries. 7742 * Access: Index 7743 */ 7744 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24); 7745 7746 /* reg_raleu_ecmp_size 7747 * ECMP Size used for matching on the existing entries. 7748 * Access: Index 7749 */ 7750 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13); 7751 7752 /* reg_raleu_new_adjacency_index 7753 * New Adjacency Index. 7754 * Access: WO 7755 */ 7756 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24); 7757 7758 /* reg_raleu_new_ecmp_size 7759 * New ECMP Size. 7760 * Access: WO 7761 */ 7762 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13); 7763 7764 static inline void mlxsw_reg_raleu_pack(char *payload, 7765 enum mlxsw_reg_ralxx_protocol protocol, 7766 u16 virtual_router, 7767 u32 adjacency_index, u16 ecmp_size, 7768 u32 new_adjacency_index, 7769 u16 new_ecmp_size) 7770 { 7771 MLXSW_REG_ZERO(raleu, payload); 7772 mlxsw_reg_raleu_protocol_set(payload, protocol); 7773 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router); 7774 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index); 7775 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size); 7776 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index); 7777 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size); 7778 } 7779 7780 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register 7781 * ---------------------------------------------------------------- 7782 * The RAUHTD register allows dumping entries from the Router Unicast Host 7783 * Table. For a given session an entry is dumped no more than one time. The 7784 * first RAUHTD access after reset is a new session. A session ends when the 7785 * num_rec response is smaller than num_rec request or for IPv4 when the 7786 * num_entries is smaller than 4. The clear activity affect the current session 7787 * or the last session if a new session has not started. 7788 */ 7789 #define MLXSW_REG_RAUHTD_ID 0x8018 7790 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20 7791 #define MLXSW_REG_RAUHTD_REC_LEN 0x20 7792 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32 7793 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \ 7794 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN) 7795 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4 7796 7797 MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN); 7798 7799 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0) 7800 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3) 7801 7802 /* reg_rauhtd_filter_fields 7803 * if a bit is '0' then the relevant field is ignored and dump is done 7804 * regardless of the field value 7805 * Bit0 - filter by activity: entry_a 7806 * Bit3 - filter by entry rip: entry_rif 7807 * Access: Index 7808 */ 7809 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8); 7810 7811 enum mlxsw_reg_rauhtd_op { 7812 MLXSW_REG_RAUHTD_OP_DUMP, 7813 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR, 7814 }; 7815 7816 /* reg_rauhtd_op 7817 * Access: OP 7818 */ 7819 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2); 7820 7821 /* reg_rauhtd_num_rec 7822 * At request: number of records requested 7823 * At response: number of records dumped 7824 * For IPv4, each record has 4 entries at request and up to 4 entries 7825 * at response 7826 * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM 7827 * Access: Index 7828 */ 7829 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8); 7830 7831 /* reg_rauhtd_entry_a 7832 * Dump only if activity has value of entry_a 7833 * Reserved if filter_fields bit0 is '0' 7834 * Access: Index 7835 */ 7836 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1); 7837 7838 enum mlxsw_reg_rauhtd_type { 7839 MLXSW_REG_RAUHTD_TYPE_IPV4, 7840 MLXSW_REG_RAUHTD_TYPE_IPV6, 7841 }; 7842 7843 /* reg_rauhtd_type 7844 * Dump only if record type is: 7845 * 0 - IPv4 7846 * 1 - IPv6 7847 * Access: Index 7848 */ 7849 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4); 7850 7851 /* reg_rauhtd_entry_rif 7852 * Dump only if RIF has value of entry_rif 7853 * Reserved if filter_fields bit3 is '0' 7854 * Access: Index 7855 */ 7856 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16); 7857 7858 static inline void mlxsw_reg_rauhtd_pack(char *payload, 7859 enum mlxsw_reg_rauhtd_type type) 7860 { 7861 MLXSW_REG_ZERO(rauhtd, payload); 7862 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A); 7863 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR); 7864 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM); 7865 mlxsw_reg_rauhtd_entry_a_set(payload, 1); 7866 mlxsw_reg_rauhtd_type_set(payload, type); 7867 } 7868 7869 /* reg_rauhtd_ipv4_rec_num_entries 7870 * Number of valid entries in this record: 7871 * 0 - 1 valid entry 7872 * 1 - 2 valid entries 7873 * 2 - 3 valid entries 7874 * 3 - 4 valid entries 7875 * Access: RO 7876 */ 7877 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries, 7878 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2, 7879 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 7880 7881 /* reg_rauhtd_rec_type 7882 * Record type. 7883 * 0 - IPv4 7884 * 1 - IPv6 7885 * Access: RO 7886 */ 7887 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2, 7888 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 7889 7890 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8 7891 7892 /* reg_rauhtd_ipv4_ent_a 7893 * Activity. Set for new entries. Set if a packet lookup has hit on the 7894 * specific entry. 7895 * Access: RO 7896 */ 7897 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 7898 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 7899 7900 /* reg_rauhtd_ipv4_ent_rif 7901 * Router interface. 7902 * Access: RO 7903 */ 7904 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 7905 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 7906 7907 /* reg_rauhtd_ipv4_ent_dip 7908 * Destination IPv4 address. 7909 * Access: RO 7910 */ 7911 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0, 7912 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false); 7913 7914 #define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20 7915 7916 /* reg_rauhtd_ipv6_ent_a 7917 * Activity. Set for new entries. Set if a packet lookup has hit on the 7918 * specific entry. 7919 * Access: RO 7920 */ 7921 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 7922 MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 7923 7924 /* reg_rauhtd_ipv6_ent_rif 7925 * Router interface. 7926 * Access: RO 7927 */ 7928 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 7929 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 7930 7931 /* reg_rauhtd_ipv6_ent_dip 7932 * Destination IPv6 address. 7933 * Access: RO 7934 */ 7935 MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 7936 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10); 7937 7938 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload, 7939 int ent_index, u16 *p_rif, 7940 u32 *p_dip) 7941 { 7942 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index); 7943 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index); 7944 } 7945 7946 static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload, 7947 int rec_index, u16 *p_rif, 7948 char *p_dip) 7949 { 7950 *p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index); 7951 mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip); 7952 } 7953 7954 /* RTDP - Routing Tunnel Decap Properties Register 7955 * ----------------------------------------------- 7956 * The RTDP register is used for configuring the tunnel decap properties of NVE 7957 * and IPinIP. 7958 */ 7959 #define MLXSW_REG_RTDP_ID 0x8020 7960 #define MLXSW_REG_RTDP_LEN 0x44 7961 7962 MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN); 7963 7964 enum mlxsw_reg_rtdp_type { 7965 MLXSW_REG_RTDP_TYPE_NVE, 7966 MLXSW_REG_RTDP_TYPE_IPIP, 7967 }; 7968 7969 /* reg_rtdp_type 7970 * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type. 7971 * Access: RW 7972 */ 7973 MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4); 7974 7975 /* reg_rtdp_tunnel_index 7976 * Index to the Decap entry. 7977 * For Spectrum, Index to KVD Linear. 7978 * Access: Index 7979 */ 7980 MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24); 7981 7982 /* reg_rtdp_egress_router_interface 7983 * Underlay egress router interface. 7984 * Valid range is from 0 to cap_max_router_interfaces - 1 7985 * Access: RW 7986 */ 7987 MLXSW_ITEM32(reg, rtdp, egress_router_interface, 0x40, 0, 16); 7988 7989 /* IPinIP */ 7990 7991 /* reg_rtdp_ipip_irif 7992 * Ingress Router Interface for the overlay router 7993 * Access: RW 7994 */ 7995 MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16); 7996 7997 enum mlxsw_reg_rtdp_ipip_sip_check { 7998 /* No sip checks. */ 7999 MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO, 8000 /* Filter packet if underlay is not IPv4 or if underlay SIP does not 8001 * equal ipv4_usip. 8002 */ 8003 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4, 8004 /* Filter packet if underlay is not IPv6 or if underlay SIP does not 8005 * equal ipv6_usip. 8006 */ 8007 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3, 8008 }; 8009 8010 /* reg_rtdp_ipip_sip_check 8011 * SIP check to perform. If decapsulation failed due to these configurations 8012 * then trap_id is IPIP_DECAP_ERROR. 8013 * Access: RW 8014 */ 8015 MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3); 8016 8017 /* If set, allow decapsulation of IPinIP (without GRE). */ 8018 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP BIT(0) 8019 /* If set, allow decapsulation of IPinGREinIP without a key. */ 8020 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE BIT(1) 8021 /* If set, allow decapsulation of IPinGREinIP with a key. */ 8022 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY BIT(2) 8023 8024 /* reg_rtdp_ipip_type_check 8025 * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to 8026 * these configurations then trap_id is IPIP_DECAP_ERROR. 8027 * Access: RW 8028 */ 8029 MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3); 8030 8031 /* reg_rtdp_ipip_gre_key_check 8032 * Whether GRE key should be checked. When check is enabled: 8033 * - A packet received as IPinIP (without GRE) will always pass. 8034 * - A packet received as IPinGREinIP without a key will not pass the check. 8035 * - A packet received as IPinGREinIP with a key will pass the check only if the 8036 * key in the packet is equal to expected_gre_key. 8037 * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR. 8038 * Access: RW 8039 */ 8040 MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1); 8041 8042 /* reg_rtdp_ipip_ipv4_usip 8043 * Underlay IPv4 address for ipv4 source address check. 8044 * Reserved when sip_check is not '1'. 8045 * Access: RW 8046 */ 8047 MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32); 8048 8049 /* reg_rtdp_ipip_ipv6_usip_ptr 8050 * This field is valid when sip_check is "sipv6 check explicitly". This is a 8051 * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index 8052 * is to the KVD linear. 8053 * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6. 8054 * Access: RW 8055 */ 8056 MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24); 8057 8058 /* reg_rtdp_ipip_expected_gre_key 8059 * GRE key for checking. 8060 * Reserved when gre_key_check is '0'. 8061 * Access: RW 8062 */ 8063 MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32); 8064 8065 static inline void mlxsw_reg_rtdp_pack(char *payload, 8066 enum mlxsw_reg_rtdp_type type, 8067 u32 tunnel_index) 8068 { 8069 MLXSW_REG_ZERO(rtdp, payload); 8070 mlxsw_reg_rtdp_type_set(payload, type); 8071 mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index); 8072 } 8073 8074 static inline void 8075 mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif, 8076 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 8077 unsigned int type_check, bool gre_key_check, 8078 u32 ipv4_usip, u32 expected_gre_key) 8079 { 8080 mlxsw_reg_rtdp_ipip_irif_set(payload, irif); 8081 mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check); 8082 mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check); 8083 mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check); 8084 mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip); 8085 mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key); 8086 } 8087 8088 /* RIGR-V2 - Router Interface Group Register Version 2 8089 * --------------------------------------------------- 8090 * The RIGR_V2 register is used to add, remove and query egress interface list 8091 * of a multicast forwarding entry. 8092 */ 8093 #define MLXSW_REG_RIGR2_ID 0x8023 8094 #define MLXSW_REG_RIGR2_LEN 0xB0 8095 8096 #define MLXSW_REG_RIGR2_MAX_ERIFS 32 8097 8098 MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN); 8099 8100 /* reg_rigr2_rigr_index 8101 * KVD Linear index. 8102 * Access: Index 8103 */ 8104 MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24); 8105 8106 /* reg_rigr2_vnext 8107 * Next RIGR Index is valid. 8108 * Access: RW 8109 */ 8110 MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1); 8111 8112 /* reg_rigr2_next_rigr_index 8113 * Next RIGR Index. The index is to the KVD linear. 8114 * Reserved when vnxet = '0'. 8115 * Access: RW 8116 */ 8117 MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24); 8118 8119 /* reg_rigr2_vrmid 8120 * RMID Index is valid. 8121 * Access: RW 8122 */ 8123 MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1); 8124 8125 /* reg_rigr2_rmid_index 8126 * RMID Index. 8127 * Range 0 .. max_mid - 1 8128 * Reserved when vrmid = '0'. 8129 * The index is to the Port Group Table (PGT) 8130 * Access: RW 8131 */ 8132 MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16); 8133 8134 /* reg_rigr2_erif_entry_v 8135 * Egress Router Interface is valid. 8136 * Note that low-entries must be set if high-entries are set. For 8137 * example: if erif_entry[2].v is set then erif_entry[1].v and 8138 * erif_entry[0].v must be set. 8139 * Index can be from 0 to cap_mc_erif_list_entries-1 8140 * Access: RW 8141 */ 8142 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false); 8143 8144 /* reg_rigr2_erif_entry_erif 8145 * Egress Router Interface. 8146 * Valid range is from 0 to cap_max_router_interfaces - 1 8147 * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1 8148 * Access: RW 8149 */ 8150 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false); 8151 8152 static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index, 8153 bool vnext, u32 next_rigr_index) 8154 { 8155 MLXSW_REG_ZERO(rigr2, payload); 8156 mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index); 8157 mlxsw_reg_rigr2_vnext_set(payload, vnext); 8158 mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index); 8159 mlxsw_reg_rigr2_vrmid_set(payload, 0); 8160 mlxsw_reg_rigr2_rmid_index_set(payload, 0); 8161 } 8162 8163 static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index, 8164 bool v, u16 erif) 8165 { 8166 mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v); 8167 mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif); 8168 } 8169 8170 /* RECR-V2 - Router ECMP Configuration Version 2 Register 8171 * ------------------------------------------------------ 8172 */ 8173 #define MLXSW_REG_RECR2_ID 0x8025 8174 #define MLXSW_REG_RECR2_LEN 0x38 8175 8176 MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN); 8177 8178 /* reg_recr2_pp 8179 * Per-port configuration 8180 * Access: Index 8181 */ 8182 MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1); 8183 8184 /* reg_recr2_sh 8185 * Symmetric hash 8186 * Access: RW 8187 */ 8188 MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1); 8189 8190 /* reg_recr2_seed 8191 * Seed 8192 * Access: RW 8193 */ 8194 MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32); 8195 8196 enum { 8197 /* Enable IPv4 fields if packet is not TCP and not UDP */ 8198 MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP = 3, 8199 /* Enable IPv4 fields if packet is TCP or UDP */ 8200 MLXSW_REG_RECR2_IPV4_EN_TCP_UDP = 4, 8201 /* Enable IPv6 fields if packet is not TCP and not UDP */ 8202 MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP = 5, 8203 /* Enable IPv6 fields if packet is TCP or UDP */ 8204 MLXSW_REG_RECR2_IPV6_EN_TCP_UDP = 6, 8205 /* Enable TCP/UDP header fields if packet is IPv4 */ 8206 MLXSW_REG_RECR2_TCP_UDP_EN_IPV4 = 7, 8207 /* Enable TCP/UDP header fields if packet is IPv6 */ 8208 MLXSW_REG_RECR2_TCP_UDP_EN_IPV6 = 8, 8209 }; 8210 8211 /* reg_recr2_outer_header_enables 8212 * Bit mask where each bit enables a specific layer to be included in 8213 * the hash calculation. 8214 * Access: RW 8215 */ 8216 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1); 8217 8218 enum { 8219 /* IPv4 Source IP */ 8220 MLXSW_REG_RECR2_IPV4_SIP0 = 9, 8221 MLXSW_REG_RECR2_IPV4_SIP3 = 12, 8222 /* IPv4 Destination IP */ 8223 MLXSW_REG_RECR2_IPV4_DIP0 = 13, 8224 MLXSW_REG_RECR2_IPV4_DIP3 = 16, 8225 /* IP Protocol */ 8226 MLXSW_REG_RECR2_IPV4_PROTOCOL = 17, 8227 /* IPv6 Source IP */ 8228 MLXSW_REG_RECR2_IPV6_SIP0_7 = 21, 8229 MLXSW_REG_RECR2_IPV6_SIP8 = 29, 8230 MLXSW_REG_RECR2_IPV6_SIP15 = 36, 8231 /* IPv6 Destination IP */ 8232 MLXSW_REG_RECR2_IPV6_DIP0_7 = 37, 8233 MLXSW_REG_RECR2_IPV6_DIP8 = 45, 8234 MLXSW_REG_RECR2_IPV6_DIP15 = 52, 8235 /* IPv6 Next Header */ 8236 MLXSW_REG_RECR2_IPV6_NEXT_HEADER = 53, 8237 /* IPv6 Flow Label */ 8238 MLXSW_REG_RECR2_IPV6_FLOW_LABEL = 57, 8239 /* TCP/UDP Source Port */ 8240 MLXSW_REG_RECR2_TCP_UDP_SPORT = 74, 8241 /* TCP/UDP Destination Port */ 8242 MLXSW_REG_RECR2_TCP_UDP_DPORT = 75, 8243 }; 8244 8245 /* reg_recr2_outer_header_fields_enable 8246 * Packet fields to enable for ECMP hash subject to outer_header_enable. 8247 * Access: RW 8248 */ 8249 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1); 8250 8251 static inline void mlxsw_reg_recr2_ipv4_sip_enable(char *payload) 8252 { 8253 int i; 8254 8255 for (i = MLXSW_REG_RECR2_IPV4_SIP0; i <= MLXSW_REG_RECR2_IPV4_SIP3; i++) 8256 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 8257 true); 8258 } 8259 8260 static inline void mlxsw_reg_recr2_ipv4_dip_enable(char *payload) 8261 { 8262 int i; 8263 8264 for (i = MLXSW_REG_RECR2_IPV4_DIP0; i <= MLXSW_REG_RECR2_IPV4_DIP3; i++) 8265 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 8266 true); 8267 } 8268 8269 static inline void mlxsw_reg_recr2_ipv6_sip_enable(char *payload) 8270 { 8271 int i = MLXSW_REG_RECR2_IPV6_SIP0_7; 8272 8273 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true); 8274 8275 i = MLXSW_REG_RECR2_IPV6_SIP8; 8276 for (; i <= MLXSW_REG_RECR2_IPV6_SIP15; i++) 8277 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 8278 true); 8279 } 8280 8281 static inline void mlxsw_reg_recr2_ipv6_dip_enable(char *payload) 8282 { 8283 int i = MLXSW_REG_RECR2_IPV6_DIP0_7; 8284 8285 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true); 8286 8287 i = MLXSW_REG_RECR2_IPV6_DIP8; 8288 for (; i <= MLXSW_REG_RECR2_IPV6_DIP15; i++) 8289 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 8290 true); 8291 } 8292 8293 static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed) 8294 { 8295 MLXSW_REG_ZERO(recr2, payload); 8296 mlxsw_reg_recr2_pp_set(payload, false); 8297 mlxsw_reg_recr2_sh_set(payload, true); 8298 mlxsw_reg_recr2_seed_set(payload, seed); 8299 } 8300 8301 /* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register 8302 * -------------------------------------------------------------- 8303 * The RMFT_V2 register is used to configure and query the multicast table. 8304 */ 8305 #define MLXSW_REG_RMFT2_ID 0x8027 8306 #define MLXSW_REG_RMFT2_LEN 0x174 8307 8308 MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN); 8309 8310 /* reg_rmft2_v 8311 * Valid 8312 * Access: RW 8313 */ 8314 MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1); 8315 8316 enum mlxsw_reg_rmft2_type { 8317 MLXSW_REG_RMFT2_TYPE_IPV4, 8318 MLXSW_REG_RMFT2_TYPE_IPV6 8319 }; 8320 8321 /* reg_rmft2_type 8322 * Access: Index 8323 */ 8324 MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2); 8325 8326 enum mlxsw_sp_reg_rmft2_op { 8327 /* For Write: 8328 * Write operation. Used to write a new entry to the table. All RW 8329 * fields are relevant for new entry. Activity bit is set for new 8330 * entries - Note write with v (Valid) 0 will delete the entry. 8331 * For Query: 8332 * Read operation 8333 */ 8334 MLXSW_REG_RMFT2_OP_READ_WRITE, 8335 }; 8336 8337 /* reg_rmft2_op 8338 * Operation. 8339 * Access: OP 8340 */ 8341 MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2); 8342 8343 /* reg_rmft2_a 8344 * Activity. Set for new entries. Set if a packet lookup has hit on the specific 8345 * entry. 8346 * Access: RO 8347 */ 8348 MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1); 8349 8350 /* reg_rmft2_offset 8351 * Offset within the multicast forwarding table to write to. 8352 * Access: Index 8353 */ 8354 MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16); 8355 8356 /* reg_rmft2_virtual_router 8357 * Virtual Router ID. Range from 0..cap_max_virtual_routers-1 8358 * Access: RW 8359 */ 8360 MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16); 8361 8362 enum mlxsw_reg_rmft2_irif_mask { 8363 MLXSW_REG_RMFT2_IRIF_MASK_IGNORE, 8364 MLXSW_REG_RMFT2_IRIF_MASK_COMPARE 8365 }; 8366 8367 /* reg_rmft2_irif_mask 8368 * Ingress RIF mask. 8369 * Access: RW 8370 */ 8371 MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1); 8372 8373 /* reg_rmft2_irif 8374 * Ingress RIF index. 8375 * Access: RW 8376 */ 8377 MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16); 8378 8379 /* reg_rmft2_dip{4,6} 8380 * Destination IPv4/6 address 8381 * Access: RW 8382 */ 8383 MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16); 8384 MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32); 8385 8386 /* reg_rmft2_dip{4,6}_mask 8387 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 8388 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 8389 * Access: RW 8390 */ 8391 MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16); 8392 MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32); 8393 8394 /* reg_rmft2_sip{4,6} 8395 * Source IPv4/6 address 8396 * Access: RW 8397 */ 8398 MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16); 8399 MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32); 8400 8401 /* reg_rmft2_sip{4,6}_mask 8402 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 8403 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 8404 * Access: RW 8405 */ 8406 MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16); 8407 MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32); 8408 8409 /* reg_rmft2_flexible_action_set 8410 * ACL action set. The only supported action types in this field and in any 8411 * action-set pointed from here are as follows: 8412 * 00h: ACTION_NULL 8413 * 01h: ACTION_MAC_TTL, only TTL configuration is supported. 8414 * 03h: ACTION_TRAP 8415 * 06h: ACTION_QOS 8416 * 08h: ACTION_POLICING_MONITORING 8417 * 10h: ACTION_ROUTER_MC 8418 * Access: RW 8419 */ 8420 MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80, 8421 MLXSW_REG_FLEX_ACTION_SET_LEN); 8422 8423 static inline void 8424 mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset, 8425 u16 virtual_router, 8426 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 8427 const char *flex_action_set) 8428 { 8429 MLXSW_REG_ZERO(rmft2, payload); 8430 mlxsw_reg_rmft2_v_set(payload, v); 8431 mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE); 8432 mlxsw_reg_rmft2_offset_set(payload, offset); 8433 mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router); 8434 mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask); 8435 mlxsw_reg_rmft2_irif_set(payload, irif); 8436 if (flex_action_set) 8437 mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload, 8438 flex_action_set); 8439 } 8440 8441 static inline void 8442 mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router, 8443 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 8444 u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask, 8445 const char *flexible_action_set) 8446 { 8447 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 8448 irif_mask, irif, flexible_action_set); 8449 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4); 8450 mlxsw_reg_rmft2_dip4_set(payload, dip4); 8451 mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask); 8452 mlxsw_reg_rmft2_sip4_set(payload, sip4); 8453 mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask); 8454 } 8455 8456 static inline void 8457 mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router, 8458 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 8459 struct in6_addr dip6, struct in6_addr dip6_mask, 8460 struct in6_addr sip6, struct in6_addr sip6_mask, 8461 const char *flexible_action_set) 8462 { 8463 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 8464 irif_mask, irif, flexible_action_set); 8465 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6); 8466 mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6); 8467 mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask); 8468 mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6); 8469 mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask); 8470 } 8471 8472 /* Note that XRALXX register position violates the rule of ordering register 8473 * definition by the ID. However, XRALXX pack helpers are using RALXX pack 8474 * helpers, RALXX registers have higher IDs. 8475 */ 8476 8477 /* XRALTA - XM Router Algorithmic LPM Tree Allocation Register 8478 * ----------------------------------------------------------- 8479 * The XRALTA is used to allocate the XLT LPM trees. 8480 * 8481 * This register embeds original RALTA register. 8482 */ 8483 #define MLXSW_REG_XRALTA_ID 0x7811 8484 #define MLXSW_REG_XRALTA_LEN 0x08 8485 #define MLXSW_REG_XRALTA_RALTA_OFFSET 0x04 8486 8487 MLXSW_REG_DEFINE(xralta, MLXSW_REG_XRALTA_ID, MLXSW_REG_XRALTA_LEN); 8488 8489 static inline void mlxsw_reg_xralta_pack(char *payload, bool alloc, 8490 enum mlxsw_reg_ralxx_protocol protocol, 8491 u8 tree_id) 8492 { 8493 char *ralta_payload = payload + MLXSW_REG_XRALTA_RALTA_OFFSET; 8494 8495 MLXSW_REG_ZERO(xralta, payload); 8496 mlxsw_reg_ralta_pack(ralta_payload, alloc, protocol, tree_id); 8497 } 8498 8499 /* XRALST - XM Router Algorithmic LPM Structure Tree Register 8500 * ---------------------------------------------------------- 8501 * The XRALST is used to set and query the structure of an XLT LPM tree. 8502 * 8503 * This register embeds original RALST register. 8504 */ 8505 #define MLXSW_REG_XRALST_ID 0x7812 8506 #define MLXSW_REG_XRALST_LEN 0x108 8507 #define MLXSW_REG_XRALST_RALST_OFFSET 0x04 8508 8509 MLXSW_REG_DEFINE(xralst, MLXSW_REG_XRALST_ID, MLXSW_REG_XRALST_LEN); 8510 8511 static inline void mlxsw_reg_xralst_pack(char *payload, u8 root_bin, u8 tree_id) 8512 { 8513 char *ralst_payload = payload + MLXSW_REG_XRALST_RALST_OFFSET; 8514 8515 MLXSW_REG_ZERO(xralst, payload); 8516 mlxsw_reg_ralst_pack(ralst_payload, root_bin, tree_id); 8517 } 8518 8519 static inline void mlxsw_reg_xralst_bin_pack(char *payload, u8 bin_number, 8520 u8 left_child_bin, 8521 u8 right_child_bin) 8522 { 8523 char *ralst_payload = payload + MLXSW_REG_XRALST_RALST_OFFSET; 8524 8525 mlxsw_reg_ralst_bin_pack(ralst_payload, bin_number, left_child_bin, 8526 right_child_bin); 8527 } 8528 8529 /* XRALTB - XM Router Algorithmic LPM Tree Binding Register 8530 * -------------------------------------------------------- 8531 * The XRALTB register is used to bind virtual router and protocol 8532 * to an allocated LPM tree. 8533 * 8534 * This register embeds original RALTB register. 8535 */ 8536 #define MLXSW_REG_XRALTB_ID 0x7813 8537 #define MLXSW_REG_XRALTB_LEN 0x08 8538 #define MLXSW_REG_XRALTB_RALTB_OFFSET 0x04 8539 8540 MLXSW_REG_DEFINE(xraltb, MLXSW_REG_XRALTB_ID, MLXSW_REG_XRALTB_LEN); 8541 8542 static inline void mlxsw_reg_xraltb_pack(char *payload, u16 virtual_router, 8543 enum mlxsw_reg_ralxx_protocol protocol, 8544 u8 tree_id) 8545 { 8546 char *raltb_payload = payload + MLXSW_REG_XRALTB_RALTB_OFFSET; 8547 8548 MLXSW_REG_ZERO(xraltb, payload); 8549 mlxsw_reg_raltb_pack(raltb_payload, virtual_router, protocol, tree_id); 8550 } 8551 8552 /* MFCR - Management Fan Control Register 8553 * -------------------------------------- 8554 * This register controls the settings of the Fan Speed PWM mechanism. 8555 */ 8556 #define MLXSW_REG_MFCR_ID 0x9001 8557 #define MLXSW_REG_MFCR_LEN 0x08 8558 8559 MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN); 8560 8561 enum mlxsw_reg_mfcr_pwm_frequency { 8562 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00, 8563 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01, 8564 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02, 8565 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40, 8566 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41, 8567 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42, 8568 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43, 8569 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44, 8570 }; 8571 8572 /* reg_mfcr_pwm_frequency 8573 * Controls the frequency of the PWM signal. 8574 * Access: RW 8575 */ 8576 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7); 8577 8578 #define MLXSW_MFCR_TACHOS_MAX 10 8579 8580 /* reg_mfcr_tacho_active 8581 * Indicates which of the tachometer is active (bit per tachometer). 8582 * Access: RO 8583 */ 8584 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX); 8585 8586 #define MLXSW_MFCR_PWMS_MAX 5 8587 8588 /* reg_mfcr_pwm_active 8589 * Indicates which of the PWM control is active (bit per PWM). 8590 * Access: RO 8591 */ 8592 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX); 8593 8594 static inline void 8595 mlxsw_reg_mfcr_pack(char *payload, 8596 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency) 8597 { 8598 MLXSW_REG_ZERO(mfcr, payload); 8599 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency); 8600 } 8601 8602 static inline void 8603 mlxsw_reg_mfcr_unpack(char *payload, 8604 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency, 8605 u16 *p_tacho_active, u8 *p_pwm_active) 8606 { 8607 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload); 8608 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload); 8609 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload); 8610 } 8611 8612 /* MFSC - Management Fan Speed Control Register 8613 * -------------------------------------------- 8614 * This register controls the settings of the Fan Speed PWM mechanism. 8615 */ 8616 #define MLXSW_REG_MFSC_ID 0x9002 8617 #define MLXSW_REG_MFSC_LEN 0x08 8618 8619 MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN); 8620 8621 /* reg_mfsc_pwm 8622 * Fan pwm to control / monitor. 8623 * Access: Index 8624 */ 8625 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3); 8626 8627 /* reg_mfsc_pwm_duty_cycle 8628 * Controls the duty cycle of the PWM. Value range from 0..255 to 8629 * represent duty cycle of 0%...100%. 8630 * Access: RW 8631 */ 8632 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8); 8633 8634 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm, 8635 u8 pwm_duty_cycle) 8636 { 8637 MLXSW_REG_ZERO(mfsc, payload); 8638 mlxsw_reg_mfsc_pwm_set(payload, pwm); 8639 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle); 8640 } 8641 8642 /* MFSM - Management Fan Speed Measurement 8643 * --------------------------------------- 8644 * This register controls the settings of the Tacho measurements and 8645 * enables reading the Tachometer measurements. 8646 */ 8647 #define MLXSW_REG_MFSM_ID 0x9003 8648 #define MLXSW_REG_MFSM_LEN 0x08 8649 8650 MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN); 8651 8652 /* reg_mfsm_tacho 8653 * Fan tachometer index. 8654 * Access: Index 8655 */ 8656 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4); 8657 8658 /* reg_mfsm_rpm 8659 * Fan speed (round per minute). 8660 * Access: RO 8661 */ 8662 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16); 8663 8664 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho) 8665 { 8666 MLXSW_REG_ZERO(mfsm, payload); 8667 mlxsw_reg_mfsm_tacho_set(payload, tacho); 8668 } 8669 8670 /* MFSL - Management Fan Speed Limit Register 8671 * ------------------------------------------ 8672 * The Fan Speed Limit register is used to configure the fan speed 8673 * event / interrupt notification mechanism. Fan speed threshold are 8674 * defined for both under-speed and over-speed. 8675 */ 8676 #define MLXSW_REG_MFSL_ID 0x9004 8677 #define MLXSW_REG_MFSL_LEN 0x0C 8678 8679 MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN); 8680 8681 /* reg_mfsl_tacho 8682 * Fan tachometer index. 8683 * Access: Index 8684 */ 8685 MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4); 8686 8687 /* reg_mfsl_tach_min 8688 * Tachometer minimum value (minimum RPM). 8689 * Access: RW 8690 */ 8691 MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16); 8692 8693 /* reg_mfsl_tach_max 8694 * Tachometer maximum value (maximum RPM). 8695 * Access: RW 8696 */ 8697 MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16); 8698 8699 static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho, 8700 u16 tach_min, u16 tach_max) 8701 { 8702 MLXSW_REG_ZERO(mfsl, payload); 8703 mlxsw_reg_mfsl_tacho_set(payload, tacho); 8704 mlxsw_reg_mfsl_tach_min_set(payload, tach_min); 8705 mlxsw_reg_mfsl_tach_max_set(payload, tach_max); 8706 } 8707 8708 static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho, 8709 u16 *p_tach_min, u16 *p_tach_max) 8710 { 8711 if (p_tach_min) 8712 *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload); 8713 8714 if (p_tach_max) 8715 *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload); 8716 } 8717 8718 /* FORE - Fan Out of Range Event Register 8719 * -------------------------------------- 8720 * This register reports the status of the controlled fans compared to the 8721 * range defined by the MFSL register. 8722 */ 8723 #define MLXSW_REG_FORE_ID 0x9007 8724 #define MLXSW_REG_FORE_LEN 0x0C 8725 8726 MLXSW_REG_DEFINE(fore, MLXSW_REG_FORE_ID, MLXSW_REG_FORE_LEN); 8727 8728 /* fan_under_limit 8729 * Fan speed is below the low limit defined in MFSL register. Each bit relates 8730 * to a single tachometer and indicates the specific tachometer reading is 8731 * below the threshold. 8732 * Access: RO 8733 */ 8734 MLXSW_ITEM32(reg, fore, fan_under_limit, 0x00, 16, 10); 8735 8736 static inline void mlxsw_reg_fore_unpack(char *payload, u8 tacho, 8737 bool *fault) 8738 { 8739 u16 limit; 8740 8741 if (fault) { 8742 limit = mlxsw_reg_fore_fan_under_limit_get(payload); 8743 *fault = limit & BIT(tacho); 8744 } 8745 } 8746 8747 /* MTCAP - Management Temperature Capabilities 8748 * ------------------------------------------- 8749 * This register exposes the capabilities of the device and 8750 * system temperature sensing. 8751 */ 8752 #define MLXSW_REG_MTCAP_ID 0x9009 8753 #define MLXSW_REG_MTCAP_LEN 0x08 8754 8755 MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN); 8756 8757 /* reg_mtcap_sensor_count 8758 * Number of sensors supported by the device. 8759 * This includes the QSFP module sensors (if exists in the QSFP module). 8760 * Access: RO 8761 */ 8762 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7); 8763 8764 /* MTMP - Management Temperature 8765 * ----------------------------- 8766 * This register controls the settings of the temperature measurements 8767 * and enables reading the temperature measurements. Note that temperature 8768 * is in 0.125 degrees Celsius. 8769 */ 8770 #define MLXSW_REG_MTMP_ID 0x900A 8771 #define MLXSW_REG_MTMP_LEN 0x20 8772 8773 MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN); 8774 8775 #define MLXSW_REG_MTMP_MODULE_INDEX_MIN 64 8776 #define MLXSW_REG_MTMP_GBOX_INDEX_MIN 256 8777 /* reg_mtmp_sensor_index 8778 * Sensors index to access. 8779 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially 8780 * (module 0 is mapped to sensor_index 64). 8781 * Access: Index 8782 */ 8783 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 12); 8784 8785 /* Convert to milli degrees Celsius */ 8786 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) ({ typeof(val) v_ = (val); \ 8787 ((v_) >= 0) ? ((v_) * 125) : \ 8788 ((s16)((GENMASK(15, 0) + (v_) + 1) \ 8789 * 125)); }) 8790 8791 /* reg_mtmp_temperature 8792 * Temperature reading from the sensor. Reading is in 0.125 Celsius 8793 * degrees units. 8794 * Access: RO 8795 */ 8796 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16); 8797 8798 /* reg_mtmp_mte 8799 * Max Temperature Enable - enables measuring the max temperature on a sensor. 8800 * Access: RW 8801 */ 8802 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1); 8803 8804 /* reg_mtmp_mtr 8805 * Max Temperature Reset - clears the value of the max temperature register. 8806 * Access: WO 8807 */ 8808 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1); 8809 8810 /* reg_mtmp_max_temperature 8811 * The highest measured temperature from the sensor. 8812 * When the bit mte is cleared, the field max_temperature is reserved. 8813 * Access: RO 8814 */ 8815 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16); 8816 8817 /* reg_mtmp_tee 8818 * Temperature Event Enable. 8819 * 0 - Do not generate event 8820 * 1 - Generate event 8821 * 2 - Generate single event 8822 * Access: RW 8823 */ 8824 8825 enum mlxsw_reg_mtmp_tee { 8826 MLXSW_REG_MTMP_TEE_NO_EVENT, 8827 MLXSW_REG_MTMP_TEE_GENERATE_EVENT, 8828 MLXSW_REG_MTMP_TEE_GENERATE_SINGLE_EVENT, 8829 }; 8830 8831 MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2); 8832 8833 #define MLXSW_REG_MTMP_THRESH_HI 0x348 /* 105 Celsius */ 8834 8835 /* reg_mtmp_temperature_threshold_hi 8836 * High threshold for Temperature Warning Event. In 0.125 Celsius. 8837 * Access: RW 8838 */ 8839 MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16); 8840 8841 #define MLXSW_REG_MTMP_HYSTERESIS_TEMP 0x28 /* 5 Celsius */ 8842 /* reg_mtmp_temperature_threshold_lo 8843 * Low threshold for Temperature Warning Event. In 0.125 Celsius. 8844 * Access: RW 8845 */ 8846 MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16); 8847 8848 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8 8849 8850 /* reg_mtmp_sensor_name 8851 * Sensor Name 8852 * Access: RO 8853 */ 8854 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE); 8855 8856 static inline void mlxsw_reg_mtmp_pack(char *payload, u16 sensor_index, 8857 bool max_temp_enable, 8858 bool max_temp_reset) 8859 { 8860 MLXSW_REG_ZERO(mtmp, payload); 8861 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index); 8862 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable); 8863 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset); 8864 mlxsw_reg_mtmp_temperature_threshold_hi_set(payload, 8865 MLXSW_REG_MTMP_THRESH_HI); 8866 } 8867 8868 static inline void mlxsw_reg_mtmp_unpack(char *payload, int *p_temp, 8869 int *p_max_temp, char *sensor_name) 8870 { 8871 s16 temp; 8872 8873 if (p_temp) { 8874 temp = mlxsw_reg_mtmp_temperature_get(payload); 8875 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 8876 } 8877 if (p_max_temp) { 8878 temp = mlxsw_reg_mtmp_max_temperature_get(payload); 8879 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 8880 } 8881 if (sensor_name) 8882 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name); 8883 } 8884 8885 /* MTWE - Management Temperature Warning Event 8886 * ------------------------------------------- 8887 * This register is used for over temperature warning. 8888 */ 8889 #define MLXSW_REG_MTWE_ID 0x900B 8890 #define MLXSW_REG_MTWE_LEN 0x10 8891 8892 MLXSW_REG_DEFINE(mtwe, MLXSW_REG_MTWE_ID, MLXSW_REG_MTWE_LEN); 8893 8894 /* reg_mtwe_sensor_warning 8895 * Bit vector indicating which of the sensor reading is above threshold. 8896 * Address 00h bit31 is sensor_warning[127]. 8897 * Address 0Ch bit0 is sensor_warning[0]. 8898 * Access: RO 8899 */ 8900 MLXSW_ITEM_BIT_ARRAY(reg, mtwe, sensor_warning, 0x0, 0x10, 1); 8901 8902 /* MTBR - Management Temperature Bulk Register 8903 * ------------------------------------------- 8904 * This register is used for bulk temperature reading. 8905 */ 8906 #define MLXSW_REG_MTBR_ID 0x900F 8907 #define MLXSW_REG_MTBR_BASE_LEN 0x10 /* base length, without records */ 8908 #define MLXSW_REG_MTBR_REC_LEN 0x04 /* record length */ 8909 #define MLXSW_REG_MTBR_REC_MAX_COUNT 47 /* firmware limitation */ 8910 #define MLXSW_REG_MTBR_LEN (MLXSW_REG_MTBR_BASE_LEN + \ 8911 MLXSW_REG_MTBR_REC_LEN * \ 8912 MLXSW_REG_MTBR_REC_MAX_COUNT) 8913 8914 MLXSW_REG_DEFINE(mtbr, MLXSW_REG_MTBR_ID, MLXSW_REG_MTBR_LEN); 8915 8916 /* reg_mtbr_base_sensor_index 8917 * Base sensors index to access (0 - ASIC sensor, 1-63 - ambient sensors, 8918 * 64-127 are mapped to the SFP+/QSFP modules sequentially). 8919 * Access: Index 8920 */ 8921 MLXSW_ITEM32(reg, mtbr, base_sensor_index, 0x00, 0, 12); 8922 8923 /* reg_mtbr_num_rec 8924 * Request: Number of records to read 8925 * Response: Number of records read 8926 * See above description for more details. 8927 * Range 1..255 8928 * Access: RW 8929 */ 8930 MLXSW_ITEM32(reg, mtbr, num_rec, 0x04, 0, 8); 8931 8932 /* reg_mtbr_rec_max_temp 8933 * The highest measured temperature from the sensor. 8934 * When the bit mte is cleared, the field max_temperature is reserved. 8935 * Access: RO 8936 */ 8937 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_max_temp, MLXSW_REG_MTBR_BASE_LEN, 16, 8938 16, MLXSW_REG_MTBR_REC_LEN, 0x00, false); 8939 8940 /* reg_mtbr_rec_temp 8941 * Temperature reading from the sensor. Reading is in 0..125 Celsius 8942 * degrees units. 8943 * Access: RO 8944 */ 8945 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_temp, MLXSW_REG_MTBR_BASE_LEN, 0, 16, 8946 MLXSW_REG_MTBR_REC_LEN, 0x00, false); 8947 8948 static inline void mlxsw_reg_mtbr_pack(char *payload, u16 base_sensor_index, 8949 u8 num_rec) 8950 { 8951 MLXSW_REG_ZERO(mtbr, payload); 8952 mlxsw_reg_mtbr_base_sensor_index_set(payload, base_sensor_index); 8953 mlxsw_reg_mtbr_num_rec_set(payload, num_rec); 8954 } 8955 8956 /* Error codes from temperatute reading */ 8957 enum mlxsw_reg_mtbr_temp_status { 8958 MLXSW_REG_MTBR_NO_CONN = 0x8000, 8959 MLXSW_REG_MTBR_NO_TEMP_SENS = 0x8001, 8960 MLXSW_REG_MTBR_INDEX_NA = 0x8002, 8961 MLXSW_REG_MTBR_BAD_SENS_INFO = 0x8003, 8962 }; 8963 8964 /* Base index for reading modules temperature */ 8965 #define MLXSW_REG_MTBR_BASE_MODULE_INDEX 64 8966 8967 static inline void mlxsw_reg_mtbr_temp_unpack(char *payload, int rec_ind, 8968 u16 *p_temp, u16 *p_max_temp) 8969 { 8970 if (p_temp) 8971 *p_temp = mlxsw_reg_mtbr_rec_temp_get(payload, rec_ind); 8972 if (p_max_temp) 8973 *p_max_temp = mlxsw_reg_mtbr_rec_max_temp_get(payload, rec_ind); 8974 } 8975 8976 /* MCIA - Management Cable Info Access 8977 * ----------------------------------- 8978 * MCIA register is used to access the SFP+ and QSFP connector's EPROM. 8979 */ 8980 8981 #define MLXSW_REG_MCIA_ID 0x9014 8982 #define MLXSW_REG_MCIA_LEN 0x40 8983 8984 MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN); 8985 8986 /* reg_mcia_l 8987 * Lock bit. Setting this bit will lock the access to the specific 8988 * cable. Used for updating a full page in a cable EPROM. Any access 8989 * other then subsequence writes will fail while the port is locked. 8990 * Access: RW 8991 */ 8992 MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1); 8993 8994 /* reg_mcia_module 8995 * Module number. 8996 * Access: Index 8997 */ 8998 MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8); 8999 9000 /* reg_mcia_status 9001 * Module status. 9002 * Access: RO 9003 */ 9004 MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8); 9005 9006 /* reg_mcia_i2c_device_address 9007 * I2C device address. 9008 * Access: RW 9009 */ 9010 MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8); 9011 9012 /* reg_mcia_page_number 9013 * Page number. 9014 * Access: RW 9015 */ 9016 MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8); 9017 9018 /* reg_mcia_device_address 9019 * Device address. 9020 * Access: RW 9021 */ 9022 MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16); 9023 9024 /* reg_mcia_size 9025 * Number of bytes to read/write (up to 48 bytes). 9026 * Access: RW 9027 */ 9028 MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16); 9029 9030 #define MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH 256 9031 #define MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH 128 9032 #define MLXSW_REG_MCIA_EEPROM_SIZE 48 9033 #define MLXSW_REG_MCIA_I2C_ADDR_LOW 0x50 9034 #define MLXSW_REG_MCIA_I2C_ADDR_HIGH 0x51 9035 #define MLXSW_REG_MCIA_PAGE0_LO_OFF 0xa0 9036 #define MLXSW_REG_MCIA_TH_ITEM_SIZE 2 9037 #define MLXSW_REG_MCIA_TH_PAGE_NUM 3 9038 #define MLXSW_REG_MCIA_TH_PAGE_CMIS_NUM 2 9039 #define MLXSW_REG_MCIA_PAGE0_LO 0 9040 #define MLXSW_REG_MCIA_TH_PAGE_OFF 0x80 9041 #define MLXSW_REG_MCIA_EEPROM_CMIS_FLAT_MEMORY BIT(7) 9042 9043 enum mlxsw_reg_mcia_eeprom_module_info_rev_id { 9044 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00, 9045 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01, 9046 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03, 9047 }; 9048 9049 enum mlxsw_reg_mcia_eeprom_module_info_id { 9050 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_SFP = 0x03, 9051 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP = 0x0C, 9052 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D, 9053 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11, 9054 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_DD = 0x18, 9055 }; 9056 9057 enum mlxsw_reg_mcia_eeprom_module_info { 9058 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID, 9059 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID, 9060 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_TYPE_ID, 9061 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_SIZE, 9062 }; 9063 9064 /* reg_mcia_eeprom 9065 * Bytes to read/write. 9066 * Access: RW 9067 */ 9068 MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_REG_MCIA_EEPROM_SIZE); 9069 9070 /* This is used to access the optional upper pages (1-3) in the QSFP+ 9071 * memory map. Page 1 is available on offset 256 through 383, page 2 - 9072 * on offset 384 through 511, page 3 - on offset 512 through 639. 9073 */ 9074 #define MLXSW_REG_MCIA_PAGE_GET(off) (((off) - \ 9075 MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH) / \ 9076 MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH + 1) 9077 9078 static inline void mlxsw_reg_mcia_pack(char *payload, u8 module, u8 lock, 9079 u8 page_number, u16 device_addr, 9080 u8 size, u8 i2c_device_addr) 9081 { 9082 MLXSW_REG_ZERO(mcia, payload); 9083 mlxsw_reg_mcia_module_set(payload, module); 9084 mlxsw_reg_mcia_l_set(payload, lock); 9085 mlxsw_reg_mcia_page_number_set(payload, page_number); 9086 mlxsw_reg_mcia_device_address_set(payload, device_addr); 9087 mlxsw_reg_mcia_size_set(payload, size); 9088 mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr); 9089 } 9090 9091 /* MPAT - Monitoring Port Analyzer Table 9092 * ------------------------------------- 9093 * MPAT Register is used to query and configure the Switch PortAnalyzer Table. 9094 * For an enabled analyzer, all fields except e (enable) cannot be modified. 9095 */ 9096 #define MLXSW_REG_MPAT_ID 0x901A 9097 #define MLXSW_REG_MPAT_LEN 0x78 9098 9099 MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN); 9100 9101 /* reg_mpat_pa_id 9102 * Port Analyzer ID. 9103 * Access: Index 9104 */ 9105 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4); 9106 9107 /* reg_mpat_session_id 9108 * Mirror Session ID. 9109 * Used for MIRROR_SESSION<i> trap. 9110 * Access: RW 9111 */ 9112 MLXSW_ITEM32(reg, mpat, session_id, 0x00, 24, 4); 9113 9114 /* reg_mpat_system_port 9115 * A unique port identifier for the final destination of the packet. 9116 * Access: RW 9117 */ 9118 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16); 9119 9120 /* reg_mpat_e 9121 * Enable. Indicating the Port Analyzer is enabled. 9122 * Access: RW 9123 */ 9124 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1); 9125 9126 /* reg_mpat_qos 9127 * Quality Of Service Mode. 9128 * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation 9129 * PCP, DEI, DSCP or VL) are configured. 9130 * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the 9131 * same as in the original packet that has triggered the mirroring. For 9132 * SPAN also the pcp,dei are maintained. 9133 * Access: RW 9134 */ 9135 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1); 9136 9137 /* reg_mpat_be 9138 * Best effort mode. Indicates mirroring traffic should not cause packet 9139 * drop or back pressure, but will discard the mirrored packets. Mirrored 9140 * packets will be forwarded on a best effort manner. 9141 * 0: Do not discard mirrored packets 9142 * 1: Discard mirrored packets if causing congestion 9143 * Access: RW 9144 */ 9145 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1); 9146 9147 enum mlxsw_reg_mpat_span_type { 9148 /* Local SPAN Ethernet. 9149 * The original packet is not encapsulated. 9150 */ 9151 MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0, 9152 9153 /* Remote SPAN Ethernet VLAN. 9154 * The packet is forwarded to the monitoring port on the monitoring 9155 * VLAN. 9156 */ 9157 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1, 9158 9159 /* Encapsulated Remote SPAN Ethernet L3 GRE. 9160 * The packet is encapsulated with GRE header. 9161 */ 9162 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3, 9163 }; 9164 9165 /* reg_mpat_span_type 9166 * SPAN type. 9167 * Access: RW 9168 */ 9169 MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4); 9170 9171 /* reg_mpat_pide 9172 * Policer enable. 9173 * Access: RW 9174 */ 9175 MLXSW_ITEM32(reg, mpat, pide, 0x0C, 15, 1); 9176 9177 /* reg_mpat_pid 9178 * Policer ID. 9179 * Access: RW 9180 */ 9181 MLXSW_ITEM32(reg, mpat, pid, 0x0C, 0, 14); 9182 9183 /* Remote SPAN - Ethernet VLAN 9184 * - - - - - - - - - - - - - - 9185 */ 9186 9187 /* reg_mpat_eth_rspan_vid 9188 * Encapsulation header VLAN ID. 9189 * Access: RW 9190 */ 9191 MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12); 9192 9193 /* Encapsulated Remote SPAN - Ethernet L2 9194 * - - - - - - - - - - - - - - - - - - - 9195 */ 9196 9197 enum mlxsw_reg_mpat_eth_rspan_version { 9198 MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15, 9199 }; 9200 9201 /* reg_mpat_eth_rspan_version 9202 * RSPAN mirror header version. 9203 * Access: RW 9204 */ 9205 MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4); 9206 9207 /* reg_mpat_eth_rspan_mac 9208 * Destination MAC address. 9209 * Access: RW 9210 */ 9211 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6); 9212 9213 /* reg_mpat_eth_rspan_tp 9214 * Tag Packet. Indicates whether the mirroring header should be VLAN tagged. 9215 * Access: RW 9216 */ 9217 MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1); 9218 9219 /* Encapsulated Remote SPAN - Ethernet L3 9220 * - - - - - - - - - - - - - - - - - - - 9221 */ 9222 9223 enum mlxsw_reg_mpat_eth_rspan_protocol { 9224 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4, 9225 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6, 9226 }; 9227 9228 /* reg_mpat_eth_rspan_protocol 9229 * SPAN encapsulation protocol. 9230 * Access: RW 9231 */ 9232 MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4); 9233 9234 /* reg_mpat_eth_rspan_ttl 9235 * Encapsulation header Time-to-Live/HopLimit. 9236 * Access: RW 9237 */ 9238 MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8); 9239 9240 /* reg_mpat_eth_rspan_smac 9241 * Source MAC address 9242 * Access: RW 9243 */ 9244 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6); 9245 9246 /* reg_mpat_eth_rspan_dip* 9247 * Destination IP address. The IP version is configured by protocol. 9248 * Access: RW 9249 */ 9250 MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32); 9251 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16); 9252 9253 /* reg_mpat_eth_rspan_sip* 9254 * Source IP address. The IP version is configured by protocol. 9255 * Access: RW 9256 */ 9257 MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32); 9258 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16); 9259 9260 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id, 9261 u16 system_port, bool e, 9262 enum mlxsw_reg_mpat_span_type span_type) 9263 { 9264 MLXSW_REG_ZERO(mpat, payload); 9265 mlxsw_reg_mpat_pa_id_set(payload, pa_id); 9266 mlxsw_reg_mpat_system_port_set(payload, system_port); 9267 mlxsw_reg_mpat_e_set(payload, e); 9268 mlxsw_reg_mpat_qos_set(payload, 1); 9269 mlxsw_reg_mpat_be_set(payload, 1); 9270 mlxsw_reg_mpat_span_type_set(payload, span_type); 9271 } 9272 9273 static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid) 9274 { 9275 mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid); 9276 } 9277 9278 static inline void 9279 mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload, 9280 enum mlxsw_reg_mpat_eth_rspan_version version, 9281 const char *mac, 9282 bool tp) 9283 { 9284 mlxsw_reg_mpat_eth_rspan_version_set(payload, version); 9285 mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac); 9286 mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp); 9287 } 9288 9289 static inline void 9290 mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl, 9291 const char *smac, 9292 u32 sip, u32 dip) 9293 { 9294 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 9295 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 9296 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 9297 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4); 9298 mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip); 9299 mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip); 9300 } 9301 9302 static inline void 9303 mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl, 9304 const char *smac, 9305 struct in6_addr sip, struct in6_addr dip) 9306 { 9307 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 9308 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 9309 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 9310 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6); 9311 mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip); 9312 mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip); 9313 } 9314 9315 /* MPAR - Monitoring Port Analyzer Register 9316 * ---------------------------------------- 9317 * MPAR register is used to query and configure the port analyzer port mirroring 9318 * properties. 9319 */ 9320 #define MLXSW_REG_MPAR_ID 0x901B 9321 #define MLXSW_REG_MPAR_LEN 0x0C 9322 9323 MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN); 9324 9325 /* reg_mpar_local_port 9326 * The local port to mirror the packets from. 9327 * Access: Index 9328 */ 9329 MLXSW_ITEM32(reg, mpar, local_port, 0x00, 16, 8); 9330 9331 enum mlxsw_reg_mpar_i_e { 9332 MLXSW_REG_MPAR_TYPE_EGRESS, 9333 MLXSW_REG_MPAR_TYPE_INGRESS, 9334 }; 9335 9336 /* reg_mpar_i_e 9337 * Ingress/Egress 9338 * Access: Index 9339 */ 9340 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4); 9341 9342 /* reg_mpar_enable 9343 * Enable mirroring 9344 * By default, port mirroring is disabled for all ports. 9345 * Access: RW 9346 */ 9347 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1); 9348 9349 /* reg_mpar_pa_id 9350 * Port Analyzer ID. 9351 * Access: RW 9352 */ 9353 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4); 9354 9355 static inline void mlxsw_reg_mpar_pack(char *payload, u8 local_port, 9356 enum mlxsw_reg_mpar_i_e i_e, 9357 bool enable, u8 pa_id) 9358 { 9359 MLXSW_REG_ZERO(mpar, payload); 9360 mlxsw_reg_mpar_local_port_set(payload, local_port); 9361 mlxsw_reg_mpar_enable_set(payload, enable); 9362 mlxsw_reg_mpar_i_e_set(payload, i_e); 9363 mlxsw_reg_mpar_pa_id_set(payload, pa_id); 9364 } 9365 9366 /* MGIR - Management General Information Register 9367 * ---------------------------------------------- 9368 * MGIR register allows software to query the hardware and firmware general 9369 * information. 9370 */ 9371 #define MLXSW_REG_MGIR_ID 0x9020 9372 #define MLXSW_REG_MGIR_LEN 0x9C 9373 9374 MLXSW_REG_DEFINE(mgir, MLXSW_REG_MGIR_ID, MLXSW_REG_MGIR_LEN); 9375 9376 /* reg_mgir_hw_info_device_hw_revision 9377 * Access: RO 9378 */ 9379 MLXSW_ITEM32(reg, mgir, hw_info_device_hw_revision, 0x0, 16, 16); 9380 9381 #define MLXSW_REG_MGIR_FW_INFO_PSID_SIZE 16 9382 9383 /* reg_mgir_fw_info_psid 9384 * PSID (ASCII string). 9385 * Access: RO 9386 */ 9387 MLXSW_ITEM_BUF(reg, mgir, fw_info_psid, 0x30, MLXSW_REG_MGIR_FW_INFO_PSID_SIZE); 9388 9389 /* reg_mgir_fw_info_extended_major 9390 * Access: RO 9391 */ 9392 MLXSW_ITEM32(reg, mgir, fw_info_extended_major, 0x44, 0, 32); 9393 9394 /* reg_mgir_fw_info_extended_minor 9395 * Access: RO 9396 */ 9397 MLXSW_ITEM32(reg, mgir, fw_info_extended_minor, 0x48, 0, 32); 9398 9399 /* reg_mgir_fw_info_extended_sub_minor 9400 * Access: RO 9401 */ 9402 MLXSW_ITEM32(reg, mgir, fw_info_extended_sub_minor, 0x4C, 0, 32); 9403 9404 static inline void mlxsw_reg_mgir_pack(char *payload) 9405 { 9406 MLXSW_REG_ZERO(mgir, payload); 9407 } 9408 9409 static inline void 9410 mlxsw_reg_mgir_unpack(char *payload, u32 *hw_rev, char *fw_info_psid, 9411 u32 *fw_major, u32 *fw_minor, u32 *fw_sub_minor) 9412 { 9413 *hw_rev = mlxsw_reg_mgir_hw_info_device_hw_revision_get(payload); 9414 mlxsw_reg_mgir_fw_info_psid_memcpy_from(payload, fw_info_psid); 9415 *fw_major = mlxsw_reg_mgir_fw_info_extended_major_get(payload); 9416 *fw_minor = mlxsw_reg_mgir_fw_info_extended_minor_get(payload); 9417 *fw_sub_minor = mlxsw_reg_mgir_fw_info_extended_sub_minor_get(payload); 9418 } 9419 9420 /* MRSR - Management Reset and Shutdown Register 9421 * --------------------------------------------- 9422 * MRSR register is used to reset or shutdown the switch or 9423 * the entire system (when applicable). 9424 */ 9425 #define MLXSW_REG_MRSR_ID 0x9023 9426 #define MLXSW_REG_MRSR_LEN 0x08 9427 9428 MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN); 9429 9430 /* reg_mrsr_command 9431 * Reset/shutdown command 9432 * 0 - do nothing 9433 * 1 - software reset 9434 * Access: WO 9435 */ 9436 MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4); 9437 9438 static inline void mlxsw_reg_mrsr_pack(char *payload) 9439 { 9440 MLXSW_REG_ZERO(mrsr, payload); 9441 mlxsw_reg_mrsr_command_set(payload, 1); 9442 } 9443 9444 /* MLCR - Management LED Control Register 9445 * -------------------------------------- 9446 * Controls the system LEDs. 9447 */ 9448 #define MLXSW_REG_MLCR_ID 0x902B 9449 #define MLXSW_REG_MLCR_LEN 0x0C 9450 9451 MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN); 9452 9453 /* reg_mlcr_local_port 9454 * Local port number. 9455 * Access: RW 9456 */ 9457 MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8); 9458 9459 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF 9460 9461 /* reg_mlcr_beacon_duration 9462 * Duration of the beacon to be active, in seconds. 9463 * 0x0 - Will turn off the beacon. 9464 * 0xFFFF - Will turn on the beacon until explicitly turned off. 9465 * Access: RW 9466 */ 9467 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16); 9468 9469 /* reg_mlcr_beacon_remain 9470 * Remaining duration of the beacon, in seconds. 9471 * 0xFFFF indicates an infinite amount of time. 9472 * Access: RO 9473 */ 9474 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16); 9475 9476 static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port, 9477 bool active) 9478 { 9479 MLXSW_REG_ZERO(mlcr, payload); 9480 mlxsw_reg_mlcr_local_port_set(payload, local_port); 9481 mlxsw_reg_mlcr_beacon_duration_set(payload, active ? 9482 MLXSW_REG_MLCR_DURATION_MAX : 0); 9483 } 9484 9485 /* MTPPS - Management Pulse Per Second Register 9486 * -------------------------------------------- 9487 * This register provides the device PPS capabilities, configure the PPS in and 9488 * out modules and holds the PPS in time stamp. 9489 */ 9490 #define MLXSW_REG_MTPPS_ID 0x9053 9491 #define MLXSW_REG_MTPPS_LEN 0x3C 9492 9493 MLXSW_REG_DEFINE(mtpps, MLXSW_REG_MTPPS_ID, MLXSW_REG_MTPPS_LEN); 9494 9495 /* reg_mtpps_enable 9496 * Enables the PPS functionality the specific pin. 9497 * A boolean variable. 9498 * Access: RW 9499 */ 9500 MLXSW_ITEM32(reg, mtpps, enable, 0x20, 31, 1); 9501 9502 enum mlxsw_reg_mtpps_pin_mode { 9503 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN = 0x2, 9504 }; 9505 9506 /* reg_mtpps_pin_mode 9507 * Pin mode to be used. The mode must comply with the supported modes of the 9508 * requested pin. 9509 * Access: RW 9510 */ 9511 MLXSW_ITEM32(reg, mtpps, pin_mode, 0x20, 8, 4); 9512 9513 #define MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN 7 9514 9515 /* reg_mtpps_pin 9516 * Pin to be configured or queried out of the supported pins. 9517 * Access: Index 9518 */ 9519 MLXSW_ITEM32(reg, mtpps, pin, 0x20, 0, 8); 9520 9521 /* reg_mtpps_time_stamp 9522 * When pin_mode = pps_in, the latched device time when it was triggered from 9523 * the external GPIO pin. 9524 * When pin_mode = pps_out or virtual_pin or pps_out_and_virtual_pin, the target 9525 * time to generate next output signal. 9526 * Time is in units of device clock. 9527 * Access: RW 9528 */ 9529 MLXSW_ITEM64(reg, mtpps, time_stamp, 0x28, 0, 64); 9530 9531 static inline void 9532 mlxsw_reg_mtpps_vpin_pack(char *payload, u64 time_stamp) 9533 { 9534 MLXSW_REG_ZERO(mtpps, payload); 9535 mlxsw_reg_mtpps_pin_set(payload, MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN); 9536 mlxsw_reg_mtpps_pin_mode_set(payload, 9537 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN); 9538 mlxsw_reg_mtpps_enable_set(payload, true); 9539 mlxsw_reg_mtpps_time_stamp_set(payload, time_stamp); 9540 } 9541 9542 /* MTUTC - Management UTC Register 9543 * ------------------------------- 9544 * Configures the HW UTC counter. 9545 */ 9546 #define MLXSW_REG_MTUTC_ID 0x9055 9547 #define MLXSW_REG_MTUTC_LEN 0x1C 9548 9549 MLXSW_REG_DEFINE(mtutc, MLXSW_REG_MTUTC_ID, MLXSW_REG_MTUTC_LEN); 9550 9551 enum mlxsw_reg_mtutc_operation { 9552 MLXSW_REG_MTUTC_OPERATION_SET_TIME_AT_NEXT_SEC = 0, 9553 MLXSW_REG_MTUTC_OPERATION_ADJUST_FREQ = 3, 9554 }; 9555 9556 /* reg_mtutc_operation 9557 * Operation. 9558 * Access: OP 9559 */ 9560 MLXSW_ITEM32(reg, mtutc, operation, 0x00, 0, 4); 9561 9562 /* reg_mtutc_freq_adjustment 9563 * Frequency adjustment: Every PPS the HW frequency will be 9564 * adjusted by this value. Units of HW clock, where HW counts 9565 * 10^9 HW clocks for 1 HW second. 9566 * Access: RW 9567 */ 9568 MLXSW_ITEM32(reg, mtutc, freq_adjustment, 0x04, 0, 32); 9569 9570 /* reg_mtutc_utc_sec 9571 * UTC seconds. 9572 * Access: WO 9573 */ 9574 MLXSW_ITEM32(reg, mtutc, utc_sec, 0x10, 0, 32); 9575 9576 static inline void 9577 mlxsw_reg_mtutc_pack(char *payload, enum mlxsw_reg_mtutc_operation oper, 9578 u32 freq_adj, u32 utc_sec) 9579 { 9580 MLXSW_REG_ZERO(mtutc, payload); 9581 mlxsw_reg_mtutc_operation_set(payload, oper); 9582 mlxsw_reg_mtutc_freq_adjustment_set(payload, freq_adj); 9583 mlxsw_reg_mtutc_utc_sec_set(payload, utc_sec); 9584 } 9585 9586 /* MCQI - Management Component Query Information 9587 * --------------------------------------------- 9588 * This register allows querying information about firmware components. 9589 */ 9590 #define MLXSW_REG_MCQI_ID 0x9061 9591 #define MLXSW_REG_MCQI_BASE_LEN 0x18 9592 #define MLXSW_REG_MCQI_CAP_LEN 0x14 9593 #define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN) 9594 9595 MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN); 9596 9597 /* reg_mcqi_component_index 9598 * Index of the accessed component. 9599 * Access: Index 9600 */ 9601 MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16); 9602 9603 enum mlxfw_reg_mcqi_info_type { 9604 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES, 9605 }; 9606 9607 /* reg_mcqi_info_type 9608 * Component properties set. 9609 * Access: RW 9610 */ 9611 MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5); 9612 9613 /* reg_mcqi_offset 9614 * The requested/returned data offset from the section start, given in bytes. 9615 * Must be DWORD aligned. 9616 * Access: RW 9617 */ 9618 MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32); 9619 9620 /* reg_mcqi_data_size 9621 * The requested/returned data size, given in bytes. If data_size is not DWORD 9622 * aligned, the last bytes are zero padded. 9623 * Access: RW 9624 */ 9625 MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16); 9626 9627 /* reg_mcqi_cap_max_component_size 9628 * Maximum size for this component, given in bytes. 9629 * Access: RO 9630 */ 9631 MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32); 9632 9633 /* reg_mcqi_cap_log_mcda_word_size 9634 * Log 2 of the access word size in bytes. Read and write access must be aligned 9635 * to the word size. Write access must be done for an integer number of words. 9636 * Access: RO 9637 */ 9638 MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4); 9639 9640 /* reg_mcqi_cap_mcda_max_write_size 9641 * Maximal write size for MCDA register 9642 * Access: RO 9643 */ 9644 MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16); 9645 9646 static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index) 9647 { 9648 MLXSW_REG_ZERO(mcqi, payload); 9649 mlxsw_reg_mcqi_component_index_set(payload, component_index); 9650 mlxsw_reg_mcqi_info_type_set(payload, 9651 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES); 9652 mlxsw_reg_mcqi_offset_set(payload, 0); 9653 mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN); 9654 } 9655 9656 static inline void mlxsw_reg_mcqi_unpack(char *payload, 9657 u32 *p_cap_max_component_size, 9658 u8 *p_cap_log_mcda_word_size, 9659 u16 *p_cap_mcda_max_write_size) 9660 { 9661 *p_cap_max_component_size = 9662 mlxsw_reg_mcqi_cap_max_component_size_get(payload); 9663 *p_cap_log_mcda_word_size = 9664 mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload); 9665 *p_cap_mcda_max_write_size = 9666 mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload); 9667 } 9668 9669 /* MCC - Management Component Control 9670 * ---------------------------------- 9671 * Controls the firmware component and updates the FSM. 9672 */ 9673 #define MLXSW_REG_MCC_ID 0x9062 9674 #define MLXSW_REG_MCC_LEN 0x1C 9675 9676 MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN); 9677 9678 enum mlxsw_reg_mcc_instruction { 9679 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01, 9680 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02, 9681 MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03, 9682 MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04, 9683 MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06, 9684 MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08, 9685 }; 9686 9687 /* reg_mcc_instruction 9688 * Command to be executed by the FSM. 9689 * Applicable for write operation only. 9690 * Access: RW 9691 */ 9692 MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8); 9693 9694 /* reg_mcc_component_index 9695 * Index of the accessed component. Applicable only for commands that 9696 * refer to components. Otherwise, this field is reserved. 9697 * Access: Index 9698 */ 9699 MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16); 9700 9701 /* reg_mcc_update_handle 9702 * Token representing the current flow executed by the FSM. 9703 * Access: WO 9704 */ 9705 MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24); 9706 9707 /* reg_mcc_error_code 9708 * Indicates the successful completion of the instruction, or the reason it 9709 * failed 9710 * Access: RO 9711 */ 9712 MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8); 9713 9714 /* reg_mcc_control_state 9715 * Current FSM state 9716 * Access: RO 9717 */ 9718 MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4); 9719 9720 /* reg_mcc_component_size 9721 * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying 9722 * the size may shorten the update time. Value 0x0 means that size is 9723 * unspecified. 9724 * Access: WO 9725 */ 9726 MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32); 9727 9728 static inline void mlxsw_reg_mcc_pack(char *payload, 9729 enum mlxsw_reg_mcc_instruction instr, 9730 u16 component_index, u32 update_handle, 9731 u32 component_size) 9732 { 9733 MLXSW_REG_ZERO(mcc, payload); 9734 mlxsw_reg_mcc_instruction_set(payload, instr); 9735 mlxsw_reg_mcc_component_index_set(payload, component_index); 9736 mlxsw_reg_mcc_update_handle_set(payload, update_handle); 9737 mlxsw_reg_mcc_component_size_set(payload, component_size); 9738 } 9739 9740 static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle, 9741 u8 *p_error_code, u8 *p_control_state) 9742 { 9743 if (p_update_handle) 9744 *p_update_handle = mlxsw_reg_mcc_update_handle_get(payload); 9745 if (p_error_code) 9746 *p_error_code = mlxsw_reg_mcc_error_code_get(payload); 9747 if (p_control_state) 9748 *p_control_state = mlxsw_reg_mcc_control_state_get(payload); 9749 } 9750 9751 /* MCDA - Management Component Data Access 9752 * --------------------------------------- 9753 * This register allows reading and writing a firmware component. 9754 */ 9755 #define MLXSW_REG_MCDA_ID 0x9063 9756 #define MLXSW_REG_MCDA_BASE_LEN 0x10 9757 #define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80 9758 #define MLXSW_REG_MCDA_LEN \ 9759 (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN) 9760 9761 MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN); 9762 9763 /* reg_mcda_update_handle 9764 * Token representing the current flow executed by the FSM. 9765 * Access: RW 9766 */ 9767 MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24); 9768 9769 /* reg_mcda_offset 9770 * Offset of accessed address relative to component start. Accesses must be in 9771 * accordance to log_mcda_word_size in MCQI reg. 9772 * Access: RW 9773 */ 9774 MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32); 9775 9776 /* reg_mcda_size 9777 * Size of the data accessed, given in bytes. 9778 * Access: RW 9779 */ 9780 MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16); 9781 9782 /* reg_mcda_data 9783 * Data block accessed. 9784 * Access: RW 9785 */ 9786 MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false); 9787 9788 static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle, 9789 u32 offset, u16 size, u8 *data) 9790 { 9791 int i; 9792 9793 MLXSW_REG_ZERO(mcda, payload); 9794 mlxsw_reg_mcda_update_handle_set(payload, update_handle); 9795 mlxsw_reg_mcda_offset_set(payload, offset); 9796 mlxsw_reg_mcda_size_set(payload, size); 9797 9798 for (i = 0; i < size / 4; i++) 9799 mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]); 9800 } 9801 9802 /* MPSC - Monitoring Packet Sampling Configuration Register 9803 * -------------------------------------------------------- 9804 * MPSC Register is used to configure the Packet Sampling mechanism. 9805 */ 9806 #define MLXSW_REG_MPSC_ID 0x9080 9807 #define MLXSW_REG_MPSC_LEN 0x1C 9808 9809 MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN); 9810 9811 /* reg_mpsc_local_port 9812 * Local port number 9813 * Not supported for CPU port 9814 * Access: Index 9815 */ 9816 MLXSW_ITEM32(reg, mpsc, local_port, 0x00, 16, 8); 9817 9818 /* reg_mpsc_e 9819 * Enable sampling on port local_port 9820 * Access: RW 9821 */ 9822 MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1); 9823 9824 #define MLXSW_REG_MPSC_RATE_MAX 3500000000UL 9825 9826 /* reg_mpsc_rate 9827 * Sampling rate = 1 out of rate packets (with randomization around 9828 * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX 9829 * Access: RW 9830 */ 9831 MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32); 9832 9833 static inline void mlxsw_reg_mpsc_pack(char *payload, u8 local_port, bool e, 9834 u32 rate) 9835 { 9836 MLXSW_REG_ZERO(mpsc, payload); 9837 mlxsw_reg_mpsc_local_port_set(payload, local_port); 9838 mlxsw_reg_mpsc_e_set(payload, e); 9839 mlxsw_reg_mpsc_rate_set(payload, rate); 9840 } 9841 9842 /* MGPC - Monitoring General Purpose Counter Set Register 9843 * The MGPC register retrieves and sets the General Purpose Counter Set. 9844 */ 9845 #define MLXSW_REG_MGPC_ID 0x9081 9846 #define MLXSW_REG_MGPC_LEN 0x18 9847 9848 MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN); 9849 9850 /* reg_mgpc_counter_set_type 9851 * Counter set type. 9852 * Access: OP 9853 */ 9854 MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8); 9855 9856 /* reg_mgpc_counter_index 9857 * Counter index. 9858 * Access: Index 9859 */ 9860 MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24); 9861 9862 enum mlxsw_reg_mgpc_opcode { 9863 /* Nop */ 9864 MLXSW_REG_MGPC_OPCODE_NOP = 0x00, 9865 /* Clear counters */ 9866 MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08, 9867 }; 9868 9869 /* reg_mgpc_opcode 9870 * Opcode. 9871 * Access: OP 9872 */ 9873 MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4); 9874 9875 /* reg_mgpc_byte_counter 9876 * Byte counter value. 9877 * Access: RW 9878 */ 9879 MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64); 9880 9881 /* reg_mgpc_packet_counter 9882 * Packet counter value. 9883 * Access: RW 9884 */ 9885 MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64); 9886 9887 static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index, 9888 enum mlxsw_reg_mgpc_opcode opcode, 9889 enum mlxsw_reg_flow_counter_set_type set_type) 9890 { 9891 MLXSW_REG_ZERO(mgpc, payload); 9892 mlxsw_reg_mgpc_counter_index_set(payload, counter_index); 9893 mlxsw_reg_mgpc_counter_set_type_set(payload, set_type); 9894 mlxsw_reg_mgpc_opcode_set(payload, opcode); 9895 } 9896 9897 /* MPRS - Monitoring Parsing State Register 9898 * ---------------------------------------- 9899 * The MPRS register is used for setting up the parsing for hash, 9900 * policy-engine and routing. 9901 */ 9902 #define MLXSW_REG_MPRS_ID 0x9083 9903 #define MLXSW_REG_MPRS_LEN 0x14 9904 9905 MLXSW_REG_DEFINE(mprs, MLXSW_REG_MPRS_ID, MLXSW_REG_MPRS_LEN); 9906 9907 /* reg_mprs_parsing_depth 9908 * Minimum parsing depth. 9909 * Need to enlarge parsing depth according to L3, MPLS, tunnels, ACL 9910 * rules, traps, hash, etc. Default is 96 bytes. Reserved when SwitchX-2. 9911 * Access: RW 9912 */ 9913 MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16); 9914 9915 /* reg_mprs_parsing_en 9916 * Parsing enable. 9917 * Bit 0 - Enable parsing of NVE of types VxLAN, VxLAN-GPE, GENEVE and 9918 * NVGRE. Default is enabled. Reserved when SwitchX-2. 9919 * Access: RW 9920 */ 9921 MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16); 9922 9923 /* reg_mprs_vxlan_udp_dport 9924 * VxLAN UDP destination port. 9925 * Used for identifying VxLAN packets and for dport field in 9926 * encapsulation. Default is 4789. 9927 * Access: RW 9928 */ 9929 MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16); 9930 9931 static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth, 9932 u16 vxlan_udp_dport) 9933 { 9934 MLXSW_REG_ZERO(mprs, payload); 9935 mlxsw_reg_mprs_parsing_depth_set(payload, parsing_depth); 9936 mlxsw_reg_mprs_parsing_en_set(payload, true); 9937 mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport); 9938 } 9939 9940 /* MOGCR - Monitoring Global Configuration Register 9941 * ------------------------------------------------ 9942 */ 9943 #define MLXSW_REG_MOGCR_ID 0x9086 9944 #define MLXSW_REG_MOGCR_LEN 0x20 9945 9946 MLXSW_REG_DEFINE(mogcr, MLXSW_REG_MOGCR_ID, MLXSW_REG_MOGCR_LEN); 9947 9948 /* reg_mogcr_ptp_iftc 9949 * PTP Ingress FIFO Trap Clear 9950 * The PTP_ING_FIFO trap provides MTPPTR with clr according 9951 * to this value. Default 0. 9952 * Reserved when IB switches and when SwitchX/-2, Spectrum-2 9953 * Access: RW 9954 */ 9955 MLXSW_ITEM32(reg, mogcr, ptp_iftc, 0x00, 1, 1); 9956 9957 /* reg_mogcr_ptp_eftc 9958 * PTP Egress FIFO Trap Clear 9959 * The PTP_EGR_FIFO trap provides MTPPTR with clr according 9960 * to this value. Default 0. 9961 * Reserved when IB switches and when SwitchX/-2, Spectrum-2 9962 * Access: RW 9963 */ 9964 MLXSW_ITEM32(reg, mogcr, ptp_eftc, 0x00, 0, 1); 9965 9966 /* reg_mogcr_mirroring_pid_base 9967 * Base policer id for mirroring policers. 9968 * Must have an even value (e.g. 1000, not 1001). 9969 * Reserved when SwitchX/-2, Switch-IB/2, Spectrum-1 and Quantum. 9970 * Access: RW 9971 */ 9972 MLXSW_ITEM32(reg, mogcr, mirroring_pid_base, 0x0C, 0, 14); 9973 9974 /* MPAGR - Monitoring Port Analyzer Global Register 9975 * ------------------------------------------------ 9976 * This register is used for global port analyzer configurations. 9977 * Note: This register is not supported by current FW versions for Spectrum-1. 9978 */ 9979 #define MLXSW_REG_MPAGR_ID 0x9089 9980 #define MLXSW_REG_MPAGR_LEN 0x0C 9981 9982 MLXSW_REG_DEFINE(mpagr, MLXSW_REG_MPAGR_ID, MLXSW_REG_MPAGR_LEN); 9983 9984 enum mlxsw_reg_mpagr_trigger { 9985 MLXSW_REG_MPAGR_TRIGGER_EGRESS, 9986 MLXSW_REG_MPAGR_TRIGGER_INGRESS, 9987 MLXSW_REG_MPAGR_TRIGGER_INGRESS_WRED, 9988 MLXSW_REG_MPAGR_TRIGGER_INGRESS_SHARED_BUFFER, 9989 MLXSW_REG_MPAGR_TRIGGER_INGRESS_ING_CONG, 9990 MLXSW_REG_MPAGR_TRIGGER_INGRESS_EGR_CONG, 9991 MLXSW_REG_MPAGR_TRIGGER_EGRESS_ECN, 9992 MLXSW_REG_MPAGR_TRIGGER_EGRESS_HIGH_LATENCY, 9993 }; 9994 9995 /* reg_mpagr_trigger 9996 * Mirror trigger. 9997 * Access: Index 9998 */ 9999 MLXSW_ITEM32(reg, mpagr, trigger, 0x00, 0, 4); 10000 10001 /* reg_mpagr_pa_id 10002 * Port analyzer ID. 10003 * Access: RW 10004 */ 10005 MLXSW_ITEM32(reg, mpagr, pa_id, 0x04, 0, 4); 10006 10007 /* reg_mpagr_probability_rate 10008 * Sampling rate. 10009 * Valid values are: 1 to 3.5*10^9 10010 * Value of 1 means "sample all". Default is 1. 10011 * Access: RW 10012 */ 10013 MLXSW_ITEM32(reg, mpagr, probability_rate, 0x08, 0, 32); 10014 10015 static inline void mlxsw_reg_mpagr_pack(char *payload, 10016 enum mlxsw_reg_mpagr_trigger trigger, 10017 u8 pa_id, u32 probability_rate) 10018 { 10019 MLXSW_REG_ZERO(mpagr, payload); 10020 mlxsw_reg_mpagr_trigger_set(payload, trigger); 10021 mlxsw_reg_mpagr_pa_id_set(payload, pa_id); 10022 mlxsw_reg_mpagr_probability_rate_set(payload, probability_rate); 10023 } 10024 10025 /* MOMTE - Monitoring Mirror Trigger Enable Register 10026 * ------------------------------------------------- 10027 * This register is used to configure the mirror enable for different mirror 10028 * reasons. 10029 */ 10030 #define MLXSW_REG_MOMTE_ID 0x908D 10031 #define MLXSW_REG_MOMTE_LEN 0x10 10032 10033 MLXSW_REG_DEFINE(momte, MLXSW_REG_MOMTE_ID, MLXSW_REG_MOMTE_LEN); 10034 10035 /* reg_momte_local_port 10036 * Local port number. 10037 * Access: Index 10038 */ 10039 MLXSW_ITEM32(reg, momte, local_port, 0x00, 16, 8); 10040 10041 enum mlxsw_reg_momte_type { 10042 MLXSW_REG_MOMTE_TYPE_WRED = 0x20, 10043 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS = 0x31, 10044 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS_DESCRIPTORS = 0x32, 10045 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_EGRESS_PORT = 0x33, 10046 MLXSW_REG_MOMTE_TYPE_ING_CONG = 0x40, 10047 MLXSW_REG_MOMTE_TYPE_EGR_CONG = 0x50, 10048 MLXSW_REG_MOMTE_TYPE_ECN = 0x60, 10049 MLXSW_REG_MOMTE_TYPE_HIGH_LATENCY = 0x70, 10050 }; 10051 10052 /* reg_momte_type 10053 * Type of mirroring. 10054 * Access: Index 10055 */ 10056 MLXSW_ITEM32(reg, momte, type, 0x04, 0, 8); 10057 10058 /* reg_momte_tclass_en 10059 * TClass/PG mirror enable. Each bit represents corresponding tclass. 10060 * 0: disable (default) 10061 * 1: enable 10062 * Access: RW 10063 */ 10064 MLXSW_ITEM_BIT_ARRAY(reg, momte, tclass_en, 0x08, 0x08, 1); 10065 10066 static inline void mlxsw_reg_momte_pack(char *payload, u8 local_port, 10067 enum mlxsw_reg_momte_type type) 10068 { 10069 MLXSW_REG_ZERO(momte, payload); 10070 mlxsw_reg_momte_local_port_set(payload, local_port); 10071 mlxsw_reg_momte_type_set(payload, type); 10072 } 10073 10074 /* MTPPPC - Time Precision Packet Port Configuration 10075 * ------------------------------------------------- 10076 * This register serves for configuration of which PTP messages should be 10077 * timestamped. This is a global configuration, despite the register name. 10078 * 10079 * Reserved when Spectrum-2. 10080 */ 10081 #define MLXSW_REG_MTPPPC_ID 0x9090 10082 #define MLXSW_REG_MTPPPC_LEN 0x28 10083 10084 MLXSW_REG_DEFINE(mtpppc, MLXSW_REG_MTPPPC_ID, MLXSW_REG_MTPPPC_LEN); 10085 10086 /* reg_mtpppc_ing_timestamp_message_type 10087 * Bitwise vector of PTP message types to timestamp at ingress. 10088 * MessageType field as defined by IEEE 1588 10089 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req) 10090 * Default all 0 10091 * Access: RW 10092 */ 10093 MLXSW_ITEM32(reg, mtpppc, ing_timestamp_message_type, 0x08, 0, 16); 10094 10095 /* reg_mtpppc_egr_timestamp_message_type 10096 * Bitwise vector of PTP message types to timestamp at egress. 10097 * MessageType field as defined by IEEE 1588 10098 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req) 10099 * Default all 0 10100 * Access: RW 10101 */ 10102 MLXSW_ITEM32(reg, mtpppc, egr_timestamp_message_type, 0x0C, 0, 16); 10103 10104 static inline void mlxsw_reg_mtpppc_pack(char *payload, u16 ing, u16 egr) 10105 { 10106 MLXSW_REG_ZERO(mtpppc, payload); 10107 mlxsw_reg_mtpppc_ing_timestamp_message_type_set(payload, ing); 10108 mlxsw_reg_mtpppc_egr_timestamp_message_type_set(payload, egr); 10109 } 10110 10111 /* MTPPTR - Time Precision Packet Timestamping Reading 10112 * --------------------------------------------------- 10113 * The MTPPTR is used for reading the per port PTP timestamp FIFO. 10114 * There is a trap for packets which are latched to the timestamp FIFO, thus the 10115 * SW knows which FIFO to read. Note that packets enter the FIFO before been 10116 * trapped. The sequence number is used to synchronize the timestamp FIFO 10117 * entries and the trapped packets. 10118 * Reserved when Spectrum-2. 10119 */ 10120 10121 #define MLXSW_REG_MTPPTR_ID 0x9091 10122 #define MLXSW_REG_MTPPTR_BASE_LEN 0x10 /* base length, without records */ 10123 #define MLXSW_REG_MTPPTR_REC_LEN 0x10 /* record length */ 10124 #define MLXSW_REG_MTPPTR_REC_MAX_COUNT 4 10125 #define MLXSW_REG_MTPPTR_LEN (MLXSW_REG_MTPPTR_BASE_LEN + \ 10126 MLXSW_REG_MTPPTR_REC_LEN * MLXSW_REG_MTPPTR_REC_MAX_COUNT) 10127 10128 MLXSW_REG_DEFINE(mtpptr, MLXSW_REG_MTPPTR_ID, MLXSW_REG_MTPPTR_LEN); 10129 10130 /* reg_mtpptr_local_port 10131 * Not supported for CPU port. 10132 * Access: Index 10133 */ 10134 MLXSW_ITEM32(reg, mtpptr, local_port, 0x00, 16, 8); 10135 10136 enum mlxsw_reg_mtpptr_dir { 10137 MLXSW_REG_MTPPTR_DIR_INGRESS, 10138 MLXSW_REG_MTPPTR_DIR_EGRESS, 10139 }; 10140 10141 /* reg_mtpptr_dir 10142 * Direction. 10143 * Access: Index 10144 */ 10145 MLXSW_ITEM32(reg, mtpptr, dir, 0x00, 0, 1); 10146 10147 /* reg_mtpptr_clr 10148 * Clear the records. 10149 * Access: OP 10150 */ 10151 MLXSW_ITEM32(reg, mtpptr, clr, 0x04, 31, 1); 10152 10153 /* reg_mtpptr_num_rec 10154 * Number of valid records in the response 10155 * Range 0.. cap_ptp_timestamp_fifo 10156 * Access: RO 10157 */ 10158 MLXSW_ITEM32(reg, mtpptr, num_rec, 0x08, 0, 4); 10159 10160 /* reg_mtpptr_rec_message_type 10161 * MessageType field as defined by IEEE 1588 Each bit corresponds to a value 10162 * (e.g. Bit0: Sync, Bit1: Delay_Req) 10163 * Access: RO 10164 */ 10165 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_message_type, 10166 MLXSW_REG_MTPPTR_BASE_LEN, 8, 4, 10167 MLXSW_REG_MTPPTR_REC_LEN, 0, false); 10168 10169 /* reg_mtpptr_rec_domain_number 10170 * DomainNumber field as defined by IEEE 1588 10171 * Access: RO 10172 */ 10173 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_domain_number, 10174 MLXSW_REG_MTPPTR_BASE_LEN, 0, 8, 10175 MLXSW_REG_MTPPTR_REC_LEN, 0, false); 10176 10177 /* reg_mtpptr_rec_sequence_id 10178 * SequenceId field as defined by IEEE 1588 10179 * Access: RO 10180 */ 10181 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_sequence_id, 10182 MLXSW_REG_MTPPTR_BASE_LEN, 0, 16, 10183 MLXSW_REG_MTPPTR_REC_LEN, 0x4, false); 10184 10185 /* reg_mtpptr_rec_timestamp_high 10186 * Timestamp of when the PTP packet has passed through the port Units of PLL 10187 * clock time. 10188 * For Spectrum-1 the PLL clock is 156.25Mhz and PLL clock time is 6.4nSec. 10189 * Access: RO 10190 */ 10191 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_high, 10192 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32, 10193 MLXSW_REG_MTPPTR_REC_LEN, 0x8, false); 10194 10195 /* reg_mtpptr_rec_timestamp_low 10196 * See rec_timestamp_high. 10197 * Access: RO 10198 */ 10199 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_low, 10200 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32, 10201 MLXSW_REG_MTPPTR_REC_LEN, 0xC, false); 10202 10203 static inline void mlxsw_reg_mtpptr_unpack(const char *payload, 10204 unsigned int rec, 10205 u8 *p_message_type, 10206 u8 *p_domain_number, 10207 u16 *p_sequence_id, 10208 u64 *p_timestamp) 10209 { 10210 u32 timestamp_high, timestamp_low; 10211 10212 *p_message_type = mlxsw_reg_mtpptr_rec_message_type_get(payload, rec); 10213 *p_domain_number = mlxsw_reg_mtpptr_rec_domain_number_get(payload, rec); 10214 *p_sequence_id = mlxsw_reg_mtpptr_rec_sequence_id_get(payload, rec); 10215 timestamp_high = mlxsw_reg_mtpptr_rec_timestamp_high_get(payload, rec); 10216 timestamp_low = mlxsw_reg_mtpptr_rec_timestamp_low_get(payload, rec); 10217 *p_timestamp = (u64)timestamp_high << 32 | timestamp_low; 10218 } 10219 10220 /* MTPTPT - Monitoring Precision Time Protocol Trap Register 10221 * --------------------------------------------------------- 10222 * This register is used for configuring under which trap to deliver PTP 10223 * packets depending on type of the packet. 10224 */ 10225 #define MLXSW_REG_MTPTPT_ID 0x9092 10226 #define MLXSW_REG_MTPTPT_LEN 0x08 10227 10228 MLXSW_REG_DEFINE(mtptpt, MLXSW_REG_MTPTPT_ID, MLXSW_REG_MTPTPT_LEN); 10229 10230 enum mlxsw_reg_mtptpt_trap_id { 10231 MLXSW_REG_MTPTPT_TRAP_ID_PTP0, 10232 MLXSW_REG_MTPTPT_TRAP_ID_PTP1, 10233 }; 10234 10235 /* reg_mtptpt_trap_id 10236 * Trap id. 10237 * Access: Index 10238 */ 10239 MLXSW_ITEM32(reg, mtptpt, trap_id, 0x00, 0, 4); 10240 10241 /* reg_mtptpt_message_type 10242 * Bitwise vector of PTP message types to trap. This is a necessary but 10243 * non-sufficient condition since need to enable also per port. See MTPPPC. 10244 * Message types are defined by IEEE 1588 Each bit corresponds to a value (e.g. 10245 * Bit0: Sync, Bit1: Delay_Req) 10246 */ 10247 MLXSW_ITEM32(reg, mtptpt, message_type, 0x04, 0, 16); 10248 10249 static inline void mlxsw_reg_mtptptp_pack(char *payload, 10250 enum mlxsw_reg_mtptpt_trap_id trap_id, 10251 u16 message_type) 10252 { 10253 MLXSW_REG_ZERO(mtptpt, payload); 10254 mlxsw_reg_mtptpt_trap_id_set(payload, trap_id); 10255 mlxsw_reg_mtptpt_message_type_set(payload, message_type); 10256 } 10257 10258 /* MFGD - Monitoring FW General Debug Register 10259 * ------------------------------------------- 10260 */ 10261 #define MLXSW_REG_MFGD_ID 0x90F0 10262 #define MLXSW_REG_MFGD_LEN 0x0C 10263 10264 MLXSW_REG_DEFINE(mfgd, MLXSW_REG_MFGD_ID, MLXSW_REG_MFGD_LEN); 10265 10266 /* reg_mfgd_fw_fatal_event_mode 10267 * 0 - don't check FW fatal (default) 10268 * 1 - check FW fatal - enable MFDE trap 10269 * Access: RW 10270 */ 10271 MLXSW_ITEM32(reg, mfgd, fatal_event_mode, 0x00, 9, 2); 10272 10273 /* reg_mfgd_trigger_test 10274 * Access: WO 10275 */ 10276 MLXSW_ITEM32(reg, mfgd, trigger_test, 0x00, 11, 1); 10277 10278 /* MGPIR - Management General Peripheral Information Register 10279 * ---------------------------------------------------------- 10280 * MGPIR register allows software to query the hardware and 10281 * firmware general information of peripheral entities. 10282 */ 10283 #define MLXSW_REG_MGPIR_ID 0x9100 10284 #define MLXSW_REG_MGPIR_LEN 0xA0 10285 10286 MLXSW_REG_DEFINE(mgpir, MLXSW_REG_MGPIR_ID, MLXSW_REG_MGPIR_LEN); 10287 10288 enum mlxsw_reg_mgpir_device_type { 10289 MLXSW_REG_MGPIR_DEVICE_TYPE_NONE, 10290 MLXSW_REG_MGPIR_DEVICE_TYPE_GEARBOX_DIE, 10291 }; 10292 10293 /* device_type 10294 * Access: RO 10295 */ 10296 MLXSW_ITEM32(reg, mgpir, device_type, 0x00, 24, 4); 10297 10298 /* devices_per_flash 10299 * Number of devices of device_type per flash (can be shared by few devices). 10300 * Access: RO 10301 */ 10302 MLXSW_ITEM32(reg, mgpir, devices_per_flash, 0x00, 16, 8); 10303 10304 /* num_of_devices 10305 * Number of devices of device_type. 10306 * Access: RO 10307 */ 10308 MLXSW_ITEM32(reg, mgpir, num_of_devices, 0x00, 0, 8); 10309 10310 /* num_of_modules 10311 * Number of modules. 10312 * Access: RO 10313 */ 10314 MLXSW_ITEM32(reg, mgpir, num_of_modules, 0x04, 0, 8); 10315 10316 static inline void mlxsw_reg_mgpir_pack(char *payload) 10317 { 10318 MLXSW_REG_ZERO(mgpir, payload); 10319 } 10320 10321 static inline void 10322 mlxsw_reg_mgpir_unpack(char *payload, u8 *num_of_devices, 10323 enum mlxsw_reg_mgpir_device_type *device_type, 10324 u8 *devices_per_flash, u8 *num_of_modules) 10325 { 10326 if (num_of_devices) 10327 *num_of_devices = mlxsw_reg_mgpir_num_of_devices_get(payload); 10328 if (device_type) 10329 *device_type = mlxsw_reg_mgpir_device_type_get(payload); 10330 if (devices_per_flash) 10331 *devices_per_flash = 10332 mlxsw_reg_mgpir_devices_per_flash_get(payload); 10333 if (num_of_modules) 10334 *num_of_modules = mlxsw_reg_mgpir_num_of_modules_get(payload); 10335 } 10336 10337 /* MFDE - Monitoring FW Debug Register 10338 * ----------------------------------- 10339 */ 10340 #define MLXSW_REG_MFDE_ID 0x9200 10341 #define MLXSW_REG_MFDE_LEN 0x18 10342 10343 MLXSW_REG_DEFINE(mfde, MLXSW_REG_MFDE_ID, MLXSW_REG_MFDE_LEN); 10344 10345 /* reg_mfde_irisc_id 10346 * Which irisc triggered the event 10347 * Access: RO 10348 */ 10349 MLXSW_ITEM32(reg, mfde, irisc_id, 0x00, 8, 4); 10350 10351 enum mlxsw_reg_mfde_event_id { 10352 MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO = 1, 10353 /* KVD insertion machine stopped */ 10354 MLXSW_REG_MFDE_EVENT_ID_KVD_IM_STOP, 10355 }; 10356 10357 /* reg_mfde_event_id 10358 * Access: RO 10359 */ 10360 MLXSW_ITEM32(reg, mfde, event_id, 0x00, 0, 8); 10361 10362 enum mlxsw_reg_mfde_method { 10363 MLXSW_REG_MFDE_METHOD_QUERY, 10364 MLXSW_REG_MFDE_METHOD_WRITE, 10365 }; 10366 10367 /* reg_mfde_method 10368 * Access: RO 10369 */ 10370 MLXSW_ITEM32(reg, mfde, method, 0x04, 29, 1); 10371 10372 /* reg_mfde_long_process 10373 * Indicates if the command is in long_process mode. 10374 * Access: RO 10375 */ 10376 MLXSW_ITEM32(reg, mfde, long_process, 0x04, 28, 1); 10377 10378 enum mlxsw_reg_mfde_command_type { 10379 MLXSW_REG_MFDE_COMMAND_TYPE_MAD, 10380 MLXSW_REG_MFDE_COMMAND_TYPE_EMAD, 10381 MLXSW_REG_MFDE_COMMAND_TYPE_CMDIF, 10382 }; 10383 10384 /* reg_mfde_command_type 10385 * Access: RO 10386 */ 10387 MLXSW_ITEM32(reg, mfde, command_type, 0x04, 24, 2); 10388 10389 /* reg_mfde_reg_attr_id 10390 * EMAD - register id, MAD - attibute id 10391 * Access: RO 10392 */ 10393 MLXSW_ITEM32(reg, mfde, reg_attr_id, 0x04, 0, 16); 10394 10395 /* reg_mfde_log_address 10396 * crspace address accessed, which resulted in timeout. 10397 * Valid in case event_id == MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO 10398 * Access: RO 10399 */ 10400 MLXSW_ITEM32(reg, mfde, log_address, 0x10, 0, 32); 10401 10402 /* reg_mfde_log_id 10403 * Which irisc triggered the timeout. 10404 * Valid in case event_id == MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO 10405 * Access: RO 10406 */ 10407 MLXSW_ITEM32(reg, mfde, log_id, 0x14, 0, 4); 10408 10409 /* reg_mfde_pipes_mask 10410 * Bit per kvh pipe. 10411 * Access: RO 10412 */ 10413 MLXSW_ITEM32(reg, mfde, pipes_mask, 0x10, 0, 16); 10414 10415 /* TNGCR - Tunneling NVE General Configuration Register 10416 * ---------------------------------------------------- 10417 * The TNGCR register is used for setting up the NVE Tunneling configuration. 10418 */ 10419 #define MLXSW_REG_TNGCR_ID 0xA001 10420 #define MLXSW_REG_TNGCR_LEN 0x44 10421 10422 MLXSW_REG_DEFINE(tngcr, MLXSW_REG_TNGCR_ID, MLXSW_REG_TNGCR_LEN); 10423 10424 enum mlxsw_reg_tngcr_type { 10425 MLXSW_REG_TNGCR_TYPE_VXLAN, 10426 MLXSW_REG_TNGCR_TYPE_VXLAN_GPE, 10427 MLXSW_REG_TNGCR_TYPE_GENEVE, 10428 MLXSW_REG_TNGCR_TYPE_NVGRE, 10429 }; 10430 10431 /* reg_tngcr_type 10432 * Tunnel type for encapsulation and decapsulation. The types are mutually 10433 * exclusive. 10434 * Note: For Spectrum the NVE parsing must be enabled in MPRS. 10435 * Access: RW 10436 */ 10437 MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4); 10438 10439 /* reg_tngcr_nve_valid 10440 * The VTEP is valid. Allows adding FDB entries for tunnel encapsulation. 10441 * Access: RW 10442 */ 10443 MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1); 10444 10445 /* reg_tngcr_nve_ttl_uc 10446 * The TTL for NVE tunnel encapsulation underlay unicast packets. 10447 * Access: RW 10448 */ 10449 MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8); 10450 10451 /* reg_tngcr_nve_ttl_mc 10452 * The TTL for NVE tunnel encapsulation underlay multicast packets. 10453 * Access: RW 10454 */ 10455 MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8); 10456 10457 enum { 10458 /* Do not copy flow label. Calculate flow label using nve_flh. */ 10459 MLXSW_REG_TNGCR_FL_NO_COPY, 10460 /* Copy flow label from inner packet if packet is IPv6 and 10461 * encapsulation is by IPv6. Otherwise, calculate flow label using 10462 * nve_flh. 10463 */ 10464 MLXSW_REG_TNGCR_FL_COPY, 10465 }; 10466 10467 /* reg_tngcr_nve_flc 10468 * For NVE tunnel encapsulation: Flow label copy from inner packet. 10469 * Access: RW 10470 */ 10471 MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1); 10472 10473 enum { 10474 /* Flow label is static. In Spectrum this means '0'. Spectrum-2 10475 * uses {nve_fl_prefix, nve_fl_suffix}. 10476 */ 10477 MLXSW_REG_TNGCR_FL_NO_HASH, 10478 /* 8 LSBs of the flow label are calculated from ECMP hash of the 10479 * inner packet. 12 MSBs are configured by nve_fl_prefix. 10480 */ 10481 MLXSW_REG_TNGCR_FL_HASH, 10482 }; 10483 10484 /* reg_tngcr_nve_flh 10485 * NVE flow label hash. 10486 * Access: RW 10487 */ 10488 MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1); 10489 10490 /* reg_tngcr_nve_fl_prefix 10491 * NVE flow label prefix. Constant 12 MSBs of the flow label. 10492 * Access: RW 10493 */ 10494 MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12); 10495 10496 /* reg_tngcr_nve_fl_suffix 10497 * NVE flow label suffix. Constant 8 LSBs of the flow label. 10498 * Reserved when nve_flh=1 and for Spectrum. 10499 * Access: RW 10500 */ 10501 MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8); 10502 10503 enum { 10504 /* Source UDP port is fixed (default '0') */ 10505 MLXSW_REG_TNGCR_UDP_SPORT_NO_HASH, 10506 /* Source UDP port is calculated based on hash */ 10507 MLXSW_REG_TNGCR_UDP_SPORT_HASH, 10508 }; 10509 10510 /* reg_tngcr_nve_udp_sport_type 10511 * NVE UDP source port type. 10512 * Spectrum uses LAG hash (SLCRv2). Spectrum-2 uses ECMP hash (RECRv2). 10513 * When the source UDP port is calculated based on hash, then the 8 LSBs 10514 * are calculated from hash the 8 MSBs are configured by 10515 * nve_udp_sport_prefix. 10516 * Access: RW 10517 */ 10518 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1); 10519 10520 /* reg_tngcr_nve_udp_sport_prefix 10521 * NVE UDP source port prefix. Constant 8 MSBs of the UDP source port. 10522 * Reserved when NVE type is NVGRE. 10523 * Access: RW 10524 */ 10525 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8); 10526 10527 /* reg_tngcr_nve_group_size_mc 10528 * The amount of sequential linked lists of MC entries. The first linked 10529 * list is configured by SFD.underlay_mc_ptr. 10530 * Valid values: 1, 2, 4, 8, 16, 32, 64 10531 * The linked list are configured by TNUMT. 10532 * The hash is set by LAG hash. 10533 * Access: RW 10534 */ 10535 MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8); 10536 10537 /* reg_tngcr_nve_group_size_flood 10538 * The amount of sequential linked lists of flooding entries. The first 10539 * linked list is configured by SFMR.nve_tunnel_flood_ptr 10540 * Valid values: 1, 2, 4, 8, 16, 32, 64 10541 * The linked list are configured by TNUMT. 10542 * The hash is set by LAG hash. 10543 * Access: RW 10544 */ 10545 MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8); 10546 10547 /* reg_tngcr_learn_enable 10548 * During decapsulation, whether to learn from NVE port. 10549 * Reserved when Spectrum-2. See TNPC. 10550 * Access: RW 10551 */ 10552 MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1); 10553 10554 /* reg_tngcr_underlay_virtual_router 10555 * Underlay virtual router. 10556 * Reserved when Spectrum-2. 10557 * Access: RW 10558 */ 10559 MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16); 10560 10561 /* reg_tngcr_underlay_rif 10562 * Underlay ingress router interface. RIF type should be loopback generic. 10563 * Reserved when Spectrum. 10564 * Access: RW 10565 */ 10566 MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16); 10567 10568 /* reg_tngcr_usipv4 10569 * Underlay source IPv4 address of the NVE. 10570 * Access: RW 10571 */ 10572 MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32); 10573 10574 /* reg_tngcr_usipv6 10575 * Underlay source IPv6 address of the NVE. For Spectrum, must not be 10576 * modified under traffic of NVE tunneling encapsulation. 10577 * Access: RW 10578 */ 10579 MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16); 10580 10581 static inline void mlxsw_reg_tngcr_pack(char *payload, 10582 enum mlxsw_reg_tngcr_type type, 10583 bool valid, u8 ttl) 10584 { 10585 MLXSW_REG_ZERO(tngcr, payload); 10586 mlxsw_reg_tngcr_type_set(payload, type); 10587 mlxsw_reg_tngcr_nve_valid_set(payload, valid); 10588 mlxsw_reg_tngcr_nve_ttl_uc_set(payload, ttl); 10589 mlxsw_reg_tngcr_nve_ttl_mc_set(payload, ttl); 10590 mlxsw_reg_tngcr_nve_flc_set(payload, MLXSW_REG_TNGCR_FL_NO_COPY); 10591 mlxsw_reg_tngcr_nve_flh_set(payload, 0); 10592 mlxsw_reg_tngcr_nve_udp_sport_type_set(payload, 10593 MLXSW_REG_TNGCR_UDP_SPORT_HASH); 10594 mlxsw_reg_tngcr_nve_udp_sport_prefix_set(payload, 0); 10595 mlxsw_reg_tngcr_nve_group_size_mc_set(payload, 1); 10596 mlxsw_reg_tngcr_nve_group_size_flood_set(payload, 1); 10597 } 10598 10599 /* TNUMT - Tunneling NVE Underlay Multicast Table Register 10600 * ------------------------------------------------------- 10601 * The TNUMT register is for building the underlay MC table. It is used 10602 * for MC, flooding and BC traffic into the NVE tunnel. 10603 */ 10604 #define MLXSW_REG_TNUMT_ID 0xA003 10605 #define MLXSW_REG_TNUMT_LEN 0x20 10606 10607 MLXSW_REG_DEFINE(tnumt, MLXSW_REG_TNUMT_ID, MLXSW_REG_TNUMT_LEN); 10608 10609 enum mlxsw_reg_tnumt_record_type { 10610 MLXSW_REG_TNUMT_RECORD_TYPE_IPV4, 10611 MLXSW_REG_TNUMT_RECORD_TYPE_IPV6, 10612 MLXSW_REG_TNUMT_RECORD_TYPE_LABEL, 10613 }; 10614 10615 /* reg_tnumt_record_type 10616 * Record type. 10617 * Access: RW 10618 */ 10619 MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4); 10620 10621 /* reg_tnumt_tunnel_port 10622 * Tunnel port. 10623 * Access: RW 10624 */ 10625 MLXSW_ITEM32(reg, tnumt, tunnel_port, 0x00, 24, 4); 10626 10627 /* reg_tnumt_underlay_mc_ptr 10628 * Index to the underlay multicast table. 10629 * For Spectrum the index is to the KVD linear. 10630 * Access: Index 10631 */ 10632 MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24); 10633 10634 /* reg_tnumt_vnext 10635 * The next_underlay_mc_ptr is valid. 10636 * Access: RW 10637 */ 10638 MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1); 10639 10640 /* reg_tnumt_next_underlay_mc_ptr 10641 * The next index to the underlay multicast table. 10642 * Access: RW 10643 */ 10644 MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24); 10645 10646 /* reg_tnumt_record_size 10647 * Number of IP addresses in the record. 10648 * Range is 1..cap_max_nve_mc_entries_ipv{4,6} 10649 * Access: RW 10650 */ 10651 MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3); 10652 10653 /* reg_tnumt_udip 10654 * The underlay IPv4 addresses. udip[i] is reserved if i >= size 10655 * Access: RW 10656 */ 10657 MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false); 10658 10659 /* reg_tnumt_udip_ptr 10660 * The pointer to the underlay IPv6 addresses. udip_ptr[i] is reserved if 10661 * i >= size. The IPv6 addresses are configured by RIPS. 10662 * Access: RW 10663 */ 10664 MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false); 10665 10666 static inline void mlxsw_reg_tnumt_pack(char *payload, 10667 enum mlxsw_reg_tnumt_record_type type, 10668 enum mlxsw_reg_tunnel_port tport, 10669 u32 underlay_mc_ptr, bool vnext, 10670 u32 next_underlay_mc_ptr, 10671 u8 record_size) 10672 { 10673 MLXSW_REG_ZERO(tnumt, payload); 10674 mlxsw_reg_tnumt_record_type_set(payload, type); 10675 mlxsw_reg_tnumt_tunnel_port_set(payload, tport); 10676 mlxsw_reg_tnumt_underlay_mc_ptr_set(payload, underlay_mc_ptr); 10677 mlxsw_reg_tnumt_vnext_set(payload, vnext); 10678 mlxsw_reg_tnumt_next_underlay_mc_ptr_set(payload, next_underlay_mc_ptr); 10679 mlxsw_reg_tnumt_record_size_set(payload, record_size); 10680 } 10681 10682 /* TNQCR - Tunneling NVE QoS Configuration Register 10683 * ------------------------------------------------ 10684 * The TNQCR register configures how QoS is set in encapsulation into the 10685 * underlay network. 10686 */ 10687 #define MLXSW_REG_TNQCR_ID 0xA010 10688 #define MLXSW_REG_TNQCR_LEN 0x0C 10689 10690 MLXSW_REG_DEFINE(tnqcr, MLXSW_REG_TNQCR_ID, MLXSW_REG_TNQCR_LEN); 10691 10692 /* reg_tnqcr_enc_set_dscp 10693 * For encapsulation: How to set DSCP field: 10694 * 0 - Copy the DSCP from the overlay (inner) IP header to the underlay 10695 * (outer) IP header. If there is no IP header, use TNQDR.dscp 10696 * 1 - Set the DSCP field as TNQDR.dscp 10697 * Access: RW 10698 */ 10699 MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1); 10700 10701 static inline void mlxsw_reg_tnqcr_pack(char *payload) 10702 { 10703 MLXSW_REG_ZERO(tnqcr, payload); 10704 mlxsw_reg_tnqcr_enc_set_dscp_set(payload, 0); 10705 } 10706 10707 /* TNQDR - Tunneling NVE QoS Default Register 10708 * ------------------------------------------ 10709 * The TNQDR register configures the default QoS settings for NVE 10710 * encapsulation. 10711 */ 10712 #define MLXSW_REG_TNQDR_ID 0xA011 10713 #define MLXSW_REG_TNQDR_LEN 0x08 10714 10715 MLXSW_REG_DEFINE(tnqdr, MLXSW_REG_TNQDR_ID, MLXSW_REG_TNQDR_LEN); 10716 10717 /* reg_tnqdr_local_port 10718 * Local port number (receive port). CPU port is supported. 10719 * Access: Index 10720 */ 10721 MLXSW_ITEM32(reg, tnqdr, local_port, 0x00, 16, 8); 10722 10723 /* reg_tnqdr_dscp 10724 * For encapsulation, the default DSCP. 10725 * Access: RW 10726 */ 10727 MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6); 10728 10729 static inline void mlxsw_reg_tnqdr_pack(char *payload, u8 local_port) 10730 { 10731 MLXSW_REG_ZERO(tnqdr, payload); 10732 mlxsw_reg_tnqdr_local_port_set(payload, local_port); 10733 mlxsw_reg_tnqdr_dscp_set(payload, 0); 10734 } 10735 10736 /* TNEEM - Tunneling NVE Encapsulation ECN Mapping Register 10737 * -------------------------------------------------------- 10738 * The TNEEM register maps ECN of the IP header at the ingress to the 10739 * encapsulation to the ECN of the underlay network. 10740 */ 10741 #define MLXSW_REG_TNEEM_ID 0xA012 10742 #define MLXSW_REG_TNEEM_LEN 0x0C 10743 10744 MLXSW_REG_DEFINE(tneem, MLXSW_REG_TNEEM_ID, MLXSW_REG_TNEEM_LEN); 10745 10746 /* reg_tneem_overlay_ecn 10747 * ECN of the IP header in the overlay network. 10748 * Access: Index 10749 */ 10750 MLXSW_ITEM32(reg, tneem, overlay_ecn, 0x04, 24, 2); 10751 10752 /* reg_tneem_underlay_ecn 10753 * ECN of the IP header in the underlay network. 10754 * Access: RW 10755 */ 10756 MLXSW_ITEM32(reg, tneem, underlay_ecn, 0x04, 16, 2); 10757 10758 static inline void mlxsw_reg_tneem_pack(char *payload, u8 overlay_ecn, 10759 u8 underlay_ecn) 10760 { 10761 MLXSW_REG_ZERO(tneem, payload); 10762 mlxsw_reg_tneem_overlay_ecn_set(payload, overlay_ecn); 10763 mlxsw_reg_tneem_underlay_ecn_set(payload, underlay_ecn); 10764 } 10765 10766 /* TNDEM - Tunneling NVE Decapsulation ECN Mapping Register 10767 * -------------------------------------------------------- 10768 * The TNDEM register configures the actions that are done in the 10769 * decapsulation. 10770 */ 10771 #define MLXSW_REG_TNDEM_ID 0xA013 10772 #define MLXSW_REG_TNDEM_LEN 0x0C 10773 10774 MLXSW_REG_DEFINE(tndem, MLXSW_REG_TNDEM_ID, MLXSW_REG_TNDEM_LEN); 10775 10776 /* reg_tndem_underlay_ecn 10777 * ECN field of the IP header in the underlay network. 10778 * Access: Index 10779 */ 10780 MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2); 10781 10782 /* reg_tndem_overlay_ecn 10783 * ECN field of the IP header in the overlay network. 10784 * Access: Index 10785 */ 10786 MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2); 10787 10788 /* reg_tndem_eip_ecn 10789 * Egress IP ECN. ECN field of the IP header of the packet which goes out 10790 * from the decapsulation. 10791 * Access: RW 10792 */ 10793 MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2); 10794 10795 /* reg_tndem_trap_en 10796 * Trap enable: 10797 * 0 - No trap due to decap ECN 10798 * 1 - Trap enable with trap_id 10799 * Access: RW 10800 */ 10801 MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4); 10802 10803 /* reg_tndem_trap_id 10804 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 10805 * Reserved when trap_en is '0'. 10806 * Access: RW 10807 */ 10808 MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9); 10809 10810 static inline void mlxsw_reg_tndem_pack(char *payload, u8 underlay_ecn, 10811 u8 overlay_ecn, u8 ecn, bool trap_en, 10812 u16 trap_id) 10813 { 10814 MLXSW_REG_ZERO(tndem, payload); 10815 mlxsw_reg_tndem_underlay_ecn_set(payload, underlay_ecn); 10816 mlxsw_reg_tndem_overlay_ecn_set(payload, overlay_ecn); 10817 mlxsw_reg_tndem_eip_ecn_set(payload, ecn); 10818 mlxsw_reg_tndem_trap_en_set(payload, trap_en); 10819 mlxsw_reg_tndem_trap_id_set(payload, trap_id); 10820 } 10821 10822 /* TNPC - Tunnel Port Configuration Register 10823 * ----------------------------------------- 10824 * The TNPC register is used for tunnel port configuration. 10825 * Reserved when Spectrum. 10826 */ 10827 #define MLXSW_REG_TNPC_ID 0xA020 10828 #define MLXSW_REG_TNPC_LEN 0x18 10829 10830 MLXSW_REG_DEFINE(tnpc, MLXSW_REG_TNPC_ID, MLXSW_REG_TNPC_LEN); 10831 10832 /* reg_tnpc_tunnel_port 10833 * Tunnel port. 10834 * Access: Index 10835 */ 10836 MLXSW_ITEM32(reg, tnpc, tunnel_port, 0x00, 0, 4); 10837 10838 /* reg_tnpc_learn_enable_v6 10839 * During IPv6 underlay decapsulation, whether to learn from tunnel port. 10840 * Access: RW 10841 */ 10842 MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1); 10843 10844 /* reg_tnpc_learn_enable_v4 10845 * During IPv4 underlay decapsulation, whether to learn from tunnel port. 10846 * Access: RW 10847 */ 10848 MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1); 10849 10850 static inline void mlxsw_reg_tnpc_pack(char *payload, 10851 enum mlxsw_reg_tunnel_port tport, 10852 bool learn_enable) 10853 { 10854 MLXSW_REG_ZERO(tnpc, payload); 10855 mlxsw_reg_tnpc_tunnel_port_set(payload, tport); 10856 mlxsw_reg_tnpc_learn_enable_v4_set(payload, learn_enable); 10857 mlxsw_reg_tnpc_learn_enable_v6_set(payload, learn_enable); 10858 } 10859 10860 /* TIGCR - Tunneling IPinIP General Configuration Register 10861 * ------------------------------------------------------- 10862 * The TIGCR register is used for setting up the IPinIP Tunnel configuration. 10863 */ 10864 #define MLXSW_REG_TIGCR_ID 0xA801 10865 #define MLXSW_REG_TIGCR_LEN 0x10 10866 10867 MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN); 10868 10869 /* reg_tigcr_ipip_ttlc 10870 * For IPinIP Tunnel encapsulation: whether to copy the ttl from the packet 10871 * header. 10872 * Access: RW 10873 */ 10874 MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1); 10875 10876 /* reg_tigcr_ipip_ttl_uc 10877 * The TTL for IPinIP Tunnel encapsulation of unicast packets if 10878 * reg_tigcr_ipip_ttlc is unset. 10879 * Access: RW 10880 */ 10881 MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8); 10882 10883 static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc) 10884 { 10885 MLXSW_REG_ZERO(tigcr, payload); 10886 mlxsw_reg_tigcr_ttlc_set(payload, ttlc); 10887 mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc); 10888 } 10889 10890 /* TIEEM - Tunneling IPinIP Encapsulation ECN Mapping Register 10891 * ----------------------------------------------------------- 10892 * The TIEEM register maps ECN of the IP header at the ingress to the 10893 * encapsulation to the ECN of the underlay network. 10894 */ 10895 #define MLXSW_REG_TIEEM_ID 0xA812 10896 #define MLXSW_REG_TIEEM_LEN 0x0C 10897 10898 MLXSW_REG_DEFINE(tieem, MLXSW_REG_TIEEM_ID, MLXSW_REG_TIEEM_LEN); 10899 10900 /* reg_tieem_overlay_ecn 10901 * ECN of the IP header in the overlay network. 10902 * Access: Index 10903 */ 10904 MLXSW_ITEM32(reg, tieem, overlay_ecn, 0x04, 24, 2); 10905 10906 /* reg_tineem_underlay_ecn 10907 * ECN of the IP header in the underlay network. 10908 * Access: RW 10909 */ 10910 MLXSW_ITEM32(reg, tieem, underlay_ecn, 0x04, 16, 2); 10911 10912 static inline void mlxsw_reg_tieem_pack(char *payload, u8 overlay_ecn, 10913 u8 underlay_ecn) 10914 { 10915 MLXSW_REG_ZERO(tieem, payload); 10916 mlxsw_reg_tieem_overlay_ecn_set(payload, overlay_ecn); 10917 mlxsw_reg_tieem_underlay_ecn_set(payload, underlay_ecn); 10918 } 10919 10920 /* TIDEM - Tunneling IPinIP Decapsulation ECN Mapping Register 10921 * ----------------------------------------------------------- 10922 * The TIDEM register configures the actions that are done in the 10923 * decapsulation. 10924 */ 10925 #define MLXSW_REG_TIDEM_ID 0xA813 10926 #define MLXSW_REG_TIDEM_LEN 0x0C 10927 10928 MLXSW_REG_DEFINE(tidem, MLXSW_REG_TIDEM_ID, MLXSW_REG_TIDEM_LEN); 10929 10930 /* reg_tidem_underlay_ecn 10931 * ECN field of the IP header in the underlay network. 10932 * Access: Index 10933 */ 10934 MLXSW_ITEM32(reg, tidem, underlay_ecn, 0x04, 24, 2); 10935 10936 /* reg_tidem_overlay_ecn 10937 * ECN field of the IP header in the overlay network. 10938 * Access: Index 10939 */ 10940 MLXSW_ITEM32(reg, tidem, overlay_ecn, 0x04, 16, 2); 10941 10942 /* reg_tidem_eip_ecn 10943 * Egress IP ECN. ECN field of the IP header of the packet which goes out 10944 * from the decapsulation. 10945 * Access: RW 10946 */ 10947 MLXSW_ITEM32(reg, tidem, eip_ecn, 0x04, 8, 2); 10948 10949 /* reg_tidem_trap_en 10950 * Trap enable: 10951 * 0 - No trap due to decap ECN 10952 * 1 - Trap enable with trap_id 10953 * Access: RW 10954 */ 10955 MLXSW_ITEM32(reg, tidem, trap_en, 0x08, 28, 4); 10956 10957 /* reg_tidem_trap_id 10958 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 10959 * Reserved when trap_en is '0'. 10960 * Access: RW 10961 */ 10962 MLXSW_ITEM32(reg, tidem, trap_id, 0x08, 0, 9); 10963 10964 static inline void mlxsw_reg_tidem_pack(char *payload, u8 underlay_ecn, 10965 u8 overlay_ecn, u8 eip_ecn, 10966 bool trap_en, u16 trap_id) 10967 { 10968 MLXSW_REG_ZERO(tidem, payload); 10969 mlxsw_reg_tidem_underlay_ecn_set(payload, underlay_ecn); 10970 mlxsw_reg_tidem_overlay_ecn_set(payload, overlay_ecn); 10971 mlxsw_reg_tidem_eip_ecn_set(payload, eip_ecn); 10972 mlxsw_reg_tidem_trap_en_set(payload, trap_en); 10973 mlxsw_reg_tidem_trap_id_set(payload, trap_id); 10974 } 10975 10976 /* SBPR - Shared Buffer Pools Register 10977 * ----------------------------------- 10978 * The SBPR configures and retrieves the shared buffer pools and configuration. 10979 */ 10980 #define MLXSW_REG_SBPR_ID 0xB001 10981 #define MLXSW_REG_SBPR_LEN 0x14 10982 10983 MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN); 10984 10985 /* shared direstion enum for SBPR, SBCM, SBPM */ 10986 enum mlxsw_reg_sbxx_dir { 10987 MLXSW_REG_SBXX_DIR_INGRESS, 10988 MLXSW_REG_SBXX_DIR_EGRESS, 10989 }; 10990 10991 /* reg_sbpr_dir 10992 * Direction. 10993 * Access: Index 10994 */ 10995 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2); 10996 10997 /* reg_sbpr_pool 10998 * Pool index. 10999 * Access: Index 11000 */ 11001 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4); 11002 11003 /* reg_sbpr_infi_size 11004 * Size is infinite. 11005 * Access: RW 11006 */ 11007 MLXSW_ITEM32(reg, sbpr, infi_size, 0x04, 31, 1); 11008 11009 /* reg_sbpr_size 11010 * Pool size in buffer cells. 11011 * Reserved when infi_size = 1. 11012 * Access: RW 11013 */ 11014 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24); 11015 11016 enum mlxsw_reg_sbpr_mode { 11017 MLXSW_REG_SBPR_MODE_STATIC, 11018 MLXSW_REG_SBPR_MODE_DYNAMIC, 11019 }; 11020 11021 /* reg_sbpr_mode 11022 * Pool quota calculation mode. 11023 * Access: RW 11024 */ 11025 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4); 11026 11027 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool, 11028 enum mlxsw_reg_sbxx_dir dir, 11029 enum mlxsw_reg_sbpr_mode mode, u32 size, 11030 bool infi_size) 11031 { 11032 MLXSW_REG_ZERO(sbpr, payload); 11033 mlxsw_reg_sbpr_pool_set(payload, pool); 11034 mlxsw_reg_sbpr_dir_set(payload, dir); 11035 mlxsw_reg_sbpr_mode_set(payload, mode); 11036 mlxsw_reg_sbpr_size_set(payload, size); 11037 mlxsw_reg_sbpr_infi_size_set(payload, infi_size); 11038 } 11039 11040 /* SBCM - Shared Buffer Class Management Register 11041 * ---------------------------------------------- 11042 * The SBCM register configures and retrieves the shared buffer allocation 11043 * and configuration according to Port-PG, including the binding to pool 11044 * and definition of the associated quota. 11045 */ 11046 #define MLXSW_REG_SBCM_ID 0xB002 11047 #define MLXSW_REG_SBCM_LEN 0x28 11048 11049 MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN); 11050 11051 /* reg_sbcm_local_port 11052 * Local port number. 11053 * For Ingress: excludes CPU port and Router port 11054 * For Egress: excludes IP Router 11055 * Access: Index 11056 */ 11057 MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8); 11058 11059 /* reg_sbcm_pg_buff 11060 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress) 11061 * For PG buffer: range is 0..cap_max_pg_buffers - 1 11062 * For traffic class: range is 0..cap_max_tclass - 1 11063 * Note that when traffic class is in MC aware mode then the traffic 11064 * classes which are MC aware cannot be configured. 11065 * Access: Index 11066 */ 11067 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6); 11068 11069 /* reg_sbcm_dir 11070 * Direction. 11071 * Access: Index 11072 */ 11073 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2); 11074 11075 /* reg_sbcm_min_buff 11076 * Minimum buffer size for the limiter, in cells. 11077 * Access: RW 11078 */ 11079 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24); 11080 11081 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */ 11082 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1 11083 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14 11084 11085 /* reg_sbcm_infi_max 11086 * Max buffer is infinite. 11087 * Access: RW 11088 */ 11089 MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1); 11090 11091 /* reg_sbcm_max_buff 11092 * When the pool associated to the port-pg/tclass is configured to 11093 * static, Maximum buffer size for the limiter configured in cells. 11094 * When the pool associated to the port-pg/tclass is configured to 11095 * dynamic, the max_buff holds the "alpha" parameter, supporting 11096 * the following values: 11097 * 0: 0 11098 * i: (1/128)*2^(i-1), for i=1..14 11099 * 0xFF: Infinity 11100 * Reserved when infi_max = 1. 11101 * Access: RW 11102 */ 11103 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24); 11104 11105 /* reg_sbcm_pool 11106 * Association of the port-priority to a pool. 11107 * Access: RW 11108 */ 11109 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4); 11110 11111 static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff, 11112 enum mlxsw_reg_sbxx_dir dir, 11113 u32 min_buff, u32 max_buff, 11114 bool infi_max, u8 pool) 11115 { 11116 MLXSW_REG_ZERO(sbcm, payload); 11117 mlxsw_reg_sbcm_local_port_set(payload, local_port); 11118 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff); 11119 mlxsw_reg_sbcm_dir_set(payload, dir); 11120 mlxsw_reg_sbcm_min_buff_set(payload, min_buff); 11121 mlxsw_reg_sbcm_max_buff_set(payload, max_buff); 11122 mlxsw_reg_sbcm_infi_max_set(payload, infi_max); 11123 mlxsw_reg_sbcm_pool_set(payload, pool); 11124 } 11125 11126 /* SBPM - Shared Buffer Port Management Register 11127 * --------------------------------------------- 11128 * The SBPM register configures and retrieves the shared buffer allocation 11129 * and configuration according to Port-Pool, including the definition 11130 * of the associated quota. 11131 */ 11132 #define MLXSW_REG_SBPM_ID 0xB003 11133 #define MLXSW_REG_SBPM_LEN 0x28 11134 11135 MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN); 11136 11137 /* reg_sbpm_local_port 11138 * Local port number. 11139 * For Ingress: excludes CPU port and Router port 11140 * For Egress: excludes IP Router 11141 * Access: Index 11142 */ 11143 MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8); 11144 11145 /* reg_sbpm_pool 11146 * The pool associated to quota counting on the local_port. 11147 * Access: Index 11148 */ 11149 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4); 11150 11151 /* reg_sbpm_dir 11152 * Direction. 11153 * Access: Index 11154 */ 11155 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2); 11156 11157 /* reg_sbpm_buff_occupancy 11158 * Current buffer occupancy in cells. 11159 * Access: RO 11160 */ 11161 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24); 11162 11163 /* reg_sbpm_clr 11164 * Clear Max Buffer Occupancy 11165 * When this bit is set, max_buff_occupancy field is cleared (and a 11166 * new max value is tracked from the time the clear was performed). 11167 * Access: OP 11168 */ 11169 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1); 11170 11171 /* reg_sbpm_max_buff_occupancy 11172 * Maximum value of buffer occupancy in cells monitored. Cleared by 11173 * writing to the clr field. 11174 * Access: RO 11175 */ 11176 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24); 11177 11178 /* reg_sbpm_min_buff 11179 * Minimum buffer size for the limiter, in cells. 11180 * Access: RW 11181 */ 11182 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24); 11183 11184 /* reg_sbpm_max_buff 11185 * When the pool associated to the port-pg/tclass is configured to 11186 * static, Maximum buffer size for the limiter configured in cells. 11187 * When the pool associated to the port-pg/tclass is configured to 11188 * dynamic, the max_buff holds the "alpha" parameter, supporting 11189 * the following values: 11190 * 0: 0 11191 * i: (1/128)*2^(i-1), for i=1..14 11192 * 0xFF: Infinity 11193 * Access: RW 11194 */ 11195 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24); 11196 11197 static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool, 11198 enum mlxsw_reg_sbxx_dir dir, bool clr, 11199 u32 min_buff, u32 max_buff) 11200 { 11201 MLXSW_REG_ZERO(sbpm, payload); 11202 mlxsw_reg_sbpm_local_port_set(payload, local_port); 11203 mlxsw_reg_sbpm_pool_set(payload, pool); 11204 mlxsw_reg_sbpm_dir_set(payload, dir); 11205 mlxsw_reg_sbpm_clr_set(payload, clr); 11206 mlxsw_reg_sbpm_min_buff_set(payload, min_buff); 11207 mlxsw_reg_sbpm_max_buff_set(payload, max_buff); 11208 } 11209 11210 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy, 11211 u32 *p_max_buff_occupancy) 11212 { 11213 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload); 11214 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload); 11215 } 11216 11217 /* SBMM - Shared Buffer Multicast Management Register 11218 * -------------------------------------------------- 11219 * The SBMM register configures and retrieves the shared buffer allocation 11220 * and configuration for MC packets according to Switch-Priority, including 11221 * the binding to pool and definition of the associated quota. 11222 */ 11223 #define MLXSW_REG_SBMM_ID 0xB004 11224 #define MLXSW_REG_SBMM_LEN 0x28 11225 11226 MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN); 11227 11228 /* reg_sbmm_prio 11229 * Switch Priority. 11230 * Access: Index 11231 */ 11232 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4); 11233 11234 /* reg_sbmm_min_buff 11235 * Minimum buffer size for the limiter, in cells. 11236 * Access: RW 11237 */ 11238 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24); 11239 11240 /* reg_sbmm_max_buff 11241 * When the pool associated to the port-pg/tclass is configured to 11242 * static, Maximum buffer size for the limiter configured in cells. 11243 * When the pool associated to the port-pg/tclass is configured to 11244 * dynamic, the max_buff holds the "alpha" parameter, supporting 11245 * the following values: 11246 * 0: 0 11247 * i: (1/128)*2^(i-1), for i=1..14 11248 * 0xFF: Infinity 11249 * Access: RW 11250 */ 11251 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24); 11252 11253 /* reg_sbmm_pool 11254 * Association of the port-priority to a pool. 11255 * Access: RW 11256 */ 11257 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4); 11258 11259 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff, 11260 u32 max_buff, u8 pool) 11261 { 11262 MLXSW_REG_ZERO(sbmm, payload); 11263 mlxsw_reg_sbmm_prio_set(payload, prio); 11264 mlxsw_reg_sbmm_min_buff_set(payload, min_buff); 11265 mlxsw_reg_sbmm_max_buff_set(payload, max_buff); 11266 mlxsw_reg_sbmm_pool_set(payload, pool); 11267 } 11268 11269 /* SBSR - Shared Buffer Status Register 11270 * ------------------------------------ 11271 * The SBSR register retrieves the shared buffer occupancy according to 11272 * Port-Pool. Note that this register enables reading a large amount of data. 11273 * It is the user's responsibility to limit the amount of data to ensure the 11274 * response can match the maximum transfer unit. In case the response exceeds 11275 * the maximum transport unit, it will be truncated with no special notice. 11276 */ 11277 #define MLXSW_REG_SBSR_ID 0xB005 11278 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */ 11279 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */ 11280 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120 11281 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \ 11282 MLXSW_REG_SBSR_REC_LEN * \ 11283 MLXSW_REG_SBSR_REC_MAX_COUNT) 11284 11285 MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN); 11286 11287 /* reg_sbsr_clr 11288 * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy 11289 * field is cleared (and a new max value is tracked from the time the clear 11290 * was performed). 11291 * Access: OP 11292 */ 11293 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1); 11294 11295 /* reg_sbsr_ingress_port_mask 11296 * Bit vector for all ingress network ports. 11297 * Indicates which of the ports (for which the relevant bit is set) 11298 * are affected by the set operation. Configuration of any other port 11299 * does not change. 11300 * Access: Index 11301 */ 11302 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1); 11303 11304 /* reg_sbsr_pg_buff_mask 11305 * Bit vector for all switch priority groups. 11306 * Indicates which of the priorities (for which the relevant bit is set) 11307 * are affected by the set operation. Configuration of any other priority 11308 * does not change. 11309 * Range is 0..cap_max_pg_buffers - 1 11310 * Access: Index 11311 */ 11312 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1); 11313 11314 /* reg_sbsr_egress_port_mask 11315 * Bit vector for all egress network ports. 11316 * Indicates which of the ports (for which the relevant bit is set) 11317 * are affected by the set operation. Configuration of any other port 11318 * does not change. 11319 * Access: Index 11320 */ 11321 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1); 11322 11323 /* reg_sbsr_tclass_mask 11324 * Bit vector for all traffic classes. 11325 * Indicates which of the traffic classes (for which the relevant bit is 11326 * set) are affected by the set operation. Configuration of any other 11327 * traffic class does not change. 11328 * Range is 0..cap_max_tclass - 1 11329 * Access: Index 11330 */ 11331 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1); 11332 11333 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr) 11334 { 11335 MLXSW_REG_ZERO(sbsr, payload); 11336 mlxsw_reg_sbsr_clr_set(payload, clr); 11337 } 11338 11339 /* reg_sbsr_rec_buff_occupancy 11340 * Current buffer occupancy in cells. 11341 * Access: RO 11342 */ 11343 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 11344 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false); 11345 11346 /* reg_sbsr_rec_max_buff_occupancy 11347 * Maximum value of buffer occupancy in cells monitored. Cleared by 11348 * writing to the clr field. 11349 * Access: RO 11350 */ 11351 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 11352 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false); 11353 11354 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index, 11355 u32 *p_buff_occupancy, 11356 u32 *p_max_buff_occupancy) 11357 { 11358 *p_buff_occupancy = 11359 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index); 11360 *p_max_buff_occupancy = 11361 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index); 11362 } 11363 11364 /* SBIB - Shared Buffer Internal Buffer Register 11365 * --------------------------------------------- 11366 * The SBIB register configures per port buffers for internal use. The internal 11367 * buffers consume memory on the port buffers (note that the port buffers are 11368 * used also by PBMC). 11369 * 11370 * For Spectrum this is used for egress mirroring. 11371 */ 11372 #define MLXSW_REG_SBIB_ID 0xB006 11373 #define MLXSW_REG_SBIB_LEN 0x10 11374 11375 MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN); 11376 11377 /* reg_sbib_local_port 11378 * Local port number 11379 * Not supported for CPU port and router port 11380 * Access: Index 11381 */ 11382 MLXSW_ITEM32(reg, sbib, local_port, 0x00, 16, 8); 11383 11384 /* reg_sbib_buff_size 11385 * Units represented in cells 11386 * Allowed range is 0 to (cap_max_headroom_size - 1) 11387 * Default is 0 11388 * Access: RW 11389 */ 11390 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24); 11391 11392 static inline void mlxsw_reg_sbib_pack(char *payload, u8 local_port, 11393 u32 buff_size) 11394 { 11395 MLXSW_REG_ZERO(sbib, payload); 11396 mlxsw_reg_sbib_local_port_set(payload, local_port); 11397 mlxsw_reg_sbib_buff_size_set(payload, buff_size); 11398 } 11399 11400 static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { 11401 MLXSW_REG(sgcr), 11402 MLXSW_REG(spad), 11403 MLXSW_REG(smid), 11404 MLXSW_REG(sspr), 11405 MLXSW_REG(sfdat), 11406 MLXSW_REG(sfd), 11407 MLXSW_REG(sfn), 11408 MLXSW_REG(spms), 11409 MLXSW_REG(spvid), 11410 MLXSW_REG(spvm), 11411 MLXSW_REG(spaft), 11412 MLXSW_REG(sfgc), 11413 MLXSW_REG(sftr), 11414 MLXSW_REG(sfdf), 11415 MLXSW_REG(sldr), 11416 MLXSW_REG(slcr), 11417 MLXSW_REG(slcor), 11418 MLXSW_REG(spmlr), 11419 MLXSW_REG(svfa), 11420 MLXSW_REG(spvtr), 11421 MLXSW_REG(svpe), 11422 MLXSW_REG(sfmr), 11423 MLXSW_REG(spvmlr), 11424 MLXSW_REG(spvc), 11425 MLXSW_REG(cwtp), 11426 MLXSW_REG(cwtpm), 11427 MLXSW_REG(pgcr), 11428 MLXSW_REG(ppbt), 11429 MLXSW_REG(pacl), 11430 MLXSW_REG(pagt), 11431 MLXSW_REG(ptar), 11432 MLXSW_REG(ppbs), 11433 MLXSW_REG(prcr), 11434 MLXSW_REG(pefa), 11435 MLXSW_REG(pemrbt), 11436 MLXSW_REG(ptce2), 11437 MLXSW_REG(perpt), 11438 MLXSW_REG(peabfe), 11439 MLXSW_REG(perar), 11440 MLXSW_REG(ptce3), 11441 MLXSW_REG(percr), 11442 MLXSW_REG(pererp), 11443 MLXSW_REG(iedr), 11444 MLXSW_REG(qpts), 11445 MLXSW_REG(qpcr), 11446 MLXSW_REG(qtct), 11447 MLXSW_REG(qeec), 11448 MLXSW_REG(qrwe), 11449 MLXSW_REG(qpdsm), 11450 MLXSW_REG(qpdp), 11451 MLXSW_REG(qpdpm), 11452 MLXSW_REG(qtctm), 11453 MLXSW_REG(qpsc), 11454 MLXSW_REG(pmlp), 11455 MLXSW_REG(pmtu), 11456 MLXSW_REG(ptys), 11457 MLXSW_REG(ppad), 11458 MLXSW_REG(paos), 11459 MLXSW_REG(pfcc), 11460 MLXSW_REG(ppcnt), 11461 MLXSW_REG(plib), 11462 MLXSW_REG(pptb), 11463 MLXSW_REG(pbmc), 11464 MLXSW_REG(pspa), 11465 MLXSW_REG(pmaos), 11466 MLXSW_REG(pplr), 11467 MLXSW_REG(pmpe), 11468 MLXSW_REG(pddr), 11469 MLXSW_REG(pmtm), 11470 MLXSW_REG(htgt), 11471 MLXSW_REG(hpkt), 11472 MLXSW_REG(rgcr), 11473 MLXSW_REG(ritr), 11474 MLXSW_REG(rtar), 11475 MLXSW_REG(ratr), 11476 MLXSW_REG(rtdp), 11477 MLXSW_REG(rdpm), 11478 MLXSW_REG(ricnt), 11479 MLXSW_REG(rrcr), 11480 MLXSW_REG(ralta), 11481 MLXSW_REG(ralst), 11482 MLXSW_REG(raltb), 11483 MLXSW_REG(ralue), 11484 MLXSW_REG(rauht), 11485 MLXSW_REG(raleu), 11486 MLXSW_REG(rauhtd), 11487 MLXSW_REG(rigr2), 11488 MLXSW_REG(recr2), 11489 MLXSW_REG(rmft2), 11490 MLXSW_REG(xralta), 11491 MLXSW_REG(xralst), 11492 MLXSW_REG(xraltb), 11493 MLXSW_REG(mfcr), 11494 MLXSW_REG(mfsc), 11495 MLXSW_REG(mfsm), 11496 MLXSW_REG(mfsl), 11497 MLXSW_REG(fore), 11498 MLXSW_REG(mtcap), 11499 MLXSW_REG(mtmp), 11500 MLXSW_REG(mtwe), 11501 MLXSW_REG(mtbr), 11502 MLXSW_REG(mcia), 11503 MLXSW_REG(mpat), 11504 MLXSW_REG(mpar), 11505 MLXSW_REG(mgir), 11506 MLXSW_REG(mrsr), 11507 MLXSW_REG(mlcr), 11508 MLXSW_REG(mtpps), 11509 MLXSW_REG(mtutc), 11510 MLXSW_REG(mpsc), 11511 MLXSW_REG(mcqi), 11512 MLXSW_REG(mcc), 11513 MLXSW_REG(mcda), 11514 MLXSW_REG(mgpc), 11515 MLXSW_REG(mprs), 11516 MLXSW_REG(mogcr), 11517 MLXSW_REG(mpagr), 11518 MLXSW_REG(momte), 11519 MLXSW_REG(mtpppc), 11520 MLXSW_REG(mtpptr), 11521 MLXSW_REG(mtptpt), 11522 MLXSW_REG(mfgd), 11523 MLXSW_REG(mgpir), 11524 MLXSW_REG(mfde), 11525 MLXSW_REG(tngcr), 11526 MLXSW_REG(tnumt), 11527 MLXSW_REG(tnqcr), 11528 MLXSW_REG(tnqdr), 11529 MLXSW_REG(tneem), 11530 MLXSW_REG(tndem), 11531 MLXSW_REG(tnpc), 11532 MLXSW_REG(tigcr), 11533 MLXSW_REG(tieem), 11534 MLXSW_REG(tidem), 11535 MLXSW_REG(sbpr), 11536 MLXSW_REG(sbcm), 11537 MLXSW_REG(sbpm), 11538 MLXSW_REG(sbmm), 11539 MLXSW_REG(sbsr), 11540 MLXSW_REG(sbib), 11541 }; 11542 11543 static inline const char *mlxsw_reg_id_str(u16 reg_id) 11544 { 11545 const struct mlxsw_reg_info *reg_info; 11546 int i; 11547 11548 for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) { 11549 reg_info = mlxsw_reg_infos[i]; 11550 if (reg_info->id == reg_id) 11551 return reg_info->name; 11552 } 11553 return "*UNKNOWN*"; 11554 } 11555 11556 /* PUDE - Port Up / Down Event 11557 * --------------------------- 11558 * Reports the operational state change of a port. 11559 */ 11560 #define MLXSW_REG_PUDE_LEN 0x10 11561 11562 /* reg_pude_swid 11563 * Switch partition ID with which to associate the port. 11564 * Access: Index 11565 */ 11566 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8); 11567 11568 /* reg_pude_local_port 11569 * Local port number. 11570 * Access: Index 11571 */ 11572 MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8); 11573 11574 /* reg_pude_admin_status 11575 * Port administrative state (the desired state). 11576 * 1 - Up. 11577 * 2 - Down. 11578 * 3 - Up once. This means that in case of link failure, the port won't go 11579 * into polling mode, but will wait to be re-enabled by software. 11580 * 4 - Disabled by system. Can only be set by hardware. 11581 * Access: RO 11582 */ 11583 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4); 11584 11585 /* reg_pude_oper_status 11586 * Port operatioanl state. 11587 * 1 - Up. 11588 * 2 - Down. 11589 * 3 - Down by port failure. This means that the device will not let the 11590 * port up again until explicitly specified by software. 11591 * Access: RO 11592 */ 11593 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4); 11594 11595 #endif 11596