1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #ifndef _MLXSW_REG_H 5 #define _MLXSW_REG_H 6 7 #include <linux/kernel.h> 8 #include <linux/string.h> 9 #include <linux/bitops.h> 10 #include <linux/if_vlan.h> 11 12 #include "item.h" 13 #include "port.h" 14 15 struct mlxsw_reg_info { 16 u16 id; 17 u16 len; /* In u8 */ 18 const char *name; 19 }; 20 21 #define MLXSW_REG_DEFINE(_name, _id, _len) \ 22 static const struct mlxsw_reg_info mlxsw_reg_##_name = { \ 23 .id = _id, \ 24 .len = _len, \ 25 .name = #_name, \ 26 } 27 28 #define MLXSW_REG(type) (&mlxsw_reg_##type) 29 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len 30 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len) 31 32 /* SGCR - Switch General Configuration Register 33 * -------------------------------------------- 34 * This register is used for configuration of the switch capabilities. 35 */ 36 #define MLXSW_REG_SGCR_ID 0x2000 37 #define MLXSW_REG_SGCR_LEN 0x10 38 39 MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN); 40 41 /* reg_sgcr_llb 42 * Link Local Broadcast (Default=0) 43 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast 44 * packets and ignore the IGMP snooping entries. 45 * Access: RW 46 */ 47 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1); 48 49 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb) 50 { 51 MLXSW_REG_ZERO(sgcr, payload); 52 mlxsw_reg_sgcr_llb_set(payload, !!llb); 53 } 54 55 /* SPAD - Switch Physical Address Register 56 * --------------------------------------- 57 * The SPAD register configures the switch physical MAC address. 58 */ 59 #define MLXSW_REG_SPAD_ID 0x2002 60 #define MLXSW_REG_SPAD_LEN 0x10 61 62 MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN); 63 64 /* reg_spad_base_mac 65 * Base MAC address for the switch partitions. 66 * Per switch partition MAC address is equal to: 67 * base_mac + swid 68 * Access: RW 69 */ 70 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6); 71 72 /* SMID - Switch Multicast ID 73 * -------------------------- 74 * The MID record maps from a MID (Multicast ID), which is a unique identifier 75 * of the multicast group within the stacking domain, into a list of local 76 * ports into which the packet is replicated. 77 */ 78 #define MLXSW_REG_SMID_ID 0x2007 79 #define MLXSW_REG_SMID_LEN 0x240 80 81 MLXSW_REG_DEFINE(smid, MLXSW_REG_SMID_ID, MLXSW_REG_SMID_LEN); 82 83 /* reg_smid_swid 84 * Switch partition ID. 85 * Access: Index 86 */ 87 MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8); 88 89 /* reg_smid_mid 90 * Multicast identifier - global identifier that represents the multicast group 91 * across all devices. 92 * Access: Index 93 */ 94 MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16); 95 96 /* reg_smid_port 97 * Local port memebership (1 bit per port). 98 * Access: RW 99 */ 100 MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1); 101 102 /* reg_smid_port_mask 103 * Local port mask (1 bit per port). 104 * Access: W 105 */ 106 MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1); 107 108 static inline void mlxsw_reg_smid_pack(char *payload, u16 mid, 109 u8 port, bool set) 110 { 111 MLXSW_REG_ZERO(smid, payload); 112 mlxsw_reg_smid_swid_set(payload, 0); 113 mlxsw_reg_smid_mid_set(payload, mid); 114 mlxsw_reg_smid_port_set(payload, port, set); 115 mlxsw_reg_smid_port_mask_set(payload, port, 1); 116 } 117 118 /* SSPR - Switch System Port Record Register 119 * ----------------------------------------- 120 * Configures the system port to local port mapping. 121 */ 122 #define MLXSW_REG_SSPR_ID 0x2008 123 #define MLXSW_REG_SSPR_LEN 0x8 124 125 MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN); 126 127 /* reg_sspr_m 128 * Master - if set, then the record describes the master system port. 129 * This is needed in case a local port is mapped into several system ports 130 * (for multipathing). That number will be reported as the source system 131 * port when packets are forwarded to the CPU. Only one master port is allowed 132 * per local port. 133 * 134 * Note: Must be set for Spectrum. 135 * Access: RW 136 */ 137 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1); 138 139 /* reg_sspr_local_port 140 * Local port number. 141 * 142 * Access: RW 143 */ 144 MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8); 145 146 /* reg_sspr_sub_port 147 * Virtual port within the physical port. 148 * Should be set to 0 when virtual ports are not enabled on the port. 149 * 150 * Access: RW 151 */ 152 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8); 153 154 /* reg_sspr_system_port 155 * Unique identifier within the stacking domain that represents all the ports 156 * that are available in the system (external ports). 157 * 158 * Currently, only single-ASIC configurations are supported, so we default to 159 * 1:1 mapping between system ports and local ports. 160 * Access: Index 161 */ 162 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16); 163 164 static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port) 165 { 166 MLXSW_REG_ZERO(sspr, payload); 167 mlxsw_reg_sspr_m_set(payload, 1); 168 mlxsw_reg_sspr_local_port_set(payload, local_port); 169 mlxsw_reg_sspr_sub_port_set(payload, 0); 170 mlxsw_reg_sspr_system_port_set(payload, local_port); 171 } 172 173 /* SFDAT - Switch Filtering Database Aging Time 174 * -------------------------------------------- 175 * Controls the Switch aging time. Aging time is able to be set per Switch 176 * Partition. 177 */ 178 #define MLXSW_REG_SFDAT_ID 0x2009 179 #define MLXSW_REG_SFDAT_LEN 0x8 180 181 MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN); 182 183 /* reg_sfdat_swid 184 * Switch partition ID. 185 * Access: Index 186 */ 187 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8); 188 189 /* reg_sfdat_age_time 190 * Aging time in seconds 191 * Min - 10 seconds 192 * Max - 1,000,000 seconds 193 * Default is 300 seconds. 194 * Access: RW 195 */ 196 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20); 197 198 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time) 199 { 200 MLXSW_REG_ZERO(sfdat, payload); 201 mlxsw_reg_sfdat_swid_set(payload, 0); 202 mlxsw_reg_sfdat_age_time_set(payload, age_time); 203 } 204 205 /* SFD - Switch Filtering Database 206 * ------------------------------- 207 * The following register defines the access to the filtering database. 208 * The register supports querying, adding, removing and modifying the database. 209 * The access is optimized for bulk updates in which case more than one 210 * FDB record is present in the same command. 211 */ 212 #define MLXSW_REG_SFD_ID 0x200A 213 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */ 214 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */ 215 #define MLXSW_REG_SFD_REC_MAX_COUNT 64 216 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \ 217 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT) 218 219 MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN); 220 221 /* reg_sfd_swid 222 * Switch partition ID for queries. Reserved on Write. 223 * Access: Index 224 */ 225 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8); 226 227 enum mlxsw_reg_sfd_op { 228 /* Dump entire FDB a (process according to record_locator) */ 229 MLXSW_REG_SFD_OP_QUERY_DUMP = 0, 230 /* Query records by {MAC, VID/FID} value */ 231 MLXSW_REG_SFD_OP_QUERY_QUERY = 1, 232 /* Query and clear activity. Query records by {MAC, VID/FID} value */ 233 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2, 234 /* Test. Response indicates if each of the records could be 235 * added to the FDB. 236 */ 237 MLXSW_REG_SFD_OP_WRITE_TEST = 0, 238 /* Add/modify. Aged-out records cannot be added. This command removes 239 * the learning notification of the {MAC, VID/FID}. Response includes 240 * the entries that were added to the FDB. 241 */ 242 MLXSW_REG_SFD_OP_WRITE_EDIT = 1, 243 /* Remove record by {MAC, VID/FID}. This command also removes 244 * the learning notification and aged-out notifications 245 * of the {MAC, VID/FID}. The response provides current (pre-removal) 246 * entries as non-aged-out. 247 */ 248 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2, 249 /* Remove learned notification by {MAC, VID/FID}. The response provides 250 * the removed learning notification. 251 */ 252 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2, 253 }; 254 255 /* reg_sfd_op 256 * Operation. 257 * Access: OP 258 */ 259 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2); 260 261 /* reg_sfd_record_locator 262 * Used for querying the FDB. Use record_locator=0 to initiate the 263 * query. When a record is returned, a new record_locator is 264 * returned to be used in the subsequent query. 265 * Reserved for database update. 266 * Access: Index 267 */ 268 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30); 269 270 /* reg_sfd_num_rec 271 * Request: Number of records to read/add/modify/remove 272 * Response: Number of records read/added/replaced/removed 273 * See above description for more details. 274 * Ranges 0..64 275 * Access: RW 276 */ 277 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8); 278 279 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op, 280 u32 record_locator) 281 { 282 MLXSW_REG_ZERO(sfd, payload); 283 mlxsw_reg_sfd_op_set(payload, op); 284 mlxsw_reg_sfd_record_locator_set(payload, record_locator); 285 } 286 287 /* reg_sfd_rec_swid 288 * Switch partition ID. 289 * Access: Index 290 */ 291 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8, 292 MLXSW_REG_SFD_REC_LEN, 0x00, false); 293 294 enum mlxsw_reg_sfd_rec_type { 295 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0, 296 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1, 297 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2, 298 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL = 0xC, 299 }; 300 301 /* reg_sfd_rec_type 302 * FDB record type. 303 * Access: RW 304 */ 305 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4, 306 MLXSW_REG_SFD_REC_LEN, 0x00, false); 307 308 enum mlxsw_reg_sfd_rec_policy { 309 /* Replacement disabled, aging disabled. */ 310 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0, 311 /* (mlag remote): Replacement enabled, aging disabled, 312 * learning notification enabled on this port. 313 */ 314 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1, 315 /* (ingress device): Replacement enabled, aging enabled. */ 316 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3, 317 }; 318 319 /* reg_sfd_rec_policy 320 * Policy. 321 * Access: RW 322 */ 323 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2, 324 MLXSW_REG_SFD_REC_LEN, 0x00, false); 325 326 /* reg_sfd_rec_a 327 * Activity. Set for new static entries. Set for static entries if a frame SMAC 328 * lookup hits on the entry. 329 * To clear the a bit, use "query and clear activity" op. 330 * Access: RO 331 */ 332 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1, 333 MLXSW_REG_SFD_REC_LEN, 0x00, false); 334 335 /* reg_sfd_rec_mac 336 * MAC address. 337 * Access: Index 338 */ 339 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6, 340 MLXSW_REG_SFD_REC_LEN, 0x02); 341 342 enum mlxsw_reg_sfd_rec_action { 343 /* forward */ 344 MLXSW_REG_SFD_REC_ACTION_NOP = 0, 345 /* forward and trap, trap_id is FDB_TRAP */ 346 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1, 347 /* trap and do not forward, trap_id is FDB_TRAP */ 348 MLXSW_REG_SFD_REC_ACTION_TRAP = 2, 349 /* forward to IP router */ 350 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3, 351 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15, 352 }; 353 354 /* reg_sfd_rec_action 355 * Action to apply on the packet. 356 * Note: Dynamic entries can only be configured with NOP action. 357 * Access: RW 358 */ 359 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4, 360 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 361 362 /* reg_sfd_uc_sub_port 363 * VEPA channel on local port. 364 * Valid only if local port is a non-stacking port. Must be 0 if multichannel 365 * VEPA is not enabled. 366 * Access: RW 367 */ 368 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 369 MLXSW_REG_SFD_REC_LEN, 0x08, false); 370 371 /* reg_sfd_uc_fid_vid 372 * Filtering ID or VLAN ID 373 * For SwitchX and SwitchX-2: 374 * - Dynamic entries (policy 2,3) use FID 375 * - Static entries (policy 0) use VID 376 * - When independent learning is configured, VID=FID 377 * For Spectrum: use FID for both Dynamic and Static entries. 378 * VID should not be used. 379 * Access: Index 380 */ 381 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 382 MLXSW_REG_SFD_REC_LEN, 0x08, false); 383 384 /* reg_sfd_uc_system_port 385 * Unique port identifier for the final destination of the packet. 386 * Access: RW 387 */ 388 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16, 389 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 390 391 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index, 392 enum mlxsw_reg_sfd_rec_type rec_type, 393 const char *mac, 394 enum mlxsw_reg_sfd_rec_action action) 395 { 396 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload); 397 398 if (rec_index >= num_rec) 399 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1); 400 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0); 401 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type); 402 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac); 403 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action); 404 } 405 406 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index, 407 enum mlxsw_reg_sfd_rec_policy policy, 408 const char *mac, u16 fid_vid, 409 enum mlxsw_reg_sfd_rec_action action, 410 u8 local_port) 411 { 412 mlxsw_reg_sfd_rec_pack(payload, rec_index, 413 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action); 414 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 415 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0); 416 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid); 417 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port); 418 } 419 420 static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index, 421 char *mac, u16 *p_fid_vid, 422 u8 *p_local_port) 423 { 424 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 425 *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index); 426 *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index); 427 } 428 429 /* reg_sfd_uc_lag_sub_port 430 * LAG sub port. 431 * Must be 0 if multichannel VEPA is not enabled. 432 * Access: RW 433 */ 434 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 435 MLXSW_REG_SFD_REC_LEN, 0x08, false); 436 437 /* reg_sfd_uc_lag_fid_vid 438 * Filtering ID or VLAN ID 439 * For SwitchX and SwitchX-2: 440 * - Dynamic entries (policy 2,3) use FID 441 * - Static entries (policy 0) use VID 442 * - When independent learning is configured, VID=FID 443 * For Spectrum: use FID for both Dynamic and Static entries. 444 * VID should not be used. 445 * Access: Index 446 */ 447 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 448 MLXSW_REG_SFD_REC_LEN, 0x08, false); 449 450 /* reg_sfd_uc_lag_lag_vid 451 * Indicates VID in case of vFIDs. Reserved for FIDs. 452 * Access: RW 453 */ 454 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, 455 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 456 457 /* reg_sfd_uc_lag_lag_id 458 * LAG Identifier - pointer into the LAG descriptor table. 459 * Access: RW 460 */ 461 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10, 462 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 463 464 static inline void 465 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index, 466 enum mlxsw_reg_sfd_rec_policy policy, 467 const char *mac, u16 fid_vid, 468 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid, 469 u16 lag_id) 470 { 471 mlxsw_reg_sfd_rec_pack(payload, rec_index, 472 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG, 473 mac, action); 474 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 475 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0); 476 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid); 477 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid); 478 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id); 479 } 480 481 static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index, 482 char *mac, u16 *p_vid, 483 u16 *p_lag_id) 484 { 485 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 486 *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index); 487 *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index); 488 } 489 490 /* reg_sfd_mc_pgi 491 * 492 * Multicast port group index - index into the port group table. 493 * Value 0x1FFF indicates the pgi should point to the MID entry. 494 * For Spectrum this value must be set to 0x1FFF 495 * Access: RW 496 */ 497 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13, 498 MLXSW_REG_SFD_REC_LEN, 0x08, false); 499 500 /* reg_sfd_mc_fid_vid 501 * 502 * Filtering ID or VLAN ID 503 * Access: Index 504 */ 505 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 506 MLXSW_REG_SFD_REC_LEN, 0x08, false); 507 508 /* reg_sfd_mc_mid 509 * 510 * Multicast identifier - global identifier that represents the multicast 511 * group across all devices. 512 * Access: RW 513 */ 514 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 515 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 516 517 static inline void 518 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index, 519 const char *mac, u16 fid_vid, 520 enum mlxsw_reg_sfd_rec_action action, u16 mid) 521 { 522 mlxsw_reg_sfd_rec_pack(payload, rec_index, 523 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action); 524 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF); 525 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid); 526 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid); 527 } 528 529 /* reg_sfd_uc_tunnel_uip_msb 530 * When protocol is IPv4, the most significant byte of the underlay IPv4 531 * destination IP. 532 * When protocol is IPv6, reserved. 533 * Access: RW 534 */ 535 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24, 536 8, MLXSW_REG_SFD_REC_LEN, 0x08, false); 537 538 /* reg_sfd_uc_tunnel_fid 539 * Filtering ID. 540 * Access: Index 541 */ 542 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 543 MLXSW_REG_SFD_REC_LEN, 0x08, false); 544 545 enum mlxsw_reg_sfd_uc_tunnel_protocol { 546 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4, 547 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6, 548 }; 549 550 /* reg_sfd_uc_tunnel_protocol 551 * IP protocol. 552 * Access: RW 553 */ 554 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27, 555 1, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 556 557 /* reg_sfd_uc_tunnel_uip_lsb 558 * When protocol is IPv4, the least significant bytes of the underlay 559 * IPv4 destination IP. 560 * When protocol is IPv6, pointer to the underlay IPv6 destination IP 561 * which is configured by RIPS. 562 * Access: RW 563 */ 564 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0, 565 24, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 566 567 static inline void 568 mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index, 569 enum mlxsw_reg_sfd_rec_policy policy, 570 const char *mac, u16 fid, 571 enum mlxsw_reg_sfd_rec_action action, u32 uip, 572 enum mlxsw_reg_sfd_uc_tunnel_protocol proto) 573 { 574 mlxsw_reg_sfd_rec_pack(payload, rec_index, 575 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL, mac, 576 action); 577 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 578 mlxsw_reg_sfd_uc_tunnel_uip_msb_set(payload, rec_index, uip >> 24); 579 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip); 580 mlxsw_reg_sfd_uc_tunnel_fid_set(payload, rec_index, fid); 581 mlxsw_reg_sfd_uc_tunnel_protocol_set(payload, rec_index, proto); 582 } 583 584 /* SFN - Switch FDB Notification Register 585 * ------------------------------------------- 586 * The switch provides notifications on newly learned FDB entries and 587 * aged out entries. The notifications can be polled by software. 588 */ 589 #define MLXSW_REG_SFN_ID 0x200B 590 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */ 591 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */ 592 #define MLXSW_REG_SFN_REC_MAX_COUNT 64 593 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \ 594 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT) 595 596 MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN); 597 598 /* reg_sfn_swid 599 * Switch partition ID. 600 * Access: Index 601 */ 602 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8); 603 604 /* reg_sfn_end 605 * Forces the current session to end. 606 * Access: OP 607 */ 608 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1); 609 610 /* reg_sfn_num_rec 611 * Request: Number of learned notifications and aged-out notification 612 * records requested. 613 * Response: Number of notification records returned (must be smaller 614 * than or equal to the value requested) 615 * Ranges 0..64 616 * Access: OP 617 */ 618 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8); 619 620 static inline void mlxsw_reg_sfn_pack(char *payload) 621 { 622 MLXSW_REG_ZERO(sfn, payload); 623 mlxsw_reg_sfn_swid_set(payload, 0); 624 mlxsw_reg_sfn_end_set(payload, 1); 625 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT); 626 } 627 628 /* reg_sfn_rec_swid 629 * Switch partition ID. 630 * Access: RO 631 */ 632 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8, 633 MLXSW_REG_SFN_REC_LEN, 0x00, false); 634 635 enum mlxsw_reg_sfn_rec_type { 636 /* MAC addresses learned on a regular port. */ 637 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5, 638 /* MAC addresses learned on a LAG port. */ 639 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6, 640 /* Aged-out MAC address on a regular port. */ 641 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7, 642 /* Aged-out MAC address on a LAG port. */ 643 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8, 644 /* Learned unicast tunnel record. */ 645 MLXSW_REG_SFN_REC_TYPE_LEARNED_UNICAST_TUNNEL = 0xD, 646 /* Aged-out unicast tunnel record. */ 647 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_UNICAST_TUNNEL = 0xE, 648 }; 649 650 /* reg_sfn_rec_type 651 * Notification record type. 652 * Access: RO 653 */ 654 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4, 655 MLXSW_REG_SFN_REC_LEN, 0x00, false); 656 657 /* reg_sfn_rec_mac 658 * MAC address. 659 * Access: RO 660 */ 661 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6, 662 MLXSW_REG_SFN_REC_LEN, 0x02); 663 664 /* reg_sfn_mac_sub_port 665 * VEPA channel on the local port. 666 * 0 if multichannel VEPA is not enabled. 667 * Access: RO 668 */ 669 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8, 670 MLXSW_REG_SFN_REC_LEN, 0x08, false); 671 672 /* reg_sfn_mac_fid 673 * Filtering identifier. 674 * Access: RO 675 */ 676 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16, 677 MLXSW_REG_SFN_REC_LEN, 0x08, false); 678 679 /* reg_sfn_mac_system_port 680 * Unique port identifier for the final destination of the packet. 681 * Access: RO 682 */ 683 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16, 684 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 685 686 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index, 687 char *mac, u16 *p_vid, 688 u8 *p_local_port) 689 { 690 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 691 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 692 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index); 693 } 694 695 /* reg_sfn_mac_lag_lag_id 696 * LAG ID (pointer into the LAG descriptor table). 697 * Access: RO 698 */ 699 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10, 700 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 701 702 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index, 703 char *mac, u16 *p_vid, 704 u16 *p_lag_id) 705 { 706 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 707 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 708 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index); 709 } 710 711 /* reg_sfn_uc_tunnel_uip_msb 712 * When protocol is IPv4, the most significant byte of the underlay IPv4 713 * address of the remote VTEP. 714 * When protocol is IPv6, reserved. 715 * Access: RO 716 */ 717 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_msb, MLXSW_REG_SFN_BASE_LEN, 24, 718 8, MLXSW_REG_SFN_REC_LEN, 0x08, false); 719 720 enum mlxsw_reg_sfn_uc_tunnel_protocol { 721 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV4, 722 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV6, 723 }; 724 725 /* reg_sfn_uc_tunnel_protocol 726 * IP protocol. 727 * Access: RO 728 */ 729 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_protocol, MLXSW_REG_SFN_BASE_LEN, 27, 730 1, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 731 732 /* reg_sfn_uc_tunnel_uip_lsb 733 * When protocol is IPv4, the least significant bytes of the underlay 734 * IPv4 address of the remote VTEP. 735 * When protocol is IPv6, ipv6_id to be queried from TNIPSD. 736 * Access: RO 737 */ 738 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0, 739 24, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 740 741 enum mlxsw_reg_sfn_tunnel_port { 742 MLXSW_REG_SFN_TUNNEL_PORT_NVE, 743 MLXSW_REG_SFN_TUNNEL_PORT_VPLS, 744 MLXSW_REG_SFN_TUNNEL_FLEX_TUNNEL0, 745 MLXSW_REG_SFN_TUNNEL_FLEX_TUNNEL1, 746 }; 747 748 /* reg_sfn_uc_tunnel_port 749 * Tunnel port. 750 * Reserved on Spectrum. 751 * Access: RO 752 */ 753 MLXSW_ITEM32_INDEXED(reg, sfn, tunnel_port, MLXSW_REG_SFN_BASE_LEN, 0, 4, 754 MLXSW_REG_SFN_REC_LEN, 0x10, false); 755 756 static inline void 757 mlxsw_reg_sfn_uc_tunnel_unpack(char *payload, int rec_index, char *mac, 758 u16 *p_fid, u32 *p_uip, 759 enum mlxsw_reg_sfn_uc_tunnel_protocol *p_proto) 760 { 761 u32 uip_msb, uip_lsb; 762 763 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 764 *p_fid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 765 uip_msb = mlxsw_reg_sfn_uc_tunnel_uip_msb_get(payload, rec_index); 766 uip_lsb = mlxsw_reg_sfn_uc_tunnel_uip_lsb_get(payload, rec_index); 767 *p_uip = uip_msb << 24 | uip_lsb; 768 *p_proto = mlxsw_reg_sfn_uc_tunnel_protocol_get(payload, rec_index); 769 } 770 771 /* SPMS - Switch Port MSTP/RSTP State Register 772 * ------------------------------------------- 773 * Configures the spanning tree state of a physical port. 774 */ 775 #define MLXSW_REG_SPMS_ID 0x200D 776 #define MLXSW_REG_SPMS_LEN 0x404 777 778 MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN); 779 780 /* reg_spms_local_port 781 * Local port number. 782 * Access: Index 783 */ 784 MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8); 785 786 enum mlxsw_reg_spms_state { 787 MLXSW_REG_SPMS_STATE_NO_CHANGE, 788 MLXSW_REG_SPMS_STATE_DISCARDING, 789 MLXSW_REG_SPMS_STATE_LEARNING, 790 MLXSW_REG_SPMS_STATE_FORWARDING, 791 }; 792 793 /* reg_spms_state 794 * Spanning tree state of each VLAN ID (VID) of the local port. 795 * 0 - Do not change spanning tree state (used only when writing). 796 * 1 - Discarding. No learning or forwarding to/from this port (default). 797 * 2 - Learning. Port is learning, but not forwarding. 798 * 3 - Forwarding. Port is learning and forwarding. 799 * Access: RW 800 */ 801 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2); 802 803 static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port) 804 { 805 MLXSW_REG_ZERO(spms, payload); 806 mlxsw_reg_spms_local_port_set(payload, local_port); 807 } 808 809 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid, 810 enum mlxsw_reg_spms_state state) 811 { 812 mlxsw_reg_spms_state_set(payload, vid, state); 813 } 814 815 /* SPVID - Switch Port VID 816 * ----------------------- 817 * The switch port VID configures the default VID for a port. 818 */ 819 #define MLXSW_REG_SPVID_ID 0x200E 820 #define MLXSW_REG_SPVID_LEN 0x08 821 822 MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN); 823 824 /* reg_spvid_local_port 825 * Local port number. 826 * Access: Index 827 */ 828 MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8); 829 830 /* reg_spvid_sub_port 831 * Virtual port within the physical port. 832 * Should be set to 0 when virtual ports are not enabled on the port. 833 * Access: Index 834 */ 835 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8); 836 837 /* reg_spvid_pvid 838 * Port default VID 839 * Access: RW 840 */ 841 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12); 842 843 static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid) 844 { 845 MLXSW_REG_ZERO(spvid, payload); 846 mlxsw_reg_spvid_local_port_set(payload, local_port); 847 mlxsw_reg_spvid_pvid_set(payload, pvid); 848 } 849 850 /* SPVM - Switch Port VLAN Membership 851 * ---------------------------------- 852 * The Switch Port VLAN Membership register configures the VLAN membership 853 * of a port in a VLAN denoted by VID. VLAN membership is managed per 854 * virtual port. The register can be used to add and remove VID(s) from a port. 855 */ 856 #define MLXSW_REG_SPVM_ID 0x200F 857 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */ 858 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */ 859 #define MLXSW_REG_SPVM_REC_MAX_COUNT 255 860 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \ 861 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT) 862 863 MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN); 864 865 /* reg_spvm_pt 866 * Priority tagged. If this bit is set, packets forwarded to the port with 867 * untagged VLAN membership (u bit is set) will be tagged with priority tag 868 * (VID=0) 869 * Access: RW 870 */ 871 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1); 872 873 /* reg_spvm_pte 874 * Priority Tagged Update Enable. On Write operations, if this bit is cleared, 875 * the pt bit will NOT be updated. To update the pt bit, pte must be set. 876 * Access: WO 877 */ 878 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1); 879 880 /* reg_spvm_local_port 881 * Local port number. 882 * Access: Index 883 */ 884 MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8); 885 886 /* reg_spvm_sub_port 887 * Virtual port within the physical port. 888 * Should be set to 0 when virtual ports are not enabled on the port. 889 * Access: Index 890 */ 891 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8); 892 893 /* reg_spvm_num_rec 894 * Number of records to update. Each record contains: i, e, u, vid. 895 * Access: OP 896 */ 897 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8); 898 899 /* reg_spvm_rec_i 900 * Ingress membership in VLAN ID. 901 * Access: Index 902 */ 903 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i, 904 MLXSW_REG_SPVM_BASE_LEN, 14, 1, 905 MLXSW_REG_SPVM_REC_LEN, 0, false); 906 907 /* reg_spvm_rec_e 908 * Egress membership in VLAN ID. 909 * Access: Index 910 */ 911 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e, 912 MLXSW_REG_SPVM_BASE_LEN, 13, 1, 913 MLXSW_REG_SPVM_REC_LEN, 0, false); 914 915 /* reg_spvm_rec_u 916 * Untagged - port is an untagged member - egress transmission uses untagged 917 * frames on VID<n> 918 * Access: Index 919 */ 920 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u, 921 MLXSW_REG_SPVM_BASE_LEN, 12, 1, 922 MLXSW_REG_SPVM_REC_LEN, 0, false); 923 924 /* reg_spvm_rec_vid 925 * Egress membership in VLAN ID. 926 * Access: Index 927 */ 928 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid, 929 MLXSW_REG_SPVM_BASE_LEN, 0, 12, 930 MLXSW_REG_SPVM_REC_LEN, 0, false); 931 932 static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port, 933 u16 vid_begin, u16 vid_end, 934 bool is_member, bool untagged) 935 { 936 int size = vid_end - vid_begin + 1; 937 int i; 938 939 MLXSW_REG_ZERO(spvm, payload); 940 mlxsw_reg_spvm_local_port_set(payload, local_port); 941 mlxsw_reg_spvm_num_rec_set(payload, size); 942 943 for (i = 0; i < size; i++) { 944 mlxsw_reg_spvm_rec_i_set(payload, i, is_member); 945 mlxsw_reg_spvm_rec_e_set(payload, i, is_member); 946 mlxsw_reg_spvm_rec_u_set(payload, i, untagged); 947 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i); 948 } 949 } 950 951 /* SPAFT - Switch Port Acceptable Frame Types 952 * ------------------------------------------ 953 * The Switch Port Acceptable Frame Types register configures the frame 954 * admittance of the port. 955 */ 956 #define MLXSW_REG_SPAFT_ID 0x2010 957 #define MLXSW_REG_SPAFT_LEN 0x08 958 959 MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN); 960 961 /* reg_spaft_local_port 962 * Local port number. 963 * Access: Index 964 * 965 * Note: CPU port is not supported (all tag types are allowed). 966 */ 967 MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8); 968 969 /* reg_spaft_sub_port 970 * Virtual port within the physical port. 971 * Should be set to 0 when virtual ports are not enabled on the port. 972 * Access: RW 973 */ 974 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8); 975 976 /* reg_spaft_allow_untagged 977 * When set, untagged frames on the ingress are allowed (default). 978 * Access: RW 979 */ 980 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1); 981 982 /* reg_spaft_allow_prio_tagged 983 * When set, priority tagged frames on the ingress are allowed (default). 984 * Access: RW 985 */ 986 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1); 987 988 /* reg_spaft_allow_tagged 989 * When set, tagged frames on the ingress are allowed (default). 990 * Access: RW 991 */ 992 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1); 993 994 static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port, 995 bool allow_untagged) 996 { 997 MLXSW_REG_ZERO(spaft, payload); 998 mlxsw_reg_spaft_local_port_set(payload, local_port); 999 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged); 1000 mlxsw_reg_spaft_allow_prio_tagged_set(payload, true); 1001 mlxsw_reg_spaft_allow_tagged_set(payload, true); 1002 } 1003 1004 /* SFGC - Switch Flooding Group Configuration 1005 * ------------------------------------------ 1006 * The following register controls the association of flooding tables and MIDs 1007 * to packet types used for flooding. 1008 */ 1009 #define MLXSW_REG_SFGC_ID 0x2011 1010 #define MLXSW_REG_SFGC_LEN 0x10 1011 1012 MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN); 1013 1014 enum mlxsw_reg_sfgc_type { 1015 MLXSW_REG_SFGC_TYPE_BROADCAST, 1016 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST, 1017 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4, 1018 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6, 1019 MLXSW_REG_SFGC_TYPE_RESERVED, 1020 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP, 1021 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL, 1022 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST, 1023 MLXSW_REG_SFGC_TYPE_MAX, 1024 }; 1025 1026 /* reg_sfgc_type 1027 * The traffic type to reach the flooding table. 1028 * Access: Index 1029 */ 1030 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4); 1031 1032 enum mlxsw_reg_sfgc_bridge_type { 1033 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0, 1034 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1, 1035 }; 1036 1037 /* reg_sfgc_bridge_type 1038 * Access: Index 1039 * 1040 * Note: SwitchX-2 only supports 802.1Q mode. 1041 */ 1042 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3); 1043 1044 enum mlxsw_flood_table_type { 1045 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1, 1046 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2, 1047 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0, 1048 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3, 1049 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4, 1050 }; 1051 1052 /* reg_sfgc_table_type 1053 * See mlxsw_flood_table_type 1054 * Access: RW 1055 * 1056 * Note: FID offset and FID types are not supported in SwitchX-2. 1057 */ 1058 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3); 1059 1060 /* reg_sfgc_flood_table 1061 * Flooding table index to associate with the specific type on the specific 1062 * switch partition. 1063 * Access: RW 1064 */ 1065 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6); 1066 1067 /* reg_sfgc_mid 1068 * The multicast ID for the swid. Not supported for Spectrum 1069 * Access: RW 1070 */ 1071 MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16); 1072 1073 /* reg_sfgc_counter_set_type 1074 * Counter Set Type for flow counters. 1075 * Access: RW 1076 */ 1077 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8); 1078 1079 /* reg_sfgc_counter_index 1080 * Counter Index for flow counters. 1081 * Access: RW 1082 */ 1083 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24); 1084 1085 static inline void 1086 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type, 1087 enum mlxsw_reg_sfgc_bridge_type bridge_type, 1088 enum mlxsw_flood_table_type table_type, 1089 unsigned int flood_table) 1090 { 1091 MLXSW_REG_ZERO(sfgc, payload); 1092 mlxsw_reg_sfgc_type_set(payload, type); 1093 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type); 1094 mlxsw_reg_sfgc_table_type_set(payload, table_type); 1095 mlxsw_reg_sfgc_flood_table_set(payload, flood_table); 1096 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID); 1097 } 1098 1099 /* SFTR - Switch Flooding Table Register 1100 * ------------------------------------- 1101 * The switch flooding table is used for flooding packet replication. The table 1102 * defines a bit mask of ports for packet replication. 1103 */ 1104 #define MLXSW_REG_SFTR_ID 0x2012 1105 #define MLXSW_REG_SFTR_LEN 0x420 1106 1107 MLXSW_REG_DEFINE(sftr, MLXSW_REG_SFTR_ID, MLXSW_REG_SFTR_LEN); 1108 1109 /* reg_sftr_swid 1110 * Switch partition ID with which to associate the port. 1111 * Access: Index 1112 */ 1113 MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8); 1114 1115 /* reg_sftr_flood_table 1116 * Flooding table index to associate with the specific type on the specific 1117 * switch partition. 1118 * Access: Index 1119 */ 1120 MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6); 1121 1122 /* reg_sftr_index 1123 * Index. Used as an index into the Flooding Table in case the table is 1124 * configured to use VID / FID or FID Offset. 1125 * Access: Index 1126 */ 1127 MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16); 1128 1129 /* reg_sftr_table_type 1130 * See mlxsw_flood_table_type 1131 * Access: RW 1132 */ 1133 MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3); 1134 1135 /* reg_sftr_range 1136 * Range of entries to update 1137 * Access: Index 1138 */ 1139 MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16); 1140 1141 /* reg_sftr_port 1142 * Local port membership (1 bit per port). 1143 * Access: RW 1144 */ 1145 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1); 1146 1147 /* reg_sftr_cpu_port_mask 1148 * CPU port mask (1 bit per port). 1149 * Access: W 1150 */ 1151 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1); 1152 1153 static inline void mlxsw_reg_sftr_pack(char *payload, 1154 unsigned int flood_table, 1155 unsigned int index, 1156 enum mlxsw_flood_table_type table_type, 1157 unsigned int range, u8 port, bool set) 1158 { 1159 MLXSW_REG_ZERO(sftr, payload); 1160 mlxsw_reg_sftr_swid_set(payload, 0); 1161 mlxsw_reg_sftr_flood_table_set(payload, flood_table); 1162 mlxsw_reg_sftr_index_set(payload, index); 1163 mlxsw_reg_sftr_table_type_set(payload, table_type); 1164 mlxsw_reg_sftr_range_set(payload, range); 1165 mlxsw_reg_sftr_port_set(payload, port, set); 1166 mlxsw_reg_sftr_port_mask_set(payload, port, 1); 1167 } 1168 1169 /* SFDF - Switch Filtering DB Flush 1170 * -------------------------------- 1171 * The switch filtering DB flush register is used to flush the FDB. 1172 * Note that FDB notifications are flushed as well. 1173 */ 1174 #define MLXSW_REG_SFDF_ID 0x2013 1175 #define MLXSW_REG_SFDF_LEN 0x14 1176 1177 MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN); 1178 1179 /* reg_sfdf_swid 1180 * Switch partition ID. 1181 * Access: Index 1182 */ 1183 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8); 1184 1185 enum mlxsw_reg_sfdf_flush_type { 1186 MLXSW_REG_SFDF_FLUSH_PER_SWID, 1187 MLXSW_REG_SFDF_FLUSH_PER_FID, 1188 MLXSW_REG_SFDF_FLUSH_PER_PORT, 1189 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID, 1190 MLXSW_REG_SFDF_FLUSH_PER_LAG, 1191 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID, 1192 MLXSW_REG_SFDF_FLUSH_PER_NVE, 1193 MLXSW_REG_SFDF_FLUSH_PER_NVE_AND_FID, 1194 }; 1195 1196 /* reg_sfdf_flush_type 1197 * Flush type. 1198 * 0 - All SWID dynamic entries are flushed. 1199 * 1 - All FID dynamic entries are flushed. 1200 * 2 - All dynamic entries pointing to port are flushed. 1201 * 3 - All FID dynamic entries pointing to port are flushed. 1202 * 4 - All dynamic entries pointing to LAG are flushed. 1203 * 5 - All FID dynamic entries pointing to LAG are flushed. 1204 * 6 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1205 * flushed. 1206 * 7 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1207 * flushed, per FID. 1208 * Access: RW 1209 */ 1210 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4); 1211 1212 /* reg_sfdf_flush_static 1213 * Static. 1214 * 0 - Flush only dynamic entries. 1215 * 1 - Flush both dynamic and static entries. 1216 * Access: RW 1217 */ 1218 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1); 1219 1220 static inline void mlxsw_reg_sfdf_pack(char *payload, 1221 enum mlxsw_reg_sfdf_flush_type type) 1222 { 1223 MLXSW_REG_ZERO(sfdf, payload); 1224 mlxsw_reg_sfdf_flush_type_set(payload, type); 1225 mlxsw_reg_sfdf_flush_static_set(payload, true); 1226 } 1227 1228 /* reg_sfdf_fid 1229 * FID to flush. 1230 * Access: RW 1231 */ 1232 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16); 1233 1234 /* reg_sfdf_system_port 1235 * Port to flush. 1236 * Access: RW 1237 */ 1238 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16); 1239 1240 /* reg_sfdf_port_fid_system_port 1241 * Port to flush, pointed to by FID. 1242 * Access: RW 1243 */ 1244 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16); 1245 1246 /* reg_sfdf_lag_id 1247 * LAG ID to flush. 1248 * Access: RW 1249 */ 1250 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10); 1251 1252 /* reg_sfdf_lag_fid_lag_id 1253 * LAG ID to flush, pointed to by FID. 1254 * Access: RW 1255 */ 1256 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10); 1257 1258 /* SLDR - Switch LAG Descriptor Register 1259 * ----------------------------------------- 1260 * The switch LAG descriptor register is populated by LAG descriptors. 1261 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to 1262 * max_lag-1. 1263 */ 1264 #define MLXSW_REG_SLDR_ID 0x2014 1265 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */ 1266 1267 MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN); 1268 1269 enum mlxsw_reg_sldr_op { 1270 /* Indicates a creation of a new LAG-ID, lag_id must be valid */ 1271 MLXSW_REG_SLDR_OP_LAG_CREATE, 1272 MLXSW_REG_SLDR_OP_LAG_DESTROY, 1273 /* Ports that appear in the list have the Distributor enabled */ 1274 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST, 1275 /* Removes ports from the disributor list */ 1276 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST, 1277 }; 1278 1279 /* reg_sldr_op 1280 * Operation. 1281 * Access: RW 1282 */ 1283 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3); 1284 1285 /* reg_sldr_lag_id 1286 * LAG identifier. The lag_id is the index into the LAG descriptor table. 1287 * Access: Index 1288 */ 1289 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10); 1290 1291 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id) 1292 { 1293 MLXSW_REG_ZERO(sldr, payload); 1294 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE); 1295 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1296 } 1297 1298 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id) 1299 { 1300 MLXSW_REG_ZERO(sldr, payload); 1301 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY); 1302 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1303 } 1304 1305 /* reg_sldr_num_ports 1306 * The number of member ports of the LAG. 1307 * Reserved for Create / Destroy operations 1308 * For Add / Remove operations - indicates the number of ports in the list. 1309 * Access: RW 1310 */ 1311 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8); 1312 1313 /* reg_sldr_system_port 1314 * System port. 1315 * Access: RW 1316 */ 1317 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false); 1318 1319 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id, 1320 u8 local_port) 1321 { 1322 MLXSW_REG_ZERO(sldr, payload); 1323 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST); 1324 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1325 mlxsw_reg_sldr_num_ports_set(payload, 1); 1326 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1327 } 1328 1329 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id, 1330 u8 local_port) 1331 { 1332 MLXSW_REG_ZERO(sldr, payload); 1333 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST); 1334 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1335 mlxsw_reg_sldr_num_ports_set(payload, 1); 1336 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1337 } 1338 1339 /* SLCR - Switch LAG Configuration 2 Register 1340 * ------------------------------------------- 1341 * The Switch LAG Configuration register is used for configuring the 1342 * LAG properties of the switch. 1343 */ 1344 #define MLXSW_REG_SLCR_ID 0x2015 1345 #define MLXSW_REG_SLCR_LEN 0x10 1346 1347 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN); 1348 1349 enum mlxsw_reg_slcr_pp { 1350 /* Global Configuration (for all ports) */ 1351 MLXSW_REG_SLCR_PP_GLOBAL, 1352 /* Per port configuration, based on local_port field */ 1353 MLXSW_REG_SLCR_PP_PER_PORT, 1354 }; 1355 1356 /* reg_slcr_pp 1357 * Per Port Configuration 1358 * Note: Reading at Global mode results in reading port 1 configuration. 1359 * Access: Index 1360 */ 1361 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1); 1362 1363 /* reg_slcr_local_port 1364 * Local port number 1365 * Supported from CPU port 1366 * Not supported from router port 1367 * Reserved when pp = Global Configuration 1368 * Access: Index 1369 */ 1370 MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8); 1371 1372 enum mlxsw_reg_slcr_type { 1373 MLXSW_REG_SLCR_TYPE_CRC, /* default */ 1374 MLXSW_REG_SLCR_TYPE_XOR, 1375 MLXSW_REG_SLCR_TYPE_RANDOM, 1376 }; 1377 1378 /* reg_slcr_type 1379 * Hash type 1380 * Access: RW 1381 */ 1382 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4); 1383 1384 /* Ingress port */ 1385 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0) 1386 /* SMAC - for IPv4 and IPv6 packets */ 1387 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1) 1388 /* SMAC - for non-IP packets */ 1389 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2) 1390 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \ 1391 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \ 1392 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP) 1393 /* DMAC - for IPv4 and IPv6 packets */ 1394 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3) 1395 /* DMAC - for non-IP packets */ 1396 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4) 1397 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \ 1398 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \ 1399 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP) 1400 /* Ethertype - for IPv4 and IPv6 packets */ 1401 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5) 1402 /* Ethertype - for non-IP packets */ 1403 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6) 1404 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \ 1405 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \ 1406 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP) 1407 /* VLAN ID - for IPv4 and IPv6 packets */ 1408 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7) 1409 /* VLAN ID - for non-IP packets */ 1410 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8) 1411 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \ 1412 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \ 1413 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP) 1414 /* Source IP address (can be IPv4 or IPv6) */ 1415 #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9) 1416 /* Destination IP address (can be IPv4 or IPv6) */ 1417 #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10) 1418 /* TCP/UDP source port */ 1419 #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11) 1420 /* TCP/UDP destination port*/ 1421 #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12) 1422 /* IPv4 Protocol/IPv6 Next Header */ 1423 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13) 1424 /* IPv6 Flow label */ 1425 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14) 1426 /* SID - FCoE source ID */ 1427 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15) 1428 /* DID - FCoE destination ID */ 1429 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16) 1430 /* OXID - FCoE originator exchange ID */ 1431 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17) 1432 /* Destination QP number - for RoCE packets */ 1433 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19) 1434 1435 /* reg_slcr_lag_hash 1436 * LAG hashing configuration. This is a bitmask, in which each set 1437 * bit includes the corresponding item in the LAG hash calculation. 1438 * The default lag_hash contains SMAC, DMAC, VLANID and 1439 * Ethertype (for all packet types). 1440 * Access: RW 1441 */ 1442 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20); 1443 1444 /* reg_slcr_seed 1445 * LAG seed value. The seed is the same for all ports. 1446 * Access: RW 1447 */ 1448 MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32); 1449 1450 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed) 1451 { 1452 MLXSW_REG_ZERO(slcr, payload); 1453 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL); 1454 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC); 1455 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash); 1456 mlxsw_reg_slcr_seed_set(payload, seed); 1457 } 1458 1459 /* SLCOR - Switch LAG Collector Register 1460 * ------------------------------------- 1461 * The Switch LAG Collector register controls the Local Port membership 1462 * in a LAG and enablement of the collector. 1463 */ 1464 #define MLXSW_REG_SLCOR_ID 0x2016 1465 #define MLXSW_REG_SLCOR_LEN 0x10 1466 1467 MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN); 1468 1469 enum mlxsw_reg_slcor_col { 1470 /* Port is added with collector disabled */ 1471 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT, 1472 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED, 1473 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED, 1474 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT, 1475 }; 1476 1477 /* reg_slcor_col 1478 * Collector configuration 1479 * Access: RW 1480 */ 1481 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2); 1482 1483 /* reg_slcor_local_port 1484 * Local port number 1485 * Not supported for CPU port 1486 * Access: Index 1487 */ 1488 MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8); 1489 1490 /* reg_slcor_lag_id 1491 * LAG Identifier. Index into the LAG descriptor table. 1492 * Access: Index 1493 */ 1494 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10); 1495 1496 /* reg_slcor_port_index 1497 * Port index in the LAG list. Only valid on Add Port to LAG col. 1498 * Valid range is from 0 to cap_max_lag_members-1 1499 * Access: RW 1500 */ 1501 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10); 1502 1503 static inline void mlxsw_reg_slcor_pack(char *payload, 1504 u8 local_port, u16 lag_id, 1505 enum mlxsw_reg_slcor_col col) 1506 { 1507 MLXSW_REG_ZERO(slcor, payload); 1508 mlxsw_reg_slcor_col_set(payload, col); 1509 mlxsw_reg_slcor_local_port_set(payload, local_port); 1510 mlxsw_reg_slcor_lag_id_set(payload, lag_id); 1511 } 1512 1513 static inline void mlxsw_reg_slcor_port_add_pack(char *payload, 1514 u8 local_port, u16 lag_id, 1515 u8 port_index) 1516 { 1517 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1518 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT); 1519 mlxsw_reg_slcor_port_index_set(payload, port_index); 1520 } 1521 1522 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload, 1523 u8 local_port, u16 lag_id) 1524 { 1525 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1526 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT); 1527 } 1528 1529 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload, 1530 u8 local_port, u16 lag_id) 1531 { 1532 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1533 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1534 } 1535 1536 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload, 1537 u8 local_port, u16 lag_id) 1538 { 1539 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1540 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1541 } 1542 1543 /* SPMLR - Switch Port MAC Learning Register 1544 * ----------------------------------------- 1545 * Controls the Switch MAC learning policy per port. 1546 */ 1547 #define MLXSW_REG_SPMLR_ID 0x2018 1548 #define MLXSW_REG_SPMLR_LEN 0x8 1549 1550 MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN); 1551 1552 /* reg_spmlr_local_port 1553 * Local port number. 1554 * Access: Index 1555 */ 1556 MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8); 1557 1558 /* reg_spmlr_sub_port 1559 * Virtual port within the physical port. 1560 * Should be set to 0 when virtual ports are not enabled on the port. 1561 * Access: Index 1562 */ 1563 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8); 1564 1565 enum mlxsw_reg_spmlr_learn_mode { 1566 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0, 1567 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2, 1568 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3, 1569 }; 1570 1571 /* reg_spmlr_learn_mode 1572 * Learning mode on the port. 1573 * 0 - Learning disabled. 1574 * 2 - Learning enabled. 1575 * 3 - Security mode. 1576 * 1577 * In security mode the switch does not learn MACs on the port, but uses the 1578 * SMAC to see if it exists on another ingress port. If so, the packet is 1579 * classified as a bad packet and is discarded unless the software registers 1580 * to receive port security error packets usign HPKT. 1581 */ 1582 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2); 1583 1584 static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port, 1585 enum mlxsw_reg_spmlr_learn_mode mode) 1586 { 1587 MLXSW_REG_ZERO(spmlr, payload); 1588 mlxsw_reg_spmlr_local_port_set(payload, local_port); 1589 mlxsw_reg_spmlr_sub_port_set(payload, 0); 1590 mlxsw_reg_spmlr_learn_mode_set(payload, mode); 1591 } 1592 1593 /* SVFA - Switch VID to FID Allocation Register 1594 * -------------------------------------------- 1595 * Controls the VID to FID mapping and {Port, VID} to FID mapping for 1596 * virtualized ports. 1597 */ 1598 #define MLXSW_REG_SVFA_ID 0x201C 1599 #define MLXSW_REG_SVFA_LEN 0x10 1600 1601 MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN); 1602 1603 /* reg_svfa_swid 1604 * Switch partition ID. 1605 * Access: Index 1606 */ 1607 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8); 1608 1609 /* reg_svfa_local_port 1610 * Local port number. 1611 * Access: Index 1612 * 1613 * Note: Reserved for 802.1Q FIDs. 1614 */ 1615 MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8); 1616 1617 enum mlxsw_reg_svfa_mt { 1618 MLXSW_REG_SVFA_MT_VID_TO_FID, 1619 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, 1620 }; 1621 1622 /* reg_svfa_mapping_table 1623 * Mapping table: 1624 * 0 - VID to FID 1625 * 1 - {Port, VID} to FID 1626 * Access: Index 1627 * 1628 * Note: Reserved for SwitchX-2. 1629 */ 1630 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3); 1631 1632 /* reg_svfa_v 1633 * Valid. 1634 * Valid if set. 1635 * Access: RW 1636 * 1637 * Note: Reserved for SwitchX-2. 1638 */ 1639 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1); 1640 1641 /* reg_svfa_fid 1642 * Filtering ID. 1643 * Access: RW 1644 */ 1645 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16); 1646 1647 /* reg_svfa_vid 1648 * VLAN ID. 1649 * Access: Index 1650 */ 1651 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12); 1652 1653 /* reg_svfa_counter_set_type 1654 * Counter set type for flow counters. 1655 * Access: RW 1656 * 1657 * Note: Reserved for SwitchX-2. 1658 */ 1659 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8); 1660 1661 /* reg_svfa_counter_index 1662 * Counter index for flow counters. 1663 * Access: RW 1664 * 1665 * Note: Reserved for SwitchX-2. 1666 */ 1667 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24); 1668 1669 static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port, 1670 enum mlxsw_reg_svfa_mt mt, bool valid, 1671 u16 fid, u16 vid) 1672 { 1673 MLXSW_REG_ZERO(svfa, payload); 1674 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port; 1675 mlxsw_reg_svfa_swid_set(payload, 0); 1676 mlxsw_reg_svfa_local_port_set(payload, local_port); 1677 mlxsw_reg_svfa_mapping_table_set(payload, mt); 1678 mlxsw_reg_svfa_v_set(payload, valid); 1679 mlxsw_reg_svfa_fid_set(payload, fid); 1680 mlxsw_reg_svfa_vid_set(payload, vid); 1681 } 1682 1683 /* SVPE - Switch Virtual-Port Enabling Register 1684 * -------------------------------------------- 1685 * Enables port virtualization. 1686 */ 1687 #define MLXSW_REG_SVPE_ID 0x201E 1688 #define MLXSW_REG_SVPE_LEN 0x4 1689 1690 MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN); 1691 1692 /* reg_svpe_local_port 1693 * Local port number 1694 * Access: Index 1695 * 1696 * Note: CPU port is not supported (uses VLAN mode only). 1697 */ 1698 MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8); 1699 1700 /* reg_svpe_vp_en 1701 * Virtual port enable. 1702 * 0 - Disable, VLAN mode (VID to FID). 1703 * 1 - Enable, Virtual port mode ({Port, VID} to FID). 1704 * Access: RW 1705 */ 1706 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1); 1707 1708 static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port, 1709 bool enable) 1710 { 1711 MLXSW_REG_ZERO(svpe, payload); 1712 mlxsw_reg_svpe_local_port_set(payload, local_port); 1713 mlxsw_reg_svpe_vp_en_set(payload, enable); 1714 } 1715 1716 /* SFMR - Switch FID Management Register 1717 * ------------------------------------- 1718 * Creates and configures FIDs. 1719 */ 1720 #define MLXSW_REG_SFMR_ID 0x201F 1721 #define MLXSW_REG_SFMR_LEN 0x18 1722 1723 MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN); 1724 1725 enum mlxsw_reg_sfmr_op { 1726 MLXSW_REG_SFMR_OP_CREATE_FID, 1727 MLXSW_REG_SFMR_OP_DESTROY_FID, 1728 }; 1729 1730 /* reg_sfmr_op 1731 * Operation. 1732 * 0 - Create or edit FID. 1733 * 1 - Destroy FID. 1734 * Access: WO 1735 */ 1736 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4); 1737 1738 /* reg_sfmr_fid 1739 * Filtering ID. 1740 * Access: Index 1741 */ 1742 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16); 1743 1744 /* reg_sfmr_fid_offset 1745 * FID offset. 1746 * Used to point into the flooding table selected by SFGC register if 1747 * the table is of type FID-Offset. Otherwise, this field is reserved. 1748 * Access: RW 1749 */ 1750 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16); 1751 1752 /* reg_sfmr_vtfp 1753 * Valid Tunnel Flood Pointer. 1754 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL. 1755 * Access: RW 1756 * 1757 * Note: Reserved for 802.1Q FIDs. 1758 */ 1759 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1); 1760 1761 /* reg_sfmr_nve_tunnel_flood_ptr 1762 * Underlay Flooding and BC Pointer. 1763 * Used as a pointer to the first entry of the group based link lists of 1764 * flooding or BC entries (for NVE tunnels). 1765 * Access: RW 1766 */ 1767 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24); 1768 1769 /* reg_sfmr_vv 1770 * VNI Valid. 1771 * If not set, then vni is reserved. 1772 * Access: RW 1773 * 1774 * Note: Reserved for 802.1Q FIDs. 1775 */ 1776 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1); 1777 1778 /* reg_sfmr_vni 1779 * Virtual Network Identifier. 1780 * Access: RW 1781 * 1782 * Note: A given VNI can only be assigned to one FID. 1783 */ 1784 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24); 1785 1786 static inline void mlxsw_reg_sfmr_pack(char *payload, 1787 enum mlxsw_reg_sfmr_op op, u16 fid, 1788 u16 fid_offset) 1789 { 1790 MLXSW_REG_ZERO(sfmr, payload); 1791 mlxsw_reg_sfmr_op_set(payload, op); 1792 mlxsw_reg_sfmr_fid_set(payload, fid); 1793 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset); 1794 mlxsw_reg_sfmr_vtfp_set(payload, false); 1795 mlxsw_reg_sfmr_vv_set(payload, false); 1796 } 1797 1798 /* SPVMLR - Switch Port VLAN MAC Learning Register 1799 * ----------------------------------------------- 1800 * Controls the switch MAC learning policy per {Port, VID}. 1801 */ 1802 #define MLXSW_REG_SPVMLR_ID 0x2020 1803 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */ 1804 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */ 1805 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255 1806 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \ 1807 MLXSW_REG_SPVMLR_REC_LEN * \ 1808 MLXSW_REG_SPVMLR_REC_MAX_COUNT) 1809 1810 MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN); 1811 1812 /* reg_spvmlr_local_port 1813 * Local ingress port. 1814 * Access: Index 1815 * 1816 * Note: CPU port is not supported. 1817 */ 1818 MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8); 1819 1820 /* reg_spvmlr_num_rec 1821 * Number of records to update. 1822 * Access: OP 1823 */ 1824 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8); 1825 1826 /* reg_spvmlr_rec_learn_enable 1827 * 0 - Disable learning for {Port, VID}. 1828 * 1 - Enable learning for {Port, VID}. 1829 * Access: RW 1830 */ 1831 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN, 1832 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1833 1834 /* reg_spvmlr_rec_vid 1835 * VLAN ID to be added/removed from port or for querying. 1836 * Access: Index 1837 */ 1838 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12, 1839 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1840 1841 static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port, 1842 u16 vid_begin, u16 vid_end, 1843 bool learn_enable) 1844 { 1845 int num_rec = vid_end - vid_begin + 1; 1846 int i; 1847 1848 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT); 1849 1850 MLXSW_REG_ZERO(spvmlr, payload); 1851 mlxsw_reg_spvmlr_local_port_set(payload, local_port); 1852 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec); 1853 1854 for (i = 0; i < num_rec; i++) { 1855 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable); 1856 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i); 1857 } 1858 } 1859 1860 /* CWTP - Congetion WRED ECN TClass Profile 1861 * ---------------------------------------- 1862 * Configures the profiles for queues of egress port and traffic class 1863 */ 1864 #define MLXSW_REG_CWTP_ID 0x2802 1865 #define MLXSW_REG_CWTP_BASE_LEN 0x28 1866 #define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08 1867 #define MLXSW_REG_CWTP_LEN 0x40 1868 1869 MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN); 1870 1871 /* reg_cwtp_local_port 1872 * Local port number 1873 * Not supported for CPU port 1874 * Access: Index 1875 */ 1876 MLXSW_ITEM32(reg, cwtp, local_port, 0, 16, 8); 1877 1878 /* reg_cwtp_traffic_class 1879 * Traffic Class to configure 1880 * Access: Index 1881 */ 1882 MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8); 1883 1884 /* reg_cwtp_profile_min 1885 * Minimum Average Queue Size of the profile in cells. 1886 * Access: RW 1887 */ 1888 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN, 1889 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false); 1890 1891 /* reg_cwtp_profile_percent 1892 * Percentage of WRED and ECN marking for maximum Average Queue size 1893 * Range is 0 to 100, units of integer percentage 1894 * Access: RW 1895 */ 1896 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN, 1897 24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 1898 1899 /* reg_cwtp_profile_max 1900 * Maximum Average Queue size of the profile in cells 1901 * Access: RW 1902 */ 1903 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN, 1904 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 1905 1906 #define MLXSW_REG_CWTP_MIN_VALUE 64 1907 #define MLXSW_REG_CWTP_MAX_PROFILE 2 1908 #define MLXSW_REG_CWTP_DEFAULT_PROFILE 1 1909 1910 static inline void mlxsw_reg_cwtp_pack(char *payload, u8 local_port, 1911 u8 traffic_class) 1912 { 1913 int i; 1914 1915 MLXSW_REG_ZERO(cwtp, payload); 1916 mlxsw_reg_cwtp_local_port_set(payload, local_port); 1917 mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class); 1918 1919 for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) { 1920 mlxsw_reg_cwtp_profile_min_set(payload, i, 1921 MLXSW_REG_CWTP_MIN_VALUE); 1922 mlxsw_reg_cwtp_profile_max_set(payload, i, 1923 MLXSW_REG_CWTP_MIN_VALUE); 1924 } 1925 } 1926 1927 #define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1) 1928 1929 static inline void 1930 mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max, 1931 u32 probability) 1932 { 1933 u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile); 1934 1935 mlxsw_reg_cwtp_profile_min_set(payload, index, min); 1936 mlxsw_reg_cwtp_profile_max_set(payload, index, max); 1937 mlxsw_reg_cwtp_profile_percent_set(payload, index, probability); 1938 } 1939 1940 /* CWTPM - Congestion WRED ECN TClass and Pool Mapping 1941 * --------------------------------------------------- 1942 * The CWTPM register maps each egress port and traffic class to profile num. 1943 */ 1944 #define MLXSW_REG_CWTPM_ID 0x2803 1945 #define MLXSW_REG_CWTPM_LEN 0x44 1946 1947 MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN); 1948 1949 /* reg_cwtpm_local_port 1950 * Local port number 1951 * Not supported for CPU port 1952 * Access: Index 1953 */ 1954 MLXSW_ITEM32(reg, cwtpm, local_port, 0, 16, 8); 1955 1956 /* reg_cwtpm_traffic_class 1957 * Traffic Class to configure 1958 * Access: Index 1959 */ 1960 MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8); 1961 1962 /* reg_cwtpm_ew 1963 * Control enablement of WRED for traffic class: 1964 * 0 - Disable 1965 * 1 - Enable 1966 * Access: RW 1967 */ 1968 MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1); 1969 1970 /* reg_cwtpm_ee 1971 * Control enablement of ECN for traffic class: 1972 * 0 - Disable 1973 * 1 - Enable 1974 * Access: RW 1975 */ 1976 MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1); 1977 1978 /* reg_cwtpm_tcp_g 1979 * TCP Green Profile. 1980 * Index of the profile within {port, traffic class} to use. 1981 * 0 for disabling both WRED and ECN for this type of traffic. 1982 * Access: RW 1983 */ 1984 MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2); 1985 1986 /* reg_cwtpm_tcp_y 1987 * TCP Yellow Profile. 1988 * Index of the profile within {port, traffic class} to use. 1989 * 0 for disabling both WRED and ECN for this type of traffic. 1990 * Access: RW 1991 */ 1992 MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2); 1993 1994 /* reg_cwtpm_tcp_r 1995 * TCP Red Profile. 1996 * Index of the profile within {port, traffic class} to use. 1997 * 0 for disabling both WRED and ECN for this type of traffic. 1998 * Access: RW 1999 */ 2000 MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2); 2001 2002 /* reg_cwtpm_ntcp_g 2003 * Non-TCP Green Profile. 2004 * Index of the profile within {port, traffic class} to use. 2005 * 0 for disabling both WRED and ECN for this type of traffic. 2006 * Access: RW 2007 */ 2008 MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2); 2009 2010 /* reg_cwtpm_ntcp_y 2011 * Non-TCP Yellow Profile. 2012 * Index of the profile within {port, traffic class} to use. 2013 * 0 for disabling both WRED and ECN for this type of traffic. 2014 * Access: RW 2015 */ 2016 MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2); 2017 2018 /* reg_cwtpm_ntcp_r 2019 * Non-TCP Red Profile. 2020 * Index of the profile within {port, traffic class} to use. 2021 * 0 for disabling both WRED and ECN for this type of traffic. 2022 * Access: RW 2023 */ 2024 MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2); 2025 2026 #define MLXSW_REG_CWTPM_RESET_PROFILE 0 2027 2028 static inline void mlxsw_reg_cwtpm_pack(char *payload, u8 local_port, 2029 u8 traffic_class, u8 profile, 2030 bool wred, bool ecn) 2031 { 2032 MLXSW_REG_ZERO(cwtpm, payload); 2033 mlxsw_reg_cwtpm_local_port_set(payload, local_port); 2034 mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class); 2035 mlxsw_reg_cwtpm_ew_set(payload, wred); 2036 mlxsw_reg_cwtpm_ee_set(payload, ecn); 2037 mlxsw_reg_cwtpm_tcp_g_set(payload, profile); 2038 mlxsw_reg_cwtpm_tcp_y_set(payload, profile); 2039 mlxsw_reg_cwtpm_tcp_r_set(payload, profile); 2040 mlxsw_reg_cwtpm_ntcp_g_set(payload, profile); 2041 mlxsw_reg_cwtpm_ntcp_y_set(payload, profile); 2042 mlxsw_reg_cwtpm_ntcp_r_set(payload, profile); 2043 } 2044 2045 /* PGCR - Policy-Engine General Configuration Register 2046 * --------------------------------------------------- 2047 * This register configures general Policy-Engine settings. 2048 */ 2049 #define MLXSW_REG_PGCR_ID 0x3001 2050 #define MLXSW_REG_PGCR_LEN 0x20 2051 2052 MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN); 2053 2054 /* reg_pgcr_default_action_pointer_base 2055 * Default action pointer base. Each region has a default action pointer 2056 * which is equal to default_action_pointer_base + region_id. 2057 * Access: RW 2058 */ 2059 MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24); 2060 2061 static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base) 2062 { 2063 MLXSW_REG_ZERO(pgcr, payload); 2064 mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base); 2065 } 2066 2067 /* PPBT - Policy-Engine Port Binding Table 2068 * --------------------------------------- 2069 * This register is used for configuration of the Port Binding Table. 2070 */ 2071 #define MLXSW_REG_PPBT_ID 0x3002 2072 #define MLXSW_REG_PPBT_LEN 0x14 2073 2074 MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN); 2075 2076 enum mlxsw_reg_pxbt_e { 2077 MLXSW_REG_PXBT_E_IACL, 2078 MLXSW_REG_PXBT_E_EACL, 2079 }; 2080 2081 /* reg_ppbt_e 2082 * Access: Index 2083 */ 2084 MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1); 2085 2086 enum mlxsw_reg_pxbt_op { 2087 MLXSW_REG_PXBT_OP_BIND, 2088 MLXSW_REG_PXBT_OP_UNBIND, 2089 }; 2090 2091 /* reg_ppbt_op 2092 * Access: RW 2093 */ 2094 MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3); 2095 2096 /* reg_ppbt_local_port 2097 * Local port. Not including CPU port. 2098 * Access: Index 2099 */ 2100 MLXSW_ITEM32(reg, ppbt, local_port, 0x00, 16, 8); 2101 2102 /* reg_ppbt_g 2103 * group - When set, the binding is of an ACL group. When cleared, 2104 * the binding is of an ACL. 2105 * Must be set to 1 for Spectrum. 2106 * Access: RW 2107 */ 2108 MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1); 2109 2110 /* reg_ppbt_acl_info 2111 * ACL/ACL group identifier. If the g bit is set, this field should hold 2112 * the acl_group_id, else it should hold the acl_id. 2113 * Access: RW 2114 */ 2115 MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16); 2116 2117 static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e, 2118 enum mlxsw_reg_pxbt_op op, 2119 u8 local_port, u16 acl_info) 2120 { 2121 MLXSW_REG_ZERO(ppbt, payload); 2122 mlxsw_reg_ppbt_e_set(payload, e); 2123 mlxsw_reg_ppbt_op_set(payload, op); 2124 mlxsw_reg_ppbt_local_port_set(payload, local_port); 2125 mlxsw_reg_ppbt_g_set(payload, true); 2126 mlxsw_reg_ppbt_acl_info_set(payload, acl_info); 2127 } 2128 2129 /* PACL - Policy-Engine ACL Register 2130 * --------------------------------- 2131 * This register is used for configuration of the ACL. 2132 */ 2133 #define MLXSW_REG_PACL_ID 0x3004 2134 #define MLXSW_REG_PACL_LEN 0x70 2135 2136 MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN); 2137 2138 /* reg_pacl_v 2139 * Valid. Setting the v bit makes the ACL valid. It should not be cleared 2140 * while the ACL is bounded to either a port, VLAN or ACL rule. 2141 * Access: RW 2142 */ 2143 MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1); 2144 2145 /* reg_pacl_acl_id 2146 * An identifier representing the ACL (managed by software) 2147 * Range 0 .. cap_max_acl_regions - 1 2148 * Access: Index 2149 */ 2150 MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16); 2151 2152 #define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16 2153 2154 /* reg_pacl_tcam_region_info 2155 * Opaque object that represents a TCAM region. 2156 * Obtained through PTAR register. 2157 * Access: RW 2158 */ 2159 MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30, 2160 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2161 2162 static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id, 2163 bool valid, const char *tcam_region_info) 2164 { 2165 MLXSW_REG_ZERO(pacl, payload); 2166 mlxsw_reg_pacl_acl_id_set(payload, acl_id); 2167 mlxsw_reg_pacl_v_set(payload, valid); 2168 mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info); 2169 } 2170 2171 /* PAGT - Policy-Engine ACL Group Table 2172 * ------------------------------------ 2173 * This register is used for configuration of the ACL Group Table. 2174 */ 2175 #define MLXSW_REG_PAGT_ID 0x3005 2176 #define MLXSW_REG_PAGT_BASE_LEN 0x30 2177 #define MLXSW_REG_PAGT_ACL_LEN 4 2178 #define MLXSW_REG_PAGT_ACL_MAX_NUM 16 2179 #define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \ 2180 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN) 2181 2182 MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN); 2183 2184 /* reg_pagt_size 2185 * Number of ACLs in the group. 2186 * Size 0 invalidates a group. 2187 * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now) 2188 * Total number of ACLs in all groups must be lower or equal 2189 * to cap_max_acl_tot_groups 2190 * Note: a group which is binded must not be invalidated 2191 * Access: Index 2192 */ 2193 MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8); 2194 2195 /* reg_pagt_acl_group_id 2196 * An identifier (numbered from 0..cap_max_acl_groups-1) representing 2197 * the ACL Group identifier (managed by software). 2198 * Access: Index 2199 */ 2200 MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16); 2201 2202 /* reg_pagt_multi 2203 * Multi-ACL 2204 * 0 - This ACL is the last ACL in the multi-ACL 2205 * 1 - This ACL is part of a multi-ACL 2206 * Access: RW 2207 */ 2208 MLXSW_ITEM32_INDEXED(reg, pagt, multi, 0x30, 31, 1, 0x04, 0x00, false); 2209 2210 /* reg_pagt_acl_id 2211 * ACL identifier 2212 * Access: RW 2213 */ 2214 MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false); 2215 2216 static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id) 2217 { 2218 MLXSW_REG_ZERO(pagt, payload); 2219 mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id); 2220 } 2221 2222 static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index, 2223 u16 acl_id, bool multi) 2224 { 2225 u8 size = mlxsw_reg_pagt_size_get(payload); 2226 2227 if (index >= size) 2228 mlxsw_reg_pagt_size_set(payload, index + 1); 2229 mlxsw_reg_pagt_multi_set(payload, index, multi); 2230 mlxsw_reg_pagt_acl_id_set(payload, index, acl_id); 2231 } 2232 2233 /* PTAR - Policy-Engine TCAM Allocation Register 2234 * --------------------------------------------- 2235 * This register is used for allocation of regions in the TCAM. 2236 * Note: Query method is not supported on this register. 2237 */ 2238 #define MLXSW_REG_PTAR_ID 0x3006 2239 #define MLXSW_REG_PTAR_BASE_LEN 0x20 2240 #define MLXSW_REG_PTAR_KEY_ID_LEN 1 2241 #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16 2242 #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \ 2243 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN) 2244 2245 MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN); 2246 2247 enum mlxsw_reg_ptar_op { 2248 /* allocate a TCAM region */ 2249 MLXSW_REG_PTAR_OP_ALLOC, 2250 /* resize a TCAM region */ 2251 MLXSW_REG_PTAR_OP_RESIZE, 2252 /* deallocate TCAM region */ 2253 MLXSW_REG_PTAR_OP_FREE, 2254 /* test allocation */ 2255 MLXSW_REG_PTAR_OP_TEST, 2256 }; 2257 2258 /* reg_ptar_op 2259 * Access: OP 2260 */ 2261 MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4); 2262 2263 /* reg_ptar_action_set_type 2264 * Type of action set to be used on this region. 2265 * For Spectrum and Spectrum-2, this is always type 2 - "flexible" 2266 * Access: WO 2267 */ 2268 MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8); 2269 2270 enum mlxsw_reg_ptar_key_type { 2271 MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50, /* Spetrum */ 2272 MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51, /* Spectrum-2 */ 2273 }; 2274 2275 /* reg_ptar_key_type 2276 * TCAM key type for the region. 2277 * Access: WO 2278 */ 2279 MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8); 2280 2281 /* reg_ptar_region_size 2282 * TCAM region size. When allocating/resizing this is the requested size, 2283 * the response is the actual size. Note that actual size may be 2284 * larger than requested. 2285 * Allowed range 1 .. cap_max_rules-1 2286 * Reserved during op deallocate. 2287 * Access: WO 2288 */ 2289 MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16); 2290 2291 /* reg_ptar_region_id 2292 * Region identifier 2293 * Range 0 .. cap_max_regions-1 2294 * Access: Index 2295 */ 2296 MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16); 2297 2298 /* reg_ptar_tcam_region_info 2299 * Opaque object that represents the TCAM region. 2300 * Returned when allocating a region. 2301 * Provided by software for ACL generation and region deallocation and resize. 2302 * Access: RW 2303 */ 2304 MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10, 2305 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2306 2307 /* reg_ptar_flexible_key_id 2308 * Identifier of the Flexible Key. 2309 * Only valid if key_type == "FLEX_KEY" 2310 * The key size will be rounded up to one of the following values: 2311 * 9B, 18B, 36B, 54B. 2312 * This field is reserved for in resize operation. 2313 * Access: WO 2314 */ 2315 MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8, 2316 MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false); 2317 2318 static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op, 2319 enum mlxsw_reg_ptar_key_type key_type, 2320 u16 region_size, u16 region_id, 2321 const char *tcam_region_info) 2322 { 2323 MLXSW_REG_ZERO(ptar, payload); 2324 mlxsw_reg_ptar_op_set(payload, op); 2325 mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */ 2326 mlxsw_reg_ptar_key_type_set(payload, key_type); 2327 mlxsw_reg_ptar_region_size_set(payload, region_size); 2328 mlxsw_reg_ptar_region_id_set(payload, region_id); 2329 mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info); 2330 } 2331 2332 static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index, 2333 u16 key_id) 2334 { 2335 mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id); 2336 } 2337 2338 static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info) 2339 { 2340 mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info); 2341 } 2342 2343 /* PPBS - Policy-Engine Policy Based Switching Register 2344 * ---------------------------------------------------- 2345 * This register retrieves and sets Policy Based Switching Table entries. 2346 */ 2347 #define MLXSW_REG_PPBS_ID 0x300C 2348 #define MLXSW_REG_PPBS_LEN 0x14 2349 2350 MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN); 2351 2352 /* reg_ppbs_pbs_ptr 2353 * Index into the PBS table. 2354 * For Spectrum, the index points to the KVD Linear. 2355 * Access: Index 2356 */ 2357 MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24); 2358 2359 /* reg_ppbs_system_port 2360 * Unique port identifier for the final destination of the packet. 2361 * Access: RW 2362 */ 2363 MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16); 2364 2365 static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr, 2366 u16 system_port) 2367 { 2368 MLXSW_REG_ZERO(ppbs, payload); 2369 mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr); 2370 mlxsw_reg_ppbs_system_port_set(payload, system_port); 2371 } 2372 2373 /* PRCR - Policy-Engine Rules Copy Register 2374 * ---------------------------------------- 2375 * This register is used for accessing rules within a TCAM region. 2376 */ 2377 #define MLXSW_REG_PRCR_ID 0x300D 2378 #define MLXSW_REG_PRCR_LEN 0x40 2379 2380 MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN); 2381 2382 enum mlxsw_reg_prcr_op { 2383 /* Move rules. Moves the rules from "tcam_region_info" starting 2384 * at offset "offset" to "dest_tcam_region_info" 2385 * at offset "dest_offset." 2386 */ 2387 MLXSW_REG_PRCR_OP_MOVE, 2388 /* Copy rules. Copies the rules from "tcam_region_info" starting 2389 * at offset "offset" to "dest_tcam_region_info" 2390 * at offset "dest_offset." 2391 */ 2392 MLXSW_REG_PRCR_OP_COPY, 2393 }; 2394 2395 /* reg_prcr_op 2396 * Access: OP 2397 */ 2398 MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4); 2399 2400 /* reg_prcr_offset 2401 * Offset within the source region to copy/move from. 2402 * Access: Index 2403 */ 2404 MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16); 2405 2406 /* reg_prcr_size 2407 * The number of rules to copy/move. 2408 * Access: WO 2409 */ 2410 MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16); 2411 2412 /* reg_prcr_tcam_region_info 2413 * Opaque object that represents the source TCAM region. 2414 * Access: Index 2415 */ 2416 MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10, 2417 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2418 2419 /* reg_prcr_dest_offset 2420 * Offset within the source region to copy/move to. 2421 * Access: Index 2422 */ 2423 MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16); 2424 2425 /* reg_prcr_dest_tcam_region_info 2426 * Opaque object that represents the destination TCAM region. 2427 * Access: Index 2428 */ 2429 MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30, 2430 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2431 2432 static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op, 2433 const char *src_tcam_region_info, 2434 u16 src_offset, 2435 const char *dest_tcam_region_info, 2436 u16 dest_offset, u16 size) 2437 { 2438 MLXSW_REG_ZERO(prcr, payload); 2439 mlxsw_reg_prcr_op_set(payload, op); 2440 mlxsw_reg_prcr_offset_set(payload, src_offset); 2441 mlxsw_reg_prcr_size_set(payload, size); 2442 mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload, 2443 src_tcam_region_info); 2444 mlxsw_reg_prcr_dest_offset_set(payload, dest_offset); 2445 mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload, 2446 dest_tcam_region_info); 2447 } 2448 2449 /* PEFA - Policy-Engine Extended Flexible Action Register 2450 * ------------------------------------------------------ 2451 * This register is used for accessing an extended flexible action entry 2452 * in the central KVD Linear Database. 2453 */ 2454 #define MLXSW_REG_PEFA_ID 0x300F 2455 #define MLXSW_REG_PEFA_LEN 0xB0 2456 2457 MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN); 2458 2459 /* reg_pefa_index 2460 * Index in the KVD Linear Centralized Database. 2461 * Access: Index 2462 */ 2463 MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24); 2464 2465 /* reg_pefa_a 2466 * Index in the KVD Linear Centralized Database. 2467 * Activity 2468 * For a new entry: set if ca=0, clear if ca=1 2469 * Set if a packet lookup has hit on the specific entry 2470 * Access: RO 2471 */ 2472 MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1); 2473 2474 /* reg_pefa_ca 2475 * Clear activity 2476 * When write: activity is according to this field 2477 * When read: after reading the activity is cleared according to ca 2478 * Access: OP 2479 */ 2480 MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1); 2481 2482 #define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8 2483 2484 /* reg_pefa_flex_action_set 2485 * Action-set to perform when rule is matched. 2486 * Must be zero padded if action set is shorter. 2487 * Access: RW 2488 */ 2489 MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN); 2490 2491 static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca, 2492 const char *flex_action_set) 2493 { 2494 MLXSW_REG_ZERO(pefa, payload); 2495 mlxsw_reg_pefa_index_set(payload, index); 2496 mlxsw_reg_pefa_ca_set(payload, ca); 2497 if (flex_action_set) 2498 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload, 2499 flex_action_set); 2500 } 2501 2502 static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a) 2503 { 2504 *p_a = mlxsw_reg_pefa_a_get(payload); 2505 } 2506 2507 /* PEMRBT - Policy-Engine Multicast Router Binding Table Register 2508 * -------------------------------------------------------------- 2509 * This register is used for binding Multicast router to an ACL group 2510 * that serves the MC router. 2511 * This register is not supported by SwitchX/-2 and Spectrum. 2512 */ 2513 #define MLXSW_REG_PEMRBT_ID 0x3014 2514 #define MLXSW_REG_PEMRBT_LEN 0x14 2515 2516 MLXSW_REG_DEFINE(pemrbt, MLXSW_REG_PEMRBT_ID, MLXSW_REG_PEMRBT_LEN); 2517 2518 enum mlxsw_reg_pemrbt_protocol { 2519 MLXSW_REG_PEMRBT_PROTO_IPV4, 2520 MLXSW_REG_PEMRBT_PROTO_IPV6, 2521 }; 2522 2523 /* reg_pemrbt_protocol 2524 * Access: Index 2525 */ 2526 MLXSW_ITEM32(reg, pemrbt, protocol, 0x00, 0, 1); 2527 2528 /* reg_pemrbt_group_id 2529 * ACL group identifier. 2530 * Range 0..cap_max_acl_groups-1 2531 * Access: RW 2532 */ 2533 MLXSW_ITEM32(reg, pemrbt, group_id, 0x10, 0, 16); 2534 2535 static inline void 2536 mlxsw_reg_pemrbt_pack(char *payload, enum mlxsw_reg_pemrbt_protocol protocol, 2537 u16 group_id) 2538 { 2539 MLXSW_REG_ZERO(pemrbt, payload); 2540 mlxsw_reg_pemrbt_protocol_set(payload, protocol); 2541 mlxsw_reg_pemrbt_group_id_set(payload, group_id); 2542 } 2543 2544 /* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2 2545 * ----------------------------------------------------- 2546 * This register is used for accessing rules within a TCAM region. 2547 * It is a new version of PTCE in order to support wider key, 2548 * mask and action within a TCAM region. This register is not supported 2549 * by SwitchX and SwitchX-2. 2550 */ 2551 #define MLXSW_REG_PTCE2_ID 0x3017 2552 #define MLXSW_REG_PTCE2_LEN 0x1D8 2553 2554 MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN); 2555 2556 /* reg_ptce2_v 2557 * Valid. 2558 * Access: RW 2559 */ 2560 MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1); 2561 2562 /* reg_ptce2_a 2563 * Activity. Set if a packet lookup has hit on the specific entry. 2564 * To clear the "a" bit, use "clear activity" op or "clear on read" op. 2565 * Access: RO 2566 */ 2567 MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1); 2568 2569 enum mlxsw_reg_ptce2_op { 2570 /* Read operation. */ 2571 MLXSW_REG_PTCE2_OP_QUERY_READ = 0, 2572 /* clear on read operation. Used to read entry 2573 * and clear Activity bit. 2574 */ 2575 MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1, 2576 /* Write operation. Used to write a new entry to the table. 2577 * All R/W fields are relevant for new entry. Activity bit is set 2578 * for new entries - Note write with v = 0 will delete the entry. 2579 */ 2580 MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0, 2581 /* Update action. Only action set will be updated. */ 2582 MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1, 2583 /* Clear activity. A bit is cleared for the entry. */ 2584 MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2, 2585 }; 2586 2587 /* reg_ptce2_op 2588 * Access: OP 2589 */ 2590 MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3); 2591 2592 /* reg_ptce2_offset 2593 * Access: Index 2594 */ 2595 MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16); 2596 2597 /* reg_ptce2_priority 2598 * Priority of the rule, higher values win. The range is 1..cap_kvd_size-1. 2599 * Note: priority does not have to be unique per rule. 2600 * Within a region, higher priority should have lower offset (no limitation 2601 * between regions in a multi-region). 2602 * Access: RW 2603 */ 2604 MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24); 2605 2606 /* reg_ptce2_tcam_region_info 2607 * Opaque object that represents the TCAM region. 2608 * Access: Index 2609 */ 2610 MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10, 2611 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2612 2613 #define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 96 2614 2615 /* reg_ptce2_flex_key_blocks 2616 * ACL Key. 2617 * Access: RW 2618 */ 2619 MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20, 2620 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2621 2622 /* reg_ptce2_mask 2623 * mask- in the same size as key. A bit that is set directs the TCAM 2624 * to compare the corresponding bit in key. A bit that is clear directs 2625 * the TCAM to ignore the corresponding bit in key. 2626 * Access: RW 2627 */ 2628 MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80, 2629 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2630 2631 /* reg_ptce2_flex_action_set 2632 * ACL action set. 2633 * Access: RW 2634 */ 2635 MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0, 2636 MLXSW_REG_FLEX_ACTION_SET_LEN); 2637 2638 static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid, 2639 enum mlxsw_reg_ptce2_op op, 2640 const char *tcam_region_info, 2641 u16 offset, u32 priority) 2642 { 2643 MLXSW_REG_ZERO(ptce2, payload); 2644 mlxsw_reg_ptce2_v_set(payload, valid); 2645 mlxsw_reg_ptce2_op_set(payload, op); 2646 mlxsw_reg_ptce2_offset_set(payload, offset); 2647 mlxsw_reg_ptce2_priority_set(payload, priority); 2648 mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info); 2649 } 2650 2651 /* PERPT - Policy-Engine ERP Table Register 2652 * ---------------------------------------- 2653 * This register adds and removes eRPs from the eRP table. 2654 */ 2655 #define MLXSW_REG_PERPT_ID 0x3021 2656 #define MLXSW_REG_PERPT_LEN 0x80 2657 2658 MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN); 2659 2660 /* reg_perpt_erpt_bank 2661 * eRP table bank. 2662 * Range 0 .. cap_max_erp_table_banks - 1 2663 * Access: Index 2664 */ 2665 MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4); 2666 2667 /* reg_perpt_erpt_index 2668 * Index to eRP table within the eRP bank. 2669 * Range is 0 .. cap_max_erp_table_bank_size - 1 2670 * Access: Index 2671 */ 2672 MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8); 2673 2674 enum mlxsw_reg_perpt_key_size { 2675 MLXSW_REG_PERPT_KEY_SIZE_2KB, 2676 MLXSW_REG_PERPT_KEY_SIZE_4KB, 2677 MLXSW_REG_PERPT_KEY_SIZE_8KB, 2678 MLXSW_REG_PERPT_KEY_SIZE_12KB, 2679 }; 2680 2681 /* reg_perpt_key_size 2682 * Access: OP 2683 */ 2684 MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4); 2685 2686 /* reg_perpt_bf_bypass 2687 * 0 - The eRP is used only if bloom filter state is set for the given 2688 * rule. 2689 * 1 - The eRP is used regardless of bloom filter state. 2690 * The bypass is an OR condition of region_id or eRP. See PERCR.bf_bypass 2691 * Access: RW 2692 */ 2693 MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1); 2694 2695 /* reg_perpt_erp_id 2696 * eRP ID for use by the rules. 2697 * Access: RW 2698 */ 2699 MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4); 2700 2701 /* reg_perpt_erpt_base_bank 2702 * Base eRP table bank, points to head of erp_vector 2703 * Range is 0 .. cap_max_erp_table_banks - 1 2704 * Access: OP 2705 */ 2706 MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4); 2707 2708 /* reg_perpt_erpt_base_index 2709 * Base index to eRP table within the eRP bank 2710 * Range is 0 .. cap_max_erp_table_bank_size - 1 2711 * Access: OP 2712 */ 2713 MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8); 2714 2715 /* reg_perpt_erp_index_in_vector 2716 * eRP index in the vector. 2717 * Access: OP 2718 */ 2719 MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4); 2720 2721 /* reg_perpt_erp_vector 2722 * eRP vector. 2723 * Access: OP 2724 */ 2725 MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1); 2726 2727 /* reg_perpt_mask 2728 * Mask 2729 * 0 - A-TCAM will ignore the bit in key 2730 * 1 - A-TCAM will compare the bit in key 2731 * Access: RW 2732 */ 2733 MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2734 2735 static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload, 2736 unsigned long *erp_vector, 2737 unsigned long size) 2738 { 2739 unsigned long bit; 2740 2741 for_each_set_bit(bit, erp_vector, size) 2742 mlxsw_reg_perpt_erp_vector_set(payload, bit, true); 2743 } 2744 2745 static inline void 2746 mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index, 2747 enum mlxsw_reg_perpt_key_size key_size, u8 erp_id, 2748 u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index, 2749 char *mask) 2750 { 2751 MLXSW_REG_ZERO(perpt, payload); 2752 mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank); 2753 mlxsw_reg_perpt_erpt_index_set(payload, erpt_index); 2754 mlxsw_reg_perpt_key_size_set(payload, key_size); 2755 mlxsw_reg_perpt_bf_bypass_set(payload, false); 2756 mlxsw_reg_perpt_erp_id_set(payload, erp_id); 2757 mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank); 2758 mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index); 2759 mlxsw_reg_perpt_erp_index_in_vector_set(payload, erp_index); 2760 mlxsw_reg_perpt_mask_memcpy_to(payload, mask); 2761 } 2762 2763 /* PERAR - Policy-Engine Region Association Register 2764 * ------------------------------------------------- 2765 * This register associates a hw region for region_id's. Changing on the fly 2766 * is supported by the device. 2767 */ 2768 #define MLXSW_REG_PERAR_ID 0x3026 2769 #define MLXSW_REG_PERAR_LEN 0x08 2770 2771 MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN); 2772 2773 /* reg_perar_region_id 2774 * Region identifier 2775 * Range 0 .. cap_max_regions-1 2776 * Access: Index 2777 */ 2778 MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16); 2779 2780 static inline unsigned int 2781 mlxsw_reg_perar_hw_regions_needed(unsigned int block_num) 2782 { 2783 return DIV_ROUND_UP(block_num, 4); 2784 } 2785 2786 /* reg_perar_hw_region 2787 * HW Region 2788 * Range 0 .. cap_max_regions-1 2789 * Default: hw_region = region_id 2790 * For a 8 key block region, 2 consecutive regions are used 2791 * For a 12 key block region, 3 consecutive regions are used 2792 * Access: RW 2793 */ 2794 MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16); 2795 2796 static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id, 2797 u16 hw_region) 2798 { 2799 MLXSW_REG_ZERO(perar, payload); 2800 mlxsw_reg_perar_region_id_set(payload, region_id); 2801 mlxsw_reg_perar_hw_region_set(payload, hw_region); 2802 } 2803 2804 /* PTCE-V3 - Policy-Engine TCAM Entry Register Version 3 2805 * ----------------------------------------------------- 2806 * This register is a new version of PTCE-V2 in order to support the 2807 * A-TCAM. This register is not supported by SwitchX/-2 and Spectrum. 2808 */ 2809 #define MLXSW_REG_PTCE3_ID 0x3027 2810 #define MLXSW_REG_PTCE3_LEN 0xF0 2811 2812 MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN); 2813 2814 /* reg_ptce3_v 2815 * Valid. 2816 * Access: RW 2817 */ 2818 MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1); 2819 2820 enum mlxsw_reg_ptce3_op { 2821 /* Write operation. Used to write a new entry to the table. 2822 * All R/W fields are relevant for new entry. Activity bit is set 2823 * for new entries. Write with v = 0 will delete the entry. Must 2824 * not be used if an entry exists. 2825 */ 2826 MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0, 2827 /* Update operation */ 2828 MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1, 2829 /* Read operation */ 2830 MLXSW_REG_PTCE3_OP_QUERY_READ = 0, 2831 }; 2832 2833 /* reg_ptce3_op 2834 * Access: OP 2835 */ 2836 MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3); 2837 2838 /* reg_ptce3_priority 2839 * Priority of the rule. Higher values win. 2840 * For Spectrum-2 range is 1..cap_kvd_size - 1 2841 * Note: Priority does not have to be unique per rule. 2842 * Access: RW 2843 */ 2844 MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24); 2845 2846 /* reg_ptce3_tcam_region_info 2847 * Opaque object that represents the TCAM region. 2848 * Access: Index 2849 */ 2850 MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10, 2851 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2852 2853 /* reg_ptce3_flex2_key_blocks 2854 * ACL key. The key must be masked according to eRP (if exists) or 2855 * according to master mask. 2856 * Access: Index 2857 */ 2858 MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20, 2859 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2860 2861 /* reg_ptce3_erp_id 2862 * eRP ID. 2863 * Access: Index 2864 */ 2865 MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4); 2866 2867 /* reg_ptce3_delta_start 2868 * Start point of delta_value and delta_mask, in bits. Must not exceed 2869 * num_key_blocks * 36 - 8. Reserved when delta_mask = 0. 2870 * Access: Index 2871 */ 2872 MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10); 2873 2874 /* reg_ptce3_delta_mask 2875 * Delta mask. 2876 * 0 - Ignore relevant bit in delta_value 2877 * 1 - Compare relevant bit in delta_value 2878 * Delta mask must not be set for reserved fields in the key blocks. 2879 * Note: No delta when no eRPs. Thus, for regions with 2880 * PERERP.erpt_pointer_valid = 0 the delta mask must be 0. 2881 * Access: Index 2882 */ 2883 MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8); 2884 2885 /* reg_ptce3_delta_value 2886 * Delta value. 2887 * Bits which are masked by delta_mask must be 0. 2888 * Access: Index 2889 */ 2890 MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8); 2891 2892 /* reg_ptce3_prune_vector 2893 * Pruning vector relative to the PERPT.erp_id. 2894 * Used for reducing lookups. 2895 * 0 - NEED: Do a lookup using the eRP. 2896 * 1 - PRUNE: Do not perform a lookup using the eRP. 2897 * Maybe be modified by PEAPBL and PEAPBM. 2898 * Note: In Spectrum-2, a region of 8 key blocks must be set to either 2899 * all 1's or all 0's. 2900 * Access: RW 2901 */ 2902 MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1); 2903 2904 /* reg_ptce3_prune_ctcam 2905 * Pruning on C-TCAM. Used for reducing lookups. 2906 * 0 - NEED: Do a lookup in the C-TCAM. 2907 * 1 - PRUNE: Do not perform a lookup in the C-TCAM. 2908 * Access: RW 2909 */ 2910 MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1); 2911 2912 /* reg_ptce3_large_exists 2913 * Large entry key ID exists. 2914 * Within the region: 2915 * 0 - SINGLE: The large_entry_key_id is not currently in use. 2916 * For rule insert: The MSB of the key (blocks 6..11) will be added. 2917 * For rule delete: The MSB of the key will be removed. 2918 * 1 - NON_SINGLE: The large_entry_key_id is currently in use. 2919 * For rule insert: The MSB of the key (blocks 6..11) will not be added. 2920 * For rule delete: The MSB of the key will not be removed. 2921 * Access: WO 2922 */ 2923 MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1); 2924 2925 /* reg_ptce3_large_entry_key_id 2926 * Large entry key ID. 2927 * A key for 12 key blocks rules. Reserved when region has less than 12 key 2928 * blocks. Must be different for different keys which have the same common 2929 * 6 key blocks (MSB, blocks 6..11) key within a region. 2930 * Range is 0..cap_max_pe_large_key_id - 1 2931 * Access: RW 2932 */ 2933 MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24); 2934 2935 /* reg_ptce3_action_pointer 2936 * Pointer to action. 2937 * Range is 0..cap_max_kvd_action_sets - 1 2938 * Access: RW 2939 */ 2940 MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24); 2941 2942 static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid, 2943 enum mlxsw_reg_ptce3_op op, 2944 u32 priority, 2945 const char *tcam_region_info, 2946 const char *key, u8 erp_id, 2947 u16 delta_start, u8 delta_mask, 2948 u8 delta_value, bool large_exists, 2949 u32 lkey_id, u32 action_pointer) 2950 { 2951 MLXSW_REG_ZERO(ptce3, payload); 2952 mlxsw_reg_ptce3_v_set(payload, valid); 2953 mlxsw_reg_ptce3_op_set(payload, op); 2954 mlxsw_reg_ptce3_priority_set(payload, priority); 2955 mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info); 2956 mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key); 2957 mlxsw_reg_ptce3_erp_id_set(payload, erp_id); 2958 mlxsw_reg_ptce3_delta_start_set(payload, delta_start); 2959 mlxsw_reg_ptce3_delta_mask_set(payload, delta_mask); 2960 mlxsw_reg_ptce3_delta_value_set(payload, delta_value); 2961 mlxsw_reg_ptce3_large_exists_set(payload, large_exists); 2962 mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id); 2963 mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer); 2964 } 2965 2966 /* PERCR - Policy-Engine Region Configuration Register 2967 * --------------------------------------------------- 2968 * This register configures the region parameters. The region_id must be 2969 * allocated. 2970 */ 2971 #define MLXSW_REG_PERCR_ID 0x302A 2972 #define MLXSW_REG_PERCR_LEN 0x80 2973 2974 MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN); 2975 2976 /* reg_percr_region_id 2977 * Region identifier. 2978 * Range 0..cap_max_regions-1 2979 * Access: Index 2980 */ 2981 MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16); 2982 2983 /* reg_percr_atcam_ignore_prune 2984 * Ignore prune_vector by other A-TCAM rules. Used e.g., for a new rule. 2985 * Access: RW 2986 */ 2987 MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1); 2988 2989 /* reg_percr_ctcam_ignore_prune 2990 * Ignore prune_ctcam by other A-TCAM rules. Used e.g., for a new rule. 2991 * Access: RW 2992 */ 2993 MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1); 2994 2995 /* reg_percr_bf_bypass 2996 * Bloom filter bypass. 2997 * 0 - Bloom filter is used (default) 2998 * 1 - Bloom filter is bypassed. The bypass is an OR condition of 2999 * region_id or eRP. See PERPT.bf_bypass 3000 * Access: RW 3001 */ 3002 MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1); 3003 3004 /* reg_percr_master_mask 3005 * Master mask. Logical OR mask of all masks of all rules of a region 3006 * (both A-TCAM and C-TCAM). When there are no eRPs 3007 * (erpt_pointer_valid = 0), then this provides the mask. 3008 * Access: RW 3009 */ 3010 MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96); 3011 3012 static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id) 3013 { 3014 MLXSW_REG_ZERO(percr, payload); 3015 mlxsw_reg_percr_region_id_set(payload, region_id); 3016 mlxsw_reg_percr_atcam_ignore_prune_set(payload, false); 3017 mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false); 3018 mlxsw_reg_percr_bf_bypass_set(payload, false); 3019 } 3020 3021 /* PERERP - Policy-Engine Region eRP Register 3022 * ------------------------------------------ 3023 * This register configures the region eRP. The region_id must be 3024 * allocated. 3025 */ 3026 #define MLXSW_REG_PERERP_ID 0x302B 3027 #define MLXSW_REG_PERERP_LEN 0x1C 3028 3029 MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN); 3030 3031 /* reg_pererp_region_id 3032 * Region identifier. 3033 * Range 0..cap_max_regions-1 3034 * Access: Index 3035 */ 3036 MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16); 3037 3038 /* reg_pererp_ctcam_le 3039 * C-TCAM lookup enable. Reserved when erpt_pointer_valid = 0. 3040 * Access: RW 3041 */ 3042 MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1); 3043 3044 /* reg_pererp_erpt_pointer_valid 3045 * erpt_pointer is valid. 3046 * Access: RW 3047 */ 3048 MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1); 3049 3050 /* reg_pererp_erpt_bank_pointer 3051 * Pointer to eRP table bank. May be modified at any time. 3052 * Range 0..cap_max_erp_table_banks-1 3053 * Reserved when erpt_pointer_valid = 0 3054 */ 3055 MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4); 3056 3057 /* reg_pererp_erpt_pointer 3058 * Pointer to eRP table within the eRP bank. Can be changed for an 3059 * existing region. 3060 * Range 0..cap_max_erp_table_size-1 3061 * Reserved when erpt_pointer_valid = 0 3062 * Access: RW 3063 */ 3064 MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8); 3065 3066 /* reg_pererp_erpt_vector 3067 * Vector of allowed eRP indexes starting from erpt_pointer within the 3068 * erpt_bank_pointer. Next entries will be in next bank. 3069 * Note that eRP index is used and not eRP ID. 3070 * Reserved when erpt_pointer_valid = 0 3071 * Access: RW 3072 */ 3073 MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1); 3074 3075 /* reg_pererp_master_rp_id 3076 * Master RP ID. When there are no eRPs, then this provides the eRP ID 3077 * for the lookup. Can be changed for an existing region. 3078 * Reserved when erpt_pointer_valid = 1 3079 * Access: RW 3080 */ 3081 MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4); 3082 3083 static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload, 3084 unsigned long *erp_vector, 3085 unsigned long size) 3086 { 3087 unsigned long bit; 3088 3089 for_each_set_bit(bit, erp_vector, size) 3090 mlxsw_reg_pererp_erpt_vector_set(payload, bit, true); 3091 } 3092 3093 static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id, 3094 bool ctcam_le, bool erpt_pointer_valid, 3095 u8 erpt_bank_pointer, u8 erpt_pointer, 3096 u8 master_rp_id) 3097 { 3098 MLXSW_REG_ZERO(pererp, payload); 3099 mlxsw_reg_pererp_region_id_set(payload, region_id); 3100 mlxsw_reg_pererp_ctcam_le_set(payload, ctcam_le); 3101 mlxsw_reg_pererp_erpt_pointer_valid_set(payload, erpt_pointer_valid); 3102 mlxsw_reg_pererp_erpt_bank_pointer_set(payload, erpt_bank_pointer); 3103 mlxsw_reg_pererp_erpt_pointer_set(payload, erpt_pointer); 3104 mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id); 3105 } 3106 3107 /* PEABFE - Policy-Engine Algorithmic Bloom Filter Entries Register 3108 * ---------------------------------------------------------------- 3109 * This register configures the Bloom filter entries. 3110 */ 3111 #define MLXSW_REG_PEABFE_ID 0x3022 3112 #define MLXSW_REG_PEABFE_BASE_LEN 0x10 3113 #define MLXSW_REG_PEABFE_BF_REC_LEN 0x4 3114 #define MLXSW_REG_PEABFE_BF_REC_MAX_COUNT 256 3115 #define MLXSW_REG_PEABFE_LEN (MLXSW_REG_PEABFE_BASE_LEN + \ 3116 MLXSW_REG_PEABFE_BF_REC_LEN * \ 3117 MLXSW_REG_PEABFE_BF_REC_MAX_COUNT) 3118 3119 MLXSW_REG_DEFINE(peabfe, MLXSW_REG_PEABFE_ID, MLXSW_REG_PEABFE_LEN); 3120 3121 /* reg_peabfe_size 3122 * Number of BF entries to be updated. 3123 * Range 1..256 3124 * Access: Op 3125 */ 3126 MLXSW_ITEM32(reg, peabfe, size, 0x00, 0, 9); 3127 3128 /* reg_peabfe_bf_entry_state 3129 * Bloom filter state 3130 * 0 - Clear 3131 * 1 - Set 3132 * Access: RW 3133 */ 3134 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_state, 3135 MLXSW_REG_PEABFE_BASE_LEN, 31, 1, 3136 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3137 3138 /* reg_peabfe_bf_entry_bank 3139 * Bloom filter bank ID 3140 * Range 0..cap_max_erp_table_banks-1 3141 * Access: Index 3142 */ 3143 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_bank, 3144 MLXSW_REG_PEABFE_BASE_LEN, 24, 4, 3145 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3146 3147 /* reg_peabfe_bf_entry_index 3148 * Bloom filter entry index 3149 * Range 0..2^cap_max_bf_log-1 3150 * Access: Index 3151 */ 3152 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_index, 3153 MLXSW_REG_PEABFE_BASE_LEN, 0, 24, 3154 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3155 3156 static inline void mlxsw_reg_peabfe_pack(char *payload) 3157 { 3158 MLXSW_REG_ZERO(peabfe, payload); 3159 } 3160 3161 static inline void mlxsw_reg_peabfe_rec_pack(char *payload, int rec_index, 3162 u8 state, u8 bank, u32 bf_index) 3163 { 3164 u8 num_rec = mlxsw_reg_peabfe_size_get(payload); 3165 3166 if (rec_index >= num_rec) 3167 mlxsw_reg_peabfe_size_set(payload, rec_index + 1); 3168 mlxsw_reg_peabfe_bf_entry_state_set(payload, rec_index, state); 3169 mlxsw_reg_peabfe_bf_entry_bank_set(payload, rec_index, bank); 3170 mlxsw_reg_peabfe_bf_entry_index_set(payload, rec_index, bf_index); 3171 } 3172 3173 /* IEDR - Infrastructure Entry Delete Register 3174 * ---------------------------------------------------- 3175 * This register is used for deleting entries from the entry tables. 3176 * It is legitimate to attempt to delete a nonexisting entry (the device will 3177 * respond as a good flow). 3178 */ 3179 #define MLXSW_REG_IEDR_ID 0x3804 3180 #define MLXSW_REG_IEDR_BASE_LEN 0x10 /* base length, without records */ 3181 #define MLXSW_REG_IEDR_REC_LEN 0x8 /* record length */ 3182 #define MLXSW_REG_IEDR_REC_MAX_COUNT 64 3183 #define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN + \ 3184 MLXSW_REG_IEDR_REC_LEN * \ 3185 MLXSW_REG_IEDR_REC_MAX_COUNT) 3186 3187 MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN); 3188 3189 /* reg_iedr_num_rec 3190 * Number of records. 3191 * Access: OP 3192 */ 3193 MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8); 3194 3195 /* reg_iedr_rec_type 3196 * Resource type. 3197 * Access: OP 3198 */ 3199 MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8, 3200 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3201 3202 /* reg_iedr_rec_size 3203 * Size of entries do be deleted. The unit is 1 entry, regardless of entry type. 3204 * Access: OP 3205 */ 3206 MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 11, 3207 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3208 3209 /* reg_iedr_rec_index_start 3210 * Resource index start. 3211 * Access: OP 3212 */ 3213 MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24, 3214 MLXSW_REG_IEDR_REC_LEN, 0x04, false); 3215 3216 static inline void mlxsw_reg_iedr_pack(char *payload) 3217 { 3218 MLXSW_REG_ZERO(iedr, payload); 3219 } 3220 3221 static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index, 3222 u8 rec_type, u16 rec_size, 3223 u32 rec_index_start) 3224 { 3225 u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload); 3226 3227 if (rec_index >= num_rec) 3228 mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1); 3229 mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type); 3230 mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size); 3231 mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start); 3232 } 3233 3234 /* QPTS - QoS Priority Trust State Register 3235 * ---------------------------------------- 3236 * This register controls the port policy to calculate the switch priority and 3237 * packet color based on incoming packet fields. 3238 */ 3239 #define MLXSW_REG_QPTS_ID 0x4002 3240 #define MLXSW_REG_QPTS_LEN 0x8 3241 3242 MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN); 3243 3244 /* reg_qpts_local_port 3245 * Local port number. 3246 * Access: Index 3247 * 3248 * Note: CPU port is supported. 3249 */ 3250 MLXSW_ITEM32(reg, qpts, local_port, 0x00, 16, 8); 3251 3252 enum mlxsw_reg_qpts_trust_state { 3253 MLXSW_REG_QPTS_TRUST_STATE_PCP = 1, 3254 MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2, /* For MPLS, trust EXP. */ 3255 }; 3256 3257 /* reg_qpts_trust_state 3258 * Trust state for a given port. 3259 * Access: RW 3260 */ 3261 MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3); 3262 3263 static inline void mlxsw_reg_qpts_pack(char *payload, u8 local_port, 3264 enum mlxsw_reg_qpts_trust_state ts) 3265 { 3266 MLXSW_REG_ZERO(qpts, payload); 3267 3268 mlxsw_reg_qpts_local_port_set(payload, local_port); 3269 mlxsw_reg_qpts_trust_state_set(payload, ts); 3270 } 3271 3272 /* QPCR - QoS Policer Configuration Register 3273 * ----------------------------------------- 3274 * The QPCR register is used to create policers - that limit 3275 * the rate of bytes or packets via some trap group. 3276 */ 3277 #define MLXSW_REG_QPCR_ID 0x4004 3278 #define MLXSW_REG_QPCR_LEN 0x28 3279 3280 MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN); 3281 3282 enum mlxsw_reg_qpcr_g { 3283 MLXSW_REG_QPCR_G_GLOBAL = 2, 3284 MLXSW_REG_QPCR_G_STORM_CONTROL = 3, 3285 }; 3286 3287 /* reg_qpcr_g 3288 * The policer type. 3289 * Access: Index 3290 */ 3291 MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2); 3292 3293 /* reg_qpcr_pid 3294 * Policer ID. 3295 * Access: Index 3296 */ 3297 MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14); 3298 3299 /* reg_qpcr_color_aware 3300 * Is the policer aware of colors. 3301 * Must be 0 (unaware) for cpu port. 3302 * Access: RW for unbounded policer. RO for bounded policer. 3303 */ 3304 MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1); 3305 3306 /* reg_qpcr_bytes 3307 * Is policer limit is for bytes per sec or packets per sec. 3308 * 0 - packets 3309 * 1 - bytes 3310 * Access: RW for unbounded policer. RO for bounded policer. 3311 */ 3312 MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1); 3313 3314 enum mlxsw_reg_qpcr_ir_units { 3315 MLXSW_REG_QPCR_IR_UNITS_M, 3316 MLXSW_REG_QPCR_IR_UNITS_K, 3317 }; 3318 3319 /* reg_qpcr_ir_units 3320 * Policer's units for cir and eir fields (for bytes limits only) 3321 * 1 - 10^3 3322 * 0 - 10^6 3323 * Access: OP 3324 */ 3325 MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1); 3326 3327 enum mlxsw_reg_qpcr_rate_type { 3328 MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1, 3329 MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2, 3330 }; 3331 3332 /* reg_qpcr_rate_type 3333 * Policer can have one limit (single rate) or 2 limits with specific operation 3334 * for packets that exceed the lower rate but not the upper one. 3335 * (For cpu port must be single rate) 3336 * Access: RW for unbounded policer. RO for bounded policer. 3337 */ 3338 MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2); 3339 3340 /* reg_qpc_cbs 3341 * Policer's committed burst size. 3342 * The policer is working with time slices of 50 nano sec. By default every 3343 * slice is granted the proportionate share of the committed rate. If we want to 3344 * allow a slice to exceed that share (while still keeping the rate per sec) we 3345 * can allow burst. The burst size is between the default proportionate share 3346 * (and no lower than 8) to 32Gb. (Even though giving a number higher than the 3347 * committed rate will result in exceeding the rate). The burst size must be a 3348 * log of 2 and will be determined by 2^cbs. 3349 * Access: RW 3350 */ 3351 MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6); 3352 3353 /* reg_qpcr_cir 3354 * Policer's committed rate. 3355 * The rate used for sungle rate, the lower rate for double rate. 3356 * For bytes limits, the rate will be this value * the unit from ir_units. 3357 * (Resolution error is up to 1%). 3358 * Access: RW 3359 */ 3360 MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32); 3361 3362 /* reg_qpcr_eir 3363 * Policer's exceed rate. 3364 * The higher rate for double rate, reserved for single rate. 3365 * Lower rate for double rate policer. 3366 * For bytes limits, the rate will be this value * the unit from ir_units. 3367 * (Resolution error is up to 1%). 3368 * Access: RW 3369 */ 3370 MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32); 3371 3372 #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2 3373 3374 /* reg_qpcr_exceed_action. 3375 * What to do with packets between the 2 limits for double rate. 3376 * Access: RW for unbounded policer. RO for bounded policer. 3377 */ 3378 MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4); 3379 3380 enum mlxsw_reg_qpcr_action { 3381 /* Discard */ 3382 MLXSW_REG_QPCR_ACTION_DISCARD = 1, 3383 /* Forward and set color to red. 3384 * If the packet is intended to cpu port, it will be dropped. 3385 */ 3386 MLXSW_REG_QPCR_ACTION_FORWARD = 2, 3387 }; 3388 3389 /* reg_qpcr_violate_action 3390 * What to do with packets that cross the cir limit (for single rate) or the eir 3391 * limit (for double rate). 3392 * Access: RW for unbounded policer. RO for bounded policer. 3393 */ 3394 MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4); 3395 3396 static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid, 3397 enum mlxsw_reg_qpcr_ir_units ir_units, 3398 bool bytes, u32 cir, u16 cbs) 3399 { 3400 MLXSW_REG_ZERO(qpcr, payload); 3401 mlxsw_reg_qpcr_pid_set(payload, pid); 3402 mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL); 3403 mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE); 3404 mlxsw_reg_qpcr_violate_action_set(payload, 3405 MLXSW_REG_QPCR_ACTION_DISCARD); 3406 mlxsw_reg_qpcr_cir_set(payload, cir); 3407 mlxsw_reg_qpcr_ir_units_set(payload, ir_units); 3408 mlxsw_reg_qpcr_bytes_set(payload, bytes); 3409 mlxsw_reg_qpcr_cbs_set(payload, cbs); 3410 } 3411 3412 /* QTCT - QoS Switch Traffic Class Table 3413 * ------------------------------------- 3414 * Configures the mapping between the packet switch priority and the 3415 * traffic class on the transmit port. 3416 */ 3417 #define MLXSW_REG_QTCT_ID 0x400A 3418 #define MLXSW_REG_QTCT_LEN 0x08 3419 3420 MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN); 3421 3422 /* reg_qtct_local_port 3423 * Local port number. 3424 * Access: Index 3425 * 3426 * Note: CPU port is not supported. 3427 */ 3428 MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8); 3429 3430 /* reg_qtct_sub_port 3431 * Virtual port within the physical port. 3432 * Should be set to 0 when virtual ports are not enabled on the port. 3433 * Access: Index 3434 */ 3435 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8); 3436 3437 /* reg_qtct_switch_prio 3438 * Switch priority. 3439 * Access: Index 3440 */ 3441 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4); 3442 3443 /* reg_qtct_tclass 3444 * Traffic class. 3445 * Default values: 3446 * switch_prio 0 : tclass 1 3447 * switch_prio 1 : tclass 0 3448 * switch_prio i : tclass i, for i > 1 3449 * Access: RW 3450 */ 3451 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4); 3452 3453 static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port, 3454 u8 switch_prio, u8 tclass) 3455 { 3456 MLXSW_REG_ZERO(qtct, payload); 3457 mlxsw_reg_qtct_local_port_set(payload, local_port); 3458 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio); 3459 mlxsw_reg_qtct_tclass_set(payload, tclass); 3460 } 3461 3462 /* QEEC - QoS ETS Element Configuration Register 3463 * --------------------------------------------- 3464 * Configures the ETS elements. 3465 */ 3466 #define MLXSW_REG_QEEC_ID 0x400D 3467 #define MLXSW_REG_QEEC_LEN 0x20 3468 3469 MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN); 3470 3471 /* reg_qeec_local_port 3472 * Local port number. 3473 * Access: Index 3474 * 3475 * Note: CPU port is supported. 3476 */ 3477 MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8); 3478 3479 enum mlxsw_reg_qeec_hr { 3480 MLXSW_REG_QEEC_HIERARCY_PORT, 3481 MLXSW_REG_QEEC_HIERARCY_GROUP, 3482 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, 3483 MLXSW_REG_QEEC_HIERARCY_TC, 3484 }; 3485 3486 /* reg_qeec_element_hierarchy 3487 * 0 - Port 3488 * 1 - Group 3489 * 2 - Subgroup 3490 * 3 - Traffic Class 3491 * Access: Index 3492 */ 3493 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4); 3494 3495 /* reg_qeec_element_index 3496 * The index of the element in the hierarchy. 3497 * Access: Index 3498 */ 3499 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8); 3500 3501 /* reg_qeec_next_element_index 3502 * The index of the next (lower) element in the hierarchy. 3503 * Access: RW 3504 * 3505 * Note: Reserved for element_hierarchy 0. 3506 */ 3507 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8); 3508 3509 /* reg_qeec_mise 3510 * Min shaper configuration enable. Enables configuration of the min 3511 * shaper on this ETS element 3512 * 0 - Disable 3513 * 1 - Enable 3514 * Access: RW 3515 */ 3516 MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1); 3517 3518 enum { 3519 MLXSW_REG_QEEC_BYTES_MODE, 3520 MLXSW_REG_QEEC_PACKETS_MODE, 3521 }; 3522 3523 /* reg_qeec_pb 3524 * Packets or bytes mode. 3525 * 0 - Bytes mode 3526 * 1 - Packets mode 3527 * Access: RW 3528 * 3529 * Note: Used for max shaper configuration. For Spectrum, packets mode 3530 * is supported only for traffic classes of CPU port. 3531 */ 3532 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1); 3533 3534 /* The smallest permitted min shaper rate. */ 3535 #define MLXSW_REG_QEEC_MIS_MIN 200000 /* Kbps */ 3536 3537 /* reg_qeec_min_shaper_rate 3538 * Min shaper information rate. 3539 * For CPU port, can only be configured for port hierarchy. 3540 * When in bytes mode, value is specified in units of 1000bps. 3541 * Access: RW 3542 */ 3543 MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28); 3544 3545 /* reg_qeec_mase 3546 * Max shaper configuration enable. Enables configuration of the max 3547 * shaper on this ETS element. 3548 * 0 - Disable 3549 * 1 - Enable 3550 * Access: RW 3551 */ 3552 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1); 3553 3554 /* A large max rate will disable the max shaper. */ 3555 #define MLXSW_REG_QEEC_MAS_DIS 200000000 /* Kbps */ 3556 3557 /* reg_qeec_max_shaper_rate 3558 * Max shaper information rate. 3559 * For CPU port, can only be configured for port hierarchy. 3560 * When in bytes mode, value is specified in units of 1000bps. 3561 * Access: RW 3562 */ 3563 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 28); 3564 3565 /* reg_qeec_de 3566 * DWRR configuration enable. Enables configuration of the dwrr and 3567 * dwrr_weight. 3568 * 0 - Disable 3569 * 1 - Enable 3570 * Access: RW 3571 */ 3572 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1); 3573 3574 /* reg_qeec_dwrr 3575 * Transmission selection algorithm to use on the link going down from 3576 * the ETS element. 3577 * 0 - Strict priority 3578 * 1 - DWRR 3579 * Access: RW 3580 */ 3581 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1); 3582 3583 /* reg_qeec_dwrr_weight 3584 * DWRR weight on the link going down from the ETS element. The 3585 * percentage of bandwidth guaranteed to an ETS element within 3586 * its hierarchy. The sum of all weights across all ETS elements 3587 * within one hierarchy should be equal to 100. Reserved when 3588 * transmission selection algorithm is strict priority. 3589 * Access: RW 3590 */ 3591 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8); 3592 3593 static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port, 3594 enum mlxsw_reg_qeec_hr hr, u8 index, 3595 u8 next_index) 3596 { 3597 MLXSW_REG_ZERO(qeec, payload); 3598 mlxsw_reg_qeec_local_port_set(payload, local_port); 3599 mlxsw_reg_qeec_element_hierarchy_set(payload, hr); 3600 mlxsw_reg_qeec_element_index_set(payload, index); 3601 mlxsw_reg_qeec_next_element_index_set(payload, next_index); 3602 } 3603 3604 /* QRWE - QoS ReWrite Enable 3605 * ------------------------- 3606 * This register configures the rewrite enable per receive port. 3607 */ 3608 #define MLXSW_REG_QRWE_ID 0x400F 3609 #define MLXSW_REG_QRWE_LEN 0x08 3610 3611 MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN); 3612 3613 /* reg_qrwe_local_port 3614 * Local port number. 3615 * Access: Index 3616 * 3617 * Note: CPU port is supported. No support for router port. 3618 */ 3619 MLXSW_ITEM32(reg, qrwe, local_port, 0x00, 16, 8); 3620 3621 /* reg_qrwe_dscp 3622 * Whether to enable DSCP rewrite (default is 0, don't rewrite). 3623 * Access: RW 3624 */ 3625 MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1); 3626 3627 /* reg_qrwe_pcp 3628 * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite). 3629 * Access: RW 3630 */ 3631 MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1); 3632 3633 static inline void mlxsw_reg_qrwe_pack(char *payload, u8 local_port, 3634 bool rewrite_pcp, bool rewrite_dscp) 3635 { 3636 MLXSW_REG_ZERO(qrwe, payload); 3637 mlxsw_reg_qrwe_local_port_set(payload, local_port); 3638 mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp); 3639 mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp); 3640 } 3641 3642 /* QPDSM - QoS Priority to DSCP Mapping 3643 * ------------------------------------ 3644 * QoS Priority to DSCP Mapping Register 3645 */ 3646 #define MLXSW_REG_QPDSM_ID 0x4011 3647 #define MLXSW_REG_QPDSM_BASE_LEN 0x04 /* base length, without records */ 3648 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4 /* record length */ 3649 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 16 3650 #define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN + \ 3651 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN * \ 3652 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT) 3653 3654 MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN); 3655 3656 /* reg_qpdsm_local_port 3657 * Local Port. Supported for data packets from CPU port. 3658 * Access: Index 3659 */ 3660 MLXSW_ITEM32(reg, qpdsm, local_port, 0x00, 16, 8); 3661 3662 /* reg_qpdsm_prio_entry_color0_e 3663 * Enable update of the entry for color 0 and a given port. 3664 * Access: WO 3665 */ 3666 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e, 3667 MLXSW_REG_QPDSM_BASE_LEN, 31, 1, 3668 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3669 3670 /* reg_qpdsm_prio_entry_color0_dscp 3671 * DSCP field in the outer label of the packet for color 0 and a given port. 3672 * Reserved when e=0. 3673 * Access: RW 3674 */ 3675 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp, 3676 MLXSW_REG_QPDSM_BASE_LEN, 24, 6, 3677 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3678 3679 /* reg_qpdsm_prio_entry_color1_e 3680 * Enable update of the entry for color 1 and a given port. 3681 * Access: WO 3682 */ 3683 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e, 3684 MLXSW_REG_QPDSM_BASE_LEN, 23, 1, 3685 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3686 3687 /* reg_qpdsm_prio_entry_color1_dscp 3688 * DSCP field in the outer label of the packet for color 1 and a given port. 3689 * Reserved when e=0. 3690 * Access: RW 3691 */ 3692 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp, 3693 MLXSW_REG_QPDSM_BASE_LEN, 16, 6, 3694 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3695 3696 /* reg_qpdsm_prio_entry_color2_e 3697 * Enable update of the entry for color 2 and a given port. 3698 * Access: WO 3699 */ 3700 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e, 3701 MLXSW_REG_QPDSM_BASE_LEN, 15, 1, 3702 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3703 3704 /* reg_qpdsm_prio_entry_color2_dscp 3705 * DSCP field in the outer label of the packet for color 2 and a given port. 3706 * Reserved when e=0. 3707 * Access: RW 3708 */ 3709 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp, 3710 MLXSW_REG_QPDSM_BASE_LEN, 8, 6, 3711 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3712 3713 static inline void mlxsw_reg_qpdsm_pack(char *payload, u8 local_port) 3714 { 3715 MLXSW_REG_ZERO(qpdsm, payload); 3716 mlxsw_reg_qpdsm_local_port_set(payload, local_port); 3717 } 3718 3719 static inline void 3720 mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp) 3721 { 3722 mlxsw_reg_qpdsm_prio_entry_color0_e_set(payload, prio, 1); 3723 mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(payload, prio, dscp); 3724 mlxsw_reg_qpdsm_prio_entry_color1_e_set(payload, prio, 1); 3725 mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(payload, prio, dscp); 3726 mlxsw_reg_qpdsm_prio_entry_color2_e_set(payload, prio, 1); 3727 mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp); 3728 } 3729 3730 /* QPDPM - QoS Port DSCP to Priority Mapping Register 3731 * -------------------------------------------------- 3732 * This register controls the mapping from DSCP field to 3733 * Switch Priority for IP packets. 3734 */ 3735 #define MLXSW_REG_QPDPM_ID 0x4013 3736 #define MLXSW_REG_QPDPM_BASE_LEN 0x4 /* base length, without records */ 3737 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2 /* record length */ 3738 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64 3739 #define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN + \ 3740 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN * \ 3741 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT) 3742 3743 MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN); 3744 3745 /* reg_qpdpm_local_port 3746 * Local Port. Supported for data packets from CPU port. 3747 * Access: Index 3748 */ 3749 MLXSW_ITEM32(reg, qpdpm, local_port, 0x00, 16, 8); 3750 3751 /* reg_qpdpm_dscp_e 3752 * Enable update of the specific entry. When cleared, the switch_prio and color 3753 * fields are ignored and the previous switch_prio and color values are 3754 * preserved. 3755 * Access: WO 3756 */ 3757 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1, 3758 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 3759 3760 /* reg_qpdpm_dscp_prio 3761 * The new Switch Priority value for the relevant DSCP value. 3762 * Access: RW 3763 */ 3764 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio, 3765 MLXSW_REG_QPDPM_BASE_LEN, 0, 4, 3766 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 3767 3768 static inline void mlxsw_reg_qpdpm_pack(char *payload, u8 local_port) 3769 { 3770 MLXSW_REG_ZERO(qpdpm, payload); 3771 mlxsw_reg_qpdpm_local_port_set(payload, local_port); 3772 } 3773 3774 static inline void 3775 mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio) 3776 { 3777 mlxsw_reg_qpdpm_dscp_entry_e_set(payload, dscp, 1); 3778 mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio); 3779 } 3780 3781 /* QTCTM - QoS Switch Traffic Class Table is Multicast-Aware Register 3782 * ------------------------------------------------------------------ 3783 * This register configures if the Switch Priority to Traffic Class mapping is 3784 * based on Multicast packet indication. If so, then multicast packets will get 3785 * a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by 3786 * QTCT. 3787 * By default, Switch Priority to Traffic Class mapping is not based on 3788 * Multicast packet indication. 3789 */ 3790 #define MLXSW_REG_QTCTM_ID 0x401A 3791 #define MLXSW_REG_QTCTM_LEN 0x08 3792 3793 MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN); 3794 3795 /* reg_qtctm_local_port 3796 * Local port number. 3797 * No support for CPU port. 3798 * Access: Index 3799 */ 3800 MLXSW_ITEM32(reg, qtctm, local_port, 0x00, 16, 8); 3801 3802 /* reg_qtctm_mc 3803 * Multicast Mode 3804 * Whether Switch Priority to Traffic Class mapping is based on Multicast packet 3805 * indication (default is 0, not based on Multicast packet indication). 3806 */ 3807 MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1); 3808 3809 static inline void 3810 mlxsw_reg_qtctm_pack(char *payload, u8 local_port, bool mc) 3811 { 3812 MLXSW_REG_ZERO(qtctm, payload); 3813 mlxsw_reg_qtctm_local_port_set(payload, local_port); 3814 mlxsw_reg_qtctm_mc_set(payload, mc); 3815 } 3816 3817 /* PMLP - Ports Module to Local Port Register 3818 * ------------------------------------------ 3819 * Configures the assignment of modules to local ports. 3820 */ 3821 #define MLXSW_REG_PMLP_ID 0x5002 3822 #define MLXSW_REG_PMLP_LEN 0x40 3823 3824 MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN); 3825 3826 /* reg_pmlp_rxtx 3827 * 0 - Tx value is used for both Tx and Rx. 3828 * 1 - Rx value is taken from a separte field. 3829 * Access: RW 3830 */ 3831 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1); 3832 3833 /* reg_pmlp_local_port 3834 * Local port number. 3835 * Access: Index 3836 */ 3837 MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8); 3838 3839 /* reg_pmlp_width 3840 * 0 - Unmap local port. 3841 * 1 - Lane 0 is used. 3842 * 2 - Lanes 0 and 1 are used. 3843 * 4 - Lanes 0, 1, 2 and 3 are used. 3844 * Access: RW 3845 */ 3846 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8); 3847 3848 /* reg_pmlp_module 3849 * Module number. 3850 * Access: RW 3851 */ 3852 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false); 3853 3854 /* reg_pmlp_tx_lane 3855 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well. 3856 * Access: RW 3857 */ 3858 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 0x00, false); 3859 3860 /* reg_pmlp_rx_lane 3861 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is 3862 * equal to Tx lane. 3863 * Access: RW 3864 */ 3865 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 0x00, false); 3866 3867 static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port) 3868 { 3869 MLXSW_REG_ZERO(pmlp, payload); 3870 mlxsw_reg_pmlp_local_port_set(payload, local_port); 3871 } 3872 3873 /* PMTU - Port MTU Register 3874 * ------------------------ 3875 * Configures and reports the port MTU. 3876 */ 3877 #define MLXSW_REG_PMTU_ID 0x5003 3878 #define MLXSW_REG_PMTU_LEN 0x10 3879 3880 MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN); 3881 3882 /* reg_pmtu_local_port 3883 * Local port number. 3884 * Access: Index 3885 */ 3886 MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8); 3887 3888 /* reg_pmtu_max_mtu 3889 * Maximum MTU. 3890 * When port type (e.g. Ethernet) is configured, the relevant MTU is 3891 * reported, otherwise the minimum between the max_mtu of the different 3892 * types is reported. 3893 * Access: RO 3894 */ 3895 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16); 3896 3897 /* reg_pmtu_admin_mtu 3898 * MTU value to set port to. Must be smaller or equal to max_mtu. 3899 * Note: If port type is Infiniband, then port must be disabled, when its 3900 * MTU is set. 3901 * Access: RW 3902 */ 3903 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16); 3904 3905 /* reg_pmtu_oper_mtu 3906 * The actual MTU configured on the port. Packets exceeding this size 3907 * will be dropped. 3908 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband 3909 * oper_mtu might be smaller than admin_mtu. 3910 * Access: RO 3911 */ 3912 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16); 3913 3914 static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port, 3915 u16 new_mtu) 3916 { 3917 MLXSW_REG_ZERO(pmtu, payload); 3918 mlxsw_reg_pmtu_local_port_set(payload, local_port); 3919 mlxsw_reg_pmtu_max_mtu_set(payload, 0); 3920 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu); 3921 mlxsw_reg_pmtu_oper_mtu_set(payload, 0); 3922 } 3923 3924 /* PTYS - Port Type and Speed Register 3925 * ----------------------------------- 3926 * Configures and reports the port speed type. 3927 * 3928 * Note: When set while the link is up, the changes will not take effect 3929 * until the port transitions from down to up state. 3930 */ 3931 #define MLXSW_REG_PTYS_ID 0x5004 3932 #define MLXSW_REG_PTYS_LEN 0x40 3933 3934 MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN); 3935 3936 /* an_disable_admin 3937 * Auto negotiation disable administrative configuration 3938 * 0 - Device doesn't support AN disable. 3939 * 1 - Device supports AN disable. 3940 * Access: RW 3941 */ 3942 MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1); 3943 3944 /* reg_ptys_local_port 3945 * Local port number. 3946 * Access: Index 3947 */ 3948 MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8); 3949 3950 #define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0) 3951 #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2) 3952 3953 /* reg_ptys_proto_mask 3954 * Protocol mask. Indicates which protocol is used. 3955 * 0 - Infiniband. 3956 * 1 - Fibre Channel. 3957 * 2 - Ethernet. 3958 * Access: Index 3959 */ 3960 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3); 3961 3962 enum { 3963 MLXSW_REG_PTYS_AN_STATUS_NA, 3964 MLXSW_REG_PTYS_AN_STATUS_OK, 3965 MLXSW_REG_PTYS_AN_STATUS_FAIL, 3966 }; 3967 3968 /* reg_ptys_an_status 3969 * Autonegotiation status. 3970 * Access: RO 3971 */ 3972 MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4); 3973 3974 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0) 3975 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1) 3976 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2) 3977 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3) 3978 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4) 3979 #define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2 BIT(5) 3980 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6) 3981 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7) 3982 #define MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4 BIT(8) 3983 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12) 3984 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13) 3985 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14) 3986 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15) 3987 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16) 3988 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18) 3989 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19) 3990 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20) 3991 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21) 3992 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22) 3993 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23) 3994 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX BIT(24) 3995 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(25) 3996 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T BIT(26) 3997 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27) 3998 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28) 3999 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29) 4000 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30) 4001 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31) 4002 4003 /* reg_ptys_eth_proto_cap 4004 * Ethernet port supported speeds and protocols. 4005 * Access: RO 4006 */ 4007 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32); 4008 4009 /* reg_ptys_ib_link_width_cap 4010 * IB port supported widths. 4011 * Access: RO 4012 */ 4013 MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16); 4014 4015 #define MLXSW_REG_PTYS_IB_SPEED_SDR BIT(0) 4016 #define MLXSW_REG_PTYS_IB_SPEED_DDR BIT(1) 4017 #define MLXSW_REG_PTYS_IB_SPEED_QDR BIT(2) 4018 #define MLXSW_REG_PTYS_IB_SPEED_FDR10 BIT(3) 4019 #define MLXSW_REG_PTYS_IB_SPEED_FDR BIT(4) 4020 #define MLXSW_REG_PTYS_IB_SPEED_EDR BIT(5) 4021 4022 /* reg_ptys_ib_proto_cap 4023 * IB port supported speeds and protocols. 4024 * Access: RO 4025 */ 4026 MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16); 4027 4028 /* reg_ptys_eth_proto_admin 4029 * Speed and protocol to set port to. 4030 * Access: RW 4031 */ 4032 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32); 4033 4034 /* reg_ptys_ib_link_width_admin 4035 * IB width to set port to. 4036 * Access: RW 4037 */ 4038 MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16); 4039 4040 /* reg_ptys_ib_proto_admin 4041 * IB speeds and protocols to set port to. 4042 * Access: RW 4043 */ 4044 MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16); 4045 4046 /* reg_ptys_eth_proto_oper 4047 * The current speed and protocol configured for the port. 4048 * Access: RO 4049 */ 4050 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32); 4051 4052 /* reg_ptys_ib_link_width_oper 4053 * The current IB width to set port to. 4054 * Access: RO 4055 */ 4056 MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16); 4057 4058 /* reg_ptys_ib_proto_oper 4059 * The current IB speed and protocol. 4060 * Access: RO 4061 */ 4062 MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16); 4063 4064 /* reg_ptys_eth_proto_lp_advertise 4065 * The protocols that were advertised by the link partner during 4066 * autonegotiation. 4067 * Access: RO 4068 */ 4069 MLXSW_ITEM32(reg, ptys, eth_proto_lp_advertise, 0x30, 0, 32); 4070 4071 static inline void mlxsw_reg_ptys_eth_pack(char *payload, u8 local_port, 4072 u32 proto_admin, bool autoneg) 4073 { 4074 MLXSW_REG_ZERO(ptys, payload); 4075 mlxsw_reg_ptys_local_port_set(payload, local_port); 4076 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4077 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin); 4078 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4079 } 4080 4081 static inline void mlxsw_reg_ptys_eth_unpack(char *payload, 4082 u32 *p_eth_proto_cap, 4083 u32 *p_eth_proto_adm, 4084 u32 *p_eth_proto_oper) 4085 { 4086 if (p_eth_proto_cap) 4087 *p_eth_proto_cap = mlxsw_reg_ptys_eth_proto_cap_get(payload); 4088 if (p_eth_proto_adm) 4089 *p_eth_proto_adm = mlxsw_reg_ptys_eth_proto_admin_get(payload); 4090 if (p_eth_proto_oper) 4091 *p_eth_proto_oper = mlxsw_reg_ptys_eth_proto_oper_get(payload); 4092 } 4093 4094 static inline void mlxsw_reg_ptys_ib_pack(char *payload, u8 local_port, 4095 u16 proto_admin, u16 link_width) 4096 { 4097 MLXSW_REG_ZERO(ptys, payload); 4098 mlxsw_reg_ptys_local_port_set(payload, local_port); 4099 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB); 4100 mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin); 4101 mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width); 4102 } 4103 4104 static inline void mlxsw_reg_ptys_ib_unpack(char *payload, u16 *p_ib_proto_cap, 4105 u16 *p_ib_link_width_cap, 4106 u16 *p_ib_proto_oper, 4107 u16 *p_ib_link_width_oper) 4108 { 4109 if (p_ib_proto_cap) 4110 *p_ib_proto_cap = mlxsw_reg_ptys_ib_proto_cap_get(payload); 4111 if (p_ib_link_width_cap) 4112 *p_ib_link_width_cap = 4113 mlxsw_reg_ptys_ib_link_width_cap_get(payload); 4114 if (p_ib_proto_oper) 4115 *p_ib_proto_oper = mlxsw_reg_ptys_ib_proto_oper_get(payload); 4116 if (p_ib_link_width_oper) 4117 *p_ib_link_width_oper = 4118 mlxsw_reg_ptys_ib_link_width_oper_get(payload); 4119 } 4120 4121 /* PPAD - Port Physical Address Register 4122 * ------------------------------------- 4123 * The PPAD register configures the per port physical MAC address. 4124 */ 4125 #define MLXSW_REG_PPAD_ID 0x5005 4126 #define MLXSW_REG_PPAD_LEN 0x10 4127 4128 MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN); 4129 4130 /* reg_ppad_single_base_mac 4131 * 0: base_mac, local port should be 0 and mac[7:0] is 4132 * reserved. HW will set incremental 4133 * 1: single_mac - mac of the local_port 4134 * Access: RW 4135 */ 4136 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1); 4137 4138 /* reg_ppad_local_port 4139 * port number, if single_base_mac = 0 then local_port is reserved 4140 * Access: RW 4141 */ 4142 MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8); 4143 4144 /* reg_ppad_mac 4145 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved. 4146 * If single_base_mac = 1 - the per port MAC address 4147 * Access: RW 4148 */ 4149 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6); 4150 4151 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac, 4152 u8 local_port) 4153 { 4154 MLXSW_REG_ZERO(ppad, payload); 4155 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac); 4156 mlxsw_reg_ppad_local_port_set(payload, local_port); 4157 } 4158 4159 /* PAOS - Ports Administrative and Operational Status Register 4160 * ----------------------------------------------------------- 4161 * Configures and retrieves per port administrative and operational status. 4162 */ 4163 #define MLXSW_REG_PAOS_ID 0x5006 4164 #define MLXSW_REG_PAOS_LEN 0x10 4165 4166 MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN); 4167 4168 /* reg_paos_swid 4169 * Switch partition ID with which to associate the port. 4170 * Note: while external ports uses unique local port numbers (and thus swid is 4171 * redundant), router ports use the same local port number where swid is the 4172 * only indication for the relevant port. 4173 * Access: Index 4174 */ 4175 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8); 4176 4177 /* reg_paos_local_port 4178 * Local port number. 4179 * Access: Index 4180 */ 4181 MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8); 4182 4183 /* reg_paos_admin_status 4184 * Port administrative state (the desired state of the port): 4185 * 1 - Up. 4186 * 2 - Down. 4187 * 3 - Up once. This means that in case of link failure, the port won't go 4188 * into polling mode, but will wait to be re-enabled by software. 4189 * 4 - Disabled by system. Can only be set by hardware. 4190 * Access: RW 4191 */ 4192 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4); 4193 4194 /* reg_paos_oper_status 4195 * Port operational state (the current state): 4196 * 1 - Up. 4197 * 2 - Down. 4198 * 3 - Down by port failure. This means that the device will not let the 4199 * port up again until explicitly specified by software. 4200 * Access: RO 4201 */ 4202 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4); 4203 4204 /* reg_paos_ase 4205 * Admin state update enabled. 4206 * Access: WO 4207 */ 4208 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1); 4209 4210 /* reg_paos_ee 4211 * Event update enable. If this bit is set, event generation will be 4212 * updated based on the e field. 4213 * Access: WO 4214 */ 4215 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1); 4216 4217 /* reg_paos_e 4218 * Event generation on operational state change: 4219 * 0 - Do not generate event. 4220 * 1 - Generate Event. 4221 * 2 - Generate Single Event. 4222 * Access: RW 4223 */ 4224 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2); 4225 4226 static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port, 4227 enum mlxsw_port_admin_status status) 4228 { 4229 MLXSW_REG_ZERO(paos, payload); 4230 mlxsw_reg_paos_swid_set(payload, 0); 4231 mlxsw_reg_paos_local_port_set(payload, local_port); 4232 mlxsw_reg_paos_admin_status_set(payload, status); 4233 mlxsw_reg_paos_oper_status_set(payload, 0); 4234 mlxsw_reg_paos_ase_set(payload, 1); 4235 mlxsw_reg_paos_ee_set(payload, 1); 4236 mlxsw_reg_paos_e_set(payload, 1); 4237 } 4238 4239 /* PFCC - Ports Flow Control Configuration Register 4240 * ------------------------------------------------ 4241 * Configures and retrieves the per port flow control configuration. 4242 */ 4243 #define MLXSW_REG_PFCC_ID 0x5007 4244 #define MLXSW_REG_PFCC_LEN 0x20 4245 4246 MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN); 4247 4248 /* reg_pfcc_local_port 4249 * Local port number. 4250 * Access: Index 4251 */ 4252 MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8); 4253 4254 /* reg_pfcc_pnat 4255 * Port number access type. Determines the way local_port is interpreted: 4256 * 0 - Local port number. 4257 * 1 - IB / label port number. 4258 * Access: Index 4259 */ 4260 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2); 4261 4262 /* reg_pfcc_shl_cap 4263 * Send to higher layers capabilities: 4264 * 0 - No capability of sending Pause and PFC frames to higher layers. 4265 * 1 - Device has capability of sending Pause and PFC frames to higher 4266 * layers. 4267 * Access: RO 4268 */ 4269 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1); 4270 4271 /* reg_pfcc_shl_opr 4272 * Send to higher layers operation: 4273 * 0 - Pause and PFC frames are handled by the port (default). 4274 * 1 - Pause and PFC frames are handled by the port and also sent to 4275 * higher layers. Only valid if shl_cap = 1. 4276 * Access: RW 4277 */ 4278 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1); 4279 4280 /* reg_pfcc_ppan 4281 * Pause policy auto negotiation. 4282 * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx. 4283 * 1 - Enabled. When auto-negotiation is performed, set the Pause policy 4284 * based on the auto-negotiation resolution. 4285 * Access: RW 4286 * 4287 * Note: The auto-negotiation advertisement is set according to pptx and 4288 * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0. 4289 */ 4290 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4); 4291 4292 /* reg_pfcc_prio_mask_tx 4293 * Bit per priority indicating if Tx flow control policy should be 4294 * updated based on bit pfctx. 4295 * Access: WO 4296 */ 4297 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8); 4298 4299 /* reg_pfcc_prio_mask_rx 4300 * Bit per priority indicating if Rx flow control policy should be 4301 * updated based on bit pfcrx. 4302 * Access: WO 4303 */ 4304 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8); 4305 4306 /* reg_pfcc_pptx 4307 * Admin Pause policy on Tx. 4308 * 0 - Never generate Pause frames (default). 4309 * 1 - Generate Pause frames according to Rx buffer threshold. 4310 * Access: RW 4311 */ 4312 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1); 4313 4314 /* reg_pfcc_aptx 4315 * Active (operational) Pause policy on Tx. 4316 * 0 - Never generate Pause frames. 4317 * 1 - Generate Pause frames according to Rx buffer threshold. 4318 * Access: RO 4319 */ 4320 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1); 4321 4322 /* reg_pfcc_pfctx 4323 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask: 4324 * 0 - Never generate priority Pause frames on the specified priority 4325 * (default). 4326 * 1 - Generate priority Pause frames according to Rx buffer threshold on 4327 * the specified priority. 4328 * Access: RW 4329 * 4330 * Note: pfctx and pptx must be mutually exclusive. 4331 */ 4332 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8); 4333 4334 /* reg_pfcc_pprx 4335 * Admin Pause policy on Rx. 4336 * 0 - Ignore received Pause frames (default). 4337 * 1 - Respect received Pause frames. 4338 * Access: RW 4339 */ 4340 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1); 4341 4342 /* reg_pfcc_aprx 4343 * Active (operational) Pause policy on Rx. 4344 * 0 - Ignore received Pause frames. 4345 * 1 - Respect received Pause frames. 4346 * Access: RO 4347 */ 4348 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1); 4349 4350 /* reg_pfcc_pfcrx 4351 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask: 4352 * 0 - Ignore incoming priority Pause frames on the specified priority 4353 * (default). 4354 * 1 - Respect incoming priority Pause frames on the specified priority. 4355 * Access: RW 4356 */ 4357 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8); 4358 4359 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF 4360 4361 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en) 4362 { 4363 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 4364 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 4365 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en); 4366 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en); 4367 } 4368 4369 static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port) 4370 { 4371 MLXSW_REG_ZERO(pfcc, payload); 4372 mlxsw_reg_pfcc_local_port_set(payload, local_port); 4373 } 4374 4375 /* PPCNT - Ports Performance Counters Register 4376 * ------------------------------------------- 4377 * The PPCNT register retrieves per port performance counters. 4378 */ 4379 #define MLXSW_REG_PPCNT_ID 0x5008 4380 #define MLXSW_REG_PPCNT_LEN 0x100 4381 #define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08 4382 4383 MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN); 4384 4385 /* reg_ppcnt_swid 4386 * For HCA: must be always 0. 4387 * Switch partition ID to associate port with. 4388 * Switch partitions are numbered from 0 to 7 inclusively. 4389 * Switch partition 254 indicates stacking ports. 4390 * Switch partition 255 indicates all switch partitions. 4391 * Only valid on Set() operation with local_port=255. 4392 * Access: Index 4393 */ 4394 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8); 4395 4396 /* reg_ppcnt_local_port 4397 * Local port number. 4398 * 255 indicates all ports on the device, and is only allowed 4399 * for Set() operation. 4400 * Access: Index 4401 */ 4402 MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8); 4403 4404 /* reg_ppcnt_pnat 4405 * Port number access type: 4406 * 0 - Local port number 4407 * 1 - IB port number 4408 * Access: Index 4409 */ 4410 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2); 4411 4412 enum mlxsw_reg_ppcnt_grp { 4413 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0, 4414 MLXSW_REG_PPCNT_RFC_2863_CNT = 0x1, 4415 MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2, 4416 MLXSW_REG_PPCNT_RFC_3635_CNT = 0x3, 4417 MLXSW_REG_PPCNT_EXT_CNT = 0x5, 4418 MLXSW_REG_PPCNT_DISCARD_CNT = 0x6, 4419 MLXSW_REG_PPCNT_PRIO_CNT = 0x10, 4420 MLXSW_REG_PPCNT_TC_CNT = 0x11, 4421 MLXSW_REG_PPCNT_TC_CONG_TC = 0x13, 4422 }; 4423 4424 /* reg_ppcnt_grp 4425 * Performance counter group. 4426 * Group 63 indicates all groups. Only valid on Set() operation with 4427 * clr bit set. 4428 * 0x0: IEEE 802.3 Counters 4429 * 0x1: RFC 2863 Counters 4430 * 0x2: RFC 2819 Counters 4431 * 0x3: RFC 3635 Counters 4432 * 0x5: Ethernet Extended Counters 4433 * 0x6: Ethernet Discard Counters 4434 * 0x8: Link Level Retransmission Counters 4435 * 0x10: Per Priority Counters 4436 * 0x11: Per Traffic Class Counters 4437 * 0x12: Physical Layer Counters 4438 * 0x13: Per Traffic Class Congestion Counters 4439 * Access: Index 4440 */ 4441 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6); 4442 4443 /* reg_ppcnt_clr 4444 * Clear counters. Setting the clr bit will reset the counter value 4445 * for all counters in the counter group. This bit can be set 4446 * for both Set() and Get() operation. 4447 * Access: OP 4448 */ 4449 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1); 4450 4451 /* reg_ppcnt_prio_tc 4452 * Priority for counter set that support per priority, valid values: 0-7. 4453 * Traffic class for counter set that support per traffic class, 4454 * valid values: 0- cap_max_tclass-1 . 4455 * For HCA: cap_max_tclass is always 8. 4456 * Otherwise must be 0. 4457 * Access: Index 4458 */ 4459 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5); 4460 4461 /* Ethernet IEEE 802.3 Counter Group */ 4462 4463 /* reg_ppcnt_a_frames_transmitted_ok 4464 * Access: RO 4465 */ 4466 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok, 4467 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4468 4469 /* reg_ppcnt_a_frames_received_ok 4470 * Access: RO 4471 */ 4472 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok, 4473 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4474 4475 /* reg_ppcnt_a_frame_check_sequence_errors 4476 * Access: RO 4477 */ 4478 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors, 4479 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 4480 4481 /* reg_ppcnt_a_alignment_errors 4482 * Access: RO 4483 */ 4484 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors, 4485 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 4486 4487 /* reg_ppcnt_a_octets_transmitted_ok 4488 * Access: RO 4489 */ 4490 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok, 4491 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 4492 4493 /* reg_ppcnt_a_octets_received_ok 4494 * Access: RO 4495 */ 4496 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok, 4497 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 4498 4499 /* reg_ppcnt_a_multicast_frames_xmitted_ok 4500 * Access: RO 4501 */ 4502 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok, 4503 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 4504 4505 /* reg_ppcnt_a_broadcast_frames_xmitted_ok 4506 * Access: RO 4507 */ 4508 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok, 4509 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 4510 4511 /* reg_ppcnt_a_multicast_frames_received_ok 4512 * Access: RO 4513 */ 4514 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok, 4515 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 4516 4517 /* reg_ppcnt_a_broadcast_frames_received_ok 4518 * Access: RO 4519 */ 4520 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok, 4521 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 4522 4523 /* reg_ppcnt_a_in_range_length_errors 4524 * Access: RO 4525 */ 4526 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors, 4527 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 4528 4529 /* reg_ppcnt_a_out_of_range_length_field 4530 * Access: RO 4531 */ 4532 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field, 4533 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 4534 4535 /* reg_ppcnt_a_frame_too_long_errors 4536 * Access: RO 4537 */ 4538 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors, 4539 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4540 4541 /* reg_ppcnt_a_symbol_error_during_carrier 4542 * Access: RO 4543 */ 4544 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier, 4545 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 4546 4547 /* reg_ppcnt_a_mac_control_frames_transmitted 4548 * Access: RO 4549 */ 4550 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted, 4551 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4552 4553 /* reg_ppcnt_a_mac_control_frames_received 4554 * Access: RO 4555 */ 4556 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received, 4557 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 4558 4559 /* reg_ppcnt_a_unsupported_opcodes_received 4560 * Access: RO 4561 */ 4562 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received, 4563 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 4564 4565 /* reg_ppcnt_a_pause_mac_ctrl_frames_received 4566 * Access: RO 4567 */ 4568 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received, 4569 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 4570 4571 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted 4572 * Access: RO 4573 */ 4574 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted, 4575 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 4576 4577 /* Ethernet RFC 2863 Counter Group */ 4578 4579 /* reg_ppcnt_if_in_discards 4580 * Access: RO 4581 */ 4582 MLXSW_ITEM64(reg, ppcnt, if_in_discards, 4583 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 4584 4585 /* reg_ppcnt_if_out_discards 4586 * Access: RO 4587 */ 4588 MLXSW_ITEM64(reg, ppcnt, if_out_discards, 4589 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 4590 4591 /* reg_ppcnt_if_out_errors 4592 * Access: RO 4593 */ 4594 MLXSW_ITEM64(reg, ppcnt, if_out_errors, 4595 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 4596 4597 /* Ethernet RFC 2819 Counter Group */ 4598 4599 /* reg_ppcnt_ether_stats_undersize_pkts 4600 * Access: RO 4601 */ 4602 MLXSW_ITEM64(reg, ppcnt, ether_stats_undersize_pkts, 4603 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 4604 4605 /* reg_ppcnt_ether_stats_oversize_pkts 4606 * Access: RO 4607 */ 4608 MLXSW_ITEM64(reg, ppcnt, ether_stats_oversize_pkts, 4609 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 4610 4611 /* reg_ppcnt_ether_stats_fragments 4612 * Access: RO 4613 */ 4614 MLXSW_ITEM64(reg, ppcnt, ether_stats_fragments, 4615 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 4616 4617 /* reg_ppcnt_ether_stats_pkts64octets 4618 * Access: RO 4619 */ 4620 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets, 4621 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 4622 4623 /* reg_ppcnt_ether_stats_pkts65to127octets 4624 * Access: RO 4625 */ 4626 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets, 4627 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4628 4629 /* reg_ppcnt_ether_stats_pkts128to255octets 4630 * Access: RO 4631 */ 4632 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets, 4633 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 4634 4635 /* reg_ppcnt_ether_stats_pkts256to511octets 4636 * Access: RO 4637 */ 4638 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets, 4639 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4640 4641 /* reg_ppcnt_ether_stats_pkts512to1023octets 4642 * Access: RO 4643 */ 4644 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets, 4645 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 4646 4647 /* reg_ppcnt_ether_stats_pkts1024to1518octets 4648 * Access: RO 4649 */ 4650 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets, 4651 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 4652 4653 /* reg_ppcnt_ether_stats_pkts1519to2047octets 4654 * Access: RO 4655 */ 4656 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets, 4657 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 4658 4659 /* reg_ppcnt_ether_stats_pkts2048to4095octets 4660 * Access: RO 4661 */ 4662 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets, 4663 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 4664 4665 /* reg_ppcnt_ether_stats_pkts4096to8191octets 4666 * Access: RO 4667 */ 4668 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets, 4669 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64); 4670 4671 /* reg_ppcnt_ether_stats_pkts8192to10239octets 4672 * Access: RO 4673 */ 4674 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets, 4675 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64); 4676 4677 /* Ethernet RFC 3635 Counter Group */ 4678 4679 /* reg_ppcnt_dot3stats_fcs_errors 4680 * Access: RO 4681 */ 4682 MLXSW_ITEM64(reg, ppcnt, dot3stats_fcs_errors, 4683 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4684 4685 /* reg_ppcnt_dot3stats_symbol_errors 4686 * Access: RO 4687 */ 4688 MLXSW_ITEM64(reg, ppcnt, dot3stats_symbol_errors, 4689 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4690 4691 /* reg_ppcnt_dot3control_in_unknown_opcodes 4692 * Access: RO 4693 */ 4694 MLXSW_ITEM64(reg, ppcnt, dot3control_in_unknown_opcodes, 4695 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 4696 4697 /* reg_ppcnt_dot3in_pause_frames 4698 * Access: RO 4699 */ 4700 MLXSW_ITEM64(reg, ppcnt, dot3in_pause_frames, 4701 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4702 4703 /* Ethernet Extended Counter Group Counters */ 4704 4705 /* reg_ppcnt_ecn_marked 4706 * Access: RO 4707 */ 4708 MLXSW_ITEM64(reg, ppcnt, ecn_marked, 4709 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4710 4711 /* Ethernet Discard Counter Group Counters */ 4712 4713 /* reg_ppcnt_ingress_general 4714 * Access: RO 4715 */ 4716 MLXSW_ITEM64(reg, ppcnt, ingress_general, 4717 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4718 4719 /* reg_ppcnt_ingress_policy_engine 4720 * Access: RO 4721 */ 4722 MLXSW_ITEM64(reg, ppcnt, ingress_policy_engine, 4723 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4724 4725 /* reg_ppcnt_ingress_vlan_membership 4726 * Access: RO 4727 */ 4728 MLXSW_ITEM64(reg, ppcnt, ingress_vlan_membership, 4729 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 4730 4731 /* reg_ppcnt_ingress_tag_frame_type 4732 * Access: RO 4733 */ 4734 MLXSW_ITEM64(reg, ppcnt, ingress_tag_frame_type, 4735 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 4736 4737 /* reg_ppcnt_egress_vlan_membership 4738 * Access: RO 4739 */ 4740 MLXSW_ITEM64(reg, ppcnt, egress_vlan_membership, 4741 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 4742 4743 /* reg_ppcnt_loopback_filter 4744 * Access: RO 4745 */ 4746 MLXSW_ITEM64(reg, ppcnt, loopback_filter, 4747 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 4748 4749 /* reg_ppcnt_egress_general 4750 * Access: RO 4751 */ 4752 MLXSW_ITEM64(reg, ppcnt, egress_general, 4753 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 4754 4755 /* reg_ppcnt_egress_hoq 4756 * Access: RO 4757 */ 4758 MLXSW_ITEM64(reg, ppcnt, egress_hoq, 4759 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 4760 4761 /* reg_ppcnt_egress_policy_engine 4762 * Access: RO 4763 */ 4764 MLXSW_ITEM64(reg, ppcnt, egress_policy_engine, 4765 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 4766 4767 /* reg_ppcnt_ingress_tx_link_down 4768 * Access: RO 4769 */ 4770 MLXSW_ITEM64(reg, ppcnt, ingress_tx_link_down, 4771 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 4772 4773 /* reg_ppcnt_egress_stp_filter 4774 * Access: RO 4775 */ 4776 MLXSW_ITEM64(reg, ppcnt, egress_stp_filter, 4777 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4778 4779 /* reg_ppcnt_egress_sll 4780 * Access: RO 4781 */ 4782 MLXSW_ITEM64(reg, ppcnt, egress_sll, 4783 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4784 4785 /* Ethernet Per Priority Group Counters */ 4786 4787 /* reg_ppcnt_rx_octets 4788 * Access: RO 4789 */ 4790 MLXSW_ITEM64(reg, ppcnt, rx_octets, 4791 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4792 4793 /* reg_ppcnt_rx_frames 4794 * Access: RO 4795 */ 4796 MLXSW_ITEM64(reg, ppcnt, rx_frames, 4797 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 4798 4799 /* reg_ppcnt_tx_octets 4800 * Access: RO 4801 */ 4802 MLXSW_ITEM64(reg, ppcnt, tx_octets, 4803 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 4804 4805 /* reg_ppcnt_tx_frames 4806 * Access: RO 4807 */ 4808 MLXSW_ITEM64(reg, ppcnt, tx_frames, 4809 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 4810 4811 /* reg_ppcnt_rx_pause 4812 * Access: RO 4813 */ 4814 MLXSW_ITEM64(reg, ppcnt, rx_pause, 4815 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 4816 4817 /* reg_ppcnt_rx_pause_duration 4818 * Access: RO 4819 */ 4820 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration, 4821 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 4822 4823 /* reg_ppcnt_tx_pause 4824 * Access: RO 4825 */ 4826 MLXSW_ITEM64(reg, ppcnt, tx_pause, 4827 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4828 4829 /* reg_ppcnt_tx_pause_duration 4830 * Access: RO 4831 */ 4832 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration, 4833 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 4834 4835 /* reg_ppcnt_rx_pause_transition 4836 * Access: RO 4837 */ 4838 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition, 4839 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4840 4841 /* Ethernet Per Traffic Group Counters */ 4842 4843 /* reg_ppcnt_tc_transmit_queue 4844 * Contains the transmit queue depth in cells of traffic class 4845 * selected by prio_tc and the port selected by local_port. 4846 * The field cannot be cleared. 4847 * Access: RO 4848 */ 4849 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue, 4850 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4851 4852 /* reg_ppcnt_tc_no_buffer_discard_uc 4853 * The number of unicast packets dropped due to lack of shared 4854 * buffer resources. 4855 * Access: RO 4856 */ 4857 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc, 4858 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4859 4860 /* Ethernet Per Traffic Class Congestion Group Counters */ 4861 4862 /* reg_ppcnt_wred_discard 4863 * Access: RO 4864 */ 4865 MLXSW_ITEM64(reg, ppcnt, wred_discard, 4866 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4867 4868 static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port, 4869 enum mlxsw_reg_ppcnt_grp grp, 4870 u8 prio_tc) 4871 { 4872 MLXSW_REG_ZERO(ppcnt, payload); 4873 mlxsw_reg_ppcnt_swid_set(payload, 0); 4874 mlxsw_reg_ppcnt_local_port_set(payload, local_port); 4875 mlxsw_reg_ppcnt_pnat_set(payload, 0); 4876 mlxsw_reg_ppcnt_grp_set(payload, grp); 4877 mlxsw_reg_ppcnt_clr_set(payload, 0); 4878 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc); 4879 } 4880 4881 /* PLIB - Port Local to InfiniBand Port 4882 * ------------------------------------ 4883 * The PLIB register performs mapping from Local Port into InfiniBand Port. 4884 */ 4885 #define MLXSW_REG_PLIB_ID 0x500A 4886 #define MLXSW_REG_PLIB_LEN 0x10 4887 4888 MLXSW_REG_DEFINE(plib, MLXSW_REG_PLIB_ID, MLXSW_REG_PLIB_LEN); 4889 4890 /* reg_plib_local_port 4891 * Local port number. 4892 * Access: Index 4893 */ 4894 MLXSW_ITEM32(reg, plib, local_port, 0x00, 16, 8); 4895 4896 /* reg_plib_ib_port 4897 * InfiniBand port remapping for local_port. 4898 * Access: RW 4899 */ 4900 MLXSW_ITEM32(reg, plib, ib_port, 0x00, 0, 8); 4901 4902 /* PPTB - Port Prio To Buffer Register 4903 * ----------------------------------- 4904 * Configures the switch priority to buffer table. 4905 */ 4906 #define MLXSW_REG_PPTB_ID 0x500B 4907 #define MLXSW_REG_PPTB_LEN 0x10 4908 4909 MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN); 4910 4911 enum { 4912 MLXSW_REG_PPTB_MM_UM, 4913 MLXSW_REG_PPTB_MM_UNICAST, 4914 MLXSW_REG_PPTB_MM_MULTICAST, 4915 }; 4916 4917 /* reg_pptb_mm 4918 * Mapping mode. 4919 * 0 - Map both unicast and multicast packets to the same buffer. 4920 * 1 - Map only unicast packets. 4921 * 2 - Map only multicast packets. 4922 * Access: Index 4923 * 4924 * Note: SwitchX-2 only supports the first option. 4925 */ 4926 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2); 4927 4928 /* reg_pptb_local_port 4929 * Local port number. 4930 * Access: Index 4931 */ 4932 MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8); 4933 4934 /* reg_pptb_um 4935 * Enables the update of the untagged_buf field. 4936 * Access: RW 4937 */ 4938 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1); 4939 4940 /* reg_pptb_pm 4941 * Enables the update of the prio_to_buff field. 4942 * Bit <i> is a flag for updating the mapping for switch priority <i>. 4943 * Access: RW 4944 */ 4945 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8); 4946 4947 /* reg_pptb_prio_to_buff 4948 * Mapping of switch priority <i> to one of the allocated receive port 4949 * buffers. 4950 * Access: RW 4951 */ 4952 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4); 4953 4954 /* reg_pptb_pm_msb 4955 * Enables the update of the prio_to_buff field. 4956 * Bit <i> is a flag for updating the mapping for switch priority <i+8>. 4957 * Access: RW 4958 */ 4959 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8); 4960 4961 /* reg_pptb_untagged_buff 4962 * Mapping of untagged frames to one of the allocated receive port buffers. 4963 * Access: RW 4964 * 4965 * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for 4966 * Spectrum, as it maps untagged packets based on the default switch priority. 4967 */ 4968 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4); 4969 4970 /* reg_pptb_prio_to_buff_msb 4971 * Mapping of switch priority <i+8> to one of the allocated receive port 4972 * buffers. 4973 * Access: RW 4974 */ 4975 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4); 4976 4977 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF 4978 4979 static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port) 4980 { 4981 MLXSW_REG_ZERO(pptb, payload); 4982 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM); 4983 mlxsw_reg_pptb_local_port_set(payload, local_port); 4984 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 4985 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 4986 } 4987 4988 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio, 4989 u8 buff) 4990 { 4991 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff); 4992 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff); 4993 } 4994 4995 /* PBMC - Port Buffer Management Control Register 4996 * ---------------------------------------------- 4997 * The PBMC register configures and retrieves the port packet buffer 4998 * allocation for different Prios, and the Pause threshold management. 4999 */ 5000 #define MLXSW_REG_PBMC_ID 0x500C 5001 #define MLXSW_REG_PBMC_LEN 0x6C 5002 5003 MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN); 5004 5005 /* reg_pbmc_local_port 5006 * Local port number. 5007 * Access: Index 5008 */ 5009 MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8); 5010 5011 /* reg_pbmc_xoff_timer_value 5012 * When device generates a pause frame, it uses this value as the pause 5013 * timer (time for the peer port to pause in quota-512 bit time). 5014 * Access: RW 5015 */ 5016 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16); 5017 5018 /* reg_pbmc_xoff_refresh 5019 * The time before a new pause frame should be sent to refresh the pause RW 5020 * state. Using the same units as xoff_timer_value above (in quota-512 bit 5021 * time). 5022 * Access: RW 5023 */ 5024 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16); 5025 5026 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11 5027 5028 /* reg_pbmc_buf_lossy 5029 * The field indicates if the buffer is lossy. 5030 * 0 - Lossless 5031 * 1 - Lossy 5032 * Access: RW 5033 */ 5034 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false); 5035 5036 /* reg_pbmc_buf_epsb 5037 * Eligible for Port Shared buffer. 5038 * If epsb is set, packets assigned to buffer are allowed to insert the port 5039 * shared buffer. 5040 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved. 5041 * Access: RW 5042 */ 5043 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false); 5044 5045 /* reg_pbmc_buf_size 5046 * The part of the packet buffer array is allocated for the specific buffer. 5047 * Units are represented in cells. 5048 * Access: RW 5049 */ 5050 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false); 5051 5052 /* reg_pbmc_buf_xoff_threshold 5053 * Once the amount of data in the buffer goes above this value, device 5054 * starts sending PFC frames for all priorities associated with the 5055 * buffer. Units are represented in cells. Reserved in case of lossy 5056 * buffer. 5057 * Access: RW 5058 * 5059 * Note: In Spectrum, reserved for buffer[9]. 5060 */ 5061 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16, 5062 0x08, 0x04, false); 5063 5064 /* reg_pbmc_buf_xon_threshold 5065 * When the amount of data in the buffer goes below this value, device 5066 * stops sending PFC frames for the priorities associated with the 5067 * buffer. Units are represented in cells. Reserved in case of lossy 5068 * buffer. 5069 * Access: RW 5070 * 5071 * Note: In Spectrum, reserved for buffer[9]. 5072 */ 5073 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16, 5074 0x08, 0x04, false); 5075 5076 static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port, 5077 u16 xoff_timer_value, u16 xoff_refresh) 5078 { 5079 MLXSW_REG_ZERO(pbmc, payload); 5080 mlxsw_reg_pbmc_local_port_set(payload, local_port); 5081 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value); 5082 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh); 5083 } 5084 5085 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload, 5086 int buf_index, 5087 u16 size) 5088 { 5089 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1); 5090 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5091 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5092 } 5093 5094 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload, 5095 int buf_index, u16 size, 5096 u16 threshold) 5097 { 5098 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0); 5099 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5100 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5101 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold); 5102 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold); 5103 } 5104 5105 /* PSPA - Port Switch Partition Allocation 5106 * --------------------------------------- 5107 * Controls the association of a port with a switch partition and enables 5108 * configuring ports as stacking ports. 5109 */ 5110 #define MLXSW_REG_PSPA_ID 0x500D 5111 #define MLXSW_REG_PSPA_LEN 0x8 5112 5113 MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN); 5114 5115 /* reg_pspa_swid 5116 * Switch partition ID. 5117 * Access: RW 5118 */ 5119 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8); 5120 5121 /* reg_pspa_local_port 5122 * Local port number. 5123 * Access: Index 5124 */ 5125 MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8); 5126 5127 /* reg_pspa_sub_port 5128 * Virtual port within the local port. Set to 0 when virtual ports are 5129 * disabled on the local port. 5130 * Access: Index 5131 */ 5132 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8); 5133 5134 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port) 5135 { 5136 MLXSW_REG_ZERO(pspa, payload); 5137 mlxsw_reg_pspa_swid_set(payload, swid); 5138 mlxsw_reg_pspa_local_port_set(payload, local_port); 5139 mlxsw_reg_pspa_sub_port_set(payload, 0); 5140 } 5141 5142 /* HTGT - Host Trap Group Table 5143 * ---------------------------- 5144 * Configures the properties for forwarding to CPU. 5145 */ 5146 #define MLXSW_REG_HTGT_ID 0x7002 5147 #define MLXSW_REG_HTGT_LEN 0x20 5148 5149 MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN); 5150 5151 /* reg_htgt_swid 5152 * Switch partition ID. 5153 * Access: Index 5154 */ 5155 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8); 5156 5157 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */ 5158 5159 /* reg_htgt_type 5160 * CPU path type. 5161 * Access: RW 5162 */ 5163 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4); 5164 5165 enum mlxsw_reg_htgt_trap_group { 5166 MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 5167 MLXSW_REG_HTGT_TRAP_GROUP_SX2_RX, 5168 MLXSW_REG_HTGT_TRAP_GROUP_SX2_CTRL, 5169 MLXSW_REG_HTGT_TRAP_GROUP_SP_STP, 5170 MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP, 5171 MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP, 5172 MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP, 5173 MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP, 5174 MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF, 5175 MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM, 5176 MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST, 5177 MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP, 5178 MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS, 5179 MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP, 5180 MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE, 5181 MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME, 5182 MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP, 5183 MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF, 5184 MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT, 5185 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD, 5186 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND, 5187 MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR, 5188 }; 5189 5190 /* reg_htgt_trap_group 5191 * Trap group number. User defined number specifying which trap groups 5192 * should be forwarded to the CPU. The mapping between trap IDs and trap 5193 * groups is configured using HPKT register. 5194 * Access: Index 5195 */ 5196 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8); 5197 5198 enum { 5199 MLXSW_REG_HTGT_POLICER_DISABLE, 5200 MLXSW_REG_HTGT_POLICER_ENABLE, 5201 }; 5202 5203 /* reg_htgt_pide 5204 * Enable policer ID specified using 'pid' field. 5205 * Access: RW 5206 */ 5207 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1); 5208 5209 #define MLXSW_REG_HTGT_INVALID_POLICER 0xff 5210 5211 /* reg_htgt_pid 5212 * Policer ID for the trap group. 5213 * Access: RW 5214 */ 5215 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8); 5216 5217 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0 5218 5219 /* reg_htgt_mirror_action 5220 * Mirror action to use. 5221 * 0 - Trap to CPU. 5222 * 1 - Trap to CPU and mirror to a mirroring agent. 5223 * 2 - Mirror to a mirroring agent and do not trap to CPU. 5224 * Access: RW 5225 * 5226 * Note: Mirroring to a mirroring agent is only supported in Spectrum. 5227 */ 5228 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2); 5229 5230 /* reg_htgt_mirroring_agent 5231 * Mirroring agent. 5232 * Access: RW 5233 */ 5234 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3); 5235 5236 #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0 5237 5238 /* reg_htgt_priority 5239 * Trap group priority. 5240 * In case a packet matches multiple classification rules, the packet will 5241 * only be trapped once, based on the trap ID associated with the group (via 5242 * register HPKT) with the highest priority. 5243 * Supported values are 0-7, with 7 represnting the highest priority. 5244 * Access: RW 5245 * 5246 * Note: In SwitchX-2 this field is ignored and the priority value is replaced 5247 * by the 'trap_group' field. 5248 */ 5249 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4); 5250 5251 #define MLXSW_REG_HTGT_DEFAULT_TC 7 5252 5253 /* reg_htgt_local_path_cpu_tclass 5254 * CPU ingress traffic class for the trap group. 5255 * Access: RW 5256 */ 5257 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6); 5258 5259 enum mlxsw_reg_htgt_local_path_rdq { 5260 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13, 5261 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14, 5262 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15, 5263 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15, 5264 }; 5265 /* reg_htgt_local_path_rdq 5266 * Receive descriptor queue (RDQ) to use for the trap group. 5267 * Access: RW 5268 */ 5269 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6); 5270 5271 static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id, 5272 u8 priority, u8 tc) 5273 { 5274 MLXSW_REG_ZERO(htgt, payload); 5275 5276 if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) { 5277 mlxsw_reg_htgt_pide_set(payload, 5278 MLXSW_REG_HTGT_POLICER_DISABLE); 5279 } else { 5280 mlxsw_reg_htgt_pide_set(payload, 5281 MLXSW_REG_HTGT_POLICER_ENABLE); 5282 mlxsw_reg_htgt_pid_set(payload, policer_id); 5283 } 5284 5285 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL); 5286 mlxsw_reg_htgt_trap_group_set(payload, group); 5287 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU); 5288 mlxsw_reg_htgt_mirroring_agent_set(payload, 0); 5289 mlxsw_reg_htgt_priority_set(payload, priority); 5290 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc); 5291 mlxsw_reg_htgt_local_path_rdq_set(payload, group); 5292 } 5293 5294 /* HPKT - Host Packet Trap 5295 * ----------------------- 5296 * Configures trap IDs inside trap groups. 5297 */ 5298 #define MLXSW_REG_HPKT_ID 0x7003 5299 #define MLXSW_REG_HPKT_LEN 0x10 5300 5301 MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN); 5302 5303 enum { 5304 MLXSW_REG_HPKT_ACK_NOT_REQUIRED, 5305 MLXSW_REG_HPKT_ACK_REQUIRED, 5306 }; 5307 5308 /* reg_hpkt_ack 5309 * Require acknowledgements from the host for events. 5310 * If set, then the device will wait for the event it sent to be acknowledged 5311 * by the host. This option is only relevant for event trap IDs. 5312 * Access: RW 5313 * 5314 * Note: Currently not supported by firmware. 5315 */ 5316 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1); 5317 5318 enum mlxsw_reg_hpkt_action { 5319 MLXSW_REG_HPKT_ACTION_FORWARD, 5320 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU, 5321 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU, 5322 MLXSW_REG_HPKT_ACTION_DISCARD, 5323 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD, 5324 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD, 5325 }; 5326 5327 /* reg_hpkt_action 5328 * Action to perform on packet when trapped. 5329 * 0 - No action. Forward to CPU based on switching rules. 5330 * 1 - Trap to CPU (CPU receives sole copy). 5331 * 2 - Mirror to CPU (CPU receives a replica of the packet). 5332 * 3 - Discard. 5333 * 4 - Soft discard (allow other traps to act on the packet). 5334 * 5 - Trap and soft discard (allow other traps to overwrite this trap). 5335 * Access: RW 5336 * 5337 * Note: Must be set to 0 (forward) for event trap IDs, as they are already 5338 * addressed to the CPU. 5339 */ 5340 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3); 5341 5342 /* reg_hpkt_trap_group 5343 * Trap group to associate the trap with. 5344 * Access: RW 5345 */ 5346 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6); 5347 5348 /* reg_hpkt_trap_id 5349 * Trap ID. 5350 * Access: Index 5351 * 5352 * Note: A trap ID can only be associated with a single trap group. The device 5353 * will associate the trap ID with the last trap group configured. 5354 */ 5355 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9); 5356 5357 enum { 5358 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT, 5359 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER, 5360 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER, 5361 }; 5362 5363 /* reg_hpkt_ctrl 5364 * Configure dedicated buffer resources for control packets. 5365 * Ignored by SwitchX-2. 5366 * 0 - Keep factory defaults. 5367 * 1 - Do not use control buffer for this trap ID. 5368 * 2 - Use control buffer for this trap ID. 5369 * Access: RW 5370 */ 5371 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2); 5372 5373 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id, 5374 enum mlxsw_reg_htgt_trap_group trap_group, 5375 bool is_ctrl) 5376 { 5377 MLXSW_REG_ZERO(hpkt, payload); 5378 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED); 5379 mlxsw_reg_hpkt_action_set(payload, action); 5380 mlxsw_reg_hpkt_trap_group_set(payload, trap_group); 5381 mlxsw_reg_hpkt_trap_id_set(payload, trap_id); 5382 mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ? 5383 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER : 5384 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER); 5385 } 5386 5387 /* RGCR - Router General Configuration Register 5388 * -------------------------------------------- 5389 * The register is used for setting up the router configuration. 5390 */ 5391 #define MLXSW_REG_RGCR_ID 0x8001 5392 #define MLXSW_REG_RGCR_LEN 0x28 5393 5394 MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN); 5395 5396 /* reg_rgcr_ipv4_en 5397 * IPv4 router enable. 5398 * Access: RW 5399 */ 5400 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1); 5401 5402 /* reg_rgcr_ipv6_en 5403 * IPv6 router enable. 5404 * Access: RW 5405 */ 5406 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1); 5407 5408 /* reg_rgcr_max_router_interfaces 5409 * Defines the maximum number of active router interfaces for all virtual 5410 * routers. 5411 * Access: RW 5412 */ 5413 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16); 5414 5415 /* reg_rgcr_usp 5416 * Update switch priority and packet color. 5417 * 0 - Preserve the value of Switch Priority and packet color. 5418 * 1 - Recalculate the value of Switch Priority and packet color. 5419 * Access: RW 5420 * 5421 * Note: Not supported by SwitchX and SwitchX-2. 5422 */ 5423 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1); 5424 5425 /* reg_rgcr_pcp_rw 5426 * Indicates how to handle the pcp_rewrite_en value: 5427 * 0 - Preserve the value of pcp_rewrite_en. 5428 * 2 - Disable PCP rewrite. 5429 * 3 - Enable PCP rewrite. 5430 * Access: RW 5431 * 5432 * Note: Not supported by SwitchX and SwitchX-2. 5433 */ 5434 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2); 5435 5436 /* reg_rgcr_activity_dis 5437 * Activity disable: 5438 * 0 - Activity will be set when an entry is hit (default). 5439 * 1 - Activity will not be set when an entry is hit. 5440 * 5441 * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry 5442 * (RALUE). 5443 * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host 5444 * Entry (RAUHT). 5445 * Bits 2:7 are reserved. 5446 * Access: RW 5447 * 5448 * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB. 5449 */ 5450 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8); 5451 5452 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en, 5453 bool ipv6_en) 5454 { 5455 MLXSW_REG_ZERO(rgcr, payload); 5456 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en); 5457 mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en); 5458 } 5459 5460 /* RITR - Router Interface Table Register 5461 * -------------------------------------- 5462 * The register is used to configure the router interface table. 5463 */ 5464 #define MLXSW_REG_RITR_ID 0x8002 5465 #define MLXSW_REG_RITR_LEN 0x40 5466 5467 MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN); 5468 5469 /* reg_ritr_enable 5470 * Enables routing on the router interface. 5471 * Access: RW 5472 */ 5473 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1); 5474 5475 /* reg_ritr_ipv4 5476 * IPv4 routing enable. Enables routing of IPv4 traffic on the router 5477 * interface. 5478 * Access: RW 5479 */ 5480 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1); 5481 5482 /* reg_ritr_ipv6 5483 * IPv6 routing enable. Enables routing of IPv6 traffic on the router 5484 * interface. 5485 * Access: RW 5486 */ 5487 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1); 5488 5489 /* reg_ritr_ipv4_mc 5490 * IPv4 multicast routing enable. 5491 * Access: RW 5492 */ 5493 MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1); 5494 5495 /* reg_ritr_ipv6_mc 5496 * IPv6 multicast routing enable. 5497 * Access: RW 5498 */ 5499 MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1); 5500 5501 enum mlxsw_reg_ritr_if_type { 5502 /* VLAN interface. */ 5503 MLXSW_REG_RITR_VLAN_IF, 5504 /* FID interface. */ 5505 MLXSW_REG_RITR_FID_IF, 5506 /* Sub-port interface. */ 5507 MLXSW_REG_RITR_SP_IF, 5508 /* Loopback Interface. */ 5509 MLXSW_REG_RITR_LOOPBACK_IF, 5510 }; 5511 5512 /* reg_ritr_type 5513 * Router interface type as per enum mlxsw_reg_ritr_if_type. 5514 * Access: RW 5515 */ 5516 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3); 5517 5518 enum { 5519 MLXSW_REG_RITR_RIF_CREATE, 5520 MLXSW_REG_RITR_RIF_DEL, 5521 }; 5522 5523 /* reg_ritr_op 5524 * Opcode: 5525 * 0 - Create or edit RIF. 5526 * 1 - Delete RIF. 5527 * Reserved for SwitchX-2. For Spectrum, editing of interface properties 5528 * is not supported. An interface must be deleted and re-created in order 5529 * to update properties. 5530 * Access: WO 5531 */ 5532 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2); 5533 5534 /* reg_ritr_rif 5535 * Router interface index. A pointer to the Router Interface Table. 5536 * Access: Index 5537 */ 5538 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16); 5539 5540 /* reg_ritr_ipv4_fe 5541 * IPv4 Forwarding Enable. 5542 * Enables routing of IPv4 traffic on the router interface. When disabled, 5543 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 5544 * Not supported in SwitchX-2. 5545 * Access: RW 5546 */ 5547 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1); 5548 5549 /* reg_ritr_ipv6_fe 5550 * IPv6 Forwarding Enable. 5551 * Enables routing of IPv6 traffic on the router interface. When disabled, 5552 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 5553 * Not supported in SwitchX-2. 5554 * Access: RW 5555 */ 5556 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1); 5557 5558 /* reg_ritr_ipv4_mc_fe 5559 * IPv4 Multicast Forwarding Enable. 5560 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 5561 * will be enabled. 5562 * Access: RW 5563 */ 5564 MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1); 5565 5566 /* reg_ritr_ipv6_mc_fe 5567 * IPv6 Multicast Forwarding Enable. 5568 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 5569 * will be enabled. 5570 * Access: RW 5571 */ 5572 MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1); 5573 5574 /* reg_ritr_lb_en 5575 * Loop-back filter enable for unicast packets. 5576 * If the flag is set then loop-back filter for unicast packets is 5577 * implemented on the RIF. Multicast packets are always subject to 5578 * loop-back filtering. 5579 * Access: RW 5580 */ 5581 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1); 5582 5583 /* reg_ritr_virtual_router 5584 * Virtual router ID associated with the router interface. 5585 * Access: RW 5586 */ 5587 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16); 5588 5589 /* reg_ritr_mtu 5590 * Router interface MTU. 5591 * Access: RW 5592 */ 5593 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16); 5594 5595 /* reg_ritr_if_swid 5596 * Switch partition ID. 5597 * Access: RW 5598 */ 5599 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8); 5600 5601 /* reg_ritr_if_mac 5602 * Router interface MAC address. 5603 * In Spectrum, all MAC addresses must have the same 38 MSBits. 5604 * Access: RW 5605 */ 5606 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6); 5607 5608 /* reg_ritr_if_vrrp_id_ipv6 5609 * VRRP ID for IPv6 5610 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 5611 * Access: RW 5612 */ 5613 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8); 5614 5615 /* reg_ritr_if_vrrp_id_ipv4 5616 * VRRP ID for IPv4 5617 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 5618 * Access: RW 5619 */ 5620 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8); 5621 5622 /* VLAN Interface */ 5623 5624 /* reg_ritr_vlan_if_vid 5625 * VLAN ID. 5626 * Access: RW 5627 */ 5628 MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12); 5629 5630 /* FID Interface */ 5631 5632 /* reg_ritr_fid_if_fid 5633 * Filtering ID. Used to connect a bridge to the router. Only FIDs from 5634 * the vFID range are supported. 5635 * Access: RW 5636 */ 5637 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16); 5638 5639 static inline void mlxsw_reg_ritr_fid_set(char *payload, 5640 enum mlxsw_reg_ritr_if_type rif_type, 5641 u16 fid) 5642 { 5643 if (rif_type == MLXSW_REG_RITR_FID_IF) 5644 mlxsw_reg_ritr_fid_if_fid_set(payload, fid); 5645 else 5646 mlxsw_reg_ritr_vlan_if_vid_set(payload, fid); 5647 } 5648 5649 /* Sub-port Interface */ 5650 5651 /* reg_ritr_sp_if_lag 5652 * LAG indication. When this bit is set the system_port field holds the 5653 * LAG identifier. 5654 * Access: RW 5655 */ 5656 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1); 5657 5658 /* reg_ritr_sp_system_port 5659 * Port unique indentifier. When lag bit is set, this field holds the 5660 * lag_id in bits 0:9. 5661 * Access: RW 5662 */ 5663 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16); 5664 5665 /* reg_ritr_sp_if_vid 5666 * VLAN ID. 5667 * Access: RW 5668 */ 5669 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12); 5670 5671 /* Loopback Interface */ 5672 5673 enum mlxsw_reg_ritr_loopback_protocol { 5674 /* IPinIP IPv4 underlay Unicast */ 5675 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4, 5676 /* IPinIP IPv6 underlay Unicast */ 5677 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6, 5678 /* IPinIP generic - used for Spectrum-2 underlay RIF */ 5679 MLXSW_REG_RITR_LOOPBACK_GENERIC, 5680 }; 5681 5682 /* reg_ritr_loopback_protocol 5683 * Access: RW 5684 */ 5685 MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4); 5686 5687 enum mlxsw_reg_ritr_loopback_ipip_type { 5688 /* Tunnel is IPinIP. */ 5689 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP, 5690 /* Tunnel is GRE, no key. */ 5691 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP, 5692 /* Tunnel is GRE, with a key. */ 5693 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP, 5694 }; 5695 5696 /* reg_ritr_loopback_ipip_type 5697 * Encapsulation type. 5698 * Access: RW 5699 */ 5700 MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4); 5701 5702 enum mlxsw_reg_ritr_loopback_ipip_options { 5703 /* The key is defined by gre_key. */ 5704 MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET, 5705 }; 5706 5707 /* reg_ritr_loopback_ipip_options 5708 * Access: RW 5709 */ 5710 MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4); 5711 5712 /* reg_ritr_loopback_ipip_uvr 5713 * Underlay Virtual Router ID. 5714 * Range is 0..cap_max_virtual_routers-1. 5715 * Reserved for Spectrum-2. 5716 * Access: RW 5717 */ 5718 MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16); 5719 5720 /* reg_ritr_loopback_ipip_underlay_rif 5721 * Underlay ingress router interface. 5722 * Reserved for Spectrum. 5723 * Access: RW 5724 */ 5725 MLXSW_ITEM32(reg, ritr, loopback_ipip_underlay_rif, 0x14, 0, 16); 5726 5727 /* reg_ritr_loopback_ipip_usip* 5728 * Encapsulation Underlay source IP. 5729 * Access: RW 5730 */ 5731 MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16); 5732 MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32); 5733 5734 /* reg_ritr_loopback_ipip_gre_key 5735 * GRE Key. 5736 * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP. 5737 * Access: RW 5738 */ 5739 MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32); 5740 5741 /* Shared between ingress/egress */ 5742 enum mlxsw_reg_ritr_counter_set_type { 5743 /* No Count. */ 5744 MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0, 5745 /* Basic. Used for router interfaces, counting the following: 5746 * - Error and Discard counters. 5747 * - Unicast, Multicast and Broadcast counters. Sharing the 5748 * same set of counters for the different type of traffic 5749 * (IPv4, IPv6 and mpls). 5750 */ 5751 MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9, 5752 }; 5753 5754 /* reg_ritr_ingress_counter_index 5755 * Counter Index for flow counter. 5756 * Access: RW 5757 */ 5758 MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24); 5759 5760 /* reg_ritr_ingress_counter_set_type 5761 * Igress Counter Set Type for router interface counter. 5762 * Access: RW 5763 */ 5764 MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8); 5765 5766 /* reg_ritr_egress_counter_index 5767 * Counter Index for flow counter. 5768 * Access: RW 5769 */ 5770 MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24); 5771 5772 /* reg_ritr_egress_counter_set_type 5773 * Egress Counter Set Type for router interface counter. 5774 * Access: RW 5775 */ 5776 MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8); 5777 5778 static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index, 5779 bool enable, bool egress) 5780 { 5781 enum mlxsw_reg_ritr_counter_set_type set_type; 5782 5783 if (enable) 5784 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC; 5785 else 5786 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT; 5787 mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type); 5788 5789 if (egress) 5790 mlxsw_reg_ritr_egress_counter_index_set(payload, index); 5791 else 5792 mlxsw_reg_ritr_ingress_counter_index_set(payload, index); 5793 } 5794 5795 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif) 5796 { 5797 MLXSW_REG_ZERO(ritr, payload); 5798 mlxsw_reg_ritr_rif_set(payload, rif); 5799 } 5800 5801 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag, 5802 u16 system_port, u16 vid) 5803 { 5804 mlxsw_reg_ritr_sp_if_lag_set(payload, lag); 5805 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port); 5806 mlxsw_reg_ritr_sp_if_vid_set(payload, vid); 5807 } 5808 5809 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable, 5810 enum mlxsw_reg_ritr_if_type type, 5811 u16 rif, u16 vr_id, u16 mtu) 5812 { 5813 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL; 5814 5815 MLXSW_REG_ZERO(ritr, payload); 5816 mlxsw_reg_ritr_enable_set(payload, enable); 5817 mlxsw_reg_ritr_ipv4_set(payload, 1); 5818 mlxsw_reg_ritr_ipv6_set(payload, 1); 5819 mlxsw_reg_ritr_ipv4_mc_set(payload, 1); 5820 mlxsw_reg_ritr_ipv6_mc_set(payload, 1); 5821 mlxsw_reg_ritr_type_set(payload, type); 5822 mlxsw_reg_ritr_op_set(payload, op); 5823 mlxsw_reg_ritr_rif_set(payload, rif); 5824 mlxsw_reg_ritr_ipv4_fe_set(payload, 1); 5825 mlxsw_reg_ritr_ipv6_fe_set(payload, 1); 5826 mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1); 5827 mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1); 5828 mlxsw_reg_ritr_lb_en_set(payload, 1); 5829 mlxsw_reg_ritr_virtual_router_set(payload, vr_id); 5830 mlxsw_reg_ritr_mtu_set(payload, mtu); 5831 } 5832 5833 static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac) 5834 { 5835 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac); 5836 } 5837 5838 static inline void 5839 mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload, 5840 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 5841 enum mlxsw_reg_ritr_loopback_ipip_options options, 5842 u16 uvr_id, u16 underlay_rif, u32 gre_key) 5843 { 5844 mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type); 5845 mlxsw_reg_ritr_loopback_ipip_options_set(payload, options); 5846 mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id); 5847 mlxsw_reg_ritr_loopback_ipip_underlay_rif_set(payload, underlay_rif); 5848 mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key); 5849 } 5850 5851 static inline void 5852 mlxsw_reg_ritr_loopback_ipip4_pack(char *payload, 5853 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 5854 enum mlxsw_reg_ritr_loopback_ipip_options options, 5855 u16 uvr_id, u16 underlay_rif, u32 usip, u32 gre_key) 5856 { 5857 mlxsw_reg_ritr_loopback_protocol_set(payload, 5858 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4); 5859 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options, 5860 uvr_id, underlay_rif, gre_key); 5861 mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip); 5862 } 5863 5864 /* RTAR - Router TCAM Allocation Register 5865 * -------------------------------------- 5866 * This register is used for allocation of regions in the TCAM table. 5867 */ 5868 #define MLXSW_REG_RTAR_ID 0x8004 5869 #define MLXSW_REG_RTAR_LEN 0x20 5870 5871 MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN); 5872 5873 enum mlxsw_reg_rtar_op { 5874 MLXSW_REG_RTAR_OP_ALLOCATE, 5875 MLXSW_REG_RTAR_OP_RESIZE, 5876 MLXSW_REG_RTAR_OP_DEALLOCATE, 5877 }; 5878 5879 /* reg_rtar_op 5880 * Access: WO 5881 */ 5882 MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4); 5883 5884 enum mlxsw_reg_rtar_key_type { 5885 MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1, 5886 MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3 5887 }; 5888 5889 /* reg_rtar_key_type 5890 * TCAM key type for the region. 5891 * Access: WO 5892 */ 5893 MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8); 5894 5895 /* reg_rtar_region_size 5896 * TCAM region size. When allocating/resizing this is the requested 5897 * size, the response is the actual size. 5898 * Note: Actual size may be larger than requested. 5899 * Reserved for op = Deallocate 5900 * Access: WO 5901 */ 5902 MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16); 5903 5904 static inline void mlxsw_reg_rtar_pack(char *payload, 5905 enum mlxsw_reg_rtar_op op, 5906 enum mlxsw_reg_rtar_key_type key_type, 5907 u16 region_size) 5908 { 5909 MLXSW_REG_ZERO(rtar, payload); 5910 mlxsw_reg_rtar_op_set(payload, op); 5911 mlxsw_reg_rtar_key_type_set(payload, key_type); 5912 mlxsw_reg_rtar_region_size_set(payload, region_size); 5913 } 5914 5915 /* RATR - Router Adjacency Table Register 5916 * -------------------------------------- 5917 * The RATR register is used to configure the Router Adjacency (next-hop) 5918 * Table. 5919 */ 5920 #define MLXSW_REG_RATR_ID 0x8008 5921 #define MLXSW_REG_RATR_LEN 0x2C 5922 5923 MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN); 5924 5925 enum mlxsw_reg_ratr_op { 5926 /* Read */ 5927 MLXSW_REG_RATR_OP_QUERY_READ = 0, 5928 /* Read and clear activity */ 5929 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2, 5930 /* Write Adjacency entry */ 5931 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1, 5932 /* Write Adjacency entry only if the activity is cleared. 5933 * The write may not succeed if the activity is set. There is not 5934 * direct feedback if the write has succeeded or not, however 5935 * the get will reveal the actual entry (SW can compare the get 5936 * response to the set command). 5937 */ 5938 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3, 5939 }; 5940 5941 /* reg_ratr_op 5942 * Note that Write operation may also be used for updating 5943 * counter_set_type and counter_index. In this case all other 5944 * fields must not be updated. 5945 * Access: OP 5946 */ 5947 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4); 5948 5949 /* reg_ratr_v 5950 * Valid bit. Indicates if the adjacency entry is valid. 5951 * Note: the device may need some time before reusing an invalidated 5952 * entry. During this time the entry can not be reused. It is 5953 * recommended to use another entry before reusing an invalidated 5954 * entry (e.g. software can put it at the end of the list for 5955 * reusing). Trying to access an invalidated entry not yet cleared 5956 * by the device results with failure indicating "Try Again" status. 5957 * When valid is '0' then egress_router_interface,trap_action, 5958 * adjacency_parameters and counters are reserved 5959 * Access: RW 5960 */ 5961 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1); 5962 5963 /* reg_ratr_a 5964 * Activity. Set for new entries. Set if a packet lookup has hit on 5965 * the specific entry. To clear the a bit, use "clear activity". 5966 * Access: RO 5967 */ 5968 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1); 5969 5970 enum mlxsw_reg_ratr_type { 5971 /* Ethernet */ 5972 MLXSW_REG_RATR_TYPE_ETHERNET, 5973 /* IPoIB Unicast without GRH. 5974 * Reserved for Spectrum. 5975 */ 5976 MLXSW_REG_RATR_TYPE_IPOIB_UC, 5977 /* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast 5978 * adjacency). 5979 * Reserved for Spectrum. 5980 */ 5981 MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH, 5982 /* IPoIB Multicast. 5983 * Reserved for Spectrum. 5984 */ 5985 MLXSW_REG_RATR_TYPE_IPOIB_MC, 5986 /* MPLS. 5987 * Reserved for SwitchX/-2. 5988 */ 5989 MLXSW_REG_RATR_TYPE_MPLS, 5990 /* IPinIP Encap. 5991 * Reserved for SwitchX/-2. 5992 */ 5993 MLXSW_REG_RATR_TYPE_IPIP, 5994 }; 5995 5996 /* reg_ratr_type 5997 * Adjacency entry type. 5998 * Access: RW 5999 */ 6000 MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4); 6001 6002 /* reg_ratr_adjacency_index_low 6003 * Bits 15:0 of index into the adjacency table. 6004 * For SwitchX and SwitchX-2, the adjacency table is linear and 6005 * used for adjacency entries only. 6006 * For Spectrum, the index is to the KVD linear. 6007 * Access: Index 6008 */ 6009 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16); 6010 6011 /* reg_ratr_egress_router_interface 6012 * Range is 0 .. cap_max_router_interfaces - 1 6013 * Access: RW 6014 */ 6015 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16); 6016 6017 enum mlxsw_reg_ratr_trap_action { 6018 MLXSW_REG_RATR_TRAP_ACTION_NOP, 6019 MLXSW_REG_RATR_TRAP_ACTION_TRAP, 6020 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU, 6021 MLXSW_REG_RATR_TRAP_ACTION_MIRROR, 6022 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS, 6023 }; 6024 6025 /* reg_ratr_trap_action 6026 * see mlxsw_reg_ratr_trap_action 6027 * Access: RW 6028 */ 6029 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4); 6030 6031 /* reg_ratr_adjacency_index_high 6032 * Bits 23:16 of the adjacency_index. 6033 * Access: Index 6034 */ 6035 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8); 6036 6037 enum mlxsw_reg_ratr_trap_id { 6038 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0, 6039 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1, 6040 }; 6041 6042 /* reg_ratr_trap_id 6043 * Trap ID to be reported to CPU. 6044 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 6045 * For trap_action of NOP, MIRROR and DISCARD_ERROR 6046 * Access: RW 6047 */ 6048 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8); 6049 6050 /* reg_ratr_eth_destination_mac 6051 * MAC address of the destination next-hop. 6052 * Access: RW 6053 */ 6054 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6); 6055 6056 enum mlxsw_reg_ratr_ipip_type { 6057 /* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */ 6058 MLXSW_REG_RATR_IPIP_TYPE_IPV4, 6059 /* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */ 6060 MLXSW_REG_RATR_IPIP_TYPE_IPV6, 6061 }; 6062 6063 /* reg_ratr_ipip_type 6064 * Underlay destination ip type. 6065 * Note: the type field must match the protocol of the router interface. 6066 * Access: RW 6067 */ 6068 MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4); 6069 6070 /* reg_ratr_ipip_ipv4_udip 6071 * Underlay ipv4 dip. 6072 * Reserved when ipip_type is IPv6. 6073 * Access: RW 6074 */ 6075 MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32); 6076 6077 /* reg_ratr_ipip_ipv6_ptr 6078 * Pointer to IPv6 underlay destination ip address. 6079 * For Spectrum: Pointer to KVD linear space. 6080 * Access: RW 6081 */ 6082 MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24); 6083 6084 enum mlxsw_reg_flow_counter_set_type { 6085 /* No count */ 6086 MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00, 6087 /* Count packets and bytes */ 6088 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03, 6089 /* Count only packets */ 6090 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05, 6091 }; 6092 6093 /* reg_ratr_counter_set_type 6094 * Counter set type for flow counters 6095 * Access: RW 6096 */ 6097 MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8); 6098 6099 /* reg_ratr_counter_index 6100 * Counter index for flow counters 6101 * Access: RW 6102 */ 6103 MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24); 6104 6105 static inline void 6106 mlxsw_reg_ratr_pack(char *payload, 6107 enum mlxsw_reg_ratr_op op, bool valid, 6108 enum mlxsw_reg_ratr_type type, 6109 u32 adjacency_index, u16 egress_rif) 6110 { 6111 MLXSW_REG_ZERO(ratr, payload); 6112 mlxsw_reg_ratr_op_set(payload, op); 6113 mlxsw_reg_ratr_v_set(payload, valid); 6114 mlxsw_reg_ratr_type_set(payload, type); 6115 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index); 6116 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16); 6117 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif); 6118 } 6119 6120 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload, 6121 const char *dest_mac) 6122 { 6123 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac); 6124 } 6125 6126 static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip) 6127 { 6128 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4); 6129 mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip); 6130 } 6131 6132 static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index, 6133 bool counter_enable) 6134 { 6135 enum mlxsw_reg_flow_counter_set_type set_type; 6136 6137 if (counter_enable) 6138 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES; 6139 else 6140 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT; 6141 6142 mlxsw_reg_ratr_counter_index_set(payload, counter_index); 6143 mlxsw_reg_ratr_counter_set_type_set(payload, set_type); 6144 } 6145 6146 /* RDPM - Router DSCP to Priority Mapping 6147 * -------------------------------------- 6148 * Controls the mapping from DSCP field to switch priority on routed packets 6149 */ 6150 #define MLXSW_REG_RDPM_ID 0x8009 6151 #define MLXSW_REG_RDPM_BASE_LEN 0x00 6152 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01 6153 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64 6154 #define MLXSW_REG_RDPM_LEN 0x40 6155 #define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \ 6156 MLXSW_REG_RDPM_LEN - \ 6157 MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN) 6158 6159 MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN); 6160 6161 /* reg_dscp_entry_e 6162 * Enable update of the specific entry 6163 * Access: Index 6164 */ 6165 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1, 6166 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 6167 6168 /* reg_dscp_entry_prio 6169 * Switch Priority 6170 * Access: RW 6171 */ 6172 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4, 6173 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 6174 6175 static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index, 6176 u8 prio) 6177 { 6178 mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1); 6179 mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio); 6180 } 6181 6182 /* RICNT - Router Interface Counter Register 6183 * ----------------------------------------- 6184 * The RICNT register retrieves per port performance counters 6185 */ 6186 #define MLXSW_REG_RICNT_ID 0x800B 6187 #define MLXSW_REG_RICNT_LEN 0x100 6188 6189 MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN); 6190 6191 /* reg_ricnt_counter_index 6192 * Counter index 6193 * Access: RW 6194 */ 6195 MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24); 6196 6197 enum mlxsw_reg_ricnt_counter_set_type { 6198 /* No Count. */ 6199 MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00, 6200 /* Basic. Used for router interfaces, counting the following: 6201 * - Error and Discard counters. 6202 * - Unicast, Multicast and Broadcast counters. Sharing the 6203 * same set of counters for the different type of traffic 6204 * (IPv4, IPv6 and mpls). 6205 */ 6206 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09, 6207 }; 6208 6209 /* reg_ricnt_counter_set_type 6210 * Counter Set Type for router interface counter 6211 * Access: RW 6212 */ 6213 MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8); 6214 6215 enum mlxsw_reg_ricnt_opcode { 6216 /* Nop. Supported only for read access*/ 6217 MLXSW_REG_RICNT_OPCODE_NOP = 0x00, 6218 /* Clear. Setting the clr bit will reset the counter value for 6219 * all counters of the specified Router Interface. 6220 */ 6221 MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08, 6222 }; 6223 6224 /* reg_ricnt_opcode 6225 * Opcode 6226 * Access: RW 6227 */ 6228 MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4); 6229 6230 /* reg_ricnt_good_unicast_packets 6231 * good unicast packets. 6232 * Access: RW 6233 */ 6234 MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64); 6235 6236 /* reg_ricnt_good_multicast_packets 6237 * good multicast packets. 6238 * Access: RW 6239 */ 6240 MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64); 6241 6242 /* reg_ricnt_good_broadcast_packets 6243 * good broadcast packets 6244 * Access: RW 6245 */ 6246 MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64); 6247 6248 /* reg_ricnt_good_unicast_bytes 6249 * A count of L3 data and padding octets not including L2 headers 6250 * for good unicast frames. 6251 * Access: RW 6252 */ 6253 MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64); 6254 6255 /* reg_ricnt_good_multicast_bytes 6256 * A count of L3 data and padding octets not including L2 headers 6257 * for good multicast frames. 6258 * Access: RW 6259 */ 6260 MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64); 6261 6262 /* reg_ritr_good_broadcast_bytes 6263 * A count of L3 data and padding octets not including L2 headers 6264 * for good broadcast frames. 6265 * Access: RW 6266 */ 6267 MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64); 6268 6269 /* reg_ricnt_error_packets 6270 * A count of errored frames that do not pass the router checks. 6271 * Access: RW 6272 */ 6273 MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64); 6274 6275 /* reg_ricnt_discrad_packets 6276 * A count of non-errored frames that do not pass the router checks. 6277 * Access: RW 6278 */ 6279 MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64); 6280 6281 /* reg_ricnt_error_bytes 6282 * A count of L3 data and padding octets not including L2 headers 6283 * for errored frames. 6284 * Access: RW 6285 */ 6286 MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64); 6287 6288 /* reg_ricnt_discard_bytes 6289 * A count of L3 data and padding octets not including L2 headers 6290 * for non-errored frames that do not pass the router checks. 6291 * Access: RW 6292 */ 6293 MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64); 6294 6295 static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index, 6296 enum mlxsw_reg_ricnt_opcode op) 6297 { 6298 MLXSW_REG_ZERO(ricnt, payload); 6299 mlxsw_reg_ricnt_op_set(payload, op); 6300 mlxsw_reg_ricnt_counter_index_set(payload, index); 6301 mlxsw_reg_ricnt_counter_set_type_set(payload, 6302 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC); 6303 } 6304 6305 /* RRCR - Router Rules Copy Register Layout 6306 * ---------------------------------------- 6307 * This register is used for moving and copying route entry rules. 6308 */ 6309 #define MLXSW_REG_RRCR_ID 0x800F 6310 #define MLXSW_REG_RRCR_LEN 0x24 6311 6312 MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN); 6313 6314 enum mlxsw_reg_rrcr_op { 6315 /* Move rules */ 6316 MLXSW_REG_RRCR_OP_MOVE, 6317 /* Copy rules */ 6318 MLXSW_REG_RRCR_OP_COPY, 6319 }; 6320 6321 /* reg_rrcr_op 6322 * Access: WO 6323 */ 6324 MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4); 6325 6326 /* reg_rrcr_offset 6327 * Offset within the region from which to copy/move. 6328 * Access: Index 6329 */ 6330 MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16); 6331 6332 /* reg_rrcr_size 6333 * The number of rules to copy/move. 6334 * Access: WO 6335 */ 6336 MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16); 6337 6338 /* reg_rrcr_table_id 6339 * Identifier of the table on which to perform the operation. Encoding is the 6340 * same as in RTAR.key_type 6341 * Access: Index 6342 */ 6343 MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4); 6344 6345 /* reg_rrcr_dest_offset 6346 * Offset within the region to which to copy/move 6347 * Access: Index 6348 */ 6349 MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16); 6350 6351 static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op, 6352 u16 offset, u16 size, 6353 enum mlxsw_reg_rtar_key_type table_id, 6354 u16 dest_offset) 6355 { 6356 MLXSW_REG_ZERO(rrcr, payload); 6357 mlxsw_reg_rrcr_op_set(payload, op); 6358 mlxsw_reg_rrcr_offset_set(payload, offset); 6359 mlxsw_reg_rrcr_size_set(payload, size); 6360 mlxsw_reg_rrcr_table_id_set(payload, table_id); 6361 mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset); 6362 } 6363 6364 /* RALTA - Router Algorithmic LPM Tree Allocation Register 6365 * ------------------------------------------------------- 6366 * RALTA is used to allocate the LPM trees of the SHSPM method. 6367 */ 6368 #define MLXSW_REG_RALTA_ID 0x8010 6369 #define MLXSW_REG_RALTA_LEN 0x04 6370 6371 MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN); 6372 6373 /* reg_ralta_op 6374 * opcode (valid for Write, must be 0 on Read) 6375 * 0 - allocate a tree 6376 * 1 - deallocate a tree 6377 * Access: OP 6378 */ 6379 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2); 6380 6381 enum mlxsw_reg_ralxx_protocol { 6382 MLXSW_REG_RALXX_PROTOCOL_IPV4, 6383 MLXSW_REG_RALXX_PROTOCOL_IPV6, 6384 }; 6385 6386 /* reg_ralta_protocol 6387 * Protocol. 6388 * Deallocation opcode: Reserved. 6389 * Access: RW 6390 */ 6391 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4); 6392 6393 /* reg_ralta_tree_id 6394 * An identifier (numbered from 1..cap_shspm_max_trees-1) representing 6395 * the tree identifier (managed by software). 6396 * Note that tree_id 0 is allocated for a default-route tree. 6397 * Access: Index 6398 */ 6399 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8); 6400 6401 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc, 6402 enum mlxsw_reg_ralxx_protocol protocol, 6403 u8 tree_id) 6404 { 6405 MLXSW_REG_ZERO(ralta, payload); 6406 mlxsw_reg_ralta_op_set(payload, !alloc); 6407 mlxsw_reg_ralta_protocol_set(payload, protocol); 6408 mlxsw_reg_ralta_tree_id_set(payload, tree_id); 6409 } 6410 6411 /* RALST - Router Algorithmic LPM Structure Tree Register 6412 * ------------------------------------------------------ 6413 * RALST is used to set and query the structure of an LPM tree. 6414 * The structure of the tree must be sorted as a sorted binary tree, while 6415 * each node is a bin that is tagged as the length of the prefixes the lookup 6416 * will refer to. Therefore, bin X refers to a set of entries with prefixes 6417 * of X bits to match with the destination address. The bin 0 indicates 6418 * the default action, when there is no match of any prefix. 6419 */ 6420 #define MLXSW_REG_RALST_ID 0x8011 6421 #define MLXSW_REG_RALST_LEN 0x104 6422 6423 MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN); 6424 6425 /* reg_ralst_root_bin 6426 * The bin number of the root bin. 6427 * 0<root_bin=<(length of IP address) 6428 * For a default-route tree configure 0xff 6429 * Access: RW 6430 */ 6431 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8); 6432 6433 /* reg_ralst_tree_id 6434 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 6435 * Access: Index 6436 */ 6437 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8); 6438 6439 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff 6440 #define MLXSW_REG_RALST_BIN_OFFSET 0x04 6441 #define MLXSW_REG_RALST_BIN_COUNT 128 6442 6443 /* reg_ralst_left_child_bin 6444 * Holding the children of the bin according to the stored tree's structure. 6445 * For trees composed of less than 4 blocks, the bins in excess are reserved. 6446 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 6447 * Access: RW 6448 */ 6449 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false); 6450 6451 /* reg_ralst_right_child_bin 6452 * Holding the children of the bin according to the stored tree's structure. 6453 * For trees composed of less than 4 blocks, the bins in excess are reserved. 6454 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 6455 * Access: RW 6456 */ 6457 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00, 6458 false); 6459 6460 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id) 6461 { 6462 MLXSW_REG_ZERO(ralst, payload); 6463 6464 /* Initialize all bins to have no left or right child */ 6465 memset(payload + MLXSW_REG_RALST_BIN_OFFSET, 6466 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2); 6467 6468 mlxsw_reg_ralst_root_bin_set(payload, root_bin); 6469 mlxsw_reg_ralst_tree_id_set(payload, tree_id); 6470 } 6471 6472 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number, 6473 u8 left_child_bin, 6474 u8 right_child_bin) 6475 { 6476 int bin_index = bin_number - 1; 6477 6478 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin); 6479 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index, 6480 right_child_bin); 6481 } 6482 6483 /* RALTB - Router Algorithmic LPM Tree Binding Register 6484 * ---------------------------------------------------- 6485 * RALTB is used to bind virtual router and protocol to an allocated LPM tree. 6486 */ 6487 #define MLXSW_REG_RALTB_ID 0x8012 6488 #define MLXSW_REG_RALTB_LEN 0x04 6489 6490 MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN); 6491 6492 /* reg_raltb_virtual_router 6493 * Virtual Router ID 6494 * Range is 0..cap_max_virtual_routers-1 6495 * Access: Index 6496 */ 6497 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16); 6498 6499 /* reg_raltb_protocol 6500 * Protocol. 6501 * Access: Index 6502 */ 6503 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4); 6504 6505 /* reg_raltb_tree_id 6506 * Tree to be used for the {virtual_router, protocol} 6507 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 6508 * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0. 6509 * Access: RW 6510 */ 6511 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8); 6512 6513 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router, 6514 enum mlxsw_reg_ralxx_protocol protocol, 6515 u8 tree_id) 6516 { 6517 MLXSW_REG_ZERO(raltb, payload); 6518 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router); 6519 mlxsw_reg_raltb_protocol_set(payload, protocol); 6520 mlxsw_reg_raltb_tree_id_set(payload, tree_id); 6521 } 6522 6523 /* RALUE - Router Algorithmic LPM Unicast Entry Register 6524 * ----------------------------------------------------- 6525 * RALUE is used to configure and query LPM entries that serve 6526 * the Unicast protocols. 6527 */ 6528 #define MLXSW_REG_RALUE_ID 0x8013 6529 #define MLXSW_REG_RALUE_LEN 0x38 6530 6531 MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN); 6532 6533 /* reg_ralue_protocol 6534 * Protocol. 6535 * Access: Index 6536 */ 6537 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4); 6538 6539 enum mlxsw_reg_ralue_op { 6540 /* Read operation. If entry doesn't exist, the operation fails. */ 6541 MLXSW_REG_RALUE_OP_QUERY_READ = 0, 6542 /* Clear on read operation. Used to read entry and 6543 * clear Activity bit. 6544 */ 6545 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1, 6546 /* Write operation. Used to write a new entry to the table. All RW 6547 * fields are written for new entry. Activity bit is set 6548 * for new entries. 6549 */ 6550 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0, 6551 /* Update operation. Used to update an existing route entry and 6552 * only update the RW fields that are detailed in the field 6553 * op_u_mask. If entry doesn't exist, the operation fails. 6554 */ 6555 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1, 6556 /* Clear activity. The Activity bit (the field a) is cleared 6557 * for the entry. 6558 */ 6559 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2, 6560 /* Delete operation. Used to delete an existing entry. If entry 6561 * doesn't exist, the operation fails. 6562 */ 6563 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3, 6564 }; 6565 6566 /* reg_ralue_op 6567 * Operation. 6568 * Access: OP 6569 */ 6570 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3); 6571 6572 /* reg_ralue_a 6573 * Activity. Set for new entries. Set if a packet lookup has hit on the 6574 * specific entry, only if the entry is a route. To clear the a bit, use 6575 * "clear activity" op. 6576 * Enabled by activity_dis in RGCR 6577 * Access: RO 6578 */ 6579 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1); 6580 6581 /* reg_ralue_virtual_router 6582 * Virtual Router ID 6583 * Range is 0..cap_max_virtual_routers-1 6584 * Access: Index 6585 */ 6586 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16); 6587 6588 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0) 6589 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1) 6590 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2) 6591 6592 /* reg_ralue_op_u_mask 6593 * opcode update mask. 6594 * On read operation, this field is reserved. 6595 * This field is valid for update opcode, otherwise - reserved. 6596 * This field is a bitmask of the fields that should be updated. 6597 * Access: WO 6598 */ 6599 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3); 6600 6601 /* reg_ralue_prefix_len 6602 * Number of bits in the prefix of the LPM route. 6603 * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes 6604 * two entries in the physical HW table. 6605 * Access: Index 6606 */ 6607 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8); 6608 6609 /* reg_ralue_dip* 6610 * The prefix of the route or of the marker that the object of the LPM 6611 * is compared with. The most significant bits of the dip are the prefix. 6612 * The least significant bits must be '0' if the prefix_len is smaller 6613 * than 128 for IPv6 or smaller than 32 for IPv4. 6614 * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved. 6615 * Access: Index 6616 */ 6617 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32); 6618 MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16); 6619 6620 enum mlxsw_reg_ralue_entry_type { 6621 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1, 6622 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2, 6623 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3, 6624 }; 6625 6626 /* reg_ralue_entry_type 6627 * Entry type. 6628 * Note - for Marker entries, the action_type and action fields are reserved. 6629 * Access: RW 6630 */ 6631 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2); 6632 6633 /* reg_ralue_bmp_len 6634 * The best match prefix length in the case that there is no match for 6635 * longer prefixes. 6636 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len 6637 * Note for any update operation with entry_type modification this 6638 * field must be set. 6639 * Access: RW 6640 */ 6641 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8); 6642 6643 enum mlxsw_reg_ralue_action_type { 6644 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE, 6645 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL, 6646 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME, 6647 }; 6648 6649 /* reg_ralue_action_type 6650 * Action Type 6651 * Indicates how the IP address is connected. 6652 * It can be connected to a local subnet through local_erif or can be 6653 * on a remote subnet connected through a next-hop router, 6654 * or transmitted to the CPU. 6655 * Reserved when entry_type = MARKER_ENTRY 6656 * Access: RW 6657 */ 6658 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2); 6659 6660 enum mlxsw_reg_ralue_trap_action { 6661 MLXSW_REG_RALUE_TRAP_ACTION_NOP, 6662 MLXSW_REG_RALUE_TRAP_ACTION_TRAP, 6663 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU, 6664 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR, 6665 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR, 6666 }; 6667 6668 /* reg_ralue_trap_action 6669 * Trap action. 6670 * For IP2ME action, only NOP and MIRROR are possible. 6671 * Access: RW 6672 */ 6673 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4); 6674 6675 /* reg_ralue_trap_id 6676 * Trap ID to be reported to CPU. 6677 * Trap ID is RTR_INGRESS0 or RTR_INGRESS1. 6678 * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved. 6679 * Access: RW 6680 */ 6681 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9); 6682 6683 /* reg_ralue_adjacency_index 6684 * Points to the first entry of the group-based ECMP. 6685 * Only relevant in case of REMOTE action. 6686 * Access: RW 6687 */ 6688 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24); 6689 6690 /* reg_ralue_ecmp_size 6691 * Amount of sequential entries starting 6692 * from the adjacency_index (the number of ECMPs). 6693 * The valid range is 1-64, 512, 1024, 2048 and 4096. 6694 * Reserved when trap_action is TRAP or DISCARD_ERROR. 6695 * Only relevant in case of REMOTE action. 6696 * Access: RW 6697 */ 6698 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13); 6699 6700 /* reg_ralue_local_erif 6701 * Egress Router Interface. 6702 * Only relevant in case of LOCAL action. 6703 * Access: RW 6704 */ 6705 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16); 6706 6707 /* reg_ralue_ip2me_v 6708 * Valid bit for the tunnel_ptr field. 6709 * If valid = 0 then trap to CPU as IP2ME trap ID. 6710 * If valid = 1 and the packet format allows NVE or IPinIP tunnel 6711 * decapsulation then tunnel decapsulation is done. 6712 * If valid = 1 and packet format does not allow NVE or IPinIP tunnel 6713 * decapsulation then trap as IP2ME trap ID. 6714 * Only relevant in case of IP2ME action. 6715 * Access: RW 6716 */ 6717 MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1); 6718 6719 /* reg_ralue_ip2me_tunnel_ptr 6720 * Tunnel Pointer for NVE or IPinIP tunnel decapsulation. 6721 * For Spectrum, pointer to KVD Linear. 6722 * Only relevant in case of IP2ME action. 6723 * Access: RW 6724 */ 6725 MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24); 6726 6727 static inline void mlxsw_reg_ralue_pack(char *payload, 6728 enum mlxsw_reg_ralxx_protocol protocol, 6729 enum mlxsw_reg_ralue_op op, 6730 u16 virtual_router, u8 prefix_len) 6731 { 6732 MLXSW_REG_ZERO(ralue, payload); 6733 mlxsw_reg_ralue_protocol_set(payload, protocol); 6734 mlxsw_reg_ralue_op_set(payload, op); 6735 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router); 6736 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len); 6737 mlxsw_reg_ralue_entry_type_set(payload, 6738 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY); 6739 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len); 6740 } 6741 6742 static inline void mlxsw_reg_ralue_pack4(char *payload, 6743 enum mlxsw_reg_ralxx_protocol protocol, 6744 enum mlxsw_reg_ralue_op op, 6745 u16 virtual_router, u8 prefix_len, 6746 u32 dip) 6747 { 6748 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 6749 mlxsw_reg_ralue_dip4_set(payload, dip); 6750 } 6751 6752 static inline void mlxsw_reg_ralue_pack6(char *payload, 6753 enum mlxsw_reg_ralxx_protocol protocol, 6754 enum mlxsw_reg_ralue_op op, 6755 u16 virtual_router, u8 prefix_len, 6756 const void *dip) 6757 { 6758 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 6759 mlxsw_reg_ralue_dip6_memcpy_to(payload, dip); 6760 } 6761 6762 static inline void 6763 mlxsw_reg_ralue_act_remote_pack(char *payload, 6764 enum mlxsw_reg_ralue_trap_action trap_action, 6765 u16 trap_id, u32 adjacency_index, u16 ecmp_size) 6766 { 6767 mlxsw_reg_ralue_action_type_set(payload, 6768 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE); 6769 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 6770 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 6771 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index); 6772 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size); 6773 } 6774 6775 static inline void 6776 mlxsw_reg_ralue_act_local_pack(char *payload, 6777 enum mlxsw_reg_ralue_trap_action trap_action, 6778 u16 trap_id, u16 local_erif) 6779 { 6780 mlxsw_reg_ralue_action_type_set(payload, 6781 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL); 6782 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 6783 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 6784 mlxsw_reg_ralue_local_erif_set(payload, local_erif); 6785 } 6786 6787 static inline void 6788 mlxsw_reg_ralue_act_ip2me_pack(char *payload) 6789 { 6790 mlxsw_reg_ralue_action_type_set(payload, 6791 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 6792 } 6793 6794 static inline void 6795 mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr) 6796 { 6797 mlxsw_reg_ralue_action_type_set(payload, 6798 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 6799 mlxsw_reg_ralue_ip2me_v_set(payload, 1); 6800 mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr); 6801 } 6802 6803 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register 6804 * ---------------------------------------------------------- 6805 * The RAUHT register is used to configure and query the Unicast Host table in 6806 * devices that implement the Algorithmic LPM. 6807 */ 6808 #define MLXSW_REG_RAUHT_ID 0x8014 6809 #define MLXSW_REG_RAUHT_LEN 0x74 6810 6811 MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN); 6812 6813 enum mlxsw_reg_rauht_type { 6814 MLXSW_REG_RAUHT_TYPE_IPV4, 6815 MLXSW_REG_RAUHT_TYPE_IPV6, 6816 }; 6817 6818 /* reg_rauht_type 6819 * Access: Index 6820 */ 6821 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2); 6822 6823 enum mlxsw_reg_rauht_op { 6824 MLXSW_REG_RAUHT_OP_QUERY_READ = 0, 6825 /* Read operation */ 6826 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1, 6827 /* Clear on read operation. Used to read entry and clear 6828 * activity bit. 6829 */ 6830 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0, 6831 /* Add. Used to write a new entry to the table. All R/W fields are 6832 * relevant for new entry. Activity bit is set for new entries. 6833 */ 6834 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1, 6835 /* Update action. Used to update an existing route entry and 6836 * only update the following fields: 6837 * trap_action, trap_id, mac, counter_set_type, counter_index 6838 */ 6839 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2, 6840 /* Clear activity. A bit is cleared for the entry. */ 6841 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3, 6842 /* Delete entry */ 6843 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4, 6844 /* Delete all host entries on a RIF. In this command, dip 6845 * field is reserved. 6846 */ 6847 }; 6848 6849 /* reg_rauht_op 6850 * Access: OP 6851 */ 6852 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3); 6853 6854 /* reg_rauht_a 6855 * Activity. Set for new entries. Set if a packet lookup has hit on 6856 * the specific entry. 6857 * To clear the a bit, use "clear activity" op. 6858 * Enabled by activity_dis in RGCR 6859 * Access: RO 6860 */ 6861 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1); 6862 6863 /* reg_rauht_rif 6864 * Router Interface 6865 * Access: Index 6866 */ 6867 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16); 6868 6869 /* reg_rauht_dip* 6870 * Destination address. 6871 * Access: Index 6872 */ 6873 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32); 6874 MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16); 6875 6876 enum mlxsw_reg_rauht_trap_action { 6877 MLXSW_REG_RAUHT_TRAP_ACTION_NOP, 6878 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP, 6879 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU, 6880 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR, 6881 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS, 6882 }; 6883 6884 /* reg_rauht_trap_action 6885 * Access: RW 6886 */ 6887 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4); 6888 6889 enum mlxsw_reg_rauht_trap_id { 6890 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0, 6891 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1, 6892 }; 6893 6894 /* reg_rauht_trap_id 6895 * Trap ID to be reported to CPU. 6896 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 6897 * For trap_action of NOP, MIRROR and DISCARD_ERROR, 6898 * trap_id is reserved. 6899 * Access: RW 6900 */ 6901 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9); 6902 6903 /* reg_rauht_counter_set_type 6904 * Counter set type for flow counters 6905 * Access: RW 6906 */ 6907 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8); 6908 6909 /* reg_rauht_counter_index 6910 * Counter index for flow counters 6911 * Access: RW 6912 */ 6913 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24); 6914 6915 /* reg_rauht_mac 6916 * MAC address. 6917 * Access: RW 6918 */ 6919 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6); 6920 6921 static inline void mlxsw_reg_rauht_pack(char *payload, 6922 enum mlxsw_reg_rauht_op op, u16 rif, 6923 const char *mac) 6924 { 6925 MLXSW_REG_ZERO(rauht, payload); 6926 mlxsw_reg_rauht_op_set(payload, op); 6927 mlxsw_reg_rauht_rif_set(payload, rif); 6928 mlxsw_reg_rauht_mac_memcpy_to(payload, mac); 6929 } 6930 6931 static inline void mlxsw_reg_rauht_pack4(char *payload, 6932 enum mlxsw_reg_rauht_op op, u16 rif, 6933 const char *mac, u32 dip) 6934 { 6935 mlxsw_reg_rauht_pack(payload, op, rif, mac); 6936 mlxsw_reg_rauht_dip4_set(payload, dip); 6937 } 6938 6939 static inline void mlxsw_reg_rauht_pack6(char *payload, 6940 enum mlxsw_reg_rauht_op op, u16 rif, 6941 const char *mac, const char *dip) 6942 { 6943 mlxsw_reg_rauht_pack(payload, op, rif, mac); 6944 mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6); 6945 mlxsw_reg_rauht_dip6_memcpy_to(payload, dip); 6946 } 6947 6948 static inline void mlxsw_reg_rauht_pack_counter(char *payload, 6949 u64 counter_index) 6950 { 6951 mlxsw_reg_rauht_counter_index_set(payload, counter_index); 6952 mlxsw_reg_rauht_counter_set_type_set(payload, 6953 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 6954 } 6955 6956 /* RALEU - Router Algorithmic LPM ECMP Update Register 6957 * --------------------------------------------------- 6958 * The register enables updating the ECMP section in the action for multiple 6959 * LPM Unicast entries in a single operation. The update is executed to 6960 * all entries of a {virtual router, protocol} tuple using the same ECMP group. 6961 */ 6962 #define MLXSW_REG_RALEU_ID 0x8015 6963 #define MLXSW_REG_RALEU_LEN 0x28 6964 6965 MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN); 6966 6967 /* reg_raleu_protocol 6968 * Protocol. 6969 * Access: Index 6970 */ 6971 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4); 6972 6973 /* reg_raleu_virtual_router 6974 * Virtual Router ID 6975 * Range is 0..cap_max_virtual_routers-1 6976 * Access: Index 6977 */ 6978 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16); 6979 6980 /* reg_raleu_adjacency_index 6981 * Adjacency Index used for matching on the existing entries. 6982 * Access: Index 6983 */ 6984 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24); 6985 6986 /* reg_raleu_ecmp_size 6987 * ECMP Size used for matching on the existing entries. 6988 * Access: Index 6989 */ 6990 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13); 6991 6992 /* reg_raleu_new_adjacency_index 6993 * New Adjacency Index. 6994 * Access: WO 6995 */ 6996 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24); 6997 6998 /* reg_raleu_new_ecmp_size 6999 * New ECMP Size. 7000 * Access: WO 7001 */ 7002 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13); 7003 7004 static inline void mlxsw_reg_raleu_pack(char *payload, 7005 enum mlxsw_reg_ralxx_protocol protocol, 7006 u16 virtual_router, 7007 u32 adjacency_index, u16 ecmp_size, 7008 u32 new_adjacency_index, 7009 u16 new_ecmp_size) 7010 { 7011 MLXSW_REG_ZERO(raleu, payload); 7012 mlxsw_reg_raleu_protocol_set(payload, protocol); 7013 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router); 7014 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index); 7015 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size); 7016 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index); 7017 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size); 7018 } 7019 7020 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register 7021 * ---------------------------------------------------------------- 7022 * The RAUHTD register allows dumping entries from the Router Unicast Host 7023 * Table. For a given session an entry is dumped no more than one time. The 7024 * first RAUHTD access after reset is a new session. A session ends when the 7025 * num_rec response is smaller than num_rec request or for IPv4 when the 7026 * num_entries is smaller than 4. The clear activity affect the current session 7027 * or the last session if a new session has not started. 7028 */ 7029 #define MLXSW_REG_RAUHTD_ID 0x8018 7030 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20 7031 #define MLXSW_REG_RAUHTD_REC_LEN 0x20 7032 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32 7033 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \ 7034 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN) 7035 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4 7036 7037 MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN); 7038 7039 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0) 7040 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3) 7041 7042 /* reg_rauhtd_filter_fields 7043 * if a bit is '0' then the relevant field is ignored and dump is done 7044 * regardless of the field value 7045 * Bit0 - filter by activity: entry_a 7046 * Bit3 - filter by entry rip: entry_rif 7047 * Access: Index 7048 */ 7049 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8); 7050 7051 enum mlxsw_reg_rauhtd_op { 7052 MLXSW_REG_RAUHTD_OP_DUMP, 7053 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR, 7054 }; 7055 7056 /* reg_rauhtd_op 7057 * Access: OP 7058 */ 7059 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2); 7060 7061 /* reg_rauhtd_num_rec 7062 * At request: number of records requested 7063 * At response: number of records dumped 7064 * For IPv4, each record has 4 entries at request and up to 4 entries 7065 * at response 7066 * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM 7067 * Access: Index 7068 */ 7069 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8); 7070 7071 /* reg_rauhtd_entry_a 7072 * Dump only if activity has value of entry_a 7073 * Reserved if filter_fields bit0 is '0' 7074 * Access: Index 7075 */ 7076 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1); 7077 7078 enum mlxsw_reg_rauhtd_type { 7079 MLXSW_REG_RAUHTD_TYPE_IPV4, 7080 MLXSW_REG_RAUHTD_TYPE_IPV6, 7081 }; 7082 7083 /* reg_rauhtd_type 7084 * Dump only if record type is: 7085 * 0 - IPv4 7086 * 1 - IPv6 7087 * Access: Index 7088 */ 7089 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4); 7090 7091 /* reg_rauhtd_entry_rif 7092 * Dump only if RIF has value of entry_rif 7093 * Reserved if filter_fields bit3 is '0' 7094 * Access: Index 7095 */ 7096 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16); 7097 7098 static inline void mlxsw_reg_rauhtd_pack(char *payload, 7099 enum mlxsw_reg_rauhtd_type type) 7100 { 7101 MLXSW_REG_ZERO(rauhtd, payload); 7102 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A); 7103 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR); 7104 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM); 7105 mlxsw_reg_rauhtd_entry_a_set(payload, 1); 7106 mlxsw_reg_rauhtd_type_set(payload, type); 7107 } 7108 7109 /* reg_rauhtd_ipv4_rec_num_entries 7110 * Number of valid entries in this record: 7111 * 0 - 1 valid entry 7112 * 1 - 2 valid entries 7113 * 2 - 3 valid entries 7114 * 3 - 4 valid entries 7115 * Access: RO 7116 */ 7117 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries, 7118 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2, 7119 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 7120 7121 /* reg_rauhtd_rec_type 7122 * Record type. 7123 * 0 - IPv4 7124 * 1 - IPv6 7125 * Access: RO 7126 */ 7127 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2, 7128 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 7129 7130 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8 7131 7132 /* reg_rauhtd_ipv4_ent_a 7133 * Activity. Set for new entries. Set if a packet lookup has hit on the 7134 * specific entry. 7135 * Access: RO 7136 */ 7137 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 7138 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 7139 7140 /* reg_rauhtd_ipv4_ent_rif 7141 * Router interface. 7142 * Access: RO 7143 */ 7144 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 7145 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 7146 7147 /* reg_rauhtd_ipv4_ent_dip 7148 * Destination IPv4 address. 7149 * Access: RO 7150 */ 7151 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0, 7152 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false); 7153 7154 #define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20 7155 7156 /* reg_rauhtd_ipv6_ent_a 7157 * Activity. Set for new entries. Set if a packet lookup has hit on the 7158 * specific entry. 7159 * Access: RO 7160 */ 7161 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 7162 MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 7163 7164 /* reg_rauhtd_ipv6_ent_rif 7165 * Router interface. 7166 * Access: RO 7167 */ 7168 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 7169 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 7170 7171 /* reg_rauhtd_ipv6_ent_dip 7172 * Destination IPv6 address. 7173 * Access: RO 7174 */ 7175 MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 7176 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10); 7177 7178 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload, 7179 int ent_index, u16 *p_rif, 7180 u32 *p_dip) 7181 { 7182 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index); 7183 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index); 7184 } 7185 7186 static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload, 7187 int rec_index, u16 *p_rif, 7188 char *p_dip) 7189 { 7190 *p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index); 7191 mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip); 7192 } 7193 7194 /* RTDP - Routing Tunnel Decap Properties Register 7195 * ----------------------------------------------- 7196 * The RTDP register is used for configuring the tunnel decap properties of NVE 7197 * and IPinIP. 7198 */ 7199 #define MLXSW_REG_RTDP_ID 0x8020 7200 #define MLXSW_REG_RTDP_LEN 0x44 7201 7202 MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN); 7203 7204 enum mlxsw_reg_rtdp_type { 7205 MLXSW_REG_RTDP_TYPE_NVE, 7206 MLXSW_REG_RTDP_TYPE_IPIP, 7207 }; 7208 7209 /* reg_rtdp_type 7210 * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type. 7211 * Access: RW 7212 */ 7213 MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4); 7214 7215 /* reg_rtdp_tunnel_index 7216 * Index to the Decap entry. 7217 * For Spectrum, Index to KVD Linear. 7218 * Access: Index 7219 */ 7220 MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24); 7221 7222 /* reg_rtdp_egress_router_interface 7223 * Underlay egress router interface. 7224 * Valid range is from 0 to cap_max_router_interfaces - 1 7225 * Access: RW 7226 */ 7227 MLXSW_ITEM32(reg, rtdp, egress_router_interface, 0x40, 0, 16); 7228 7229 /* IPinIP */ 7230 7231 /* reg_rtdp_ipip_irif 7232 * Ingress Router Interface for the overlay router 7233 * Access: RW 7234 */ 7235 MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16); 7236 7237 enum mlxsw_reg_rtdp_ipip_sip_check { 7238 /* No sip checks. */ 7239 MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO, 7240 /* Filter packet if underlay is not IPv4 or if underlay SIP does not 7241 * equal ipv4_usip. 7242 */ 7243 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4, 7244 /* Filter packet if underlay is not IPv6 or if underlay SIP does not 7245 * equal ipv6_usip. 7246 */ 7247 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3, 7248 }; 7249 7250 /* reg_rtdp_ipip_sip_check 7251 * SIP check to perform. If decapsulation failed due to these configurations 7252 * then trap_id is IPIP_DECAP_ERROR. 7253 * Access: RW 7254 */ 7255 MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3); 7256 7257 /* If set, allow decapsulation of IPinIP (without GRE). */ 7258 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP BIT(0) 7259 /* If set, allow decapsulation of IPinGREinIP without a key. */ 7260 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE BIT(1) 7261 /* If set, allow decapsulation of IPinGREinIP with a key. */ 7262 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY BIT(2) 7263 7264 /* reg_rtdp_ipip_type_check 7265 * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to 7266 * these configurations then trap_id is IPIP_DECAP_ERROR. 7267 * Access: RW 7268 */ 7269 MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3); 7270 7271 /* reg_rtdp_ipip_gre_key_check 7272 * Whether GRE key should be checked. When check is enabled: 7273 * - A packet received as IPinIP (without GRE) will always pass. 7274 * - A packet received as IPinGREinIP without a key will not pass the check. 7275 * - A packet received as IPinGREinIP with a key will pass the check only if the 7276 * key in the packet is equal to expected_gre_key. 7277 * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR. 7278 * Access: RW 7279 */ 7280 MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1); 7281 7282 /* reg_rtdp_ipip_ipv4_usip 7283 * Underlay IPv4 address for ipv4 source address check. 7284 * Reserved when sip_check is not '1'. 7285 * Access: RW 7286 */ 7287 MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32); 7288 7289 /* reg_rtdp_ipip_ipv6_usip_ptr 7290 * This field is valid when sip_check is "sipv6 check explicitly". This is a 7291 * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index 7292 * is to the KVD linear. 7293 * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6. 7294 * Access: RW 7295 */ 7296 MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24); 7297 7298 /* reg_rtdp_ipip_expected_gre_key 7299 * GRE key for checking. 7300 * Reserved when gre_key_check is '0'. 7301 * Access: RW 7302 */ 7303 MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32); 7304 7305 static inline void mlxsw_reg_rtdp_pack(char *payload, 7306 enum mlxsw_reg_rtdp_type type, 7307 u32 tunnel_index) 7308 { 7309 MLXSW_REG_ZERO(rtdp, payload); 7310 mlxsw_reg_rtdp_type_set(payload, type); 7311 mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index); 7312 } 7313 7314 static inline void 7315 mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif, 7316 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 7317 unsigned int type_check, bool gre_key_check, 7318 u32 ipv4_usip, u32 expected_gre_key) 7319 { 7320 mlxsw_reg_rtdp_ipip_irif_set(payload, irif); 7321 mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check); 7322 mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check); 7323 mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check); 7324 mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip); 7325 mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key); 7326 } 7327 7328 /* RIGR-V2 - Router Interface Group Register Version 2 7329 * --------------------------------------------------- 7330 * The RIGR_V2 register is used to add, remove and query egress interface list 7331 * of a multicast forwarding entry. 7332 */ 7333 #define MLXSW_REG_RIGR2_ID 0x8023 7334 #define MLXSW_REG_RIGR2_LEN 0xB0 7335 7336 #define MLXSW_REG_RIGR2_MAX_ERIFS 32 7337 7338 MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN); 7339 7340 /* reg_rigr2_rigr_index 7341 * KVD Linear index. 7342 * Access: Index 7343 */ 7344 MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24); 7345 7346 /* reg_rigr2_vnext 7347 * Next RIGR Index is valid. 7348 * Access: RW 7349 */ 7350 MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1); 7351 7352 /* reg_rigr2_next_rigr_index 7353 * Next RIGR Index. The index is to the KVD linear. 7354 * Reserved when vnxet = '0'. 7355 * Access: RW 7356 */ 7357 MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24); 7358 7359 /* reg_rigr2_vrmid 7360 * RMID Index is valid. 7361 * Access: RW 7362 */ 7363 MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1); 7364 7365 /* reg_rigr2_rmid_index 7366 * RMID Index. 7367 * Range 0 .. max_mid - 1 7368 * Reserved when vrmid = '0'. 7369 * The index is to the Port Group Table (PGT) 7370 * Access: RW 7371 */ 7372 MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16); 7373 7374 /* reg_rigr2_erif_entry_v 7375 * Egress Router Interface is valid. 7376 * Note that low-entries must be set if high-entries are set. For 7377 * example: if erif_entry[2].v is set then erif_entry[1].v and 7378 * erif_entry[0].v must be set. 7379 * Index can be from 0 to cap_mc_erif_list_entries-1 7380 * Access: RW 7381 */ 7382 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false); 7383 7384 /* reg_rigr2_erif_entry_erif 7385 * Egress Router Interface. 7386 * Valid range is from 0 to cap_max_router_interfaces - 1 7387 * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1 7388 * Access: RW 7389 */ 7390 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false); 7391 7392 static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index, 7393 bool vnext, u32 next_rigr_index) 7394 { 7395 MLXSW_REG_ZERO(rigr2, payload); 7396 mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index); 7397 mlxsw_reg_rigr2_vnext_set(payload, vnext); 7398 mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index); 7399 mlxsw_reg_rigr2_vrmid_set(payload, 0); 7400 mlxsw_reg_rigr2_rmid_index_set(payload, 0); 7401 } 7402 7403 static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index, 7404 bool v, u16 erif) 7405 { 7406 mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v); 7407 mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif); 7408 } 7409 7410 /* RECR-V2 - Router ECMP Configuration Version 2 Register 7411 * ------------------------------------------------------ 7412 */ 7413 #define MLXSW_REG_RECR2_ID 0x8025 7414 #define MLXSW_REG_RECR2_LEN 0x38 7415 7416 MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN); 7417 7418 /* reg_recr2_pp 7419 * Per-port configuration 7420 * Access: Index 7421 */ 7422 MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1); 7423 7424 /* reg_recr2_sh 7425 * Symmetric hash 7426 * Access: RW 7427 */ 7428 MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1); 7429 7430 /* reg_recr2_seed 7431 * Seed 7432 * Access: RW 7433 */ 7434 MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32); 7435 7436 enum { 7437 /* Enable IPv4 fields if packet is not TCP and not UDP */ 7438 MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP = 3, 7439 /* Enable IPv4 fields if packet is TCP or UDP */ 7440 MLXSW_REG_RECR2_IPV4_EN_TCP_UDP = 4, 7441 /* Enable IPv6 fields if packet is not TCP and not UDP */ 7442 MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP = 5, 7443 /* Enable IPv6 fields if packet is TCP or UDP */ 7444 MLXSW_REG_RECR2_IPV6_EN_TCP_UDP = 6, 7445 /* Enable TCP/UDP header fields if packet is IPv4 */ 7446 MLXSW_REG_RECR2_TCP_UDP_EN_IPV4 = 7, 7447 /* Enable TCP/UDP header fields if packet is IPv6 */ 7448 MLXSW_REG_RECR2_TCP_UDP_EN_IPV6 = 8, 7449 }; 7450 7451 /* reg_recr2_outer_header_enables 7452 * Bit mask where each bit enables a specific layer to be included in 7453 * the hash calculation. 7454 * Access: RW 7455 */ 7456 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1); 7457 7458 enum { 7459 /* IPv4 Source IP */ 7460 MLXSW_REG_RECR2_IPV4_SIP0 = 9, 7461 MLXSW_REG_RECR2_IPV4_SIP3 = 12, 7462 /* IPv4 Destination IP */ 7463 MLXSW_REG_RECR2_IPV4_DIP0 = 13, 7464 MLXSW_REG_RECR2_IPV4_DIP3 = 16, 7465 /* IP Protocol */ 7466 MLXSW_REG_RECR2_IPV4_PROTOCOL = 17, 7467 /* IPv6 Source IP */ 7468 MLXSW_REG_RECR2_IPV6_SIP0_7 = 21, 7469 MLXSW_REG_RECR2_IPV6_SIP8 = 29, 7470 MLXSW_REG_RECR2_IPV6_SIP15 = 36, 7471 /* IPv6 Destination IP */ 7472 MLXSW_REG_RECR2_IPV6_DIP0_7 = 37, 7473 MLXSW_REG_RECR2_IPV6_DIP8 = 45, 7474 MLXSW_REG_RECR2_IPV6_DIP15 = 52, 7475 /* IPv6 Next Header */ 7476 MLXSW_REG_RECR2_IPV6_NEXT_HEADER = 53, 7477 /* IPv6 Flow Label */ 7478 MLXSW_REG_RECR2_IPV6_FLOW_LABEL = 57, 7479 /* TCP/UDP Source Port */ 7480 MLXSW_REG_RECR2_TCP_UDP_SPORT = 74, 7481 /* TCP/UDP Destination Port */ 7482 MLXSW_REG_RECR2_TCP_UDP_DPORT = 75, 7483 }; 7484 7485 /* reg_recr2_outer_header_fields_enable 7486 * Packet fields to enable for ECMP hash subject to outer_header_enable. 7487 * Access: RW 7488 */ 7489 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1); 7490 7491 static inline void mlxsw_reg_recr2_ipv4_sip_enable(char *payload) 7492 { 7493 int i; 7494 7495 for (i = MLXSW_REG_RECR2_IPV4_SIP0; i <= MLXSW_REG_RECR2_IPV4_SIP3; i++) 7496 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7497 true); 7498 } 7499 7500 static inline void mlxsw_reg_recr2_ipv4_dip_enable(char *payload) 7501 { 7502 int i; 7503 7504 for (i = MLXSW_REG_RECR2_IPV4_DIP0; i <= MLXSW_REG_RECR2_IPV4_DIP3; i++) 7505 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7506 true); 7507 } 7508 7509 static inline void mlxsw_reg_recr2_ipv6_sip_enable(char *payload) 7510 { 7511 int i = MLXSW_REG_RECR2_IPV6_SIP0_7; 7512 7513 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true); 7514 7515 i = MLXSW_REG_RECR2_IPV6_SIP8; 7516 for (; i <= MLXSW_REG_RECR2_IPV6_SIP15; i++) 7517 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7518 true); 7519 } 7520 7521 static inline void mlxsw_reg_recr2_ipv6_dip_enable(char *payload) 7522 { 7523 int i = MLXSW_REG_RECR2_IPV6_DIP0_7; 7524 7525 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true); 7526 7527 i = MLXSW_REG_RECR2_IPV6_DIP8; 7528 for (; i <= MLXSW_REG_RECR2_IPV6_DIP15; i++) 7529 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7530 true); 7531 } 7532 7533 static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed) 7534 { 7535 MLXSW_REG_ZERO(recr2, payload); 7536 mlxsw_reg_recr2_pp_set(payload, false); 7537 mlxsw_reg_recr2_sh_set(payload, true); 7538 mlxsw_reg_recr2_seed_set(payload, seed); 7539 } 7540 7541 /* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register 7542 * -------------------------------------------------------------- 7543 * The RMFT_V2 register is used to configure and query the multicast table. 7544 */ 7545 #define MLXSW_REG_RMFT2_ID 0x8027 7546 #define MLXSW_REG_RMFT2_LEN 0x174 7547 7548 MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN); 7549 7550 /* reg_rmft2_v 7551 * Valid 7552 * Access: RW 7553 */ 7554 MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1); 7555 7556 enum mlxsw_reg_rmft2_type { 7557 MLXSW_REG_RMFT2_TYPE_IPV4, 7558 MLXSW_REG_RMFT2_TYPE_IPV6 7559 }; 7560 7561 /* reg_rmft2_type 7562 * Access: Index 7563 */ 7564 MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2); 7565 7566 enum mlxsw_sp_reg_rmft2_op { 7567 /* For Write: 7568 * Write operation. Used to write a new entry to the table. All RW 7569 * fields are relevant for new entry. Activity bit is set for new 7570 * entries - Note write with v (Valid) 0 will delete the entry. 7571 * For Query: 7572 * Read operation 7573 */ 7574 MLXSW_REG_RMFT2_OP_READ_WRITE, 7575 }; 7576 7577 /* reg_rmft2_op 7578 * Operation. 7579 * Access: OP 7580 */ 7581 MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2); 7582 7583 /* reg_rmft2_a 7584 * Activity. Set for new entries. Set if a packet lookup has hit on the specific 7585 * entry. 7586 * Access: RO 7587 */ 7588 MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1); 7589 7590 /* reg_rmft2_offset 7591 * Offset within the multicast forwarding table to write to. 7592 * Access: Index 7593 */ 7594 MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16); 7595 7596 /* reg_rmft2_virtual_router 7597 * Virtual Router ID. Range from 0..cap_max_virtual_routers-1 7598 * Access: RW 7599 */ 7600 MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16); 7601 7602 enum mlxsw_reg_rmft2_irif_mask { 7603 MLXSW_REG_RMFT2_IRIF_MASK_IGNORE, 7604 MLXSW_REG_RMFT2_IRIF_MASK_COMPARE 7605 }; 7606 7607 /* reg_rmft2_irif_mask 7608 * Ingress RIF mask. 7609 * Access: RW 7610 */ 7611 MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1); 7612 7613 /* reg_rmft2_irif 7614 * Ingress RIF index. 7615 * Access: RW 7616 */ 7617 MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16); 7618 7619 /* reg_rmft2_dip{4,6} 7620 * Destination IPv4/6 address 7621 * Access: RW 7622 */ 7623 MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16); 7624 MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32); 7625 7626 /* reg_rmft2_dip{4,6}_mask 7627 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 7628 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 7629 * Access: RW 7630 */ 7631 MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16); 7632 MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32); 7633 7634 /* reg_rmft2_sip{4,6} 7635 * Source IPv4/6 address 7636 * Access: RW 7637 */ 7638 MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16); 7639 MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32); 7640 7641 /* reg_rmft2_sip{4,6}_mask 7642 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 7643 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 7644 * Access: RW 7645 */ 7646 MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16); 7647 MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32); 7648 7649 /* reg_rmft2_flexible_action_set 7650 * ACL action set. The only supported action types in this field and in any 7651 * action-set pointed from here are as follows: 7652 * 00h: ACTION_NULL 7653 * 01h: ACTION_MAC_TTL, only TTL configuration is supported. 7654 * 03h: ACTION_TRAP 7655 * 06h: ACTION_QOS 7656 * 08h: ACTION_POLICING_MONITORING 7657 * 10h: ACTION_ROUTER_MC 7658 * Access: RW 7659 */ 7660 MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80, 7661 MLXSW_REG_FLEX_ACTION_SET_LEN); 7662 7663 static inline void 7664 mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset, 7665 u16 virtual_router, 7666 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 7667 const char *flex_action_set) 7668 { 7669 MLXSW_REG_ZERO(rmft2, payload); 7670 mlxsw_reg_rmft2_v_set(payload, v); 7671 mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE); 7672 mlxsw_reg_rmft2_offset_set(payload, offset); 7673 mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router); 7674 mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask); 7675 mlxsw_reg_rmft2_irif_set(payload, irif); 7676 if (flex_action_set) 7677 mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload, 7678 flex_action_set); 7679 } 7680 7681 static inline void 7682 mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router, 7683 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 7684 u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask, 7685 const char *flexible_action_set) 7686 { 7687 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 7688 irif_mask, irif, flexible_action_set); 7689 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4); 7690 mlxsw_reg_rmft2_dip4_set(payload, dip4); 7691 mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask); 7692 mlxsw_reg_rmft2_sip4_set(payload, sip4); 7693 mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask); 7694 } 7695 7696 static inline void 7697 mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router, 7698 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 7699 struct in6_addr dip6, struct in6_addr dip6_mask, 7700 struct in6_addr sip6, struct in6_addr sip6_mask, 7701 const char *flexible_action_set) 7702 { 7703 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 7704 irif_mask, irif, flexible_action_set); 7705 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6); 7706 mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6); 7707 mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask); 7708 mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6); 7709 mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask); 7710 } 7711 7712 /* MFCR - Management Fan Control Register 7713 * -------------------------------------- 7714 * This register controls the settings of the Fan Speed PWM mechanism. 7715 */ 7716 #define MLXSW_REG_MFCR_ID 0x9001 7717 #define MLXSW_REG_MFCR_LEN 0x08 7718 7719 MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN); 7720 7721 enum mlxsw_reg_mfcr_pwm_frequency { 7722 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00, 7723 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01, 7724 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02, 7725 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40, 7726 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41, 7727 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42, 7728 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43, 7729 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44, 7730 }; 7731 7732 /* reg_mfcr_pwm_frequency 7733 * Controls the frequency of the PWM signal. 7734 * Access: RW 7735 */ 7736 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7); 7737 7738 #define MLXSW_MFCR_TACHOS_MAX 10 7739 7740 /* reg_mfcr_tacho_active 7741 * Indicates which of the tachometer is active (bit per tachometer). 7742 * Access: RO 7743 */ 7744 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX); 7745 7746 #define MLXSW_MFCR_PWMS_MAX 5 7747 7748 /* reg_mfcr_pwm_active 7749 * Indicates which of the PWM control is active (bit per PWM). 7750 * Access: RO 7751 */ 7752 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX); 7753 7754 static inline void 7755 mlxsw_reg_mfcr_pack(char *payload, 7756 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency) 7757 { 7758 MLXSW_REG_ZERO(mfcr, payload); 7759 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency); 7760 } 7761 7762 static inline void 7763 mlxsw_reg_mfcr_unpack(char *payload, 7764 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency, 7765 u16 *p_tacho_active, u8 *p_pwm_active) 7766 { 7767 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload); 7768 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload); 7769 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload); 7770 } 7771 7772 /* MFSC - Management Fan Speed Control Register 7773 * -------------------------------------------- 7774 * This register controls the settings of the Fan Speed PWM mechanism. 7775 */ 7776 #define MLXSW_REG_MFSC_ID 0x9002 7777 #define MLXSW_REG_MFSC_LEN 0x08 7778 7779 MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN); 7780 7781 /* reg_mfsc_pwm 7782 * Fan pwm to control / monitor. 7783 * Access: Index 7784 */ 7785 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3); 7786 7787 /* reg_mfsc_pwm_duty_cycle 7788 * Controls the duty cycle of the PWM. Value range from 0..255 to 7789 * represent duty cycle of 0%...100%. 7790 * Access: RW 7791 */ 7792 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8); 7793 7794 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm, 7795 u8 pwm_duty_cycle) 7796 { 7797 MLXSW_REG_ZERO(mfsc, payload); 7798 mlxsw_reg_mfsc_pwm_set(payload, pwm); 7799 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle); 7800 } 7801 7802 /* MFSM - Management Fan Speed Measurement 7803 * --------------------------------------- 7804 * This register controls the settings of the Tacho measurements and 7805 * enables reading the Tachometer measurements. 7806 */ 7807 #define MLXSW_REG_MFSM_ID 0x9003 7808 #define MLXSW_REG_MFSM_LEN 0x08 7809 7810 MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN); 7811 7812 /* reg_mfsm_tacho 7813 * Fan tachometer index. 7814 * Access: Index 7815 */ 7816 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4); 7817 7818 /* reg_mfsm_rpm 7819 * Fan speed (round per minute). 7820 * Access: RO 7821 */ 7822 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16); 7823 7824 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho) 7825 { 7826 MLXSW_REG_ZERO(mfsm, payload); 7827 mlxsw_reg_mfsm_tacho_set(payload, tacho); 7828 } 7829 7830 /* MFSL - Management Fan Speed Limit Register 7831 * ------------------------------------------ 7832 * The Fan Speed Limit register is used to configure the fan speed 7833 * event / interrupt notification mechanism. Fan speed threshold are 7834 * defined for both under-speed and over-speed. 7835 */ 7836 #define MLXSW_REG_MFSL_ID 0x9004 7837 #define MLXSW_REG_MFSL_LEN 0x0C 7838 7839 MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN); 7840 7841 /* reg_mfsl_tacho 7842 * Fan tachometer index. 7843 * Access: Index 7844 */ 7845 MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4); 7846 7847 /* reg_mfsl_tach_min 7848 * Tachometer minimum value (minimum RPM). 7849 * Access: RW 7850 */ 7851 MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16); 7852 7853 /* reg_mfsl_tach_max 7854 * Tachometer maximum value (maximum RPM). 7855 * Access: RW 7856 */ 7857 MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16); 7858 7859 static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho, 7860 u16 tach_min, u16 tach_max) 7861 { 7862 MLXSW_REG_ZERO(mfsl, payload); 7863 mlxsw_reg_mfsl_tacho_set(payload, tacho); 7864 mlxsw_reg_mfsl_tach_min_set(payload, tach_min); 7865 mlxsw_reg_mfsl_tach_max_set(payload, tach_max); 7866 } 7867 7868 static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho, 7869 u16 *p_tach_min, u16 *p_tach_max) 7870 { 7871 if (p_tach_min) 7872 *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload); 7873 7874 if (p_tach_max) 7875 *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload); 7876 } 7877 7878 /* FORE - Fan Out of Range Event Register 7879 * -------------------------------------- 7880 * This register reports the status of the controlled fans compared to the 7881 * range defined by the MFSL register. 7882 */ 7883 #define MLXSW_REG_FORE_ID 0x9007 7884 #define MLXSW_REG_FORE_LEN 0x0C 7885 7886 MLXSW_REG_DEFINE(fore, MLXSW_REG_FORE_ID, MLXSW_REG_FORE_LEN); 7887 7888 /* fan_under_limit 7889 * Fan speed is below the low limit defined in MFSL register. Each bit relates 7890 * to a single tachometer and indicates the specific tachometer reading is 7891 * below the threshold. 7892 * Access: RO 7893 */ 7894 MLXSW_ITEM32(reg, fore, fan_under_limit, 0x00, 16, 10); 7895 7896 static inline void mlxsw_reg_fore_unpack(char *payload, u8 tacho, 7897 bool *fault) 7898 { 7899 u16 limit; 7900 7901 if (fault) { 7902 limit = mlxsw_reg_fore_fan_under_limit_get(payload); 7903 *fault = limit & BIT(tacho); 7904 } 7905 } 7906 7907 /* MTCAP - Management Temperature Capabilities 7908 * ------------------------------------------- 7909 * This register exposes the capabilities of the device and 7910 * system temperature sensing. 7911 */ 7912 #define MLXSW_REG_MTCAP_ID 0x9009 7913 #define MLXSW_REG_MTCAP_LEN 0x08 7914 7915 MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN); 7916 7917 /* reg_mtcap_sensor_count 7918 * Number of sensors supported by the device. 7919 * This includes the QSFP module sensors (if exists in the QSFP module). 7920 * Access: RO 7921 */ 7922 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7); 7923 7924 /* MTMP - Management Temperature 7925 * ----------------------------- 7926 * This register controls the settings of the temperature measurements 7927 * and enables reading the temperature measurements. Note that temperature 7928 * is in 0.125 degrees Celsius. 7929 */ 7930 #define MLXSW_REG_MTMP_ID 0x900A 7931 #define MLXSW_REG_MTMP_LEN 0x20 7932 7933 MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN); 7934 7935 /* reg_mtmp_sensor_index 7936 * Sensors index to access. 7937 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially 7938 * (module 0 is mapped to sensor_index 64). 7939 * Access: Index 7940 */ 7941 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 7); 7942 7943 /* Convert to milli degrees Celsius */ 7944 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) (val * 125) 7945 7946 /* reg_mtmp_temperature 7947 * Temperature reading from the sensor. Reading is in 0.125 Celsius 7948 * degrees units. 7949 * Access: RO 7950 */ 7951 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16); 7952 7953 /* reg_mtmp_mte 7954 * Max Temperature Enable - enables measuring the max temperature on a sensor. 7955 * Access: RW 7956 */ 7957 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1); 7958 7959 /* reg_mtmp_mtr 7960 * Max Temperature Reset - clears the value of the max temperature register. 7961 * Access: WO 7962 */ 7963 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1); 7964 7965 /* reg_mtmp_max_temperature 7966 * The highest measured temperature from the sensor. 7967 * When the bit mte is cleared, the field max_temperature is reserved. 7968 * Access: RO 7969 */ 7970 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16); 7971 7972 /* reg_mtmp_tee 7973 * Temperature Event Enable. 7974 * 0 - Do not generate event 7975 * 1 - Generate event 7976 * 2 - Generate single event 7977 * Access: RW 7978 */ 7979 MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2); 7980 7981 #define MLXSW_REG_MTMP_THRESH_HI 0x348 /* 105 Celsius */ 7982 7983 /* reg_mtmp_temperature_threshold_hi 7984 * High threshold for Temperature Warning Event. In 0.125 Celsius. 7985 * Access: RW 7986 */ 7987 MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16); 7988 7989 /* reg_mtmp_temperature_threshold_lo 7990 * Low threshold for Temperature Warning Event. In 0.125 Celsius. 7991 * Access: RW 7992 */ 7993 MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16); 7994 7995 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8 7996 7997 /* reg_mtmp_sensor_name 7998 * Sensor Name 7999 * Access: RO 8000 */ 8001 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE); 8002 8003 static inline void mlxsw_reg_mtmp_pack(char *payload, u8 sensor_index, 8004 bool max_temp_enable, 8005 bool max_temp_reset) 8006 { 8007 MLXSW_REG_ZERO(mtmp, payload); 8008 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index); 8009 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable); 8010 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset); 8011 mlxsw_reg_mtmp_temperature_threshold_hi_set(payload, 8012 MLXSW_REG_MTMP_THRESH_HI); 8013 } 8014 8015 static inline void mlxsw_reg_mtmp_unpack(char *payload, unsigned int *p_temp, 8016 unsigned int *p_max_temp, 8017 char *sensor_name) 8018 { 8019 u16 temp; 8020 8021 if (p_temp) { 8022 temp = mlxsw_reg_mtmp_temperature_get(payload); 8023 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 8024 } 8025 if (p_max_temp) { 8026 temp = mlxsw_reg_mtmp_max_temperature_get(payload); 8027 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 8028 } 8029 if (sensor_name) 8030 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name); 8031 } 8032 8033 /* MTBR - Management Temperature Bulk Register 8034 * ------------------------------------------- 8035 * This register is used for bulk temperature reading. 8036 */ 8037 #define MLXSW_REG_MTBR_ID 0x900F 8038 #define MLXSW_REG_MTBR_BASE_LEN 0x10 /* base length, without records */ 8039 #define MLXSW_REG_MTBR_REC_LEN 0x04 /* record length */ 8040 #define MLXSW_REG_MTBR_REC_MAX_COUNT 47 /* firmware limitation */ 8041 #define MLXSW_REG_MTBR_LEN (MLXSW_REG_MTBR_BASE_LEN + \ 8042 MLXSW_REG_MTBR_REC_LEN * \ 8043 MLXSW_REG_MTBR_REC_MAX_COUNT) 8044 8045 MLXSW_REG_DEFINE(mtbr, MLXSW_REG_MTBR_ID, MLXSW_REG_MTBR_LEN); 8046 8047 /* reg_mtbr_base_sensor_index 8048 * Base sensors index to access (0 - ASIC sensor, 1-63 - ambient sensors, 8049 * 64-127 are mapped to the SFP+/QSFP modules sequentially). 8050 * Access: Index 8051 */ 8052 MLXSW_ITEM32(reg, mtbr, base_sensor_index, 0x00, 0, 7); 8053 8054 /* reg_mtbr_num_rec 8055 * Request: Number of records to read 8056 * Response: Number of records read 8057 * See above description for more details. 8058 * Range 1..255 8059 * Access: RW 8060 */ 8061 MLXSW_ITEM32(reg, mtbr, num_rec, 0x04, 0, 8); 8062 8063 /* reg_mtbr_rec_max_temp 8064 * The highest measured temperature from the sensor. 8065 * When the bit mte is cleared, the field max_temperature is reserved. 8066 * Access: RO 8067 */ 8068 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_max_temp, MLXSW_REG_MTBR_BASE_LEN, 16, 8069 16, MLXSW_REG_MTBR_REC_LEN, 0x00, false); 8070 8071 /* reg_mtbr_rec_temp 8072 * Temperature reading from the sensor. Reading is in 0..125 Celsius 8073 * degrees units. 8074 * Access: RO 8075 */ 8076 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_temp, MLXSW_REG_MTBR_BASE_LEN, 0, 16, 8077 MLXSW_REG_MTBR_REC_LEN, 0x00, false); 8078 8079 static inline void mlxsw_reg_mtbr_pack(char *payload, u8 base_sensor_index, 8080 u8 num_rec) 8081 { 8082 MLXSW_REG_ZERO(mtbr, payload); 8083 mlxsw_reg_mtbr_base_sensor_index_set(payload, base_sensor_index); 8084 mlxsw_reg_mtbr_num_rec_set(payload, num_rec); 8085 } 8086 8087 /* Error codes from temperatute reading */ 8088 enum mlxsw_reg_mtbr_temp_status { 8089 MLXSW_REG_MTBR_NO_CONN = 0x8000, 8090 MLXSW_REG_MTBR_NO_TEMP_SENS = 0x8001, 8091 MLXSW_REG_MTBR_INDEX_NA = 0x8002, 8092 MLXSW_REG_MTBR_BAD_SENS_INFO = 0x8003, 8093 }; 8094 8095 /* Base index for reading modules temperature */ 8096 #define MLXSW_REG_MTBR_BASE_MODULE_INDEX 64 8097 8098 static inline void mlxsw_reg_mtbr_temp_unpack(char *payload, int rec_ind, 8099 u16 *p_temp, u16 *p_max_temp) 8100 { 8101 if (p_temp) 8102 *p_temp = mlxsw_reg_mtbr_rec_temp_get(payload, rec_ind); 8103 if (p_max_temp) 8104 *p_max_temp = mlxsw_reg_mtbr_rec_max_temp_get(payload, rec_ind); 8105 } 8106 8107 /* MCIA - Management Cable Info Access 8108 * ----------------------------------- 8109 * MCIA register is used to access the SFP+ and QSFP connector's EPROM. 8110 */ 8111 8112 #define MLXSW_REG_MCIA_ID 0x9014 8113 #define MLXSW_REG_MCIA_LEN 0x40 8114 8115 MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN); 8116 8117 /* reg_mcia_l 8118 * Lock bit. Setting this bit will lock the access to the specific 8119 * cable. Used for updating a full page in a cable EPROM. Any access 8120 * other then subsequence writes will fail while the port is locked. 8121 * Access: RW 8122 */ 8123 MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1); 8124 8125 /* reg_mcia_module 8126 * Module number. 8127 * Access: Index 8128 */ 8129 MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8); 8130 8131 /* reg_mcia_status 8132 * Module status. 8133 * Access: RO 8134 */ 8135 MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8); 8136 8137 /* reg_mcia_i2c_device_address 8138 * I2C device address. 8139 * Access: RW 8140 */ 8141 MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8); 8142 8143 /* reg_mcia_page_number 8144 * Page number. 8145 * Access: RW 8146 */ 8147 MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8); 8148 8149 /* reg_mcia_device_address 8150 * Device address. 8151 * Access: RW 8152 */ 8153 MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16); 8154 8155 /* reg_mcia_size 8156 * Number of bytes to read/write (up to 48 bytes). 8157 * Access: RW 8158 */ 8159 MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16); 8160 8161 #define MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH 256 8162 #define MLXSW_REG_MCIA_EEPROM_SIZE 48 8163 #define MLXSW_REG_MCIA_I2C_ADDR_LOW 0x50 8164 #define MLXSW_REG_MCIA_I2C_ADDR_HIGH 0x51 8165 #define MLXSW_REG_MCIA_PAGE0_LO_OFF 0xa0 8166 #define MLXSW_REG_MCIA_TH_ITEM_SIZE 2 8167 #define MLXSW_REG_MCIA_TH_PAGE_NUM 3 8168 #define MLXSW_REG_MCIA_PAGE0_LO 0 8169 #define MLXSW_REG_MCIA_TH_PAGE_OFF 0x80 8170 8171 enum mlxsw_reg_mcia_eeprom_module_info_rev_id { 8172 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00, 8173 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01, 8174 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03, 8175 }; 8176 8177 enum mlxsw_reg_mcia_eeprom_module_info_id { 8178 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_SFP = 0x03, 8179 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP = 0x0C, 8180 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D, 8181 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11, 8182 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_DD = 0x18, 8183 }; 8184 8185 enum mlxsw_reg_mcia_eeprom_module_info { 8186 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID, 8187 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID, 8188 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_SIZE, 8189 }; 8190 8191 /* reg_mcia_eeprom 8192 * Bytes to read/write. 8193 * Access: RW 8194 */ 8195 MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_REG_MCIA_EEPROM_SIZE); 8196 8197 static inline void mlxsw_reg_mcia_pack(char *payload, u8 module, u8 lock, 8198 u8 page_number, u16 device_addr, 8199 u8 size, u8 i2c_device_addr) 8200 { 8201 MLXSW_REG_ZERO(mcia, payload); 8202 mlxsw_reg_mcia_module_set(payload, module); 8203 mlxsw_reg_mcia_l_set(payload, lock); 8204 mlxsw_reg_mcia_page_number_set(payload, page_number); 8205 mlxsw_reg_mcia_device_address_set(payload, device_addr); 8206 mlxsw_reg_mcia_size_set(payload, size); 8207 mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr); 8208 } 8209 8210 /* MPAT - Monitoring Port Analyzer Table 8211 * ------------------------------------- 8212 * MPAT Register is used to query and configure the Switch PortAnalyzer Table. 8213 * For an enabled analyzer, all fields except e (enable) cannot be modified. 8214 */ 8215 #define MLXSW_REG_MPAT_ID 0x901A 8216 #define MLXSW_REG_MPAT_LEN 0x78 8217 8218 MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN); 8219 8220 /* reg_mpat_pa_id 8221 * Port Analyzer ID. 8222 * Access: Index 8223 */ 8224 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4); 8225 8226 /* reg_mpat_system_port 8227 * A unique port identifier for the final destination of the packet. 8228 * Access: RW 8229 */ 8230 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16); 8231 8232 /* reg_mpat_e 8233 * Enable. Indicating the Port Analyzer is enabled. 8234 * Access: RW 8235 */ 8236 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1); 8237 8238 /* reg_mpat_qos 8239 * Quality Of Service Mode. 8240 * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation 8241 * PCP, DEI, DSCP or VL) are configured. 8242 * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the 8243 * same as in the original packet that has triggered the mirroring. For 8244 * SPAN also the pcp,dei are maintained. 8245 * Access: RW 8246 */ 8247 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1); 8248 8249 /* reg_mpat_be 8250 * Best effort mode. Indicates mirroring traffic should not cause packet 8251 * drop or back pressure, but will discard the mirrored packets. Mirrored 8252 * packets will be forwarded on a best effort manner. 8253 * 0: Do not discard mirrored packets 8254 * 1: Discard mirrored packets if causing congestion 8255 * Access: RW 8256 */ 8257 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1); 8258 8259 enum mlxsw_reg_mpat_span_type { 8260 /* Local SPAN Ethernet. 8261 * The original packet is not encapsulated. 8262 */ 8263 MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0, 8264 8265 /* Remote SPAN Ethernet VLAN. 8266 * The packet is forwarded to the monitoring port on the monitoring 8267 * VLAN. 8268 */ 8269 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1, 8270 8271 /* Encapsulated Remote SPAN Ethernet L3 GRE. 8272 * The packet is encapsulated with GRE header. 8273 */ 8274 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3, 8275 }; 8276 8277 /* reg_mpat_span_type 8278 * SPAN type. 8279 * Access: RW 8280 */ 8281 MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4); 8282 8283 /* Remote SPAN - Ethernet VLAN 8284 * - - - - - - - - - - - - - - 8285 */ 8286 8287 /* reg_mpat_eth_rspan_vid 8288 * Encapsulation header VLAN ID. 8289 * Access: RW 8290 */ 8291 MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12); 8292 8293 /* Encapsulated Remote SPAN - Ethernet L2 8294 * - - - - - - - - - - - - - - - - - - - 8295 */ 8296 8297 enum mlxsw_reg_mpat_eth_rspan_version { 8298 MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15, 8299 }; 8300 8301 /* reg_mpat_eth_rspan_version 8302 * RSPAN mirror header version. 8303 * Access: RW 8304 */ 8305 MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4); 8306 8307 /* reg_mpat_eth_rspan_mac 8308 * Destination MAC address. 8309 * Access: RW 8310 */ 8311 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6); 8312 8313 /* reg_mpat_eth_rspan_tp 8314 * Tag Packet. Indicates whether the mirroring header should be VLAN tagged. 8315 * Access: RW 8316 */ 8317 MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1); 8318 8319 /* Encapsulated Remote SPAN - Ethernet L3 8320 * - - - - - - - - - - - - - - - - - - - 8321 */ 8322 8323 enum mlxsw_reg_mpat_eth_rspan_protocol { 8324 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4, 8325 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6, 8326 }; 8327 8328 /* reg_mpat_eth_rspan_protocol 8329 * SPAN encapsulation protocol. 8330 * Access: RW 8331 */ 8332 MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4); 8333 8334 /* reg_mpat_eth_rspan_ttl 8335 * Encapsulation header Time-to-Live/HopLimit. 8336 * Access: RW 8337 */ 8338 MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8); 8339 8340 /* reg_mpat_eth_rspan_smac 8341 * Source MAC address 8342 * Access: RW 8343 */ 8344 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6); 8345 8346 /* reg_mpat_eth_rspan_dip* 8347 * Destination IP address. The IP version is configured by protocol. 8348 * Access: RW 8349 */ 8350 MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32); 8351 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16); 8352 8353 /* reg_mpat_eth_rspan_sip* 8354 * Source IP address. The IP version is configured by protocol. 8355 * Access: RW 8356 */ 8357 MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32); 8358 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16); 8359 8360 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id, 8361 u16 system_port, bool e, 8362 enum mlxsw_reg_mpat_span_type span_type) 8363 { 8364 MLXSW_REG_ZERO(mpat, payload); 8365 mlxsw_reg_mpat_pa_id_set(payload, pa_id); 8366 mlxsw_reg_mpat_system_port_set(payload, system_port); 8367 mlxsw_reg_mpat_e_set(payload, e); 8368 mlxsw_reg_mpat_qos_set(payload, 1); 8369 mlxsw_reg_mpat_be_set(payload, 1); 8370 mlxsw_reg_mpat_span_type_set(payload, span_type); 8371 } 8372 8373 static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid) 8374 { 8375 mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid); 8376 } 8377 8378 static inline void 8379 mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload, 8380 enum mlxsw_reg_mpat_eth_rspan_version version, 8381 const char *mac, 8382 bool tp) 8383 { 8384 mlxsw_reg_mpat_eth_rspan_version_set(payload, version); 8385 mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac); 8386 mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp); 8387 } 8388 8389 static inline void 8390 mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl, 8391 const char *smac, 8392 u32 sip, u32 dip) 8393 { 8394 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 8395 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 8396 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 8397 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4); 8398 mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip); 8399 mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip); 8400 } 8401 8402 static inline void 8403 mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl, 8404 const char *smac, 8405 struct in6_addr sip, struct in6_addr dip) 8406 { 8407 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 8408 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 8409 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 8410 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6); 8411 mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip); 8412 mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip); 8413 } 8414 8415 /* MPAR - Monitoring Port Analyzer Register 8416 * ---------------------------------------- 8417 * MPAR register is used to query and configure the port analyzer port mirroring 8418 * properties. 8419 */ 8420 #define MLXSW_REG_MPAR_ID 0x901B 8421 #define MLXSW_REG_MPAR_LEN 0x08 8422 8423 MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN); 8424 8425 /* reg_mpar_local_port 8426 * The local port to mirror the packets from. 8427 * Access: Index 8428 */ 8429 MLXSW_ITEM32(reg, mpar, local_port, 0x00, 16, 8); 8430 8431 enum mlxsw_reg_mpar_i_e { 8432 MLXSW_REG_MPAR_TYPE_EGRESS, 8433 MLXSW_REG_MPAR_TYPE_INGRESS, 8434 }; 8435 8436 /* reg_mpar_i_e 8437 * Ingress/Egress 8438 * Access: Index 8439 */ 8440 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4); 8441 8442 /* reg_mpar_enable 8443 * Enable mirroring 8444 * By default, port mirroring is disabled for all ports. 8445 * Access: RW 8446 */ 8447 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1); 8448 8449 /* reg_mpar_pa_id 8450 * Port Analyzer ID. 8451 * Access: RW 8452 */ 8453 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4); 8454 8455 static inline void mlxsw_reg_mpar_pack(char *payload, u8 local_port, 8456 enum mlxsw_reg_mpar_i_e i_e, 8457 bool enable, u8 pa_id) 8458 { 8459 MLXSW_REG_ZERO(mpar, payload); 8460 mlxsw_reg_mpar_local_port_set(payload, local_port); 8461 mlxsw_reg_mpar_enable_set(payload, enable); 8462 mlxsw_reg_mpar_i_e_set(payload, i_e); 8463 mlxsw_reg_mpar_pa_id_set(payload, pa_id); 8464 } 8465 8466 /* MRSR - Management Reset and Shutdown Register 8467 * --------------------------------------------- 8468 * MRSR register is used to reset or shutdown the switch or 8469 * the entire system (when applicable). 8470 */ 8471 #define MLXSW_REG_MRSR_ID 0x9023 8472 #define MLXSW_REG_MRSR_LEN 0x08 8473 8474 MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN); 8475 8476 /* reg_mrsr_command 8477 * Reset/shutdown command 8478 * 0 - do nothing 8479 * 1 - software reset 8480 * Access: WO 8481 */ 8482 MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4); 8483 8484 static inline void mlxsw_reg_mrsr_pack(char *payload) 8485 { 8486 MLXSW_REG_ZERO(mrsr, payload); 8487 mlxsw_reg_mrsr_command_set(payload, 1); 8488 } 8489 8490 /* MLCR - Management LED Control Register 8491 * -------------------------------------- 8492 * Controls the system LEDs. 8493 */ 8494 #define MLXSW_REG_MLCR_ID 0x902B 8495 #define MLXSW_REG_MLCR_LEN 0x0C 8496 8497 MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN); 8498 8499 /* reg_mlcr_local_port 8500 * Local port number. 8501 * Access: RW 8502 */ 8503 MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8); 8504 8505 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF 8506 8507 /* reg_mlcr_beacon_duration 8508 * Duration of the beacon to be active, in seconds. 8509 * 0x0 - Will turn off the beacon. 8510 * 0xFFFF - Will turn on the beacon until explicitly turned off. 8511 * Access: RW 8512 */ 8513 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16); 8514 8515 /* reg_mlcr_beacon_remain 8516 * Remaining duration of the beacon, in seconds. 8517 * 0xFFFF indicates an infinite amount of time. 8518 * Access: RO 8519 */ 8520 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16); 8521 8522 static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port, 8523 bool active) 8524 { 8525 MLXSW_REG_ZERO(mlcr, payload); 8526 mlxsw_reg_mlcr_local_port_set(payload, local_port); 8527 mlxsw_reg_mlcr_beacon_duration_set(payload, active ? 8528 MLXSW_REG_MLCR_DURATION_MAX : 0); 8529 } 8530 8531 /* MCQI - Management Component Query Information 8532 * --------------------------------------------- 8533 * This register allows querying information about firmware components. 8534 */ 8535 #define MLXSW_REG_MCQI_ID 0x9061 8536 #define MLXSW_REG_MCQI_BASE_LEN 0x18 8537 #define MLXSW_REG_MCQI_CAP_LEN 0x14 8538 #define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN) 8539 8540 MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN); 8541 8542 /* reg_mcqi_component_index 8543 * Index of the accessed component. 8544 * Access: Index 8545 */ 8546 MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16); 8547 8548 enum mlxfw_reg_mcqi_info_type { 8549 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES, 8550 }; 8551 8552 /* reg_mcqi_info_type 8553 * Component properties set. 8554 * Access: RW 8555 */ 8556 MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5); 8557 8558 /* reg_mcqi_offset 8559 * The requested/returned data offset from the section start, given in bytes. 8560 * Must be DWORD aligned. 8561 * Access: RW 8562 */ 8563 MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32); 8564 8565 /* reg_mcqi_data_size 8566 * The requested/returned data size, given in bytes. If data_size is not DWORD 8567 * aligned, the last bytes are zero padded. 8568 * Access: RW 8569 */ 8570 MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16); 8571 8572 /* reg_mcqi_cap_max_component_size 8573 * Maximum size for this component, given in bytes. 8574 * Access: RO 8575 */ 8576 MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32); 8577 8578 /* reg_mcqi_cap_log_mcda_word_size 8579 * Log 2 of the access word size in bytes. Read and write access must be aligned 8580 * to the word size. Write access must be done for an integer number of words. 8581 * Access: RO 8582 */ 8583 MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4); 8584 8585 /* reg_mcqi_cap_mcda_max_write_size 8586 * Maximal write size for MCDA register 8587 * Access: RO 8588 */ 8589 MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16); 8590 8591 static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index) 8592 { 8593 MLXSW_REG_ZERO(mcqi, payload); 8594 mlxsw_reg_mcqi_component_index_set(payload, component_index); 8595 mlxsw_reg_mcqi_info_type_set(payload, 8596 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES); 8597 mlxsw_reg_mcqi_offset_set(payload, 0); 8598 mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN); 8599 } 8600 8601 static inline void mlxsw_reg_mcqi_unpack(char *payload, 8602 u32 *p_cap_max_component_size, 8603 u8 *p_cap_log_mcda_word_size, 8604 u16 *p_cap_mcda_max_write_size) 8605 { 8606 *p_cap_max_component_size = 8607 mlxsw_reg_mcqi_cap_max_component_size_get(payload); 8608 *p_cap_log_mcda_word_size = 8609 mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload); 8610 *p_cap_mcda_max_write_size = 8611 mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload); 8612 } 8613 8614 /* MCC - Management Component Control 8615 * ---------------------------------- 8616 * Controls the firmware component and updates the FSM. 8617 */ 8618 #define MLXSW_REG_MCC_ID 0x9062 8619 #define MLXSW_REG_MCC_LEN 0x1C 8620 8621 MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN); 8622 8623 enum mlxsw_reg_mcc_instruction { 8624 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01, 8625 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02, 8626 MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03, 8627 MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04, 8628 MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06, 8629 MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08, 8630 }; 8631 8632 /* reg_mcc_instruction 8633 * Command to be executed by the FSM. 8634 * Applicable for write operation only. 8635 * Access: RW 8636 */ 8637 MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8); 8638 8639 /* reg_mcc_component_index 8640 * Index of the accessed component. Applicable only for commands that 8641 * refer to components. Otherwise, this field is reserved. 8642 * Access: Index 8643 */ 8644 MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16); 8645 8646 /* reg_mcc_update_handle 8647 * Token representing the current flow executed by the FSM. 8648 * Access: WO 8649 */ 8650 MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24); 8651 8652 /* reg_mcc_error_code 8653 * Indicates the successful completion of the instruction, or the reason it 8654 * failed 8655 * Access: RO 8656 */ 8657 MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8); 8658 8659 /* reg_mcc_control_state 8660 * Current FSM state 8661 * Access: RO 8662 */ 8663 MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4); 8664 8665 /* reg_mcc_component_size 8666 * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying 8667 * the size may shorten the update time. Value 0x0 means that size is 8668 * unspecified. 8669 * Access: WO 8670 */ 8671 MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32); 8672 8673 static inline void mlxsw_reg_mcc_pack(char *payload, 8674 enum mlxsw_reg_mcc_instruction instr, 8675 u16 component_index, u32 update_handle, 8676 u32 component_size) 8677 { 8678 MLXSW_REG_ZERO(mcc, payload); 8679 mlxsw_reg_mcc_instruction_set(payload, instr); 8680 mlxsw_reg_mcc_component_index_set(payload, component_index); 8681 mlxsw_reg_mcc_update_handle_set(payload, update_handle); 8682 mlxsw_reg_mcc_component_size_set(payload, component_size); 8683 } 8684 8685 static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle, 8686 u8 *p_error_code, u8 *p_control_state) 8687 { 8688 if (p_update_handle) 8689 *p_update_handle = mlxsw_reg_mcc_update_handle_get(payload); 8690 if (p_error_code) 8691 *p_error_code = mlxsw_reg_mcc_error_code_get(payload); 8692 if (p_control_state) 8693 *p_control_state = mlxsw_reg_mcc_control_state_get(payload); 8694 } 8695 8696 /* MCDA - Management Component Data Access 8697 * --------------------------------------- 8698 * This register allows reading and writing a firmware component. 8699 */ 8700 #define MLXSW_REG_MCDA_ID 0x9063 8701 #define MLXSW_REG_MCDA_BASE_LEN 0x10 8702 #define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80 8703 #define MLXSW_REG_MCDA_LEN \ 8704 (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN) 8705 8706 MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN); 8707 8708 /* reg_mcda_update_handle 8709 * Token representing the current flow executed by the FSM. 8710 * Access: RW 8711 */ 8712 MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24); 8713 8714 /* reg_mcda_offset 8715 * Offset of accessed address relative to component start. Accesses must be in 8716 * accordance to log_mcda_word_size in MCQI reg. 8717 * Access: RW 8718 */ 8719 MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32); 8720 8721 /* reg_mcda_size 8722 * Size of the data accessed, given in bytes. 8723 * Access: RW 8724 */ 8725 MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16); 8726 8727 /* reg_mcda_data 8728 * Data block accessed. 8729 * Access: RW 8730 */ 8731 MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false); 8732 8733 static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle, 8734 u32 offset, u16 size, u8 *data) 8735 { 8736 int i; 8737 8738 MLXSW_REG_ZERO(mcda, payload); 8739 mlxsw_reg_mcda_update_handle_set(payload, update_handle); 8740 mlxsw_reg_mcda_offset_set(payload, offset); 8741 mlxsw_reg_mcda_size_set(payload, size); 8742 8743 for (i = 0; i < size / 4; i++) 8744 mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]); 8745 } 8746 8747 /* MPSC - Monitoring Packet Sampling Configuration Register 8748 * -------------------------------------------------------- 8749 * MPSC Register is used to configure the Packet Sampling mechanism. 8750 */ 8751 #define MLXSW_REG_MPSC_ID 0x9080 8752 #define MLXSW_REG_MPSC_LEN 0x1C 8753 8754 MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN); 8755 8756 /* reg_mpsc_local_port 8757 * Local port number 8758 * Not supported for CPU port 8759 * Access: Index 8760 */ 8761 MLXSW_ITEM32(reg, mpsc, local_port, 0x00, 16, 8); 8762 8763 /* reg_mpsc_e 8764 * Enable sampling on port local_port 8765 * Access: RW 8766 */ 8767 MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1); 8768 8769 #define MLXSW_REG_MPSC_RATE_MAX 3500000000UL 8770 8771 /* reg_mpsc_rate 8772 * Sampling rate = 1 out of rate packets (with randomization around 8773 * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX 8774 * Access: RW 8775 */ 8776 MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32); 8777 8778 static inline void mlxsw_reg_mpsc_pack(char *payload, u8 local_port, bool e, 8779 u32 rate) 8780 { 8781 MLXSW_REG_ZERO(mpsc, payload); 8782 mlxsw_reg_mpsc_local_port_set(payload, local_port); 8783 mlxsw_reg_mpsc_e_set(payload, e); 8784 mlxsw_reg_mpsc_rate_set(payload, rate); 8785 } 8786 8787 /* MGPC - Monitoring General Purpose Counter Set Register 8788 * The MGPC register retrieves and sets the General Purpose Counter Set. 8789 */ 8790 #define MLXSW_REG_MGPC_ID 0x9081 8791 #define MLXSW_REG_MGPC_LEN 0x18 8792 8793 MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN); 8794 8795 /* reg_mgpc_counter_set_type 8796 * Counter set type. 8797 * Access: OP 8798 */ 8799 MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8); 8800 8801 /* reg_mgpc_counter_index 8802 * Counter index. 8803 * Access: Index 8804 */ 8805 MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24); 8806 8807 enum mlxsw_reg_mgpc_opcode { 8808 /* Nop */ 8809 MLXSW_REG_MGPC_OPCODE_NOP = 0x00, 8810 /* Clear counters */ 8811 MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08, 8812 }; 8813 8814 /* reg_mgpc_opcode 8815 * Opcode. 8816 * Access: OP 8817 */ 8818 MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4); 8819 8820 /* reg_mgpc_byte_counter 8821 * Byte counter value. 8822 * Access: RW 8823 */ 8824 MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64); 8825 8826 /* reg_mgpc_packet_counter 8827 * Packet counter value. 8828 * Access: RW 8829 */ 8830 MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64); 8831 8832 static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index, 8833 enum mlxsw_reg_mgpc_opcode opcode, 8834 enum mlxsw_reg_flow_counter_set_type set_type) 8835 { 8836 MLXSW_REG_ZERO(mgpc, payload); 8837 mlxsw_reg_mgpc_counter_index_set(payload, counter_index); 8838 mlxsw_reg_mgpc_counter_set_type_set(payload, set_type); 8839 mlxsw_reg_mgpc_opcode_set(payload, opcode); 8840 } 8841 8842 /* MPRS - Monitoring Parsing State Register 8843 * ---------------------------------------- 8844 * The MPRS register is used for setting up the parsing for hash, 8845 * policy-engine and routing. 8846 */ 8847 #define MLXSW_REG_MPRS_ID 0x9083 8848 #define MLXSW_REG_MPRS_LEN 0x14 8849 8850 MLXSW_REG_DEFINE(mprs, MLXSW_REG_MPRS_ID, MLXSW_REG_MPRS_LEN); 8851 8852 /* reg_mprs_parsing_depth 8853 * Minimum parsing depth. 8854 * Need to enlarge parsing depth according to L3, MPLS, tunnels, ACL 8855 * rules, traps, hash, etc. Default is 96 bytes. Reserved when SwitchX-2. 8856 * Access: RW 8857 */ 8858 MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16); 8859 8860 /* reg_mprs_parsing_en 8861 * Parsing enable. 8862 * Bit 0 - Enable parsing of NVE of types VxLAN, VxLAN-GPE, GENEVE and 8863 * NVGRE. Default is enabled. Reserved when SwitchX-2. 8864 * Access: RW 8865 */ 8866 MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16); 8867 8868 /* reg_mprs_vxlan_udp_dport 8869 * VxLAN UDP destination port. 8870 * Used for identifying VxLAN packets and for dport field in 8871 * encapsulation. Default is 4789. 8872 * Access: RW 8873 */ 8874 MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16); 8875 8876 static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth, 8877 u16 vxlan_udp_dport) 8878 { 8879 MLXSW_REG_ZERO(mprs, payload); 8880 mlxsw_reg_mprs_parsing_depth_set(payload, parsing_depth); 8881 mlxsw_reg_mprs_parsing_en_set(payload, true); 8882 mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport); 8883 } 8884 8885 /* TNGCR - Tunneling NVE General Configuration Register 8886 * ---------------------------------------------------- 8887 * The TNGCR register is used for setting up the NVE Tunneling configuration. 8888 */ 8889 #define MLXSW_REG_TNGCR_ID 0xA001 8890 #define MLXSW_REG_TNGCR_LEN 0x44 8891 8892 MLXSW_REG_DEFINE(tngcr, MLXSW_REG_TNGCR_ID, MLXSW_REG_TNGCR_LEN); 8893 8894 enum mlxsw_reg_tngcr_type { 8895 MLXSW_REG_TNGCR_TYPE_VXLAN, 8896 MLXSW_REG_TNGCR_TYPE_VXLAN_GPE, 8897 MLXSW_REG_TNGCR_TYPE_GENEVE, 8898 MLXSW_REG_TNGCR_TYPE_NVGRE, 8899 }; 8900 8901 /* reg_tngcr_type 8902 * Tunnel type for encapsulation and decapsulation. The types are mutually 8903 * exclusive. 8904 * Note: For Spectrum the NVE parsing must be enabled in MPRS. 8905 * Access: RW 8906 */ 8907 MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4); 8908 8909 /* reg_tngcr_nve_valid 8910 * The VTEP is valid. Allows adding FDB entries for tunnel encapsulation. 8911 * Access: RW 8912 */ 8913 MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1); 8914 8915 /* reg_tngcr_nve_ttl_uc 8916 * The TTL for NVE tunnel encapsulation underlay unicast packets. 8917 * Access: RW 8918 */ 8919 MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8); 8920 8921 /* reg_tngcr_nve_ttl_mc 8922 * The TTL for NVE tunnel encapsulation underlay multicast packets. 8923 * Access: RW 8924 */ 8925 MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8); 8926 8927 enum { 8928 /* Do not copy flow label. Calculate flow label using nve_flh. */ 8929 MLXSW_REG_TNGCR_FL_NO_COPY, 8930 /* Copy flow label from inner packet if packet is IPv6 and 8931 * encapsulation is by IPv6. Otherwise, calculate flow label using 8932 * nve_flh. 8933 */ 8934 MLXSW_REG_TNGCR_FL_COPY, 8935 }; 8936 8937 /* reg_tngcr_nve_flc 8938 * For NVE tunnel encapsulation: Flow label copy from inner packet. 8939 * Access: RW 8940 */ 8941 MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1); 8942 8943 enum { 8944 /* Flow label is static. In Spectrum this means '0'. Spectrum-2 8945 * uses {nve_fl_prefix, nve_fl_suffix}. 8946 */ 8947 MLXSW_REG_TNGCR_FL_NO_HASH, 8948 /* 8 LSBs of the flow label are calculated from ECMP hash of the 8949 * inner packet. 12 MSBs are configured by nve_fl_prefix. 8950 */ 8951 MLXSW_REG_TNGCR_FL_HASH, 8952 }; 8953 8954 /* reg_tngcr_nve_flh 8955 * NVE flow label hash. 8956 * Access: RW 8957 */ 8958 MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1); 8959 8960 /* reg_tngcr_nve_fl_prefix 8961 * NVE flow label prefix. Constant 12 MSBs of the flow label. 8962 * Access: RW 8963 */ 8964 MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12); 8965 8966 /* reg_tngcr_nve_fl_suffix 8967 * NVE flow label suffix. Constant 8 LSBs of the flow label. 8968 * Reserved when nve_flh=1 and for Spectrum. 8969 * Access: RW 8970 */ 8971 MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8); 8972 8973 enum { 8974 /* Source UDP port is fixed (default '0') */ 8975 MLXSW_REG_TNGCR_UDP_SPORT_NO_HASH, 8976 /* Source UDP port is calculated based on hash */ 8977 MLXSW_REG_TNGCR_UDP_SPORT_HASH, 8978 }; 8979 8980 /* reg_tngcr_nve_udp_sport_type 8981 * NVE UDP source port type. 8982 * Spectrum uses LAG hash (SLCRv2). Spectrum-2 uses ECMP hash (RECRv2). 8983 * When the source UDP port is calculated based on hash, then the 8 LSBs 8984 * are calculated from hash the 8 MSBs are configured by 8985 * nve_udp_sport_prefix. 8986 * Access: RW 8987 */ 8988 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1); 8989 8990 /* reg_tngcr_nve_udp_sport_prefix 8991 * NVE UDP source port prefix. Constant 8 MSBs of the UDP source port. 8992 * Reserved when NVE type is NVGRE. 8993 * Access: RW 8994 */ 8995 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8); 8996 8997 /* reg_tngcr_nve_group_size_mc 8998 * The amount of sequential linked lists of MC entries. The first linked 8999 * list is configured by SFD.underlay_mc_ptr. 9000 * Valid values: 1, 2, 4, 8, 16, 32, 64 9001 * The linked list are configured by TNUMT. 9002 * The hash is set by LAG hash. 9003 * Access: RW 9004 */ 9005 MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8); 9006 9007 /* reg_tngcr_nve_group_size_flood 9008 * The amount of sequential linked lists of flooding entries. The first 9009 * linked list is configured by SFMR.nve_tunnel_flood_ptr 9010 * Valid values: 1, 2, 4, 8, 16, 32, 64 9011 * The linked list are configured by TNUMT. 9012 * The hash is set by LAG hash. 9013 * Access: RW 9014 */ 9015 MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8); 9016 9017 /* reg_tngcr_learn_enable 9018 * During decapsulation, whether to learn from NVE port. 9019 * Reserved when Spectrum-2. See TNPC. 9020 * Access: RW 9021 */ 9022 MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1); 9023 9024 /* reg_tngcr_underlay_virtual_router 9025 * Underlay virtual router. 9026 * Reserved when Spectrum-2. 9027 * Access: RW 9028 */ 9029 MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16); 9030 9031 /* reg_tngcr_underlay_rif 9032 * Underlay ingress router interface. RIF type should be loopback generic. 9033 * Reserved when Spectrum. 9034 * Access: RW 9035 */ 9036 MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16); 9037 9038 /* reg_tngcr_usipv4 9039 * Underlay source IPv4 address of the NVE. 9040 * Access: RW 9041 */ 9042 MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32); 9043 9044 /* reg_tngcr_usipv6 9045 * Underlay source IPv6 address of the NVE. For Spectrum, must not be 9046 * modified under traffic of NVE tunneling encapsulation. 9047 * Access: RW 9048 */ 9049 MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16); 9050 9051 static inline void mlxsw_reg_tngcr_pack(char *payload, 9052 enum mlxsw_reg_tngcr_type type, 9053 bool valid, u8 ttl) 9054 { 9055 MLXSW_REG_ZERO(tngcr, payload); 9056 mlxsw_reg_tngcr_type_set(payload, type); 9057 mlxsw_reg_tngcr_nve_valid_set(payload, valid); 9058 mlxsw_reg_tngcr_nve_ttl_uc_set(payload, ttl); 9059 mlxsw_reg_tngcr_nve_ttl_mc_set(payload, ttl); 9060 mlxsw_reg_tngcr_nve_flc_set(payload, MLXSW_REG_TNGCR_FL_NO_COPY); 9061 mlxsw_reg_tngcr_nve_flh_set(payload, 0); 9062 mlxsw_reg_tngcr_nve_udp_sport_type_set(payload, 9063 MLXSW_REG_TNGCR_UDP_SPORT_HASH); 9064 mlxsw_reg_tngcr_nve_udp_sport_prefix_set(payload, 0); 9065 mlxsw_reg_tngcr_nve_group_size_mc_set(payload, 1); 9066 mlxsw_reg_tngcr_nve_group_size_flood_set(payload, 1); 9067 } 9068 9069 /* TNUMT - Tunneling NVE Underlay Multicast Table Register 9070 * ------------------------------------------------------- 9071 * The TNUMT register is for building the underlay MC table. It is used 9072 * for MC, flooding and BC traffic into the NVE tunnel. 9073 */ 9074 #define MLXSW_REG_TNUMT_ID 0xA003 9075 #define MLXSW_REG_TNUMT_LEN 0x20 9076 9077 MLXSW_REG_DEFINE(tnumt, MLXSW_REG_TNUMT_ID, MLXSW_REG_TNUMT_LEN); 9078 9079 enum mlxsw_reg_tnumt_record_type { 9080 MLXSW_REG_TNUMT_RECORD_TYPE_IPV4, 9081 MLXSW_REG_TNUMT_RECORD_TYPE_IPV6, 9082 MLXSW_REG_TNUMT_RECORD_TYPE_LABEL, 9083 }; 9084 9085 /* reg_tnumt_record_type 9086 * Record type. 9087 * Access: RW 9088 */ 9089 MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4); 9090 9091 enum mlxsw_reg_tnumt_tunnel_port { 9092 MLXSW_REG_TNUMT_TUNNEL_PORT_NVE, 9093 MLXSW_REG_TNUMT_TUNNEL_PORT_VPLS, 9094 MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL0, 9095 MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL1, 9096 }; 9097 9098 /* reg_tnumt_tunnel_port 9099 * Tunnel port. 9100 * Access: RW 9101 */ 9102 MLXSW_ITEM32(reg, tnumt, tunnel_port, 0x00, 24, 4); 9103 9104 /* reg_tnumt_underlay_mc_ptr 9105 * Index to the underlay multicast table. 9106 * For Spectrum the index is to the KVD linear. 9107 * Access: Index 9108 */ 9109 MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24); 9110 9111 /* reg_tnumt_vnext 9112 * The next_underlay_mc_ptr is valid. 9113 * Access: RW 9114 */ 9115 MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1); 9116 9117 /* reg_tnumt_next_underlay_mc_ptr 9118 * The next index to the underlay multicast table. 9119 * Access: RW 9120 */ 9121 MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24); 9122 9123 /* reg_tnumt_record_size 9124 * Number of IP addresses in the record. 9125 * Range is 1..cap_max_nve_mc_entries_ipv{4,6} 9126 * Access: RW 9127 */ 9128 MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3); 9129 9130 /* reg_tnumt_udip 9131 * The underlay IPv4 addresses. udip[i] is reserved if i >= size 9132 * Access: RW 9133 */ 9134 MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false); 9135 9136 /* reg_tnumt_udip_ptr 9137 * The pointer to the underlay IPv6 addresses. udip_ptr[i] is reserved if 9138 * i >= size. The IPv6 addresses are configured by RIPS. 9139 * Access: RW 9140 */ 9141 MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false); 9142 9143 static inline void mlxsw_reg_tnumt_pack(char *payload, 9144 enum mlxsw_reg_tnumt_record_type type, 9145 enum mlxsw_reg_tnumt_tunnel_port tport, 9146 u32 underlay_mc_ptr, bool vnext, 9147 u32 next_underlay_mc_ptr, 9148 u8 record_size) 9149 { 9150 MLXSW_REG_ZERO(tnumt, payload); 9151 mlxsw_reg_tnumt_record_type_set(payload, type); 9152 mlxsw_reg_tnumt_tunnel_port_set(payload, tport); 9153 mlxsw_reg_tnumt_underlay_mc_ptr_set(payload, underlay_mc_ptr); 9154 mlxsw_reg_tnumt_vnext_set(payload, vnext); 9155 mlxsw_reg_tnumt_next_underlay_mc_ptr_set(payload, next_underlay_mc_ptr); 9156 mlxsw_reg_tnumt_record_size_set(payload, record_size); 9157 } 9158 9159 /* TNQCR - Tunneling NVE QoS Configuration Register 9160 * ------------------------------------------------ 9161 * The TNQCR register configures how QoS is set in encapsulation into the 9162 * underlay network. 9163 */ 9164 #define MLXSW_REG_TNQCR_ID 0xA010 9165 #define MLXSW_REG_TNQCR_LEN 0x0C 9166 9167 MLXSW_REG_DEFINE(tnqcr, MLXSW_REG_TNQCR_ID, MLXSW_REG_TNQCR_LEN); 9168 9169 /* reg_tnqcr_enc_set_dscp 9170 * For encapsulation: How to set DSCP field: 9171 * 0 - Copy the DSCP from the overlay (inner) IP header to the underlay 9172 * (outer) IP header. If there is no IP header, use TNQDR.dscp 9173 * 1 - Set the DSCP field as TNQDR.dscp 9174 * Access: RW 9175 */ 9176 MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1); 9177 9178 static inline void mlxsw_reg_tnqcr_pack(char *payload) 9179 { 9180 MLXSW_REG_ZERO(tnqcr, payload); 9181 mlxsw_reg_tnqcr_enc_set_dscp_set(payload, 0); 9182 } 9183 9184 /* TNQDR - Tunneling NVE QoS Default Register 9185 * ------------------------------------------ 9186 * The TNQDR register configures the default QoS settings for NVE 9187 * encapsulation. 9188 */ 9189 #define MLXSW_REG_TNQDR_ID 0xA011 9190 #define MLXSW_REG_TNQDR_LEN 0x08 9191 9192 MLXSW_REG_DEFINE(tnqdr, MLXSW_REG_TNQDR_ID, MLXSW_REG_TNQDR_LEN); 9193 9194 /* reg_tnqdr_local_port 9195 * Local port number (receive port). CPU port is supported. 9196 * Access: Index 9197 */ 9198 MLXSW_ITEM32(reg, tnqdr, local_port, 0x00, 16, 8); 9199 9200 /* reg_tnqdr_dscp 9201 * For encapsulation, the default DSCP. 9202 * Access: RW 9203 */ 9204 MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6); 9205 9206 static inline void mlxsw_reg_tnqdr_pack(char *payload, u8 local_port) 9207 { 9208 MLXSW_REG_ZERO(tnqdr, payload); 9209 mlxsw_reg_tnqdr_local_port_set(payload, local_port); 9210 mlxsw_reg_tnqdr_dscp_set(payload, 0); 9211 } 9212 9213 /* TNEEM - Tunneling NVE Encapsulation ECN Mapping Register 9214 * -------------------------------------------------------- 9215 * The TNEEM register maps ECN of the IP header at the ingress to the 9216 * encapsulation to the ECN of the underlay network. 9217 */ 9218 #define MLXSW_REG_TNEEM_ID 0xA012 9219 #define MLXSW_REG_TNEEM_LEN 0x0C 9220 9221 MLXSW_REG_DEFINE(tneem, MLXSW_REG_TNEEM_ID, MLXSW_REG_TNEEM_LEN); 9222 9223 /* reg_tneem_overlay_ecn 9224 * ECN of the IP header in the overlay network. 9225 * Access: Index 9226 */ 9227 MLXSW_ITEM32(reg, tneem, overlay_ecn, 0x04, 24, 2); 9228 9229 /* reg_tneem_underlay_ecn 9230 * ECN of the IP header in the underlay network. 9231 * Access: RW 9232 */ 9233 MLXSW_ITEM32(reg, tneem, underlay_ecn, 0x04, 16, 2); 9234 9235 static inline void mlxsw_reg_tneem_pack(char *payload, u8 overlay_ecn, 9236 u8 underlay_ecn) 9237 { 9238 MLXSW_REG_ZERO(tneem, payload); 9239 mlxsw_reg_tneem_overlay_ecn_set(payload, overlay_ecn); 9240 mlxsw_reg_tneem_underlay_ecn_set(payload, underlay_ecn); 9241 } 9242 9243 /* TNDEM - Tunneling NVE Decapsulation ECN Mapping Register 9244 * -------------------------------------------------------- 9245 * The TNDEM register configures the actions that are done in the 9246 * decapsulation. 9247 */ 9248 #define MLXSW_REG_TNDEM_ID 0xA013 9249 #define MLXSW_REG_TNDEM_LEN 0x0C 9250 9251 MLXSW_REG_DEFINE(tndem, MLXSW_REG_TNDEM_ID, MLXSW_REG_TNDEM_LEN); 9252 9253 /* reg_tndem_underlay_ecn 9254 * ECN field of the IP header in the underlay network. 9255 * Access: Index 9256 */ 9257 MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2); 9258 9259 /* reg_tndem_overlay_ecn 9260 * ECN field of the IP header in the overlay network. 9261 * Access: Index 9262 */ 9263 MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2); 9264 9265 /* reg_tndem_eip_ecn 9266 * Egress IP ECN. ECN field of the IP header of the packet which goes out 9267 * from the decapsulation. 9268 * Access: RW 9269 */ 9270 MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2); 9271 9272 /* reg_tndem_trap_en 9273 * Trap enable: 9274 * 0 - No trap due to decap ECN 9275 * 1 - Trap enable with trap_id 9276 * Access: RW 9277 */ 9278 MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4); 9279 9280 /* reg_tndem_trap_id 9281 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 9282 * Reserved when trap_en is '0'. 9283 * Access: RW 9284 */ 9285 MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9); 9286 9287 static inline void mlxsw_reg_tndem_pack(char *payload, u8 underlay_ecn, 9288 u8 overlay_ecn, u8 ecn, bool trap_en, 9289 u16 trap_id) 9290 { 9291 MLXSW_REG_ZERO(tndem, payload); 9292 mlxsw_reg_tndem_underlay_ecn_set(payload, underlay_ecn); 9293 mlxsw_reg_tndem_overlay_ecn_set(payload, overlay_ecn); 9294 mlxsw_reg_tndem_eip_ecn_set(payload, ecn); 9295 mlxsw_reg_tndem_trap_en_set(payload, trap_en); 9296 mlxsw_reg_tndem_trap_id_set(payload, trap_id); 9297 } 9298 9299 /* TNPC - Tunnel Port Configuration Register 9300 * ----------------------------------------- 9301 * The TNPC register is used for tunnel port configuration. 9302 * Reserved when Spectrum. 9303 */ 9304 #define MLXSW_REG_TNPC_ID 0xA020 9305 #define MLXSW_REG_TNPC_LEN 0x18 9306 9307 MLXSW_REG_DEFINE(tnpc, MLXSW_REG_TNPC_ID, MLXSW_REG_TNPC_LEN); 9308 9309 enum mlxsw_reg_tnpc_tunnel_port { 9310 MLXSW_REG_TNPC_TUNNEL_PORT_NVE, 9311 MLXSW_REG_TNPC_TUNNEL_PORT_VPLS, 9312 MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL0, 9313 MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL1, 9314 }; 9315 9316 /* reg_tnpc_tunnel_port 9317 * Tunnel port. 9318 * Access: Index 9319 */ 9320 MLXSW_ITEM32(reg, tnpc, tunnel_port, 0x00, 0, 4); 9321 9322 /* reg_tnpc_learn_enable_v6 9323 * During IPv6 underlay decapsulation, whether to learn from tunnel port. 9324 * Access: RW 9325 */ 9326 MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1); 9327 9328 /* reg_tnpc_learn_enable_v4 9329 * During IPv4 underlay decapsulation, whether to learn from tunnel port. 9330 * Access: RW 9331 */ 9332 MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1); 9333 9334 static inline void mlxsw_reg_tnpc_pack(char *payload, 9335 enum mlxsw_reg_tnpc_tunnel_port tport, 9336 bool learn_enable) 9337 { 9338 MLXSW_REG_ZERO(tnpc, payload); 9339 mlxsw_reg_tnpc_tunnel_port_set(payload, tport); 9340 mlxsw_reg_tnpc_learn_enable_v4_set(payload, learn_enable); 9341 mlxsw_reg_tnpc_learn_enable_v6_set(payload, learn_enable); 9342 } 9343 9344 /* TIGCR - Tunneling IPinIP General Configuration Register 9345 * ------------------------------------------------------- 9346 * The TIGCR register is used for setting up the IPinIP Tunnel configuration. 9347 */ 9348 #define MLXSW_REG_TIGCR_ID 0xA801 9349 #define MLXSW_REG_TIGCR_LEN 0x10 9350 9351 MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN); 9352 9353 /* reg_tigcr_ipip_ttlc 9354 * For IPinIP Tunnel encapsulation: whether to copy the ttl from the packet 9355 * header. 9356 * Access: RW 9357 */ 9358 MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1); 9359 9360 /* reg_tigcr_ipip_ttl_uc 9361 * The TTL for IPinIP Tunnel encapsulation of unicast packets if 9362 * reg_tigcr_ipip_ttlc is unset. 9363 * Access: RW 9364 */ 9365 MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8); 9366 9367 static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc) 9368 { 9369 MLXSW_REG_ZERO(tigcr, payload); 9370 mlxsw_reg_tigcr_ttlc_set(payload, ttlc); 9371 mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc); 9372 } 9373 9374 /* SBPR - Shared Buffer Pools Register 9375 * ----------------------------------- 9376 * The SBPR configures and retrieves the shared buffer pools and configuration. 9377 */ 9378 #define MLXSW_REG_SBPR_ID 0xB001 9379 #define MLXSW_REG_SBPR_LEN 0x14 9380 9381 MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN); 9382 9383 /* shared direstion enum for SBPR, SBCM, SBPM */ 9384 enum mlxsw_reg_sbxx_dir { 9385 MLXSW_REG_SBXX_DIR_INGRESS, 9386 MLXSW_REG_SBXX_DIR_EGRESS, 9387 }; 9388 9389 /* reg_sbpr_dir 9390 * Direction. 9391 * Access: Index 9392 */ 9393 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2); 9394 9395 /* reg_sbpr_pool 9396 * Pool index. 9397 * Access: Index 9398 */ 9399 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4); 9400 9401 /* reg_sbpr_infi_size 9402 * Size is infinite. 9403 * Access: RW 9404 */ 9405 MLXSW_ITEM32(reg, sbpr, infi_size, 0x04, 31, 1); 9406 9407 /* reg_sbpr_size 9408 * Pool size in buffer cells. 9409 * Reserved when infi_size = 1. 9410 * Access: RW 9411 */ 9412 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24); 9413 9414 enum mlxsw_reg_sbpr_mode { 9415 MLXSW_REG_SBPR_MODE_STATIC, 9416 MLXSW_REG_SBPR_MODE_DYNAMIC, 9417 }; 9418 9419 /* reg_sbpr_mode 9420 * Pool quota calculation mode. 9421 * Access: RW 9422 */ 9423 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4); 9424 9425 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool, 9426 enum mlxsw_reg_sbxx_dir dir, 9427 enum mlxsw_reg_sbpr_mode mode, u32 size, 9428 bool infi_size) 9429 { 9430 MLXSW_REG_ZERO(sbpr, payload); 9431 mlxsw_reg_sbpr_pool_set(payload, pool); 9432 mlxsw_reg_sbpr_dir_set(payload, dir); 9433 mlxsw_reg_sbpr_mode_set(payload, mode); 9434 mlxsw_reg_sbpr_size_set(payload, size); 9435 mlxsw_reg_sbpr_infi_size_set(payload, infi_size); 9436 } 9437 9438 /* SBCM - Shared Buffer Class Management Register 9439 * ---------------------------------------------- 9440 * The SBCM register configures and retrieves the shared buffer allocation 9441 * and configuration according to Port-PG, including the binding to pool 9442 * and definition of the associated quota. 9443 */ 9444 #define MLXSW_REG_SBCM_ID 0xB002 9445 #define MLXSW_REG_SBCM_LEN 0x28 9446 9447 MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN); 9448 9449 /* reg_sbcm_local_port 9450 * Local port number. 9451 * For Ingress: excludes CPU port and Router port 9452 * For Egress: excludes IP Router 9453 * Access: Index 9454 */ 9455 MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8); 9456 9457 /* reg_sbcm_pg_buff 9458 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress) 9459 * For PG buffer: range is 0..cap_max_pg_buffers - 1 9460 * For traffic class: range is 0..cap_max_tclass - 1 9461 * Note that when traffic class is in MC aware mode then the traffic 9462 * classes which are MC aware cannot be configured. 9463 * Access: Index 9464 */ 9465 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6); 9466 9467 /* reg_sbcm_dir 9468 * Direction. 9469 * Access: Index 9470 */ 9471 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2); 9472 9473 /* reg_sbcm_min_buff 9474 * Minimum buffer size for the limiter, in cells. 9475 * Access: RW 9476 */ 9477 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24); 9478 9479 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */ 9480 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1 9481 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14 9482 9483 /* reg_sbcm_infi_max 9484 * Max buffer is infinite. 9485 * Access: RW 9486 */ 9487 MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1); 9488 9489 /* reg_sbcm_max_buff 9490 * When the pool associated to the port-pg/tclass is configured to 9491 * static, Maximum buffer size for the limiter configured in cells. 9492 * When the pool associated to the port-pg/tclass is configured to 9493 * dynamic, the max_buff holds the "alpha" parameter, supporting 9494 * the following values: 9495 * 0: 0 9496 * i: (1/128)*2^(i-1), for i=1..14 9497 * 0xFF: Infinity 9498 * Reserved when infi_max = 1. 9499 * Access: RW 9500 */ 9501 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24); 9502 9503 /* reg_sbcm_pool 9504 * Association of the port-priority to a pool. 9505 * Access: RW 9506 */ 9507 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4); 9508 9509 static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff, 9510 enum mlxsw_reg_sbxx_dir dir, 9511 u32 min_buff, u32 max_buff, 9512 bool infi_max, u8 pool) 9513 { 9514 MLXSW_REG_ZERO(sbcm, payload); 9515 mlxsw_reg_sbcm_local_port_set(payload, local_port); 9516 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff); 9517 mlxsw_reg_sbcm_dir_set(payload, dir); 9518 mlxsw_reg_sbcm_min_buff_set(payload, min_buff); 9519 mlxsw_reg_sbcm_max_buff_set(payload, max_buff); 9520 mlxsw_reg_sbcm_infi_max_set(payload, infi_max); 9521 mlxsw_reg_sbcm_pool_set(payload, pool); 9522 } 9523 9524 /* SBPM - Shared Buffer Port Management Register 9525 * --------------------------------------------- 9526 * The SBPM register configures and retrieves the shared buffer allocation 9527 * and configuration according to Port-Pool, including the definition 9528 * of the associated quota. 9529 */ 9530 #define MLXSW_REG_SBPM_ID 0xB003 9531 #define MLXSW_REG_SBPM_LEN 0x28 9532 9533 MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN); 9534 9535 /* reg_sbpm_local_port 9536 * Local port number. 9537 * For Ingress: excludes CPU port and Router port 9538 * For Egress: excludes IP Router 9539 * Access: Index 9540 */ 9541 MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8); 9542 9543 /* reg_sbpm_pool 9544 * The pool associated to quota counting on the local_port. 9545 * Access: Index 9546 */ 9547 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4); 9548 9549 /* reg_sbpm_dir 9550 * Direction. 9551 * Access: Index 9552 */ 9553 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2); 9554 9555 /* reg_sbpm_buff_occupancy 9556 * Current buffer occupancy in cells. 9557 * Access: RO 9558 */ 9559 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24); 9560 9561 /* reg_sbpm_clr 9562 * Clear Max Buffer Occupancy 9563 * When this bit is set, max_buff_occupancy field is cleared (and a 9564 * new max value is tracked from the time the clear was performed). 9565 * Access: OP 9566 */ 9567 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1); 9568 9569 /* reg_sbpm_max_buff_occupancy 9570 * Maximum value of buffer occupancy in cells monitored. Cleared by 9571 * writing to the clr field. 9572 * Access: RO 9573 */ 9574 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24); 9575 9576 /* reg_sbpm_min_buff 9577 * Minimum buffer size for the limiter, in cells. 9578 * Access: RW 9579 */ 9580 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24); 9581 9582 /* reg_sbpm_max_buff 9583 * When the pool associated to the port-pg/tclass is configured to 9584 * static, Maximum buffer size for the limiter configured in cells. 9585 * When the pool associated to the port-pg/tclass is configured to 9586 * dynamic, the max_buff holds the "alpha" parameter, supporting 9587 * the following values: 9588 * 0: 0 9589 * i: (1/128)*2^(i-1), for i=1..14 9590 * 0xFF: Infinity 9591 * Access: RW 9592 */ 9593 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24); 9594 9595 static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool, 9596 enum mlxsw_reg_sbxx_dir dir, bool clr, 9597 u32 min_buff, u32 max_buff) 9598 { 9599 MLXSW_REG_ZERO(sbpm, payload); 9600 mlxsw_reg_sbpm_local_port_set(payload, local_port); 9601 mlxsw_reg_sbpm_pool_set(payload, pool); 9602 mlxsw_reg_sbpm_dir_set(payload, dir); 9603 mlxsw_reg_sbpm_clr_set(payload, clr); 9604 mlxsw_reg_sbpm_min_buff_set(payload, min_buff); 9605 mlxsw_reg_sbpm_max_buff_set(payload, max_buff); 9606 } 9607 9608 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy, 9609 u32 *p_max_buff_occupancy) 9610 { 9611 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload); 9612 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload); 9613 } 9614 9615 /* SBMM - Shared Buffer Multicast Management Register 9616 * -------------------------------------------------- 9617 * The SBMM register configures and retrieves the shared buffer allocation 9618 * and configuration for MC packets according to Switch-Priority, including 9619 * the binding to pool and definition of the associated quota. 9620 */ 9621 #define MLXSW_REG_SBMM_ID 0xB004 9622 #define MLXSW_REG_SBMM_LEN 0x28 9623 9624 MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN); 9625 9626 /* reg_sbmm_prio 9627 * Switch Priority. 9628 * Access: Index 9629 */ 9630 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4); 9631 9632 /* reg_sbmm_min_buff 9633 * Minimum buffer size for the limiter, in cells. 9634 * Access: RW 9635 */ 9636 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24); 9637 9638 /* reg_sbmm_max_buff 9639 * When the pool associated to the port-pg/tclass is configured to 9640 * static, Maximum buffer size for the limiter configured in cells. 9641 * When the pool associated to the port-pg/tclass is configured to 9642 * dynamic, the max_buff holds the "alpha" parameter, supporting 9643 * the following values: 9644 * 0: 0 9645 * i: (1/128)*2^(i-1), for i=1..14 9646 * 0xFF: Infinity 9647 * Access: RW 9648 */ 9649 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24); 9650 9651 /* reg_sbmm_pool 9652 * Association of the port-priority to a pool. 9653 * Access: RW 9654 */ 9655 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4); 9656 9657 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff, 9658 u32 max_buff, u8 pool) 9659 { 9660 MLXSW_REG_ZERO(sbmm, payload); 9661 mlxsw_reg_sbmm_prio_set(payload, prio); 9662 mlxsw_reg_sbmm_min_buff_set(payload, min_buff); 9663 mlxsw_reg_sbmm_max_buff_set(payload, max_buff); 9664 mlxsw_reg_sbmm_pool_set(payload, pool); 9665 } 9666 9667 /* SBSR - Shared Buffer Status Register 9668 * ------------------------------------ 9669 * The SBSR register retrieves the shared buffer occupancy according to 9670 * Port-Pool. Note that this register enables reading a large amount of data. 9671 * It is the user's responsibility to limit the amount of data to ensure the 9672 * response can match the maximum transfer unit. In case the response exceeds 9673 * the maximum transport unit, it will be truncated with no special notice. 9674 */ 9675 #define MLXSW_REG_SBSR_ID 0xB005 9676 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */ 9677 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */ 9678 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120 9679 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \ 9680 MLXSW_REG_SBSR_REC_LEN * \ 9681 MLXSW_REG_SBSR_REC_MAX_COUNT) 9682 9683 MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN); 9684 9685 /* reg_sbsr_clr 9686 * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy 9687 * field is cleared (and a new max value is tracked from the time the clear 9688 * was performed). 9689 * Access: OP 9690 */ 9691 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1); 9692 9693 /* reg_sbsr_ingress_port_mask 9694 * Bit vector for all ingress network ports. 9695 * Indicates which of the ports (for which the relevant bit is set) 9696 * are affected by the set operation. Configuration of any other port 9697 * does not change. 9698 * Access: Index 9699 */ 9700 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1); 9701 9702 /* reg_sbsr_pg_buff_mask 9703 * Bit vector for all switch priority groups. 9704 * Indicates which of the priorities (for which the relevant bit is set) 9705 * are affected by the set operation. Configuration of any other priority 9706 * does not change. 9707 * Range is 0..cap_max_pg_buffers - 1 9708 * Access: Index 9709 */ 9710 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1); 9711 9712 /* reg_sbsr_egress_port_mask 9713 * Bit vector for all egress network ports. 9714 * Indicates which of the ports (for which the relevant bit is set) 9715 * are affected by the set operation. Configuration of any other port 9716 * does not change. 9717 * Access: Index 9718 */ 9719 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1); 9720 9721 /* reg_sbsr_tclass_mask 9722 * Bit vector for all traffic classes. 9723 * Indicates which of the traffic classes (for which the relevant bit is 9724 * set) are affected by the set operation. Configuration of any other 9725 * traffic class does not change. 9726 * Range is 0..cap_max_tclass - 1 9727 * Access: Index 9728 */ 9729 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1); 9730 9731 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr) 9732 { 9733 MLXSW_REG_ZERO(sbsr, payload); 9734 mlxsw_reg_sbsr_clr_set(payload, clr); 9735 } 9736 9737 /* reg_sbsr_rec_buff_occupancy 9738 * Current buffer occupancy in cells. 9739 * Access: RO 9740 */ 9741 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 9742 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false); 9743 9744 /* reg_sbsr_rec_max_buff_occupancy 9745 * Maximum value of buffer occupancy in cells monitored. Cleared by 9746 * writing to the clr field. 9747 * Access: RO 9748 */ 9749 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 9750 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false); 9751 9752 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index, 9753 u32 *p_buff_occupancy, 9754 u32 *p_max_buff_occupancy) 9755 { 9756 *p_buff_occupancy = 9757 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index); 9758 *p_max_buff_occupancy = 9759 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index); 9760 } 9761 9762 /* SBIB - Shared Buffer Internal Buffer Register 9763 * --------------------------------------------- 9764 * The SBIB register configures per port buffers for internal use. The internal 9765 * buffers consume memory on the port buffers (note that the port buffers are 9766 * used also by PBMC). 9767 * 9768 * For Spectrum this is used for egress mirroring. 9769 */ 9770 #define MLXSW_REG_SBIB_ID 0xB006 9771 #define MLXSW_REG_SBIB_LEN 0x10 9772 9773 MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN); 9774 9775 /* reg_sbib_local_port 9776 * Local port number 9777 * Not supported for CPU port and router port 9778 * Access: Index 9779 */ 9780 MLXSW_ITEM32(reg, sbib, local_port, 0x00, 16, 8); 9781 9782 /* reg_sbib_buff_size 9783 * Units represented in cells 9784 * Allowed range is 0 to (cap_max_headroom_size - 1) 9785 * Default is 0 9786 * Access: RW 9787 */ 9788 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24); 9789 9790 static inline void mlxsw_reg_sbib_pack(char *payload, u8 local_port, 9791 u32 buff_size) 9792 { 9793 MLXSW_REG_ZERO(sbib, payload); 9794 mlxsw_reg_sbib_local_port_set(payload, local_port); 9795 mlxsw_reg_sbib_buff_size_set(payload, buff_size); 9796 } 9797 9798 static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { 9799 MLXSW_REG(sgcr), 9800 MLXSW_REG(spad), 9801 MLXSW_REG(smid), 9802 MLXSW_REG(sspr), 9803 MLXSW_REG(sfdat), 9804 MLXSW_REG(sfd), 9805 MLXSW_REG(sfn), 9806 MLXSW_REG(spms), 9807 MLXSW_REG(spvid), 9808 MLXSW_REG(spvm), 9809 MLXSW_REG(spaft), 9810 MLXSW_REG(sfgc), 9811 MLXSW_REG(sftr), 9812 MLXSW_REG(sfdf), 9813 MLXSW_REG(sldr), 9814 MLXSW_REG(slcr), 9815 MLXSW_REG(slcor), 9816 MLXSW_REG(spmlr), 9817 MLXSW_REG(svfa), 9818 MLXSW_REG(svpe), 9819 MLXSW_REG(sfmr), 9820 MLXSW_REG(spvmlr), 9821 MLXSW_REG(cwtp), 9822 MLXSW_REG(cwtpm), 9823 MLXSW_REG(pgcr), 9824 MLXSW_REG(ppbt), 9825 MLXSW_REG(pacl), 9826 MLXSW_REG(pagt), 9827 MLXSW_REG(ptar), 9828 MLXSW_REG(ppbs), 9829 MLXSW_REG(prcr), 9830 MLXSW_REG(pefa), 9831 MLXSW_REG(pemrbt), 9832 MLXSW_REG(ptce2), 9833 MLXSW_REG(perpt), 9834 MLXSW_REG(peabfe), 9835 MLXSW_REG(perar), 9836 MLXSW_REG(ptce3), 9837 MLXSW_REG(percr), 9838 MLXSW_REG(pererp), 9839 MLXSW_REG(iedr), 9840 MLXSW_REG(qpts), 9841 MLXSW_REG(qpcr), 9842 MLXSW_REG(qtct), 9843 MLXSW_REG(qeec), 9844 MLXSW_REG(qrwe), 9845 MLXSW_REG(qpdsm), 9846 MLXSW_REG(qpdpm), 9847 MLXSW_REG(qtctm), 9848 MLXSW_REG(pmlp), 9849 MLXSW_REG(pmtu), 9850 MLXSW_REG(ptys), 9851 MLXSW_REG(ppad), 9852 MLXSW_REG(paos), 9853 MLXSW_REG(pfcc), 9854 MLXSW_REG(ppcnt), 9855 MLXSW_REG(plib), 9856 MLXSW_REG(pptb), 9857 MLXSW_REG(pbmc), 9858 MLXSW_REG(pspa), 9859 MLXSW_REG(htgt), 9860 MLXSW_REG(hpkt), 9861 MLXSW_REG(rgcr), 9862 MLXSW_REG(ritr), 9863 MLXSW_REG(rtar), 9864 MLXSW_REG(ratr), 9865 MLXSW_REG(rtdp), 9866 MLXSW_REG(rdpm), 9867 MLXSW_REG(ricnt), 9868 MLXSW_REG(rrcr), 9869 MLXSW_REG(ralta), 9870 MLXSW_REG(ralst), 9871 MLXSW_REG(raltb), 9872 MLXSW_REG(ralue), 9873 MLXSW_REG(rauht), 9874 MLXSW_REG(raleu), 9875 MLXSW_REG(rauhtd), 9876 MLXSW_REG(rigr2), 9877 MLXSW_REG(recr2), 9878 MLXSW_REG(rmft2), 9879 MLXSW_REG(mfcr), 9880 MLXSW_REG(mfsc), 9881 MLXSW_REG(mfsm), 9882 MLXSW_REG(mfsl), 9883 MLXSW_REG(fore), 9884 MLXSW_REG(mtcap), 9885 MLXSW_REG(mtmp), 9886 MLXSW_REG(mtbr), 9887 MLXSW_REG(mcia), 9888 MLXSW_REG(mpat), 9889 MLXSW_REG(mpar), 9890 MLXSW_REG(mrsr), 9891 MLXSW_REG(mlcr), 9892 MLXSW_REG(mpsc), 9893 MLXSW_REG(mcqi), 9894 MLXSW_REG(mcc), 9895 MLXSW_REG(mcda), 9896 MLXSW_REG(mgpc), 9897 MLXSW_REG(mprs), 9898 MLXSW_REG(tngcr), 9899 MLXSW_REG(tnumt), 9900 MLXSW_REG(tnqcr), 9901 MLXSW_REG(tnqdr), 9902 MLXSW_REG(tneem), 9903 MLXSW_REG(tndem), 9904 MLXSW_REG(tnpc), 9905 MLXSW_REG(tigcr), 9906 MLXSW_REG(sbpr), 9907 MLXSW_REG(sbcm), 9908 MLXSW_REG(sbpm), 9909 MLXSW_REG(sbmm), 9910 MLXSW_REG(sbsr), 9911 MLXSW_REG(sbib), 9912 }; 9913 9914 static inline const char *mlxsw_reg_id_str(u16 reg_id) 9915 { 9916 const struct mlxsw_reg_info *reg_info; 9917 int i; 9918 9919 for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) { 9920 reg_info = mlxsw_reg_infos[i]; 9921 if (reg_info->id == reg_id) 9922 return reg_info->name; 9923 } 9924 return "*UNKNOWN*"; 9925 } 9926 9927 /* PUDE - Port Up / Down Event 9928 * --------------------------- 9929 * Reports the operational state change of a port. 9930 */ 9931 #define MLXSW_REG_PUDE_LEN 0x10 9932 9933 /* reg_pude_swid 9934 * Switch partition ID with which to associate the port. 9935 * Access: Index 9936 */ 9937 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8); 9938 9939 /* reg_pude_local_port 9940 * Local port number. 9941 * Access: Index 9942 */ 9943 MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8); 9944 9945 /* reg_pude_admin_status 9946 * Port administrative state (the desired state). 9947 * 1 - Up. 9948 * 2 - Down. 9949 * 3 - Up once. This means that in case of link failure, the port won't go 9950 * into polling mode, but will wait to be re-enabled by software. 9951 * 4 - Disabled by system. Can only be set by hardware. 9952 * Access: RO 9953 */ 9954 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4); 9955 9956 /* reg_pude_oper_status 9957 * Port operatioanl state. 9958 * 1 - Up. 9959 * 2 - Down. 9960 * 3 - Down by port failure. This means that the device will not let the 9961 * port up again until explicitly specified by software. 9962 * Access: RO 9963 */ 9964 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4); 9965 9966 #endif 9967