1 /* 2 * drivers/net/ethernet/mellanox/mlxsw/reg.h 3 * Copyright (c) 2015-2017 Mellanox Technologies. All rights reserved. 4 * Copyright (c) 2015-2016 Ido Schimmel <idosch@mellanox.com> 5 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com> 6 * Copyright (c) 2015-2017 Jiri Pirko <jiri@mellanox.com> 7 * Copyright (c) 2016 Yotam Gigi <yotamg@mellanox.com> 8 * Copyright (c) 2017 Petr Machata <petrm@mellanox.com> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the names of the copyright holders nor the names of its 19 * contributors may be used to endorse or promote products derived from 20 * this software without specific prior written permission. 21 * 22 * Alternatively, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2 as published by the Free 24 * Software Foundation. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 27 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 30 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _MLXSW_REG_H 40 #define _MLXSW_REG_H 41 42 #include <linux/string.h> 43 #include <linux/bitops.h> 44 #include <linux/if_vlan.h> 45 46 #include "item.h" 47 #include "port.h" 48 49 struct mlxsw_reg_info { 50 u16 id; 51 u16 len; /* In u8 */ 52 const char *name; 53 }; 54 55 #define MLXSW_REG_DEFINE(_name, _id, _len) \ 56 static const struct mlxsw_reg_info mlxsw_reg_##_name = { \ 57 .id = _id, \ 58 .len = _len, \ 59 .name = #_name, \ 60 } 61 62 #define MLXSW_REG(type) (&mlxsw_reg_##type) 63 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len 64 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len) 65 66 /* SGCR - Switch General Configuration Register 67 * -------------------------------------------- 68 * This register is used for configuration of the switch capabilities. 69 */ 70 #define MLXSW_REG_SGCR_ID 0x2000 71 #define MLXSW_REG_SGCR_LEN 0x10 72 73 MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN); 74 75 /* reg_sgcr_llb 76 * Link Local Broadcast (Default=0) 77 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast 78 * packets and ignore the IGMP snooping entries. 79 * Access: RW 80 */ 81 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1); 82 83 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb) 84 { 85 MLXSW_REG_ZERO(sgcr, payload); 86 mlxsw_reg_sgcr_llb_set(payload, !!llb); 87 } 88 89 /* SPAD - Switch Physical Address Register 90 * --------------------------------------- 91 * The SPAD register configures the switch physical MAC address. 92 */ 93 #define MLXSW_REG_SPAD_ID 0x2002 94 #define MLXSW_REG_SPAD_LEN 0x10 95 96 MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN); 97 98 /* reg_spad_base_mac 99 * Base MAC address for the switch partitions. 100 * Per switch partition MAC address is equal to: 101 * base_mac + swid 102 * Access: RW 103 */ 104 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6); 105 106 /* SMID - Switch Multicast ID 107 * -------------------------- 108 * The MID record maps from a MID (Multicast ID), which is a unique identifier 109 * of the multicast group within the stacking domain, into a list of local 110 * ports into which the packet is replicated. 111 */ 112 #define MLXSW_REG_SMID_ID 0x2007 113 #define MLXSW_REG_SMID_LEN 0x240 114 115 MLXSW_REG_DEFINE(smid, MLXSW_REG_SMID_ID, MLXSW_REG_SMID_LEN); 116 117 /* reg_smid_swid 118 * Switch partition ID. 119 * Access: Index 120 */ 121 MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8); 122 123 /* reg_smid_mid 124 * Multicast identifier - global identifier that represents the multicast group 125 * across all devices. 126 * Access: Index 127 */ 128 MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16); 129 130 /* reg_smid_port 131 * Local port memebership (1 bit per port). 132 * Access: RW 133 */ 134 MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1); 135 136 /* reg_smid_port_mask 137 * Local port mask (1 bit per port). 138 * Access: W 139 */ 140 MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1); 141 142 static inline void mlxsw_reg_smid_pack(char *payload, u16 mid, 143 u8 port, bool set) 144 { 145 MLXSW_REG_ZERO(smid, payload); 146 mlxsw_reg_smid_swid_set(payload, 0); 147 mlxsw_reg_smid_mid_set(payload, mid); 148 mlxsw_reg_smid_port_set(payload, port, set); 149 mlxsw_reg_smid_port_mask_set(payload, port, 1); 150 } 151 152 /* SSPR - Switch System Port Record Register 153 * ----------------------------------------- 154 * Configures the system port to local port mapping. 155 */ 156 #define MLXSW_REG_SSPR_ID 0x2008 157 #define MLXSW_REG_SSPR_LEN 0x8 158 159 MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN); 160 161 /* reg_sspr_m 162 * Master - if set, then the record describes the master system port. 163 * This is needed in case a local port is mapped into several system ports 164 * (for multipathing). That number will be reported as the source system 165 * port when packets are forwarded to the CPU. Only one master port is allowed 166 * per local port. 167 * 168 * Note: Must be set for Spectrum. 169 * Access: RW 170 */ 171 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1); 172 173 /* reg_sspr_local_port 174 * Local port number. 175 * 176 * Access: RW 177 */ 178 MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8); 179 180 /* reg_sspr_sub_port 181 * Virtual port within the physical port. 182 * Should be set to 0 when virtual ports are not enabled on the port. 183 * 184 * Access: RW 185 */ 186 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8); 187 188 /* reg_sspr_system_port 189 * Unique identifier within the stacking domain that represents all the ports 190 * that are available in the system (external ports). 191 * 192 * Currently, only single-ASIC configurations are supported, so we default to 193 * 1:1 mapping between system ports and local ports. 194 * Access: Index 195 */ 196 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16); 197 198 static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port) 199 { 200 MLXSW_REG_ZERO(sspr, payload); 201 mlxsw_reg_sspr_m_set(payload, 1); 202 mlxsw_reg_sspr_local_port_set(payload, local_port); 203 mlxsw_reg_sspr_sub_port_set(payload, 0); 204 mlxsw_reg_sspr_system_port_set(payload, local_port); 205 } 206 207 /* SFDAT - Switch Filtering Database Aging Time 208 * -------------------------------------------- 209 * Controls the Switch aging time. Aging time is able to be set per Switch 210 * Partition. 211 */ 212 #define MLXSW_REG_SFDAT_ID 0x2009 213 #define MLXSW_REG_SFDAT_LEN 0x8 214 215 MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN); 216 217 /* reg_sfdat_swid 218 * Switch partition ID. 219 * Access: Index 220 */ 221 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8); 222 223 /* reg_sfdat_age_time 224 * Aging time in seconds 225 * Min - 10 seconds 226 * Max - 1,000,000 seconds 227 * Default is 300 seconds. 228 * Access: RW 229 */ 230 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20); 231 232 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time) 233 { 234 MLXSW_REG_ZERO(sfdat, payload); 235 mlxsw_reg_sfdat_swid_set(payload, 0); 236 mlxsw_reg_sfdat_age_time_set(payload, age_time); 237 } 238 239 /* SFD - Switch Filtering Database 240 * ------------------------------- 241 * The following register defines the access to the filtering database. 242 * The register supports querying, adding, removing and modifying the database. 243 * The access is optimized for bulk updates in which case more than one 244 * FDB record is present in the same command. 245 */ 246 #define MLXSW_REG_SFD_ID 0x200A 247 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */ 248 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */ 249 #define MLXSW_REG_SFD_REC_MAX_COUNT 64 250 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \ 251 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT) 252 253 MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN); 254 255 /* reg_sfd_swid 256 * Switch partition ID for queries. Reserved on Write. 257 * Access: Index 258 */ 259 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8); 260 261 enum mlxsw_reg_sfd_op { 262 /* Dump entire FDB a (process according to record_locator) */ 263 MLXSW_REG_SFD_OP_QUERY_DUMP = 0, 264 /* Query records by {MAC, VID/FID} value */ 265 MLXSW_REG_SFD_OP_QUERY_QUERY = 1, 266 /* Query and clear activity. Query records by {MAC, VID/FID} value */ 267 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2, 268 /* Test. Response indicates if each of the records could be 269 * added to the FDB. 270 */ 271 MLXSW_REG_SFD_OP_WRITE_TEST = 0, 272 /* Add/modify. Aged-out records cannot be added. This command removes 273 * the learning notification of the {MAC, VID/FID}. Response includes 274 * the entries that were added to the FDB. 275 */ 276 MLXSW_REG_SFD_OP_WRITE_EDIT = 1, 277 /* Remove record by {MAC, VID/FID}. This command also removes 278 * the learning notification and aged-out notifications 279 * of the {MAC, VID/FID}. The response provides current (pre-removal) 280 * entries as non-aged-out. 281 */ 282 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2, 283 /* Remove learned notification by {MAC, VID/FID}. The response provides 284 * the removed learning notification. 285 */ 286 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2, 287 }; 288 289 /* reg_sfd_op 290 * Operation. 291 * Access: OP 292 */ 293 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2); 294 295 /* reg_sfd_record_locator 296 * Used for querying the FDB. Use record_locator=0 to initiate the 297 * query. When a record is returned, a new record_locator is 298 * returned to be used in the subsequent query. 299 * Reserved for database update. 300 * Access: Index 301 */ 302 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30); 303 304 /* reg_sfd_num_rec 305 * Request: Number of records to read/add/modify/remove 306 * Response: Number of records read/added/replaced/removed 307 * See above description for more details. 308 * Ranges 0..64 309 * Access: RW 310 */ 311 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8); 312 313 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op, 314 u32 record_locator) 315 { 316 MLXSW_REG_ZERO(sfd, payload); 317 mlxsw_reg_sfd_op_set(payload, op); 318 mlxsw_reg_sfd_record_locator_set(payload, record_locator); 319 } 320 321 /* reg_sfd_rec_swid 322 * Switch partition ID. 323 * Access: Index 324 */ 325 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8, 326 MLXSW_REG_SFD_REC_LEN, 0x00, false); 327 328 enum mlxsw_reg_sfd_rec_type { 329 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0, 330 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1, 331 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2, 332 }; 333 334 /* reg_sfd_rec_type 335 * FDB record type. 336 * Access: RW 337 */ 338 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4, 339 MLXSW_REG_SFD_REC_LEN, 0x00, false); 340 341 enum mlxsw_reg_sfd_rec_policy { 342 /* Replacement disabled, aging disabled. */ 343 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0, 344 /* (mlag remote): Replacement enabled, aging disabled, 345 * learning notification enabled on this port. 346 */ 347 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1, 348 /* (ingress device): Replacement enabled, aging enabled. */ 349 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3, 350 }; 351 352 /* reg_sfd_rec_policy 353 * Policy. 354 * Access: RW 355 */ 356 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2, 357 MLXSW_REG_SFD_REC_LEN, 0x00, false); 358 359 /* reg_sfd_rec_a 360 * Activity. Set for new static entries. Set for static entries if a frame SMAC 361 * lookup hits on the entry. 362 * To clear the a bit, use "query and clear activity" op. 363 * Access: RO 364 */ 365 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1, 366 MLXSW_REG_SFD_REC_LEN, 0x00, false); 367 368 /* reg_sfd_rec_mac 369 * MAC address. 370 * Access: Index 371 */ 372 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6, 373 MLXSW_REG_SFD_REC_LEN, 0x02); 374 375 enum mlxsw_reg_sfd_rec_action { 376 /* forward */ 377 MLXSW_REG_SFD_REC_ACTION_NOP = 0, 378 /* forward and trap, trap_id is FDB_TRAP */ 379 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1, 380 /* trap and do not forward, trap_id is FDB_TRAP */ 381 MLXSW_REG_SFD_REC_ACTION_TRAP = 2, 382 /* forward to IP router */ 383 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3, 384 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15, 385 }; 386 387 /* reg_sfd_rec_action 388 * Action to apply on the packet. 389 * Note: Dynamic entries can only be configured with NOP action. 390 * Access: RW 391 */ 392 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4, 393 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 394 395 /* reg_sfd_uc_sub_port 396 * VEPA channel on local port. 397 * Valid only if local port is a non-stacking port. Must be 0 if multichannel 398 * VEPA is not enabled. 399 * Access: RW 400 */ 401 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 402 MLXSW_REG_SFD_REC_LEN, 0x08, false); 403 404 /* reg_sfd_uc_fid_vid 405 * Filtering ID or VLAN ID 406 * For SwitchX and SwitchX-2: 407 * - Dynamic entries (policy 2,3) use FID 408 * - Static entries (policy 0) use VID 409 * - When independent learning is configured, VID=FID 410 * For Spectrum: use FID for both Dynamic and Static entries. 411 * VID should not be used. 412 * Access: Index 413 */ 414 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 415 MLXSW_REG_SFD_REC_LEN, 0x08, false); 416 417 /* reg_sfd_uc_system_port 418 * Unique port identifier for the final destination of the packet. 419 * Access: RW 420 */ 421 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16, 422 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 423 424 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index, 425 enum mlxsw_reg_sfd_rec_type rec_type, 426 const char *mac, 427 enum mlxsw_reg_sfd_rec_action action) 428 { 429 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload); 430 431 if (rec_index >= num_rec) 432 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1); 433 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0); 434 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type); 435 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac); 436 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action); 437 } 438 439 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index, 440 enum mlxsw_reg_sfd_rec_policy policy, 441 const char *mac, u16 fid_vid, 442 enum mlxsw_reg_sfd_rec_action action, 443 u8 local_port) 444 { 445 mlxsw_reg_sfd_rec_pack(payload, rec_index, 446 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action); 447 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 448 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0); 449 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid); 450 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port); 451 } 452 453 static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index, 454 char *mac, u16 *p_fid_vid, 455 u8 *p_local_port) 456 { 457 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 458 *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index); 459 *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index); 460 } 461 462 /* reg_sfd_uc_lag_sub_port 463 * LAG sub port. 464 * Must be 0 if multichannel VEPA is not enabled. 465 * Access: RW 466 */ 467 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 468 MLXSW_REG_SFD_REC_LEN, 0x08, false); 469 470 /* reg_sfd_uc_lag_fid_vid 471 * Filtering ID or VLAN ID 472 * For SwitchX and SwitchX-2: 473 * - Dynamic entries (policy 2,3) use FID 474 * - Static entries (policy 0) use VID 475 * - When independent learning is configured, VID=FID 476 * For Spectrum: use FID for both Dynamic and Static entries. 477 * VID should not be used. 478 * Access: Index 479 */ 480 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 481 MLXSW_REG_SFD_REC_LEN, 0x08, false); 482 483 /* reg_sfd_uc_lag_lag_vid 484 * Indicates VID in case of vFIDs. Reserved for FIDs. 485 * Access: RW 486 */ 487 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, 488 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 489 490 /* reg_sfd_uc_lag_lag_id 491 * LAG Identifier - pointer into the LAG descriptor table. 492 * Access: RW 493 */ 494 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10, 495 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 496 497 static inline void 498 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index, 499 enum mlxsw_reg_sfd_rec_policy policy, 500 const char *mac, u16 fid_vid, 501 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid, 502 u16 lag_id) 503 { 504 mlxsw_reg_sfd_rec_pack(payload, rec_index, 505 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG, 506 mac, action); 507 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 508 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0); 509 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid); 510 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid); 511 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id); 512 } 513 514 static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index, 515 char *mac, u16 *p_vid, 516 u16 *p_lag_id) 517 { 518 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 519 *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index); 520 *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index); 521 } 522 523 /* reg_sfd_mc_pgi 524 * 525 * Multicast port group index - index into the port group table. 526 * Value 0x1FFF indicates the pgi should point to the MID entry. 527 * For Spectrum this value must be set to 0x1FFF 528 * Access: RW 529 */ 530 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13, 531 MLXSW_REG_SFD_REC_LEN, 0x08, false); 532 533 /* reg_sfd_mc_fid_vid 534 * 535 * Filtering ID or VLAN ID 536 * Access: Index 537 */ 538 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 539 MLXSW_REG_SFD_REC_LEN, 0x08, false); 540 541 /* reg_sfd_mc_mid 542 * 543 * Multicast identifier - global identifier that represents the multicast 544 * group across all devices. 545 * Access: RW 546 */ 547 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 548 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 549 550 static inline void 551 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index, 552 const char *mac, u16 fid_vid, 553 enum mlxsw_reg_sfd_rec_action action, u16 mid) 554 { 555 mlxsw_reg_sfd_rec_pack(payload, rec_index, 556 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action); 557 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF); 558 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid); 559 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid); 560 } 561 562 /* SFN - Switch FDB Notification Register 563 * ------------------------------------------- 564 * The switch provides notifications on newly learned FDB entries and 565 * aged out entries. The notifications can be polled by software. 566 */ 567 #define MLXSW_REG_SFN_ID 0x200B 568 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */ 569 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */ 570 #define MLXSW_REG_SFN_REC_MAX_COUNT 64 571 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \ 572 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT) 573 574 MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN); 575 576 /* reg_sfn_swid 577 * Switch partition ID. 578 * Access: Index 579 */ 580 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8); 581 582 /* reg_sfn_end 583 * Forces the current session to end. 584 * Access: OP 585 */ 586 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1); 587 588 /* reg_sfn_num_rec 589 * Request: Number of learned notifications and aged-out notification 590 * records requested. 591 * Response: Number of notification records returned (must be smaller 592 * than or equal to the value requested) 593 * Ranges 0..64 594 * Access: OP 595 */ 596 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8); 597 598 static inline void mlxsw_reg_sfn_pack(char *payload) 599 { 600 MLXSW_REG_ZERO(sfn, payload); 601 mlxsw_reg_sfn_swid_set(payload, 0); 602 mlxsw_reg_sfn_end_set(payload, 1); 603 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT); 604 } 605 606 /* reg_sfn_rec_swid 607 * Switch partition ID. 608 * Access: RO 609 */ 610 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8, 611 MLXSW_REG_SFN_REC_LEN, 0x00, false); 612 613 enum mlxsw_reg_sfn_rec_type { 614 /* MAC addresses learned on a regular port. */ 615 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5, 616 /* MAC addresses learned on a LAG port. */ 617 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6, 618 /* Aged-out MAC address on a regular port. */ 619 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7, 620 /* Aged-out MAC address on a LAG port. */ 621 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8, 622 }; 623 624 /* reg_sfn_rec_type 625 * Notification record type. 626 * Access: RO 627 */ 628 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4, 629 MLXSW_REG_SFN_REC_LEN, 0x00, false); 630 631 /* reg_sfn_rec_mac 632 * MAC address. 633 * Access: RO 634 */ 635 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6, 636 MLXSW_REG_SFN_REC_LEN, 0x02); 637 638 /* reg_sfn_mac_sub_port 639 * VEPA channel on the local port. 640 * 0 if multichannel VEPA is not enabled. 641 * Access: RO 642 */ 643 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8, 644 MLXSW_REG_SFN_REC_LEN, 0x08, false); 645 646 /* reg_sfn_mac_fid 647 * Filtering identifier. 648 * Access: RO 649 */ 650 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16, 651 MLXSW_REG_SFN_REC_LEN, 0x08, false); 652 653 /* reg_sfn_mac_system_port 654 * Unique port identifier for the final destination of the packet. 655 * Access: RO 656 */ 657 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16, 658 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 659 660 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index, 661 char *mac, u16 *p_vid, 662 u8 *p_local_port) 663 { 664 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 665 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 666 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index); 667 } 668 669 /* reg_sfn_mac_lag_lag_id 670 * LAG ID (pointer into the LAG descriptor table). 671 * Access: RO 672 */ 673 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10, 674 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 675 676 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index, 677 char *mac, u16 *p_vid, 678 u16 *p_lag_id) 679 { 680 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 681 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 682 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index); 683 } 684 685 /* SPMS - Switch Port MSTP/RSTP State Register 686 * ------------------------------------------- 687 * Configures the spanning tree state of a physical port. 688 */ 689 #define MLXSW_REG_SPMS_ID 0x200D 690 #define MLXSW_REG_SPMS_LEN 0x404 691 692 MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN); 693 694 /* reg_spms_local_port 695 * Local port number. 696 * Access: Index 697 */ 698 MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8); 699 700 enum mlxsw_reg_spms_state { 701 MLXSW_REG_SPMS_STATE_NO_CHANGE, 702 MLXSW_REG_SPMS_STATE_DISCARDING, 703 MLXSW_REG_SPMS_STATE_LEARNING, 704 MLXSW_REG_SPMS_STATE_FORWARDING, 705 }; 706 707 /* reg_spms_state 708 * Spanning tree state of each VLAN ID (VID) of the local port. 709 * 0 - Do not change spanning tree state (used only when writing). 710 * 1 - Discarding. No learning or forwarding to/from this port (default). 711 * 2 - Learning. Port is learning, but not forwarding. 712 * 3 - Forwarding. Port is learning and forwarding. 713 * Access: RW 714 */ 715 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2); 716 717 static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port) 718 { 719 MLXSW_REG_ZERO(spms, payload); 720 mlxsw_reg_spms_local_port_set(payload, local_port); 721 } 722 723 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid, 724 enum mlxsw_reg_spms_state state) 725 { 726 mlxsw_reg_spms_state_set(payload, vid, state); 727 } 728 729 /* SPVID - Switch Port VID 730 * ----------------------- 731 * The switch port VID configures the default VID for a port. 732 */ 733 #define MLXSW_REG_SPVID_ID 0x200E 734 #define MLXSW_REG_SPVID_LEN 0x08 735 736 MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN); 737 738 /* reg_spvid_local_port 739 * Local port number. 740 * Access: Index 741 */ 742 MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8); 743 744 /* reg_spvid_sub_port 745 * Virtual port within the physical port. 746 * Should be set to 0 when virtual ports are not enabled on the port. 747 * Access: Index 748 */ 749 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8); 750 751 /* reg_spvid_pvid 752 * Port default VID 753 * Access: RW 754 */ 755 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12); 756 757 static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid) 758 { 759 MLXSW_REG_ZERO(spvid, payload); 760 mlxsw_reg_spvid_local_port_set(payload, local_port); 761 mlxsw_reg_spvid_pvid_set(payload, pvid); 762 } 763 764 /* SPVM - Switch Port VLAN Membership 765 * ---------------------------------- 766 * The Switch Port VLAN Membership register configures the VLAN membership 767 * of a port in a VLAN denoted by VID. VLAN membership is managed per 768 * virtual port. The register can be used to add and remove VID(s) from a port. 769 */ 770 #define MLXSW_REG_SPVM_ID 0x200F 771 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */ 772 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */ 773 #define MLXSW_REG_SPVM_REC_MAX_COUNT 255 774 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \ 775 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT) 776 777 MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN); 778 779 /* reg_spvm_pt 780 * Priority tagged. If this bit is set, packets forwarded to the port with 781 * untagged VLAN membership (u bit is set) will be tagged with priority tag 782 * (VID=0) 783 * Access: RW 784 */ 785 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1); 786 787 /* reg_spvm_pte 788 * Priority Tagged Update Enable. On Write operations, if this bit is cleared, 789 * the pt bit will NOT be updated. To update the pt bit, pte must be set. 790 * Access: WO 791 */ 792 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1); 793 794 /* reg_spvm_local_port 795 * Local port number. 796 * Access: Index 797 */ 798 MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8); 799 800 /* reg_spvm_sub_port 801 * Virtual port within the physical port. 802 * Should be set to 0 when virtual ports are not enabled on the port. 803 * Access: Index 804 */ 805 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8); 806 807 /* reg_spvm_num_rec 808 * Number of records to update. Each record contains: i, e, u, vid. 809 * Access: OP 810 */ 811 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8); 812 813 /* reg_spvm_rec_i 814 * Ingress membership in VLAN ID. 815 * Access: Index 816 */ 817 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i, 818 MLXSW_REG_SPVM_BASE_LEN, 14, 1, 819 MLXSW_REG_SPVM_REC_LEN, 0, false); 820 821 /* reg_spvm_rec_e 822 * Egress membership in VLAN ID. 823 * Access: Index 824 */ 825 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e, 826 MLXSW_REG_SPVM_BASE_LEN, 13, 1, 827 MLXSW_REG_SPVM_REC_LEN, 0, false); 828 829 /* reg_spvm_rec_u 830 * Untagged - port is an untagged member - egress transmission uses untagged 831 * frames on VID<n> 832 * Access: Index 833 */ 834 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u, 835 MLXSW_REG_SPVM_BASE_LEN, 12, 1, 836 MLXSW_REG_SPVM_REC_LEN, 0, false); 837 838 /* reg_spvm_rec_vid 839 * Egress membership in VLAN ID. 840 * Access: Index 841 */ 842 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid, 843 MLXSW_REG_SPVM_BASE_LEN, 0, 12, 844 MLXSW_REG_SPVM_REC_LEN, 0, false); 845 846 static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port, 847 u16 vid_begin, u16 vid_end, 848 bool is_member, bool untagged) 849 { 850 int size = vid_end - vid_begin + 1; 851 int i; 852 853 MLXSW_REG_ZERO(spvm, payload); 854 mlxsw_reg_spvm_local_port_set(payload, local_port); 855 mlxsw_reg_spvm_num_rec_set(payload, size); 856 857 for (i = 0; i < size; i++) { 858 mlxsw_reg_spvm_rec_i_set(payload, i, is_member); 859 mlxsw_reg_spvm_rec_e_set(payload, i, is_member); 860 mlxsw_reg_spvm_rec_u_set(payload, i, untagged); 861 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i); 862 } 863 } 864 865 /* SPAFT - Switch Port Acceptable Frame Types 866 * ------------------------------------------ 867 * The Switch Port Acceptable Frame Types register configures the frame 868 * admittance of the port. 869 */ 870 #define MLXSW_REG_SPAFT_ID 0x2010 871 #define MLXSW_REG_SPAFT_LEN 0x08 872 873 MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN); 874 875 /* reg_spaft_local_port 876 * Local port number. 877 * Access: Index 878 * 879 * Note: CPU port is not supported (all tag types are allowed). 880 */ 881 MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8); 882 883 /* reg_spaft_sub_port 884 * Virtual port within the physical port. 885 * Should be set to 0 when virtual ports are not enabled on the port. 886 * Access: RW 887 */ 888 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8); 889 890 /* reg_spaft_allow_untagged 891 * When set, untagged frames on the ingress are allowed (default). 892 * Access: RW 893 */ 894 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1); 895 896 /* reg_spaft_allow_prio_tagged 897 * When set, priority tagged frames on the ingress are allowed (default). 898 * Access: RW 899 */ 900 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1); 901 902 /* reg_spaft_allow_tagged 903 * When set, tagged frames on the ingress are allowed (default). 904 * Access: RW 905 */ 906 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1); 907 908 static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port, 909 bool allow_untagged) 910 { 911 MLXSW_REG_ZERO(spaft, payload); 912 mlxsw_reg_spaft_local_port_set(payload, local_port); 913 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged); 914 mlxsw_reg_spaft_allow_prio_tagged_set(payload, true); 915 mlxsw_reg_spaft_allow_tagged_set(payload, true); 916 } 917 918 /* SFGC - Switch Flooding Group Configuration 919 * ------------------------------------------ 920 * The following register controls the association of flooding tables and MIDs 921 * to packet types used for flooding. 922 */ 923 #define MLXSW_REG_SFGC_ID 0x2011 924 #define MLXSW_REG_SFGC_LEN 0x10 925 926 MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN); 927 928 enum mlxsw_reg_sfgc_type { 929 MLXSW_REG_SFGC_TYPE_BROADCAST, 930 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST, 931 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4, 932 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6, 933 MLXSW_REG_SFGC_TYPE_RESERVED, 934 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP, 935 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL, 936 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST, 937 MLXSW_REG_SFGC_TYPE_MAX, 938 }; 939 940 /* reg_sfgc_type 941 * The traffic type to reach the flooding table. 942 * Access: Index 943 */ 944 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4); 945 946 enum mlxsw_reg_sfgc_bridge_type { 947 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0, 948 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1, 949 }; 950 951 /* reg_sfgc_bridge_type 952 * Access: Index 953 * 954 * Note: SwitchX-2 only supports 802.1Q mode. 955 */ 956 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3); 957 958 enum mlxsw_flood_table_type { 959 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1, 960 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2, 961 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0, 962 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3, 963 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4, 964 }; 965 966 /* reg_sfgc_table_type 967 * See mlxsw_flood_table_type 968 * Access: RW 969 * 970 * Note: FID offset and FID types are not supported in SwitchX-2. 971 */ 972 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3); 973 974 /* reg_sfgc_flood_table 975 * Flooding table index to associate with the specific type on the specific 976 * switch partition. 977 * Access: RW 978 */ 979 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6); 980 981 /* reg_sfgc_mid 982 * The multicast ID for the swid. Not supported for Spectrum 983 * Access: RW 984 */ 985 MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16); 986 987 /* reg_sfgc_counter_set_type 988 * Counter Set Type for flow counters. 989 * Access: RW 990 */ 991 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8); 992 993 /* reg_sfgc_counter_index 994 * Counter Index for flow counters. 995 * Access: RW 996 */ 997 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24); 998 999 static inline void 1000 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type, 1001 enum mlxsw_reg_sfgc_bridge_type bridge_type, 1002 enum mlxsw_flood_table_type table_type, 1003 unsigned int flood_table) 1004 { 1005 MLXSW_REG_ZERO(sfgc, payload); 1006 mlxsw_reg_sfgc_type_set(payload, type); 1007 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type); 1008 mlxsw_reg_sfgc_table_type_set(payload, table_type); 1009 mlxsw_reg_sfgc_flood_table_set(payload, flood_table); 1010 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID); 1011 } 1012 1013 /* SFTR - Switch Flooding Table Register 1014 * ------------------------------------- 1015 * The switch flooding table is used for flooding packet replication. The table 1016 * defines a bit mask of ports for packet replication. 1017 */ 1018 #define MLXSW_REG_SFTR_ID 0x2012 1019 #define MLXSW_REG_SFTR_LEN 0x420 1020 1021 MLXSW_REG_DEFINE(sftr, MLXSW_REG_SFTR_ID, MLXSW_REG_SFTR_LEN); 1022 1023 /* reg_sftr_swid 1024 * Switch partition ID with which to associate the port. 1025 * Access: Index 1026 */ 1027 MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8); 1028 1029 /* reg_sftr_flood_table 1030 * Flooding table index to associate with the specific type on the specific 1031 * switch partition. 1032 * Access: Index 1033 */ 1034 MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6); 1035 1036 /* reg_sftr_index 1037 * Index. Used as an index into the Flooding Table in case the table is 1038 * configured to use VID / FID or FID Offset. 1039 * Access: Index 1040 */ 1041 MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16); 1042 1043 /* reg_sftr_table_type 1044 * See mlxsw_flood_table_type 1045 * Access: RW 1046 */ 1047 MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3); 1048 1049 /* reg_sftr_range 1050 * Range of entries to update 1051 * Access: Index 1052 */ 1053 MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16); 1054 1055 /* reg_sftr_port 1056 * Local port membership (1 bit per port). 1057 * Access: RW 1058 */ 1059 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1); 1060 1061 /* reg_sftr_cpu_port_mask 1062 * CPU port mask (1 bit per port). 1063 * Access: W 1064 */ 1065 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1); 1066 1067 static inline void mlxsw_reg_sftr_pack(char *payload, 1068 unsigned int flood_table, 1069 unsigned int index, 1070 enum mlxsw_flood_table_type table_type, 1071 unsigned int range, u8 port, bool set) 1072 { 1073 MLXSW_REG_ZERO(sftr, payload); 1074 mlxsw_reg_sftr_swid_set(payload, 0); 1075 mlxsw_reg_sftr_flood_table_set(payload, flood_table); 1076 mlxsw_reg_sftr_index_set(payload, index); 1077 mlxsw_reg_sftr_table_type_set(payload, table_type); 1078 mlxsw_reg_sftr_range_set(payload, range); 1079 mlxsw_reg_sftr_port_set(payload, port, set); 1080 mlxsw_reg_sftr_port_mask_set(payload, port, 1); 1081 } 1082 1083 /* SFDF - Switch Filtering DB Flush 1084 * -------------------------------- 1085 * The switch filtering DB flush register is used to flush the FDB. 1086 * Note that FDB notifications are flushed as well. 1087 */ 1088 #define MLXSW_REG_SFDF_ID 0x2013 1089 #define MLXSW_REG_SFDF_LEN 0x14 1090 1091 MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN); 1092 1093 /* reg_sfdf_swid 1094 * Switch partition ID. 1095 * Access: Index 1096 */ 1097 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8); 1098 1099 enum mlxsw_reg_sfdf_flush_type { 1100 MLXSW_REG_SFDF_FLUSH_PER_SWID, 1101 MLXSW_REG_SFDF_FLUSH_PER_FID, 1102 MLXSW_REG_SFDF_FLUSH_PER_PORT, 1103 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID, 1104 MLXSW_REG_SFDF_FLUSH_PER_LAG, 1105 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID, 1106 }; 1107 1108 /* reg_sfdf_flush_type 1109 * Flush type. 1110 * 0 - All SWID dynamic entries are flushed. 1111 * 1 - All FID dynamic entries are flushed. 1112 * 2 - All dynamic entries pointing to port are flushed. 1113 * 3 - All FID dynamic entries pointing to port are flushed. 1114 * 4 - All dynamic entries pointing to LAG are flushed. 1115 * 5 - All FID dynamic entries pointing to LAG are flushed. 1116 * Access: RW 1117 */ 1118 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4); 1119 1120 /* reg_sfdf_flush_static 1121 * Static. 1122 * 0 - Flush only dynamic entries. 1123 * 1 - Flush both dynamic and static entries. 1124 * Access: RW 1125 */ 1126 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1); 1127 1128 static inline void mlxsw_reg_sfdf_pack(char *payload, 1129 enum mlxsw_reg_sfdf_flush_type type) 1130 { 1131 MLXSW_REG_ZERO(sfdf, payload); 1132 mlxsw_reg_sfdf_flush_type_set(payload, type); 1133 mlxsw_reg_sfdf_flush_static_set(payload, true); 1134 } 1135 1136 /* reg_sfdf_fid 1137 * FID to flush. 1138 * Access: RW 1139 */ 1140 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16); 1141 1142 /* reg_sfdf_system_port 1143 * Port to flush. 1144 * Access: RW 1145 */ 1146 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16); 1147 1148 /* reg_sfdf_port_fid_system_port 1149 * Port to flush, pointed to by FID. 1150 * Access: RW 1151 */ 1152 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16); 1153 1154 /* reg_sfdf_lag_id 1155 * LAG ID to flush. 1156 * Access: RW 1157 */ 1158 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10); 1159 1160 /* reg_sfdf_lag_fid_lag_id 1161 * LAG ID to flush, pointed to by FID. 1162 * Access: RW 1163 */ 1164 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10); 1165 1166 /* SLDR - Switch LAG Descriptor Register 1167 * ----------------------------------------- 1168 * The switch LAG descriptor register is populated by LAG descriptors. 1169 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to 1170 * max_lag-1. 1171 */ 1172 #define MLXSW_REG_SLDR_ID 0x2014 1173 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */ 1174 1175 MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN); 1176 1177 enum mlxsw_reg_sldr_op { 1178 /* Indicates a creation of a new LAG-ID, lag_id must be valid */ 1179 MLXSW_REG_SLDR_OP_LAG_CREATE, 1180 MLXSW_REG_SLDR_OP_LAG_DESTROY, 1181 /* Ports that appear in the list have the Distributor enabled */ 1182 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST, 1183 /* Removes ports from the disributor list */ 1184 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST, 1185 }; 1186 1187 /* reg_sldr_op 1188 * Operation. 1189 * Access: RW 1190 */ 1191 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3); 1192 1193 /* reg_sldr_lag_id 1194 * LAG identifier. The lag_id is the index into the LAG descriptor table. 1195 * Access: Index 1196 */ 1197 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10); 1198 1199 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id) 1200 { 1201 MLXSW_REG_ZERO(sldr, payload); 1202 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE); 1203 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1204 } 1205 1206 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id) 1207 { 1208 MLXSW_REG_ZERO(sldr, payload); 1209 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY); 1210 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1211 } 1212 1213 /* reg_sldr_num_ports 1214 * The number of member ports of the LAG. 1215 * Reserved for Create / Destroy operations 1216 * For Add / Remove operations - indicates the number of ports in the list. 1217 * Access: RW 1218 */ 1219 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8); 1220 1221 /* reg_sldr_system_port 1222 * System port. 1223 * Access: RW 1224 */ 1225 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false); 1226 1227 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id, 1228 u8 local_port) 1229 { 1230 MLXSW_REG_ZERO(sldr, payload); 1231 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST); 1232 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1233 mlxsw_reg_sldr_num_ports_set(payload, 1); 1234 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1235 } 1236 1237 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id, 1238 u8 local_port) 1239 { 1240 MLXSW_REG_ZERO(sldr, payload); 1241 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST); 1242 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1243 mlxsw_reg_sldr_num_ports_set(payload, 1); 1244 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1245 } 1246 1247 /* SLCR - Switch LAG Configuration 2 Register 1248 * ------------------------------------------- 1249 * The Switch LAG Configuration register is used for configuring the 1250 * LAG properties of the switch. 1251 */ 1252 #define MLXSW_REG_SLCR_ID 0x2015 1253 #define MLXSW_REG_SLCR_LEN 0x10 1254 1255 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN); 1256 1257 enum mlxsw_reg_slcr_pp { 1258 /* Global Configuration (for all ports) */ 1259 MLXSW_REG_SLCR_PP_GLOBAL, 1260 /* Per port configuration, based on local_port field */ 1261 MLXSW_REG_SLCR_PP_PER_PORT, 1262 }; 1263 1264 /* reg_slcr_pp 1265 * Per Port Configuration 1266 * Note: Reading at Global mode results in reading port 1 configuration. 1267 * Access: Index 1268 */ 1269 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1); 1270 1271 /* reg_slcr_local_port 1272 * Local port number 1273 * Supported from CPU port 1274 * Not supported from router port 1275 * Reserved when pp = Global Configuration 1276 * Access: Index 1277 */ 1278 MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8); 1279 1280 enum mlxsw_reg_slcr_type { 1281 MLXSW_REG_SLCR_TYPE_CRC, /* default */ 1282 MLXSW_REG_SLCR_TYPE_XOR, 1283 MLXSW_REG_SLCR_TYPE_RANDOM, 1284 }; 1285 1286 /* reg_slcr_type 1287 * Hash type 1288 * Access: RW 1289 */ 1290 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4); 1291 1292 /* Ingress port */ 1293 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0) 1294 /* SMAC - for IPv4 and IPv6 packets */ 1295 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1) 1296 /* SMAC - for non-IP packets */ 1297 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2) 1298 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \ 1299 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \ 1300 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP) 1301 /* DMAC - for IPv4 and IPv6 packets */ 1302 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3) 1303 /* DMAC - for non-IP packets */ 1304 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4) 1305 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \ 1306 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \ 1307 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP) 1308 /* Ethertype - for IPv4 and IPv6 packets */ 1309 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5) 1310 /* Ethertype - for non-IP packets */ 1311 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6) 1312 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \ 1313 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \ 1314 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP) 1315 /* VLAN ID - for IPv4 and IPv6 packets */ 1316 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7) 1317 /* VLAN ID - for non-IP packets */ 1318 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8) 1319 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \ 1320 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \ 1321 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP) 1322 /* Source IP address (can be IPv4 or IPv6) */ 1323 #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9) 1324 /* Destination IP address (can be IPv4 or IPv6) */ 1325 #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10) 1326 /* TCP/UDP source port */ 1327 #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11) 1328 /* TCP/UDP destination port*/ 1329 #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12) 1330 /* IPv4 Protocol/IPv6 Next Header */ 1331 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13) 1332 /* IPv6 Flow label */ 1333 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14) 1334 /* SID - FCoE source ID */ 1335 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15) 1336 /* DID - FCoE destination ID */ 1337 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16) 1338 /* OXID - FCoE originator exchange ID */ 1339 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17) 1340 /* Destination QP number - for RoCE packets */ 1341 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19) 1342 1343 /* reg_slcr_lag_hash 1344 * LAG hashing configuration. This is a bitmask, in which each set 1345 * bit includes the corresponding item in the LAG hash calculation. 1346 * The default lag_hash contains SMAC, DMAC, VLANID and 1347 * Ethertype (for all packet types). 1348 * Access: RW 1349 */ 1350 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20); 1351 1352 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash) 1353 { 1354 MLXSW_REG_ZERO(slcr, payload); 1355 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL); 1356 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC); 1357 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash); 1358 } 1359 1360 /* SLCOR - Switch LAG Collector Register 1361 * ------------------------------------- 1362 * The Switch LAG Collector register controls the Local Port membership 1363 * in a LAG and enablement of the collector. 1364 */ 1365 #define MLXSW_REG_SLCOR_ID 0x2016 1366 #define MLXSW_REG_SLCOR_LEN 0x10 1367 1368 MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN); 1369 1370 enum mlxsw_reg_slcor_col { 1371 /* Port is added with collector disabled */ 1372 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT, 1373 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED, 1374 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED, 1375 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT, 1376 }; 1377 1378 /* reg_slcor_col 1379 * Collector configuration 1380 * Access: RW 1381 */ 1382 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2); 1383 1384 /* reg_slcor_local_port 1385 * Local port number 1386 * Not supported for CPU port 1387 * Access: Index 1388 */ 1389 MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8); 1390 1391 /* reg_slcor_lag_id 1392 * LAG Identifier. Index into the LAG descriptor table. 1393 * Access: Index 1394 */ 1395 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10); 1396 1397 /* reg_slcor_port_index 1398 * Port index in the LAG list. Only valid on Add Port to LAG col. 1399 * Valid range is from 0 to cap_max_lag_members-1 1400 * Access: RW 1401 */ 1402 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10); 1403 1404 static inline void mlxsw_reg_slcor_pack(char *payload, 1405 u8 local_port, u16 lag_id, 1406 enum mlxsw_reg_slcor_col col) 1407 { 1408 MLXSW_REG_ZERO(slcor, payload); 1409 mlxsw_reg_slcor_col_set(payload, col); 1410 mlxsw_reg_slcor_local_port_set(payload, local_port); 1411 mlxsw_reg_slcor_lag_id_set(payload, lag_id); 1412 } 1413 1414 static inline void mlxsw_reg_slcor_port_add_pack(char *payload, 1415 u8 local_port, u16 lag_id, 1416 u8 port_index) 1417 { 1418 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1419 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT); 1420 mlxsw_reg_slcor_port_index_set(payload, port_index); 1421 } 1422 1423 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload, 1424 u8 local_port, u16 lag_id) 1425 { 1426 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1427 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT); 1428 } 1429 1430 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload, 1431 u8 local_port, u16 lag_id) 1432 { 1433 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1434 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1435 } 1436 1437 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload, 1438 u8 local_port, u16 lag_id) 1439 { 1440 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1441 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1442 } 1443 1444 /* SPMLR - Switch Port MAC Learning Register 1445 * ----------------------------------------- 1446 * Controls the Switch MAC learning policy per port. 1447 */ 1448 #define MLXSW_REG_SPMLR_ID 0x2018 1449 #define MLXSW_REG_SPMLR_LEN 0x8 1450 1451 MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN); 1452 1453 /* reg_spmlr_local_port 1454 * Local port number. 1455 * Access: Index 1456 */ 1457 MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8); 1458 1459 /* reg_spmlr_sub_port 1460 * Virtual port within the physical port. 1461 * Should be set to 0 when virtual ports are not enabled on the port. 1462 * Access: Index 1463 */ 1464 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8); 1465 1466 enum mlxsw_reg_spmlr_learn_mode { 1467 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0, 1468 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2, 1469 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3, 1470 }; 1471 1472 /* reg_spmlr_learn_mode 1473 * Learning mode on the port. 1474 * 0 - Learning disabled. 1475 * 2 - Learning enabled. 1476 * 3 - Security mode. 1477 * 1478 * In security mode the switch does not learn MACs on the port, but uses the 1479 * SMAC to see if it exists on another ingress port. If so, the packet is 1480 * classified as a bad packet and is discarded unless the software registers 1481 * to receive port security error packets usign HPKT. 1482 */ 1483 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2); 1484 1485 static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port, 1486 enum mlxsw_reg_spmlr_learn_mode mode) 1487 { 1488 MLXSW_REG_ZERO(spmlr, payload); 1489 mlxsw_reg_spmlr_local_port_set(payload, local_port); 1490 mlxsw_reg_spmlr_sub_port_set(payload, 0); 1491 mlxsw_reg_spmlr_learn_mode_set(payload, mode); 1492 } 1493 1494 /* SVFA - Switch VID to FID Allocation Register 1495 * -------------------------------------------- 1496 * Controls the VID to FID mapping and {Port, VID} to FID mapping for 1497 * virtualized ports. 1498 */ 1499 #define MLXSW_REG_SVFA_ID 0x201C 1500 #define MLXSW_REG_SVFA_LEN 0x10 1501 1502 MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN); 1503 1504 /* reg_svfa_swid 1505 * Switch partition ID. 1506 * Access: Index 1507 */ 1508 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8); 1509 1510 /* reg_svfa_local_port 1511 * Local port number. 1512 * Access: Index 1513 * 1514 * Note: Reserved for 802.1Q FIDs. 1515 */ 1516 MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8); 1517 1518 enum mlxsw_reg_svfa_mt { 1519 MLXSW_REG_SVFA_MT_VID_TO_FID, 1520 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, 1521 }; 1522 1523 /* reg_svfa_mapping_table 1524 * Mapping table: 1525 * 0 - VID to FID 1526 * 1 - {Port, VID} to FID 1527 * Access: Index 1528 * 1529 * Note: Reserved for SwitchX-2. 1530 */ 1531 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3); 1532 1533 /* reg_svfa_v 1534 * Valid. 1535 * Valid if set. 1536 * Access: RW 1537 * 1538 * Note: Reserved for SwitchX-2. 1539 */ 1540 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1); 1541 1542 /* reg_svfa_fid 1543 * Filtering ID. 1544 * Access: RW 1545 */ 1546 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16); 1547 1548 /* reg_svfa_vid 1549 * VLAN ID. 1550 * Access: Index 1551 */ 1552 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12); 1553 1554 /* reg_svfa_counter_set_type 1555 * Counter set type for flow counters. 1556 * Access: RW 1557 * 1558 * Note: Reserved for SwitchX-2. 1559 */ 1560 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8); 1561 1562 /* reg_svfa_counter_index 1563 * Counter index for flow counters. 1564 * Access: RW 1565 * 1566 * Note: Reserved for SwitchX-2. 1567 */ 1568 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24); 1569 1570 static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port, 1571 enum mlxsw_reg_svfa_mt mt, bool valid, 1572 u16 fid, u16 vid) 1573 { 1574 MLXSW_REG_ZERO(svfa, payload); 1575 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port; 1576 mlxsw_reg_svfa_swid_set(payload, 0); 1577 mlxsw_reg_svfa_local_port_set(payload, local_port); 1578 mlxsw_reg_svfa_mapping_table_set(payload, mt); 1579 mlxsw_reg_svfa_v_set(payload, valid); 1580 mlxsw_reg_svfa_fid_set(payload, fid); 1581 mlxsw_reg_svfa_vid_set(payload, vid); 1582 } 1583 1584 /* SVPE - Switch Virtual-Port Enabling Register 1585 * -------------------------------------------- 1586 * Enables port virtualization. 1587 */ 1588 #define MLXSW_REG_SVPE_ID 0x201E 1589 #define MLXSW_REG_SVPE_LEN 0x4 1590 1591 MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN); 1592 1593 /* reg_svpe_local_port 1594 * Local port number 1595 * Access: Index 1596 * 1597 * Note: CPU port is not supported (uses VLAN mode only). 1598 */ 1599 MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8); 1600 1601 /* reg_svpe_vp_en 1602 * Virtual port enable. 1603 * 0 - Disable, VLAN mode (VID to FID). 1604 * 1 - Enable, Virtual port mode ({Port, VID} to FID). 1605 * Access: RW 1606 */ 1607 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1); 1608 1609 static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port, 1610 bool enable) 1611 { 1612 MLXSW_REG_ZERO(svpe, payload); 1613 mlxsw_reg_svpe_local_port_set(payload, local_port); 1614 mlxsw_reg_svpe_vp_en_set(payload, enable); 1615 } 1616 1617 /* SFMR - Switch FID Management Register 1618 * ------------------------------------- 1619 * Creates and configures FIDs. 1620 */ 1621 #define MLXSW_REG_SFMR_ID 0x201F 1622 #define MLXSW_REG_SFMR_LEN 0x18 1623 1624 MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN); 1625 1626 enum mlxsw_reg_sfmr_op { 1627 MLXSW_REG_SFMR_OP_CREATE_FID, 1628 MLXSW_REG_SFMR_OP_DESTROY_FID, 1629 }; 1630 1631 /* reg_sfmr_op 1632 * Operation. 1633 * 0 - Create or edit FID. 1634 * 1 - Destroy FID. 1635 * Access: WO 1636 */ 1637 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4); 1638 1639 /* reg_sfmr_fid 1640 * Filtering ID. 1641 * Access: Index 1642 */ 1643 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16); 1644 1645 /* reg_sfmr_fid_offset 1646 * FID offset. 1647 * Used to point into the flooding table selected by SFGC register if 1648 * the table is of type FID-Offset. Otherwise, this field is reserved. 1649 * Access: RW 1650 */ 1651 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16); 1652 1653 /* reg_sfmr_vtfp 1654 * Valid Tunnel Flood Pointer. 1655 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL. 1656 * Access: RW 1657 * 1658 * Note: Reserved for 802.1Q FIDs. 1659 */ 1660 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1); 1661 1662 /* reg_sfmr_nve_tunnel_flood_ptr 1663 * Underlay Flooding and BC Pointer. 1664 * Used as a pointer to the first entry of the group based link lists of 1665 * flooding or BC entries (for NVE tunnels). 1666 * Access: RW 1667 */ 1668 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24); 1669 1670 /* reg_sfmr_vv 1671 * VNI Valid. 1672 * If not set, then vni is reserved. 1673 * Access: RW 1674 * 1675 * Note: Reserved for 802.1Q FIDs. 1676 */ 1677 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1); 1678 1679 /* reg_sfmr_vni 1680 * Virtual Network Identifier. 1681 * Access: RW 1682 * 1683 * Note: A given VNI can only be assigned to one FID. 1684 */ 1685 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24); 1686 1687 static inline void mlxsw_reg_sfmr_pack(char *payload, 1688 enum mlxsw_reg_sfmr_op op, u16 fid, 1689 u16 fid_offset) 1690 { 1691 MLXSW_REG_ZERO(sfmr, payload); 1692 mlxsw_reg_sfmr_op_set(payload, op); 1693 mlxsw_reg_sfmr_fid_set(payload, fid); 1694 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset); 1695 mlxsw_reg_sfmr_vtfp_set(payload, false); 1696 mlxsw_reg_sfmr_vv_set(payload, false); 1697 } 1698 1699 /* SPVMLR - Switch Port VLAN MAC Learning Register 1700 * ----------------------------------------------- 1701 * Controls the switch MAC learning policy per {Port, VID}. 1702 */ 1703 #define MLXSW_REG_SPVMLR_ID 0x2020 1704 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */ 1705 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */ 1706 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255 1707 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \ 1708 MLXSW_REG_SPVMLR_REC_LEN * \ 1709 MLXSW_REG_SPVMLR_REC_MAX_COUNT) 1710 1711 MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN); 1712 1713 /* reg_spvmlr_local_port 1714 * Local ingress port. 1715 * Access: Index 1716 * 1717 * Note: CPU port is not supported. 1718 */ 1719 MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8); 1720 1721 /* reg_spvmlr_num_rec 1722 * Number of records to update. 1723 * Access: OP 1724 */ 1725 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8); 1726 1727 /* reg_spvmlr_rec_learn_enable 1728 * 0 - Disable learning for {Port, VID}. 1729 * 1 - Enable learning for {Port, VID}. 1730 * Access: RW 1731 */ 1732 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN, 1733 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1734 1735 /* reg_spvmlr_rec_vid 1736 * VLAN ID to be added/removed from port or for querying. 1737 * Access: Index 1738 */ 1739 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12, 1740 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1741 1742 static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port, 1743 u16 vid_begin, u16 vid_end, 1744 bool learn_enable) 1745 { 1746 int num_rec = vid_end - vid_begin + 1; 1747 int i; 1748 1749 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT); 1750 1751 MLXSW_REG_ZERO(spvmlr, payload); 1752 mlxsw_reg_spvmlr_local_port_set(payload, local_port); 1753 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec); 1754 1755 for (i = 0; i < num_rec; i++) { 1756 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable); 1757 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i); 1758 } 1759 } 1760 1761 /* PPBT - Policy-Engine Port Binding Table 1762 * --------------------------------------- 1763 * This register is used for configuration of the Port Binding Table. 1764 */ 1765 #define MLXSW_REG_PPBT_ID 0x3002 1766 #define MLXSW_REG_PPBT_LEN 0x14 1767 1768 MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN); 1769 1770 enum mlxsw_reg_pxbt_e { 1771 MLXSW_REG_PXBT_E_IACL, 1772 MLXSW_REG_PXBT_E_EACL, 1773 }; 1774 1775 /* reg_ppbt_e 1776 * Access: Index 1777 */ 1778 MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1); 1779 1780 enum mlxsw_reg_pxbt_op { 1781 MLXSW_REG_PXBT_OP_BIND, 1782 MLXSW_REG_PXBT_OP_UNBIND, 1783 }; 1784 1785 /* reg_ppbt_op 1786 * Access: RW 1787 */ 1788 MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3); 1789 1790 /* reg_ppbt_local_port 1791 * Local port. Not including CPU port. 1792 * Access: Index 1793 */ 1794 MLXSW_ITEM32(reg, ppbt, local_port, 0x00, 16, 8); 1795 1796 /* reg_ppbt_g 1797 * group - When set, the binding is of an ACL group. When cleared, 1798 * the binding is of an ACL. 1799 * Must be set to 1 for Spectrum. 1800 * Access: RW 1801 */ 1802 MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1); 1803 1804 /* reg_ppbt_acl_info 1805 * ACL/ACL group identifier. If the g bit is set, this field should hold 1806 * the acl_group_id, else it should hold the acl_id. 1807 * Access: RW 1808 */ 1809 MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16); 1810 1811 static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e, 1812 enum mlxsw_reg_pxbt_op op, 1813 u8 local_port, u16 acl_info) 1814 { 1815 MLXSW_REG_ZERO(ppbt, payload); 1816 mlxsw_reg_ppbt_e_set(payload, e); 1817 mlxsw_reg_ppbt_op_set(payload, op); 1818 mlxsw_reg_ppbt_local_port_set(payload, local_port); 1819 mlxsw_reg_ppbt_g_set(payload, true); 1820 mlxsw_reg_ppbt_acl_info_set(payload, acl_info); 1821 } 1822 1823 /* PACL - Policy-Engine ACL Register 1824 * --------------------------------- 1825 * This register is used for configuration of the ACL. 1826 */ 1827 #define MLXSW_REG_PACL_ID 0x3004 1828 #define MLXSW_REG_PACL_LEN 0x70 1829 1830 MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN); 1831 1832 /* reg_pacl_v 1833 * Valid. Setting the v bit makes the ACL valid. It should not be cleared 1834 * while the ACL is bounded to either a port, VLAN or ACL rule. 1835 * Access: RW 1836 */ 1837 MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1); 1838 1839 /* reg_pacl_acl_id 1840 * An identifier representing the ACL (managed by software) 1841 * Range 0 .. cap_max_acl_regions - 1 1842 * Access: Index 1843 */ 1844 MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16); 1845 1846 #define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16 1847 1848 /* reg_pacl_tcam_region_info 1849 * Opaque object that represents a TCAM region. 1850 * Obtained through PTAR register. 1851 * Access: RW 1852 */ 1853 MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30, 1854 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 1855 1856 static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id, 1857 bool valid, const char *tcam_region_info) 1858 { 1859 MLXSW_REG_ZERO(pacl, payload); 1860 mlxsw_reg_pacl_acl_id_set(payload, acl_id); 1861 mlxsw_reg_pacl_v_set(payload, valid); 1862 mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info); 1863 } 1864 1865 /* PAGT - Policy-Engine ACL Group Table 1866 * ------------------------------------ 1867 * This register is used for configuration of the ACL Group Table. 1868 */ 1869 #define MLXSW_REG_PAGT_ID 0x3005 1870 #define MLXSW_REG_PAGT_BASE_LEN 0x30 1871 #define MLXSW_REG_PAGT_ACL_LEN 4 1872 #define MLXSW_REG_PAGT_ACL_MAX_NUM 16 1873 #define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \ 1874 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN) 1875 1876 MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN); 1877 1878 /* reg_pagt_size 1879 * Number of ACLs in the group. 1880 * Size 0 invalidates a group. 1881 * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now) 1882 * Total number of ACLs in all groups must be lower or equal 1883 * to cap_max_acl_tot_groups 1884 * Note: a group which is binded must not be invalidated 1885 * Access: Index 1886 */ 1887 MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8); 1888 1889 /* reg_pagt_acl_group_id 1890 * An identifier (numbered from 0..cap_max_acl_groups-1) representing 1891 * the ACL Group identifier (managed by software). 1892 * Access: Index 1893 */ 1894 MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16); 1895 1896 /* reg_pagt_acl_id 1897 * ACL identifier 1898 * Access: RW 1899 */ 1900 MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false); 1901 1902 static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id) 1903 { 1904 MLXSW_REG_ZERO(pagt, payload); 1905 mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id); 1906 } 1907 1908 static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index, 1909 u16 acl_id) 1910 { 1911 u8 size = mlxsw_reg_pagt_size_get(payload); 1912 1913 if (index >= size) 1914 mlxsw_reg_pagt_size_set(payload, index + 1); 1915 mlxsw_reg_pagt_acl_id_set(payload, index, acl_id); 1916 } 1917 1918 /* PTAR - Policy-Engine TCAM Allocation Register 1919 * --------------------------------------------- 1920 * This register is used for allocation of regions in the TCAM. 1921 * Note: Query method is not supported on this register. 1922 */ 1923 #define MLXSW_REG_PTAR_ID 0x3006 1924 #define MLXSW_REG_PTAR_BASE_LEN 0x20 1925 #define MLXSW_REG_PTAR_KEY_ID_LEN 1 1926 #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16 1927 #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \ 1928 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN) 1929 1930 MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN); 1931 1932 enum mlxsw_reg_ptar_op { 1933 /* allocate a TCAM region */ 1934 MLXSW_REG_PTAR_OP_ALLOC, 1935 /* resize a TCAM region */ 1936 MLXSW_REG_PTAR_OP_RESIZE, 1937 /* deallocate TCAM region */ 1938 MLXSW_REG_PTAR_OP_FREE, 1939 /* test allocation */ 1940 MLXSW_REG_PTAR_OP_TEST, 1941 }; 1942 1943 /* reg_ptar_op 1944 * Access: OP 1945 */ 1946 MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4); 1947 1948 /* reg_ptar_action_set_type 1949 * Type of action set to be used on this region. 1950 * For Spectrum, this is always type 2 - "flexible" 1951 * Access: WO 1952 */ 1953 MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8); 1954 1955 /* reg_ptar_key_type 1956 * TCAM key type for the region. 1957 * For Spectrum, this is always type 0x50 - "FLEX_KEY" 1958 * Access: WO 1959 */ 1960 MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8); 1961 1962 /* reg_ptar_region_size 1963 * TCAM region size. When allocating/resizing this is the requested size, 1964 * the response is the actual size. Note that actual size may be 1965 * larger than requested. 1966 * Allowed range 1 .. cap_max_rules-1 1967 * Reserved during op deallocate. 1968 * Access: WO 1969 */ 1970 MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16); 1971 1972 /* reg_ptar_region_id 1973 * Region identifier 1974 * Range 0 .. cap_max_regions-1 1975 * Access: Index 1976 */ 1977 MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16); 1978 1979 /* reg_ptar_tcam_region_info 1980 * Opaque object that represents the TCAM region. 1981 * Returned when allocating a region. 1982 * Provided by software for ACL generation and region deallocation and resize. 1983 * Access: RW 1984 */ 1985 MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10, 1986 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 1987 1988 /* reg_ptar_flexible_key_id 1989 * Identifier of the Flexible Key. 1990 * Only valid if key_type == "FLEX_KEY" 1991 * The key size will be rounded up to one of the following values: 1992 * 9B, 18B, 36B, 54B. 1993 * This field is reserved for in resize operation. 1994 * Access: WO 1995 */ 1996 MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8, 1997 MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false); 1998 1999 static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op, 2000 u16 region_size, u16 region_id, 2001 const char *tcam_region_info) 2002 { 2003 MLXSW_REG_ZERO(ptar, payload); 2004 mlxsw_reg_ptar_op_set(payload, op); 2005 mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */ 2006 mlxsw_reg_ptar_key_type_set(payload, 0x50); /* "FLEX_KEY" */ 2007 mlxsw_reg_ptar_region_size_set(payload, region_size); 2008 mlxsw_reg_ptar_region_id_set(payload, region_id); 2009 mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info); 2010 } 2011 2012 static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index, 2013 u16 key_id) 2014 { 2015 mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id); 2016 } 2017 2018 static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info) 2019 { 2020 mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info); 2021 } 2022 2023 /* PPBS - Policy-Engine Policy Based Switching Register 2024 * ---------------------------------------------------- 2025 * This register retrieves and sets Policy Based Switching Table entries. 2026 */ 2027 #define MLXSW_REG_PPBS_ID 0x300C 2028 #define MLXSW_REG_PPBS_LEN 0x14 2029 2030 MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN); 2031 2032 /* reg_ppbs_pbs_ptr 2033 * Index into the PBS table. 2034 * For Spectrum, the index points to the KVD Linear. 2035 * Access: Index 2036 */ 2037 MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24); 2038 2039 /* reg_ppbs_system_port 2040 * Unique port identifier for the final destination of the packet. 2041 * Access: RW 2042 */ 2043 MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16); 2044 2045 static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr, 2046 u16 system_port) 2047 { 2048 MLXSW_REG_ZERO(ppbs, payload); 2049 mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr); 2050 mlxsw_reg_ppbs_system_port_set(payload, system_port); 2051 } 2052 2053 /* PRCR - Policy-Engine Rules Copy Register 2054 * ---------------------------------------- 2055 * This register is used for accessing rules within a TCAM region. 2056 */ 2057 #define MLXSW_REG_PRCR_ID 0x300D 2058 #define MLXSW_REG_PRCR_LEN 0x40 2059 2060 MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN); 2061 2062 enum mlxsw_reg_prcr_op { 2063 /* Move rules. Moves the rules from "tcam_region_info" starting 2064 * at offset "offset" to "dest_tcam_region_info" 2065 * at offset "dest_offset." 2066 */ 2067 MLXSW_REG_PRCR_OP_MOVE, 2068 /* Copy rules. Copies the rules from "tcam_region_info" starting 2069 * at offset "offset" to "dest_tcam_region_info" 2070 * at offset "dest_offset." 2071 */ 2072 MLXSW_REG_PRCR_OP_COPY, 2073 }; 2074 2075 /* reg_prcr_op 2076 * Access: OP 2077 */ 2078 MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4); 2079 2080 /* reg_prcr_offset 2081 * Offset within the source region to copy/move from. 2082 * Access: Index 2083 */ 2084 MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16); 2085 2086 /* reg_prcr_size 2087 * The number of rules to copy/move. 2088 * Access: WO 2089 */ 2090 MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16); 2091 2092 /* reg_prcr_tcam_region_info 2093 * Opaque object that represents the source TCAM region. 2094 * Access: Index 2095 */ 2096 MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10, 2097 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2098 2099 /* reg_prcr_dest_offset 2100 * Offset within the source region to copy/move to. 2101 * Access: Index 2102 */ 2103 MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16); 2104 2105 /* reg_prcr_dest_tcam_region_info 2106 * Opaque object that represents the destination TCAM region. 2107 * Access: Index 2108 */ 2109 MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30, 2110 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2111 2112 static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op, 2113 const char *src_tcam_region_info, 2114 u16 src_offset, 2115 const char *dest_tcam_region_info, 2116 u16 dest_offset, u16 size) 2117 { 2118 MLXSW_REG_ZERO(prcr, payload); 2119 mlxsw_reg_prcr_op_set(payload, op); 2120 mlxsw_reg_prcr_offset_set(payload, src_offset); 2121 mlxsw_reg_prcr_size_set(payload, size); 2122 mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload, 2123 src_tcam_region_info); 2124 mlxsw_reg_prcr_dest_offset_set(payload, dest_offset); 2125 mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload, 2126 dest_tcam_region_info); 2127 } 2128 2129 /* PEFA - Policy-Engine Extended Flexible Action Register 2130 * ------------------------------------------------------ 2131 * This register is used for accessing an extended flexible action entry 2132 * in the central KVD Linear Database. 2133 */ 2134 #define MLXSW_REG_PEFA_ID 0x300F 2135 #define MLXSW_REG_PEFA_LEN 0xB0 2136 2137 MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN); 2138 2139 /* reg_pefa_index 2140 * Index in the KVD Linear Centralized Database. 2141 * Access: Index 2142 */ 2143 MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24); 2144 2145 #define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8 2146 2147 /* reg_pefa_flex_action_set 2148 * Action-set to perform when rule is matched. 2149 * Must be zero padded if action set is shorter. 2150 * Access: RW 2151 */ 2152 MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN); 2153 2154 static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, 2155 const char *flex_action_set) 2156 { 2157 MLXSW_REG_ZERO(pefa, payload); 2158 mlxsw_reg_pefa_index_set(payload, index); 2159 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload, flex_action_set); 2160 } 2161 2162 /* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2 2163 * ----------------------------------------------------- 2164 * This register is used for accessing rules within a TCAM region. 2165 * It is a new version of PTCE in order to support wider key, 2166 * mask and action within a TCAM region. This register is not supported 2167 * by SwitchX and SwitchX-2. 2168 */ 2169 #define MLXSW_REG_PTCE2_ID 0x3017 2170 #define MLXSW_REG_PTCE2_LEN 0x1D8 2171 2172 MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN); 2173 2174 /* reg_ptce2_v 2175 * Valid. 2176 * Access: RW 2177 */ 2178 MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1); 2179 2180 /* reg_ptce2_a 2181 * Activity. Set if a packet lookup has hit on the specific entry. 2182 * To clear the "a" bit, use "clear activity" op or "clear on read" op. 2183 * Access: RO 2184 */ 2185 MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1); 2186 2187 enum mlxsw_reg_ptce2_op { 2188 /* Read operation. */ 2189 MLXSW_REG_PTCE2_OP_QUERY_READ = 0, 2190 /* clear on read operation. Used to read entry 2191 * and clear Activity bit. 2192 */ 2193 MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1, 2194 /* Write operation. Used to write a new entry to the table. 2195 * All R/W fields are relevant for new entry. Activity bit is set 2196 * for new entries - Note write with v = 0 will delete the entry. 2197 */ 2198 MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0, 2199 /* Update action. Only action set will be updated. */ 2200 MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1, 2201 /* Clear activity. A bit is cleared for the entry. */ 2202 MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2, 2203 }; 2204 2205 /* reg_ptce2_op 2206 * Access: OP 2207 */ 2208 MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3); 2209 2210 /* reg_ptce2_offset 2211 * Access: Index 2212 */ 2213 MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16); 2214 2215 /* reg_ptce2_tcam_region_info 2216 * Opaque object that represents the TCAM region. 2217 * Access: Index 2218 */ 2219 MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10, 2220 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2221 2222 #define MLXSW_REG_PTCE2_FLEX_KEY_BLOCKS_LEN 96 2223 2224 /* reg_ptce2_flex_key_blocks 2225 * ACL Key. 2226 * Access: RW 2227 */ 2228 MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20, 2229 MLXSW_REG_PTCE2_FLEX_KEY_BLOCKS_LEN); 2230 2231 /* reg_ptce2_mask 2232 * mask- in the same size as key. A bit that is set directs the TCAM 2233 * to compare the corresponding bit in key. A bit that is clear directs 2234 * the TCAM to ignore the corresponding bit in key. 2235 * Access: RW 2236 */ 2237 MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80, 2238 MLXSW_REG_PTCE2_FLEX_KEY_BLOCKS_LEN); 2239 2240 /* reg_ptce2_flex_action_set 2241 * ACL action set. 2242 * Access: RW 2243 */ 2244 MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0, 2245 MLXSW_REG_FLEX_ACTION_SET_LEN); 2246 2247 static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid, 2248 enum mlxsw_reg_ptce2_op op, 2249 const char *tcam_region_info, 2250 u16 offset) 2251 { 2252 MLXSW_REG_ZERO(ptce2, payload); 2253 mlxsw_reg_ptce2_v_set(payload, valid); 2254 mlxsw_reg_ptce2_op_set(payload, op); 2255 mlxsw_reg_ptce2_offset_set(payload, offset); 2256 mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info); 2257 } 2258 2259 /* QPCR - QoS Policer Configuration Register 2260 * ----------------------------------------- 2261 * The QPCR register is used to create policers - that limit 2262 * the rate of bytes or packets via some trap group. 2263 */ 2264 #define MLXSW_REG_QPCR_ID 0x4004 2265 #define MLXSW_REG_QPCR_LEN 0x28 2266 2267 MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN); 2268 2269 enum mlxsw_reg_qpcr_g { 2270 MLXSW_REG_QPCR_G_GLOBAL = 2, 2271 MLXSW_REG_QPCR_G_STORM_CONTROL = 3, 2272 }; 2273 2274 /* reg_qpcr_g 2275 * The policer type. 2276 * Access: Index 2277 */ 2278 MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2); 2279 2280 /* reg_qpcr_pid 2281 * Policer ID. 2282 * Access: Index 2283 */ 2284 MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14); 2285 2286 /* reg_qpcr_color_aware 2287 * Is the policer aware of colors. 2288 * Must be 0 (unaware) for cpu port. 2289 * Access: RW for unbounded policer. RO for bounded policer. 2290 */ 2291 MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1); 2292 2293 /* reg_qpcr_bytes 2294 * Is policer limit is for bytes per sec or packets per sec. 2295 * 0 - packets 2296 * 1 - bytes 2297 * Access: RW for unbounded policer. RO for bounded policer. 2298 */ 2299 MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1); 2300 2301 enum mlxsw_reg_qpcr_ir_units { 2302 MLXSW_REG_QPCR_IR_UNITS_M, 2303 MLXSW_REG_QPCR_IR_UNITS_K, 2304 }; 2305 2306 /* reg_qpcr_ir_units 2307 * Policer's units for cir and eir fields (for bytes limits only) 2308 * 1 - 10^3 2309 * 0 - 10^6 2310 * Access: OP 2311 */ 2312 MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1); 2313 2314 enum mlxsw_reg_qpcr_rate_type { 2315 MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1, 2316 MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2, 2317 }; 2318 2319 /* reg_qpcr_rate_type 2320 * Policer can have one limit (single rate) or 2 limits with specific operation 2321 * for packets that exceed the lower rate but not the upper one. 2322 * (For cpu port must be single rate) 2323 * Access: RW for unbounded policer. RO for bounded policer. 2324 */ 2325 MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2); 2326 2327 /* reg_qpc_cbs 2328 * Policer's committed burst size. 2329 * The policer is working with time slices of 50 nano sec. By default every 2330 * slice is granted the proportionate share of the committed rate. If we want to 2331 * allow a slice to exceed that share (while still keeping the rate per sec) we 2332 * can allow burst. The burst size is between the default proportionate share 2333 * (and no lower than 8) to 32Gb. (Even though giving a number higher than the 2334 * committed rate will result in exceeding the rate). The burst size must be a 2335 * log of 2 and will be determined by 2^cbs. 2336 * Access: RW 2337 */ 2338 MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6); 2339 2340 /* reg_qpcr_cir 2341 * Policer's committed rate. 2342 * The rate used for sungle rate, the lower rate for double rate. 2343 * For bytes limits, the rate will be this value * the unit from ir_units. 2344 * (Resolution error is up to 1%). 2345 * Access: RW 2346 */ 2347 MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32); 2348 2349 /* reg_qpcr_eir 2350 * Policer's exceed rate. 2351 * The higher rate for double rate, reserved for single rate. 2352 * Lower rate for double rate policer. 2353 * For bytes limits, the rate will be this value * the unit from ir_units. 2354 * (Resolution error is up to 1%). 2355 * Access: RW 2356 */ 2357 MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32); 2358 2359 #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2 2360 2361 /* reg_qpcr_exceed_action. 2362 * What to do with packets between the 2 limits for double rate. 2363 * Access: RW for unbounded policer. RO for bounded policer. 2364 */ 2365 MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4); 2366 2367 enum mlxsw_reg_qpcr_action { 2368 /* Discard */ 2369 MLXSW_REG_QPCR_ACTION_DISCARD = 1, 2370 /* Forward and set color to red. 2371 * If the packet is intended to cpu port, it will be dropped. 2372 */ 2373 MLXSW_REG_QPCR_ACTION_FORWARD = 2, 2374 }; 2375 2376 /* reg_qpcr_violate_action 2377 * What to do with packets that cross the cir limit (for single rate) or the eir 2378 * limit (for double rate). 2379 * Access: RW for unbounded policer. RO for bounded policer. 2380 */ 2381 MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4); 2382 2383 static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid, 2384 enum mlxsw_reg_qpcr_ir_units ir_units, 2385 bool bytes, u32 cir, u16 cbs) 2386 { 2387 MLXSW_REG_ZERO(qpcr, payload); 2388 mlxsw_reg_qpcr_pid_set(payload, pid); 2389 mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL); 2390 mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE); 2391 mlxsw_reg_qpcr_violate_action_set(payload, 2392 MLXSW_REG_QPCR_ACTION_DISCARD); 2393 mlxsw_reg_qpcr_cir_set(payload, cir); 2394 mlxsw_reg_qpcr_ir_units_set(payload, ir_units); 2395 mlxsw_reg_qpcr_bytes_set(payload, bytes); 2396 mlxsw_reg_qpcr_cbs_set(payload, cbs); 2397 } 2398 2399 /* QTCT - QoS Switch Traffic Class Table 2400 * ------------------------------------- 2401 * Configures the mapping between the packet switch priority and the 2402 * traffic class on the transmit port. 2403 */ 2404 #define MLXSW_REG_QTCT_ID 0x400A 2405 #define MLXSW_REG_QTCT_LEN 0x08 2406 2407 MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN); 2408 2409 /* reg_qtct_local_port 2410 * Local port number. 2411 * Access: Index 2412 * 2413 * Note: CPU port is not supported. 2414 */ 2415 MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8); 2416 2417 /* reg_qtct_sub_port 2418 * Virtual port within the physical port. 2419 * Should be set to 0 when virtual ports are not enabled on the port. 2420 * Access: Index 2421 */ 2422 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8); 2423 2424 /* reg_qtct_switch_prio 2425 * Switch priority. 2426 * Access: Index 2427 */ 2428 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4); 2429 2430 /* reg_qtct_tclass 2431 * Traffic class. 2432 * Default values: 2433 * switch_prio 0 : tclass 1 2434 * switch_prio 1 : tclass 0 2435 * switch_prio i : tclass i, for i > 1 2436 * Access: RW 2437 */ 2438 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4); 2439 2440 static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port, 2441 u8 switch_prio, u8 tclass) 2442 { 2443 MLXSW_REG_ZERO(qtct, payload); 2444 mlxsw_reg_qtct_local_port_set(payload, local_port); 2445 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio); 2446 mlxsw_reg_qtct_tclass_set(payload, tclass); 2447 } 2448 2449 /* QEEC - QoS ETS Element Configuration Register 2450 * --------------------------------------------- 2451 * Configures the ETS elements. 2452 */ 2453 #define MLXSW_REG_QEEC_ID 0x400D 2454 #define MLXSW_REG_QEEC_LEN 0x1C 2455 2456 MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN); 2457 2458 /* reg_qeec_local_port 2459 * Local port number. 2460 * Access: Index 2461 * 2462 * Note: CPU port is supported. 2463 */ 2464 MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8); 2465 2466 enum mlxsw_reg_qeec_hr { 2467 MLXSW_REG_QEEC_HIERARCY_PORT, 2468 MLXSW_REG_QEEC_HIERARCY_GROUP, 2469 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, 2470 MLXSW_REG_QEEC_HIERARCY_TC, 2471 }; 2472 2473 /* reg_qeec_element_hierarchy 2474 * 0 - Port 2475 * 1 - Group 2476 * 2 - Subgroup 2477 * 3 - Traffic Class 2478 * Access: Index 2479 */ 2480 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4); 2481 2482 /* reg_qeec_element_index 2483 * The index of the element in the hierarchy. 2484 * Access: Index 2485 */ 2486 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8); 2487 2488 /* reg_qeec_next_element_index 2489 * The index of the next (lower) element in the hierarchy. 2490 * Access: RW 2491 * 2492 * Note: Reserved for element_hierarchy 0. 2493 */ 2494 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8); 2495 2496 enum { 2497 MLXSW_REG_QEEC_BYTES_MODE, 2498 MLXSW_REG_QEEC_PACKETS_MODE, 2499 }; 2500 2501 /* reg_qeec_pb 2502 * Packets or bytes mode. 2503 * 0 - Bytes mode 2504 * 1 - Packets mode 2505 * Access: RW 2506 * 2507 * Note: Used for max shaper configuration. For Spectrum, packets mode 2508 * is supported only for traffic classes of CPU port. 2509 */ 2510 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1); 2511 2512 /* reg_qeec_mase 2513 * Max shaper configuration enable. Enables configuration of the max 2514 * shaper on this ETS element. 2515 * 0 - Disable 2516 * 1 - Enable 2517 * Access: RW 2518 */ 2519 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1); 2520 2521 /* A large max rate will disable the max shaper. */ 2522 #define MLXSW_REG_QEEC_MAS_DIS 200000000 /* Kbps */ 2523 2524 /* reg_qeec_max_shaper_rate 2525 * Max shaper information rate. 2526 * For CPU port, can only be configured for port hierarchy. 2527 * When in bytes mode, value is specified in units of 1000bps. 2528 * Access: RW 2529 */ 2530 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 28); 2531 2532 /* reg_qeec_de 2533 * DWRR configuration enable. Enables configuration of the dwrr and 2534 * dwrr_weight. 2535 * 0 - Disable 2536 * 1 - Enable 2537 * Access: RW 2538 */ 2539 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1); 2540 2541 /* reg_qeec_dwrr 2542 * Transmission selection algorithm to use on the link going down from 2543 * the ETS element. 2544 * 0 - Strict priority 2545 * 1 - DWRR 2546 * Access: RW 2547 */ 2548 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1); 2549 2550 /* reg_qeec_dwrr_weight 2551 * DWRR weight on the link going down from the ETS element. The 2552 * percentage of bandwidth guaranteed to an ETS element within 2553 * its hierarchy. The sum of all weights across all ETS elements 2554 * within one hierarchy should be equal to 100. Reserved when 2555 * transmission selection algorithm is strict priority. 2556 * Access: RW 2557 */ 2558 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8); 2559 2560 static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port, 2561 enum mlxsw_reg_qeec_hr hr, u8 index, 2562 u8 next_index) 2563 { 2564 MLXSW_REG_ZERO(qeec, payload); 2565 mlxsw_reg_qeec_local_port_set(payload, local_port); 2566 mlxsw_reg_qeec_element_hierarchy_set(payload, hr); 2567 mlxsw_reg_qeec_element_index_set(payload, index); 2568 mlxsw_reg_qeec_next_element_index_set(payload, next_index); 2569 } 2570 2571 /* PMLP - Ports Module to Local Port Register 2572 * ------------------------------------------ 2573 * Configures the assignment of modules to local ports. 2574 */ 2575 #define MLXSW_REG_PMLP_ID 0x5002 2576 #define MLXSW_REG_PMLP_LEN 0x40 2577 2578 MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN); 2579 2580 /* reg_pmlp_rxtx 2581 * 0 - Tx value is used for both Tx and Rx. 2582 * 1 - Rx value is taken from a separte field. 2583 * Access: RW 2584 */ 2585 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1); 2586 2587 /* reg_pmlp_local_port 2588 * Local port number. 2589 * Access: Index 2590 */ 2591 MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8); 2592 2593 /* reg_pmlp_width 2594 * 0 - Unmap local port. 2595 * 1 - Lane 0 is used. 2596 * 2 - Lanes 0 and 1 are used. 2597 * 4 - Lanes 0, 1, 2 and 3 are used. 2598 * Access: RW 2599 */ 2600 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8); 2601 2602 /* reg_pmlp_module 2603 * Module number. 2604 * Access: RW 2605 */ 2606 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false); 2607 2608 /* reg_pmlp_tx_lane 2609 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well. 2610 * Access: RW 2611 */ 2612 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 0x00, false); 2613 2614 /* reg_pmlp_rx_lane 2615 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is 2616 * equal to Tx lane. 2617 * Access: RW 2618 */ 2619 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 0x00, false); 2620 2621 static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port) 2622 { 2623 MLXSW_REG_ZERO(pmlp, payload); 2624 mlxsw_reg_pmlp_local_port_set(payload, local_port); 2625 } 2626 2627 /* PMTU - Port MTU Register 2628 * ------------------------ 2629 * Configures and reports the port MTU. 2630 */ 2631 #define MLXSW_REG_PMTU_ID 0x5003 2632 #define MLXSW_REG_PMTU_LEN 0x10 2633 2634 MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN); 2635 2636 /* reg_pmtu_local_port 2637 * Local port number. 2638 * Access: Index 2639 */ 2640 MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8); 2641 2642 /* reg_pmtu_max_mtu 2643 * Maximum MTU. 2644 * When port type (e.g. Ethernet) is configured, the relevant MTU is 2645 * reported, otherwise the minimum between the max_mtu of the different 2646 * types is reported. 2647 * Access: RO 2648 */ 2649 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16); 2650 2651 /* reg_pmtu_admin_mtu 2652 * MTU value to set port to. Must be smaller or equal to max_mtu. 2653 * Note: If port type is Infiniband, then port must be disabled, when its 2654 * MTU is set. 2655 * Access: RW 2656 */ 2657 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16); 2658 2659 /* reg_pmtu_oper_mtu 2660 * The actual MTU configured on the port. Packets exceeding this size 2661 * will be dropped. 2662 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband 2663 * oper_mtu might be smaller than admin_mtu. 2664 * Access: RO 2665 */ 2666 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16); 2667 2668 static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port, 2669 u16 new_mtu) 2670 { 2671 MLXSW_REG_ZERO(pmtu, payload); 2672 mlxsw_reg_pmtu_local_port_set(payload, local_port); 2673 mlxsw_reg_pmtu_max_mtu_set(payload, 0); 2674 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu); 2675 mlxsw_reg_pmtu_oper_mtu_set(payload, 0); 2676 } 2677 2678 /* PTYS - Port Type and Speed Register 2679 * ----------------------------------- 2680 * Configures and reports the port speed type. 2681 * 2682 * Note: When set while the link is up, the changes will not take effect 2683 * until the port transitions from down to up state. 2684 */ 2685 #define MLXSW_REG_PTYS_ID 0x5004 2686 #define MLXSW_REG_PTYS_LEN 0x40 2687 2688 MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN); 2689 2690 /* reg_ptys_local_port 2691 * Local port number. 2692 * Access: Index 2693 */ 2694 MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8); 2695 2696 #define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0) 2697 #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2) 2698 2699 /* reg_ptys_proto_mask 2700 * Protocol mask. Indicates which protocol is used. 2701 * 0 - Infiniband. 2702 * 1 - Fibre Channel. 2703 * 2 - Ethernet. 2704 * Access: Index 2705 */ 2706 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3); 2707 2708 enum { 2709 MLXSW_REG_PTYS_AN_STATUS_NA, 2710 MLXSW_REG_PTYS_AN_STATUS_OK, 2711 MLXSW_REG_PTYS_AN_STATUS_FAIL, 2712 }; 2713 2714 /* reg_ptys_an_status 2715 * Autonegotiation status. 2716 * Access: RO 2717 */ 2718 MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4); 2719 2720 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0) 2721 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1) 2722 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2) 2723 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3) 2724 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4) 2725 #define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2 BIT(5) 2726 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6) 2727 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7) 2728 #define MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4 BIT(8) 2729 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12) 2730 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13) 2731 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14) 2732 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15) 2733 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16) 2734 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18) 2735 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19) 2736 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20) 2737 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21) 2738 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22) 2739 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23) 2740 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX BIT(24) 2741 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(25) 2742 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T BIT(26) 2743 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27) 2744 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28) 2745 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29) 2746 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30) 2747 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31) 2748 2749 /* reg_ptys_eth_proto_cap 2750 * Ethernet port supported speeds and protocols. 2751 * Access: RO 2752 */ 2753 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32); 2754 2755 /* reg_ptys_ib_link_width_cap 2756 * IB port supported widths. 2757 * Access: RO 2758 */ 2759 MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16); 2760 2761 #define MLXSW_REG_PTYS_IB_SPEED_SDR BIT(0) 2762 #define MLXSW_REG_PTYS_IB_SPEED_DDR BIT(1) 2763 #define MLXSW_REG_PTYS_IB_SPEED_QDR BIT(2) 2764 #define MLXSW_REG_PTYS_IB_SPEED_FDR10 BIT(3) 2765 #define MLXSW_REG_PTYS_IB_SPEED_FDR BIT(4) 2766 #define MLXSW_REG_PTYS_IB_SPEED_EDR BIT(5) 2767 2768 /* reg_ptys_ib_proto_cap 2769 * IB port supported speeds and protocols. 2770 * Access: RO 2771 */ 2772 MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16); 2773 2774 /* reg_ptys_eth_proto_admin 2775 * Speed and protocol to set port to. 2776 * Access: RW 2777 */ 2778 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32); 2779 2780 /* reg_ptys_ib_link_width_admin 2781 * IB width to set port to. 2782 * Access: RW 2783 */ 2784 MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16); 2785 2786 /* reg_ptys_ib_proto_admin 2787 * IB speeds and protocols to set port to. 2788 * Access: RW 2789 */ 2790 MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16); 2791 2792 /* reg_ptys_eth_proto_oper 2793 * The current speed and protocol configured for the port. 2794 * Access: RO 2795 */ 2796 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32); 2797 2798 /* reg_ptys_ib_link_width_oper 2799 * The current IB width to set port to. 2800 * Access: RO 2801 */ 2802 MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16); 2803 2804 /* reg_ptys_ib_proto_oper 2805 * The current IB speed and protocol. 2806 * Access: RO 2807 */ 2808 MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16); 2809 2810 /* reg_ptys_eth_proto_lp_advertise 2811 * The protocols that were advertised by the link partner during 2812 * autonegotiation. 2813 * Access: RO 2814 */ 2815 MLXSW_ITEM32(reg, ptys, eth_proto_lp_advertise, 0x30, 0, 32); 2816 2817 static inline void mlxsw_reg_ptys_eth_pack(char *payload, u8 local_port, 2818 u32 proto_admin) 2819 { 2820 MLXSW_REG_ZERO(ptys, payload); 2821 mlxsw_reg_ptys_local_port_set(payload, local_port); 2822 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 2823 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin); 2824 } 2825 2826 static inline void mlxsw_reg_ptys_eth_unpack(char *payload, 2827 u32 *p_eth_proto_cap, 2828 u32 *p_eth_proto_adm, 2829 u32 *p_eth_proto_oper) 2830 { 2831 if (p_eth_proto_cap) 2832 *p_eth_proto_cap = mlxsw_reg_ptys_eth_proto_cap_get(payload); 2833 if (p_eth_proto_adm) 2834 *p_eth_proto_adm = mlxsw_reg_ptys_eth_proto_admin_get(payload); 2835 if (p_eth_proto_oper) 2836 *p_eth_proto_oper = mlxsw_reg_ptys_eth_proto_oper_get(payload); 2837 } 2838 2839 static inline void mlxsw_reg_ptys_ib_pack(char *payload, u8 local_port, 2840 u16 proto_admin, u16 link_width) 2841 { 2842 MLXSW_REG_ZERO(ptys, payload); 2843 mlxsw_reg_ptys_local_port_set(payload, local_port); 2844 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB); 2845 mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin); 2846 mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width); 2847 } 2848 2849 static inline void mlxsw_reg_ptys_ib_unpack(char *payload, u16 *p_ib_proto_cap, 2850 u16 *p_ib_link_width_cap, 2851 u16 *p_ib_proto_oper, 2852 u16 *p_ib_link_width_oper) 2853 { 2854 if (p_ib_proto_cap) 2855 *p_ib_proto_cap = mlxsw_reg_ptys_ib_proto_cap_get(payload); 2856 if (p_ib_link_width_cap) 2857 *p_ib_link_width_cap = 2858 mlxsw_reg_ptys_ib_link_width_cap_get(payload); 2859 if (p_ib_proto_oper) 2860 *p_ib_proto_oper = mlxsw_reg_ptys_ib_proto_oper_get(payload); 2861 if (p_ib_link_width_oper) 2862 *p_ib_link_width_oper = 2863 mlxsw_reg_ptys_ib_link_width_oper_get(payload); 2864 } 2865 2866 /* PPAD - Port Physical Address Register 2867 * ------------------------------------- 2868 * The PPAD register configures the per port physical MAC address. 2869 */ 2870 #define MLXSW_REG_PPAD_ID 0x5005 2871 #define MLXSW_REG_PPAD_LEN 0x10 2872 2873 MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN); 2874 2875 /* reg_ppad_single_base_mac 2876 * 0: base_mac, local port should be 0 and mac[7:0] is 2877 * reserved. HW will set incremental 2878 * 1: single_mac - mac of the local_port 2879 * Access: RW 2880 */ 2881 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1); 2882 2883 /* reg_ppad_local_port 2884 * port number, if single_base_mac = 0 then local_port is reserved 2885 * Access: RW 2886 */ 2887 MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8); 2888 2889 /* reg_ppad_mac 2890 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved. 2891 * If single_base_mac = 1 - the per port MAC address 2892 * Access: RW 2893 */ 2894 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6); 2895 2896 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac, 2897 u8 local_port) 2898 { 2899 MLXSW_REG_ZERO(ppad, payload); 2900 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac); 2901 mlxsw_reg_ppad_local_port_set(payload, local_port); 2902 } 2903 2904 /* PAOS - Ports Administrative and Operational Status Register 2905 * ----------------------------------------------------------- 2906 * Configures and retrieves per port administrative and operational status. 2907 */ 2908 #define MLXSW_REG_PAOS_ID 0x5006 2909 #define MLXSW_REG_PAOS_LEN 0x10 2910 2911 MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN); 2912 2913 /* reg_paos_swid 2914 * Switch partition ID with which to associate the port. 2915 * Note: while external ports uses unique local port numbers (and thus swid is 2916 * redundant), router ports use the same local port number where swid is the 2917 * only indication for the relevant port. 2918 * Access: Index 2919 */ 2920 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8); 2921 2922 /* reg_paos_local_port 2923 * Local port number. 2924 * Access: Index 2925 */ 2926 MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8); 2927 2928 /* reg_paos_admin_status 2929 * Port administrative state (the desired state of the port): 2930 * 1 - Up. 2931 * 2 - Down. 2932 * 3 - Up once. This means that in case of link failure, the port won't go 2933 * into polling mode, but will wait to be re-enabled by software. 2934 * 4 - Disabled by system. Can only be set by hardware. 2935 * Access: RW 2936 */ 2937 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4); 2938 2939 /* reg_paos_oper_status 2940 * Port operational state (the current state): 2941 * 1 - Up. 2942 * 2 - Down. 2943 * 3 - Down by port failure. This means that the device will not let the 2944 * port up again until explicitly specified by software. 2945 * Access: RO 2946 */ 2947 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4); 2948 2949 /* reg_paos_ase 2950 * Admin state update enabled. 2951 * Access: WO 2952 */ 2953 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1); 2954 2955 /* reg_paos_ee 2956 * Event update enable. If this bit is set, event generation will be 2957 * updated based on the e field. 2958 * Access: WO 2959 */ 2960 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1); 2961 2962 /* reg_paos_e 2963 * Event generation on operational state change: 2964 * 0 - Do not generate event. 2965 * 1 - Generate Event. 2966 * 2 - Generate Single Event. 2967 * Access: RW 2968 */ 2969 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2); 2970 2971 static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port, 2972 enum mlxsw_port_admin_status status) 2973 { 2974 MLXSW_REG_ZERO(paos, payload); 2975 mlxsw_reg_paos_swid_set(payload, 0); 2976 mlxsw_reg_paos_local_port_set(payload, local_port); 2977 mlxsw_reg_paos_admin_status_set(payload, status); 2978 mlxsw_reg_paos_oper_status_set(payload, 0); 2979 mlxsw_reg_paos_ase_set(payload, 1); 2980 mlxsw_reg_paos_ee_set(payload, 1); 2981 mlxsw_reg_paos_e_set(payload, 1); 2982 } 2983 2984 /* PFCC - Ports Flow Control Configuration Register 2985 * ------------------------------------------------ 2986 * Configures and retrieves the per port flow control configuration. 2987 */ 2988 #define MLXSW_REG_PFCC_ID 0x5007 2989 #define MLXSW_REG_PFCC_LEN 0x20 2990 2991 MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN); 2992 2993 /* reg_pfcc_local_port 2994 * Local port number. 2995 * Access: Index 2996 */ 2997 MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8); 2998 2999 /* reg_pfcc_pnat 3000 * Port number access type. Determines the way local_port is interpreted: 3001 * 0 - Local port number. 3002 * 1 - IB / label port number. 3003 * Access: Index 3004 */ 3005 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2); 3006 3007 /* reg_pfcc_shl_cap 3008 * Send to higher layers capabilities: 3009 * 0 - No capability of sending Pause and PFC frames to higher layers. 3010 * 1 - Device has capability of sending Pause and PFC frames to higher 3011 * layers. 3012 * Access: RO 3013 */ 3014 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1); 3015 3016 /* reg_pfcc_shl_opr 3017 * Send to higher layers operation: 3018 * 0 - Pause and PFC frames are handled by the port (default). 3019 * 1 - Pause and PFC frames are handled by the port and also sent to 3020 * higher layers. Only valid if shl_cap = 1. 3021 * Access: RW 3022 */ 3023 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1); 3024 3025 /* reg_pfcc_ppan 3026 * Pause policy auto negotiation. 3027 * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx. 3028 * 1 - Enabled. When auto-negotiation is performed, set the Pause policy 3029 * based on the auto-negotiation resolution. 3030 * Access: RW 3031 * 3032 * Note: The auto-negotiation advertisement is set according to pptx and 3033 * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0. 3034 */ 3035 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4); 3036 3037 /* reg_pfcc_prio_mask_tx 3038 * Bit per priority indicating if Tx flow control policy should be 3039 * updated based on bit pfctx. 3040 * Access: WO 3041 */ 3042 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8); 3043 3044 /* reg_pfcc_prio_mask_rx 3045 * Bit per priority indicating if Rx flow control policy should be 3046 * updated based on bit pfcrx. 3047 * Access: WO 3048 */ 3049 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8); 3050 3051 /* reg_pfcc_pptx 3052 * Admin Pause policy on Tx. 3053 * 0 - Never generate Pause frames (default). 3054 * 1 - Generate Pause frames according to Rx buffer threshold. 3055 * Access: RW 3056 */ 3057 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1); 3058 3059 /* reg_pfcc_aptx 3060 * Active (operational) Pause policy on Tx. 3061 * 0 - Never generate Pause frames. 3062 * 1 - Generate Pause frames according to Rx buffer threshold. 3063 * Access: RO 3064 */ 3065 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1); 3066 3067 /* reg_pfcc_pfctx 3068 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask: 3069 * 0 - Never generate priority Pause frames on the specified priority 3070 * (default). 3071 * 1 - Generate priority Pause frames according to Rx buffer threshold on 3072 * the specified priority. 3073 * Access: RW 3074 * 3075 * Note: pfctx and pptx must be mutually exclusive. 3076 */ 3077 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8); 3078 3079 /* reg_pfcc_pprx 3080 * Admin Pause policy on Rx. 3081 * 0 - Ignore received Pause frames (default). 3082 * 1 - Respect received Pause frames. 3083 * Access: RW 3084 */ 3085 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1); 3086 3087 /* reg_pfcc_aprx 3088 * Active (operational) Pause policy on Rx. 3089 * 0 - Ignore received Pause frames. 3090 * 1 - Respect received Pause frames. 3091 * Access: RO 3092 */ 3093 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1); 3094 3095 /* reg_pfcc_pfcrx 3096 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask: 3097 * 0 - Ignore incoming priority Pause frames on the specified priority 3098 * (default). 3099 * 1 - Respect incoming priority Pause frames on the specified priority. 3100 * Access: RW 3101 */ 3102 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8); 3103 3104 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF 3105 3106 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en) 3107 { 3108 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 3109 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 3110 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en); 3111 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en); 3112 } 3113 3114 static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port) 3115 { 3116 MLXSW_REG_ZERO(pfcc, payload); 3117 mlxsw_reg_pfcc_local_port_set(payload, local_port); 3118 } 3119 3120 /* PPCNT - Ports Performance Counters Register 3121 * ------------------------------------------- 3122 * The PPCNT register retrieves per port performance counters. 3123 */ 3124 #define MLXSW_REG_PPCNT_ID 0x5008 3125 #define MLXSW_REG_PPCNT_LEN 0x100 3126 3127 MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN); 3128 3129 /* reg_ppcnt_swid 3130 * For HCA: must be always 0. 3131 * Switch partition ID to associate port with. 3132 * Switch partitions are numbered from 0 to 7 inclusively. 3133 * Switch partition 254 indicates stacking ports. 3134 * Switch partition 255 indicates all switch partitions. 3135 * Only valid on Set() operation with local_port=255. 3136 * Access: Index 3137 */ 3138 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8); 3139 3140 /* reg_ppcnt_local_port 3141 * Local port number. 3142 * 255 indicates all ports on the device, and is only allowed 3143 * for Set() operation. 3144 * Access: Index 3145 */ 3146 MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8); 3147 3148 /* reg_ppcnt_pnat 3149 * Port number access type: 3150 * 0 - Local port number 3151 * 1 - IB port number 3152 * Access: Index 3153 */ 3154 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2); 3155 3156 enum mlxsw_reg_ppcnt_grp { 3157 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0, 3158 MLXSW_REG_PPCNT_PRIO_CNT = 0x10, 3159 MLXSW_REG_PPCNT_TC_CNT = 0x11, 3160 }; 3161 3162 /* reg_ppcnt_grp 3163 * Performance counter group. 3164 * Group 63 indicates all groups. Only valid on Set() operation with 3165 * clr bit set. 3166 * 0x0: IEEE 802.3 Counters 3167 * 0x1: RFC 2863 Counters 3168 * 0x2: RFC 2819 Counters 3169 * 0x3: RFC 3635 Counters 3170 * 0x5: Ethernet Extended Counters 3171 * 0x8: Link Level Retransmission Counters 3172 * 0x10: Per Priority Counters 3173 * 0x11: Per Traffic Class Counters 3174 * 0x12: Physical Layer Counters 3175 * Access: Index 3176 */ 3177 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6); 3178 3179 /* reg_ppcnt_clr 3180 * Clear counters. Setting the clr bit will reset the counter value 3181 * for all counters in the counter group. This bit can be set 3182 * for both Set() and Get() operation. 3183 * Access: OP 3184 */ 3185 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1); 3186 3187 /* reg_ppcnt_prio_tc 3188 * Priority for counter set that support per priority, valid values: 0-7. 3189 * Traffic class for counter set that support per traffic class, 3190 * valid values: 0- cap_max_tclass-1 . 3191 * For HCA: cap_max_tclass is always 8. 3192 * Otherwise must be 0. 3193 * Access: Index 3194 */ 3195 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5); 3196 3197 /* Ethernet IEEE 802.3 Counter Group */ 3198 3199 /* reg_ppcnt_a_frames_transmitted_ok 3200 * Access: RO 3201 */ 3202 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok, 3203 0x08 + 0x00, 0, 64); 3204 3205 /* reg_ppcnt_a_frames_received_ok 3206 * Access: RO 3207 */ 3208 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok, 3209 0x08 + 0x08, 0, 64); 3210 3211 /* reg_ppcnt_a_frame_check_sequence_errors 3212 * Access: RO 3213 */ 3214 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors, 3215 0x08 + 0x10, 0, 64); 3216 3217 /* reg_ppcnt_a_alignment_errors 3218 * Access: RO 3219 */ 3220 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors, 3221 0x08 + 0x18, 0, 64); 3222 3223 /* reg_ppcnt_a_octets_transmitted_ok 3224 * Access: RO 3225 */ 3226 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok, 3227 0x08 + 0x20, 0, 64); 3228 3229 /* reg_ppcnt_a_octets_received_ok 3230 * Access: RO 3231 */ 3232 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok, 3233 0x08 + 0x28, 0, 64); 3234 3235 /* reg_ppcnt_a_multicast_frames_xmitted_ok 3236 * Access: RO 3237 */ 3238 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok, 3239 0x08 + 0x30, 0, 64); 3240 3241 /* reg_ppcnt_a_broadcast_frames_xmitted_ok 3242 * Access: RO 3243 */ 3244 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok, 3245 0x08 + 0x38, 0, 64); 3246 3247 /* reg_ppcnt_a_multicast_frames_received_ok 3248 * Access: RO 3249 */ 3250 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok, 3251 0x08 + 0x40, 0, 64); 3252 3253 /* reg_ppcnt_a_broadcast_frames_received_ok 3254 * Access: RO 3255 */ 3256 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok, 3257 0x08 + 0x48, 0, 64); 3258 3259 /* reg_ppcnt_a_in_range_length_errors 3260 * Access: RO 3261 */ 3262 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors, 3263 0x08 + 0x50, 0, 64); 3264 3265 /* reg_ppcnt_a_out_of_range_length_field 3266 * Access: RO 3267 */ 3268 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field, 3269 0x08 + 0x58, 0, 64); 3270 3271 /* reg_ppcnt_a_frame_too_long_errors 3272 * Access: RO 3273 */ 3274 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors, 3275 0x08 + 0x60, 0, 64); 3276 3277 /* reg_ppcnt_a_symbol_error_during_carrier 3278 * Access: RO 3279 */ 3280 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier, 3281 0x08 + 0x68, 0, 64); 3282 3283 /* reg_ppcnt_a_mac_control_frames_transmitted 3284 * Access: RO 3285 */ 3286 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted, 3287 0x08 + 0x70, 0, 64); 3288 3289 /* reg_ppcnt_a_mac_control_frames_received 3290 * Access: RO 3291 */ 3292 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received, 3293 0x08 + 0x78, 0, 64); 3294 3295 /* reg_ppcnt_a_unsupported_opcodes_received 3296 * Access: RO 3297 */ 3298 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received, 3299 0x08 + 0x80, 0, 64); 3300 3301 /* reg_ppcnt_a_pause_mac_ctrl_frames_received 3302 * Access: RO 3303 */ 3304 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received, 3305 0x08 + 0x88, 0, 64); 3306 3307 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted 3308 * Access: RO 3309 */ 3310 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted, 3311 0x08 + 0x90, 0, 64); 3312 3313 /* Ethernet Per Priority Group Counters */ 3314 3315 /* reg_ppcnt_rx_octets 3316 * Access: RO 3317 */ 3318 MLXSW_ITEM64(reg, ppcnt, rx_octets, 0x08 + 0x00, 0, 64); 3319 3320 /* reg_ppcnt_rx_frames 3321 * Access: RO 3322 */ 3323 MLXSW_ITEM64(reg, ppcnt, rx_frames, 0x08 + 0x20, 0, 64); 3324 3325 /* reg_ppcnt_tx_octets 3326 * Access: RO 3327 */ 3328 MLXSW_ITEM64(reg, ppcnt, tx_octets, 0x08 + 0x28, 0, 64); 3329 3330 /* reg_ppcnt_tx_frames 3331 * Access: RO 3332 */ 3333 MLXSW_ITEM64(reg, ppcnt, tx_frames, 0x08 + 0x48, 0, 64); 3334 3335 /* reg_ppcnt_rx_pause 3336 * Access: RO 3337 */ 3338 MLXSW_ITEM64(reg, ppcnt, rx_pause, 0x08 + 0x50, 0, 64); 3339 3340 /* reg_ppcnt_rx_pause_duration 3341 * Access: RO 3342 */ 3343 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration, 0x08 + 0x58, 0, 64); 3344 3345 /* reg_ppcnt_tx_pause 3346 * Access: RO 3347 */ 3348 MLXSW_ITEM64(reg, ppcnt, tx_pause, 0x08 + 0x60, 0, 64); 3349 3350 /* reg_ppcnt_tx_pause_duration 3351 * Access: RO 3352 */ 3353 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration, 0x08 + 0x68, 0, 64); 3354 3355 /* reg_ppcnt_rx_pause_transition 3356 * Access: RO 3357 */ 3358 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition, 0x08 + 0x70, 0, 64); 3359 3360 /* Ethernet Per Traffic Group Counters */ 3361 3362 /* reg_ppcnt_tc_transmit_queue 3363 * Contains the transmit queue depth in cells of traffic class 3364 * selected by prio_tc and the port selected by local_port. 3365 * The field cannot be cleared. 3366 * Access: RO 3367 */ 3368 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue, 0x08 + 0x00, 0, 64); 3369 3370 /* reg_ppcnt_tc_no_buffer_discard_uc 3371 * The number of unicast packets dropped due to lack of shared 3372 * buffer resources. 3373 * Access: RO 3374 */ 3375 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc, 0x08 + 0x08, 0, 64); 3376 3377 static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port, 3378 enum mlxsw_reg_ppcnt_grp grp, 3379 u8 prio_tc) 3380 { 3381 MLXSW_REG_ZERO(ppcnt, payload); 3382 mlxsw_reg_ppcnt_swid_set(payload, 0); 3383 mlxsw_reg_ppcnt_local_port_set(payload, local_port); 3384 mlxsw_reg_ppcnt_pnat_set(payload, 0); 3385 mlxsw_reg_ppcnt_grp_set(payload, grp); 3386 mlxsw_reg_ppcnt_clr_set(payload, 0); 3387 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc); 3388 } 3389 3390 /* PLIB - Port Local to InfiniBand Port 3391 * ------------------------------------ 3392 * The PLIB register performs mapping from Local Port into InfiniBand Port. 3393 */ 3394 #define MLXSW_REG_PLIB_ID 0x500A 3395 #define MLXSW_REG_PLIB_LEN 0x10 3396 3397 MLXSW_REG_DEFINE(plib, MLXSW_REG_PLIB_ID, MLXSW_REG_PLIB_LEN); 3398 3399 /* reg_plib_local_port 3400 * Local port number. 3401 * Access: Index 3402 */ 3403 MLXSW_ITEM32(reg, plib, local_port, 0x00, 16, 8); 3404 3405 /* reg_plib_ib_port 3406 * InfiniBand port remapping for local_port. 3407 * Access: RW 3408 */ 3409 MLXSW_ITEM32(reg, plib, ib_port, 0x00, 0, 8); 3410 3411 /* PPTB - Port Prio To Buffer Register 3412 * ----------------------------------- 3413 * Configures the switch priority to buffer table. 3414 */ 3415 #define MLXSW_REG_PPTB_ID 0x500B 3416 #define MLXSW_REG_PPTB_LEN 0x10 3417 3418 MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN); 3419 3420 enum { 3421 MLXSW_REG_PPTB_MM_UM, 3422 MLXSW_REG_PPTB_MM_UNICAST, 3423 MLXSW_REG_PPTB_MM_MULTICAST, 3424 }; 3425 3426 /* reg_pptb_mm 3427 * Mapping mode. 3428 * 0 - Map both unicast and multicast packets to the same buffer. 3429 * 1 - Map only unicast packets. 3430 * 2 - Map only multicast packets. 3431 * Access: Index 3432 * 3433 * Note: SwitchX-2 only supports the first option. 3434 */ 3435 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2); 3436 3437 /* reg_pptb_local_port 3438 * Local port number. 3439 * Access: Index 3440 */ 3441 MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8); 3442 3443 /* reg_pptb_um 3444 * Enables the update of the untagged_buf field. 3445 * Access: RW 3446 */ 3447 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1); 3448 3449 /* reg_pptb_pm 3450 * Enables the update of the prio_to_buff field. 3451 * Bit <i> is a flag for updating the mapping for switch priority <i>. 3452 * Access: RW 3453 */ 3454 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8); 3455 3456 /* reg_pptb_prio_to_buff 3457 * Mapping of switch priority <i> to one of the allocated receive port 3458 * buffers. 3459 * Access: RW 3460 */ 3461 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4); 3462 3463 /* reg_pptb_pm_msb 3464 * Enables the update of the prio_to_buff field. 3465 * Bit <i> is a flag for updating the mapping for switch priority <i+8>. 3466 * Access: RW 3467 */ 3468 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8); 3469 3470 /* reg_pptb_untagged_buff 3471 * Mapping of untagged frames to one of the allocated receive port buffers. 3472 * Access: RW 3473 * 3474 * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for 3475 * Spectrum, as it maps untagged packets based on the default switch priority. 3476 */ 3477 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4); 3478 3479 /* reg_pptb_prio_to_buff_msb 3480 * Mapping of switch priority <i+8> to one of the allocated receive port 3481 * buffers. 3482 * Access: RW 3483 */ 3484 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4); 3485 3486 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF 3487 3488 static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port) 3489 { 3490 MLXSW_REG_ZERO(pptb, payload); 3491 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM); 3492 mlxsw_reg_pptb_local_port_set(payload, local_port); 3493 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 3494 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 3495 } 3496 3497 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio, 3498 u8 buff) 3499 { 3500 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff); 3501 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff); 3502 } 3503 3504 /* PBMC - Port Buffer Management Control Register 3505 * ---------------------------------------------- 3506 * The PBMC register configures and retrieves the port packet buffer 3507 * allocation for different Prios, and the Pause threshold management. 3508 */ 3509 #define MLXSW_REG_PBMC_ID 0x500C 3510 #define MLXSW_REG_PBMC_LEN 0x6C 3511 3512 MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN); 3513 3514 /* reg_pbmc_local_port 3515 * Local port number. 3516 * Access: Index 3517 */ 3518 MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8); 3519 3520 /* reg_pbmc_xoff_timer_value 3521 * When device generates a pause frame, it uses this value as the pause 3522 * timer (time for the peer port to pause in quota-512 bit time). 3523 * Access: RW 3524 */ 3525 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16); 3526 3527 /* reg_pbmc_xoff_refresh 3528 * The time before a new pause frame should be sent to refresh the pause RW 3529 * state. Using the same units as xoff_timer_value above (in quota-512 bit 3530 * time). 3531 * Access: RW 3532 */ 3533 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16); 3534 3535 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11 3536 3537 /* reg_pbmc_buf_lossy 3538 * The field indicates if the buffer is lossy. 3539 * 0 - Lossless 3540 * 1 - Lossy 3541 * Access: RW 3542 */ 3543 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false); 3544 3545 /* reg_pbmc_buf_epsb 3546 * Eligible for Port Shared buffer. 3547 * If epsb is set, packets assigned to buffer are allowed to insert the port 3548 * shared buffer. 3549 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved. 3550 * Access: RW 3551 */ 3552 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false); 3553 3554 /* reg_pbmc_buf_size 3555 * The part of the packet buffer array is allocated for the specific buffer. 3556 * Units are represented in cells. 3557 * Access: RW 3558 */ 3559 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false); 3560 3561 /* reg_pbmc_buf_xoff_threshold 3562 * Once the amount of data in the buffer goes above this value, device 3563 * starts sending PFC frames for all priorities associated with the 3564 * buffer. Units are represented in cells. Reserved in case of lossy 3565 * buffer. 3566 * Access: RW 3567 * 3568 * Note: In Spectrum, reserved for buffer[9]. 3569 */ 3570 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16, 3571 0x08, 0x04, false); 3572 3573 /* reg_pbmc_buf_xon_threshold 3574 * When the amount of data in the buffer goes below this value, device 3575 * stops sending PFC frames for the priorities associated with the 3576 * buffer. Units are represented in cells. Reserved in case of lossy 3577 * buffer. 3578 * Access: RW 3579 * 3580 * Note: In Spectrum, reserved for buffer[9]. 3581 */ 3582 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16, 3583 0x08, 0x04, false); 3584 3585 static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port, 3586 u16 xoff_timer_value, u16 xoff_refresh) 3587 { 3588 MLXSW_REG_ZERO(pbmc, payload); 3589 mlxsw_reg_pbmc_local_port_set(payload, local_port); 3590 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value); 3591 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh); 3592 } 3593 3594 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload, 3595 int buf_index, 3596 u16 size) 3597 { 3598 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1); 3599 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 3600 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 3601 } 3602 3603 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload, 3604 int buf_index, u16 size, 3605 u16 threshold) 3606 { 3607 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0); 3608 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 3609 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 3610 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold); 3611 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold); 3612 } 3613 3614 /* PSPA - Port Switch Partition Allocation 3615 * --------------------------------------- 3616 * Controls the association of a port with a switch partition and enables 3617 * configuring ports as stacking ports. 3618 */ 3619 #define MLXSW_REG_PSPA_ID 0x500D 3620 #define MLXSW_REG_PSPA_LEN 0x8 3621 3622 MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN); 3623 3624 /* reg_pspa_swid 3625 * Switch partition ID. 3626 * Access: RW 3627 */ 3628 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8); 3629 3630 /* reg_pspa_local_port 3631 * Local port number. 3632 * Access: Index 3633 */ 3634 MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8); 3635 3636 /* reg_pspa_sub_port 3637 * Virtual port within the local port. Set to 0 when virtual ports are 3638 * disabled on the local port. 3639 * Access: Index 3640 */ 3641 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8); 3642 3643 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port) 3644 { 3645 MLXSW_REG_ZERO(pspa, payload); 3646 mlxsw_reg_pspa_swid_set(payload, swid); 3647 mlxsw_reg_pspa_local_port_set(payload, local_port); 3648 mlxsw_reg_pspa_sub_port_set(payload, 0); 3649 } 3650 3651 /* HTGT - Host Trap Group Table 3652 * ---------------------------- 3653 * Configures the properties for forwarding to CPU. 3654 */ 3655 #define MLXSW_REG_HTGT_ID 0x7002 3656 #define MLXSW_REG_HTGT_LEN 0x20 3657 3658 MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN); 3659 3660 /* reg_htgt_swid 3661 * Switch partition ID. 3662 * Access: Index 3663 */ 3664 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8); 3665 3666 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */ 3667 3668 /* reg_htgt_type 3669 * CPU path type. 3670 * Access: RW 3671 */ 3672 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4); 3673 3674 enum mlxsw_reg_htgt_trap_group { 3675 MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 3676 MLXSW_REG_HTGT_TRAP_GROUP_SX2_RX, 3677 MLXSW_REG_HTGT_TRAP_GROUP_SX2_CTRL, 3678 MLXSW_REG_HTGT_TRAP_GROUP_SP_STP, 3679 MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP, 3680 MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP, 3681 MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP, 3682 MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP, 3683 MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF, 3684 MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM, 3685 MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST, 3686 MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP, 3687 MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS, 3688 MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP, 3689 MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE, 3690 MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME, 3691 MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP, 3692 MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF, 3693 MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT, 3694 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD, 3695 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND, 3696 }; 3697 3698 /* reg_htgt_trap_group 3699 * Trap group number. User defined number specifying which trap groups 3700 * should be forwarded to the CPU. The mapping between trap IDs and trap 3701 * groups is configured using HPKT register. 3702 * Access: Index 3703 */ 3704 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8); 3705 3706 enum { 3707 MLXSW_REG_HTGT_POLICER_DISABLE, 3708 MLXSW_REG_HTGT_POLICER_ENABLE, 3709 }; 3710 3711 /* reg_htgt_pide 3712 * Enable policer ID specified using 'pid' field. 3713 * Access: RW 3714 */ 3715 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1); 3716 3717 #define MLXSW_REG_HTGT_INVALID_POLICER 0xff 3718 3719 /* reg_htgt_pid 3720 * Policer ID for the trap group. 3721 * Access: RW 3722 */ 3723 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8); 3724 3725 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0 3726 3727 /* reg_htgt_mirror_action 3728 * Mirror action to use. 3729 * 0 - Trap to CPU. 3730 * 1 - Trap to CPU and mirror to a mirroring agent. 3731 * 2 - Mirror to a mirroring agent and do not trap to CPU. 3732 * Access: RW 3733 * 3734 * Note: Mirroring to a mirroring agent is only supported in Spectrum. 3735 */ 3736 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2); 3737 3738 /* reg_htgt_mirroring_agent 3739 * Mirroring agent. 3740 * Access: RW 3741 */ 3742 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3); 3743 3744 #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0 3745 3746 /* reg_htgt_priority 3747 * Trap group priority. 3748 * In case a packet matches multiple classification rules, the packet will 3749 * only be trapped once, based on the trap ID associated with the group (via 3750 * register HPKT) with the highest priority. 3751 * Supported values are 0-7, with 7 represnting the highest priority. 3752 * Access: RW 3753 * 3754 * Note: In SwitchX-2 this field is ignored and the priority value is replaced 3755 * by the 'trap_group' field. 3756 */ 3757 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4); 3758 3759 #define MLXSW_REG_HTGT_DEFAULT_TC 7 3760 3761 /* reg_htgt_local_path_cpu_tclass 3762 * CPU ingress traffic class for the trap group. 3763 * Access: RW 3764 */ 3765 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6); 3766 3767 enum mlxsw_reg_htgt_local_path_rdq { 3768 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13, 3769 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14, 3770 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15, 3771 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15, 3772 }; 3773 /* reg_htgt_local_path_rdq 3774 * Receive descriptor queue (RDQ) to use for the trap group. 3775 * Access: RW 3776 */ 3777 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6); 3778 3779 static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id, 3780 u8 priority, u8 tc) 3781 { 3782 MLXSW_REG_ZERO(htgt, payload); 3783 3784 if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) { 3785 mlxsw_reg_htgt_pide_set(payload, 3786 MLXSW_REG_HTGT_POLICER_DISABLE); 3787 } else { 3788 mlxsw_reg_htgt_pide_set(payload, 3789 MLXSW_REG_HTGT_POLICER_ENABLE); 3790 mlxsw_reg_htgt_pid_set(payload, policer_id); 3791 } 3792 3793 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL); 3794 mlxsw_reg_htgt_trap_group_set(payload, group); 3795 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU); 3796 mlxsw_reg_htgt_mirroring_agent_set(payload, 0); 3797 mlxsw_reg_htgt_priority_set(payload, priority); 3798 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc); 3799 mlxsw_reg_htgt_local_path_rdq_set(payload, group); 3800 } 3801 3802 /* HPKT - Host Packet Trap 3803 * ----------------------- 3804 * Configures trap IDs inside trap groups. 3805 */ 3806 #define MLXSW_REG_HPKT_ID 0x7003 3807 #define MLXSW_REG_HPKT_LEN 0x10 3808 3809 MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN); 3810 3811 enum { 3812 MLXSW_REG_HPKT_ACK_NOT_REQUIRED, 3813 MLXSW_REG_HPKT_ACK_REQUIRED, 3814 }; 3815 3816 /* reg_hpkt_ack 3817 * Require acknowledgements from the host for events. 3818 * If set, then the device will wait for the event it sent to be acknowledged 3819 * by the host. This option is only relevant for event trap IDs. 3820 * Access: RW 3821 * 3822 * Note: Currently not supported by firmware. 3823 */ 3824 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1); 3825 3826 enum mlxsw_reg_hpkt_action { 3827 MLXSW_REG_HPKT_ACTION_FORWARD, 3828 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU, 3829 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU, 3830 MLXSW_REG_HPKT_ACTION_DISCARD, 3831 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD, 3832 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD, 3833 }; 3834 3835 /* reg_hpkt_action 3836 * Action to perform on packet when trapped. 3837 * 0 - No action. Forward to CPU based on switching rules. 3838 * 1 - Trap to CPU (CPU receives sole copy). 3839 * 2 - Mirror to CPU (CPU receives a replica of the packet). 3840 * 3 - Discard. 3841 * 4 - Soft discard (allow other traps to act on the packet). 3842 * 5 - Trap and soft discard (allow other traps to overwrite this trap). 3843 * Access: RW 3844 * 3845 * Note: Must be set to 0 (forward) for event trap IDs, as they are already 3846 * addressed to the CPU. 3847 */ 3848 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3); 3849 3850 /* reg_hpkt_trap_group 3851 * Trap group to associate the trap with. 3852 * Access: RW 3853 */ 3854 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6); 3855 3856 /* reg_hpkt_trap_id 3857 * Trap ID. 3858 * Access: Index 3859 * 3860 * Note: A trap ID can only be associated with a single trap group. The device 3861 * will associate the trap ID with the last trap group configured. 3862 */ 3863 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9); 3864 3865 enum { 3866 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT, 3867 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER, 3868 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER, 3869 }; 3870 3871 /* reg_hpkt_ctrl 3872 * Configure dedicated buffer resources for control packets. 3873 * Ignored by SwitchX-2. 3874 * 0 - Keep factory defaults. 3875 * 1 - Do not use control buffer for this trap ID. 3876 * 2 - Use control buffer for this trap ID. 3877 * Access: RW 3878 */ 3879 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2); 3880 3881 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id, 3882 enum mlxsw_reg_htgt_trap_group trap_group, 3883 bool is_ctrl) 3884 { 3885 MLXSW_REG_ZERO(hpkt, payload); 3886 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED); 3887 mlxsw_reg_hpkt_action_set(payload, action); 3888 mlxsw_reg_hpkt_trap_group_set(payload, trap_group); 3889 mlxsw_reg_hpkt_trap_id_set(payload, trap_id); 3890 mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ? 3891 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER : 3892 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER); 3893 } 3894 3895 /* RGCR - Router General Configuration Register 3896 * -------------------------------------------- 3897 * The register is used for setting up the router configuration. 3898 */ 3899 #define MLXSW_REG_RGCR_ID 0x8001 3900 #define MLXSW_REG_RGCR_LEN 0x28 3901 3902 MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN); 3903 3904 /* reg_rgcr_ipv4_en 3905 * IPv4 router enable. 3906 * Access: RW 3907 */ 3908 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1); 3909 3910 /* reg_rgcr_ipv6_en 3911 * IPv6 router enable. 3912 * Access: RW 3913 */ 3914 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1); 3915 3916 /* reg_rgcr_max_router_interfaces 3917 * Defines the maximum number of active router interfaces for all virtual 3918 * routers. 3919 * Access: RW 3920 */ 3921 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16); 3922 3923 /* reg_rgcr_usp 3924 * Update switch priority and packet color. 3925 * 0 - Preserve the value of Switch Priority and packet color. 3926 * 1 - Recalculate the value of Switch Priority and packet color. 3927 * Access: RW 3928 * 3929 * Note: Not supported by SwitchX and SwitchX-2. 3930 */ 3931 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1); 3932 3933 /* reg_rgcr_pcp_rw 3934 * Indicates how to handle the pcp_rewrite_en value: 3935 * 0 - Preserve the value of pcp_rewrite_en. 3936 * 2 - Disable PCP rewrite. 3937 * 3 - Enable PCP rewrite. 3938 * Access: RW 3939 * 3940 * Note: Not supported by SwitchX and SwitchX-2. 3941 */ 3942 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2); 3943 3944 /* reg_rgcr_activity_dis 3945 * Activity disable: 3946 * 0 - Activity will be set when an entry is hit (default). 3947 * 1 - Activity will not be set when an entry is hit. 3948 * 3949 * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry 3950 * (RALUE). 3951 * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host 3952 * Entry (RAUHT). 3953 * Bits 2:7 are reserved. 3954 * Access: RW 3955 * 3956 * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB. 3957 */ 3958 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8); 3959 3960 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en, 3961 bool ipv6_en) 3962 { 3963 MLXSW_REG_ZERO(rgcr, payload); 3964 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en); 3965 mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en); 3966 } 3967 3968 /* RITR - Router Interface Table Register 3969 * -------------------------------------- 3970 * The register is used to configure the router interface table. 3971 */ 3972 #define MLXSW_REG_RITR_ID 0x8002 3973 #define MLXSW_REG_RITR_LEN 0x40 3974 3975 MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN); 3976 3977 /* reg_ritr_enable 3978 * Enables routing on the router interface. 3979 * Access: RW 3980 */ 3981 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1); 3982 3983 /* reg_ritr_ipv4 3984 * IPv4 routing enable. Enables routing of IPv4 traffic on the router 3985 * interface. 3986 * Access: RW 3987 */ 3988 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1); 3989 3990 /* reg_ritr_ipv6 3991 * IPv6 routing enable. Enables routing of IPv6 traffic on the router 3992 * interface. 3993 * Access: RW 3994 */ 3995 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1); 3996 3997 /* reg_ritr_ipv4_mc 3998 * IPv4 multicast routing enable. 3999 * Access: RW 4000 */ 4001 MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1); 4002 4003 enum mlxsw_reg_ritr_if_type { 4004 /* VLAN interface. */ 4005 MLXSW_REG_RITR_VLAN_IF, 4006 /* FID interface. */ 4007 MLXSW_REG_RITR_FID_IF, 4008 /* Sub-port interface. */ 4009 MLXSW_REG_RITR_SP_IF, 4010 /* Loopback Interface. */ 4011 MLXSW_REG_RITR_LOOPBACK_IF, 4012 }; 4013 4014 /* reg_ritr_type 4015 * Router interface type as per enum mlxsw_reg_ritr_if_type. 4016 * Access: RW 4017 */ 4018 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3); 4019 4020 enum { 4021 MLXSW_REG_RITR_RIF_CREATE, 4022 MLXSW_REG_RITR_RIF_DEL, 4023 }; 4024 4025 /* reg_ritr_op 4026 * Opcode: 4027 * 0 - Create or edit RIF. 4028 * 1 - Delete RIF. 4029 * Reserved for SwitchX-2. For Spectrum, editing of interface properties 4030 * is not supported. An interface must be deleted and re-created in order 4031 * to update properties. 4032 * Access: WO 4033 */ 4034 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2); 4035 4036 /* reg_ritr_rif 4037 * Router interface index. A pointer to the Router Interface Table. 4038 * Access: Index 4039 */ 4040 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16); 4041 4042 /* reg_ritr_ipv4_fe 4043 * IPv4 Forwarding Enable. 4044 * Enables routing of IPv4 traffic on the router interface. When disabled, 4045 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 4046 * Not supported in SwitchX-2. 4047 * Access: RW 4048 */ 4049 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1); 4050 4051 /* reg_ritr_ipv6_fe 4052 * IPv6 Forwarding Enable. 4053 * Enables routing of IPv6 traffic on the router interface. When disabled, 4054 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 4055 * Not supported in SwitchX-2. 4056 * Access: RW 4057 */ 4058 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1); 4059 4060 /* reg_ritr_ipv4_mc_fe 4061 * IPv4 Multicast Forwarding Enable. 4062 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 4063 * will be enabled. 4064 * Access: RW 4065 */ 4066 MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1); 4067 4068 /* reg_ritr_lb_en 4069 * Loop-back filter enable for unicast packets. 4070 * If the flag is set then loop-back filter for unicast packets is 4071 * implemented on the RIF. Multicast packets are always subject to 4072 * loop-back filtering. 4073 * Access: RW 4074 */ 4075 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1); 4076 4077 /* reg_ritr_virtual_router 4078 * Virtual router ID associated with the router interface. 4079 * Access: RW 4080 */ 4081 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16); 4082 4083 /* reg_ritr_mtu 4084 * Router interface MTU. 4085 * Access: RW 4086 */ 4087 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16); 4088 4089 /* reg_ritr_if_swid 4090 * Switch partition ID. 4091 * Access: RW 4092 */ 4093 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8); 4094 4095 /* reg_ritr_if_mac 4096 * Router interface MAC address. 4097 * In Spectrum, all MAC addresses must have the same 38 MSBits. 4098 * Access: RW 4099 */ 4100 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6); 4101 4102 /* VLAN Interface */ 4103 4104 /* reg_ritr_vlan_if_vid 4105 * VLAN ID. 4106 * Access: RW 4107 */ 4108 MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12); 4109 4110 /* FID Interface */ 4111 4112 /* reg_ritr_fid_if_fid 4113 * Filtering ID. Used to connect a bridge to the router. Only FIDs from 4114 * the vFID range are supported. 4115 * Access: RW 4116 */ 4117 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16); 4118 4119 static inline void mlxsw_reg_ritr_fid_set(char *payload, 4120 enum mlxsw_reg_ritr_if_type rif_type, 4121 u16 fid) 4122 { 4123 if (rif_type == MLXSW_REG_RITR_FID_IF) 4124 mlxsw_reg_ritr_fid_if_fid_set(payload, fid); 4125 else 4126 mlxsw_reg_ritr_vlan_if_vid_set(payload, fid); 4127 } 4128 4129 /* Sub-port Interface */ 4130 4131 /* reg_ritr_sp_if_lag 4132 * LAG indication. When this bit is set the system_port field holds the 4133 * LAG identifier. 4134 * Access: RW 4135 */ 4136 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1); 4137 4138 /* reg_ritr_sp_system_port 4139 * Port unique indentifier. When lag bit is set, this field holds the 4140 * lag_id in bits 0:9. 4141 * Access: RW 4142 */ 4143 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16); 4144 4145 /* reg_ritr_sp_if_vid 4146 * VLAN ID. 4147 * Access: RW 4148 */ 4149 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12); 4150 4151 /* Loopback Interface */ 4152 4153 enum mlxsw_reg_ritr_loopback_protocol { 4154 /* IPinIP IPv4 underlay Unicast */ 4155 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4, 4156 /* IPinIP IPv6 underlay Unicast */ 4157 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6, 4158 }; 4159 4160 /* reg_ritr_loopback_protocol 4161 * Access: RW 4162 */ 4163 MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4); 4164 4165 enum mlxsw_reg_ritr_loopback_ipip_type { 4166 /* Tunnel is IPinIP. */ 4167 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP, 4168 /* Tunnel is GRE, no key. */ 4169 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP, 4170 /* Tunnel is GRE, with a key. */ 4171 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP, 4172 }; 4173 4174 /* reg_ritr_loopback_ipip_type 4175 * Encapsulation type. 4176 * Access: RW 4177 */ 4178 MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4); 4179 4180 enum mlxsw_reg_ritr_loopback_ipip_options { 4181 /* The key is defined by gre_key. */ 4182 MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET, 4183 }; 4184 4185 /* reg_ritr_loopback_ipip_options 4186 * Access: RW 4187 */ 4188 MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4); 4189 4190 /* reg_ritr_loopback_ipip_uvr 4191 * Underlay Virtual Router ID. 4192 * Range is 0..cap_max_virtual_routers-1. 4193 * Reserved for Spectrum-2. 4194 * Access: RW 4195 */ 4196 MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16); 4197 4198 /* reg_ritr_loopback_ipip_usip* 4199 * Encapsulation Underlay source IP. 4200 * Access: RW 4201 */ 4202 MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16); 4203 MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32); 4204 4205 /* reg_ritr_loopback_ipip_gre_key 4206 * GRE Key. 4207 * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP. 4208 * Access: RW 4209 */ 4210 MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32); 4211 4212 /* Shared between ingress/egress */ 4213 enum mlxsw_reg_ritr_counter_set_type { 4214 /* No Count. */ 4215 MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0, 4216 /* Basic. Used for router interfaces, counting the following: 4217 * - Error and Discard counters. 4218 * - Unicast, Multicast and Broadcast counters. Sharing the 4219 * same set of counters for the different type of traffic 4220 * (IPv4, IPv6 and mpls). 4221 */ 4222 MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9, 4223 }; 4224 4225 /* reg_ritr_ingress_counter_index 4226 * Counter Index for flow counter. 4227 * Access: RW 4228 */ 4229 MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24); 4230 4231 /* reg_ritr_ingress_counter_set_type 4232 * Igress Counter Set Type for router interface counter. 4233 * Access: RW 4234 */ 4235 MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8); 4236 4237 /* reg_ritr_egress_counter_index 4238 * Counter Index for flow counter. 4239 * Access: RW 4240 */ 4241 MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24); 4242 4243 /* reg_ritr_egress_counter_set_type 4244 * Egress Counter Set Type for router interface counter. 4245 * Access: RW 4246 */ 4247 MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8); 4248 4249 static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index, 4250 bool enable, bool egress) 4251 { 4252 enum mlxsw_reg_ritr_counter_set_type set_type; 4253 4254 if (enable) 4255 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC; 4256 else 4257 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT; 4258 mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type); 4259 4260 if (egress) 4261 mlxsw_reg_ritr_egress_counter_index_set(payload, index); 4262 else 4263 mlxsw_reg_ritr_ingress_counter_index_set(payload, index); 4264 } 4265 4266 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif) 4267 { 4268 MLXSW_REG_ZERO(ritr, payload); 4269 mlxsw_reg_ritr_rif_set(payload, rif); 4270 } 4271 4272 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag, 4273 u16 system_port, u16 vid) 4274 { 4275 mlxsw_reg_ritr_sp_if_lag_set(payload, lag); 4276 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port); 4277 mlxsw_reg_ritr_sp_if_vid_set(payload, vid); 4278 } 4279 4280 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable, 4281 enum mlxsw_reg_ritr_if_type type, 4282 u16 rif, u16 vr_id, u16 mtu) 4283 { 4284 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL; 4285 4286 MLXSW_REG_ZERO(ritr, payload); 4287 mlxsw_reg_ritr_enable_set(payload, enable); 4288 mlxsw_reg_ritr_ipv4_set(payload, 1); 4289 mlxsw_reg_ritr_ipv6_set(payload, 1); 4290 mlxsw_reg_ritr_ipv4_mc_set(payload, 1); 4291 mlxsw_reg_ritr_type_set(payload, type); 4292 mlxsw_reg_ritr_op_set(payload, op); 4293 mlxsw_reg_ritr_rif_set(payload, rif); 4294 mlxsw_reg_ritr_ipv4_fe_set(payload, 1); 4295 mlxsw_reg_ritr_ipv6_fe_set(payload, 1); 4296 mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1); 4297 mlxsw_reg_ritr_lb_en_set(payload, 1); 4298 mlxsw_reg_ritr_virtual_router_set(payload, vr_id); 4299 mlxsw_reg_ritr_mtu_set(payload, mtu); 4300 } 4301 4302 static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac) 4303 { 4304 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac); 4305 } 4306 4307 static inline void 4308 mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload, 4309 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 4310 enum mlxsw_reg_ritr_loopback_ipip_options options, 4311 u16 uvr_id, u32 gre_key) 4312 { 4313 mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type); 4314 mlxsw_reg_ritr_loopback_ipip_options_set(payload, options); 4315 mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id); 4316 mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key); 4317 } 4318 4319 static inline void 4320 mlxsw_reg_ritr_loopback_ipip4_pack(char *payload, 4321 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 4322 enum mlxsw_reg_ritr_loopback_ipip_options options, 4323 u16 uvr_id, u32 usip, u32 gre_key) 4324 { 4325 mlxsw_reg_ritr_loopback_protocol_set(payload, 4326 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4); 4327 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options, 4328 uvr_id, gre_key); 4329 mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip); 4330 } 4331 4332 /* RTAR - Router TCAM Allocation Register 4333 * -------------------------------------- 4334 * This register is used for allocation of regions in the TCAM table. 4335 */ 4336 #define MLXSW_REG_RTAR_ID 0x8004 4337 #define MLXSW_REG_RTAR_LEN 0x20 4338 4339 MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN); 4340 4341 enum mlxsw_reg_rtar_op { 4342 MLXSW_REG_RTAR_OP_ALLOCATE, 4343 MLXSW_REG_RTAR_OP_RESIZE, 4344 MLXSW_REG_RTAR_OP_DEALLOCATE, 4345 }; 4346 4347 /* reg_rtar_op 4348 * Access: WO 4349 */ 4350 MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4); 4351 4352 enum mlxsw_reg_rtar_key_type { 4353 MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1, 4354 MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3 4355 }; 4356 4357 /* reg_rtar_key_type 4358 * TCAM key type for the region. 4359 * Access: WO 4360 */ 4361 MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8); 4362 4363 /* reg_rtar_region_size 4364 * TCAM region size. When allocating/resizing this is the requested 4365 * size, the response is the actual size. 4366 * Note: Actual size may be larger than requested. 4367 * Reserved for op = Deallocate 4368 * Access: WO 4369 */ 4370 MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16); 4371 4372 static inline void mlxsw_reg_rtar_pack(char *payload, 4373 enum mlxsw_reg_rtar_op op, 4374 enum mlxsw_reg_rtar_key_type key_type, 4375 u16 region_size) 4376 { 4377 MLXSW_REG_ZERO(rtar, payload); 4378 mlxsw_reg_rtar_op_set(payload, op); 4379 mlxsw_reg_rtar_key_type_set(payload, key_type); 4380 mlxsw_reg_rtar_region_size_set(payload, region_size); 4381 } 4382 4383 /* RATR - Router Adjacency Table Register 4384 * -------------------------------------- 4385 * The RATR register is used to configure the Router Adjacency (next-hop) 4386 * Table. 4387 */ 4388 #define MLXSW_REG_RATR_ID 0x8008 4389 #define MLXSW_REG_RATR_LEN 0x2C 4390 4391 MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN); 4392 4393 enum mlxsw_reg_ratr_op { 4394 /* Read */ 4395 MLXSW_REG_RATR_OP_QUERY_READ = 0, 4396 /* Read and clear activity */ 4397 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2, 4398 /* Write Adjacency entry */ 4399 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1, 4400 /* Write Adjacency entry only if the activity is cleared. 4401 * The write may not succeed if the activity is set. There is not 4402 * direct feedback if the write has succeeded or not, however 4403 * the get will reveal the actual entry (SW can compare the get 4404 * response to the set command). 4405 */ 4406 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3, 4407 }; 4408 4409 /* reg_ratr_op 4410 * Note that Write operation may also be used for updating 4411 * counter_set_type and counter_index. In this case all other 4412 * fields must not be updated. 4413 * Access: OP 4414 */ 4415 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4); 4416 4417 /* reg_ratr_v 4418 * Valid bit. Indicates if the adjacency entry is valid. 4419 * Note: the device may need some time before reusing an invalidated 4420 * entry. During this time the entry can not be reused. It is 4421 * recommended to use another entry before reusing an invalidated 4422 * entry (e.g. software can put it at the end of the list for 4423 * reusing). Trying to access an invalidated entry not yet cleared 4424 * by the device results with failure indicating "Try Again" status. 4425 * When valid is '0' then egress_router_interface,trap_action, 4426 * adjacency_parameters and counters are reserved 4427 * Access: RW 4428 */ 4429 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1); 4430 4431 /* reg_ratr_a 4432 * Activity. Set for new entries. Set if a packet lookup has hit on 4433 * the specific entry. To clear the a bit, use "clear activity". 4434 * Access: RO 4435 */ 4436 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1); 4437 4438 enum mlxsw_reg_ratr_type { 4439 /* Ethernet */ 4440 MLXSW_REG_RATR_TYPE_ETHERNET, 4441 /* IPoIB Unicast without GRH. 4442 * Reserved for Spectrum. 4443 */ 4444 MLXSW_REG_RATR_TYPE_IPOIB_UC, 4445 /* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast 4446 * adjacency). 4447 * Reserved for Spectrum. 4448 */ 4449 MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH, 4450 /* IPoIB Multicast. 4451 * Reserved for Spectrum. 4452 */ 4453 MLXSW_REG_RATR_TYPE_IPOIB_MC, 4454 /* MPLS. 4455 * Reserved for SwitchX/-2. 4456 */ 4457 MLXSW_REG_RATR_TYPE_MPLS, 4458 /* IPinIP Encap. 4459 * Reserved for SwitchX/-2. 4460 */ 4461 MLXSW_REG_RATR_TYPE_IPIP, 4462 }; 4463 4464 /* reg_ratr_type 4465 * Adjacency entry type. 4466 * Access: RW 4467 */ 4468 MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4); 4469 4470 /* reg_ratr_adjacency_index_low 4471 * Bits 15:0 of index into the adjacency table. 4472 * For SwitchX and SwitchX-2, the adjacency table is linear and 4473 * used for adjacency entries only. 4474 * For Spectrum, the index is to the KVD linear. 4475 * Access: Index 4476 */ 4477 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16); 4478 4479 /* reg_ratr_egress_router_interface 4480 * Range is 0 .. cap_max_router_interfaces - 1 4481 * Access: RW 4482 */ 4483 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16); 4484 4485 enum mlxsw_reg_ratr_trap_action { 4486 MLXSW_REG_RATR_TRAP_ACTION_NOP, 4487 MLXSW_REG_RATR_TRAP_ACTION_TRAP, 4488 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU, 4489 MLXSW_REG_RATR_TRAP_ACTION_MIRROR, 4490 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS, 4491 }; 4492 4493 /* reg_ratr_trap_action 4494 * see mlxsw_reg_ratr_trap_action 4495 * Access: RW 4496 */ 4497 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4); 4498 4499 /* reg_ratr_adjacency_index_high 4500 * Bits 23:16 of the adjacency_index. 4501 * Access: Index 4502 */ 4503 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8); 4504 4505 enum mlxsw_reg_ratr_trap_id { 4506 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0, 4507 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1, 4508 }; 4509 4510 /* reg_ratr_trap_id 4511 * Trap ID to be reported to CPU. 4512 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 4513 * For trap_action of NOP, MIRROR and DISCARD_ERROR 4514 * Access: RW 4515 */ 4516 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8); 4517 4518 /* reg_ratr_eth_destination_mac 4519 * MAC address of the destination next-hop. 4520 * Access: RW 4521 */ 4522 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6); 4523 4524 enum mlxsw_reg_ratr_ipip_type { 4525 /* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */ 4526 MLXSW_REG_RATR_IPIP_TYPE_IPV4, 4527 /* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */ 4528 MLXSW_REG_RATR_IPIP_TYPE_IPV6, 4529 }; 4530 4531 /* reg_ratr_ipip_type 4532 * Underlay destination ip type. 4533 * Note: the type field must match the protocol of the router interface. 4534 * Access: RW 4535 */ 4536 MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4); 4537 4538 /* reg_ratr_ipip_ipv4_udip 4539 * Underlay ipv4 dip. 4540 * Reserved when ipip_type is IPv6. 4541 * Access: RW 4542 */ 4543 MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32); 4544 4545 /* reg_ratr_ipip_ipv6_ptr 4546 * Pointer to IPv6 underlay destination ip address. 4547 * For Spectrum: Pointer to KVD linear space. 4548 * Access: RW 4549 */ 4550 MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24); 4551 4552 enum mlxsw_reg_flow_counter_set_type { 4553 /* No count */ 4554 MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00, 4555 /* Count packets and bytes */ 4556 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03, 4557 /* Count only packets */ 4558 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05, 4559 }; 4560 4561 /* reg_ratr_counter_set_type 4562 * Counter set type for flow counters 4563 * Access: RW 4564 */ 4565 MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8); 4566 4567 /* reg_ratr_counter_index 4568 * Counter index for flow counters 4569 * Access: RW 4570 */ 4571 MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24); 4572 4573 static inline void 4574 mlxsw_reg_ratr_pack(char *payload, 4575 enum mlxsw_reg_ratr_op op, bool valid, 4576 enum mlxsw_reg_ratr_type type, 4577 u32 adjacency_index, u16 egress_rif) 4578 { 4579 MLXSW_REG_ZERO(ratr, payload); 4580 mlxsw_reg_ratr_op_set(payload, op); 4581 mlxsw_reg_ratr_v_set(payload, valid); 4582 mlxsw_reg_ratr_type_set(payload, type); 4583 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index); 4584 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16); 4585 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif); 4586 } 4587 4588 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload, 4589 const char *dest_mac) 4590 { 4591 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac); 4592 } 4593 4594 static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip) 4595 { 4596 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4); 4597 mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip); 4598 } 4599 4600 static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index, 4601 bool counter_enable) 4602 { 4603 enum mlxsw_reg_flow_counter_set_type set_type; 4604 4605 if (counter_enable) 4606 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES; 4607 else 4608 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT; 4609 4610 mlxsw_reg_ratr_counter_index_set(payload, counter_index); 4611 mlxsw_reg_ratr_counter_set_type_set(payload, set_type); 4612 } 4613 4614 /* RICNT - Router Interface Counter Register 4615 * ----------------------------------------- 4616 * The RICNT register retrieves per port performance counters 4617 */ 4618 #define MLXSW_REG_RICNT_ID 0x800B 4619 #define MLXSW_REG_RICNT_LEN 0x100 4620 4621 MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN); 4622 4623 /* reg_ricnt_counter_index 4624 * Counter index 4625 * Access: RW 4626 */ 4627 MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24); 4628 4629 enum mlxsw_reg_ricnt_counter_set_type { 4630 /* No Count. */ 4631 MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00, 4632 /* Basic. Used for router interfaces, counting the following: 4633 * - Error and Discard counters. 4634 * - Unicast, Multicast and Broadcast counters. Sharing the 4635 * same set of counters for the different type of traffic 4636 * (IPv4, IPv6 and mpls). 4637 */ 4638 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09, 4639 }; 4640 4641 /* reg_ricnt_counter_set_type 4642 * Counter Set Type for router interface counter 4643 * Access: RW 4644 */ 4645 MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8); 4646 4647 enum mlxsw_reg_ricnt_opcode { 4648 /* Nop. Supported only for read access*/ 4649 MLXSW_REG_RICNT_OPCODE_NOP = 0x00, 4650 /* Clear. Setting the clr bit will reset the counter value for 4651 * all counters of the specified Router Interface. 4652 */ 4653 MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08, 4654 }; 4655 4656 /* reg_ricnt_opcode 4657 * Opcode 4658 * Access: RW 4659 */ 4660 MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4); 4661 4662 /* reg_ricnt_good_unicast_packets 4663 * good unicast packets. 4664 * Access: RW 4665 */ 4666 MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64); 4667 4668 /* reg_ricnt_good_multicast_packets 4669 * good multicast packets. 4670 * Access: RW 4671 */ 4672 MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64); 4673 4674 /* reg_ricnt_good_broadcast_packets 4675 * good broadcast packets 4676 * Access: RW 4677 */ 4678 MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64); 4679 4680 /* reg_ricnt_good_unicast_bytes 4681 * A count of L3 data and padding octets not including L2 headers 4682 * for good unicast frames. 4683 * Access: RW 4684 */ 4685 MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64); 4686 4687 /* reg_ricnt_good_multicast_bytes 4688 * A count of L3 data and padding octets not including L2 headers 4689 * for good multicast frames. 4690 * Access: RW 4691 */ 4692 MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64); 4693 4694 /* reg_ritr_good_broadcast_bytes 4695 * A count of L3 data and padding octets not including L2 headers 4696 * for good broadcast frames. 4697 * Access: RW 4698 */ 4699 MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64); 4700 4701 /* reg_ricnt_error_packets 4702 * A count of errored frames that do not pass the router checks. 4703 * Access: RW 4704 */ 4705 MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64); 4706 4707 /* reg_ricnt_discrad_packets 4708 * A count of non-errored frames that do not pass the router checks. 4709 * Access: RW 4710 */ 4711 MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64); 4712 4713 /* reg_ricnt_error_bytes 4714 * A count of L3 data and padding octets not including L2 headers 4715 * for errored frames. 4716 * Access: RW 4717 */ 4718 MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64); 4719 4720 /* reg_ricnt_discard_bytes 4721 * A count of L3 data and padding octets not including L2 headers 4722 * for non-errored frames that do not pass the router checks. 4723 * Access: RW 4724 */ 4725 MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64); 4726 4727 static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index, 4728 enum mlxsw_reg_ricnt_opcode op) 4729 { 4730 MLXSW_REG_ZERO(ricnt, payload); 4731 mlxsw_reg_ricnt_op_set(payload, op); 4732 mlxsw_reg_ricnt_counter_index_set(payload, index); 4733 mlxsw_reg_ricnt_counter_set_type_set(payload, 4734 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC); 4735 } 4736 4737 /* RRCR - Router Rules Copy Register Layout 4738 * ---------------------------------------- 4739 * This register is used for moving and copying route entry rules. 4740 */ 4741 #define MLXSW_REG_RRCR_ID 0x800F 4742 #define MLXSW_REG_RRCR_LEN 0x24 4743 4744 MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN); 4745 4746 enum mlxsw_reg_rrcr_op { 4747 /* Move rules */ 4748 MLXSW_REG_RRCR_OP_MOVE, 4749 /* Copy rules */ 4750 MLXSW_REG_RRCR_OP_COPY, 4751 }; 4752 4753 /* reg_rrcr_op 4754 * Access: WO 4755 */ 4756 MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4); 4757 4758 /* reg_rrcr_offset 4759 * Offset within the region from which to copy/move. 4760 * Access: Index 4761 */ 4762 MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16); 4763 4764 /* reg_rrcr_size 4765 * The number of rules to copy/move. 4766 * Access: WO 4767 */ 4768 MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16); 4769 4770 /* reg_rrcr_table_id 4771 * Identifier of the table on which to perform the operation. Encoding is the 4772 * same as in RTAR.key_type 4773 * Access: Index 4774 */ 4775 MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4); 4776 4777 /* reg_rrcr_dest_offset 4778 * Offset within the region to which to copy/move 4779 * Access: Index 4780 */ 4781 MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16); 4782 4783 static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op, 4784 u16 offset, u16 size, 4785 enum mlxsw_reg_rtar_key_type table_id, 4786 u16 dest_offset) 4787 { 4788 MLXSW_REG_ZERO(rrcr, payload); 4789 mlxsw_reg_rrcr_op_set(payload, op); 4790 mlxsw_reg_rrcr_offset_set(payload, offset); 4791 mlxsw_reg_rrcr_size_set(payload, size); 4792 mlxsw_reg_rrcr_table_id_set(payload, table_id); 4793 mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset); 4794 } 4795 4796 /* RALTA - Router Algorithmic LPM Tree Allocation Register 4797 * ------------------------------------------------------- 4798 * RALTA is used to allocate the LPM trees of the SHSPM method. 4799 */ 4800 #define MLXSW_REG_RALTA_ID 0x8010 4801 #define MLXSW_REG_RALTA_LEN 0x04 4802 4803 MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN); 4804 4805 /* reg_ralta_op 4806 * opcode (valid for Write, must be 0 on Read) 4807 * 0 - allocate a tree 4808 * 1 - deallocate a tree 4809 * Access: OP 4810 */ 4811 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2); 4812 4813 enum mlxsw_reg_ralxx_protocol { 4814 MLXSW_REG_RALXX_PROTOCOL_IPV4, 4815 MLXSW_REG_RALXX_PROTOCOL_IPV6, 4816 }; 4817 4818 /* reg_ralta_protocol 4819 * Protocol. 4820 * Deallocation opcode: Reserved. 4821 * Access: RW 4822 */ 4823 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4); 4824 4825 /* reg_ralta_tree_id 4826 * An identifier (numbered from 1..cap_shspm_max_trees-1) representing 4827 * the tree identifier (managed by software). 4828 * Note that tree_id 0 is allocated for a default-route tree. 4829 * Access: Index 4830 */ 4831 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8); 4832 4833 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc, 4834 enum mlxsw_reg_ralxx_protocol protocol, 4835 u8 tree_id) 4836 { 4837 MLXSW_REG_ZERO(ralta, payload); 4838 mlxsw_reg_ralta_op_set(payload, !alloc); 4839 mlxsw_reg_ralta_protocol_set(payload, protocol); 4840 mlxsw_reg_ralta_tree_id_set(payload, tree_id); 4841 } 4842 4843 /* RALST - Router Algorithmic LPM Structure Tree Register 4844 * ------------------------------------------------------ 4845 * RALST is used to set and query the structure of an LPM tree. 4846 * The structure of the tree must be sorted as a sorted binary tree, while 4847 * each node is a bin that is tagged as the length of the prefixes the lookup 4848 * will refer to. Therefore, bin X refers to a set of entries with prefixes 4849 * of X bits to match with the destination address. The bin 0 indicates 4850 * the default action, when there is no match of any prefix. 4851 */ 4852 #define MLXSW_REG_RALST_ID 0x8011 4853 #define MLXSW_REG_RALST_LEN 0x104 4854 4855 MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN); 4856 4857 /* reg_ralst_root_bin 4858 * The bin number of the root bin. 4859 * 0<root_bin=<(length of IP address) 4860 * For a default-route tree configure 0xff 4861 * Access: RW 4862 */ 4863 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8); 4864 4865 /* reg_ralst_tree_id 4866 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 4867 * Access: Index 4868 */ 4869 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8); 4870 4871 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff 4872 #define MLXSW_REG_RALST_BIN_OFFSET 0x04 4873 #define MLXSW_REG_RALST_BIN_COUNT 128 4874 4875 /* reg_ralst_left_child_bin 4876 * Holding the children of the bin according to the stored tree's structure. 4877 * For trees composed of less than 4 blocks, the bins in excess are reserved. 4878 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 4879 * Access: RW 4880 */ 4881 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false); 4882 4883 /* reg_ralst_right_child_bin 4884 * Holding the children of the bin according to the stored tree's structure. 4885 * For trees composed of less than 4 blocks, the bins in excess are reserved. 4886 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 4887 * Access: RW 4888 */ 4889 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00, 4890 false); 4891 4892 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id) 4893 { 4894 MLXSW_REG_ZERO(ralst, payload); 4895 4896 /* Initialize all bins to have no left or right child */ 4897 memset(payload + MLXSW_REG_RALST_BIN_OFFSET, 4898 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2); 4899 4900 mlxsw_reg_ralst_root_bin_set(payload, root_bin); 4901 mlxsw_reg_ralst_tree_id_set(payload, tree_id); 4902 } 4903 4904 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number, 4905 u8 left_child_bin, 4906 u8 right_child_bin) 4907 { 4908 int bin_index = bin_number - 1; 4909 4910 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin); 4911 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index, 4912 right_child_bin); 4913 } 4914 4915 /* RALTB - Router Algorithmic LPM Tree Binding Register 4916 * ---------------------------------------------------- 4917 * RALTB is used to bind virtual router and protocol to an allocated LPM tree. 4918 */ 4919 #define MLXSW_REG_RALTB_ID 0x8012 4920 #define MLXSW_REG_RALTB_LEN 0x04 4921 4922 MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN); 4923 4924 /* reg_raltb_virtual_router 4925 * Virtual Router ID 4926 * Range is 0..cap_max_virtual_routers-1 4927 * Access: Index 4928 */ 4929 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16); 4930 4931 /* reg_raltb_protocol 4932 * Protocol. 4933 * Access: Index 4934 */ 4935 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4); 4936 4937 /* reg_raltb_tree_id 4938 * Tree to be used for the {virtual_router, protocol} 4939 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 4940 * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0. 4941 * Access: RW 4942 */ 4943 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8); 4944 4945 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router, 4946 enum mlxsw_reg_ralxx_protocol protocol, 4947 u8 tree_id) 4948 { 4949 MLXSW_REG_ZERO(raltb, payload); 4950 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router); 4951 mlxsw_reg_raltb_protocol_set(payload, protocol); 4952 mlxsw_reg_raltb_tree_id_set(payload, tree_id); 4953 } 4954 4955 /* RALUE - Router Algorithmic LPM Unicast Entry Register 4956 * ----------------------------------------------------- 4957 * RALUE is used to configure and query LPM entries that serve 4958 * the Unicast protocols. 4959 */ 4960 #define MLXSW_REG_RALUE_ID 0x8013 4961 #define MLXSW_REG_RALUE_LEN 0x38 4962 4963 MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN); 4964 4965 /* reg_ralue_protocol 4966 * Protocol. 4967 * Access: Index 4968 */ 4969 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4); 4970 4971 enum mlxsw_reg_ralue_op { 4972 /* Read operation. If entry doesn't exist, the operation fails. */ 4973 MLXSW_REG_RALUE_OP_QUERY_READ = 0, 4974 /* Clear on read operation. Used to read entry and 4975 * clear Activity bit. 4976 */ 4977 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1, 4978 /* Write operation. Used to write a new entry to the table. All RW 4979 * fields are written for new entry. Activity bit is set 4980 * for new entries. 4981 */ 4982 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0, 4983 /* Update operation. Used to update an existing route entry and 4984 * only update the RW fields that are detailed in the field 4985 * op_u_mask. If entry doesn't exist, the operation fails. 4986 */ 4987 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1, 4988 /* Clear activity. The Activity bit (the field a) is cleared 4989 * for the entry. 4990 */ 4991 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2, 4992 /* Delete operation. Used to delete an existing entry. If entry 4993 * doesn't exist, the operation fails. 4994 */ 4995 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3, 4996 }; 4997 4998 /* reg_ralue_op 4999 * Operation. 5000 * Access: OP 5001 */ 5002 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3); 5003 5004 /* reg_ralue_a 5005 * Activity. Set for new entries. Set if a packet lookup has hit on the 5006 * specific entry, only if the entry is a route. To clear the a bit, use 5007 * "clear activity" op. 5008 * Enabled by activity_dis in RGCR 5009 * Access: RO 5010 */ 5011 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1); 5012 5013 /* reg_ralue_virtual_router 5014 * Virtual Router ID 5015 * Range is 0..cap_max_virtual_routers-1 5016 * Access: Index 5017 */ 5018 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16); 5019 5020 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0) 5021 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1) 5022 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2) 5023 5024 /* reg_ralue_op_u_mask 5025 * opcode update mask. 5026 * On read operation, this field is reserved. 5027 * This field is valid for update opcode, otherwise - reserved. 5028 * This field is a bitmask of the fields that should be updated. 5029 * Access: WO 5030 */ 5031 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3); 5032 5033 /* reg_ralue_prefix_len 5034 * Number of bits in the prefix of the LPM route. 5035 * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes 5036 * two entries in the physical HW table. 5037 * Access: Index 5038 */ 5039 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8); 5040 5041 /* reg_ralue_dip* 5042 * The prefix of the route or of the marker that the object of the LPM 5043 * is compared with. The most significant bits of the dip are the prefix. 5044 * The least significant bits must be '0' if the prefix_len is smaller 5045 * than 128 for IPv6 or smaller than 32 for IPv4. 5046 * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved. 5047 * Access: Index 5048 */ 5049 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32); 5050 MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16); 5051 5052 enum mlxsw_reg_ralue_entry_type { 5053 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1, 5054 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2, 5055 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3, 5056 }; 5057 5058 /* reg_ralue_entry_type 5059 * Entry type. 5060 * Note - for Marker entries, the action_type and action fields are reserved. 5061 * Access: RW 5062 */ 5063 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2); 5064 5065 /* reg_ralue_bmp_len 5066 * The best match prefix length in the case that there is no match for 5067 * longer prefixes. 5068 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len 5069 * Note for any update operation with entry_type modification this 5070 * field must be set. 5071 * Access: RW 5072 */ 5073 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8); 5074 5075 enum mlxsw_reg_ralue_action_type { 5076 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE, 5077 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL, 5078 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME, 5079 }; 5080 5081 /* reg_ralue_action_type 5082 * Action Type 5083 * Indicates how the IP address is connected. 5084 * It can be connected to a local subnet through local_erif or can be 5085 * on a remote subnet connected through a next-hop router, 5086 * or transmitted to the CPU. 5087 * Reserved when entry_type = MARKER_ENTRY 5088 * Access: RW 5089 */ 5090 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2); 5091 5092 enum mlxsw_reg_ralue_trap_action { 5093 MLXSW_REG_RALUE_TRAP_ACTION_NOP, 5094 MLXSW_REG_RALUE_TRAP_ACTION_TRAP, 5095 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU, 5096 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR, 5097 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR, 5098 }; 5099 5100 /* reg_ralue_trap_action 5101 * Trap action. 5102 * For IP2ME action, only NOP and MIRROR are possible. 5103 * Access: RW 5104 */ 5105 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4); 5106 5107 /* reg_ralue_trap_id 5108 * Trap ID to be reported to CPU. 5109 * Trap ID is RTR_INGRESS0 or RTR_INGRESS1. 5110 * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved. 5111 * Access: RW 5112 */ 5113 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9); 5114 5115 /* reg_ralue_adjacency_index 5116 * Points to the first entry of the group-based ECMP. 5117 * Only relevant in case of REMOTE action. 5118 * Access: RW 5119 */ 5120 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24); 5121 5122 /* reg_ralue_ecmp_size 5123 * Amount of sequential entries starting 5124 * from the adjacency_index (the number of ECMPs). 5125 * The valid range is 1-64, 512, 1024, 2048 and 4096. 5126 * Reserved when trap_action is TRAP or DISCARD_ERROR. 5127 * Only relevant in case of REMOTE action. 5128 * Access: RW 5129 */ 5130 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13); 5131 5132 /* reg_ralue_local_erif 5133 * Egress Router Interface. 5134 * Only relevant in case of LOCAL action. 5135 * Access: RW 5136 */ 5137 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16); 5138 5139 /* reg_ralue_ip2me_v 5140 * Valid bit for the tunnel_ptr field. 5141 * If valid = 0 then trap to CPU as IP2ME trap ID. 5142 * If valid = 1 and the packet format allows NVE or IPinIP tunnel 5143 * decapsulation then tunnel decapsulation is done. 5144 * If valid = 1 and packet format does not allow NVE or IPinIP tunnel 5145 * decapsulation then trap as IP2ME trap ID. 5146 * Only relevant in case of IP2ME action. 5147 * Access: RW 5148 */ 5149 MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1); 5150 5151 /* reg_ralue_ip2me_tunnel_ptr 5152 * Tunnel Pointer for NVE or IPinIP tunnel decapsulation. 5153 * For Spectrum, pointer to KVD Linear. 5154 * Only relevant in case of IP2ME action. 5155 * Access: RW 5156 */ 5157 MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24); 5158 5159 static inline void mlxsw_reg_ralue_pack(char *payload, 5160 enum mlxsw_reg_ralxx_protocol protocol, 5161 enum mlxsw_reg_ralue_op op, 5162 u16 virtual_router, u8 prefix_len) 5163 { 5164 MLXSW_REG_ZERO(ralue, payload); 5165 mlxsw_reg_ralue_protocol_set(payload, protocol); 5166 mlxsw_reg_ralue_op_set(payload, op); 5167 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router); 5168 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len); 5169 mlxsw_reg_ralue_entry_type_set(payload, 5170 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY); 5171 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len); 5172 } 5173 5174 static inline void mlxsw_reg_ralue_pack4(char *payload, 5175 enum mlxsw_reg_ralxx_protocol protocol, 5176 enum mlxsw_reg_ralue_op op, 5177 u16 virtual_router, u8 prefix_len, 5178 u32 dip) 5179 { 5180 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 5181 mlxsw_reg_ralue_dip4_set(payload, dip); 5182 } 5183 5184 static inline void mlxsw_reg_ralue_pack6(char *payload, 5185 enum mlxsw_reg_ralxx_protocol protocol, 5186 enum mlxsw_reg_ralue_op op, 5187 u16 virtual_router, u8 prefix_len, 5188 const void *dip) 5189 { 5190 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 5191 mlxsw_reg_ralue_dip6_memcpy_to(payload, dip); 5192 } 5193 5194 static inline void 5195 mlxsw_reg_ralue_act_remote_pack(char *payload, 5196 enum mlxsw_reg_ralue_trap_action trap_action, 5197 u16 trap_id, u32 adjacency_index, u16 ecmp_size) 5198 { 5199 mlxsw_reg_ralue_action_type_set(payload, 5200 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE); 5201 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 5202 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 5203 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index); 5204 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size); 5205 } 5206 5207 static inline void 5208 mlxsw_reg_ralue_act_local_pack(char *payload, 5209 enum mlxsw_reg_ralue_trap_action trap_action, 5210 u16 trap_id, u16 local_erif) 5211 { 5212 mlxsw_reg_ralue_action_type_set(payload, 5213 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL); 5214 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 5215 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 5216 mlxsw_reg_ralue_local_erif_set(payload, local_erif); 5217 } 5218 5219 static inline void 5220 mlxsw_reg_ralue_act_ip2me_pack(char *payload) 5221 { 5222 mlxsw_reg_ralue_action_type_set(payload, 5223 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 5224 } 5225 5226 static inline void 5227 mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr) 5228 { 5229 mlxsw_reg_ralue_action_type_set(payload, 5230 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 5231 mlxsw_reg_ralue_ip2me_v_set(payload, 1); 5232 mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr); 5233 } 5234 5235 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register 5236 * ---------------------------------------------------------- 5237 * The RAUHT register is used to configure and query the Unicast Host table in 5238 * devices that implement the Algorithmic LPM. 5239 */ 5240 #define MLXSW_REG_RAUHT_ID 0x8014 5241 #define MLXSW_REG_RAUHT_LEN 0x74 5242 5243 MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN); 5244 5245 enum mlxsw_reg_rauht_type { 5246 MLXSW_REG_RAUHT_TYPE_IPV4, 5247 MLXSW_REG_RAUHT_TYPE_IPV6, 5248 }; 5249 5250 /* reg_rauht_type 5251 * Access: Index 5252 */ 5253 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2); 5254 5255 enum mlxsw_reg_rauht_op { 5256 MLXSW_REG_RAUHT_OP_QUERY_READ = 0, 5257 /* Read operation */ 5258 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1, 5259 /* Clear on read operation. Used to read entry and clear 5260 * activity bit. 5261 */ 5262 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0, 5263 /* Add. Used to write a new entry to the table. All R/W fields are 5264 * relevant for new entry. Activity bit is set for new entries. 5265 */ 5266 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1, 5267 /* Update action. Used to update an existing route entry and 5268 * only update the following fields: 5269 * trap_action, trap_id, mac, counter_set_type, counter_index 5270 */ 5271 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2, 5272 /* Clear activity. A bit is cleared for the entry. */ 5273 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3, 5274 /* Delete entry */ 5275 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4, 5276 /* Delete all host entries on a RIF. In this command, dip 5277 * field is reserved. 5278 */ 5279 }; 5280 5281 /* reg_rauht_op 5282 * Access: OP 5283 */ 5284 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3); 5285 5286 /* reg_rauht_a 5287 * Activity. Set for new entries. Set if a packet lookup has hit on 5288 * the specific entry. 5289 * To clear the a bit, use "clear activity" op. 5290 * Enabled by activity_dis in RGCR 5291 * Access: RO 5292 */ 5293 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1); 5294 5295 /* reg_rauht_rif 5296 * Router Interface 5297 * Access: Index 5298 */ 5299 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16); 5300 5301 /* reg_rauht_dip* 5302 * Destination address. 5303 * Access: Index 5304 */ 5305 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32); 5306 MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16); 5307 5308 enum mlxsw_reg_rauht_trap_action { 5309 MLXSW_REG_RAUHT_TRAP_ACTION_NOP, 5310 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP, 5311 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU, 5312 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR, 5313 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS, 5314 }; 5315 5316 /* reg_rauht_trap_action 5317 * Access: RW 5318 */ 5319 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4); 5320 5321 enum mlxsw_reg_rauht_trap_id { 5322 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0, 5323 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1, 5324 }; 5325 5326 /* reg_rauht_trap_id 5327 * Trap ID to be reported to CPU. 5328 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 5329 * For trap_action of NOP, MIRROR and DISCARD_ERROR, 5330 * trap_id is reserved. 5331 * Access: RW 5332 */ 5333 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9); 5334 5335 /* reg_rauht_counter_set_type 5336 * Counter set type for flow counters 5337 * Access: RW 5338 */ 5339 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8); 5340 5341 /* reg_rauht_counter_index 5342 * Counter index for flow counters 5343 * Access: RW 5344 */ 5345 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24); 5346 5347 /* reg_rauht_mac 5348 * MAC address. 5349 * Access: RW 5350 */ 5351 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6); 5352 5353 static inline void mlxsw_reg_rauht_pack(char *payload, 5354 enum mlxsw_reg_rauht_op op, u16 rif, 5355 const char *mac) 5356 { 5357 MLXSW_REG_ZERO(rauht, payload); 5358 mlxsw_reg_rauht_op_set(payload, op); 5359 mlxsw_reg_rauht_rif_set(payload, rif); 5360 mlxsw_reg_rauht_mac_memcpy_to(payload, mac); 5361 } 5362 5363 static inline void mlxsw_reg_rauht_pack4(char *payload, 5364 enum mlxsw_reg_rauht_op op, u16 rif, 5365 const char *mac, u32 dip) 5366 { 5367 mlxsw_reg_rauht_pack(payload, op, rif, mac); 5368 mlxsw_reg_rauht_dip4_set(payload, dip); 5369 } 5370 5371 static inline void mlxsw_reg_rauht_pack6(char *payload, 5372 enum mlxsw_reg_rauht_op op, u16 rif, 5373 const char *mac, const char *dip) 5374 { 5375 mlxsw_reg_rauht_pack(payload, op, rif, mac); 5376 mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6); 5377 mlxsw_reg_rauht_dip6_memcpy_to(payload, dip); 5378 } 5379 5380 static inline void mlxsw_reg_rauht_pack_counter(char *payload, 5381 u64 counter_index) 5382 { 5383 mlxsw_reg_rauht_counter_index_set(payload, counter_index); 5384 mlxsw_reg_rauht_counter_set_type_set(payload, 5385 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 5386 } 5387 5388 /* RALEU - Router Algorithmic LPM ECMP Update Register 5389 * --------------------------------------------------- 5390 * The register enables updating the ECMP section in the action for multiple 5391 * LPM Unicast entries in a single operation. The update is executed to 5392 * all entries of a {virtual router, protocol} tuple using the same ECMP group. 5393 */ 5394 #define MLXSW_REG_RALEU_ID 0x8015 5395 #define MLXSW_REG_RALEU_LEN 0x28 5396 5397 MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN); 5398 5399 /* reg_raleu_protocol 5400 * Protocol. 5401 * Access: Index 5402 */ 5403 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4); 5404 5405 /* reg_raleu_virtual_router 5406 * Virtual Router ID 5407 * Range is 0..cap_max_virtual_routers-1 5408 * Access: Index 5409 */ 5410 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16); 5411 5412 /* reg_raleu_adjacency_index 5413 * Adjacency Index used for matching on the existing entries. 5414 * Access: Index 5415 */ 5416 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24); 5417 5418 /* reg_raleu_ecmp_size 5419 * ECMP Size used for matching on the existing entries. 5420 * Access: Index 5421 */ 5422 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13); 5423 5424 /* reg_raleu_new_adjacency_index 5425 * New Adjacency Index. 5426 * Access: WO 5427 */ 5428 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24); 5429 5430 /* reg_raleu_new_ecmp_size 5431 * New ECMP Size. 5432 * Access: WO 5433 */ 5434 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13); 5435 5436 static inline void mlxsw_reg_raleu_pack(char *payload, 5437 enum mlxsw_reg_ralxx_protocol protocol, 5438 u16 virtual_router, 5439 u32 adjacency_index, u16 ecmp_size, 5440 u32 new_adjacency_index, 5441 u16 new_ecmp_size) 5442 { 5443 MLXSW_REG_ZERO(raleu, payload); 5444 mlxsw_reg_raleu_protocol_set(payload, protocol); 5445 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router); 5446 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index); 5447 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size); 5448 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index); 5449 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size); 5450 } 5451 5452 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register 5453 * ---------------------------------------------------------------- 5454 * The RAUHTD register allows dumping entries from the Router Unicast Host 5455 * Table. For a given session an entry is dumped no more than one time. The 5456 * first RAUHTD access after reset is a new session. A session ends when the 5457 * num_rec response is smaller than num_rec request or for IPv4 when the 5458 * num_entries is smaller than 4. The clear activity affect the current session 5459 * or the last session if a new session has not started. 5460 */ 5461 #define MLXSW_REG_RAUHTD_ID 0x8018 5462 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20 5463 #define MLXSW_REG_RAUHTD_REC_LEN 0x20 5464 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32 5465 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \ 5466 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN) 5467 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4 5468 5469 MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN); 5470 5471 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0) 5472 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3) 5473 5474 /* reg_rauhtd_filter_fields 5475 * if a bit is '0' then the relevant field is ignored and dump is done 5476 * regardless of the field value 5477 * Bit0 - filter by activity: entry_a 5478 * Bit3 - filter by entry rip: entry_rif 5479 * Access: Index 5480 */ 5481 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8); 5482 5483 enum mlxsw_reg_rauhtd_op { 5484 MLXSW_REG_RAUHTD_OP_DUMP, 5485 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR, 5486 }; 5487 5488 /* reg_rauhtd_op 5489 * Access: OP 5490 */ 5491 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2); 5492 5493 /* reg_rauhtd_num_rec 5494 * At request: number of records requested 5495 * At response: number of records dumped 5496 * For IPv4, each record has 4 entries at request and up to 4 entries 5497 * at response 5498 * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM 5499 * Access: Index 5500 */ 5501 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8); 5502 5503 /* reg_rauhtd_entry_a 5504 * Dump only if activity has value of entry_a 5505 * Reserved if filter_fields bit0 is '0' 5506 * Access: Index 5507 */ 5508 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1); 5509 5510 enum mlxsw_reg_rauhtd_type { 5511 MLXSW_REG_RAUHTD_TYPE_IPV4, 5512 MLXSW_REG_RAUHTD_TYPE_IPV6, 5513 }; 5514 5515 /* reg_rauhtd_type 5516 * Dump only if record type is: 5517 * 0 - IPv4 5518 * 1 - IPv6 5519 * Access: Index 5520 */ 5521 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4); 5522 5523 /* reg_rauhtd_entry_rif 5524 * Dump only if RIF has value of entry_rif 5525 * Reserved if filter_fields bit3 is '0' 5526 * Access: Index 5527 */ 5528 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16); 5529 5530 static inline void mlxsw_reg_rauhtd_pack(char *payload, 5531 enum mlxsw_reg_rauhtd_type type) 5532 { 5533 MLXSW_REG_ZERO(rauhtd, payload); 5534 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A); 5535 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR); 5536 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM); 5537 mlxsw_reg_rauhtd_entry_a_set(payload, 1); 5538 mlxsw_reg_rauhtd_type_set(payload, type); 5539 } 5540 5541 /* reg_rauhtd_ipv4_rec_num_entries 5542 * Number of valid entries in this record: 5543 * 0 - 1 valid entry 5544 * 1 - 2 valid entries 5545 * 2 - 3 valid entries 5546 * 3 - 4 valid entries 5547 * Access: RO 5548 */ 5549 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries, 5550 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2, 5551 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 5552 5553 /* reg_rauhtd_rec_type 5554 * Record type. 5555 * 0 - IPv4 5556 * 1 - IPv6 5557 * Access: RO 5558 */ 5559 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2, 5560 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 5561 5562 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8 5563 5564 /* reg_rauhtd_ipv4_ent_a 5565 * Activity. Set for new entries. Set if a packet lookup has hit on the 5566 * specific entry. 5567 * Access: RO 5568 */ 5569 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 5570 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 5571 5572 /* reg_rauhtd_ipv4_ent_rif 5573 * Router interface. 5574 * Access: RO 5575 */ 5576 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 5577 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 5578 5579 /* reg_rauhtd_ipv4_ent_dip 5580 * Destination IPv4 address. 5581 * Access: RO 5582 */ 5583 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0, 5584 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false); 5585 5586 #define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20 5587 5588 /* reg_rauhtd_ipv6_ent_a 5589 * Activity. Set for new entries. Set if a packet lookup has hit on the 5590 * specific entry. 5591 * Access: RO 5592 */ 5593 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 5594 MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 5595 5596 /* reg_rauhtd_ipv6_ent_rif 5597 * Router interface. 5598 * Access: RO 5599 */ 5600 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 5601 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 5602 5603 /* reg_rauhtd_ipv6_ent_dip 5604 * Destination IPv6 address. 5605 * Access: RO 5606 */ 5607 MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 5608 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10); 5609 5610 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload, 5611 int ent_index, u16 *p_rif, 5612 u32 *p_dip) 5613 { 5614 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index); 5615 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index); 5616 } 5617 5618 static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload, 5619 int rec_index, u16 *p_rif, 5620 char *p_dip) 5621 { 5622 *p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index); 5623 mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip); 5624 } 5625 5626 /* RTDP - Routing Tunnel Decap Properties Register 5627 * ----------------------------------------------- 5628 * The RTDP register is used for configuring the tunnel decap properties of NVE 5629 * and IPinIP. 5630 */ 5631 #define MLXSW_REG_RTDP_ID 0x8020 5632 #define MLXSW_REG_RTDP_LEN 0x44 5633 5634 MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN); 5635 5636 enum mlxsw_reg_rtdp_type { 5637 MLXSW_REG_RTDP_TYPE_NVE, 5638 MLXSW_REG_RTDP_TYPE_IPIP, 5639 }; 5640 5641 /* reg_rtdp_type 5642 * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type. 5643 * Access: RW 5644 */ 5645 MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4); 5646 5647 /* reg_rtdp_tunnel_index 5648 * Index to the Decap entry. 5649 * For Spectrum, Index to KVD Linear. 5650 * Access: Index 5651 */ 5652 MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24); 5653 5654 /* IPinIP */ 5655 5656 /* reg_rtdp_ipip_irif 5657 * Ingress Router Interface for the overlay router 5658 * Access: RW 5659 */ 5660 MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16); 5661 5662 enum mlxsw_reg_rtdp_ipip_sip_check { 5663 /* No sip checks. */ 5664 MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO, 5665 /* Filter packet if underlay is not IPv4 or if underlay SIP does not 5666 * equal ipv4_usip. 5667 */ 5668 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4, 5669 /* Filter packet if underlay is not IPv6 or if underlay SIP does not 5670 * equal ipv6_usip. 5671 */ 5672 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3, 5673 }; 5674 5675 /* reg_rtdp_ipip_sip_check 5676 * SIP check to perform. If decapsulation failed due to these configurations 5677 * then trap_id is IPIP_DECAP_ERROR. 5678 * Access: RW 5679 */ 5680 MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3); 5681 5682 /* If set, allow decapsulation of IPinIP (without GRE). */ 5683 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP BIT(0) 5684 /* If set, allow decapsulation of IPinGREinIP without a key. */ 5685 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE BIT(1) 5686 /* If set, allow decapsulation of IPinGREinIP with a key. */ 5687 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY BIT(2) 5688 5689 /* reg_rtdp_ipip_type_check 5690 * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to 5691 * these configurations then trap_id is IPIP_DECAP_ERROR. 5692 * Access: RW 5693 */ 5694 MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3); 5695 5696 /* reg_rtdp_ipip_gre_key_check 5697 * Whether GRE key should be checked. When check is enabled: 5698 * - A packet received as IPinIP (without GRE) will always pass. 5699 * - A packet received as IPinGREinIP without a key will not pass the check. 5700 * - A packet received as IPinGREinIP with a key will pass the check only if the 5701 * key in the packet is equal to expected_gre_key. 5702 * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR. 5703 * Access: RW 5704 */ 5705 MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1); 5706 5707 /* reg_rtdp_ipip_ipv4_usip 5708 * Underlay IPv4 address for ipv4 source address check. 5709 * Reserved when sip_check is not '1'. 5710 * Access: RW 5711 */ 5712 MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32); 5713 5714 /* reg_rtdp_ipip_ipv6_usip_ptr 5715 * This field is valid when sip_check is "sipv6 check explicitly". This is a 5716 * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index 5717 * is to the KVD linear. 5718 * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6. 5719 * Access: RW 5720 */ 5721 MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24); 5722 5723 /* reg_rtdp_ipip_expected_gre_key 5724 * GRE key for checking. 5725 * Reserved when gre_key_check is '0'. 5726 * Access: RW 5727 */ 5728 MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32); 5729 5730 static inline void mlxsw_reg_rtdp_pack(char *payload, 5731 enum mlxsw_reg_rtdp_type type, 5732 u32 tunnel_index) 5733 { 5734 MLXSW_REG_ZERO(rtdp, payload); 5735 mlxsw_reg_rtdp_type_set(payload, type); 5736 mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index); 5737 } 5738 5739 static inline void 5740 mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif, 5741 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 5742 unsigned int type_check, bool gre_key_check, 5743 u32 ipv4_usip, u32 expected_gre_key) 5744 { 5745 mlxsw_reg_rtdp_ipip_irif_set(payload, irif); 5746 mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check); 5747 mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check); 5748 mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check); 5749 mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip); 5750 mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key); 5751 } 5752 5753 /* RIGR-V2 - Router Interface Group Register Version 2 5754 * --------------------------------------------------- 5755 * The RIGR_V2 register is used to add, remove and query egress interface list 5756 * of a multicast forwarding entry. 5757 */ 5758 #define MLXSW_REG_RIGR2_ID 0x8023 5759 #define MLXSW_REG_RIGR2_LEN 0xB0 5760 5761 #define MLXSW_REG_RIGR2_MAX_ERIFS 32 5762 5763 MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN); 5764 5765 /* reg_rigr2_rigr_index 5766 * KVD Linear index. 5767 * Access: Index 5768 */ 5769 MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24); 5770 5771 /* reg_rigr2_vnext 5772 * Next RIGR Index is valid. 5773 * Access: RW 5774 */ 5775 MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1); 5776 5777 /* reg_rigr2_next_rigr_index 5778 * Next RIGR Index. The index is to the KVD linear. 5779 * Reserved when vnxet = '0'. 5780 * Access: RW 5781 */ 5782 MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24); 5783 5784 /* reg_rigr2_vrmid 5785 * RMID Index is valid. 5786 * Access: RW 5787 */ 5788 MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1); 5789 5790 /* reg_rigr2_rmid_index 5791 * RMID Index. 5792 * Range 0 .. max_mid - 1 5793 * Reserved when vrmid = '0'. 5794 * The index is to the Port Group Table (PGT) 5795 * Access: RW 5796 */ 5797 MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16); 5798 5799 /* reg_rigr2_erif_entry_v 5800 * Egress Router Interface is valid. 5801 * Note that low-entries must be set if high-entries are set. For 5802 * example: if erif_entry[2].v is set then erif_entry[1].v and 5803 * erif_entry[0].v must be set. 5804 * Index can be from 0 to cap_mc_erif_list_entries-1 5805 * Access: RW 5806 */ 5807 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false); 5808 5809 /* reg_rigr2_erif_entry_erif 5810 * Egress Router Interface. 5811 * Valid range is from 0 to cap_max_router_interfaces - 1 5812 * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1 5813 * Access: RW 5814 */ 5815 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false); 5816 5817 static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index, 5818 bool vnext, u32 next_rigr_index) 5819 { 5820 MLXSW_REG_ZERO(rigr2, payload); 5821 mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index); 5822 mlxsw_reg_rigr2_vnext_set(payload, vnext); 5823 mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index); 5824 mlxsw_reg_rigr2_vrmid_set(payload, 0); 5825 mlxsw_reg_rigr2_rmid_index_set(payload, 0); 5826 } 5827 5828 static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index, 5829 bool v, u16 erif) 5830 { 5831 mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v); 5832 mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif); 5833 } 5834 5835 /* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register 5836 * -------------------------------------------------------------- 5837 * The RMFT_V2 register is used to configure and query the multicast table. 5838 */ 5839 #define MLXSW_REG_RMFT2_ID 0x8027 5840 #define MLXSW_REG_RMFT2_LEN 0x174 5841 5842 MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN); 5843 5844 /* reg_rmft2_v 5845 * Valid 5846 * Access: RW 5847 */ 5848 MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1); 5849 5850 enum mlxsw_reg_rmft2_type { 5851 MLXSW_REG_RMFT2_TYPE_IPV4, 5852 MLXSW_REG_RMFT2_TYPE_IPV6 5853 }; 5854 5855 /* reg_rmft2_type 5856 * Access: Index 5857 */ 5858 MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2); 5859 5860 enum mlxsw_sp_reg_rmft2_op { 5861 /* For Write: 5862 * Write operation. Used to write a new entry to the table. All RW 5863 * fields are relevant for new entry. Activity bit is set for new 5864 * entries - Note write with v (Valid) 0 will delete the entry. 5865 * For Query: 5866 * Read operation 5867 */ 5868 MLXSW_REG_RMFT2_OP_READ_WRITE, 5869 }; 5870 5871 /* reg_rmft2_op 5872 * Operation. 5873 * Access: OP 5874 */ 5875 MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2); 5876 5877 /* reg_rmft2_a 5878 * Activity. Set for new entries. Set if a packet lookup has hit on the specific 5879 * entry. 5880 * Access: RO 5881 */ 5882 MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1); 5883 5884 /* reg_rmft2_offset 5885 * Offset within the multicast forwarding table to write to. 5886 * Access: Index 5887 */ 5888 MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16); 5889 5890 /* reg_rmft2_virtual_router 5891 * Virtual Router ID. Range from 0..cap_max_virtual_routers-1 5892 * Access: RW 5893 */ 5894 MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16); 5895 5896 enum mlxsw_reg_rmft2_irif_mask { 5897 MLXSW_REG_RMFT2_IRIF_MASK_IGNORE, 5898 MLXSW_REG_RMFT2_IRIF_MASK_COMPARE 5899 }; 5900 5901 /* reg_rmft2_irif_mask 5902 * Ingress RIF mask. 5903 * Access: RW 5904 */ 5905 MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1); 5906 5907 /* reg_rmft2_irif 5908 * Ingress RIF index. 5909 * Access: RW 5910 */ 5911 MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16); 5912 5913 /* reg_rmft2_dip4 5914 * Destination IPv4 address 5915 * Access: RW 5916 */ 5917 MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32); 5918 5919 /* reg_rmft2_dip4_mask 5920 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 5921 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 5922 * Access: RW 5923 */ 5924 MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32); 5925 5926 /* reg_rmft2_sip4 5927 * Source IPv4 address 5928 * Access: RW 5929 */ 5930 MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32); 5931 5932 /* reg_rmft2_sip4_mask 5933 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 5934 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 5935 * Access: RW 5936 */ 5937 MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32); 5938 5939 /* reg_rmft2_flexible_action_set 5940 * ACL action set. The only supported action types in this field and in any 5941 * action-set pointed from here are as follows: 5942 * 00h: ACTION_NULL 5943 * 01h: ACTION_MAC_TTL, only TTL configuration is supported. 5944 * 03h: ACTION_TRAP 5945 * 06h: ACTION_QOS 5946 * 08h: ACTION_POLICING_MONITORING 5947 * 10h: ACTION_ROUTER_MC 5948 * Access: RW 5949 */ 5950 MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80, 5951 MLXSW_REG_FLEX_ACTION_SET_LEN); 5952 5953 static inline void 5954 mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router, 5955 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 5956 u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask, 5957 const char *flexible_action_set) 5958 { 5959 MLXSW_REG_ZERO(rmft2, payload); 5960 mlxsw_reg_rmft2_v_set(payload, v); 5961 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4); 5962 mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE); 5963 mlxsw_reg_rmft2_offset_set(payload, offset); 5964 mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router); 5965 mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask); 5966 mlxsw_reg_rmft2_irif_set(payload, irif); 5967 mlxsw_reg_rmft2_dip4_set(payload, dip4); 5968 mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask); 5969 mlxsw_reg_rmft2_sip4_set(payload, sip4); 5970 mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask); 5971 if (flexible_action_set) 5972 mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload, 5973 flexible_action_set); 5974 } 5975 5976 /* MFCR - Management Fan Control Register 5977 * -------------------------------------- 5978 * This register controls the settings of the Fan Speed PWM mechanism. 5979 */ 5980 #define MLXSW_REG_MFCR_ID 0x9001 5981 #define MLXSW_REG_MFCR_LEN 0x08 5982 5983 MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN); 5984 5985 enum mlxsw_reg_mfcr_pwm_frequency { 5986 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00, 5987 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01, 5988 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02, 5989 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40, 5990 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41, 5991 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42, 5992 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43, 5993 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44, 5994 }; 5995 5996 /* reg_mfcr_pwm_frequency 5997 * Controls the frequency of the PWM signal. 5998 * Access: RW 5999 */ 6000 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7); 6001 6002 #define MLXSW_MFCR_TACHOS_MAX 10 6003 6004 /* reg_mfcr_tacho_active 6005 * Indicates which of the tachometer is active (bit per tachometer). 6006 * Access: RO 6007 */ 6008 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX); 6009 6010 #define MLXSW_MFCR_PWMS_MAX 5 6011 6012 /* reg_mfcr_pwm_active 6013 * Indicates which of the PWM control is active (bit per PWM). 6014 * Access: RO 6015 */ 6016 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX); 6017 6018 static inline void 6019 mlxsw_reg_mfcr_pack(char *payload, 6020 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency) 6021 { 6022 MLXSW_REG_ZERO(mfcr, payload); 6023 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency); 6024 } 6025 6026 static inline void 6027 mlxsw_reg_mfcr_unpack(char *payload, 6028 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency, 6029 u16 *p_tacho_active, u8 *p_pwm_active) 6030 { 6031 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload); 6032 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload); 6033 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload); 6034 } 6035 6036 /* MFSC - Management Fan Speed Control Register 6037 * -------------------------------------------- 6038 * This register controls the settings of the Fan Speed PWM mechanism. 6039 */ 6040 #define MLXSW_REG_MFSC_ID 0x9002 6041 #define MLXSW_REG_MFSC_LEN 0x08 6042 6043 MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN); 6044 6045 /* reg_mfsc_pwm 6046 * Fan pwm to control / monitor. 6047 * Access: Index 6048 */ 6049 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3); 6050 6051 /* reg_mfsc_pwm_duty_cycle 6052 * Controls the duty cycle of the PWM. Value range from 0..255 to 6053 * represent duty cycle of 0%...100%. 6054 * Access: RW 6055 */ 6056 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8); 6057 6058 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm, 6059 u8 pwm_duty_cycle) 6060 { 6061 MLXSW_REG_ZERO(mfsc, payload); 6062 mlxsw_reg_mfsc_pwm_set(payload, pwm); 6063 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle); 6064 } 6065 6066 /* MFSM - Management Fan Speed Measurement 6067 * --------------------------------------- 6068 * This register controls the settings of the Tacho measurements and 6069 * enables reading the Tachometer measurements. 6070 */ 6071 #define MLXSW_REG_MFSM_ID 0x9003 6072 #define MLXSW_REG_MFSM_LEN 0x08 6073 6074 MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN); 6075 6076 /* reg_mfsm_tacho 6077 * Fan tachometer index. 6078 * Access: Index 6079 */ 6080 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4); 6081 6082 /* reg_mfsm_rpm 6083 * Fan speed (round per minute). 6084 * Access: RO 6085 */ 6086 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16); 6087 6088 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho) 6089 { 6090 MLXSW_REG_ZERO(mfsm, payload); 6091 mlxsw_reg_mfsm_tacho_set(payload, tacho); 6092 } 6093 6094 /* MFSL - Management Fan Speed Limit Register 6095 * ------------------------------------------ 6096 * The Fan Speed Limit register is used to configure the fan speed 6097 * event / interrupt notification mechanism. Fan speed threshold are 6098 * defined for both under-speed and over-speed. 6099 */ 6100 #define MLXSW_REG_MFSL_ID 0x9004 6101 #define MLXSW_REG_MFSL_LEN 0x0C 6102 6103 MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN); 6104 6105 /* reg_mfsl_tacho 6106 * Fan tachometer index. 6107 * Access: Index 6108 */ 6109 MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4); 6110 6111 /* reg_mfsl_tach_min 6112 * Tachometer minimum value (minimum RPM). 6113 * Access: RW 6114 */ 6115 MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16); 6116 6117 /* reg_mfsl_tach_max 6118 * Tachometer maximum value (maximum RPM). 6119 * Access: RW 6120 */ 6121 MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16); 6122 6123 static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho, 6124 u16 tach_min, u16 tach_max) 6125 { 6126 MLXSW_REG_ZERO(mfsl, payload); 6127 mlxsw_reg_mfsl_tacho_set(payload, tacho); 6128 mlxsw_reg_mfsl_tach_min_set(payload, tach_min); 6129 mlxsw_reg_mfsl_tach_max_set(payload, tach_max); 6130 } 6131 6132 static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho, 6133 u16 *p_tach_min, u16 *p_tach_max) 6134 { 6135 if (p_tach_min) 6136 *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload); 6137 6138 if (p_tach_max) 6139 *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload); 6140 } 6141 6142 /* MTCAP - Management Temperature Capabilities 6143 * ------------------------------------------- 6144 * This register exposes the capabilities of the device and 6145 * system temperature sensing. 6146 */ 6147 #define MLXSW_REG_MTCAP_ID 0x9009 6148 #define MLXSW_REG_MTCAP_LEN 0x08 6149 6150 MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN); 6151 6152 /* reg_mtcap_sensor_count 6153 * Number of sensors supported by the device. 6154 * This includes the QSFP module sensors (if exists in the QSFP module). 6155 * Access: RO 6156 */ 6157 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7); 6158 6159 /* MTMP - Management Temperature 6160 * ----------------------------- 6161 * This register controls the settings of the temperature measurements 6162 * and enables reading the temperature measurements. Note that temperature 6163 * is in 0.125 degrees Celsius. 6164 */ 6165 #define MLXSW_REG_MTMP_ID 0x900A 6166 #define MLXSW_REG_MTMP_LEN 0x20 6167 6168 MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN); 6169 6170 /* reg_mtmp_sensor_index 6171 * Sensors index to access. 6172 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially 6173 * (module 0 is mapped to sensor_index 64). 6174 * Access: Index 6175 */ 6176 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 7); 6177 6178 /* Convert to milli degrees Celsius */ 6179 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) (val * 125) 6180 6181 /* reg_mtmp_temperature 6182 * Temperature reading from the sensor. Reading is in 0.125 Celsius 6183 * degrees units. 6184 * Access: RO 6185 */ 6186 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16); 6187 6188 /* reg_mtmp_mte 6189 * Max Temperature Enable - enables measuring the max temperature on a sensor. 6190 * Access: RW 6191 */ 6192 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1); 6193 6194 /* reg_mtmp_mtr 6195 * Max Temperature Reset - clears the value of the max temperature register. 6196 * Access: WO 6197 */ 6198 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1); 6199 6200 /* reg_mtmp_max_temperature 6201 * The highest measured temperature from the sensor. 6202 * When the bit mte is cleared, the field max_temperature is reserved. 6203 * Access: RO 6204 */ 6205 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16); 6206 6207 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8 6208 6209 /* reg_mtmp_sensor_name 6210 * Sensor Name 6211 * Access: RO 6212 */ 6213 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE); 6214 6215 static inline void mlxsw_reg_mtmp_pack(char *payload, u8 sensor_index, 6216 bool max_temp_enable, 6217 bool max_temp_reset) 6218 { 6219 MLXSW_REG_ZERO(mtmp, payload); 6220 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index); 6221 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable); 6222 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset); 6223 } 6224 6225 static inline void mlxsw_reg_mtmp_unpack(char *payload, unsigned int *p_temp, 6226 unsigned int *p_max_temp, 6227 char *sensor_name) 6228 { 6229 u16 temp; 6230 6231 if (p_temp) { 6232 temp = mlxsw_reg_mtmp_temperature_get(payload); 6233 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 6234 } 6235 if (p_max_temp) { 6236 temp = mlxsw_reg_mtmp_max_temperature_get(payload); 6237 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 6238 } 6239 if (sensor_name) 6240 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name); 6241 } 6242 6243 /* MCIA - Management Cable Info Access 6244 * ----------------------------------- 6245 * MCIA register is used to access the SFP+ and QSFP connector's EPROM. 6246 */ 6247 6248 #define MLXSW_REG_MCIA_ID 0x9014 6249 #define MLXSW_REG_MCIA_LEN 0x40 6250 6251 MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN); 6252 6253 /* reg_mcia_l 6254 * Lock bit. Setting this bit will lock the access to the specific 6255 * cable. Used for updating a full page in a cable EPROM. Any access 6256 * other then subsequence writes will fail while the port is locked. 6257 * Access: RW 6258 */ 6259 MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1); 6260 6261 /* reg_mcia_module 6262 * Module number. 6263 * Access: Index 6264 */ 6265 MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8); 6266 6267 /* reg_mcia_status 6268 * Module status. 6269 * Access: RO 6270 */ 6271 MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8); 6272 6273 /* reg_mcia_i2c_device_address 6274 * I2C device address. 6275 * Access: RW 6276 */ 6277 MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8); 6278 6279 /* reg_mcia_page_number 6280 * Page number. 6281 * Access: RW 6282 */ 6283 MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8); 6284 6285 /* reg_mcia_device_address 6286 * Device address. 6287 * Access: RW 6288 */ 6289 MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16); 6290 6291 /* reg_mcia_size 6292 * Number of bytes to read/write (up to 48 bytes). 6293 * Access: RW 6294 */ 6295 MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16); 6296 6297 #define MLXSW_SP_REG_MCIA_EEPROM_SIZE 48 6298 6299 /* reg_mcia_eeprom 6300 * Bytes to read/write. 6301 * Access: RW 6302 */ 6303 MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_SP_REG_MCIA_EEPROM_SIZE); 6304 6305 static inline void mlxsw_reg_mcia_pack(char *payload, u8 module, u8 lock, 6306 u8 page_number, u16 device_addr, 6307 u8 size, u8 i2c_device_addr) 6308 { 6309 MLXSW_REG_ZERO(mcia, payload); 6310 mlxsw_reg_mcia_module_set(payload, module); 6311 mlxsw_reg_mcia_l_set(payload, lock); 6312 mlxsw_reg_mcia_page_number_set(payload, page_number); 6313 mlxsw_reg_mcia_device_address_set(payload, device_addr); 6314 mlxsw_reg_mcia_size_set(payload, size); 6315 mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr); 6316 } 6317 6318 /* MPAT - Monitoring Port Analyzer Table 6319 * ------------------------------------- 6320 * MPAT Register is used to query and configure the Switch PortAnalyzer Table. 6321 * For an enabled analyzer, all fields except e (enable) cannot be modified. 6322 */ 6323 #define MLXSW_REG_MPAT_ID 0x901A 6324 #define MLXSW_REG_MPAT_LEN 0x78 6325 6326 MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN); 6327 6328 /* reg_mpat_pa_id 6329 * Port Analyzer ID. 6330 * Access: Index 6331 */ 6332 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4); 6333 6334 /* reg_mpat_system_port 6335 * A unique port identifier for the final destination of the packet. 6336 * Access: RW 6337 */ 6338 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16); 6339 6340 /* reg_mpat_e 6341 * Enable. Indicating the Port Analyzer is enabled. 6342 * Access: RW 6343 */ 6344 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1); 6345 6346 /* reg_mpat_qos 6347 * Quality Of Service Mode. 6348 * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation 6349 * PCP, DEI, DSCP or VL) are configured. 6350 * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the 6351 * same as in the original packet that has triggered the mirroring. For 6352 * SPAN also the pcp,dei are maintained. 6353 * Access: RW 6354 */ 6355 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1); 6356 6357 /* reg_mpat_be 6358 * Best effort mode. Indicates mirroring traffic should not cause packet 6359 * drop or back pressure, but will discard the mirrored packets. Mirrored 6360 * packets will be forwarded on a best effort manner. 6361 * 0: Do not discard mirrored packets 6362 * 1: Discard mirrored packets if causing congestion 6363 * Access: RW 6364 */ 6365 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1); 6366 6367 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id, 6368 u16 system_port, bool e) 6369 { 6370 MLXSW_REG_ZERO(mpat, payload); 6371 mlxsw_reg_mpat_pa_id_set(payload, pa_id); 6372 mlxsw_reg_mpat_system_port_set(payload, system_port); 6373 mlxsw_reg_mpat_e_set(payload, e); 6374 mlxsw_reg_mpat_qos_set(payload, 1); 6375 mlxsw_reg_mpat_be_set(payload, 1); 6376 } 6377 6378 /* MPAR - Monitoring Port Analyzer Register 6379 * ---------------------------------------- 6380 * MPAR register is used to query and configure the port analyzer port mirroring 6381 * properties. 6382 */ 6383 #define MLXSW_REG_MPAR_ID 0x901B 6384 #define MLXSW_REG_MPAR_LEN 0x08 6385 6386 MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN); 6387 6388 /* reg_mpar_local_port 6389 * The local port to mirror the packets from. 6390 * Access: Index 6391 */ 6392 MLXSW_ITEM32(reg, mpar, local_port, 0x00, 16, 8); 6393 6394 enum mlxsw_reg_mpar_i_e { 6395 MLXSW_REG_MPAR_TYPE_EGRESS, 6396 MLXSW_REG_MPAR_TYPE_INGRESS, 6397 }; 6398 6399 /* reg_mpar_i_e 6400 * Ingress/Egress 6401 * Access: Index 6402 */ 6403 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4); 6404 6405 /* reg_mpar_enable 6406 * Enable mirroring 6407 * By default, port mirroring is disabled for all ports. 6408 * Access: RW 6409 */ 6410 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1); 6411 6412 /* reg_mpar_pa_id 6413 * Port Analyzer ID. 6414 * Access: RW 6415 */ 6416 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4); 6417 6418 static inline void mlxsw_reg_mpar_pack(char *payload, u8 local_port, 6419 enum mlxsw_reg_mpar_i_e i_e, 6420 bool enable, u8 pa_id) 6421 { 6422 MLXSW_REG_ZERO(mpar, payload); 6423 mlxsw_reg_mpar_local_port_set(payload, local_port); 6424 mlxsw_reg_mpar_enable_set(payload, enable); 6425 mlxsw_reg_mpar_i_e_set(payload, i_e); 6426 mlxsw_reg_mpar_pa_id_set(payload, pa_id); 6427 } 6428 6429 /* MLCR - Management LED Control Register 6430 * -------------------------------------- 6431 * Controls the system LEDs. 6432 */ 6433 #define MLXSW_REG_MLCR_ID 0x902B 6434 #define MLXSW_REG_MLCR_LEN 0x0C 6435 6436 MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN); 6437 6438 /* reg_mlcr_local_port 6439 * Local port number. 6440 * Access: RW 6441 */ 6442 MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8); 6443 6444 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF 6445 6446 /* reg_mlcr_beacon_duration 6447 * Duration of the beacon to be active, in seconds. 6448 * 0x0 - Will turn off the beacon. 6449 * 0xFFFF - Will turn on the beacon until explicitly turned off. 6450 * Access: RW 6451 */ 6452 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16); 6453 6454 /* reg_mlcr_beacon_remain 6455 * Remaining duration of the beacon, in seconds. 6456 * 0xFFFF indicates an infinite amount of time. 6457 * Access: RO 6458 */ 6459 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16); 6460 6461 static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port, 6462 bool active) 6463 { 6464 MLXSW_REG_ZERO(mlcr, payload); 6465 mlxsw_reg_mlcr_local_port_set(payload, local_port); 6466 mlxsw_reg_mlcr_beacon_duration_set(payload, active ? 6467 MLXSW_REG_MLCR_DURATION_MAX : 0); 6468 } 6469 6470 /* MCQI - Management Component Query Information 6471 * --------------------------------------------- 6472 * This register allows querying information about firmware components. 6473 */ 6474 #define MLXSW_REG_MCQI_ID 0x9061 6475 #define MLXSW_REG_MCQI_BASE_LEN 0x18 6476 #define MLXSW_REG_MCQI_CAP_LEN 0x14 6477 #define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN) 6478 6479 MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN); 6480 6481 /* reg_mcqi_component_index 6482 * Index of the accessed component. 6483 * Access: Index 6484 */ 6485 MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16); 6486 6487 enum mlxfw_reg_mcqi_info_type { 6488 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES, 6489 }; 6490 6491 /* reg_mcqi_info_type 6492 * Component properties set. 6493 * Access: RW 6494 */ 6495 MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5); 6496 6497 /* reg_mcqi_offset 6498 * The requested/returned data offset from the section start, given in bytes. 6499 * Must be DWORD aligned. 6500 * Access: RW 6501 */ 6502 MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32); 6503 6504 /* reg_mcqi_data_size 6505 * The requested/returned data size, given in bytes. If data_size is not DWORD 6506 * aligned, the last bytes are zero padded. 6507 * Access: RW 6508 */ 6509 MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16); 6510 6511 /* reg_mcqi_cap_max_component_size 6512 * Maximum size for this component, given in bytes. 6513 * Access: RO 6514 */ 6515 MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32); 6516 6517 /* reg_mcqi_cap_log_mcda_word_size 6518 * Log 2 of the access word size in bytes. Read and write access must be aligned 6519 * to the word size. Write access must be done for an integer number of words. 6520 * Access: RO 6521 */ 6522 MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4); 6523 6524 /* reg_mcqi_cap_mcda_max_write_size 6525 * Maximal write size for MCDA register 6526 * Access: RO 6527 */ 6528 MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16); 6529 6530 static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index) 6531 { 6532 MLXSW_REG_ZERO(mcqi, payload); 6533 mlxsw_reg_mcqi_component_index_set(payload, component_index); 6534 mlxsw_reg_mcqi_info_type_set(payload, 6535 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES); 6536 mlxsw_reg_mcqi_offset_set(payload, 0); 6537 mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN); 6538 } 6539 6540 static inline void mlxsw_reg_mcqi_unpack(char *payload, 6541 u32 *p_cap_max_component_size, 6542 u8 *p_cap_log_mcda_word_size, 6543 u16 *p_cap_mcda_max_write_size) 6544 { 6545 *p_cap_max_component_size = 6546 mlxsw_reg_mcqi_cap_max_component_size_get(payload); 6547 *p_cap_log_mcda_word_size = 6548 mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload); 6549 *p_cap_mcda_max_write_size = 6550 mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload); 6551 } 6552 6553 /* MCC - Management Component Control 6554 * ---------------------------------- 6555 * Controls the firmware component and updates the FSM. 6556 */ 6557 #define MLXSW_REG_MCC_ID 0x9062 6558 #define MLXSW_REG_MCC_LEN 0x1C 6559 6560 MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN); 6561 6562 enum mlxsw_reg_mcc_instruction { 6563 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01, 6564 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02, 6565 MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03, 6566 MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04, 6567 MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06, 6568 MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08, 6569 }; 6570 6571 /* reg_mcc_instruction 6572 * Command to be executed by the FSM. 6573 * Applicable for write operation only. 6574 * Access: RW 6575 */ 6576 MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8); 6577 6578 /* reg_mcc_component_index 6579 * Index of the accessed component. Applicable only for commands that 6580 * refer to components. Otherwise, this field is reserved. 6581 * Access: Index 6582 */ 6583 MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16); 6584 6585 /* reg_mcc_update_handle 6586 * Token representing the current flow executed by the FSM. 6587 * Access: WO 6588 */ 6589 MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24); 6590 6591 /* reg_mcc_error_code 6592 * Indicates the successful completion of the instruction, or the reason it 6593 * failed 6594 * Access: RO 6595 */ 6596 MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8); 6597 6598 /* reg_mcc_control_state 6599 * Current FSM state 6600 * Access: RO 6601 */ 6602 MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4); 6603 6604 /* reg_mcc_component_size 6605 * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying 6606 * the size may shorten the update time. Value 0x0 means that size is 6607 * unspecified. 6608 * Access: WO 6609 */ 6610 MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32); 6611 6612 static inline void mlxsw_reg_mcc_pack(char *payload, 6613 enum mlxsw_reg_mcc_instruction instr, 6614 u16 component_index, u32 update_handle, 6615 u32 component_size) 6616 { 6617 MLXSW_REG_ZERO(mcc, payload); 6618 mlxsw_reg_mcc_instruction_set(payload, instr); 6619 mlxsw_reg_mcc_component_index_set(payload, component_index); 6620 mlxsw_reg_mcc_update_handle_set(payload, update_handle); 6621 mlxsw_reg_mcc_component_size_set(payload, component_size); 6622 } 6623 6624 static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle, 6625 u8 *p_error_code, u8 *p_control_state) 6626 { 6627 if (p_update_handle) 6628 *p_update_handle = mlxsw_reg_mcc_update_handle_get(payload); 6629 if (p_error_code) 6630 *p_error_code = mlxsw_reg_mcc_error_code_get(payload); 6631 if (p_control_state) 6632 *p_control_state = mlxsw_reg_mcc_control_state_get(payload); 6633 } 6634 6635 /* MCDA - Management Component Data Access 6636 * --------------------------------------- 6637 * This register allows reading and writing a firmware component. 6638 */ 6639 #define MLXSW_REG_MCDA_ID 0x9063 6640 #define MLXSW_REG_MCDA_BASE_LEN 0x10 6641 #define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80 6642 #define MLXSW_REG_MCDA_LEN \ 6643 (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN) 6644 6645 MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN); 6646 6647 /* reg_mcda_update_handle 6648 * Token representing the current flow executed by the FSM. 6649 * Access: RW 6650 */ 6651 MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24); 6652 6653 /* reg_mcda_offset 6654 * Offset of accessed address relative to component start. Accesses must be in 6655 * accordance to log_mcda_word_size in MCQI reg. 6656 * Access: RW 6657 */ 6658 MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32); 6659 6660 /* reg_mcda_size 6661 * Size of the data accessed, given in bytes. 6662 * Access: RW 6663 */ 6664 MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16); 6665 6666 /* reg_mcda_data 6667 * Data block accessed. 6668 * Access: RW 6669 */ 6670 MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false); 6671 6672 static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle, 6673 u32 offset, u16 size, u8 *data) 6674 { 6675 int i; 6676 6677 MLXSW_REG_ZERO(mcda, payload); 6678 mlxsw_reg_mcda_update_handle_set(payload, update_handle); 6679 mlxsw_reg_mcda_offset_set(payload, offset); 6680 mlxsw_reg_mcda_size_set(payload, size); 6681 6682 for (i = 0; i < size / 4; i++) 6683 mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]); 6684 } 6685 6686 /* MPSC - Monitoring Packet Sampling Configuration Register 6687 * -------------------------------------------------------- 6688 * MPSC Register is used to configure the Packet Sampling mechanism. 6689 */ 6690 #define MLXSW_REG_MPSC_ID 0x9080 6691 #define MLXSW_REG_MPSC_LEN 0x1C 6692 6693 MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN); 6694 6695 /* reg_mpsc_local_port 6696 * Local port number 6697 * Not supported for CPU port 6698 * Access: Index 6699 */ 6700 MLXSW_ITEM32(reg, mpsc, local_port, 0x00, 16, 8); 6701 6702 /* reg_mpsc_e 6703 * Enable sampling on port local_port 6704 * Access: RW 6705 */ 6706 MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1); 6707 6708 #define MLXSW_REG_MPSC_RATE_MAX 3500000000UL 6709 6710 /* reg_mpsc_rate 6711 * Sampling rate = 1 out of rate packets (with randomization around 6712 * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX 6713 * Access: RW 6714 */ 6715 MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32); 6716 6717 static inline void mlxsw_reg_mpsc_pack(char *payload, u8 local_port, bool e, 6718 u32 rate) 6719 { 6720 MLXSW_REG_ZERO(mpsc, payload); 6721 mlxsw_reg_mpsc_local_port_set(payload, local_port); 6722 mlxsw_reg_mpsc_e_set(payload, e); 6723 mlxsw_reg_mpsc_rate_set(payload, rate); 6724 } 6725 6726 /* MGPC - Monitoring General Purpose Counter Set Register 6727 * The MGPC register retrieves and sets the General Purpose Counter Set. 6728 */ 6729 #define MLXSW_REG_MGPC_ID 0x9081 6730 #define MLXSW_REG_MGPC_LEN 0x18 6731 6732 MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN); 6733 6734 /* reg_mgpc_counter_set_type 6735 * Counter set type. 6736 * Access: OP 6737 */ 6738 MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8); 6739 6740 /* reg_mgpc_counter_index 6741 * Counter index. 6742 * Access: Index 6743 */ 6744 MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24); 6745 6746 enum mlxsw_reg_mgpc_opcode { 6747 /* Nop */ 6748 MLXSW_REG_MGPC_OPCODE_NOP = 0x00, 6749 /* Clear counters */ 6750 MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08, 6751 }; 6752 6753 /* reg_mgpc_opcode 6754 * Opcode. 6755 * Access: OP 6756 */ 6757 MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4); 6758 6759 /* reg_mgpc_byte_counter 6760 * Byte counter value. 6761 * Access: RW 6762 */ 6763 MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64); 6764 6765 /* reg_mgpc_packet_counter 6766 * Packet counter value. 6767 * Access: RW 6768 */ 6769 MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64); 6770 6771 static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index, 6772 enum mlxsw_reg_mgpc_opcode opcode, 6773 enum mlxsw_reg_flow_counter_set_type set_type) 6774 { 6775 MLXSW_REG_ZERO(mgpc, payload); 6776 mlxsw_reg_mgpc_counter_index_set(payload, counter_index); 6777 mlxsw_reg_mgpc_counter_set_type_set(payload, set_type); 6778 mlxsw_reg_mgpc_opcode_set(payload, opcode); 6779 } 6780 6781 /* SBPR - Shared Buffer Pools Register 6782 * ----------------------------------- 6783 * The SBPR configures and retrieves the shared buffer pools and configuration. 6784 */ 6785 #define MLXSW_REG_SBPR_ID 0xB001 6786 #define MLXSW_REG_SBPR_LEN 0x14 6787 6788 MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN); 6789 6790 /* shared direstion enum for SBPR, SBCM, SBPM */ 6791 enum mlxsw_reg_sbxx_dir { 6792 MLXSW_REG_SBXX_DIR_INGRESS, 6793 MLXSW_REG_SBXX_DIR_EGRESS, 6794 }; 6795 6796 /* reg_sbpr_dir 6797 * Direction. 6798 * Access: Index 6799 */ 6800 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2); 6801 6802 /* reg_sbpr_pool 6803 * Pool index. 6804 * Access: Index 6805 */ 6806 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4); 6807 6808 /* reg_sbpr_size 6809 * Pool size in buffer cells. 6810 * Access: RW 6811 */ 6812 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24); 6813 6814 enum mlxsw_reg_sbpr_mode { 6815 MLXSW_REG_SBPR_MODE_STATIC, 6816 MLXSW_REG_SBPR_MODE_DYNAMIC, 6817 }; 6818 6819 /* reg_sbpr_mode 6820 * Pool quota calculation mode. 6821 * Access: RW 6822 */ 6823 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4); 6824 6825 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool, 6826 enum mlxsw_reg_sbxx_dir dir, 6827 enum mlxsw_reg_sbpr_mode mode, u32 size) 6828 { 6829 MLXSW_REG_ZERO(sbpr, payload); 6830 mlxsw_reg_sbpr_pool_set(payload, pool); 6831 mlxsw_reg_sbpr_dir_set(payload, dir); 6832 mlxsw_reg_sbpr_mode_set(payload, mode); 6833 mlxsw_reg_sbpr_size_set(payload, size); 6834 } 6835 6836 /* SBCM - Shared Buffer Class Management Register 6837 * ---------------------------------------------- 6838 * The SBCM register configures and retrieves the shared buffer allocation 6839 * and configuration according to Port-PG, including the binding to pool 6840 * and definition of the associated quota. 6841 */ 6842 #define MLXSW_REG_SBCM_ID 0xB002 6843 #define MLXSW_REG_SBCM_LEN 0x28 6844 6845 MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN); 6846 6847 /* reg_sbcm_local_port 6848 * Local port number. 6849 * For Ingress: excludes CPU port and Router port 6850 * For Egress: excludes IP Router 6851 * Access: Index 6852 */ 6853 MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8); 6854 6855 /* reg_sbcm_pg_buff 6856 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress) 6857 * For PG buffer: range is 0..cap_max_pg_buffers - 1 6858 * For traffic class: range is 0..cap_max_tclass - 1 6859 * Note that when traffic class is in MC aware mode then the traffic 6860 * classes which are MC aware cannot be configured. 6861 * Access: Index 6862 */ 6863 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6); 6864 6865 /* reg_sbcm_dir 6866 * Direction. 6867 * Access: Index 6868 */ 6869 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2); 6870 6871 /* reg_sbcm_min_buff 6872 * Minimum buffer size for the limiter, in cells. 6873 * Access: RW 6874 */ 6875 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24); 6876 6877 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */ 6878 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1 6879 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14 6880 6881 /* reg_sbcm_max_buff 6882 * When the pool associated to the port-pg/tclass is configured to 6883 * static, Maximum buffer size for the limiter configured in cells. 6884 * When the pool associated to the port-pg/tclass is configured to 6885 * dynamic, the max_buff holds the "alpha" parameter, supporting 6886 * the following values: 6887 * 0: 0 6888 * i: (1/128)*2^(i-1), for i=1..14 6889 * 0xFF: Infinity 6890 * Access: RW 6891 */ 6892 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24); 6893 6894 /* reg_sbcm_pool 6895 * Association of the port-priority to a pool. 6896 * Access: RW 6897 */ 6898 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4); 6899 6900 static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff, 6901 enum mlxsw_reg_sbxx_dir dir, 6902 u32 min_buff, u32 max_buff, u8 pool) 6903 { 6904 MLXSW_REG_ZERO(sbcm, payload); 6905 mlxsw_reg_sbcm_local_port_set(payload, local_port); 6906 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff); 6907 mlxsw_reg_sbcm_dir_set(payload, dir); 6908 mlxsw_reg_sbcm_min_buff_set(payload, min_buff); 6909 mlxsw_reg_sbcm_max_buff_set(payload, max_buff); 6910 mlxsw_reg_sbcm_pool_set(payload, pool); 6911 } 6912 6913 /* SBPM - Shared Buffer Port Management Register 6914 * --------------------------------------------- 6915 * The SBPM register configures and retrieves the shared buffer allocation 6916 * and configuration according to Port-Pool, including the definition 6917 * of the associated quota. 6918 */ 6919 #define MLXSW_REG_SBPM_ID 0xB003 6920 #define MLXSW_REG_SBPM_LEN 0x28 6921 6922 MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN); 6923 6924 /* reg_sbpm_local_port 6925 * Local port number. 6926 * For Ingress: excludes CPU port and Router port 6927 * For Egress: excludes IP Router 6928 * Access: Index 6929 */ 6930 MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8); 6931 6932 /* reg_sbpm_pool 6933 * The pool associated to quota counting on the local_port. 6934 * Access: Index 6935 */ 6936 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4); 6937 6938 /* reg_sbpm_dir 6939 * Direction. 6940 * Access: Index 6941 */ 6942 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2); 6943 6944 /* reg_sbpm_buff_occupancy 6945 * Current buffer occupancy in cells. 6946 * Access: RO 6947 */ 6948 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24); 6949 6950 /* reg_sbpm_clr 6951 * Clear Max Buffer Occupancy 6952 * When this bit is set, max_buff_occupancy field is cleared (and a 6953 * new max value is tracked from the time the clear was performed). 6954 * Access: OP 6955 */ 6956 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1); 6957 6958 /* reg_sbpm_max_buff_occupancy 6959 * Maximum value of buffer occupancy in cells monitored. Cleared by 6960 * writing to the clr field. 6961 * Access: RO 6962 */ 6963 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24); 6964 6965 /* reg_sbpm_min_buff 6966 * Minimum buffer size for the limiter, in cells. 6967 * Access: RW 6968 */ 6969 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24); 6970 6971 /* reg_sbpm_max_buff 6972 * When the pool associated to the port-pg/tclass is configured to 6973 * static, Maximum buffer size for the limiter configured in cells. 6974 * When the pool associated to the port-pg/tclass is configured to 6975 * dynamic, the max_buff holds the "alpha" parameter, supporting 6976 * the following values: 6977 * 0: 0 6978 * i: (1/128)*2^(i-1), for i=1..14 6979 * 0xFF: Infinity 6980 * Access: RW 6981 */ 6982 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24); 6983 6984 static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool, 6985 enum mlxsw_reg_sbxx_dir dir, bool clr, 6986 u32 min_buff, u32 max_buff) 6987 { 6988 MLXSW_REG_ZERO(sbpm, payload); 6989 mlxsw_reg_sbpm_local_port_set(payload, local_port); 6990 mlxsw_reg_sbpm_pool_set(payload, pool); 6991 mlxsw_reg_sbpm_dir_set(payload, dir); 6992 mlxsw_reg_sbpm_clr_set(payload, clr); 6993 mlxsw_reg_sbpm_min_buff_set(payload, min_buff); 6994 mlxsw_reg_sbpm_max_buff_set(payload, max_buff); 6995 } 6996 6997 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy, 6998 u32 *p_max_buff_occupancy) 6999 { 7000 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload); 7001 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload); 7002 } 7003 7004 /* SBMM - Shared Buffer Multicast Management Register 7005 * -------------------------------------------------- 7006 * The SBMM register configures and retrieves the shared buffer allocation 7007 * and configuration for MC packets according to Switch-Priority, including 7008 * the binding to pool and definition of the associated quota. 7009 */ 7010 #define MLXSW_REG_SBMM_ID 0xB004 7011 #define MLXSW_REG_SBMM_LEN 0x28 7012 7013 MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN); 7014 7015 /* reg_sbmm_prio 7016 * Switch Priority. 7017 * Access: Index 7018 */ 7019 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4); 7020 7021 /* reg_sbmm_min_buff 7022 * Minimum buffer size for the limiter, in cells. 7023 * Access: RW 7024 */ 7025 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24); 7026 7027 /* reg_sbmm_max_buff 7028 * When the pool associated to the port-pg/tclass is configured to 7029 * static, Maximum buffer size for the limiter configured in cells. 7030 * When the pool associated to the port-pg/tclass is configured to 7031 * dynamic, the max_buff holds the "alpha" parameter, supporting 7032 * the following values: 7033 * 0: 0 7034 * i: (1/128)*2^(i-1), for i=1..14 7035 * 0xFF: Infinity 7036 * Access: RW 7037 */ 7038 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24); 7039 7040 /* reg_sbmm_pool 7041 * Association of the port-priority to a pool. 7042 * Access: RW 7043 */ 7044 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4); 7045 7046 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff, 7047 u32 max_buff, u8 pool) 7048 { 7049 MLXSW_REG_ZERO(sbmm, payload); 7050 mlxsw_reg_sbmm_prio_set(payload, prio); 7051 mlxsw_reg_sbmm_min_buff_set(payload, min_buff); 7052 mlxsw_reg_sbmm_max_buff_set(payload, max_buff); 7053 mlxsw_reg_sbmm_pool_set(payload, pool); 7054 } 7055 7056 /* SBSR - Shared Buffer Status Register 7057 * ------------------------------------ 7058 * The SBSR register retrieves the shared buffer occupancy according to 7059 * Port-Pool. Note that this register enables reading a large amount of data. 7060 * It is the user's responsibility to limit the amount of data to ensure the 7061 * response can match the maximum transfer unit. In case the response exceeds 7062 * the maximum transport unit, it will be truncated with no special notice. 7063 */ 7064 #define MLXSW_REG_SBSR_ID 0xB005 7065 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */ 7066 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */ 7067 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120 7068 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \ 7069 MLXSW_REG_SBSR_REC_LEN * \ 7070 MLXSW_REG_SBSR_REC_MAX_COUNT) 7071 7072 MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN); 7073 7074 /* reg_sbsr_clr 7075 * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy 7076 * field is cleared (and a new max value is tracked from the time the clear 7077 * was performed). 7078 * Access: OP 7079 */ 7080 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1); 7081 7082 /* reg_sbsr_ingress_port_mask 7083 * Bit vector for all ingress network ports. 7084 * Indicates which of the ports (for which the relevant bit is set) 7085 * are affected by the set operation. Configuration of any other port 7086 * does not change. 7087 * Access: Index 7088 */ 7089 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1); 7090 7091 /* reg_sbsr_pg_buff_mask 7092 * Bit vector for all switch priority groups. 7093 * Indicates which of the priorities (for which the relevant bit is set) 7094 * are affected by the set operation. Configuration of any other priority 7095 * does not change. 7096 * Range is 0..cap_max_pg_buffers - 1 7097 * Access: Index 7098 */ 7099 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1); 7100 7101 /* reg_sbsr_egress_port_mask 7102 * Bit vector for all egress network ports. 7103 * Indicates which of the ports (for which the relevant bit is set) 7104 * are affected by the set operation. Configuration of any other port 7105 * does not change. 7106 * Access: Index 7107 */ 7108 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1); 7109 7110 /* reg_sbsr_tclass_mask 7111 * Bit vector for all traffic classes. 7112 * Indicates which of the traffic classes (for which the relevant bit is 7113 * set) are affected by the set operation. Configuration of any other 7114 * traffic class does not change. 7115 * Range is 0..cap_max_tclass - 1 7116 * Access: Index 7117 */ 7118 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1); 7119 7120 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr) 7121 { 7122 MLXSW_REG_ZERO(sbsr, payload); 7123 mlxsw_reg_sbsr_clr_set(payload, clr); 7124 } 7125 7126 /* reg_sbsr_rec_buff_occupancy 7127 * Current buffer occupancy in cells. 7128 * Access: RO 7129 */ 7130 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 7131 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false); 7132 7133 /* reg_sbsr_rec_max_buff_occupancy 7134 * Maximum value of buffer occupancy in cells monitored. Cleared by 7135 * writing to the clr field. 7136 * Access: RO 7137 */ 7138 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 7139 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false); 7140 7141 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index, 7142 u32 *p_buff_occupancy, 7143 u32 *p_max_buff_occupancy) 7144 { 7145 *p_buff_occupancy = 7146 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index); 7147 *p_max_buff_occupancy = 7148 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index); 7149 } 7150 7151 /* SBIB - Shared Buffer Internal Buffer Register 7152 * --------------------------------------------- 7153 * The SBIB register configures per port buffers for internal use. The internal 7154 * buffers consume memory on the port buffers (note that the port buffers are 7155 * used also by PBMC). 7156 * 7157 * For Spectrum this is used for egress mirroring. 7158 */ 7159 #define MLXSW_REG_SBIB_ID 0xB006 7160 #define MLXSW_REG_SBIB_LEN 0x10 7161 7162 MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN); 7163 7164 /* reg_sbib_local_port 7165 * Local port number 7166 * Not supported for CPU port and router port 7167 * Access: Index 7168 */ 7169 MLXSW_ITEM32(reg, sbib, local_port, 0x00, 16, 8); 7170 7171 /* reg_sbib_buff_size 7172 * Units represented in cells 7173 * Allowed range is 0 to (cap_max_headroom_size - 1) 7174 * Default is 0 7175 * Access: RW 7176 */ 7177 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24); 7178 7179 static inline void mlxsw_reg_sbib_pack(char *payload, u8 local_port, 7180 u32 buff_size) 7181 { 7182 MLXSW_REG_ZERO(sbib, payload); 7183 mlxsw_reg_sbib_local_port_set(payload, local_port); 7184 mlxsw_reg_sbib_buff_size_set(payload, buff_size); 7185 } 7186 7187 static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { 7188 MLXSW_REG(sgcr), 7189 MLXSW_REG(spad), 7190 MLXSW_REG(smid), 7191 MLXSW_REG(sspr), 7192 MLXSW_REG(sfdat), 7193 MLXSW_REG(sfd), 7194 MLXSW_REG(sfn), 7195 MLXSW_REG(spms), 7196 MLXSW_REG(spvid), 7197 MLXSW_REG(spvm), 7198 MLXSW_REG(spaft), 7199 MLXSW_REG(sfgc), 7200 MLXSW_REG(sftr), 7201 MLXSW_REG(sfdf), 7202 MLXSW_REG(sldr), 7203 MLXSW_REG(slcr), 7204 MLXSW_REG(slcor), 7205 MLXSW_REG(spmlr), 7206 MLXSW_REG(svfa), 7207 MLXSW_REG(svpe), 7208 MLXSW_REG(sfmr), 7209 MLXSW_REG(spvmlr), 7210 MLXSW_REG(ppbt), 7211 MLXSW_REG(pacl), 7212 MLXSW_REG(pagt), 7213 MLXSW_REG(ptar), 7214 MLXSW_REG(ppbs), 7215 MLXSW_REG(prcr), 7216 MLXSW_REG(pefa), 7217 MLXSW_REG(ptce2), 7218 MLXSW_REG(qpcr), 7219 MLXSW_REG(qtct), 7220 MLXSW_REG(qeec), 7221 MLXSW_REG(pmlp), 7222 MLXSW_REG(pmtu), 7223 MLXSW_REG(ptys), 7224 MLXSW_REG(ppad), 7225 MLXSW_REG(paos), 7226 MLXSW_REG(pfcc), 7227 MLXSW_REG(ppcnt), 7228 MLXSW_REG(plib), 7229 MLXSW_REG(pptb), 7230 MLXSW_REG(pbmc), 7231 MLXSW_REG(pspa), 7232 MLXSW_REG(htgt), 7233 MLXSW_REG(hpkt), 7234 MLXSW_REG(rgcr), 7235 MLXSW_REG(ritr), 7236 MLXSW_REG(rtar), 7237 MLXSW_REG(ratr), 7238 MLXSW_REG(rtdp), 7239 MLXSW_REG(ricnt), 7240 MLXSW_REG(rrcr), 7241 MLXSW_REG(ralta), 7242 MLXSW_REG(ralst), 7243 MLXSW_REG(raltb), 7244 MLXSW_REG(ralue), 7245 MLXSW_REG(rauht), 7246 MLXSW_REG(raleu), 7247 MLXSW_REG(rauhtd), 7248 MLXSW_REG(rigr2), 7249 MLXSW_REG(rmft2), 7250 MLXSW_REG(mfcr), 7251 MLXSW_REG(mfsc), 7252 MLXSW_REG(mfsm), 7253 MLXSW_REG(mfsl), 7254 MLXSW_REG(mtcap), 7255 MLXSW_REG(mtmp), 7256 MLXSW_REG(mcia), 7257 MLXSW_REG(mpat), 7258 MLXSW_REG(mpar), 7259 MLXSW_REG(mlcr), 7260 MLXSW_REG(mpsc), 7261 MLXSW_REG(mcqi), 7262 MLXSW_REG(mcc), 7263 MLXSW_REG(mcda), 7264 MLXSW_REG(mgpc), 7265 MLXSW_REG(sbpr), 7266 MLXSW_REG(sbcm), 7267 MLXSW_REG(sbpm), 7268 MLXSW_REG(sbmm), 7269 MLXSW_REG(sbsr), 7270 MLXSW_REG(sbib), 7271 }; 7272 7273 static inline const char *mlxsw_reg_id_str(u16 reg_id) 7274 { 7275 const struct mlxsw_reg_info *reg_info; 7276 int i; 7277 7278 for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) { 7279 reg_info = mlxsw_reg_infos[i]; 7280 if (reg_info->id == reg_id) 7281 return reg_info->name; 7282 } 7283 return "*UNKNOWN*"; 7284 } 7285 7286 /* PUDE - Port Up / Down Event 7287 * --------------------------- 7288 * Reports the operational state change of a port. 7289 */ 7290 #define MLXSW_REG_PUDE_LEN 0x10 7291 7292 /* reg_pude_swid 7293 * Switch partition ID with which to associate the port. 7294 * Access: Index 7295 */ 7296 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8); 7297 7298 /* reg_pude_local_port 7299 * Local port number. 7300 * Access: Index 7301 */ 7302 MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8); 7303 7304 /* reg_pude_admin_status 7305 * Port administrative state (the desired state). 7306 * 1 - Up. 7307 * 2 - Down. 7308 * 3 - Up once. This means that in case of link failure, the port won't go 7309 * into polling mode, but will wait to be re-enabled by software. 7310 * 4 - Disabled by system. Can only be set by hardware. 7311 * Access: RO 7312 */ 7313 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4); 7314 7315 /* reg_pude_oper_status 7316 * Port operatioanl state. 7317 * 1 - Up. 7318 * 2 - Down. 7319 * 3 - Down by port failure. This means that the device will not let the 7320 * port up again until explicitly specified by software. 7321 * Access: RO 7322 */ 7323 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4); 7324 7325 #endif 7326