1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #ifndef _MLXSW_REG_H 5 #define _MLXSW_REG_H 6 7 #include <linux/kernel.h> 8 #include <linux/string.h> 9 #include <linux/bitops.h> 10 #include <linux/if_vlan.h> 11 12 #include "item.h" 13 #include "port.h" 14 15 struct mlxsw_reg_info { 16 u16 id; 17 u16 len; /* In u8 */ 18 const char *name; 19 }; 20 21 #define MLXSW_REG_DEFINE(_name, _id, _len) \ 22 static const struct mlxsw_reg_info mlxsw_reg_##_name = { \ 23 .id = _id, \ 24 .len = _len, \ 25 .name = #_name, \ 26 } 27 28 #define MLXSW_REG(type) (&mlxsw_reg_##type) 29 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len 30 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len) 31 32 /* SGCR - Switch General Configuration Register 33 * -------------------------------------------- 34 * This register is used for configuration of the switch capabilities. 35 */ 36 #define MLXSW_REG_SGCR_ID 0x2000 37 #define MLXSW_REG_SGCR_LEN 0x10 38 39 MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN); 40 41 /* reg_sgcr_llb 42 * Link Local Broadcast (Default=0) 43 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast 44 * packets and ignore the IGMP snooping entries. 45 * Access: RW 46 */ 47 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1); 48 49 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb) 50 { 51 MLXSW_REG_ZERO(sgcr, payload); 52 mlxsw_reg_sgcr_llb_set(payload, !!llb); 53 } 54 55 /* SPAD - Switch Physical Address Register 56 * --------------------------------------- 57 * The SPAD register configures the switch physical MAC address. 58 */ 59 #define MLXSW_REG_SPAD_ID 0x2002 60 #define MLXSW_REG_SPAD_LEN 0x10 61 62 MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN); 63 64 /* reg_spad_base_mac 65 * Base MAC address for the switch partitions. 66 * Per switch partition MAC address is equal to: 67 * base_mac + swid 68 * Access: RW 69 */ 70 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6); 71 72 /* SMID - Switch Multicast ID 73 * -------------------------- 74 * The MID record maps from a MID (Multicast ID), which is a unique identifier 75 * of the multicast group within the stacking domain, into a list of local 76 * ports into which the packet is replicated. 77 */ 78 #define MLXSW_REG_SMID_ID 0x2007 79 #define MLXSW_REG_SMID_LEN 0x240 80 81 MLXSW_REG_DEFINE(smid, MLXSW_REG_SMID_ID, MLXSW_REG_SMID_LEN); 82 83 /* reg_smid_swid 84 * Switch partition ID. 85 * Access: Index 86 */ 87 MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8); 88 89 /* reg_smid_mid 90 * Multicast identifier - global identifier that represents the multicast group 91 * across all devices. 92 * Access: Index 93 */ 94 MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16); 95 96 /* reg_smid_port 97 * Local port memebership (1 bit per port). 98 * Access: RW 99 */ 100 MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1); 101 102 /* reg_smid_port_mask 103 * Local port mask (1 bit per port). 104 * Access: W 105 */ 106 MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1); 107 108 static inline void mlxsw_reg_smid_pack(char *payload, u16 mid, 109 u8 port, bool set) 110 { 111 MLXSW_REG_ZERO(smid, payload); 112 mlxsw_reg_smid_swid_set(payload, 0); 113 mlxsw_reg_smid_mid_set(payload, mid); 114 mlxsw_reg_smid_port_set(payload, port, set); 115 mlxsw_reg_smid_port_mask_set(payload, port, 1); 116 } 117 118 /* SSPR - Switch System Port Record Register 119 * ----------------------------------------- 120 * Configures the system port to local port mapping. 121 */ 122 #define MLXSW_REG_SSPR_ID 0x2008 123 #define MLXSW_REG_SSPR_LEN 0x8 124 125 MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN); 126 127 /* reg_sspr_m 128 * Master - if set, then the record describes the master system port. 129 * This is needed in case a local port is mapped into several system ports 130 * (for multipathing). That number will be reported as the source system 131 * port when packets are forwarded to the CPU. Only one master port is allowed 132 * per local port. 133 * 134 * Note: Must be set for Spectrum. 135 * Access: RW 136 */ 137 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1); 138 139 /* reg_sspr_local_port 140 * Local port number. 141 * 142 * Access: RW 143 */ 144 MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8); 145 146 /* reg_sspr_sub_port 147 * Virtual port within the physical port. 148 * Should be set to 0 when virtual ports are not enabled on the port. 149 * 150 * Access: RW 151 */ 152 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8); 153 154 /* reg_sspr_system_port 155 * Unique identifier within the stacking domain that represents all the ports 156 * that are available in the system (external ports). 157 * 158 * Currently, only single-ASIC configurations are supported, so we default to 159 * 1:1 mapping between system ports and local ports. 160 * Access: Index 161 */ 162 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16); 163 164 static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port) 165 { 166 MLXSW_REG_ZERO(sspr, payload); 167 mlxsw_reg_sspr_m_set(payload, 1); 168 mlxsw_reg_sspr_local_port_set(payload, local_port); 169 mlxsw_reg_sspr_sub_port_set(payload, 0); 170 mlxsw_reg_sspr_system_port_set(payload, local_port); 171 } 172 173 /* SFDAT - Switch Filtering Database Aging Time 174 * -------------------------------------------- 175 * Controls the Switch aging time. Aging time is able to be set per Switch 176 * Partition. 177 */ 178 #define MLXSW_REG_SFDAT_ID 0x2009 179 #define MLXSW_REG_SFDAT_LEN 0x8 180 181 MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN); 182 183 /* reg_sfdat_swid 184 * Switch partition ID. 185 * Access: Index 186 */ 187 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8); 188 189 /* reg_sfdat_age_time 190 * Aging time in seconds 191 * Min - 10 seconds 192 * Max - 1,000,000 seconds 193 * Default is 300 seconds. 194 * Access: RW 195 */ 196 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20); 197 198 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time) 199 { 200 MLXSW_REG_ZERO(sfdat, payload); 201 mlxsw_reg_sfdat_swid_set(payload, 0); 202 mlxsw_reg_sfdat_age_time_set(payload, age_time); 203 } 204 205 /* SFD - Switch Filtering Database 206 * ------------------------------- 207 * The following register defines the access to the filtering database. 208 * The register supports querying, adding, removing and modifying the database. 209 * The access is optimized for bulk updates in which case more than one 210 * FDB record is present in the same command. 211 */ 212 #define MLXSW_REG_SFD_ID 0x200A 213 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */ 214 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */ 215 #define MLXSW_REG_SFD_REC_MAX_COUNT 64 216 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \ 217 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT) 218 219 MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN); 220 221 /* reg_sfd_swid 222 * Switch partition ID for queries. Reserved on Write. 223 * Access: Index 224 */ 225 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8); 226 227 enum mlxsw_reg_sfd_op { 228 /* Dump entire FDB a (process according to record_locator) */ 229 MLXSW_REG_SFD_OP_QUERY_DUMP = 0, 230 /* Query records by {MAC, VID/FID} value */ 231 MLXSW_REG_SFD_OP_QUERY_QUERY = 1, 232 /* Query and clear activity. Query records by {MAC, VID/FID} value */ 233 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2, 234 /* Test. Response indicates if each of the records could be 235 * added to the FDB. 236 */ 237 MLXSW_REG_SFD_OP_WRITE_TEST = 0, 238 /* Add/modify. Aged-out records cannot be added. This command removes 239 * the learning notification of the {MAC, VID/FID}. Response includes 240 * the entries that were added to the FDB. 241 */ 242 MLXSW_REG_SFD_OP_WRITE_EDIT = 1, 243 /* Remove record by {MAC, VID/FID}. This command also removes 244 * the learning notification and aged-out notifications 245 * of the {MAC, VID/FID}. The response provides current (pre-removal) 246 * entries as non-aged-out. 247 */ 248 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2, 249 /* Remove learned notification by {MAC, VID/FID}. The response provides 250 * the removed learning notification. 251 */ 252 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2, 253 }; 254 255 /* reg_sfd_op 256 * Operation. 257 * Access: OP 258 */ 259 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2); 260 261 /* reg_sfd_record_locator 262 * Used for querying the FDB. Use record_locator=0 to initiate the 263 * query. When a record is returned, a new record_locator is 264 * returned to be used in the subsequent query. 265 * Reserved for database update. 266 * Access: Index 267 */ 268 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30); 269 270 /* reg_sfd_num_rec 271 * Request: Number of records to read/add/modify/remove 272 * Response: Number of records read/added/replaced/removed 273 * See above description for more details. 274 * Ranges 0..64 275 * Access: RW 276 */ 277 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8); 278 279 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op, 280 u32 record_locator) 281 { 282 MLXSW_REG_ZERO(sfd, payload); 283 mlxsw_reg_sfd_op_set(payload, op); 284 mlxsw_reg_sfd_record_locator_set(payload, record_locator); 285 } 286 287 /* reg_sfd_rec_swid 288 * Switch partition ID. 289 * Access: Index 290 */ 291 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8, 292 MLXSW_REG_SFD_REC_LEN, 0x00, false); 293 294 enum mlxsw_reg_sfd_rec_type { 295 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0, 296 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1, 297 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2, 298 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL = 0xC, 299 }; 300 301 /* reg_sfd_rec_type 302 * FDB record type. 303 * Access: RW 304 */ 305 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4, 306 MLXSW_REG_SFD_REC_LEN, 0x00, false); 307 308 enum mlxsw_reg_sfd_rec_policy { 309 /* Replacement disabled, aging disabled. */ 310 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0, 311 /* (mlag remote): Replacement enabled, aging disabled, 312 * learning notification enabled on this port. 313 */ 314 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1, 315 /* (ingress device): Replacement enabled, aging enabled. */ 316 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3, 317 }; 318 319 /* reg_sfd_rec_policy 320 * Policy. 321 * Access: RW 322 */ 323 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2, 324 MLXSW_REG_SFD_REC_LEN, 0x00, false); 325 326 /* reg_sfd_rec_a 327 * Activity. Set for new static entries. Set for static entries if a frame SMAC 328 * lookup hits on the entry. 329 * To clear the a bit, use "query and clear activity" op. 330 * Access: RO 331 */ 332 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1, 333 MLXSW_REG_SFD_REC_LEN, 0x00, false); 334 335 /* reg_sfd_rec_mac 336 * MAC address. 337 * Access: Index 338 */ 339 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6, 340 MLXSW_REG_SFD_REC_LEN, 0x02); 341 342 enum mlxsw_reg_sfd_rec_action { 343 /* forward */ 344 MLXSW_REG_SFD_REC_ACTION_NOP = 0, 345 /* forward and trap, trap_id is FDB_TRAP */ 346 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1, 347 /* trap and do not forward, trap_id is FDB_TRAP */ 348 MLXSW_REG_SFD_REC_ACTION_TRAP = 2, 349 /* forward to IP router */ 350 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3, 351 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15, 352 }; 353 354 /* reg_sfd_rec_action 355 * Action to apply on the packet. 356 * Note: Dynamic entries can only be configured with NOP action. 357 * Access: RW 358 */ 359 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4, 360 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 361 362 /* reg_sfd_uc_sub_port 363 * VEPA channel on local port. 364 * Valid only if local port is a non-stacking port. Must be 0 if multichannel 365 * VEPA is not enabled. 366 * Access: RW 367 */ 368 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 369 MLXSW_REG_SFD_REC_LEN, 0x08, false); 370 371 /* reg_sfd_uc_fid_vid 372 * Filtering ID or VLAN ID 373 * For SwitchX and SwitchX-2: 374 * - Dynamic entries (policy 2,3) use FID 375 * - Static entries (policy 0) use VID 376 * - When independent learning is configured, VID=FID 377 * For Spectrum: use FID for both Dynamic and Static entries. 378 * VID should not be used. 379 * Access: Index 380 */ 381 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 382 MLXSW_REG_SFD_REC_LEN, 0x08, false); 383 384 /* reg_sfd_uc_system_port 385 * Unique port identifier for the final destination of the packet. 386 * Access: RW 387 */ 388 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16, 389 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 390 391 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index, 392 enum mlxsw_reg_sfd_rec_type rec_type, 393 const char *mac, 394 enum mlxsw_reg_sfd_rec_action action) 395 { 396 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload); 397 398 if (rec_index >= num_rec) 399 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1); 400 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0); 401 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type); 402 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac); 403 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action); 404 } 405 406 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index, 407 enum mlxsw_reg_sfd_rec_policy policy, 408 const char *mac, u16 fid_vid, 409 enum mlxsw_reg_sfd_rec_action action, 410 u8 local_port) 411 { 412 mlxsw_reg_sfd_rec_pack(payload, rec_index, 413 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action); 414 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 415 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0); 416 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid); 417 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port); 418 } 419 420 static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index, 421 char *mac, u16 *p_fid_vid, 422 u8 *p_local_port) 423 { 424 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 425 *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index); 426 *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index); 427 } 428 429 /* reg_sfd_uc_lag_sub_port 430 * LAG sub port. 431 * Must be 0 if multichannel VEPA is not enabled. 432 * Access: RW 433 */ 434 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 435 MLXSW_REG_SFD_REC_LEN, 0x08, false); 436 437 /* reg_sfd_uc_lag_fid_vid 438 * Filtering ID or VLAN ID 439 * For SwitchX and SwitchX-2: 440 * - Dynamic entries (policy 2,3) use FID 441 * - Static entries (policy 0) use VID 442 * - When independent learning is configured, VID=FID 443 * For Spectrum: use FID for both Dynamic and Static entries. 444 * VID should not be used. 445 * Access: Index 446 */ 447 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 448 MLXSW_REG_SFD_REC_LEN, 0x08, false); 449 450 /* reg_sfd_uc_lag_lag_vid 451 * Indicates VID in case of vFIDs. Reserved for FIDs. 452 * Access: RW 453 */ 454 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, 455 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 456 457 /* reg_sfd_uc_lag_lag_id 458 * LAG Identifier - pointer into the LAG descriptor table. 459 * Access: RW 460 */ 461 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10, 462 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 463 464 static inline void 465 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index, 466 enum mlxsw_reg_sfd_rec_policy policy, 467 const char *mac, u16 fid_vid, 468 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid, 469 u16 lag_id) 470 { 471 mlxsw_reg_sfd_rec_pack(payload, rec_index, 472 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG, 473 mac, action); 474 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 475 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0); 476 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid); 477 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid); 478 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id); 479 } 480 481 static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index, 482 char *mac, u16 *p_vid, 483 u16 *p_lag_id) 484 { 485 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 486 *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index); 487 *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index); 488 } 489 490 /* reg_sfd_mc_pgi 491 * 492 * Multicast port group index - index into the port group table. 493 * Value 0x1FFF indicates the pgi should point to the MID entry. 494 * For Spectrum this value must be set to 0x1FFF 495 * Access: RW 496 */ 497 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13, 498 MLXSW_REG_SFD_REC_LEN, 0x08, false); 499 500 /* reg_sfd_mc_fid_vid 501 * 502 * Filtering ID or VLAN ID 503 * Access: Index 504 */ 505 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 506 MLXSW_REG_SFD_REC_LEN, 0x08, false); 507 508 /* reg_sfd_mc_mid 509 * 510 * Multicast identifier - global identifier that represents the multicast 511 * group across all devices. 512 * Access: RW 513 */ 514 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 515 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 516 517 static inline void 518 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index, 519 const char *mac, u16 fid_vid, 520 enum mlxsw_reg_sfd_rec_action action, u16 mid) 521 { 522 mlxsw_reg_sfd_rec_pack(payload, rec_index, 523 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action); 524 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF); 525 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid); 526 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid); 527 } 528 529 /* reg_sfd_uc_tunnel_uip_msb 530 * When protocol is IPv4, the most significant byte of the underlay IPv4 531 * destination IP. 532 * When protocol is IPv6, reserved. 533 * Access: RW 534 */ 535 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24, 536 8, MLXSW_REG_SFD_REC_LEN, 0x08, false); 537 538 /* reg_sfd_uc_tunnel_fid 539 * Filtering ID. 540 * Access: Index 541 */ 542 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 543 MLXSW_REG_SFD_REC_LEN, 0x08, false); 544 545 enum mlxsw_reg_sfd_uc_tunnel_protocol { 546 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4, 547 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6, 548 }; 549 550 /* reg_sfd_uc_tunnel_protocol 551 * IP protocol. 552 * Access: RW 553 */ 554 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27, 555 1, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 556 557 /* reg_sfd_uc_tunnel_uip_lsb 558 * When protocol is IPv4, the least significant bytes of the underlay 559 * IPv4 destination IP. 560 * When protocol is IPv6, pointer to the underlay IPv6 destination IP 561 * which is configured by RIPS. 562 * Access: RW 563 */ 564 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0, 565 24, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 566 567 static inline void 568 mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index, 569 enum mlxsw_reg_sfd_rec_policy policy, 570 const char *mac, u16 fid, 571 enum mlxsw_reg_sfd_rec_action action, u32 uip, 572 enum mlxsw_reg_sfd_uc_tunnel_protocol proto) 573 { 574 mlxsw_reg_sfd_rec_pack(payload, rec_index, 575 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL, mac, 576 action); 577 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 578 mlxsw_reg_sfd_uc_tunnel_uip_msb_set(payload, rec_index, uip >> 24); 579 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip); 580 mlxsw_reg_sfd_uc_tunnel_fid_set(payload, rec_index, fid); 581 mlxsw_reg_sfd_uc_tunnel_protocol_set(payload, rec_index, proto); 582 } 583 584 /* SFN - Switch FDB Notification Register 585 * ------------------------------------------- 586 * The switch provides notifications on newly learned FDB entries and 587 * aged out entries. The notifications can be polled by software. 588 */ 589 #define MLXSW_REG_SFN_ID 0x200B 590 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */ 591 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */ 592 #define MLXSW_REG_SFN_REC_MAX_COUNT 64 593 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \ 594 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT) 595 596 MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN); 597 598 /* reg_sfn_swid 599 * Switch partition ID. 600 * Access: Index 601 */ 602 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8); 603 604 /* reg_sfn_end 605 * Forces the current session to end. 606 * Access: OP 607 */ 608 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1); 609 610 /* reg_sfn_num_rec 611 * Request: Number of learned notifications and aged-out notification 612 * records requested. 613 * Response: Number of notification records returned (must be smaller 614 * than or equal to the value requested) 615 * Ranges 0..64 616 * Access: OP 617 */ 618 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8); 619 620 static inline void mlxsw_reg_sfn_pack(char *payload) 621 { 622 MLXSW_REG_ZERO(sfn, payload); 623 mlxsw_reg_sfn_swid_set(payload, 0); 624 mlxsw_reg_sfn_end_set(payload, 0); 625 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT); 626 } 627 628 /* reg_sfn_rec_swid 629 * Switch partition ID. 630 * Access: RO 631 */ 632 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8, 633 MLXSW_REG_SFN_REC_LEN, 0x00, false); 634 635 enum mlxsw_reg_sfn_rec_type { 636 /* MAC addresses learned on a regular port. */ 637 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5, 638 /* MAC addresses learned on a LAG port. */ 639 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6, 640 /* Aged-out MAC address on a regular port. */ 641 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7, 642 /* Aged-out MAC address on a LAG port. */ 643 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8, 644 /* Learned unicast tunnel record. */ 645 MLXSW_REG_SFN_REC_TYPE_LEARNED_UNICAST_TUNNEL = 0xD, 646 /* Aged-out unicast tunnel record. */ 647 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_UNICAST_TUNNEL = 0xE, 648 }; 649 650 /* reg_sfn_rec_type 651 * Notification record type. 652 * Access: RO 653 */ 654 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4, 655 MLXSW_REG_SFN_REC_LEN, 0x00, false); 656 657 /* reg_sfn_rec_mac 658 * MAC address. 659 * Access: RO 660 */ 661 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6, 662 MLXSW_REG_SFN_REC_LEN, 0x02); 663 664 /* reg_sfn_mac_sub_port 665 * VEPA channel on the local port. 666 * 0 if multichannel VEPA is not enabled. 667 * Access: RO 668 */ 669 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8, 670 MLXSW_REG_SFN_REC_LEN, 0x08, false); 671 672 /* reg_sfn_mac_fid 673 * Filtering identifier. 674 * Access: RO 675 */ 676 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16, 677 MLXSW_REG_SFN_REC_LEN, 0x08, false); 678 679 /* reg_sfn_mac_system_port 680 * Unique port identifier for the final destination of the packet. 681 * Access: RO 682 */ 683 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16, 684 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 685 686 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index, 687 char *mac, u16 *p_vid, 688 u8 *p_local_port) 689 { 690 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 691 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 692 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index); 693 } 694 695 /* reg_sfn_mac_lag_lag_id 696 * LAG ID (pointer into the LAG descriptor table). 697 * Access: RO 698 */ 699 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10, 700 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 701 702 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index, 703 char *mac, u16 *p_vid, 704 u16 *p_lag_id) 705 { 706 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 707 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 708 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index); 709 } 710 711 /* reg_sfn_uc_tunnel_uip_msb 712 * When protocol is IPv4, the most significant byte of the underlay IPv4 713 * address of the remote VTEP. 714 * When protocol is IPv6, reserved. 715 * Access: RO 716 */ 717 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_msb, MLXSW_REG_SFN_BASE_LEN, 24, 718 8, MLXSW_REG_SFN_REC_LEN, 0x08, false); 719 720 enum mlxsw_reg_sfn_uc_tunnel_protocol { 721 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV4, 722 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV6, 723 }; 724 725 /* reg_sfn_uc_tunnel_protocol 726 * IP protocol. 727 * Access: RO 728 */ 729 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_protocol, MLXSW_REG_SFN_BASE_LEN, 27, 730 1, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 731 732 /* reg_sfn_uc_tunnel_uip_lsb 733 * When protocol is IPv4, the least significant bytes of the underlay 734 * IPv4 address of the remote VTEP. 735 * When protocol is IPv6, ipv6_id to be queried from TNIPSD. 736 * Access: RO 737 */ 738 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0, 739 24, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 740 741 enum mlxsw_reg_sfn_tunnel_port { 742 MLXSW_REG_SFN_TUNNEL_PORT_NVE, 743 MLXSW_REG_SFN_TUNNEL_PORT_VPLS, 744 MLXSW_REG_SFN_TUNNEL_FLEX_TUNNEL0, 745 MLXSW_REG_SFN_TUNNEL_FLEX_TUNNEL1, 746 }; 747 748 /* reg_sfn_uc_tunnel_port 749 * Tunnel port. 750 * Reserved on Spectrum. 751 * Access: RO 752 */ 753 MLXSW_ITEM32_INDEXED(reg, sfn, tunnel_port, MLXSW_REG_SFN_BASE_LEN, 0, 4, 754 MLXSW_REG_SFN_REC_LEN, 0x10, false); 755 756 static inline void 757 mlxsw_reg_sfn_uc_tunnel_unpack(char *payload, int rec_index, char *mac, 758 u16 *p_fid, u32 *p_uip, 759 enum mlxsw_reg_sfn_uc_tunnel_protocol *p_proto) 760 { 761 u32 uip_msb, uip_lsb; 762 763 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 764 *p_fid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 765 uip_msb = mlxsw_reg_sfn_uc_tunnel_uip_msb_get(payload, rec_index); 766 uip_lsb = mlxsw_reg_sfn_uc_tunnel_uip_lsb_get(payload, rec_index); 767 *p_uip = uip_msb << 24 | uip_lsb; 768 *p_proto = mlxsw_reg_sfn_uc_tunnel_protocol_get(payload, rec_index); 769 } 770 771 /* SPMS - Switch Port MSTP/RSTP State Register 772 * ------------------------------------------- 773 * Configures the spanning tree state of a physical port. 774 */ 775 #define MLXSW_REG_SPMS_ID 0x200D 776 #define MLXSW_REG_SPMS_LEN 0x404 777 778 MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN); 779 780 /* reg_spms_local_port 781 * Local port number. 782 * Access: Index 783 */ 784 MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8); 785 786 enum mlxsw_reg_spms_state { 787 MLXSW_REG_SPMS_STATE_NO_CHANGE, 788 MLXSW_REG_SPMS_STATE_DISCARDING, 789 MLXSW_REG_SPMS_STATE_LEARNING, 790 MLXSW_REG_SPMS_STATE_FORWARDING, 791 }; 792 793 /* reg_spms_state 794 * Spanning tree state of each VLAN ID (VID) of the local port. 795 * 0 - Do not change spanning tree state (used only when writing). 796 * 1 - Discarding. No learning or forwarding to/from this port (default). 797 * 2 - Learning. Port is learning, but not forwarding. 798 * 3 - Forwarding. Port is learning and forwarding. 799 * Access: RW 800 */ 801 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2); 802 803 static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port) 804 { 805 MLXSW_REG_ZERO(spms, payload); 806 mlxsw_reg_spms_local_port_set(payload, local_port); 807 } 808 809 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid, 810 enum mlxsw_reg_spms_state state) 811 { 812 mlxsw_reg_spms_state_set(payload, vid, state); 813 } 814 815 /* SPVID - Switch Port VID 816 * ----------------------- 817 * The switch port VID configures the default VID for a port. 818 */ 819 #define MLXSW_REG_SPVID_ID 0x200E 820 #define MLXSW_REG_SPVID_LEN 0x08 821 822 MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN); 823 824 /* reg_spvid_local_port 825 * Local port number. 826 * Access: Index 827 */ 828 MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8); 829 830 /* reg_spvid_sub_port 831 * Virtual port within the physical port. 832 * Should be set to 0 when virtual ports are not enabled on the port. 833 * Access: Index 834 */ 835 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8); 836 837 /* reg_spvid_et_vlan 838 * EtherType used for when VLAN is pushed at ingress (for untagged 839 * packets or for QinQ push mode). 840 * 0: ether_type0 - (default) 841 * 1: ether_type1 842 * 2: ether_type2 - Reserved when Spectrum-1, supported by Spectrum-2 843 * Ethertype IDs are configured by SVER. 844 * Access: RW 845 */ 846 MLXSW_ITEM32(reg, spvid, et_vlan, 0x04, 16, 2); 847 848 /* reg_spvid_pvid 849 * Port default VID 850 * Access: RW 851 */ 852 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12); 853 854 static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid, 855 u8 et_vlan) 856 { 857 MLXSW_REG_ZERO(spvid, payload); 858 mlxsw_reg_spvid_local_port_set(payload, local_port); 859 mlxsw_reg_spvid_pvid_set(payload, pvid); 860 mlxsw_reg_spvid_et_vlan_set(payload, et_vlan); 861 } 862 863 /* SPVM - Switch Port VLAN Membership 864 * ---------------------------------- 865 * The Switch Port VLAN Membership register configures the VLAN membership 866 * of a port in a VLAN denoted by VID. VLAN membership is managed per 867 * virtual port. The register can be used to add and remove VID(s) from a port. 868 */ 869 #define MLXSW_REG_SPVM_ID 0x200F 870 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */ 871 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */ 872 #define MLXSW_REG_SPVM_REC_MAX_COUNT 255 873 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \ 874 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT) 875 876 MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN); 877 878 /* reg_spvm_pt 879 * Priority tagged. If this bit is set, packets forwarded to the port with 880 * untagged VLAN membership (u bit is set) will be tagged with priority tag 881 * (VID=0) 882 * Access: RW 883 */ 884 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1); 885 886 /* reg_spvm_pte 887 * Priority Tagged Update Enable. On Write operations, if this bit is cleared, 888 * the pt bit will NOT be updated. To update the pt bit, pte must be set. 889 * Access: WO 890 */ 891 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1); 892 893 /* reg_spvm_local_port 894 * Local port number. 895 * Access: Index 896 */ 897 MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8); 898 899 /* reg_spvm_sub_port 900 * Virtual port within the physical port. 901 * Should be set to 0 when virtual ports are not enabled on the port. 902 * Access: Index 903 */ 904 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8); 905 906 /* reg_spvm_num_rec 907 * Number of records to update. Each record contains: i, e, u, vid. 908 * Access: OP 909 */ 910 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8); 911 912 /* reg_spvm_rec_i 913 * Ingress membership in VLAN ID. 914 * Access: Index 915 */ 916 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i, 917 MLXSW_REG_SPVM_BASE_LEN, 14, 1, 918 MLXSW_REG_SPVM_REC_LEN, 0, false); 919 920 /* reg_spvm_rec_e 921 * Egress membership in VLAN ID. 922 * Access: Index 923 */ 924 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e, 925 MLXSW_REG_SPVM_BASE_LEN, 13, 1, 926 MLXSW_REG_SPVM_REC_LEN, 0, false); 927 928 /* reg_spvm_rec_u 929 * Untagged - port is an untagged member - egress transmission uses untagged 930 * frames on VID<n> 931 * Access: Index 932 */ 933 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u, 934 MLXSW_REG_SPVM_BASE_LEN, 12, 1, 935 MLXSW_REG_SPVM_REC_LEN, 0, false); 936 937 /* reg_spvm_rec_vid 938 * Egress membership in VLAN ID. 939 * Access: Index 940 */ 941 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid, 942 MLXSW_REG_SPVM_BASE_LEN, 0, 12, 943 MLXSW_REG_SPVM_REC_LEN, 0, false); 944 945 static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port, 946 u16 vid_begin, u16 vid_end, 947 bool is_member, bool untagged) 948 { 949 int size = vid_end - vid_begin + 1; 950 int i; 951 952 MLXSW_REG_ZERO(spvm, payload); 953 mlxsw_reg_spvm_local_port_set(payload, local_port); 954 mlxsw_reg_spvm_num_rec_set(payload, size); 955 956 for (i = 0; i < size; i++) { 957 mlxsw_reg_spvm_rec_i_set(payload, i, is_member); 958 mlxsw_reg_spvm_rec_e_set(payload, i, is_member); 959 mlxsw_reg_spvm_rec_u_set(payload, i, untagged); 960 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i); 961 } 962 } 963 964 /* SPAFT - Switch Port Acceptable Frame Types 965 * ------------------------------------------ 966 * The Switch Port Acceptable Frame Types register configures the frame 967 * admittance of the port. 968 */ 969 #define MLXSW_REG_SPAFT_ID 0x2010 970 #define MLXSW_REG_SPAFT_LEN 0x08 971 972 MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN); 973 974 /* reg_spaft_local_port 975 * Local port number. 976 * Access: Index 977 * 978 * Note: CPU port is not supported (all tag types are allowed). 979 */ 980 MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8); 981 982 /* reg_spaft_sub_port 983 * Virtual port within the physical port. 984 * Should be set to 0 when virtual ports are not enabled on the port. 985 * Access: RW 986 */ 987 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8); 988 989 /* reg_spaft_allow_untagged 990 * When set, untagged frames on the ingress are allowed (default). 991 * Access: RW 992 */ 993 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1); 994 995 /* reg_spaft_allow_prio_tagged 996 * When set, priority tagged frames on the ingress are allowed (default). 997 * Access: RW 998 */ 999 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1); 1000 1001 /* reg_spaft_allow_tagged 1002 * When set, tagged frames on the ingress are allowed (default). 1003 * Access: RW 1004 */ 1005 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1); 1006 1007 static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port, 1008 bool allow_untagged) 1009 { 1010 MLXSW_REG_ZERO(spaft, payload); 1011 mlxsw_reg_spaft_local_port_set(payload, local_port); 1012 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged); 1013 mlxsw_reg_spaft_allow_prio_tagged_set(payload, allow_untagged); 1014 mlxsw_reg_spaft_allow_tagged_set(payload, true); 1015 } 1016 1017 /* SFGC - Switch Flooding Group Configuration 1018 * ------------------------------------------ 1019 * The following register controls the association of flooding tables and MIDs 1020 * to packet types used for flooding. 1021 */ 1022 #define MLXSW_REG_SFGC_ID 0x2011 1023 #define MLXSW_REG_SFGC_LEN 0x10 1024 1025 MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN); 1026 1027 enum mlxsw_reg_sfgc_type { 1028 MLXSW_REG_SFGC_TYPE_BROADCAST, 1029 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST, 1030 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4, 1031 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6, 1032 MLXSW_REG_SFGC_TYPE_RESERVED, 1033 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP, 1034 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL, 1035 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST, 1036 MLXSW_REG_SFGC_TYPE_MAX, 1037 }; 1038 1039 /* reg_sfgc_type 1040 * The traffic type to reach the flooding table. 1041 * Access: Index 1042 */ 1043 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4); 1044 1045 enum mlxsw_reg_sfgc_bridge_type { 1046 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0, 1047 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1, 1048 }; 1049 1050 /* reg_sfgc_bridge_type 1051 * Access: Index 1052 * 1053 * Note: SwitchX-2 only supports 802.1Q mode. 1054 */ 1055 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3); 1056 1057 enum mlxsw_flood_table_type { 1058 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1, 1059 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2, 1060 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0, 1061 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3, 1062 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4, 1063 }; 1064 1065 /* reg_sfgc_table_type 1066 * See mlxsw_flood_table_type 1067 * Access: RW 1068 * 1069 * Note: FID offset and FID types are not supported in SwitchX-2. 1070 */ 1071 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3); 1072 1073 /* reg_sfgc_flood_table 1074 * Flooding table index to associate with the specific type on the specific 1075 * switch partition. 1076 * Access: RW 1077 */ 1078 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6); 1079 1080 /* reg_sfgc_mid 1081 * The multicast ID for the swid. Not supported for Spectrum 1082 * Access: RW 1083 */ 1084 MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16); 1085 1086 /* reg_sfgc_counter_set_type 1087 * Counter Set Type for flow counters. 1088 * Access: RW 1089 */ 1090 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8); 1091 1092 /* reg_sfgc_counter_index 1093 * Counter Index for flow counters. 1094 * Access: RW 1095 */ 1096 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24); 1097 1098 static inline void 1099 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type, 1100 enum mlxsw_reg_sfgc_bridge_type bridge_type, 1101 enum mlxsw_flood_table_type table_type, 1102 unsigned int flood_table) 1103 { 1104 MLXSW_REG_ZERO(sfgc, payload); 1105 mlxsw_reg_sfgc_type_set(payload, type); 1106 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type); 1107 mlxsw_reg_sfgc_table_type_set(payload, table_type); 1108 mlxsw_reg_sfgc_flood_table_set(payload, flood_table); 1109 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID); 1110 } 1111 1112 /* SFTR - Switch Flooding Table Register 1113 * ------------------------------------- 1114 * The switch flooding table is used for flooding packet replication. The table 1115 * defines a bit mask of ports for packet replication. 1116 */ 1117 #define MLXSW_REG_SFTR_ID 0x2012 1118 #define MLXSW_REG_SFTR_LEN 0x420 1119 1120 MLXSW_REG_DEFINE(sftr, MLXSW_REG_SFTR_ID, MLXSW_REG_SFTR_LEN); 1121 1122 /* reg_sftr_swid 1123 * Switch partition ID with which to associate the port. 1124 * Access: Index 1125 */ 1126 MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8); 1127 1128 /* reg_sftr_flood_table 1129 * Flooding table index to associate with the specific type on the specific 1130 * switch partition. 1131 * Access: Index 1132 */ 1133 MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6); 1134 1135 /* reg_sftr_index 1136 * Index. Used as an index into the Flooding Table in case the table is 1137 * configured to use VID / FID or FID Offset. 1138 * Access: Index 1139 */ 1140 MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16); 1141 1142 /* reg_sftr_table_type 1143 * See mlxsw_flood_table_type 1144 * Access: RW 1145 */ 1146 MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3); 1147 1148 /* reg_sftr_range 1149 * Range of entries to update 1150 * Access: Index 1151 */ 1152 MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16); 1153 1154 /* reg_sftr_port 1155 * Local port membership (1 bit per port). 1156 * Access: RW 1157 */ 1158 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1); 1159 1160 /* reg_sftr_cpu_port_mask 1161 * CPU port mask (1 bit per port). 1162 * Access: W 1163 */ 1164 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1); 1165 1166 static inline void mlxsw_reg_sftr_pack(char *payload, 1167 unsigned int flood_table, 1168 unsigned int index, 1169 enum mlxsw_flood_table_type table_type, 1170 unsigned int range, u8 port, bool set) 1171 { 1172 MLXSW_REG_ZERO(sftr, payload); 1173 mlxsw_reg_sftr_swid_set(payload, 0); 1174 mlxsw_reg_sftr_flood_table_set(payload, flood_table); 1175 mlxsw_reg_sftr_index_set(payload, index); 1176 mlxsw_reg_sftr_table_type_set(payload, table_type); 1177 mlxsw_reg_sftr_range_set(payload, range); 1178 mlxsw_reg_sftr_port_set(payload, port, set); 1179 mlxsw_reg_sftr_port_mask_set(payload, port, 1); 1180 } 1181 1182 /* SFDF - Switch Filtering DB Flush 1183 * -------------------------------- 1184 * The switch filtering DB flush register is used to flush the FDB. 1185 * Note that FDB notifications are flushed as well. 1186 */ 1187 #define MLXSW_REG_SFDF_ID 0x2013 1188 #define MLXSW_REG_SFDF_LEN 0x14 1189 1190 MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN); 1191 1192 /* reg_sfdf_swid 1193 * Switch partition ID. 1194 * Access: Index 1195 */ 1196 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8); 1197 1198 enum mlxsw_reg_sfdf_flush_type { 1199 MLXSW_REG_SFDF_FLUSH_PER_SWID, 1200 MLXSW_REG_SFDF_FLUSH_PER_FID, 1201 MLXSW_REG_SFDF_FLUSH_PER_PORT, 1202 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID, 1203 MLXSW_REG_SFDF_FLUSH_PER_LAG, 1204 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID, 1205 MLXSW_REG_SFDF_FLUSH_PER_NVE, 1206 MLXSW_REG_SFDF_FLUSH_PER_NVE_AND_FID, 1207 }; 1208 1209 /* reg_sfdf_flush_type 1210 * Flush type. 1211 * 0 - All SWID dynamic entries are flushed. 1212 * 1 - All FID dynamic entries are flushed. 1213 * 2 - All dynamic entries pointing to port are flushed. 1214 * 3 - All FID dynamic entries pointing to port are flushed. 1215 * 4 - All dynamic entries pointing to LAG are flushed. 1216 * 5 - All FID dynamic entries pointing to LAG are flushed. 1217 * 6 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1218 * flushed. 1219 * 7 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1220 * flushed, per FID. 1221 * Access: RW 1222 */ 1223 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4); 1224 1225 /* reg_sfdf_flush_static 1226 * Static. 1227 * 0 - Flush only dynamic entries. 1228 * 1 - Flush both dynamic and static entries. 1229 * Access: RW 1230 */ 1231 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1); 1232 1233 static inline void mlxsw_reg_sfdf_pack(char *payload, 1234 enum mlxsw_reg_sfdf_flush_type type) 1235 { 1236 MLXSW_REG_ZERO(sfdf, payload); 1237 mlxsw_reg_sfdf_flush_type_set(payload, type); 1238 mlxsw_reg_sfdf_flush_static_set(payload, true); 1239 } 1240 1241 /* reg_sfdf_fid 1242 * FID to flush. 1243 * Access: RW 1244 */ 1245 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16); 1246 1247 /* reg_sfdf_system_port 1248 * Port to flush. 1249 * Access: RW 1250 */ 1251 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16); 1252 1253 /* reg_sfdf_port_fid_system_port 1254 * Port to flush, pointed to by FID. 1255 * Access: RW 1256 */ 1257 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16); 1258 1259 /* reg_sfdf_lag_id 1260 * LAG ID to flush. 1261 * Access: RW 1262 */ 1263 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10); 1264 1265 /* reg_sfdf_lag_fid_lag_id 1266 * LAG ID to flush, pointed to by FID. 1267 * Access: RW 1268 */ 1269 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10); 1270 1271 /* SLDR - Switch LAG Descriptor Register 1272 * ----------------------------------------- 1273 * The switch LAG descriptor register is populated by LAG descriptors. 1274 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to 1275 * max_lag-1. 1276 */ 1277 #define MLXSW_REG_SLDR_ID 0x2014 1278 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */ 1279 1280 MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN); 1281 1282 enum mlxsw_reg_sldr_op { 1283 /* Indicates a creation of a new LAG-ID, lag_id must be valid */ 1284 MLXSW_REG_SLDR_OP_LAG_CREATE, 1285 MLXSW_REG_SLDR_OP_LAG_DESTROY, 1286 /* Ports that appear in the list have the Distributor enabled */ 1287 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST, 1288 /* Removes ports from the disributor list */ 1289 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST, 1290 }; 1291 1292 /* reg_sldr_op 1293 * Operation. 1294 * Access: RW 1295 */ 1296 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3); 1297 1298 /* reg_sldr_lag_id 1299 * LAG identifier. The lag_id is the index into the LAG descriptor table. 1300 * Access: Index 1301 */ 1302 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10); 1303 1304 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id) 1305 { 1306 MLXSW_REG_ZERO(sldr, payload); 1307 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE); 1308 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1309 } 1310 1311 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id) 1312 { 1313 MLXSW_REG_ZERO(sldr, payload); 1314 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY); 1315 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1316 } 1317 1318 /* reg_sldr_num_ports 1319 * The number of member ports of the LAG. 1320 * Reserved for Create / Destroy operations 1321 * For Add / Remove operations - indicates the number of ports in the list. 1322 * Access: RW 1323 */ 1324 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8); 1325 1326 /* reg_sldr_system_port 1327 * System port. 1328 * Access: RW 1329 */ 1330 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false); 1331 1332 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id, 1333 u8 local_port) 1334 { 1335 MLXSW_REG_ZERO(sldr, payload); 1336 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST); 1337 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1338 mlxsw_reg_sldr_num_ports_set(payload, 1); 1339 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1340 } 1341 1342 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id, 1343 u8 local_port) 1344 { 1345 MLXSW_REG_ZERO(sldr, payload); 1346 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST); 1347 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1348 mlxsw_reg_sldr_num_ports_set(payload, 1); 1349 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1350 } 1351 1352 /* SLCR - Switch LAG Configuration 2 Register 1353 * ------------------------------------------- 1354 * The Switch LAG Configuration register is used for configuring the 1355 * LAG properties of the switch. 1356 */ 1357 #define MLXSW_REG_SLCR_ID 0x2015 1358 #define MLXSW_REG_SLCR_LEN 0x10 1359 1360 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN); 1361 1362 enum mlxsw_reg_slcr_pp { 1363 /* Global Configuration (for all ports) */ 1364 MLXSW_REG_SLCR_PP_GLOBAL, 1365 /* Per port configuration, based on local_port field */ 1366 MLXSW_REG_SLCR_PP_PER_PORT, 1367 }; 1368 1369 /* reg_slcr_pp 1370 * Per Port Configuration 1371 * Note: Reading at Global mode results in reading port 1 configuration. 1372 * Access: Index 1373 */ 1374 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1); 1375 1376 /* reg_slcr_local_port 1377 * Local port number 1378 * Supported from CPU port 1379 * Not supported from router port 1380 * Reserved when pp = Global Configuration 1381 * Access: Index 1382 */ 1383 MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8); 1384 1385 enum mlxsw_reg_slcr_type { 1386 MLXSW_REG_SLCR_TYPE_CRC, /* default */ 1387 MLXSW_REG_SLCR_TYPE_XOR, 1388 MLXSW_REG_SLCR_TYPE_RANDOM, 1389 }; 1390 1391 /* reg_slcr_type 1392 * Hash type 1393 * Access: RW 1394 */ 1395 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4); 1396 1397 /* Ingress port */ 1398 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0) 1399 /* SMAC - for IPv4 and IPv6 packets */ 1400 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1) 1401 /* SMAC - for non-IP packets */ 1402 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2) 1403 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \ 1404 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \ 1405 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP) 1406 /* DMAC - for IPv4 and IPv6 packets */ 1407 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3) 1408 /* DMAC - for non-IP packets */ 1409 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4) 1410 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \ 1411 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \ 1412 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP) 1413 /* Ethertype - for IPv4 and IPv6 packets */ 1414 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5) 1415 /* Ethertype - for non-IP packets */ 1416 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6) 1417 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \ 1418 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \ 1419 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP) 1420 /* VLAN ID - for IPv4 and IPv6 packets */ 1421 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7) 1422 /* VLAN ID - for non-IP packets */ 1423 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8) 1424 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \ 1425 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \ 1426 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP) 1427 /* Source IP address (can be IPv4 or IPv6) */ 1428 #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9) 1429 /* Destination IP address (can be IPv4 or IPv6) */ 1430 #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10) 1431 /* TCP/UDP source port */ 1432 #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11) 1433 /* TCP/UDP destination port*/ 1434 #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12) 1435 /* IPv4 Protocol/IPv6 Next Header */ 1436 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13) 1437 /* IPv6 Flow label */ 1438 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14) 1439 /* SID - FCoE source ID */ 1440 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15) 1441 /* DID - FCoE destination ID */ 1442 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16) 1443 /* OXID - FCoE originator exchange ID */ 1444 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17) 1445 /* Destination QP number - for RoCE packets */ 1446 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19) 1447 1448 /* reg_slcr_lag_hash 1449 * LAG hashing configuration. This is a bitmask, in which each set 1450 * bit includes the corresponding item in the LAG hash calculation. 1451 * The default lag_hash contains SMAC, DMAC, VLANID and 1452 * Ethertype (for all packet types). 1453 * Access: RW 1454 */ 1455 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20); 1456 1457 /* reg_slcr_seed 1458 * LAG seed value. The seed is the same for all ports. 1459 * Access: RW 1460 */ 1461 MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32); 1462 1463 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed) 1464 { 1465 MLXSW_REG_ZERO(slcr, payload); 1466 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL); 1467 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC); 1468 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash); 1469 mlxsw_reg_slcr_seed_set(payload, seed); 1470 } 1471 1472 /* SLCOR - Switch LAG Collector Register 1473 * ------------------------------------- 1474 * The Switch LAG Collector register controls the Local Port membership 1475 * in a LAG and enablement of the collector. 1476 */ 1477 #define MLXSW_REG_SLCOR_ID 0x2016 1478 #define MLXSW_REG_SLCOR_LEN 0x10 1479 1480 MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN); 1481 1482 enum mlxsw_reg_slcor_col { 1483 /* Port is added with collector disabled */ 1484 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT, 1485 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED, 1486 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED, 1487 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT, 1488 }; 1489 1490 /* reg_slcor_col 1491 * Collector configuration 1492 * Access: RW 1493 */ 1494 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2); 1495 1496 /* reg_slcor_local_port 1497 * Local port number 1498 * Not supported for CPU port 1499 * Access: Index 1500 */ 1501 MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8); 1502 1503 /* reg_slcor_lag_id 1504 * LAG Identifier. Index into the LAG descriptor table. 1505 * Access: Index 1506 */ 1507 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10); 1508 1509 /* reg_slcor_port_index 1510 * Port index in the LAG list. Only valid on Add Port to LAG col. 1511 * Valid range is from 0 to cap_max_lag_members-1 1512 * Access: RW 1513 */ 1514 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10); 1515 1516 static inline void mlxsw_reg_slcor_pack(char *payload, 1517 u8 local_port, u16 lag_id, 1518 enum mlxsw_reg_slcor_col col) 1519 { 1520 MLXSW_REG_ZERO(slcor, payload); 1521 mlxsw_reg_slcor_col_set(payload, col); 1522 mlxsw_reg_slcor_local_port_set(payload, local_port); 1523 mlxsw_reg_slcor_lag_id_set(payload, lag_id); 1524 } 1525 1526 static inline void mlxsw_reg_slcor_port_add_pack(char *payload, 1527 u8 local_port, u16 lag_id, 1528 u8 port_index) 1529 { 1530 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1531 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT); 1532 mlxsw_reg_slcor_port_index_set(payload, port_index); 1533 } 1534 1535 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload, 1536 u8 local_port, u16 lag_id) 1537 { 1538 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1539 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT); 1540 } 1541 1542 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload, 1543 u8 local_port, u16 lag_id) 1544 { 1545 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1546 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1547 } 1548 1549 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload, 1550 u8 local_port, u16 lag_id) 1551 { 1552 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1553 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1554 } 1555 1556 /* SPMLR - Switch Port MAC Learning Register 1557 * ----------------------------------------- 1558 * Controls the Switch MAC learning policy per port. 1559 */ 1560 #define MLXSW_REG_SPMLR_ID 0x2018 1561 #define MLXSW_REG_SPMLR_LEN 0x8 1562 1563 MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN); 1564 1565 /* reg_spmlr_local_port 1566 * Local port number. 1567 * Access: Index 1568 */ 1569 MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8); 1570 1571 /* reg_spmlr_sub_port 1572 * Virtual port within the physical port. 1573 * Should be set to 0 when virtual ports are not enabled on the port. 1574 * Access: Index 1575 */ 1576 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8); 1577 1578 enum mlxsw_reg_spmlr_learn_mode { 1579 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0, 1580 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2, 1581 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3, 1582 }; 1583 1584 /* reg_spmlr_learn_mode 1585 * Learning mode on the port. 1586 * 0 - Learning disabled. 1587 * 2 - Learning enabled. 1588 * 3 - Security mode. 1589 * 1590 * In security mode the switch does not learn MACs on the port, but uses the 1591 * SMAC to see if it exists on another ingress port. If so, the packet is 1592 * classified as a bad packet and is discarded unless the software registers 1593 * to receive port security error packets usign HPKT. 1594 */ 1595 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2); 1596 1597 static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port, 1598 enum mlxsw_reg_spmlr_learn_mode mode) 1599 { 1600 MLXSW_REG_ZERO(spmlr, payload); 1601 mlxsw_reg_spmlr_local_port_set(payload, local_port); 1602 mlxsw_reg_spmlr_sub_port_set(payload, 0); 1603 mlxsw_reg_spmlr_learn_mode_set(payload, mode); 1604 } 1605 1606 /* SVFA - Switch VID to FID Allocation Register 1607 * -------------------------------------------- 1608 * Controls the VID to FID mapping and {Port, VID} to FID mapping for 1609 * virtualized ports. 1610 */ 1611 #define MLXSW_REG_SVFA_ID 0x201C 1612 #define MLXSW_REG_SVFA_LEN 0x10 1613 1614 MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN); 1615 1616 /* reg_svfa_swid 1617 * Switch partition ID. 1618 * Access: Index 1619 */ 1620 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8); 1621 1622 /* reg_svfa_local_port 1623 * Local port number. 1624 * Access: Index 1625 * 1626 * Note: Reserved for 802.1Q FIDs. 1627 */ 1628 MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8); 1629 1630 enum mlxsw_reg_svfa_mt { 1631 MLXSW_REG_SVFA_MT_VID_TO_FID, 1632 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, 1633 }; 1634 1635 /* reg_svfa_mapping_table 1636 * Mapping table: 1637 * 0 - VID to FID 1638 * 1 - {Port, VID} to FID 1639 * Access: Index 1640 * 1641 * Note: Reserved for SwitchX-2. 1642 */ 1643 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3); 1644 1645 /* reg_svfa_v 1646 * Valid. 1647 * Valid if set. 1648 * Access: RW 1649 * 1650 * Note: Reserved for SwitchX-2. 1651 */ 1652 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1); 1653 1654 /* reg_svfa_fid 1655 * Filtering ID. 1656 * Access: RW 1657 */ 1658 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16); 1659 1660 /* reg_svfa_vid 1661 * VLAN ID. 1662 * Access: Index 1663 */ 1664 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12); 1665 1666 /* reg_svfa_counter_set_type 1667 * Counter set type for flow counters. 1668 * Access: RW 1669 * 1670 * Note: Reserved for SwitchX-2. 1671 */ 1672 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8); 1673 1674 /* reg_svfa_counter_index 1675 * Counter index for flow counters. 1676 * Access: RW 1677 * 1678 * Note: Reserved for SwitchX-2. 1679 */ 1680 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24); 1681 1682 static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port, 1683 enum mlxsw_reg_svfa_mt mt, bool valid, 1684 u16 fid, u16 vid) 1685 { 1686 MLXSW_REG_ZERO(svfa, payload); 1687 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port; 1688 mlxsw_reg_svfa_swid_set(payload, 0); 1689 mlxsw_reg_svfa_local_port_set(payload, local_port); 1690 mlxsw_reg_svfa_mapping_table_set(payload, mt); 1691 mlxsw_reg_svfa_v_set(payload, valid); 1692 mlxsw_reg_svfa_fid_set(payload, fid); 1693 mlxsw_reg_svfa_vid_set(payload, vid); 1694 } 1695 1696 /* SVPE - Switch Virtual-Port Enabling Register 1697 * -------------------------------------------- 1698 * Enables port virtualization. 1699 */ 1700 #define MLXSW_REG_SVPE_ID 0x201E 1701 #define MLXSW_REG_SVPE_LEN 0x4 1702 1703 MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN); 1704 1705 /* reg_svpe_local_port 1706 * Local port number 1707 * Access: Index 1708 * 1709 * Note: CPU port is not supported (uses VLAN mode only). 1710 */ 1711 MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8); 1712 1713 /* reg_svpe_vp_en 1714 * Virtual port enable. 1715 * 0 - Disable, VLAN mode (VID to FID). 1716 * 1 - Enable, Virtual port mode ({Port, VID} to FID). 1717 * Access: RW 1718 */ 1719 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1); 1720 1721 static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port, 1722 bool enable) 1723 { 1724 MLXSW_REG_ZERO(svpe, payload); 1725 mlxsw_reg_svpe_local_port_set(payload, local_port); 1726 mlxsw_reg_svpe_vp_en_set(payload, enable); 1727 } 1728 1729 /* SFMR - Switch FID Management Register 1730 * ------------------------------------- 1731 * Creates and configures FIDs. 1732 */ 1733 #define MLXSW_REG_SFMR_ID 0x201F 1734 #define MLXSW_REG_SFMR_LEN 0x18 1735 1736 MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN); 1737 1738 enum mlxsw_reg_sfmr_op { 1739 MLXSW_REG_SFMR_OP_CREATE_FID, 1740 MLXSW_REG_SFMR_OP_DESTROY_FID, 1741 }; 1742 1743 /* reg_sfmr_op 1744 * Operation. 1745 * 0 - Create or edit FID. 1746 * 1 - Destroy FID. 1747 * Access: WO 1748 */ 1749 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4); 1750 1751 /* reg_sfmr_fid 1752 * Filtering ID. 1753 * Access: Index 1754 */ 1755 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16); 1756 1757 /* reg_sfmr_fid_offset 1758 * FID offset. 1759 * Used to point into the flooding table selected by SFGC register if 1760 * the table is of type FID-Offset. Otherwise, this field is reserved. 1761 * Access: RW 1762 */ 1763 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16); 1764 1765 /* reg_sfmr_vtfp 1766 * Valid Tunnel Flood Pointer. 1767 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL. 1768 * Access: RW 1769 * 1770 * Note: Reserved for 802.1Q FIDs. 1771 */ 1772 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1); 1773 1774 /* reg_sfmr_nve_tunnel_flood_ptr 1775 * Underlay Flooding and BC Pointer. 1776 * Used as a pointer to the first entry of the group based link lists of 1777 * flooding or BC entries (for NVE tunnels). 1778 * Access: RW 1779 */ 1780 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24); 1781 1782 /* reg_sfmr_vv 1783 * VNI Valid. 1784 * If not set, then vni is reserved. 1785 * Access: RW 1786 * 1787 * Note: Reserved for 802.1Q FIDs. 1788 */ 1789 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1); 1790 1791 /* reg_sfmr_vni 1792 * Virtual Network Identifier. 1793 * Access: RW 1794 * 1795 * Note: A given VNI can only be assigned to one FID. 1796 */ 1797 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24); 1798 1799 static inline void mlxsw_reg_sfmr_pack(char *payload, 1800 enum mlxsw_reg_sfmr_op op, u16 fid, 1801 u16 fid_offset) 1802 { 1803 MLXSW_REG_ZERO(sfmr, payload); 1804 mlxsw_reg_sfmr_op_set(payload, op); 1805 mlxsw_reg_sfmr_fid_set(payload, fid); 1806 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset); 1807 mlxsw_reg_sfmr_vtfp_set(payload, false); 1808 mlxsw_reg_sfmr_vv_set(payload, false); 1809 } 1810 1811 /* SPVMLR - Switch Port VLAN MAC Learning Register 1812 * ----------------------------------------------- 1813 * Controls the switch MAC learning policy per {Port, VID}. 1814 */ 1815 #define MLXSW_REG_SPVMLR_ID 0x2020 1816 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */ 1817 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */ 1818 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255 1819 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \ 1820 MLXSW_REG_SPVMLR_REC_LEN * \ 1821 MLXSW_REG_SPVMLR_REC_MAX_COUNT) 1822 1823 MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN); 1824 1825 /* reg_spvmlr_local_port 1826 * Local ingress port. 1827 * Access: Index 1828 * 1829 * Note: CPU port is not supported. 1830 */ 1831 MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8); 1832 1833 /* reg_spvmlr_num_rec 1834 * Number of records to update. 1835 * Access: OP 1836 */ 1837 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8); 1838 1839 /* reg_spvmlr_rec_learn_enable 1840 * 0 - Disable learning for {Port, VID}. 1841 * 1 - Enable learning for {Port, VID}. 1842 * Access: RW 1843 */ 1844 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN, 1845 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1846 1847 /* reg_spvmlr_rec_vid 1848 * VLAN ID to be added/removed from port or for querying. 1849 * Access: Index 1850 */ 1851 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12, 1852 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1853 1854 static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port, 1855 u16 vid_begin, u16 vid_end, 1856 bool learn_enable) 1857 { 1858 int num_rec = vid_end - vid_begin + 1; 1859 int i; 1860 1861 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT); 1862 1863 MLXSW_REG_ZERO(spvmlr, payload); 1864 mlxsw_reg_spvmlr_local_port_set(payload, local_port); 1865 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec); 1866 1867 for (i = 0; i < num_rec; i++) { 1868 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable); 1869 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i); 1870 } 1871 } 1872 1873 /* SPVC - Switch Port VLAN Classification Register 1874 * ----------------------------------------------- 1875 * Configures the port to identify packets as untagged / single tagged / 1876 * double packets based on the packet EtherTypes. 1877 * Ethertype IDs are configured by SVER. 1878 */ 1879 #define MLXSW_REG_SPVC_ID 0x2026 1880 #define MLXSW_REG_SPVC_LEN 0x0C 1881 1882 MLXSW_REG_DEFINE(spvc, MLXSW_REG_SPVC_ID, MLXSW_REG_SPVC_LEN); 1883 1884 /* reg_spvc_local_port 1885 * Local port. 1886 * Access: Index 1887 * 1888 * Note: applies both to Rx port and Tx port, so if a packet traverses 1889 * through Rx port i and a Tx port j then port i and port j must have the 1890 * same configuration. 1891 */ 1892 MLXSW_ITEM32(reg, spvc, local_port, 0x00, 16, 8); 1893 1894 /* reg_spvc_inner_et2 1895 * Vlan Tag1 EtherType2 enable. 1896 * Packet is initially classified as double VLAN Tag if in addition to 1897 * being classified with a tag0 VLAN Tag its tag1 EtherType value is 1898 * equal to ether_type2. 1899 * 0: disable (default) 1900 * 1: enable 1901 * Access: RW 1902 */ 1903 MLXSW_ITEM32(reg, spvc, inner_et2, 0x08, 17, 1); 1904 1905 /* reg_spvc_et2 1906 * Vlan Tag0 EtherType2 enable. 1907 * Packet is initially classified as VLAN Tag if its tag0 EtherType is 1908 * equal to ether_type2. 1909 * 0: disable (default) 1910 * 1: enable 1911 * Access: RW 1912 */ 1913 MLXSW_ITEM32(reg, spvc, et2, 0x08, 16, 1); 1914 1915 /* reg_spvc_inner_et1 1916 * Vlan Tag1 EtherType1 enable. 1917 * Packet is initially classified as double VLAN Tag if in addition to 1918 * being classified with a tag0 VLAN Tag its tag1 EtherType value is 1919 * equal to ether_type1. 1920 * 0: disable 1921 * 1: enable (default) 1922 * Access: RW 1923 */ 1924 MLXSW_ITEM32(reg, spvc, inner_et1, 0x08, 9, 1); 1925 1926 /* reg_spvc_et1 1927 * Vlan Tag0 EtherType1 enable. 1928 * Packet is initially classified as VLAN Tag if its tag0 EtherType is 1929 * equal to ether_type1. 1930 * 0: disable 1931 * 1: enable (default) 1932 * Access: RW 1933 */ 1934 MLXSW_ITEM32(reg, spvc, et1, 0x08, 8, 1); 1935 1936 /* reg_inner_et0 1937 * Vlan Tag1 EtherType0 enable. 1938 * Packet is initially classified as double VLAN Tag if in addition to 1939 * being classified with a tag0 VLAN Tag its tag1 EtherType value is 1940 * equal to ether_type0. 1941 * 0: disable 1942 * 1: enable (default) 1943 * Access: RW 1944 */ 1945 MLXSW_ITEM32(reg, spvc, inner_et0, 0x08, 1, 1); 1946 1947 /* reg_et0 1948 * Vlan Tag0 EtherType0 enable. 1949 * Packet is initially classified as VLAN Tag if its tag0 EtherType is 1950 * equal to ether_type0. 1951 * 0: disable 1952 * 1: enable (default) 1953 * Access: RW 1954 */ 1955 MLXSW_ITEM32(reg, spvc, et0, 0x08, 0, 1); 1956 1957 static inline void mlxsw_reg_spvc_pack(char *payload, u8 local_port, bool et1, 1958 bool et0) 1959 { 1960 MLXSW_REG_ZERO(spvc, payload); 1961 mlxsw_reg_spvc_local_port_set(payload, local_port); 1962 /* Enable inner_et1 and inner_et0 to enable identification of double 1963 * tagged packets. 1964 */ 1965 mlxsw_reg_spvc_inner_et1_set(payload, 1); 1966 mlxsw_reg_spvc_inner_et0_set(payload, 1); 1967 mlxsw_reg_spvc_et1_set(payload, et1); 1968 mlxsw_reg_spvc_et0_set(payload, et0); 1969 } 1970 1971 /* CWTP - Congetion WRED ECN TClass Profile 1972 * ---------------------------------------- 1973 * Configures the profiles for queues of egress port and traffic class 1974 */ 1975 #define MLXSW_REG_CWTP_ID 0x2802 1976 #define MLXSW_REG_CWTP_BASE_LEN 0x28 1977 #define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08 1978 #define MLXSW_REG_CWTP_LEN 0x40 1979 1980 MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN); 1981 1982 /* reg_cwtp_local_port 1983 * Local port number 1984 * Not supported for CPU port 1985 * Access: Index 1986 */ 1987 MLXSW_ITEM32(reg, cwtp, local_port, 0, 16, 8); 1988 1989 /* reg_cwtp_traffic_class 1990 * Traffic Class to configure 1991 * Access: Index 1992 */ 1993 MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8); 1994 1995 /* reg_cwtp_profile_min 1996 * Minimum Average Queue Size of the profile in cells. 1997 * Access: RW 1998 */ 1999 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN, 2000 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false); 2001 2002 /* reg_cwtp_profile_percent 2003 * Percentage of WRED and ECN marking for maximum Average Queue size 2004 * Range is 0 to 100, units of integer percentage 2005 * Access: RW 2006 */ 2007 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN, 2008 24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 2009 2010 /* reg_cwtp_profile_max 2011 * Maximum Average Queue size of the profile in cells 2012 * Access: RW 2013 */ 2014 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN, 2015 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 2016 2017 #define MLXSW_REG_CWTP_MIN_VALUE 64 2018 #define MLXSW_REG_CWTP_MAX_PROFILE 2 2019 #define MLXSW_REG_CWTP_DEFAULT_PROFILE 1 2020 2021 static inline void mlxsw_reg_cwtp_pack(char *payload, u8 local_port, 2022 u8 traffic_class) 2023 { 2024 int i; 2025 2026 MLXSW_REG_ZERO(cwtp, payload); 2027 mlxsw_reg_cwtp_local_port_set(payload, local_port); 2028 mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class); 2029 2030 for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) { 2031 mlxsw_reg_cwtp_profile_min_set(payload, i, 2032 MLXSW_REG_CWTP_MIN_VALUE); 2033 mlxsw_reg_cwtp_profile_max_set(payload, i, 2034 MLXSW_REG_CWTP_MIN_VALUE); 2035 } 2036 } 2037 2038 #define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1) 2039 2040 static inline void 2041 mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max, 2042 u32 probability) 2043 { 2044 u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile); 2045 2046 mlxsw_reg_cwtp_profile_min_set(payload, index, min); 2047 mlxsw_reg_cwtp_profile_max_set(payload, index, max); 2048 mlxsw_reg_cwtp_profile_percent_set(payload, index, probability); 2049 } 2050 2051 /* CWTPM - Congestion WRED ECN TClass and Pool Mapping 2052 * --------------------------------------------------- 2053 * The CWTPM register maps each egress port and traffic class to profile num. 2054 */ 2055 #define MLXSW_REG_CWTPM_ID 0x2803 2056 #define MLXSW_REG_CWTPM_LEN 0x44 2057 2058 MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN); 2059 2060 /* reg_cwtpm_local_port 2061 * Local port number 2062 * Not supported for CPU port 2063 * Access: Index 2064 */ 2065 MLXSW_ITEM32(reg, cwtpm, local_port, 0, 16, 8); 2066 2067 /* reg_cwtpm_traffic_class 2068 * Traffic Class to configure 2069 * Access: Index 2070 */ 2071 MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8); 2072 2073 /* reg_cwtpm_ew 2074 * Control enablement of WRED for traffic class: 2075 * 0 - Disable 2076 * 1 - Enable 2077 * Access: RW 2078 */ 2079 MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1); 2080 2081 /* reg_cwtpm_ee 2082 * Control enablement of ECN for traffic class: 2083 * 0 - Disable 2084 * 1 - Enable 2085 * Access: RW 2086 */ 2087 MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1); 2088 2089 /* reg_cwtpm_tcp_g 2090 * TCP Green Profile. 2091 * Index of the profile within {port, traffic class} to use. 2092 * 0 for disabling both WRED and ECN for this type of traffic. 2093 * Access: RW 2094 */ 2095 MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2); 2096 2097 /* reg_cwtpm_tcp_y 2098 * TCP Yellow Profile. 2099 * Index of the profile within {port, traffic class} to use. 2100 * 0 for disabling both WRED and ECN for this type of traffic. 2101 * Access: RW 2102 */ 2103 MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2); 2104 2105 /* reg_cwtpm_tcp_r 2106 * TCP Red Profile. 2107 * Index of the profile within {port, traffic class} to use. 2108 * 0 for disabling both WRED and ECN for this type of traffic. 2109 * Access: RW 2110 */ 2111 MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2); 2112 2113 /* reg_cwtpm_ntcp_g 2114 * Non-TCP Green Profile. 2115 * Index of the profile within {port, traffic class} to use. 2116 * 0 for disabling both WRED and ECN for this type of traffic. 2117 * Access: RW 2118 */ 2119 MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2); 2120 2121 /* reg_cwtpm_ntcp_y 2122 * Non-TCP Yellow Profile. 2123 * Index of the profile within {port, traffic class} to use. 2124 * 0 for disabling both WRED and ECN for this type of traffic. 2125 * Access: RW 2126 */ 2127 MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2); 2128 2129 /* reg_cwtpm_ntcp_r 2130 * Non-TCP Red Profile. 2131 * Index of the profile within {port, traffic class} to use. 2132 * 0 for disabling both WRED and ECN for this type of traffic. 2133 * Access: RW 2134 */ 2135 MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2); 2136 2137 #define MLXSW_REG_CWTPM_RESET_PROFILE 0 2138 2139 static inline void mlxsw_reg_cwtpm_pack(char *payload, u8 local_port, 2140 u8 traffic_class, u8 profile, 2141 bool wred, bool ecn) 2142 { 2143 MLXSW_REG_ZERO(cwtpm, payload); 2144 mlxsw_reg_cwtpm_local_port_set(payload, local_port); 2145 mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class); 2146 mlxsw_reg_cwtpm_ew_set(payload, wred); 2147 mlxsw_reg_cwtpm_ee_set(payload, ecn); 2148 mlxsw_reg_cwtpm_tcp_g_set(payload, profile); 2149 mlxsw_reg_cwtpm_tcp_y_set(payload, profile); 2150 mlxsw_reg_cwtpm_tcp_r_set(payload, profile); 2151 mlxsw_reg_cwtpm_ntcp_g_set(payload, profile); 2152 mlxsw_reg_cwtpm_ntcp_y_set(payload, profile); 2153 mlxsw_reg_cwtpm_ntcp_r_set(payload, profile); 2154 } 2155 2156 /* PGCR - Policy-Engine General Configuration Register 2157 * --------------------------------------------------- 2158 * This register configures general Policy-Engine settings. 2159 */ 2160 #define MLXSW_REG_PGCR_ID 0x3001 2161 #define MLXSW_REG_PGCR_LEN 0x20 2162 2163 MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN); 2164 2165 /* reg_pgcr_default_action_pointer_base 2166 * Default action pointer base. Each region has a default action pointer 2167 * which is equal to default_action_pointer_base + region_id. 2168 * Access: RW 2169 */ 2170 MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24); 2171 2172 static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base) 2173 { 2174 MLXSW_REG_ZERO(pgcr, payload); 2175 mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base); 2176 } 2177 2178 /* PPBT - Policy-Engine Port Binding Table 2179 * --------------------------------------- 2180 * This register is used for configuration of the Port Binding Table. 2181 */ 2182 #define MLXSW_REG_PPBT_ID 0x3002 2183 #define MLXSW_REG_PPBT_LEN 0x14 2184 2185 MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN); 2186 2187 enum mlxsw_reg_pxbt_e { 2188 MLXSW_REG_PXBT_E_IACL, 2189 MLXSW_REG_PXBT_E_EACL, 2190 }; 2191 2192 /* reg_ppbt_e 2193 * Access: Index 2194 */ 2195 MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1); 2196 2197 enum mlxsw_reg_pxbt_op { 2198 MLXSW_REG_PXBT_OP_BIND, 2199 MLXSW_REG_PXBT_OP_UNBIND, 2200 }; 2201 2202 /* reg_ppbt_op 2203 * Access: RW 2204 */ 2205 MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3); 2206 2207 /* reg_ppbt_local_port 2208 * Local port. Not including CPU port. 2209 * Access: Index 2210 */ 2211 MLXSW_ITEM32(reg, ppbt, local_port, 0x00, 16, 8); 2212 2213 /* reg_ppbt_g 2214 * group - When set, the binding is of an ACL group. When cleared, 2215 * the binding is of an ACL. 2216 * Must be set to 1 for Spectrum. 2217 * Access: RW 2218 */ 2219 MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1); 2220 2221 /* reg_ppbt_acl_info 2222 * ACL/ACL group identifier. If the g bit is set, this field should hold 2223 * the acl_group_id, else it should hold the acl_id. 2224 * Access: RW 2225 */ 2226 MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16); 2227 2228 static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e, 2229 enum mlxsw_reg_pxbt_op op, 2230 u8 local_port, u16 acl_info) 2231 { 2232 MLXSW_REG_ZERO(ppbt, payload); 2233 mlxsw_reg_ppbt_e_set(payload, e); 2234 mlxsw_reg_ppbt_op_set(payload, op); 2235 mlxsw_reg_ppbt_local_port_set(payload, local_port); 2236 mlxsw_reg_ppbt_g_set(payload, true); 2237 mlxsw_reg_ppbt_acl_info_set(payload, acl_info); 2238 } 2239 2240 /* PACL - Policy-Engine ACL Register 2241 * --------------------------------- 2242 * This register is used for configuration of the ACL. 2243 */ 2244 #define MLXSW_REG_PACL_ID 0x3004 2245 #define MLXSW_REG_PACL_LEN 0x70 2246 2247 MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN); 2248 2249 /* reg_pacl_v 2250 * Valid. Setting the v bit makes the ACL valid. It should not be cleared 2251 * while the ACL is bounded to either a port, VLAN or ACL rule. 2252 * Access: RW 2253 */ 2254 MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1); 2255 2256 /* reg_pacl_acl_id 2257 * An identifier representing the ACL (managed by software) 2258 * Range 0 .. cap_max_acl_regions - 1 2259 * Access: Index 2260 */ 2261 MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16); 2262 2263 #define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16 2264 2265 /* reg_pacl_tcam_region_info 2266 * Opaque object that represents a TCAM region. 2267 * Obtained through PTAR register. 2268 * Access: RW 2269 */ 2270 MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30, 2271 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2272 2273 static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id, 2274 bool valid, const char *tcam_region_info) 2275 { 2276 MLXSW_REG_ZERO(pacl, payload); 2277 mlxsw_reg_pacl_acl_id_set(payload, acl_id); 2278 mlxsw_reg_pacl_v_set(payload, valid); 2279 mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info); 2280 } 2281 2282 /* PAGT - Policy-Engine ACL Group Table 2283 * ------------------------------------ 2284 * This register is used for configuration of the ACL Group Table. 2285 */ 2286 #define MLXSW_REG_PAGT_ID 0x3005 2287 #define MLXSW_REG_PAGT_BASE_LEN 0x30 2288 #define MLXSW_REG_PAGT_ACL_LEN 4 2289 #define MLXSW_REG_PAGT_ACL_MAX_NUM 16 2290 #define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \ 2291 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN) 2292 2293 MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN); 2294 2295 /* reg_pagt_size 2296 * Number of ACLs in the group. 2297 * Size 0 invalidates a group. 2298 * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now) 2299 * Total number of ACLs in all groups must be lower or equal 2300 * to cap_max_acl_tot_groups 2301 * Note: a group which is binded must not be invalidated 2302 * Access: Index 2303 */ 2304 MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8); 2305 2306 /* reg_pagt_acl_group_id 2307 * An identifier (numbered from 0..cap_max_acl_groups-1) representing 2308 * the ACL Group identifier (managed by software). 2309 * Access: Index 2310 */ 2311 MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16); 2312 2313 /* reg_pagt_multi 2314 * Multi-ACL 2315 * 0 - This ACL is the last ACL in the multi-ACL 2316 * 1 - This ACL is part of a multi-ACL 2317 * Access: RW 2318 */ 2319 MLXSW_ITEM32_INDEXED(reg, pagt, multi, 0x30, 31, 1, 0x04, 0x00, false); 2320 2321 /* reg_pagt_acl_id 2322 * ACL identifier 2323 * Access: RW 2324 */ 2325 MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false); 2326 2327 static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id) 2328 { 2329 MLXSW_REG_ZERO(pagt, payload); 2330 mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id); 2331 } 2332 2333 static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index, 2334 u16 acl_id, bool multi) 2335 { 2336 u8 size = mlxsw_reg_pagt_size_get(payload); 2337 2338 if (index >= size) 2339 mlxsw_reg_pagt_size_set(payload, index + 1); 2340 mlxsw_reg_pagt_multi_set(payload, index, multi); 2341 mlxsw_reg_pagt_acl_id_set(payload, index, acl_id); 2342 } 2343 2344 /* PTAR - Policy-Engine TCAM Allocation Register 2345 * --------------------------------------------- 2346 * This register is used for allocation of regions in the TCAM. 2347 * Note: Query method is not supported on this register. 2348 */ 2349 #define MLXSW_REG_PTAR_ID 0x3006 2350 #define MLXSW_REG_PTAR_BASE_LEN 0x20 2351 #define MLXSW_REG_PTAR_KEY_ID_LEN 1 2352 #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16 2353 #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \ 2354 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN) 2355 2356 MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN); 2357 2358 enum mlxsw_reg_ptar_op { 2359 /* allocate a TCAM region */ 2360 MLXSW_REG_PTAR_OP_ALLOC, 2361 /* resize a TCAM region */ 2362 MLXSW_REG_PTAR_OP_RESIZE, 2363 /* deallocate TCAM region */ 2364 MLXSW_REG_PTAR_OP_FREE, 2365 /* test allocation */ 2366 MLXSW_REG_PTAR_OP_TEST, 2367 }; 2368 2369 /* reg_ptar_op 2370 * Access: OP 2371 */ 2372 MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4); 2373 2374 /* reg_ptar_action_set_type 2375 * Type of action set to be used on this region. 2376 * For Spectrum and Spectrum-2, this is always type 2 - "flexible" 2377 * Access: WO 2378 */ 2379 MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8); 2380 2381 enum mlxsw_reg_ptar_key_type { 2382 MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50, /* Spetrum */ 2383 MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51, /* Spectrum-2 */ 2384 }; 2385 2386 /* reg_ptar_key_type 2387 * TCAM key type for the region. 2388 * Access: WO 2389 */ 2390 MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8); 2391 2392 /* reg_ptar_region_size 2393 * TCAM region size. When allocating/resizing this is the requested size, 2394 * the response is the actual size. Note that actual size may be 2395 * larger than requested. 2396 * Allowed range 1 .. cap_max_rules-1 2397 * Reserved during op deallocate. 2398 * Access: WO 2399 */ 2400 MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16); 2401 2402 /* reg_ptar_region_id 2403 * Region identifier 2404 * Range 0 .. cap_max_regions-1 2405 * Access: Index 2406 */ 2407 MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16); 2408 2409 /* reg_ptar_tcam_region_info 2410 * Opaque object that represents the TCAM region. 2411 * Returned when allocating a region. 2412 * Provided by software for ACL generation and region deallocation and resize. 2413 * Access: RW 2414 */ 2415 MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10, 2416 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2417 2418 /* reg_ptar_flexible_key_id 2419 * Identifier of the Flexible Key. 2420 * Only valid if key_type == "FLEX_KEY" 2421 * The key size will be rounded up to one of the following values: 2422 * 9B, 18B, 36B, 54B. 2423 * This field is reserved for in resize operation. 2424 * Access: WO 2425 */ 2426 MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8, 2427 MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false); 2428 2429 static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op, 2430 enum mlxsw_reg_ptar_key_type key_type, 2431 u16 region_size, u16 region_id, 2432 const char *tcam_region_info) 2433 { 2434 MLXSW_REG_ZERO(ptar, payload); 2435 mlxsw_reg_ptar_op_set(payload, op); 2436 mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */ 2437 mlxsw_reg_ptar_key_type_set(payload, key_type); 2438 mlxsw_reg_ptar_region_size_set(payload, region_size); 2439 mlxsw_reg_ptar_region_id_set(payload, region_id); 2440 mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info); 2441 } 2442 2443 static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index, 2444 u16 key_id) 2445 { 2446 mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id); 2447 } 2448 2449 static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info) 2450 { 2451 mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info); 2452 } 2453 2454 /* PPBS - Policy-Engine Policy Based Switching Register 2455 * ---------------------------------------------------- 2456 * This register retrieves and sets Policy Based Switching Table entries. 2457 */ 2458 #define MLXSW_REG_PPBS_ID 0x300C 2459 #define MLXSW_REG_PPBS_LEN 0x14 2460 2461 MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN); 2462 2463 /* reg_ppbs_pbs_ptr 2464 * Index into the PBS table. 2465 * For Spectrum, the index points to the KVD Linear. 2466 * Access: Index 2467 */ 2468 MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24); 2469 2470 /* reg_ppbs_system_port 2471 * Unique port identifier for the final destination of the packet. 2472 * Access: RW 2473 */ 2474 MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16); 2475 2476 static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr, 2477 u16 system_port) 2478 { 2479 MLXSW_REG_ZERO(ppbs, payload); 2480 mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr); 2481 mlxsw_reg_ppbs_system_port_set(payload, system_port); 2482 } 2483 2484 /* PRCR - Policy-Engine Rules Copy Register 2485 * ---------------------------------------- 2486 * This register is used for accessing rules within a TCAM region. 2487 */ 2488 #define MLXSW_REG_PRCR_ID 0x300D 2489 #define MLXSW_REG_PRCR_LEN 0x40 2490 2491 MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN); 2492 2493 enum mlxsw_reg_prcr_op { 2494 /* Move rules. Moves the rules from "tcam_region_info" starting 2495 * at offset "offset" to "dest_tcam_region_info" 2496 * at offset "dest_offset." 2497 */ 2498 MLXSW_REG_PRCR_OP_MOVE, 2499 /* Copy rules. Copies the rules from "tcam_region_info" starting 2500 * at offset "offset" to "dest_tcam_region_info" 2501 * at offset "dest_offset." 2502 */ 2503 MLXSW_REG_PRCR_OP_COPY, 2504 }; 2505 2506 /* reg_prcr_op 2507 * Access: OP 2508 */ 2509 MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4); 2510 2511 /* reg_prcr_offset 2512 * Offset within the source region to copy/move from. 2513 * Access: Index 2514 */ 2515 MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16); 2516 2517 /* reg_prcr_size 2518 * The number of rules to copy/move. 2519 * Access: WO 2520 */ 2521 MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16); 2522 2523 /* reg_prcr_tcam_region_info 2524 * Opaque object that represents the source TCAM region. 2525 * Access: Index 2526 */ 2527 MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10, 2528 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2529 2530 /* reg_prcr_dest_offset 2531 * Offset within the source region to copy/move to. 2532 * Access: Index 2533 */ 2534 MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16); 2535 2536 /* reg_prcr_dest_tcam_region_info 2537 * Opaque object that represents the destination TCAM region. 2538 * Access: Index 2539 */ 2540 MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30, 2541 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2542 2543 static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op, 2544 const char *src_tcam_region_info, 2545 u16 src_offset, 2546 const char *dest_tcam_region_info, 2547 u16 dest_offset, u16 size) 2548 { 2549 MLXSW_REG_ZERO(prcr, payload); 2550 mlxsw_reg_prcr_op_set(payload, op); 2551 mlxsw_reg_prcr_offset_set(payload, src_offset); 2552 mlxsw_reg_prcr_size_set(payload, size); 2553 mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload, 2554 src_tcam_region_info); 2555 mlxsw_reg_prcr_dest_offset_set(payload, dest_offset); 2556 mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload, 2557 dest_tcam_region_info); 2558 } 2559 2560 /* PEFA - Policy-Engine Extended Flexible Action Register 2561 * ------------------------------------------------------ 2562 * This register is used for accessing an extended flexible action entry 2563 * in the central KVD Linear Database. 2564 */ 2565 #define MLXSW_REG_PEFA_ID 0x300F 2566 #define MLXSW_REG_PEFA_LEN 0xB0 2567 2568 MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN); 2569 2570 /* reg_pefa_index 2571 * Index in the KVD Linear Centralized Database. 2572 * Access: Index 2573 */ 2574 MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24); 2575 2576 /* reg_pefa_a 2577 * Index in the KVD Linear Centralized Database. 2578 * Activity 2579 * For a new entry: set if ca=0, clear if ca=1 2580 * Set if a packet lookup has hit on the specific entry 2581 * Access: RO 2582 */ 2583 MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1); 2584 2585 /* reg_pefa_ca 2586 * Clear activity 2587 * When write: activity is according to this field 2588 * When read: after reading the activity is cleared according to ca 2589 * Access: OP 2590 */ 2591 MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1); 2592 2593 #define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8 2594 2595 /* reg_pefa_flex_action_set 2596 * Action-set to perform when rule is matched. 2597 * Must be zero padded if action set is shorter. 2598 * Access: RW 2599 */ 2600 MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN); 2601 2602 static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca, 2603 const char *flex_action_set) 2604 { 2605 MLXSW_REG_ZERO(pefa, payload); 2606 mlxsw_reg_pefa_index_set(payload, index); 2607 mlxsw_reg_pefa_ca_set(payload, ca); 2608 if (flex_action_set) 2609 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload, 2610 flex_action_set); 2611 } 2612 2613 static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a) 2614 { 2615 *p_a = mlxsw_reg_pefa_a_get(payload); 2616 } 2617 2618 /* PEMRBT - Policy-Engine Multicast Router Binding Table Register 2619 * -------------------------------------------------------------- 2620 * This register is used for binding Multicast router to an ACL group 2621 * that serves the MC router. 2622 * This register is not supported by SwitchX/-2 and Spectrum. 2623 */ 2624 #define MLXSW_REG_PEMRBT_ID 0x3014 2625 #define MLXSW_REG_PEMRBT_LEN 0x14 2626 2627 MLXSW_REG_DEFINE(pemrbt, MLXSW_REG_PEMRBT_ID, MLXSW_REG_PEMRBT_LEN); 2628 2629 enum mlxsw_reg_pemrbt_protocol { 2630 MLXSW_REG_PEMRBT_PROTO_IPV4, 2631 MLXSW_REG_PEMRBT_PROTO_IPV6, 2632 }; 2633 2634 /* reg_pemrbt_protocol 2635 * Access: Index 2636 */ 2637 MLXSW_ITEM32(reg, pemrbt, protocol, 0x00, 0, 1); 2638 2639 /* reg_pemrbt_group_id 2640 * ACL group identifier. 2641 * Range 0..cap_max_acl_groups-1 2642 * Access: RW 2643 */ 2644 MLXSW_ITEM32(reg, pemrbt, group_id, 0x10, 0, 16); 2645 2646 static inline void 2647 mlxsw_reg_pemrbt_pack(char *payload, enum mlxsw_reg_pemrbt_protocol protocol, 2648 u16 group_id) 2649 { 2650 MLXSW_REG_ZERO(pemrbt, payload); 2651 mlxsw_reg_pemrbt_protocol_set(payload, protocol); 2652 mlxsw_reg_pemrbt_group_id_set(payload, group_id); 2653 } 2654 2655 /* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2 2656 * ----------------------------------------------------- 2657 * This register is used for accessing rules within a TCAM region. 2658 * It is a new version of PTCE in order to support wider key, 2659 * mask and action within a TCAM region. This register is not supported 2660 * by SwitchX and SwitchX-2. 2661 */ 2662 #define MLXSW_REG_PTCE2_ID 0x3017 2663 #define MLXSW_REG_PTCE2_LEN 0x1D8 2664 2665 MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN); 2666 2667 /* reg_ptce2_v 2668 * Valid. 2669 * Access: RW 2670 */ 2671 MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1); 2672 2673 /* reg_ptce2_a 2674 * Activity. Set if a packet lookup has hit on the specific entry. 2675 * To clear the "a" bit, use "clear activity" op or "clear on read" op. 2676 * Access: RO 2677 */ 2678 MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1); 2679 2680 enum mlxsw_reg_ptce2_op { 2681 /* Read operation. */ 2682 MLXSW_REG_PTCE2_OP_QUERY_READ = 0, 2683 /* clear on read operation. Used to read entry 2684 * and clear Activity bit. 2685 */ 2686 MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1, 2687 /* Write operation. Used to write a new entry to the table. 2688 * All R/W fields are relevant for new entry. Activity bit is set 2689 * for new entries - Note write with v = 0 will delete the entry. 2690 */ 2691 MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0, 2692 /* Update action. Only action set will be updated. */ 2693 MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1, 2694 /* Clear activity. A bit is cleared for the entry. */ 2695 MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2, 2696 }; 2697 2698 /* reg_ptce2_op 2699 * Access: OP 2700 */ 2701 MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3); 2702 2703 /* reg_ptce2_offset 2704 * Access: Index 2705 */ 2706 MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16); 2707 2708 /* reg_ptce2_priority 2709 * Priority of the rule, higher values win. The range is 1..cap_kvd_size-1. 2710 * Note: priority does not have to be unique per rule. 2711 * Within a region, higher priority should have lower offset (no limitation 2712 * between regions in a multi-region). 2713 * Access: RW 2714 */ 2715 MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24); 2716 2717 /* reg_ptce2_tcam_region_info 2718 * Opaque object that represents the TCAM region. 2719 * Access: Index 2720 */ 2721 MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10, 2722 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2723 2724 #define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 96 2725 2726 /* reg_ptce2_flex_key_blocks 2727 * ACL Key. 2728 * Access: RW 2729 */ 2730 MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20, 2731 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2732 2733 /* reg_ptce2_mask 2734 * mask- in the same size as key. A bit that is set directs the TCAM 2735 * to compare the corresponding bit in key. A bit that is clear directs 2736 * the TCAM to ignore the corresponding bit in key. 2737 * Access: RW 2738 */ 2739 MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80, 2740 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2741 2742 /* reg_ptce2_flex_action_set 2743 * ACL action set. 2744 * Access: RW 2745 */ 2746 MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0, 2747 MLXSW_REG_FLEX_ACTION_SET_LEN); 2748 2749 static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid, 2750 enum mlxsw_reg_ptce2_op op, 2751 const char *tcam_region_info, 2752 u16 offset, u32 priority) 2753 { 2754 MLXSW_REG_ZERO(ptce2, payload); 2755 mlxsw_reg_ptce2_v_set(payload, valid); 2756 mlxsw_reg_ptce2_op_set(payload, op); 2757 mlxsw_reg_ptce2_offset_set(payload, offset); 2758 mlxsw_reg_ptce2_priority_set(payload, priority); 2759 mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info); 2760 } 2761 2762 /* PERPT - Policy-Engine ERP Table Register 2763 * ---------------------------------------- 2764 * This register adds and removes eRPs from the eRP table. 2765 */ 2766 #define MLXSW_REG_PERPT_ID 0x3021 2767 #define MLXSW_REG_PERPT_LEN 0x80 2768 2769 MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN); 2770 2771 /* reg_perpt_erpt_bank 2772 * eRP table bank. 2773 * Range 0 .. cap_max_erp_table_banks - 1 2774 * Access: Index 2775 */ 2776 MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4); 2777 2778 /* reg_perpt_erpt_index 2779 * Index to eRP table within the eRP bank. 2780 * Range is 0 .. cap_max_erp_table_bank_size - 1 2781 * Access: Index 2782 */ 2783 MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8); 2784 2785 enum mlxsw_reg_perpt_key_size { 2786 MLXSW_REG_PERPT_KEY_SIZE_2KB, 2787 MLXSW_REG_PERPT_KEY_SIZE_4KB, 2788 MLXSW_REG_PERPT_KEY_SIZE_8KB, 2789 MLXSW_REG_PERPT_KEY_SIZE_12KB, 2790 }; 2791 2792 /* reg_perpt_key_size 2793 * Access: OP 2794 */ 2795 MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4); 2796 2797 /* reg_perpt_bf_bypass 2798 * 0 - The eRP is used only if bloom filter state is set for the given 2799 * rule. 2800 * 1 - The eRP is used regardless of bloom filter state. 2801 * The bypass is an OR condition of region_id or eRP. See PERCR.bf_bypass 2802 * Access: RW 2803 */ 2804 MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1); 2805 2806 /* reg_perpt_erp_id 2807 * eRP ID for use by the rules. 2808 * Access: RW 2809 */ 2810 MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4); 2811 2812 /* reg_perpt_erpt_base_bank 2813 * Base eRP table bank, points to head of erp_vector 2814 * Range is 0 .. cap_max_erp_table_banks - 1 2815 * Access: OP 2816 */ 2817 MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4); 2818 2819 /* reg_perpt_erpt_base_index 2820 * Base index to eRP table within the eRP bank 2821 * Range is 0 .. cap_max_erp_table_bank_size - 1 2822 * Access: OP 2823 */ 2824 MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8); 2825 2826 /* reg_perpt_erp_index_in_vector 2827 * eRP index in the vector. 2828 * Access: OP 2829 */ 2830 MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4); 2831 2832 /* reg_perpt_erp_vector 2833 * eRP vector. 2834 * Access: OP 2835 */ 2836 MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1); 2837 2838 /* reg_perpt_mask 2839 * Mask 2840 * 0 - A-TCAM will ignore the bit in key 2841 * 1 - A-TCAM will compare the bit in key 2842 * Access: RW 2843 */ 2844 MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2845 2846 static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload, 2847 unsigned long *erp_vector, 2848 unsigned long size) 2849 { 2850 unsigned long bit; 2851 2852 for_each_set_bit(bit, erp_vector, size) 2853 mlxsw_reg_perpt_erp_vector_set(payload, bit, true); 2854 } 2855 2856 static inline void 2857 mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index, 2858 enum mlxsw_reg_perpt_key_size key_size, u8 erp_id, 2859 u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index, 2860 char *mask) 2861 { 2862 MLXSW_REG_ZERO(perpt, payload); 2863 mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank); 2864 mlxsw_reg_perpt_erpt_index_set(payload, erpt_index); 2865 mlxsw_reg_perpt_key_size_set(payload, key_size); 2866 mlxsw_reg_perpt_bf_bypass_set(payload, false); 2867 mlxsw_reg_perpt_erp_id_set(payload, erp_id); 2868 mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank); 2869 mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index); 2870 mlxsw_reg_perpt_erp_index_in_vector_set(payload, erp_index); 2871 mlxsw_reg_perpt_mask_memcpy_to(payload, mask); 2872 } 2873 2874 /* PERAR - Policy-Engine Region Association Register 2875 * ------------------------------------------------- 2876 * This register associates a hw region for region_id's. Changing on the fly 2877 * is supported by the device. 2878 */ 2879 #define MLXSW_REG_PERAR_ID 0x3026 2880 #define MLXSW_REG_PERAR_LEN 0x08 2881 2882 MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN); 2883 2884 /* reg_perar_region_id 2885 * Region identifier 2886 * Range 0 .. cap_max_regions-1 2887 * Access: Index 2888 */ 2889 MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16); 2890 2891 static inline unsigned int 2892 mlxsw_reg_perar_hw_regions_needed(unsigned int block_num) 2893 { 2894 return DIV_ROUND_UP(block_num, 4); 2895 } 2896 2897 /* reg_perar_hw_region 2898 * HW Region 2899 * Range 0 .. cap_max_regions-1 2900 * Default: hw_region = region_id 2901 * For a 8 key block region, 2 consecutive regions are used 2902 * For a 12 key block region, 3 consecutive regions are used 2903 * Access: RW 2904 */ 2905 MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16); 2906 2907 static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id, 2908 u16 hw_region) 2909 { 2910 MLXSW_REG_ZERO(perar, payload); 2911 mlxsw_reg_perar_region_id_set(payload, region_id); 2912 mlxsw_reg_perar_hw_region_set(payload, hw_region); 2913 } 2914 2915 /* PTCE-V3 - Policy-Engine TCAM Entry Register Version 3 2916 * ----------------------------------------------------- 2917 * This register is a new version of PTCE-V2 in order to support the 2918 * A-TCAM. This register is not supported by SwitchX/-2 and Spectrum. 2919 */ 2920 #define MLXSW_REG_PTCE3_ID 0x3027 2921 #define MLXSW_REG_PTCE3_LEN 0xF0 2922 2923 MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN); 2924 2925 /* reg_ptce3_v 2926 * Valid. 2927 * Access: RW 2928 */ 2929 MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1); 2930 2931 enum mlxsw_reg_ptce3_op { 2932 /* Write operation. Used to write a new entry to the table. 2933 * All R/W fields are relevant for new entry. Activity bit is set 2934 * for new entries. Write with v = 0 will delete the entry. Must 2935 * not be used if an entry exists. 2936 */ 2937 MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0, 2938 /* Update operation */ 2939 MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1, 2940 /* Read operation */ 2941 MLXSW_REG_PTCE3_OP_QUERY_READ = 0, 2942 }; 2943 2944 /* reg_ptce3_op 2945 * Access: OP 2946 */ 2947 MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3); 2948 2949 /* reg_ptce3_priority 2950 * Priority of the rule. Higher values win. 2951 * For Spectrum-2 range is 1..cap_kvd_size - 1 2952 * Note: Priority does not have to be unique per rule. 2953 * Access: RW 2954 */ 2955 MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24); 2956 2957 /* reg_ptce3_tcam_region_info 2958 * Opaque object that represents the TCAM region. 2959 * Access: Index 2960 */ 2961 MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10, 2962 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2963 2964 /* reg_ptce3_flex2_key_blocks 2965 * ACL key. The key must be masked according to eRP (if exists) or 2966 * according to master mask. 2967 * Access: Index 2968 */ 2969 MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20, 2970 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2971 2972 /* reg_ptce3_erp_id 2973 * eRP ID. 2974 * Access: Index 2975 */ 2976 MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4); 2977 2978 /* reg_ptce3_delta_start 2979 * Start point of delta_value and delta_mask, in bits. Must not exceed 2980 * num_key_blocks * 36 - 8. Reserved when delta_mask = 0. 2981 * Access: Index 2982 */ 2983 MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10); 2984 2985 /* reg_ptce3_delta_mask 2986 * Delta mask. 2987 * 0 - Ignore relevant bit in delta_value 2988 * 1 - Compare relevant bit in delta_value 2989 * Delta mask must not be set for reserved fields in the key blocks. 2990 * Note: No delta when no eRPs. Thus, for regions with 2991 * PERERP.erpt_pointer_valid = 0 the delta mask must be 0. 2992 * Access: Index 2993 */ 2994 MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8); 2995 2996 /* reg_ptce3_delta_value 2997 * Delta value. 2998 * Bits which are masked by delta_mask must be 0. 2999 * Access: Index 3000 */ 3001 MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8); 3002 3003 /* reg_ptce3_prune_vector 3004 * Pruning vector relative to the PERPT.erp_id. 3005 * Used for reducing lookups. 3006 * 0 - NEED: Do a lookup using the eRP. 3007 * 1 - PRUNE: Do not perform a lookup using the eRP. 3008 * Maybe be modified by PEAPBL and PEAPBM. 3009 * Note: In Spectrum-2, a region of 8 key blocks must be set to either 3010 * all 1's or all 0's. 3011 * Access: RW 3012 */ 3013 MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1); 3014 3015 /* reg_ptce3_prune_ctcam 3016 * Pruning on C-TCAM. Used for reducing lookups. 3017 * 0 - NEED: Do a lookup in the C-TCAM. 3018 * 1 - PRUNE: Do not perform a lookup in the C-TCAM. 3019 * Access: RW 3020 */ 3021 MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1); 3022 3023 /* reg_ptce3_large_exists 3024 * Large entry key ID exists. 3025 * Within the region: 3026 * 0 - SINGLE: The large_entry_key_id is not currently in use. 3027 * For rule insert: The MSB of the key (blocks 6..11) will be added. 3028 * For rule delete: The MSB of the key will be removed. 3029 * 1 - NON_SINGLE: The large_entry_key_id is currently in use. 3030 * For rule insert: The MSB of the key (blocks 6..11) will not be added. 3031 * For rule delete: The MSB of the key will not be removed. 3032 * Access: WO 3033 */ 3034 MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1); 3035 3036 /* reg_ptce3_large_entry_key_id 3037 * Large entry key ID. 3038 * A key for 12 key blocks rules. Reserved when region has less than 12 key 3039 * blocks. Must be different for different keys which have the same common 3040 * 6 key blocks (MSB, blocks 6..11) key within a region. 3041 * Range is 0..cap_max_pe_large_key_id - 1 3042 * Access: RW 3043 */ 3044 MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24); 3045 3046 /* reg_ptce3_action_pointer 3047 * Pointer to action. 3048 * Range is 0..cap_max_kvd_action_sets - 1 3049 * Access: RW 3050 */ 3051 MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24); 3052 3053 static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid, 3054 enum mlxsw_reg_ptce3_op op, 3055 u32 priority, 3056 const char *tcam_region_info, 3057 const char *key, u8 erp_id, 3058 u16 delta_start, u8 delta_mask, 3059 u8 delta_value, bool large_exists, 3060 u32 lkey_id, u32 action_pointer) 3061 { 3062 MLXSW_REG_ZERO(ptce3, payload); 3063 mlxsw_reg_ptce3_v_set(payload, valid); 3064 mlxsw_reg_ptce3_op_set(payload, op); 3065 mlxsw_reg_ptce3_priority_set(payload, priority); 3066 mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info); 3067 mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key); 3068 mlxsw_reg_ptce3_erp_id_set(payload, erp_id); 3069 mlxsw_reg_ptce3_delta_start_set(payload, delta_start); 3070 mlxsw_reg_ptce3_delta_mask_set(payload, delta_mask); 3071 mlxsw_reg_ptce3_delta_value_set(payload, delta_value); 3072 mlxsw_reg_ptce3_large_exists_set(payload, large_exists); 3073 mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id); 3074 mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer); 3075 } 3076 3077 /* PERCR - Policy-Engine Region Configuration Register 3078 * --------------------------------------------------- 3079 * This register configures the region parameters. The region_id must be 3080 * allocated. 3081 */ 3082 #define MLXSW_REG_PERCR_ID 0x302A 3083 #define MLXSW_REG_PERCR_LEN 0x80 3084 3085 MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN); 3086 3087 /* reg_percr_region_id 3088 * Region identifier. 3089 * Range 0..cap_max_regions-1 3090 * Access: Index 3091 */ 3092 MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16); 3093 3094 /* reg_percr_atcam_ignore_prune 3095 * Ignore prune_vector by other A-TCAM rules. Used e.g., for a new rule. 3096 * Access: RW 3097 */ 3098 MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1); 3099 3100 /* reg_percr_ctcam_ignore_prune 3101 * Ignore prune_ctcam by other A-TCAM rules. Used e.g., for a new rule. 3102 * Access: RW 3103 */ 3104 MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1); 3105 3106 /* reg_percr_bf_bypass 3107 * Bloom filter bypass. 3108 * 0 - Bloom filter is used (default) 3109 * 1 - Bloom filter is bypassed. The bypass is an OR condition of 3110 * region_id or eRP. See PERPT.bf_bypass 3111 * Access: RW 3112 */ 3113 MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1); 3114 3115 /* reg_percr_master_mask 3116 * Master mask. Logical OR mask of all masks of all rules of a region 3117 * (both A-TCAM and C-TCAM). When there are no eRPs 3118 * (erpt_pointer_valid = 0), then this provides the mask. 3119 * Access: RW 3120 */ 3121 MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96); 3122 3123 static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id) 3124 { 3125 MLXSW_REG_ZERO(percr, payload); 3126 mlxsw_reg_percr_region_id_set(payload, region_id); 3127 mlxsw_reg_percr_atcam_ignore_prune_set(payload, false); 3128 mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false); 3129 mlxsw_reg_percr_bf_bypass_set(payload, false); 3130 } 3131 3132 /* PERERP - Policy-Engine Region eRP Register 3133 * ------------------------------------------ 3134 * This register configures the region eRP. The region_id must be 3135 * allocated. 3136 */ 3137 #define MLXSW_REG_PERERP_ID 0x302B 3138 #define MLXSW_REG_PERERP_LEN 0x1C 3139 3140 MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN); 3141 3142 /* reg_pererp_region_id 3143 * Region identifier. 3144 * Range 0..cap_max_regions-1 3145 * Access: Index 3146 */ 3147 MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16); 3148 3149 /* reg_pererp_ctcam_le 3150 * C-TCAM lookup enable. Reserved when erpt_pointer_valid = 0. 3151 * Access: RW 3152 */ 3153 MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1); 3154 3155 /* reg_pererp_erpt_pointer_valid 3156 * erpt_pointer is valid. 3157 * Access: RW 3158 */ 3159 MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1); 3160 3161 /* reg_pererp_erpt_bank_pointer 3162 * Pointer to eRP table bank. May be modified at any time. 3163 * Range 0..cap_max_erp_table_banks-1 3164 * Reserved when erpt_pointer_valid = 0 3165 */ 3166 MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4); 3167 3168 /* reg_pererp_erpt_pointer 3169 * Pointer to eRP table within the eRP bank. Can be changed for an 3170 * existing region. 3171 * Range 0..cap_max_erp_table_size-1 3172 * Reserved when erpt_pointer_valid = 0 3173 * Access: RW 3174 */ 3175 MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8); 3176 3177 /* reg_pererp_erpt_vector 3178 * Vector of allowed eRP indexes starting from erpt_pointer within the 3179 * erpt_bank_pointer. Next entries will be in next bank. 3180 * Note that eRP index is used and not eRP ID. 3181 * Reserved when erpt_pointer_valid = 0 3182 * Access: RW 3183 */ 3184 MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1); 3185 3186 /* reg_pererp_master_rp_id 3187 * Master RP ID. When there are no eRPs, then this provides the eRP ID 3188 * for the lookup. Can be changed for an existing region. 3189 * Reserved when erpt_pointer_valid = 1 3190 * Access: RW 3191 */ 3192 MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4); 3193 3194 static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload, 3195 unsigned long *erp_vector, 3196 unsigned long size) 3197 { 3198 unsigned long bit; 3199 3200 for_each_set_bit(bit, erp_vector, size) 3201 mlxsw_reg_pererp_erpt_vector_set(payload, bit, true); 3202 } 3203 3204 static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id, 3205 bool ctcam_le, bool erpt_pointer_valid, 3206 u8 erpt_bank_pointer, u8 erpt_pointer, 3207 u8 master_rp_id) 3208 { 3209 MLXSW_REG_ZERO(pererp, payload); 3210 mlxsw_reg_pererp_region_id_set(payload, region_id); 3211 mlxsw_reg_pererp_ctcam_le_set(payload, ctcam_le); 3212 mlxsw_reg_pererp_erpt_pointer_valid_set(payload, erpt_pointer_valid); 3213 mlxsw_reg_pererp_erpt_bank_pointer_set(payload, erpt_bank_pointer); 3214 mlxsw_reg_pererp_erpt_pointer_set(payload, erpt_pointer); 3215 mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id); 3216 } 3217 3218 /* PEABFE - Policy-Engine Algorithmic Bloom Filter Entries Register 3219 * ---------------------------------------------------------------- 3220 * This register configures the Bloom filter entries. 3221 */ 3222 #define MLXSW_REG_PEABFE_ID 0x3022 3223 #define MLXSW_REG_PEABFE_BASE_LEN 0x10 3224 #define MLXSW_REG_PEABFE_BF_REC_LEN 0x4 3225 #define MLXSW_REG_PEABFE_BF_REC_MAX_COUNT 256 3226 #define MLXSW_REG_PEABFE_LEN (MLXSW_REG_PEABFE_BASE_LEN + \ 3227 MLXSW_REG_PEABFE_BF_REC_LEN * \ 3228 MLXSW_REG_PEABFE_BF_REC_MAX_COUNT) 3229 3230 MLXSW_REG_DEFINE(peabfe, MLXSW_REG_PEABFE_ID, MLXSW_REG_PEABFE_LEN); 3231 3232 /* reg_peabfe_size 3233 * Number of BF entries to be updated. 3234 * Range 1..256 3235 * Access: Op 3236 */ 3237 MLXSW_ITEM32(reg, peabfe, size, 0x00, 0, 9); 3238 3239 /* reg_peabfe_bf_entry_state 3240 * Bloom filter state 3241 * 0 - Clear 3242 * 1 - Set 3243 * Access: RW 3244 */ 3245 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_state, 3246 MLXSW_REG_PEABFE_BASE_LEN, 31, 1, 3247 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3248 3249 /* reg_peabfe_bf_entry_bank 3250 * Bloom filter bank ID 3251 * Range 0..cap_max_erp_table_banks-1 3252 * Access: Index 3253 */ 3254 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_bank, 3255 MLXSW_REG_PEABFE_BASE_LEN, 24, 4, 3256 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3257 3258 /* reg_peabfe_bf_entry_index 3259 * Bloom filter entry index 3260 * Range 0..2^cap_max_bf_log-1 3261 * Access: Index 3262 */ 3263 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_index, 3264 MLXSW_REG_PEABFE_BASE_LEN, 0, 24, 3265 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3266 3267 static inline void mlxsw_reg_peabfe_pack(char *payload) 3268 { 3269 MLXSW_REG_ZERO(peabfe, payload); 3270 } 3271 3272 static inline void mlxsw_reg_peabfe_rec_pack(char *payload, int rec_index, 3273 u8 state, u8 bank, u32 bf_index) 3274 { 3275 u8 num_rec = mlxsw_reg_peabfe_size_get(payload); 3276 3277 if (rec_index >= num_rec) 3278 mlxsw_reg_peabfe_size_set(payload, rec_index + 1); 3279 mlxsw_reg_peabfe_bf_entry_state_set(payload, rec_index, state); 3280 mlxsw_reg_peabfe_bf_entry_bank_set(payload, rec_index, bank); 3281 mlxsw_reg_peabfe_bf_entry_index_set(payload, rec_index, bf_index); 3282 } 3283 3284 /* IEDR - Infrastructure Entry Delete Register 3285 * ---------------------------------------------------- 3286 * This register is used for deleting entries from the entry tables. 3287 * It is legitimate to attempt to delete a nonexisting entry (the device will 3288 * respond as a good flow). 3289 */ 3290 #define MLXSW_REG_IEDR_ID 0x3804 3291 #define MLXSW_REG_IEDR_BASE_LEN 0x10 /* base length, without records */ 3292 #define MLXSW_REG_IEDR_REC_LEN 0x8 /* record length */ 3293 #define MLXSW_REG_IEDR_REC_MAX_COUNT 64 3294 #define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN + \ 3295 MLXSW_REG_IEDR_REC_LEN * \ 3296 MLXSW_REG_IEDR_REC_MAX_COUNT) 3297 3298 MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN); 3299 3300 /* reg_iedr_num_rec 3301 * Number of records. 3302 * Access: OP 3303 */ 3304 MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8); 3305 3306 /* reg_iedr_rec_type 3307 * Resource type. 3308 * Access: OP 3309 */ 3310 MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8, 3311 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3312 3313 /* reg_iedr_rec_size 3314 * Size of entries do be deleted. The unit is 1 entry, regardless of entry type. 3315 * Access: OP 3316 */ 3317 MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 13, 3318 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3319 3320 /* reg_iedr_rec_index_start 3321 * Resource index start. 3322 * Access: OP 3323 */ 3324 MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24, 3325 MLXSW_REG_IEDR_REC_LEN, 0x04, false); 3326 3327 static inline void mlxsw_reg_iedr_pack(char *payload) 3328 { 3329 MLXSW_REG_ZERO(iedr, payload); 3330 } 3331 3332 static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index, 3333 u8 rec_type, u16 rec_size, 3334 u32 rec_index_start) 3335 { 3336 u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload); 3337 3338 if (rec_index >= num_rec) 3339 mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1); 3340 mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type); 3341 mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size); 3342 mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start); 3343 } 3344 3345 /* QPTS - QoS Priority Trust State Register 3346 * ---------------------------------------- 3347 * This register controls the port policy to calculate the switch priority and 3348 * packet color based on incoming packet fields. 3349 */ 3350 #define MLXSW_REG_QPTS_ID 0x4002 3351 #define MLXSW_REG_QPTS_LEN 0x8 3352 3353 MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN); 3354 3355 /* reg_qpts_local_port 3356 * Local port number. 3357 * Access: Index 3358 * 3359 * Note: CPU port is supported. 3360 */ 3361 MLXSW_ITEM32(reg, qpts, local_port, 0x00, 16, 8); 3362 3363 enum mlxsw_reg_qpts_trust_state { 3364 MLXSW_REG_QPTS_TRUST_STATE_PCP = 1, 3365 MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2, /* For MPLS, trust EXP. */ 3366 }; 3367 3368 /* reg_qpts_trust_state 3369 * Trust state for a given port. 3370 * Access: RW 3371 */ 3372 MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3); 3373 3374 static inline void mlxsw_reg_qpts_pack(char *payload, u8 local_port, 3375 enum mlxsw_reg_qpts_trust_state ts) 3376 { 3377 MLXSW_REG_ZERO(qpts, payload); 3378 3379 mlxsw_reg_qpts_local_port_set(payload, local_port); 3380 mlxsw_reg_qpts_trust_state_set(payload, ts); 3381 } 3382 3383 /* QPCR - QoS Policer Configuration Register 3384 * ----------------------------------------- 3385 * The QPCR register is used to create policers - that limit 3386 * the rate of bytes or packets via some trap group. 3387 */ 3388 #define MLXSW_REG_QPCR_ID 0x4004 3389 #define MLXSW_REG_QPCR_LEN 0x28 3390 3391 MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN); 3392 3393 enum mlxsw_reg_qpcr_g { 3394 MLXSW_REG_QPCR_G_GLOBAL = 2, 3395 MLXSW_REG_QPCR_G_STORM_CONTROL = 3, 3396 }; 3397 3398 /* reg_qpcr_g 3399 * The policer type. 3400 * Access: Index 3401 */ 3402 MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2); 3403 3404 /* reg_qpcr_pid 3405 * Policer ID. 3406 * Access: Index 3407 */ 3408 MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14); 3409 3410 /* reg_qpcr_clear_counter 3411 * Clear counters. 3412 * Access: OP 3413 */ 3414 MLXSW_ITEM32(reg, qpcr, clear_counter, 0x04, 31, 1); 3415 3416 /* reg_qpcr_color_aware 3417 * Is the policer aware of colors. 3418 * Must be 0 (unaware) for cpu port. 3419 * Access: RW for unbounded policer. RO for bounded policer. 3420 */ 3421 MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1); 3422 3423 /* reg_qpcr_bytes 3424 * Is policer limit is for bytes per sec or packets per sec. 3425 * 0 - packets 3426 * 1 - bytes 3427 * Access: RW for unbounded policer. RO for bounded policer. 3428 */ 3429 MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1); 3430 3431 enum mlxsw_reg_qpcr_ir_units { 3432 MLXSW_REG_QPCR_IR_UNITS_M, 3433 MLXSW_REG_QPCR_IR_UNITS_K, 3434 }; 3435 3436 /* reg_qpcr_ir_units 3437 * Policer's units for cir and eir fields (for bytes limits only) 3438 * 1 - 10^3 3439 * 0 - 10^6 3440 * Access: OP 3441 */ 3442 MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1); 3443 3444 enum mlxsw_reg_qpcr_rate_type { 3445 MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1, 3446 MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2, 3447 }; 3448 3449 /* reg_qpcr_rate_type 3450 * Policer can have one limit (single rate) or 2 limits with specific operation 3451 * for packets that exceed the lower rate but not the upper one. 3452 * (For cpu port must be single rate) 3453 * Access: RW for unbounded policer. RO for bounded policer. 3454 */ 3455 MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2); 3456 3457 /* reg_qpc_cbs 3458 * Policer's committed burst size. 3459 * The policer is working with time slices of 50 nano sec. By default every 3460 * slice is granted the proportionate share of the committed rate. If we want to 3461 * allow a slice to exceed that share (while still keeping the rate per sec) we 3462 * can allow burst. The burst size is between the default proportionate share 3463 * (and no lower than 8) to 32Gb. (Even though giving a number higher than the 3464 * committed rate will result in exceeding the rate). The burst size must be a 3465 * log of 2 and will be determined by 2^cbs. 3466 * Access: RW 3467 */ 3468 MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6); 3469 3470 /* reg_qpcr_cir 3471 * Policer's committed rate. 3472 * The rate used for sungle rate, the lower rate for double rate. 3473 * For bytes limits, the rate will be this value * the unit from ir_units. 3474 * (Resolution error is up to 1%). 3475 * Access: RW 3476 */ 3477 MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32); 3478 3479 /* reg_qpcr_eir 3480 * Policer's exceed rate. 3481 * The higher rate for double rate, reserved for single rate. 3482 * Lower rate for double rate policer. 3483 * For bytes limits, the rate will be this value * the unit from ir_units. 3484 * (Resolution error is up to 1%). 3485 * Access: RW 3486 */ 3487 MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32); 3488 3489 #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2 3490 3491 /* reg_qpcr_exceed_action. 3492 * What to do with packets between the 2 limits for double rate. 3493 * Access: RW for unbounded policer. RO for bounded policer. 3494 */ 3495 MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4); 3496 3497 enum mlxsw_reg_qpcr_action { 3498 /* Discard */ 3499 MLXSW_REG_QPCR_ACTION_DISCARD = 1, 3500 /* Forward and set color to red. 3501 * If the packet is intended to cpu port, it will be dropped. 3502 */ 3503 MLXSW_REG_QPCR_ACTION_FORWARD = 2, 3504 }; 3505 3506 /* reg_qpcr_violate_action 3507 * What to do with packets that cross the cir limit (for single rate) or the eir 3508 * limit (for double rate). 3509 * Access: RW for unbounded policer. RO for bounded policer. 3510 */ 3511 MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4); 3512 3513 /* reg_qpcr_violate_count 3514 * Counts the number of times violate_action happened on this PID. 3515 * Access: RW 3516 */ 3517 MLXSW_ITEM64(reg, qpcr, violate_count, 0x20, 0, 64); 3518 3519 /* Packets */ 3520 #define MLXSW_REG_QPCR_LOWEST_CIR 1 3521 #define MLXSW_REG_QPCR_HIGHEST_CIR (2 * 1000 * 1000 * 1000) /* 2Gpps */ 3522 #define MLXSW_REG_QPCR_LOWEST_CBS 4 3523 #define MLXSW_REG_QPCR_HIGHEST_CBS 24 3524 3525 /* Bandwidth */ 3526 #define MLXSW_REG_QPCR_LOWEST_CIR_BITS 1024 /* bps */ 3527 #define MLXSW_REG_QPCR_HIGHEST_CIR_BITS 2000000000000ULL /* 2Tbps */ 3528 #define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP1 4 3529 #define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP2 4 3530 #define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP1 25 3531 #define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP2 31 3532 3533 static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid, 3534 enum mlxsw_reg_qpcr_ir_units ir_units, 3535 bool bytes, u32 cir, u16 cbs) 3536 { 3537 MLXSW_REG_ZERO(qpcr, payload); 3538 mlxsw_reg_qpcr_pid_set(payload, pid); 3539 mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL); 3540 mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE); 3541 mlxsw_reg_qpcr_violate_action_set(payload, 3542 MLXSW_REG_QPCR_ACTION_DISCARD); 3543 mlxsw_reg_qpcr_cir_set(payload, cir); 3544 mlxsw_reg_qpcr_ir_units_set(payload, ir_units); 3545 mlxsw_reg_qpcr_bytes_set(payload, bytes); 3546 mlxsw_reg_qpcr_cbs_set(payload, cbs); 3547 } 3548 3549 /* QTCT - QoS Switch Traffic Class Table 3550 * ------------------------------------- 3551 * Configures the mapping between the packet switch priority and the 3552 * traffic class on the transmit port. 3553 */ 3554 #define MLXSW_REG_QTCT_ID 0x400A 3555 #define MLXSW_REG_QTCT_LEN 0x08 3556 3557 MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN); 3558 3559 /* reg_qtct_local_port 3560 * Local port number. 3561 * Access: Index 3562 * 3563 * Note: CPU port is not supported. 3564 */ 3565 MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8); 3566 3567 /* reg_qtct_sub_port 3568 * Virtual port within the physical port. 3569 * Should be set to 0 when virtual ports are not enabled on the port. 3570 * Access: Index 3571 */ 3572 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8); 3573 3574 /* reg_qtct_switch_prio 3575 * Switch priority. 3576 * Access: Index 3577 */ 3578 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4); 3579 3580 /* reg_qtct_tclass 3581 * Traffic class. 3582 * Default values: 3583 * switch_prio 0 : tclass 1 3584 * switch_prio 1 : tclass 0 3585 * switch_prio i : tclass i, for i > 1 3586 * Access: RW 3587 */ 3588 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4); 3589 3590 static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port, 3591 u8 switch_prio, u8 tclass) 3592 { 3593 MLXSW_REG_ZERO(qtct, payload); 3594 mlxsw_reg_qtct_local_port_set(payload, local_port); 3595 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio); 3596 mlxsw_reg_qtct_tclass_set(payload, tclass); 3597 } 3598 3599 /* QEEC - QoS ETS Element Configuration Register 3600 * --------------------------------------------- 3601 * Configures the ETS elements. 3602 */ 3603 #define MLXSW_REG_QEEC_ID 0x400D 3604 #define MLXSW_REG_QEEC_LEN 0x20 3605 3606 MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN); 3607 3608 /* reg_qeec_local_port 3609 * Local port number. 3610 * Access: Index 3611 * 3612 * Note: CPU port is supported. 3613 */ 3614 MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8); 3615 3616 enum mlxsw_reg_qeec_hr { 3617 MLXSW_REG_QEEC_HR_PORT, 3618 MLXSW_REG_QEEC_HR_GROUP, 3619 MLXSW_REG_QEEC_HR_SUBGROUP, 3620 MLXSW_REG_QEEC_HR_TC, 3621 }; 3622 3623 /* reg_qeec_element_hierarchy 3624 * 0 - Port 3625 * 1 - Group 3626 * 2 - Subgroup 3627 * 3 - Traffic Class 3628 * Access: Index 3629 */ 3630 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4); 3631 3632 /* reg_qeec_element_index 3633 * The index of the element in the hierarchy. 3634 * Access: Index 3635 */ 3636 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8); 3637 3638 /* reg_qeec_next_element_index 3639 * The index of the next (lower) element in the hierarchy. 3640 * Access: RW 3641 * 3642 * Note: Reserved for element_hierarchy 0. 3643 */ 3644 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8); 3645 3646 /* reg_qeec_mise 3647 * Min shaper configuration enable. Enables configuration of the min 3648 * shaper on this ETS element 3649 * 0 - Disable 3650 * 1 - Enable 3651 * Access: RW 3652 */ 3653 MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1); 3654 3655 /* reg_qeec_ptps 3656 * PTP shaper 3657 * 0: regular shaper mode 3658 * 1: PTP oriented shaper 3659 * Allowed only for hierarchy 0 3660 * Not supported for CPU port 3661 * Note that ptps mode may affect the shaper rates of all hierarchies 3662 * Supported only on Spectrum-1 3663 * Access: RW 3664 */ 3665 MLXSW_ITEM32(reg, qeec, ptps, 0x0C, 29, 1); 3666 3667 enum { 3668 MLXSW_REG_QEEC_BYTES_MODE, 3669 MLXSW_REG_QEEC_PACKETS_MODE, 3670 }; 3671 3672 /* reg_qeec_pb 3673 * Packets or bytes mode. 3674 * 0 - Bytes mode 3675 * 1 - Packets mode 3676 * Access: RW 3677 * 3678 * Note: Used for max shaper configuration. For Spectrum, packets mode 3679 * is supported only for traffic classes of CPU port. 3680 */ 3681 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1); 3682 3683 /* The smallest permitted min shaper rate. */ 3684 #define MLXSW_REG_QEEC_MIS_MIN 200000 /* Kbps */ 3685 3686 /* reg_qeec_min_shaper_rate 3687 * Min shaper information rate. 3688 * For CPU port, can only be configured for port hierarchy. 3689 * When in bytes mode, value is specified in units of 1000bps. 3690 * Access: RW 3691 */ 3692 MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28); 3693 3694 /* reg_qeec_mase 3695 * Max shaper configuration enable. Enables configuration of the max 3696 * shaper on this ETS element. 3697 * 0 - Disable 3698 * 1 - Enable 3699 * Access: RW 3700 */ 3701 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1); 3702 3703 /* The largest max shaper value possible to disable the shaper. */ 3704 #define MLXSW_REG_QEEC_MAS_DIS ((1u << 31) - 1) /* Kbps */ 3705 3706 /* reg_qeec_max_shaper_rate 3707 * Max shaper information rate. 3708 * For CPU port, can only be configured for port hierarchy. 3709 * When in bytes mode, value is specified in units of 1000bps. 3710 * Access: RW 3711 */ 3712 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 31); 3713 3714 /* reg_qeec_de 3715 * DWRR configuration enable. Enables configuration of the dwrr and 3716 * dwrr_weight. 3717 * 0 - Disable 3718 * 1 - Enable 3719 * Access: RW 3720 */ 3721 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1); 3722 3723 /* reg_qeec_dwrr 3724 * Transmission selection algorithm to use on the link going down from 3725 * the ETS element. 3726 * 0 - Strict priority 3727 * 1 - DWRR 3728 * Access: RW 3729 */ 3730 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1); 3731 3732 /* reg_qeec_dwrr_weight 3733 * DWRR weight on the link going down from the ETS element. The 3734 * percentage of bandwidth guaranteed to an ETS element within 3735 * its hierarchy. The sum of all weights across all ETS elements 3736 * within one hierarchy should be equal to 100. Reserved when 3737 * transmission selection algorithm is strict priority. 3738 * Access: RW 3739 */ 3740 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8); 3741 3742 /* reg_qeec_max_shaper_bs 3743 * Max shaper burst size 3744 * Burst size is 2^max_shaper_bs * 512 bits 3745 * For Spectrum-1: Range is: 5..25 3746 * For Spectrum-2: Range is: 11..25 3747 * Reserved when ptps = 1 3748 * Access: RW 3749 */ 3750 MLXSW_ITEM32(reg, qeec, max_shaper_bs, 0x1C, 0, 6); 3751 3752 #define MLXSW_REG_QEEC_HIGHEST_SHAPER_BS 25 3753 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1 5 3754 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2 11 3755 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3 5 3756 3757 static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port, 3758 enum mlxsw_reg_qeec_hr hr, u8 index, 3759 u8 next_index) 3760 { 3761 MLXSW_REG_ZERO(qeec, payload); 3762 mlxsw_reg_qeec_local_port_set(payload, local_port); 3763 mlxsw_reg_qeec_element_hierarchy_set(payload, hr); 3764 mlxsw_reg_qeec_element_index_set(payload, index); 3765 mlxsw_reg_qeec_next_element_index_set(payload, next_index); 3766 } 3767 3768 static inline void mlxsw_reg_qeec_ptps_pack(char *payload, u8 local_port, 3769 bool ptps) 3770 { 3771 MLXSW_REG_ZERO(qeec, payload); 3772 mlxsw_reg_qeec_local_port_set(payload, local_port); 3773 mlxsw_reg_qeec_element_hierarchy_set(payload, MLXSW_REG_QEEC_HR_PORT); 3774 mlxsw_reg_qeec_ptps_set(payload, ptps); 3775 } 3776 3777 /* QRWE - QoS ReWrite Enable 3778 * ------------------------- 3779 * This register configures the rewrite enable per receive port. 3780 */ 3781 #define MLXSW_REG_QRWE_ID 0x400F 3782 #define MLXSW_REG_QRWE_LEN 0x08 3783 3784 MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN); 3785 3786 /* reg_qrwe_local_port 3787 * Local port number. 3788 * Access: Index 3789 * 3790 * Note: CPU port is supported. No support for router port. 3791 */ 3792 MLXSW_ITEM32(reg, qrwe, local_port, 0x00, 16, 8); 3793 3794 /* reg_qrwe_dscp 3795 * Whether to enable DSCP rewrite (default is 0, don't rewrite). 3796 * Access: RW 3797 */ 3798 MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1); 3799 3800 /* reg_qrwe_pcp 3801 * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite). 3802 * Access: RW 3803 */ 3804 MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1); 3805 3806 static inline void mlxsw_reg_qrwe_pack(char *payload, u8 local_port, 3807 bool rewrite_pcp, bool rewrite_dscp) 3808 { 3809 MLXSW_REG_ZERO(qrwe, payload); 3810 mlxsw_reg_qrwe_local_port_set(payload, local_port); 3811 mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp); 3812 mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp); 3813 } 3814 3815 /* QPDSM - QoS Priority to DSCP Mapping 3816 * ------------------------------------ 3817 * QoS Priority to DSCP Mapping Register 3818 */ 3819 #define MLXSW_REG_QPDSM_ID 0x4011 3820 #define MLXSW_REG_QPDSM_BASE_LEN 0x04 /* base length, without records */ 3821 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4 /* record length */ 3822 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 16 3823 #define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN + \ 3824 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN * \ 3825 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT) 3826 3827 MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN); 3828 3829 /* reg_qpdsm_local_port 3830 * Local Port. Supported for data packets from CPU port. 3831 * Access: Index 3832 */ 3833 MLXSW_ITEM32(reg, qpdsm, local_port, 0x00, 16, 8); 3834 3835 /* reg_qpdsm_prio_entry_color0_e 3836 * Enable update of the entry for color 0 and a given port. 3837 * Access: WO 3838 */ 3839 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e, 3840 MLXSW_REG_QPDSM_BASE_LEN, 31, 1, 3841 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3842 3843 /* reg_qpdsm_prio_entry_color0_dscp 3844 * DSCP field in the outer label of the packet for color 0 and a given port. 3845 * Reserved when e=0. 3846 * Access: RW 3847 */ 3848 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp, 3849 MLXSW_REG_QPDSM_BASE_LEN, 24, 6, 3850 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3851 3852 /* reg_qpdsm_prio_entry_color1_e 3853 * Enable update of the entry for color 1 and a given port. 3854 * Access: WO 3855 */ 3856 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e, 3857 MLXSW_REG_QPDSM_BASE_LEN, 23, 1, 3858 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3859 3860 /* reg_qpdsm_prio_entry_color1_dscp 3861 * DSCP field in the outer label of the packet for color 1 and a given port. 3862 * Reserved when e=0. 3863 * Access: RW 3864 */ 3865 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp, 3866 MLXSW_REG_QPDSM_BASE_LEN, 16, 6, 3867 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3868 3869 /* reg_qpdsm_prio_entry_color2_e 3870 * Enable update of the entry for color 2 and a given port. 3871 * Access: WO 3872 */ 3873 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e, 3874 MLXSW_REG_QPDSM_BASE_LEN, 15, 1, 3875 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3876 3877 /* reg_qpdsm_prio_entry_color2_dscp 3878 * DSCP field in the outer label of the packet for color 2 and a given port. 3879 * Reserved when e=0. 3880 * Access: RW 3881 */ 3882 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp, 3883 MLXSW_REG_QPDSM_BASE_LEN, 8, 6, 3884 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3885 3886 static inline void mlxsw_reg_qpdsm_pack(char *payload, u8 local_port) 3887 { 3888 MLXSW_REG_ZERO(qpdsm, payload); 3889 mlxsw_reg_qpdsm_local_port_set(payload, local_port); 3890 } 3891 3892 static inline void 3893 mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp) 3894 { 3895 mlxsw_reg_qpdsm_prio_entry_color0_e_set(payload, prio, 1); 3896 mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(payload, prio, dscp); 3897 mlxsw_reg_qpdsm_prio_entry_color1_e_set(payload, prio, 1); 3898 mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(payload, prio, dscp); 3899 mlxsw_reg_qpdsm_prio_entry_color2_e_set(payload, prio, 1); 3900 mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp); 3901 } 3902 3903 /* QPDP - QoS Port DSCP to Priority Mapping Register 3904 * ------------------------------------------------- 3905 * This register controls the port default Switch Priority and Color. The 3906 * default Switch Priority and Color are used for frames where the trust state 3907 * uses default values. All member ports of a LAG should be configured with the 3908 * same default values. 3909 */ 3910 #define MLXSW_REG_QPDP_ID 0x4007 3911 #define MLXSW_REG_QPDP_LEN 0x8 3912 3913 MLXSW_REG_DEFINE(qpdp, MLXSW_REG_QPDP_ID, MLXSW_REG_QPDP_LEN); 3914 3915 /* reg_qpdp_local_port 3916 * Local Port. Supported for data packets from CPU port. 3917 * Access: Index 3918 */ 3919 MLXSW_ITEM32(reg, qpdp, local_port, 0x00, 16, 8); 3920 3921 /* reg_qpdp_switch_prio 3922 * Default port Switch Priority (default 0) 3923 * Access: RW 3924 */ 3925 MLXSW_ITEM32(reg, qpdp, switch_prio, 0x04, 0, 4); 3926 3927 static inline void mlxsw_reg_qpdp_pack(char *payload, u8 local_port, 3928 u8 switch_prio) 3929 { 3930 MLXSW_REG_ZERO(qpdp, payload); 3931 mlxsw_reg_qpdp_local_port_set(payload, local_port); 3932 mlxsw_reg_qpdp_switch_prio_set(payload, switch_prio); 3933 } 3934 3935 /* QPDPM - QoS Port DSCP to Priority Mapping Register 3936 * -------------------------------------------------- 3937 * This register controls the mapping from DSCP field to 3938 * Switch Priority for IP packets. 3939 */ 3940 #define MLXSW_REG_QPDPM_ID 0x4013 3941 #define MLXSW_REG_QPDPM_BASE_LEN 0x4 /* base length, without records */ 3942 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2 /* record length */ 3943 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64 3944 #define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN + \ 3945 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN * \ 3946 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT) 3947 3948 MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN); 3949 3950 /* reg_qpdpm_local_port 3951 * Local Port. Supported for data packets from CPU port. 3952 * Access: Index 3953 */ 3954 MLXSW_ITEM32(reg, qpdpm, local_port, 0x00, 16, 8); 3955 3956 /* reg_qpdpm_dscp_e 3957 * Enable update of the specific entry. When cleared, the switch_prio and color 3958 * fields are ignored and the previous switch_prio and color values are 3959 * preserved. 3960 * Access: WO 3961 */ 3962 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1, 3963 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 3964 3965 /* reg_qpdpm_dscp_prio 3966 * The new Switch Priority value for the relevant DSCP value. 3967 * Access: RW 3968 */ 3969 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio, 3970 MLXSW_REG_QPDPM_BASE_LEN, 0, 4, 3971 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 3972 3973 static inline void mlxsw_reg_qpdpm_pack(char *payload, u8 local_port) 3974 { 3975 MLXSW_REG_ZERO(qpdpm, payload); 3976 mlxsw_reg_qpdpm_local_port_set(payload, local_port); 3977 } 3978 3979 static inline void 3980 mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio) 3981 { 3982 mlxsw_reg_qpdpm_dscp_entry_e_set(payload, dscp, 1); 3983 mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio); 3984 } 3985 3986 /* QTCTM - QoS Switch Traffic Class Table is Multicast-Aware Register 3987 * ------------------------------------------------------------------ 3988 * This register configures if the Switch Priority to Traffic Class mapping is 3989 * based on Multicast packet indication. If so, then multicast packets will get 3990 * a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by 3991 * QTCT. 3992 * By default, Switch Priority to Traffic Class mapping is not based on 3993 * Multicast packet indication. 3994 */ 3995 #define MLXSW_REG_QTCTM_ID 0x401A 3996 #define MLXSW_REG_QTCTM_LEN 0x08 3997 3998 MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN); 3999 4000 /* reg_qtctm_local_port 4001 * Local port number. 4002 * No support for CPU port. 4003 * Access: Index 4004 */ 4005 MLXSW_ITEM32(reg, qtctm, local_port, 0x00, 16, 8); 4006 4007 /* reg_qtctm_mc 4008 * Multicast Mode 4009 * Whether Switch Priority to Traffic Class mapping is based on Multicast packet 4010 * indication (default is 0, not based on Multicast packet indication). 4011 */ 4012 MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1); 4013 4014 static inline void 4015 mlxsw_reg_qtctm_pack(char *payload, u8 local_port, bool mc) 4016 { 4017 MLXSW_REG_ZERO(qtctm, payload); 4018 mlxsw_reg_qtctm_local_port_set(payload, local_port); 4019 mlxsw_reg_qtctm_mc_set(payload, mc); 4020 } 4021 4022 /* QPSC - QoS PTP Shaper Configuration Register 4023 * -------------------------------------------- 4024 * The QPSC allows advanced configuration of the shapers when QEEC.ptps=1. 4025 * Supported only on Spectrum-1. 4026 */ 4027 #define MLXSW_REG_QPSC_ID 0x401B 4028 #define MLXSW_REG_QPSC_LEN 0x28 4029 4030 MLXSW_REG_DEFINE(qpsc, MLXSW_REG_QPSC_ID, MLXSW_REG_QPSC_LEN); 4031 4032 enum mlxsw_reg_qpsc_port_speed { 4033 MLXSW_REG_QPSC_PORT_SPEED_100M, 4034 MLXSW_REG_QPSC_PORT_SPEED_1G, 4035 MLXSW_REG_QPSC_PORT_SPEED_10G, 4036 MLXSW_REG_QPSC_PORT_SPEED_25G, 4037 }; 4038 4039 /* reg_qpsc_port_speed 4040 * Port speed. 4041 * Access: Index 4042 */ 4043 MLXSW_ITEM32(reg, qpsc, port_speed, 0x00, 0, 4); 4044 4045 /* reg_qpsc_shaper_time_exp 4046 * The base-time-interval for updating the shapers tokens (for all hierarchies). 4047 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec 4048 * shaper_rate = 64bit * shaper_inc / shaper_update_rate 4049 * Access: RW 4050 */ 4051 MLXSW_ITEM32(reg, qpsc, shaper_time_exp, 0x04, 16, 4); 4052 4053 /* reg_qpsc_shaper_time_mantissa 4054 * The base-time-interval for updating the shapers tokens (for all hierarchies). 4055 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec 4056 * shaper_rate = 64bit * shaper_inc / shaper_update_rate 4057 * Access: RW 4058 */ 4059 MLXSW_ITEM32(reg, qpsc, shaper_time_mantissa, 0x04, 0, 5); 4060 4061 /* reg_qpsc_shaper_inc 4062 * Number of tokens added to shaper on each update. 4063 * Units of 8B. 4064 * Access: RW 4065 */ 4066 MLXSW_ITEM32(reg, qpsc, shaper_inc, 0x08, 0, 5); 4067 4068 /* reg_qpsc_shaper_bs 4069 * Max shaper Burst size. 4070 * Burst size is 2 ^ max_shaper_bs * 512 [bits] 4071 * Range is: 5..25 (from 2KB..2GB) 4072 * Access: RW 4073 */ 4074 MLXSW_ITEM32(reg, qpsc, shaper_bs, 0x0C, 0, 6); 4075 4076 /* reg_qpsc_ptsc_we 4077 * Write enable to port_to_shaper_credits. 4078 * Access: WO 4079 */ 4080 MLXSW_ITEM32(reg, qpsc, ptsc_we, 0x10, 31, 1); 4081 4082 /* reg_qpsc_port_to_shaper_credits 4083 * For split ports: range 1..57 4084 * For non-split ports: range 1..112 4085 * Written only when ptsc_we is set. 4086 * Access: RW 4087 */ 4088 MLXSW_ITEM32(reg, qpsc, port_to_shaper_credits, 0x10, 0, 8); 4089 4090 /* reg_qpsc_ing_timestamp_inc 4091 * Ingress timestamp increment. 4092 * 2's complement. 4093 * The timestamp of MTPPTR at ingress will be incremented by this value. Global 4094 * value for all ports. 4095 * Same units as used by MTPPTR. 4096 * Access: RW 4097 */ 4098 MLXSW_ITEM32(reg, qpsc, ing_timestamp_inc, 0x20, 0, 32); 4099 4100 /* reg_qpsc_egr_timestamp_inc 4101 * Egress timestamp increment. 4102 * 2's complement. 4103 * The timestamp of MTPPTR at egress will be incremented by this value. Global 4104 * value for all ports. 4105 * Same units as used by MTPPTR. 4106 * Access: RW 4107 */ 4108 MLXSW_ITEM32(reg, qpsc, egr_timestamp_inc, 0x24, 0, 32); 4109 4110 static inline void 4111 mlxsw_reg_qpsc_pack(char *payload, enum mlxsw_reg_qpsc_port_speed port_speed, 4112 u8 shaper_time_exp, u8 shaper_time_mantissa, u8 shaper_inc, 4113 u8 shaper_bs, u8 port_to_shaper_credits, 4114 int ing_timestamp_inc, int egr_timestamp_inc) 4115 { 4116 MLXSW_REG_ZERO(qpsc, payload); 4117 mlxsw_reg_qpsc_port_speed_set(payload, port_speed); 4118 mlxsw_reg_qpsc_shaper_time_exp_set(payload, shaper_time_exp); 4119 mlxsw_reg_qpsc_shaper_time_mantissa_set(payload, shaper_time_mantissa); 4120 mlxsw_reg_qpsc_shaper_inc_set(payload, shaper_inc); 4121 mlxsw_reg_qpsc_shaper_bs_set(payload, shaper_bs); 4122 mlxsw_reg_qpsc_ptsc_we_set(payload, true); 4123 mlxsw_reg_qpsc_port_to_shaper_credits_set(payload, port_to_shaper_credits); 4124 mlxsw_reg_qpsc_ing_timestamp_inc_set(payload, ing_timestamp_inc); 4125 mlxsw_reg_qpsc_egr_timestamp_inc_set(payload, egr_timestamp_inc); 4126 } 4127 4128 /* PMLP - Ports Module to Local Port Register 4129 * ------------------------------------------ 4130 * Configures the assignment of modules to local ports. 4131 */ 4132 #define MLXSW_REG_PMLP_ID 0x5002 4133 #define MLXSW_REG_PMLP_LEN 0x40 4134 4135 MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN); 4136 4137 /* reg_pmlp_rxtx 4138 * 0 - Tx value is used for both Tx and Rx. 4139 * 1 - Rx value is taken from a separte field. 4140 * Access: RW 4141 */ 4142 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1); 4143 4144 /* reg_pmlp_local_port 4145 * Local port number. 4146 * Access: Index 4147 */ 4148 MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8); 4149 4150 /* reg_pmlp_width 4151 * 0 - Unmap local port. 4152 * 1 - Lane 0 is used. 4153 * 2 - Lanes 0 and 1 are used. 4154 * 4 - Lanes 0, 1, 2 and 3 are used. 4155 * 8 - Lanes 0-7 are used. 4156 * Access: RW 4157 */ 4158 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8); 4159 4160 /* reg_pmlp_module 4161 * Module number. 4162 * Access: RW 4163 */ 4164 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false); 4165 4166 /* reg_pmlp_tx_lane 4167 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well. 4168 * Access: RW 4169 */ 4170 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 4, 0x04, 0x00, false); 4171 4172 /* reg_pmlp_rx_lane 4173 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is 4174 * equal to Tx lane. 4175 * Access: RW 4176 */ 4177 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 4, 0x04, 0x00, false); 4178 4179 static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port) 4180 { 4181 MLXSW_REG_ZERO(pmlp, payload); 4182 mlxsw_reg_pmlp_local_port_set(payload, local_port); 4183 } 4184 4185 /* PMTU - Port MTU Register 4186 * ------------------------ 4187 * Configures and reports the port MTU. 4188 */ 4189 #define MLXSW_REG_PMTU_ID 0x5003 4190 #define MLXSW_REG_PMTU_LEN 0x10 4191 4192 MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN); 4193 4194 /* reg_pmtu_local_port 4195 * Local port number. 4196 * Access: Index 4197 */ 4198 MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8); 4199 4200 /* reg_pmtu_max_mtu 4201 * Maximum MTU. 4202 * When port type (e.g. Ethernet) is configured, the relevant MTU is 4203 * reported, otherwise the minimum between the max_mtu of the different 4204 * types is reported. 4205 * Access: RO 4206 */ 4207 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16); 4208 4209 /* reg_pmtu_admin_mtu 4210 * MTU value to set port to. Must be smaller or equal to max_mtu. 4211 * Note: If port type is Infiniband, then port must be disabled, when its 4212 * MTU is set. 4213 * Access: RW 4214 */ 4215 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16); 4216 4217 /* reg_pmtu_oper_mtu 4218 * The actual MTU configured on the port. Packets exceeding this size 4219 * will be dropped. 4220 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband 4221 * oper_mtu might be smaller than admin_mtu. 4222 * Access: RO 4223 */ 4224 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16); 4225 4226 static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port, 4227 u16 new_mtu) 4228 { 4229 MLXSW_REG_ZERO(pmtu, payload); 4230 mlxsw_reg_pmtu_local_port_set(payload, local_port); 4231 mlxsw_reg_pmtu_max_mtu_set(payload, 0); 4232 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu); 4233 mlxsw_reg_pmtu_oper_mtu_set(payload, 0); 4234 } 4235 4236 /* PTYS - Port Type and Speed Register 4237 * ----------------------------------- 4238 * Configures and reports the port speed type. 4239 * 4240 * Note: When set while the link is up, the changes will not take effect 4241 * until the port transitions from down to up state. 4242 */ 4243 #define MLXSW_REG_PTYS_ID 0x5004 4244 #define MLXSW_REG_PTYS_LEN 0x40 4245 4246 MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN); 4247 4248 /* an_disable_admin 4249 * Auto negotiation disable administrative configuration 4250 * 0 - Device doesn't support AN disable. 4251 * 1 - Device supports AN disable. 4252 * Access: RW 4253 */ 4254 MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1); 4255 4256 /* reg_ptys_local_port 4257 * Local port number. 4258 * Access: Index 4259 */ 4260 MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8); 4261 4262 #define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0) 4263 #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2) 4264 4265 /* reg_ptys_proto_mask 4266 * Protocol mask. Indicates which protocol is used. 4267 * 0 - Infiniband. 4268 * 1 - Fibre Channel. 4269 * 2 - Ethernet. 4270 * Access: Index 4271 */ 4272 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3); 4273 4274 enum { 4275 MLXSW_REG_PTYS_AN_STATUS_NA, 4276 MLXSW_REG_PTYS_AN_STATUS_OK, 4277 MLXSW_REG_PTYS_AN_STATUS_FAIL, 4278 }; 4279 4280 /* reg_ptys_an_status 4281 * Autonegotiation status. 4282 * Access: RO 4283 */ 4284 MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4); 4285 4286 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M BIT(0) 4287 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII BIT(1) 4288 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R BIT(3) 4289 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G BIT(4) 4290 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G BIT(5) 4291 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR BIT(6) 4292 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 BIT(7) 4293 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR BIT(8) 4294 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4 BIT(9) 4295 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2 BIT(10) 4296 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4 BIT(12) 4297 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_8 BIT(15) 4298 4299 /* reg_ptys_ext_eth_proto_cap 4300 * Extended Ethernet port supported speeds and protocols. 4301 * Access: RO 4302 */ 4303 MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32); 4304 4305 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0) 4306 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1) 4307 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2) 4308 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3) 4309 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4) 4310 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6) 4311 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7) 4312 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12) 4313 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13) 4314 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14) 4315 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15) 4316 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16) 4317 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18) 4318 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19) 4319 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20) 4320 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21) 4321 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22) 4322 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27) 4323 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28) 4324 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29) 4325 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30) 4326 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31) 4327 4328 /* reg_ptys_eth_proto_cap 4329 * Ethernet port supported speeds and protocols. 4330 * Access: RO 4331 */ 4332 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32); 4333 4334 /* reg_ptys_ib_link_width_cap 4335 * IB port supported widths. 4336 * Access: RO 4337 */ 4338 MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16); 4339 4340 #define MLXSW_REG_PTYS_IB_SPEED_SDR BIT(0) 4341 #define MLXSW_REG_PTYS_IB_SPEED_DDR BIT(1) 4342 #define MLXSW_REG_PTYS_IB_SPEED_QDR BIT(2) 4343 #define MLXSW_REG_PTYS_IB_SPEED_FDR10 BIT(3) 4344 #define MLXSW_REG_PTYS_IB_SPEED_FDR BIT(4) 4345 #define MLXSW_REG_PTYS_IB_SPEED_EDR BIT(5) 4346 4347 /* reg_ptys_ib_proto_cap 4348 * IB port supported speeds and protocols. 4349 * Access: RO 4350 */ 4351 MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16); 4352 4353 /* reg_ptys_ext_eth_proto_admin 4354 * Extended speed and protocol to set port to. 4355 * Access: RW 4356 */ 4357 MLXSW_ITEM32(reg, ptys, ext_eth_proto_admin, 0x14, 0, 32); 4358 4359 /* reg_ptys_eth_proto_admin 4360 * Speed and protocol to set port to. 4361 * Access: RW 4362 */ 4363 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32); 4364 4365 /* reg_ptys_ib_link_width_admin 4366 * IB width to set port to. 4367 * Access: RW 4368 */ 4369 MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16); 4370 4371 /* reg_ptys_ib_proto_admin 4372 * IB speeds and protocols to set port to. 4373 * Access: RW 4374 */ 4375 MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16); 4376 4377 /* reg_ptys_ext_eth_proto_oper 4378 * The extended current speed and protocol configured for the port. 4379 * Access: RO 4380 */ 4381 MLXSW_ITEM32(reg, ptys, ext_eth_proto_oper, 0x20, 0, 32); 4382 4383 /* reg_ptys_eth_proto_oper 4384 * The current speed and protocol configured for the port. 4385 * Access: RO 4386 */ 4387 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32); 4388 4389 /* reg_ptys_ib_link_width_oper 4390 * The current IB width to set port to. 4391 * Access: RO 4392 */ 4393 MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16); 4394 4395 /* reg_ptys_ib_proto_oper 4396 * The current IB speed and protocol. 4397 * Access: RO 4398 */ 4399 MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16); 4400 4401 enum mlxsw_reg_ptys_connector_type { 4402 MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR, 4403 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE, 4404 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP, 4405 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI, 4406 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC, 4407 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII, 4408 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE, 4409 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA, 4410 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER, 4411 }; 4412 4413 /* reg_ptys_connector_type 4414 * Connector type indication. 4415 * Access: RO 4416 */ 4417 MLXSW_ITEM32(reg, ptys, connector_type, 0x2C, 0, 4); 4418 4419 static inline void mlxsw_reg_ptys_eth_pack(char *payload, u8 local_port, 4420 u32 proto_admin, bool autoneg) 4421 { 4422 MLXSW_REG_ZERO(ptys, payload); 4423 mlxsw_reg_ptys_local_port_set(payload, local_port); 4424 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4425 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin); 4426 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4427 } 4428 4429 static inline void mlxsw_reg_ptys_ext_eth_pack(char *payload, u8 local_port, 4430 u32 proto_admin, bool autoneg) 4431 { 4432 MLXSW_REG_ZERO(ptys, payload); 4433 mlxsw_reg_ptys_local_port_set(payload, local_port); 4434 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4435 mlxsw_reg_ptys_ext_eth_proto_admin_set(payload, proto_admin); 4436 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4437 } 4438 4439 static inline void mlxsw_reg_ptys_eth_unpack(char *payload, 4440 u32 *p_eth_proto_cap, 4441 u32 *p_eth_proto_admin, 4442 u32 *p_eth_proto_oper) 4443 { 4444 if (p_eth_proto_cap) 4445 *p_eth_proto_cap = 4446 mlxsw_reg_ptys_eth_proto_cap_get(payload); 4447 if (p_eth_proto_admin) 4448 *p_eth_proto_admin = 4449 mlxsw_reg_ptys_eth_proto_admin_get(payload); 4450 if (p_eth_proto_oper) 4451 *p_eth_proto_oper = 4452 mlxsw_reg_ptys_eth_proto_oper_get(payload); 4453 } 4454 4455 static inline void mlxsw_reg_ptys_ext_eth_unpack(char *payload, 4456 u32 *p_eth_proto_cap, 4457 u32 *p_eth_proto_admin, 4458 u32 *p_eth_proto_oper) 4459 { 4460 if (p_eth_proto_cap) 4461 *p_eth_proto_cap = 4462 mlxsw_reg_ptys_ext_eth_proto_cap_get(payload); 4463 if (p_eth_proto_admin) 4464 *p_eth_proto_admin = 4465 mlxsw_reg_ptys_ext_eth_proto_admin_get(payload); 4466 if (p_eth_proto_oper) 4467 *p_eth_proto_oper = 4468 mlxsw_reg_ptys_ext_eth_proto_oper_get(payload); 4469 } 4470 4471 static inline void mlxsw_reg_ptys_ib_pack(char *payload, u8 local_port, 4472 u16 proto_admin, u16 link_width) 4473 { 4474 MLXSW_REG_ZERO(ptys, payload); 4475 mlxsw_reg_ptys_local_port_set(payload, local_port); 4476 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB); 4477 mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin); 4478 mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width); 4479 } 4480 4481 static inline void mlxsw_reg_ptys_ib_unpack(char *payload, u16 *p_ib_proto_cap, 4482 u16 *p_ib_link_width_cap, 4483 u16 *p_ib_proto_oper, 4484 u16 *p_ib_link_width_oper) 4485 { 4486 if (p_ib_proto_cap) 4487 *p_ib_proto_cap = mlxsw_reg_ptys_ib_proto_cap_get(payload); 4488 if (p_ib_link_width_cap) 4489 *p_ib_link_width_cap = 4490 mlxsw_reg_ptys_ib_link_width_cap_get(payload); 4491 if (p_ib_proto_oper) 4492 *p_ib_proto_oper = mlxsw_reg_ptys_ib_proto_oper_get(payload); 4493 if (p_ib_link_width_oper) 4494 *p_ib_link_width_oper = 4495 mlxsw_reg_ptys_ib_link_width_oper_get(payload); 4496 } 4497 4498 /* PPAD - Port Physical Address Register 4499 * ------------------------------------- 4500 * The PPAD register configures the per port physical MAC address. 4501 */ 4502 #define MLXSW_REG_PPAD_ID 0x5005 4503 #define MLXSW_REG_PPAD_LEN 0x10 4504 4505 MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN); 4506 4507 /* reg_ppad_single_base_mac 4508 * 0: base_mac, local port should be 0 and mac[7:0] is 4509 * reserved. HW will set incremental 4510 * 1: single_mac - mac of the local_port 4511 * Access: RW 4512 */ 4513 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1); 4514 4515 /* reg_ppad_local_port 4516 * port number, if single_base_mac = 0 then local_port is reserved 4517 * Access: RW 4518 */ 4519 MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8); 4520 4521 /* reg_ppad_mac 4522 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved. 4523 * If single_base_mac = 1 - the per port MAC address 4524 * Access: RW 4525 */ 4526 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6); 4527 4528 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac, 4529 u8 local_port) 4530 { 4531 MLXSW_REG_ZERO(ppad, payload); 4532 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac); 4533 mlxsw_reg_ppad_local_port_set(payload, local_port); 4534 } 4535 4536 /* PAOS - Ports Administrative and Operational Status Register 4537 * ----------------------------------------------------------- 4538 * Configures and retrieves per port administrative and operational status. 4539 */ 4540 #define MLXSW_REG_PAOS_ID 0x5006 4541 #define MLXSW_REG_PAOS_LEN 0x10 4542 4543 MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN); 4544 4545 /* reg_paos_swid 4546 * Switch partition ID with which to associate the port. 4547 * Note: while external ports uses unique local port numbers (and thus swid is 4548 * redundant), router ports use the same local port number where swid is the 4549 * only indication for the relevant port. 4550 * Access: Index 4551 */ 4552 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8); 4553 4554 /* reg_paos_local_port 4555 * Local port number. 4556 * Access: Index 4557 */ 4558 MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8); 4559 4560 /* reg_paos_admin_status 4561 * Port administrative state (the desired state of the port): 4562 * 1 - Up. 4563 * 2 - Down. 4564 * 3 - Up once. This means that in case of link failure, the port won't go 4565 * into polling mode, but will wait to be re-enabled by software. 4566 * 4 - Disabled by system. Can only be set by hardware. 4567 * Access: RW 4568 */ 4569 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4); 4570 4571 /* reg_paos_oper_status 4572 * Port operational state (the current state): 4573 * 1 - Up. 4574 * 2 - Down. 4575 * 3 - Down by port failure. This means that the device will not let the 4576 * port up again until explicitly specified by software. 4577 * Access: RO 4578 */ 4579 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4); 4580 4581 /* reg_paos_ase 4582 * Admin state update enabled. 4583 * Access: WO 4584 */ 4585 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1); 4586 4587 /* reg_paos_ee 4588 * Event update enable. If this bit is set, event generation will be 4589 * updated based on the e field. 4590 * Access: WO 4591 */ 4592 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1); 4593 4594 /* reg_paos_e 4595 * Event generation on operational state change: 4596 * 0 - Do not generate event. 4597 * 1 - Generate Event. 4598 * 2 - Generate Single Event. 4599 * Access: RW 4600 */ 4601 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2); 4602 4603 static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port, 4604 enum mlxsw_port_admin_status status) 4605 { 4606 MLXSW_REG_ZERO(paos, payload); 4607 mlxsw_reg_paos_swid_set(payload, 0); 4608 mlxsw_reg_paos_local_port_set(payload, local_port); 4609 mlxsw_reg_paos_admin_status_set(payload, status); 4610 mlxsw_reg_paos_oper_status_set(payload, 0); 4611 mlxsw_reg_paos_ase_set(payload, 1); 4612 mlxsw_reg_paos_ee_set(payload, 1); 4613 mlxsw_reg_paos_e_set(payload, 1); 4614 } 4615 4616 /* PFCC - Ports Flow Control Configuration Register 4617 * ------------------------------------------------ 4618 * Configures and retrieves the per port flow control configuration. 4619 */ 4620 #define MLXSW_REG_PFCC_ID 0x5007 4621 #define MLXSW_REG_PFCC_LEN 0x20 4622 4623 MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN); 4624 4625 /* reg_pfcc_local_port 4626 * Local port number. 4627 * Access: Index 4628 */ 4629 MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8); 4630 4631 /* reg_pfcc_pnat 4632 * Port number access type. Determines the way local_port is interpreted: 4633 * 0 - Local port number. 4634 * 1 - IB / label port number. 4635 * Access: Index 4636 */ 4637 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2); 4638 4639 /* reg_pfcc_shl_cap 4640 * Send to higher layers capabilities: 4641 * 0 - No capability of sending Pause and PFC frames to higher layers. 4642 * 1 - Device has capability of sending Pause and PFC frames to higher 4643 * layers. 4644 * Access: RO 4645 */ 4646 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1); 4647 4648 /* reg_pfcc_shl_opr 4649 * Send to higher layers operation: 4650 * 0 - Pause and PFC frames are handled by the port (default). 4651 * 1 - Pause and PFC frames are handled by the port and also sent to 4652 * higher layers. Only valid if shl_cap = 1. 4653 * Access: RW 4654 */ 4655 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1); 4656 4657 /* reg_pfcc_ppan 4658 * Pause policy auto negotiation. 4659 * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx. 4660 * 1 - Enabled. When auto-negotiation is performed, set the Pause policy 4661 * based on the auto-negotiation resolution. 4662 * Access: RW 4663 * 4664 * Note: The auto-negotiation advertisement is set according to pptx and 4665 * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0. 4666 */ 4667 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4); 4668 4669 /* reg_pfcc_prio_mask_tx 4670 * Bit per priority indicating if Tx flow control policy should be 4671 * updated based on bit pfctx. 4672 * Access: WO 4673 */ 4674 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8); 4675 4676 /* reg_pfcc_prio_mask_rx 4677 * Bit per priority indicating if Rx flow control policy should be 4678 * updated based on bit pfcrx. 4679 * Access: WO 4680 */ 4681 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8); 4682 4683 /* reg_pfcc_pptx 4684 * Admin Pause policy on Tx. 4685 * 0 - Never generate Pause frames (default). 4686 * 1 - Generate Pause frames according to Rx buffer threshold. 4687 * Access: RW 4688 */ 4689 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1); 4690 4691 /* reg_pfcc_aptx 4692 * Active (operational) Pause policy on Tx. 4693 * 0 - Never generate Pause frames. 4694 * 1 - Generate Pause frames according to Rx buffer threshold. 4695 * Access: RO 4696 */ 4697 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1); 4698 4699 /* reg_pfcc_pfctx 4700 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask: 4701 * 0 - Never generate priority Pause frames on the specified priority 4702 * (default). 4703 * 1 - Generate priority Pause frames according to Rx buffer threshold on 4704 * the specified priority. 4705 * Access: RW 4706 * 4707 * Note: pfctx and pptx must be mutually exclusive. 4708 */ 4709 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8); 4710 4711 /* reg_pfcc_pprx 4712 * Admin Pause policy on Rx. 4713 * 0 - Ignore received Pause frames (default). 4714 * 1 - Respect received Pause frames. 4715 * Access: RW 4716 */ 4717 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1); 4718 4719 /* reg_pfcc_aprx 4720 * Active (operational) Pause policy on Rx. 4721 * 0 - Ignore received Pause frames. 4722 * 1 - Respect received Pause frames. 4723 * Access: RO 4724 */ 4725 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1); 4726 4727 /* reg_pfcc_pfcrx 4728 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask: 4729 * 0 - Ignore incoming priority Pause frames on the specified priority 4730 * (default). 4731 * 1 - Respect incoming priority Pause frames on the specified priority. 4732 * Access: RW 4733 */ 4734 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8); 4735 4736 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF 4737 4738 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en) 4739 { 4740 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 4741 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 4742 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en); 4743 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en); 4744 } 4745 4746 static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port) 4747 { 4748 MLXSW_REG_ZERO(pfcc, payload); 4749 mlxsw_reg_pfcc_local_port_set(payload, local_port); 4750 } 4751 4752 /* PPCNT - Ports Performance Counters Register 4753 * ------------------------------------------- 4754 * The PPCNT register retrieves per port performance counters. 4755 */ 4756 #define MLXSW_REG_PPCNT_ID 0x5008 4757 #define MLXSW_REG_PPCNT_LEN 0x100 4758 #define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08 4759 4760 MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN); 4761 4762 /* reg_ppcnt_swid 4763 * For HCA: must be always 0. 4764 * Switch partition ID to associate port with. 4765 * Switch partitions are numbered from 0 to 7 inclusively. 4766 * Switch partition 254 indicates stacking ports. 4767 * Switch partition 255 indicates all switch partitions. 4768 * Only valid on Set() operation with local_port=255. 4769 * Access: Index 4770 */ 4771 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8); 4772 4773 /* reg_ppcnt_local_port 4774 * Local port number. 4775 * 255 indicates all ports on the device, and is only allowed 4776 * for Set() operation. 4777 * Access: Index 4778 */ 4779 MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8); 4780 4781 /* reg_ppcnt_pnat 4782 * Port number access type: 4783 * 0 - Local port number 4784 * 1 - IB port number 4785 * Access: Index 4786 */ 4787 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2); 4788 4789 enum mlxsw_reg_ppcnt_grp { 4790 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0, 4791 MLXSW_REG_PPCNT_RFC_2863_CNT = 0x1, 4792 MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2, 4793 MLXSW_REG_PPCNT_RFC_3635_CNT = 0x3, 4794 MLXSW_REG_PPCNT_EXT_CNT = 0x5, 4795 MLXSW_REG_PPCNT_DISCARD_CNT = 0x6, 4796 MLXSW_REG_PPCNT_PRIO_CNT = 0x10, 4797 MLXSW_REG_PPCNT_TC_CNT = 0x11, 4798 MLXSW_REG_PPCNT_TC_CONG_TC = 0x13, 4799 }; 4800 4801 /* reg_ppcnt_grp 4802 * Performance counter group. 4803 * Group 63 indicates all groups. Only valid on Set() operation with 4804 * clr bit set. 4805 * 0x0: IEEE 802.3 Counters 4806 * 0x1: RFC 2863 Counters 4807 * 0x2: RFC 2819 Counters 4808 * 0x3: RFC 3635 Counters 4809 * 0x5: Ethernet Extended Counters 4810 * 0x6: Ethernet Discard Counters 4811 * 0x8: Link Level Retransmission Counters 4812 * 0x10: Per Priority Counters 4813 * 0x11: Per Traffic Class Counters 4814 * 0x12: Physical Layer Counters 4815 * 0x13: Per Traffic Class Congestion Counters 4816 * Access: Index 4817 */ 4818 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6); 4819 4820 /* reg_ppcnt_clr 4821 * Clear counters. Setting the clr bit will reset the counter value 4822 * for all counters in the counter group. This bit can be set 4823 * for both Set() and Get() operation. 4824 * Access: OP 4825 */ 4826 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1); 4827 4828 /* reg_ppcnt_prio_tc 4829 * Priority for counter set that support per priority, valid values: 0-7. 4830 * Traffic class for counter set that support per traffic class, 4831 * valid values: 0- cap_max_tclass-1 . 4832 * For HCA: cap_max_tclass is always 8. 4833 * Otherwise must be 0. 4834 * Access: Index 4835 */ 4836 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5); 4837 4838 /* Ethernet IEEE 802.3 Counter Group */ 4839 4840 /* reg_ppcnt_a_frames_transmitted_ok 4841 * Access: RO 4842 */ 4843 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok, 4844 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4845 4846 /* reg_ppcnt_a_frames_received_ok 4847 * Access: RO 4848 */ 4849 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok, 4850 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4851 4852 /* reg_ppcnt_a_frame_check_sequence_errors 4853 * Access: RO 4854 */ 4855 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors, 4856 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 4857 4858 /* reg_ppcnt_a_alignment_errors 4859 * Access: RO 4860 */ 4861 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors, 4862 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 4863 4864 /* reg_ppcnt_a_octets_transmitted_ok 4865 * Access: RO 4866 */ 4867 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok, 4868 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 4869 4870 /* reg_ppcnt_a_octets_received_ok 4871 * Access: RO 4872 */ 4873 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok, 4874 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 4875 4876 /* reg_ppcnt_a_multicast_frames_xmitted_ok 4877 * Access: RO 4878 */ 4879 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok, 4880 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 4881 4882 /* reg_ppcnt_a_broadcast_frames_xmitted_ok 4883 * Access: RO 4884 */ 4885 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok, 4886 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 4887 4888 /* reg_ppcnt_a_multicast_frames_received_ok 4889 * Access: RO 4890 */ 4891 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok, 4892 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 4893 4894 /* reg_ppcnt_a_broadcast_frames_received_ok 4895 * Access: RO 4896 */ 4897 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok, 4898 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 4899 4900 /* reg_ppcnt_a_in_range_length_errors 4901 * Access: RO 4902 */ 4903 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors, 4904 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 4905 4906 /* reg_ppcnt_a_out_of_range_length_field 4907 * Access: RO 4908 */ 4909 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field, 4910 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 4911 4912 /* reg_ppcnt_a_frame_too_long_errors 4913 * Access: RO 4914 */ 4915 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors, 4916 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4917 4918 /* reg_ppcnt_a_symbol_error_during_carrier 4919 * Access: RO 4920 */ 4921 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier, 4922 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 4923 4924 /* reg_ppcnt_a_mac_control_frames_transmitted 4925 * Access: RO 4926 */ 4927 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted, 4928 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4929 4930 /* reg_ppcnt_a_mac_control_frames_received 4931 * Access: RO 4932 */ 4933 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received, 4934 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 4935 4936 /* reg_ppcnt_a_unsupported_opcodes_received 4937 * Access: RO 4938 */ 4939 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received, 4940 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 4941 4942 /* reg_ppcnt_a_pause_mac_ctrl_frames_received 4943 * Access: RO 4944 */ 4945 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received, 4946 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 4947 4948 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted 4949 * Access: RO 4950 */ 4951 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted, 4952 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 4953 4954 /* Ethernet RFC 2863 Counter Group */ 4955 4956 /* reg_ppcnt_if_in_discards 4957 * Access: RO 4958 */ 4959 MLXSW_ITEM64(reg, ppcnt, if_in_discards, 4960 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 4961 4962 /* reg_ppcnt_if_out_discards 4963 * Access: RO 4964 */ 4965 MLXSW_ITEM64(reg, ppcnt, if_out_discards, 4966 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 4967 4968 /* reg_ppcnt_if_out_errors 4969 * Access: RO 4970 */ 4971 MLXSW_ITEM64(reg, ppcnt, if_out_errors, 4972 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 4973 4974 /* Ethernet RFC 2819 Counter Group */ 4975 4976 /* reg_ppcnt_ether_stats_undersize_pkts 4977 * Access: RO 4978 */ 4979 MLXSW_ITEM64(reg, ppcnt, ether_stats_undersize_pkts, 4980 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 4981 4982 /* reg_ppcnt_ether_stats_oversize_pkts 4983 * Access: RO 4984 */ 4985 MLXSW_ITEM64(reg, ppcnt, ether_stats_oversize_pkts, 4986 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 4987 4988 /* reg_ppcnt_ether_stats_fragments 4989 * Access: RO 4990 */ 4991 MLXSW_ITEM64(reg, ppcnt, ether_stats_fragments, 4992 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 4993 4994 /* reg_ppcnt_ether_stats_pkts64octets 4995 * Access: RO 4996 */ 4997 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets, 4998 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 4999 5000 /* reg_ppcnt_ether_stats_pkts65to127octets 5001 * Access: RO 5002 */ 5003 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets, 5004 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5005 5006 /* reg_ppcnt_ether_stats_pkts128to255octets 5007 * Access: RO 5008 */ 5009 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets, 5010 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5011 5012 /* reg_ppcnt_ether_stats_pkts256to511octets 5013 * Access: RO 5014 */ 5015 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets, 5016 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5017 5018 /* reg_ppcnt_ether_stats_pkts512to1023octets 5019 * Access: RO 5020 */ 5021 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets, 5022 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 5023 5024 /* reg_ppcnt_ether_stats_pkts1024to1518octets 5025 * Access: RO 5026 */ 5027 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets, 5028 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 5029 5030 /* reg_ppcnt_ether_stats_pkts1519to2047octets 5031 * Access: RO 5032 */ 5033 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets, 5034 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 5035 5036 /* reg_ppcnt_ether_stats_pkts2048to4095octets 5037 * Access: RO 5038 */ 5039 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets, 5040 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 5041 5042 /* reg_ppcnt_ether_stats_pkts4096to8191octets 5043 * Access: RO 5044 */ 5045 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets, 5046 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64); 5047 5048 /* reg_ppcnt_ether_stats_pkts8192to10239octets 5049 * Access: RO 5050 */ 5051 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets, 5052 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64); 5053 5054 /* Ethernet RFC 3635 Counter Group */ 5055 5056 /* reg_ppcnt_dot3stats_fcs_errors 5057 * Access: RO 5058 */ 5059 MLXSW_ITEM64(reg, ppcnt, dot3stats_fcs_errors, 5060 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5061 5062 /* reg_ppcnt_dot3stats_symbol_errors 5063 * Access: RO 5064 */ 5065 MLXSW_ITEM64(reg, ppcnt, dot3stats_symbol_errors, 5066 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5067 5068 /* reg_ppcnt_dot3control_in_unknown_opcodes 5069 * Access: RO 5070 */ 5071 MLXSW_ITEM64(reg, ppcnt, dot3control_in_unknown_opcodes, 5072 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5073 5074 /* reg_ppcnt_dot3in_pause_frames 5075 * Access: RO 5076 */ 5077 MLXSW_ITEM64(reg, ppcnt, dot3in_pause_frames, 5078 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5079 5080 /* Ethernet Extended Counter Group Counters */ 5081 5082 /* reg_ppcnt_ecn_marked 5083 * Access: RO 5084 */ 5085 MLXSW_ITEM64(reg, ppcnt, ecn_marked, 5086 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5087 5088 /* Ethernet Discard Counter Group Counters */ 5089 5090 /* reg_ppcnt_ingress_general 5091 * Access: RO 5092 */ 5093 MLXSW_ITEM64(reg, ppcnt, ingress_general, 5094 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5095 5096 /* reg_ppcnt_ingress_policy_engine 5097 * Access: RO 5098 */ 5099 MLXSW_ITEM64(reg, ppcnt, ingress_policy_engine, 5100 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5101 5102 /* reg_ppcnt_ingress_vlan_membership 5103 * Access: RO 5104 */ 5105 MLXSW_ITEM64(reg, ppcnt, ingress_vlan_membership, 5106 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 5107 5108 /* reg_ppcnt_ingress_tag_frame_type 5109 * Access: RO 5110 */ 5111 MLXSW_ITEM64(reg, ppcnt, ingress_tag_frame_type, 5112 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 5113 5114 /* reg_ppcnt_egress_vlan_membership 5115 * Access: RO 5116 */ 5117 MLXSW_ITEM64(reg, ppcnt, egress_vlan_membership, 5118 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5119 5120 /* reg_ppcnt_loopback_filter 5121 * Access: RO 5122 */ 5123 MLXSW_ITEM64(reg, ppcnt, loopback_filter, 5124 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5125 5126 /* reg_ppcnt_egress_general 5127 * Access: RO 5128 */ 5129 MLXSW_ITEM64(reg, ppcnt, egress_general, 5130 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 5131 5132 /* reg_ppcnt_egress_hoq 5133 * Access: RO 5134 */ 5135 MLXSW_ITEM64(reg, ppcnt, egress_hoq, 5136 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5137 5138 /* reg_ppcnt_egress_policy_engine 5139 * Access: RO 5140 */ 5141 MLXSW_ITEM64(reg, ppcnt, egress_policy_engine, 5142 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5143 5144 /* reg_ppcnt_ingress_tx_link_down 5145 * Access: RO 5146 */ 5147 MLXSW_ITEM64(reg, ppcnt, ingress_tx_link_down, 5148 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5149 5150 /* reg_ppcnt_egress_stp_filter 5151 * Access: RO 5152 */ 5153 MLXSW_ITEM64(reg, ppcnt, egress_stp_filter, 5154 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5155 5156 /* reg_ppcnt_egress_sll 5157 * Access: RO 5158 */ 5159 MLXSW_ITEM64(reg, ppcnt, egress_sll, 5160 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5161 5162 /* Ethernet Per Priority Group Counters */ 5163 5164 /* reg_ppcnt_rx_octets 5165 * Access: RO 5166 */ 5167 MLXSW_ITEM64(reg, ppcnt, rx_octets, 5168 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5169 5170 /* reg_ppcnt_rx_frames 5171 * Access: RO 5172 */ 5173 MLXSW_ITEM64(reg, ppcnt, rx_frames, 5174 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5175 5176 /* reg_ppcnt_tx_octets 5177 * Access: RO 5178 */ 5179 MLXSW_ITEM64(reg, ppcnt, tx_octets, 5180 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5181 5182 /* reg_ppcnt_tx_frames 5183 * Access: RO 5184 */ 5185 MLXSW_ITEM64(reg, ppcnt, tx_frames, 5186 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 5187 5188 /* reg_ppcnt_rx_pause 5189 * Access: RO 5190 */ 5191 MLXSW_ITEM64(reg, ppcnt, rx_pause, 5192 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5193 5194 /* reg_ppcnt_rx_pause_duration 5195 * Access: RO 5196 */ 5197 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration, 5198 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5199 5200 /* reg_ppcnt_tx_pause 5201 * Access: RO 5202 */ 5203 MLXSW_ITEM64(reg, ppcnt, tx_pause, 5204 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5205 5206 /* reg_ppcnt_tx_pause_duration 5207 * Access: RO 5208 */ 5209 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration, 5210 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5211 5212 /* reg_ppcnt_rx_pause_transition 5213 * Access: RO 5214 */ 5215 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition, 5216 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5217 5218 /* Ethernet Per Traffic Group Counters */ 5219 5220 /* reg_ppcnt_tc_transmit_queue 5221 * Contains the transmit queue depth in cells of traffic class 5222 * selected by prio_tc and the port selected by local_port. 5223 * The field cannot be cleared. 5224 * Access: RO 5225 */ 5226 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue, 5227 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5228 5229 /* reg_ppcnt_tc_no_buffer_discard_uc 5230 * The number of unicast packets dropped due to lack of shared 5231 * buffer resources. 5232 * Access: RO 5233 */ 5234 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc, 5235 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5236 5237 /* Ethernet Per Traffic Class Congestion Group Counters */ 5238 5239 /* reg_ppcnt_wred_discard 5240 * Access: RO 5241 */ 5242 MLXSW_ITEM64(reg, ppcnt, wred_discard, 5243 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5244 5245 static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port, 5246 enum mlxsw_reg_ppcnt_grp grp, 5247 u8 prio_tc) 5248 { 5249 MLXSW_REG_ZERO(ppcnt, payload); 5250 mlxsw_reg_ppcnt_swid_set(payload, 0); 5251 mlxsw_reg_ppcnt_local_port_set(payload, local_port); 5252 mlxsw_reg_ppcnt_pnat_set(payload, 0); 5253 mlxsw_reg_ppcnt_grp_set(payload, grp); 5254 mlxsw_reg_ppcnt_clr_set(payload, 0); 5255 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc); 5256 } 5257 5258 /* PLIB - Port Local to InfiniBand Port 5259 * ------------------------------------ 5260 * The PLIB register performs mapping from Local Port into InfiniBand Port. 5261 */ 5262 #define MLXSW_REG_PLIB_ID 0x500A 5263 #define MLXSW_REG_PLIB_LEN 0x10 5264 5265 MLXSW_REG_DEFINE(plib, MLXSW_REG_PLIB_ID, MLXSW_REG_PLIB_LEN); 5266 5267 /* reg_plib_local_port 5268 * Local port number. 5269 * Access: Index 5270 */ 5271 MLXSW_ITEM32(reg, plib, local_port, 0x00, 16, 8); 5272 5273 /* reg_plib_ib_port 5274 * InfiniBand port remapping for local_port. 5275 * Access: RW 5276 */ 5277 MLXSW_ITEM32(reg, plib, ib_port, 0x00, 0, 8); 5278 5279 /* PPTB - Port Prio To Buffer Register 5280 * ----------------------------------- 5281 * Configures the switch priority to buffer table. 5282 */ 5283 #define MLXSW_REG_PPTB_ID 0x500B 5284 #define MLXSW_REG_PPTB_LEN 0x10 5285 5286 MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN); 5287 5288 enum { 5289 MLXSW_REG_PPTB_MM_UM, 5290 MLXSW_REG_PPTB_MM_UNICAST, 5291 MLXSW_REG_PPTB_MM_MULTICAST, 5292 }; 5293 5294 /* reg_pptb_mm 5295 * Mapping mode. 5296 * 0 - Map both unicast and multicast packets to the same buffer. 5297 * 1 - Map only unicast packets. 5298 * 2 - Map only multicast packets. 5299 * Access: Index 5300 * 5301 * Note: SwitchX-2 only supports the first option. 5302 */ 5303 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2); 5304 5305 /* reg_pptb_local_port 5306 * Local port number. 5307 * Access: Index 5308 */ 5309 MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8); 5310 5311 /* reg_pptb_um 5312 * Enables the update of the untagged_buf field. 5313 * Access: RW 5314 */ 5315 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1); 5316 5317 /* reg_pptb_pm 5318 * Enables the update of the prio_to_buff field. 5319 * Bit <i> is a flag for updating the mapping for switch priority <i>. 5320 * Access: RW 5321 */ 5322 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8); 5323 5324 /* reg_pptb_prio_to_buff 5325 * Mapping of switch priority <i> to one of the allocated receive port 5326 * buffers. 5327 * Access: RW 5328 */ 5329 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4); 5330 5331 /* reg_pptb_pm_msb 5332 * Enables the update of the prio_to_buff field. 5333 * Bit <i> is a flag for updating the mapping for switch priority <i+8>. 5334 * Access: RW 5335 */ 5336 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8); 5337 5338 /* reg_pptb_untagged_buff 5339 * Mapping of untagged frames to one of the allocated receive port buffers. 5340 * Access: RW 5341 * 5342 * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for 5343 * Spectrum, as it maps untagged packets based on the default switch priority. 5344 */ 5345 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4); 5346 5347 /* reg_pptb_prio_to_buff_msb 5348 * Mapping of switch priority <i+8> to one of the allocated receive port 5349 * buffers. 5350 * Access: RW 5351 */ 5352 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4); 5353 5354 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF 5355 5356 static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port) 5357 { 5358 MLXSW_REG_ZERO(pptb, payload); 5359 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM); 5360 mlxsw_reg_pptb_local_port_set(payload, local_port); 5361 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 5362 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 5363 } 5364 5365 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio, 5366 u8 buff) 5367 { 5368 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff); 5369 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff); 5370 } 5371 5372 /* PBMC - Port Buffer Management Control Register 5373 * ---------------------------------------------- 5374 * The PBMC register configures and retrieves the port packet buffer 5375 * allocation for different Prios, and the Pause threshold management. 5376 */ 5377 #define MLXSW_REG_PBMC_ID 0x500C 5378 #define MLXSW_REG_PBMC_LEN 0x6C 5379 5380 MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN); 5381 5382 /* reg_pbmc_local_port 5383 * Local port number. 5384 * Access: Index 5385 */ 5386 MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8); 5387 5388 /* reg_pbmc_xoff_timer_value 5389 * When device generates a pause frame, it uses this value as the pause 5390 * timer (time for the peer port to pause in quota-512 bit time). 5391 * Access: RW 5392 */ 5393 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16); 5394 5395 /* reg_pbmc_xoff_refresh 5396 * The time before a new pause frame should be sent to refresh the pause RW 5397 * state. Using the same units as xoff_timer_value above (in quota-512 bit 5398 * time). 5399 * Access: RW 5400 */ 5401 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16); 5402 5403 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11 5404 5405 /* reg_pbmc_buf_lossy 5406 * The field indicates if the buffer is lossy. 5407 * 0 - Lossless 5408 * 1 - Lossy 5409 * Access: RW 5410 */ 5411 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false); 5412 5413 /* reg_pbmc_buf_epsb 5414 * Eligible for Port Shared buffer. 5415 * If epsb is set, packets assigned to buffer are allowed to insert the port 5416 * shared buffer. 5417 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved. 5418 * Access: RW 5419 */ 5420 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false); 5421 5422 /* reg_pbmc_buf_size 5423 * The part of the packet buffer array is allocated for the specific buffer. 5424 * Units are represented in cells. 5425 * Access: RW 5426 */ 5427 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false); 5428 5429 /* reg_pbmc_buf_xoff_threshold 5430 * Once the amount of data in the buffer goes above this value, device 5431 * starts sending PFC frames for all priorities associated with the 5432 * buffer. Units are represented in cells. Reserved in case of lossy 5433 * buffer. 5434 * Access: RW 5435 * 5436 * Note: In Spectrum, reserved for buffer[9]. 5437 */ 5438 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16, 5439 0x08, 0x04, false); 5440 5441 /* reg_pbmc_buf_xon_threshold 5442 * When the amount of data in the buffer goes below this value, device 5443 * stops sending PFC frames for the priorities associated with the 5444 * buffer. Units are represented in cells. Reserved in case of lossy 5445 * buffer. 5446 * Access: RW 5447 * 5448 * Note: In Spectrum, reserved for buffer[9]. 5449 */ 5450 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16, 5451 0x08, 0x04, false); 5452 5453 static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port, 5454 u16 xoff_timer_value, u16 xoff_refresh) 5455 { 5456 MLXSW_REG_ZERO(pbmc, payload); 5457 mlxsw_reg_pbmc_local_port_set(payload, local_port); 5458 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value); 5459 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh); 5460 } 5461 5462 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload, 5463 int buf_index, 5464 u16 size) 5465 { 5466 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1); 5467 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5468 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5469 } 5470 5471 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload, 5472 int buf_index, u16 size, 5473 u16 threshold) 5474 { 5475 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0); 5476 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5477 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5478 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold); 5479 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold); 5480 } 5481 5482 /* PSPA - Port Switch Partition Allocation 5483 * --------------------------------------- 5484 * Controls the association of a port with a switch partition and enables 5485 * configuring ports as stacking ports. 5486 */ 5487 #define MLXSW_REG_PSPA_ID 0x500D 5488 #define MLXSW_REG_PSPA_LEN 0x8 5489 5490 MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN); 5491 5492 /* reg_pspa_swid 5493 * Switch partition ID. 5494 * Access: RW 5495 */ 5496 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8); 5497 5498 /* reg_pspa_local_port 5499 * Local port number. 5500 * Access: Index 5501 */ 5502 MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8); 5503 5504 /* reg_pspa_sub_port 5505 * Virtual port within the local port. Set to 0 when virtual ports are 5506 * disabled on the local port. 5507 * Access: Index 5508 */ 5509 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8); 5510 5511 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port) 5512 { 5513 MLXSW_REG_ZERO(pspa, payload); 5514 mlxsw_reg_pspa_swid_set(payload, swid); 5515 mlxsw_reg_pspa_local_port_set(payload, local_port); 5516 mlxsw_reg_pspa_sub_port_set(payload, 0); 5517 } 5518 5519 /* PMAOS - Ports Module Administrative and Operational Status 5520 * ---------------------------------------------------------- 5521 * This register configures and retrieves the per module status. 5522 */ 5523 #define MLXSW_REG_PMAOS_ID 0x5012 5524 #define MLXSW_REG_PMAOS_LEN 0x10 5525 5526 MLXSW_REG_DEFINE(pmaos, MLXSW_REG_PMAOS_ID, MLXSW_REG_PMAOS_LEN); 5527 5528 /* reg_slot_index 5529 * Slot index. 5530 * Access: Index 5531 */ 5532 MLXSW_ITEM32(reg, pmaos, slot_index, 0x00, 24, 4); 5533 5534 /* reg_pmaos_module 5535 * Module number. 5536 * Access: Index 5537 */ 5538 MLXSW_ITEM32(reg, pmaos, module, 0x00, 16, 8); 5539 5540 /* reg_pmaos_ase 5541 * Admin state update enable. 5542 * If this bit is set, admin state will be updated based on admin_state field. 5543 * Only relevant on Set() operations. 5544 * Access: WO 5545 */ 5546 MLXSW_ITEM32(reg, pmaos, ase, 0x04, 31, 1); 5547 5548 /* reg_pmaos_ee 5549 * Event update enable. 5550 * If this bit is set, event generation will be updated based on the e field. 5551 * Only relevant on Set operations. 5552 * Access: WO 5553 */ 5554 MLXSW_ITEM32(reg, pmaos, ee, 0x04, 30, 1); 5555 5556 enum mlxsw_reg_pmaos_e { 5557 MLXSW_REG_PMAOS_E_DO_NOT_GENERATE_EVENT, 5558 MLXSW_REG_PMAOS_E_GENERATE_EVENT, 5559 MLXSW_REG_PMAOS_E_GENERATE_SINGLE_EVENT, 5560 }; 5561 5562 /* reg_pmaos_e 5563 * Event Generation on operational state change. 5564 * Access: RW 5565 */ 5566 MLXSW_ITEM32(reg, pmaos, e, 0x04, 0, 2); 5567 5568 static inline void mlxsw_reg_pmaos_pack(char *payload, u8 module, 5569 enum mlxsw_reg_pmaos_e e) 5570 { 5571 MLXSW_REG_ZERO(pmaos, payload); 5572 mlxsw_reg_pmaos_module_set(payload, module); 5573 mlxsw_reg_pmaos_e_set(payload, e); 5574 mlxsw_reg_pmaos_ee_set(payload, true); 5575 } 5576 5577 /* PPLR - Port Physical Loopback Register 5578 * -------------------------------------- 5579 * This register allows configuration of the port's loopback mode. 5580 */ 5581 #define MLXSW_REG_PPLR_ID 0x5018 5582 #define MLXSW_REG_PPLR_LEN 0x8 5583 5584 MLXSW_REG_DEFINE(pplr, MLXSW_REG_PPLR_ID, MLXSW_REG_PPLR_LEN); 5585 5586 /* reg_pplr_local_port 5587 * Local port number. 5588 * Access: Index 5589 */ 5590 MLXSW_ITEM32(reg, pplr, local_port, 0x00, 16, 8); 5591 5592 /* Phy local loopback. When set the port's egress traffic is looped back 5593 * to the receiver and the port transmitter is disabled. 5594 */ 5595 #define MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL BIT(1) 5596 5597 /* reg_pplr_lb_en 5598 * Loopback enable. 5599 * Access: RW 5600 */ 5601 MLXSW_ITEM32(reg, pplr, lb_en, 0x04, 0, 8); 5602 5603 static inline void mlxsw_reg_pplr_pack(char *payload, u8 local_port, 5604 bool phy_local) 5605 { 5606 MLXSW_REG_ZERO(pplr, payload); 5607 mlxsw_reg_pplr_local_port_set(payload, local_port); 5608 mlxsw_reg_pplr_lb_en_set(payload, 5609 phy_local ? 5610 MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL : 0); 5611 } 5612 5613 /* PMPE - Port Module Plug/Unplug Event Register 5614 * --------------------------------------------- 5615 * This register reports any operational status change of a module. 5616 * A change in the module’s state will generate an event only if the change 5617 * happens after arming the event mechanism. Any changes to the module state 5618 * while the event mechanism is not armed will not be reported. Software can 5619 * query the PMPE register for module status. 5620 */ 5621 #define MLXSW_REG_PMPE_ID 0x5024 5622 #define MLXSW_REG_PMPE_LEN 0x10 5623 5624 MLXSW_REG_DEFINE(pmpe, MLXSW_REG_PMPE_ID, MLXSW_REG_PMPE_LEN); 5625 5626 /* reg_pmpe_slot_index 5627 * Slot index. 5628 * Access: Index 5629 */ 5630 MLXSW_ITEM32(reg, pmpe, slot_index, 0x00, 24, 4); 5631 5632 /* reg_pmpe_module 5633 * Module number. 5634 * Access: Index 5635 */ 5636 MLXSW_ITEM32(reg, pmpe, module, 0x00, 16, 8); 5637 5638 enum mlxsw_reg_pmpe_module_status { 5639 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_ENABLED = 1, 5640 MLXSW_REG_PMPE_MODULE_STATUS_UNPLUGGED, 5641 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_ERROR, 5642 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_DISABLED, 5643 }; 5644 5645 /* reg_pmpe_module_status 5646 * Module status. 5647 * Access: RO 5648 */ 5649 MLXSW_ITEM32(reg, pmpe, module_status, 0x00, 0, 4); 5650 5651 /* reg_pmpe_error_type 5652 * Module error details. 5653 * Access: RO 5654 */ 5655 MLXSW_ITEM32(reg, pmpe, error_type, 0x04, 8, 4); 5656 5657 /* PDDR - Port Diagnostics Database Register 5658 * ----------------------------------------- 5659 * The PDDR enables to read the Phy debug database 5660 */ 5661 #define MLXSW_REG_PDDR_ID 0x5031 5662 #define MLXSW_REG_PDDR_LEN 0x100 5663 5664 MLXSW_REG_DEFINE(pddr, MLXSW_REG_PDDR_ID, MLXSW_REG_PDDR_LEN); 5665 5666 /* reg_pddr_local_port 5667 * Local port number. 5668 * Access: Index 5669 */ 5670 MLXSW_ITEM32(reg, pddr, local_port, 0x00, 16, 8); 5671 5672 enum mlxsw_reg_pddr_page_select { 5673 MLXSW_REG_PDDR_PAGE_SELECT_TROUBLESHOOTING_INFO = 1, 5674 }; 5675 5676 /* reg_pddr_page_select 5677 * Page select index. 5678 * Access: Index 5679 */ 5680 MLXSW_ITEM32(reg, pddr, page_select, 0x04, 0, 8); 5681 5682 enum mlxsw_reg_pddr_trblsh_group_opcode { 5683 /* Monitor opcodes */ 5684 MLXSW_REG_PDDR_TRBLSH_GROUP_OPCODE_MONITOR, 5685 }; 5686 5687 /* reg_pddr_group_opcode 5688 * Group selector. 5689 * Access: Index 5690 */ 5691 MLXSW_ITEM32(reg, pddr, trblsh_group_opcode, 0x08, 0, 16); 5692 5693 /* reg_pddr_status_opcode 5694 * Group selector. 5695 * Access: RO 5696 */ 5697 MLXSW_ITEM32(reg, pddr, trblsh_status_opcode, 0x0C, 0, 16); 5698 5699 static inline void mlxsw_reg_pddr_pack(char *payload, u8 local_port, 5700 u8 page_select) 5701 { 5702 MLXSW_REG_ZERO(pddr, payload); 5703 mlxsw_reg_pddr_local_port_set(payload, local_port); 5704 mlxsw_reg_pddr_page_select_set(payload, page_select); 5705 } 5706 5707 /* PMTM - Port Module Type Mapping Register 5708 * ---------------------------------------- 5709 * The PMTM allows query or configuration of module types. 5710 */ 5711 #define MLXSW_REG_PMTM_ID 0x5067 5712 #define MLXSW_REG_PMTM_LEN 0x10 5713 5714 MLXSW_REG_DEFINE(pmtm, MLXSW_REG_PMTM_ID, MLXSW_REG_PMTM_LEN); 5715 5716 /* reg_pmtm_module 5717 * Module number. 5718 * Access: Index 5719 */ 5720 MLXSW_ITEM32(reg, pmtm, module, 0x00, 16, 8); 5721 5722 enum mlxsw_reg_pmtm_module_type { 5723 /* Backplane with 4 lanes */ 5724 MLXSW_REG_PMTM_MODULE_TYPE_BP_4X, 5725 /* QSFP */ 5726 MLXSW_REG_PMTM_MODULE_TYPE_QSFP, 5727 /* SFP */ 5728 MLXSW_REG_PMTM_MODULE_TYPE_SFP, 5729 /* Backplane with single lane */ 5730 MLXSW_REG_PMTM_MODULE_TYPE_BP_1X = 4, 5731 /* Backplane with two lane */ 5732 MLXSW_REG_PMTM_MODULE_TYPE_BP_2X = 8, 5733 /* Chip2Chip4x */ 5734 MLXSW_REG_PMTM_MODULE_TYPE_C2C4X = 10, 5735 /* Chip2Chip2x */ 5736 MLXSW_REG_PMTM_MODULE_TYPE_C2C2X, 5737 /* Chip2Chip1x */ 5738 MLXSW_REG_PMTM_MODULE_TYPE_C2C1X, 5739 /* QSFP-DD */ 5740 MLXSW_REG_PMTM_MODULE_TYPE_QSFP_DD = 14, 5741 /* OSFP */ 5742 MLXSW_REG_PMTM_MODULE_TYPE_OSFP, 5743 /* SFP-DD */ 5744 MLXSW_REG_PMTM_MODULE_TYPE_SFP_DD, 5745 /* DSFP */ 5746 MLXSW_REG_PMTM_MODULE_TYPE_DSFP, 5747 /* Chip2Chip8x */ 5748 MLXSW_REG_PMTM_MODULE_TYPE_C2C8X, 5749 }; 5750 5751 /* reg_pmtm_module_type 5752 * Module type. 5753 * Access: RW 5754 */ 5755 MLXSW_ITEM32(reg, pmtm, module_type, 0x04, 0, 4); 5756 5757 static inline void mlxsw_reg_pmtm_pack(char *payload, u8 module) 5758 { 5759 MLXSW_REG_ZERO(pmtm, payload); 5760 mlxsw_reg_pmtm_module_set(payload, module); 5761 } 5762 5763 static inline void 5764 mlxsw_reg_pmtm_unpack(char *payload, 5765 enum mlxsw_reg_pmtm_module_type *module_type) 5766 { 5767 *module_type = mlxsw_reg_pmtm_module_type_get(payload); 5768 } 5769 5770 /* HTGT - Host Trap Group Table 5771 * ---------------------------- 5772 * Configures the properties for forwarding to CPU. 5773 */ 5774 #define MLXSW_REG_HTGT_ID 0x7002 5775 #define MLXSW_REG_HTGT_LEN 0x20 5776 5777 MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN); 5778 5779 /* reg_htgt_swid 5780 * Switch partition ID. 5781 * Access: Index 5782 */ 5783 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8); 5784 5785 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */ 5786 5787 /* reg_htgt_type 5788 * CPU path type. 5789 * Access: RW 5790 */ 5791 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4); 5792 5793 enum mlxsw_reg_htgt_trap_group { 5794 MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 5795 MLXSW_REG_HTGT_TRAP_GROUP_MFDE, 5796 MLXSW_REG_HTGT_TRAP_GROUP_MTWE, 5797 MLXSW_REG_HTGT_TRAP_GROUP_PMPE, 5798 MLXSW_REG_HTGT_TRAP_GROUP_SP_STP, 5799 MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP, 5800 MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP, 5801 MLXSW_REG_HTGT_TRAP_GROUP_SP_MC_SNOOPING, 5802 MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP, 5803 MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF, 5804 MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM, 5805 MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST, 5806 MLXSW_REG_HTGT_TRAP_GROUP_SP_NEIGH_DISCOVERY, 5807 MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP, 5808 MLXSW_REG_HTGT_TRAP_GROUP_SP_EXTERNAL_ROUTE, 5809 MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME, 5810 MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP, 5811 MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT, 5812 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6, 5813 MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR, 5814 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0, 5815 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1, 5816 MLXSW_REG_HTGT_TRAP_GROUP_SP_VRRP, 5817 MLXSW_REG_HTGT_TRAP_GROUP_SP_PKT_SAMPLE, 5818 MLXSW_REG_HTGT_TRAP_GROUP_SP_FLOW_LOGGING, 5819 MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS, 5820 MLXSW_REG_HTGT_TRAP_GROUP_SP_BFD, 5821 MLXSW_REG_HTGT_TRAP_GROUP_SP_DUMMY, 5822 MLXSW_REG_HTGT_TRAP_GROUP_SP_L2_DISCARDS, 5823 MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_DISCARDS, 5824 MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_EXCEPTIONS, 5825 MLXSW_REG_HTGT_TRAP_GROUP_SP_TUNNEL_DISCARDS, 5826 MLXSW_REG_HTGT_TRAP_GROUP_SP_ACL_DISCARDS, 5827 MLXSW_REG_HTGT_TRAP_GROUP_SP_BUFFER_DISCARDS, 5828 5829 __MLXSW_REG_HTGT_TRAP_GROUP_MAX, 5830 MLXSW_REG_HTGT_TRAP_GROUP_MAX = __MLXSW_REG_HTGT_TRAP_GROUP_MAX - 1 5831 }; 5832 5833 /* reg_htgt_trap_group 5834 * Trap group number. User defined number specifying which trap groups 5835 * should be forwarded to the CPU. The mapping between trap IDs and trap 5836 * groups is configured using HPKT register. 5837 * Access: Index 5838 */ 5839 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8); 5840 5841 enum { 5842 MLXSW_REG_HTGT_POLICER_DISABLE, 5843 MLXSW_REG_HTGT_POLICER_ENABLE, 5844 }; 5845 5846 /* reg_htgt_pide 5847 * Enable policer ID specified using 'pid' field. 5848 * Access: RW 5849 */ 5850 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1); 5851 5852 #define MLXSW_REG_HTGT_INVALID_POLICER 0xff 5853 5854 /* reg_htgt_pid 5855 * Policer ID for the trap group. 5856 * Access: RW 5857 */ 5858 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8); 5859 5860 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0 5861 5862 /* reg_htgt_mirror_action 5863 * Mirror action to use. 5864 * 0 - Trap to CPU. 5865 * 1 - Trap to CPU and mirror to a mirroring agent. 5866 * 2 - Mirror to a mirroring agent and do not trap to CPU. 5867 * Access: RW 5868 * 5869 * Note: Mirroring to a mirroring agent is only supported in Spectrum. 5870 */ 5871 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2); 5872 5873 /* reg_htgt_mirroring_agent 5874 * Mirroring agent. 5875 * Access: RW 5876 */ 5877 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3); 5878 5879 #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0 5880 5881 /* reg_htgt_priority 5882 * Trap group priority. 5883 * In case a packet matches multiple classification rules, the packet will 5884 * only be trapped once, based on the trap ID associated with the group (via 5885 * register HPKT) with the highest priority. 5886 * Supported values are 0-7, with 7 represnting the highest priority. 5887 * Access: RW 5888 * 5889 * Note: In SwitchX-2 this field is ignored and the priority value is replaced 5890 * by the 'trap_group' field. 5891 */ 5892 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4); 5893 5894 #define MLXSW_REG_HTGT_DEFAULT_TC 7 5895 5896 /* reg_htgt_local_path_cpu_tclass 5897 * CPU ingress traffic class for the trap group. 5898 * Access: RW 5899 */ 5900 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6); 5901 5902 enum mlxsw_reg_htgt_local_path_rdq { 5903 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13, 5904 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14, 5905 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15, 5906 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15, 5907 }; 5908 /* reg_htgt_local_path_rdq 5909 * Receive descriptor queue (RDQ) to use for the trap group. 5910 * Access: RW 5911 */ 5912 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6); 5913 5914 static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id, 5915 u8 priority, u8 tc) 5916 { 5917 MLXSW_REG_ZERO(htgt, payload); 5918 5919 if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) { 5920 mlxsw_reg_htgt_pide_set(payload, 5921 MLXSW_REG_HTGT_POLICER_DISABLE); 5922 } else { 5923 mlxsw_reg_htgt_pide_set(payload, 5924 MLXSW_REG_HTGT_POLICER_ENABLE); 5925 mlxsw_reg_htgt_pid_set(payload, policer_id); 5926 } 5927 5928 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL); 5929 mlxsw_reg_htgt_trap_group_set(payload, group); 5930 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU); 5931 mlxsw_reg_htgt_mirroring_agent_set(payload, 0); 5932 mlxsw_reg_htgt_priority_set(payload, priority); 5933 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc); 5934 mlxsw_reg_htgt_local_path_rdq_set(payload, group); 5935 } 5936 5937 /* HPKT - Host Packet Trap 5938 * ----------------------- 5939 * Configures trap IDs inside trap groups. 5940 */ 5941 #define MLXSW_REG_HPKT_ID 0x7003 5942 #define MLXSW_REG_HPKT_LEN 0x10 5943 5944 MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN); 5945 5946 enum { 5947 MLXSW_REG_HPKT_ACK_NOT_REQUIRED, 5948 MLXSW_REG_HPKT_ACK_REQUIRED, 5949 }; 5950 5951 /* reg_hpkt_ack 5952 * Require acknowledgements from the host for events. 5953 * If set, then the device will wait for the event it sent to be acknowledged 5954 * by the host. This option is only relevant for event trap IDs. 5955 * Access: RW 5956 * 5957 * Note: Currently not supported by firmware. 5958 */ 5959 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1); 5960 5961 enum mlxsw_reg_hpkt_action { 5962 MLXSW_REG_HPKT_ACTION_FORWARD, 5963 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU, 5964 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU, 5965 MLXSW_REG_HPKT_ACTION_DISCARD, 5966 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD, 5967 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD, 5968 MLXSW_REG_HPKT_ACTION_TRAP_EXCEPTION_TO_CPU, 5969 MLXSW_REG_HPKT_ACTION_SET_FW_DEFAULT = 15, 5970 }; 5971 5972 /* reg_hpkt_action 5973 * Action to perform on packet when trapped. 5974 * 0 - No action. Forward to CPU based on switching rules. 5975 * 1 - Trap to CPU (CPU receives sole copy). 5976 * 2 - Mirror to CPU (CPU receives a replica of the packet). 5977 * 3 - Discard. 5978 * 4 - Soft discard (allow other traps to act on the packet). 5979 * 5 - Trap and soft discard (allow other traps to overwrite this trap). 5980 * 6 - Trap to CPU (CPU receives sole copy) and count it as error. 5981 * 15 - Restore the firmware's default action. 5982 * Access: RW 5983 * 5984 * Note: Must be set to 0 (forward) for event trap IDs, as they are already 5985 * addressed to the CPU. 5986 */ 5987 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3); 5988 5989 /* reg_hpkt_trap_group 5990 * Trap group to associate the trap with. 5991 * Access: RW 5992 */ 5993 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6); 5994 5995 /* reg_hpkt_trap_id 5996 * Trap ID. 5997 * Access: Index 5998 * 5999 * Note: A trap ID can only be associated with a single trap group. The device 6000 * will associate the trap ID with the last trap group configured. 6001 */ 6002 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 10); 6003 6004 enum { 6005 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT, 6006 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER, 6007 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER, 6008 }; 6009 6010 /* reg_hpkt_ctrl 6011 * Configure dedicated buffer resources for control packets. 6012 * Ignored by SwitchX-2. 6013 * 0 - Keep factory defaults. 6014 * 1 - Do not use control buffer for this trap ID. 6015 * 2 - Use control buffer for this trap ID. 6016 * Access: RW 6017 */ 6018 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2); 6019 6020 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id, 6021 enum mlxsw_reg_htgt_trap_group trap_group, 6022 bool is_ctrl) 6023 { 6024 MLXSW_REG_ZERO(hpkt, payload); 6025 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED); 6026 mlxsw_reg_hpkt_action_set(payload, action); 6027 mlxsw_reg_hpkt_trap_group_set(payload, trap_group); 6028 mlxsw_reg_hpkt_trap_id_set(payload, trap_id); 6029 mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ? 6030 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER : 6031 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER); 6032 } 6033 6034 /* RGCR - Router General Configuration Register 6035 * -------------------------------------------- 6036 * The register is used for setting up the router configuration. 6037 */ 6038 #define MLXSW_REG_RGCR_ID 0x8001 6039 #define MLXSW_REG_RGCR_LEN 0x28 6040 6041 MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN); 6042 6043 /* reg_rgcr_ipv4_en 6044 * IPv4 router enable. 6045 * Access: RW 6046 */ 6047 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1); 6048 6049 /* reg_rgcr_ipv6_en 6050 * IPv6 router enable. 6051 * Access: RW 6052 */ 6053 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1); 6054 6055 /* reg_rgcr_max_router_interfaces 6056 * Defines the maximum number of active router interfaces for all virtual 6057 * routers. 6058 * Access: RW 6059 */ 6060 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16); 6061 6062 /* reg_rgcr_usp 6063 * Update switch priority and packet color. 6064 * 0 - Preserve the value of Switch Priority and packet color. 6065 * 1 - Recalculate the value of Switch Priority and packet color. 6066 * Access: RW 6067 * 6068 * Note: Not supported by SwitchX and SwitchX-2. 6069 */ 6070 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1); 6071 6072 /* reg_rgcr_pcp_rw 6073 * Indicates how to handle the pcp_rewrite_en value: 6074 * 0 - Preserve the value of pcp_rewrite_en. 6075 * 2 - Disable PCP rewrite. 6076 * 3 - Enable PCP rewrite. 6077 * Access: RW 6078 * 6079 * Note: Not supported by SwitchX and SwitchX-2. 6080 */ 6081 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2); 6082 6083 /* reg_rgcr_activity_dis 6084 * Activity disable: 6085 * 0 - Activity will be set when an entry is hit (default). 6086 * 1 - Activity will not be set when an entry is hit. 6087 * 6088 * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry 6089 * (RALUE). 6090 * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host 6091 * Entry (RAUHT). 6092 * Bits 2:7 are reserved. 6093 * Access: RW 6094 * 6095 * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB. 6096 */ 6097 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8); 6098 6099 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en, 6100 bool ipv6_en) 6101 { 6102 MLXSW_REG_ZERO(rgcr, payload); 6103 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en); 6104 mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en); 6105 } 6106 6107 /* RITR - Router Interface Table Register 6108 * -------------------------------------- 6109 * The register is used to configure the router interface table. 6110 */ 6111 #define MLXSW_REG_RITR_ID 0x8002 6112 #define MLXSW_REG_RITR_LEN 0x40 6113 6114 MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN); 6115 6116 /* reg_ritr_enable 6117 * Enables routing on the router interface. 6118 * Access: RW 6119 */ 6120 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1); 6121 6122 /* reg_ritr_ipv4 6123 * IPv4 routing enable. Enables routing of IPv4 traffic on the router 6124 * interface. 6125 * Access: RW 6126 */ 6127 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1); 6128 6129 /* reg_ritr_ipv6 6130 * IPv6 routing enable. Enables routing of IPv6 traffic on the router 6131 * interface. 6132 * Access: RW 6133 */ 6134 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1); 6135 6136 /* reg_ritr_ipv4_mc 6137 * IPv4 multicast routing enable. 6138 * Access: RW 6139 */ 6140 MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1); 6141 6142 /* reg_ritr_ipv6_mc 6143 * IPv6 multicast routing enable. 6144 * Access: RW 6145 */ 6146 MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1); 6147 6148 enum mlxsw_reg_ritr_if_type { 6149 /* VLAN interface. */ 6150 MLXSW_REG_RITR_VLAN_IF, 6151 /* FID interface. */ 6152 MLXSW_REG_RITR_FID_IF, 6153 /* Sub-port interface. */ 6154 MLXSW_REG_RITR_SP_IF, 6155 /* Loopback Interface. */ 6156 MLXSW_REG_RITR_LOOPBACK_IF, 6157 }; 6158 6159 /* reg_ritr_type 6160 * Router interface type as per enum mlxsw_reg_ritr_if_type. 6161 * Access: RW 6162 */ 6163 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3); 6164 6165 enum { 6166 MLXSW_REG_RITR_RIF_CREATE, 6167 MLXSW_REG_RITR_RIF_DEL, 6168 }; 6169 6170 /* reg_ritr_op 6171 * Opcode: 6172 * 0 - Create or edit RIF. 6173 * 1 - Delete RIF. 6174 * Reserved for SwitchX-2. For Spectrum, editing of interface properties 6175 * is not supported. An interface must be deleted and re-created in order 6176 * to update properties. 6177 * Access: WO 6178 */ 6179 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2); 6180 6181 /* reg_ritr_rif 6182 * Router interface index. A pointer to the Router Interface Table. 6183 * Access: Index 6184 */ 6185 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16); 6186 6187 /* reg_ritr_ipv4_fe 6188 * IPv4 Forwarding Enable. 6189 * Enables routing of IPv4 traffic on the router interface. When disabled, 6190 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 6191 * Not supported in SwitchX-2. 6192 * Access: RW 6193 */ 6194 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1); 6195 6196 /* reg_ritr_ipv6_fe 6197 * IPv6 Forwarding Enable. 6198 * Enables routing of IPv6 traffic on the router interface. When disabled, 6199 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 6200 * Not supported in SwitchX-2. 6201 * Access: RW 6202 */ 6203 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1); 6204 6205 /* reg_ritr_ipv4_mc_fe 6206 * IPv4 Multicast Forwarding Enable. 6207 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 6208 * will be enabled. 6209 * Access: RW 6210 */ 6211 MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1); 6212 6213 /* reg_ritr_ipv6_mc_fe 6214 * IPv6 Multicast Forwarding Enable. 6215 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 6216 * will be enabled. 6217 * Access: RW 6218 */ 6219 MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1); 6220 6221 /* reg_ritr_lb_en 6222 * Loop-back filter enable for unicast packets. 6223 * If the flag is set then loop-back filter for unicast packets is 6224 * implemented on the RIF. Multicast packets are always subject to 6225 * loop-back filtering. 6226 * Access: RW 6227 */ 6228 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1); 6229 6230 /* reg_ritr_virtual_router 6231 * Virtual router ID associated with the router interface. 6232 * Access: RW 6233 */ 6234 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16); 6235 6236 /* reg_ritr_mtu 6237 * Router interface MTU. 6238 * Access: RW 6239 */ 6240 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16); 6241 6242 /* reg_ritr_if_swid 6243 * Switch partition ID. 6244 * Access: RW 6245 */ 6246 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8); 6247 6248 /* reg_ritr_if_mac 6249 * Router interface MAC address. 6250 * In Spectrum, all MAC addresses must have the same 38 MSBits. 6251 * Access: RW 6252 */ 6253 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6); 6254 6255 /* reg_ritr_if_vrrp_id_ipv6 6256 * VRRP ID for IPv6 6257 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 6258 * Access: RW 6259 */ 6260 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8); 6261 6262 /* reg_ritr_if_vrrp_id_ipv4 6263 * VRRP ID for IPv4 6264 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 6265 * Access: RW 6266 */ 6267 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8); 6268 6269 /* VLAN Interface */ 6270 6271 /* reg_ritr_vlan_if_vid 6272 * VLAN ID. 6273 * Access: RW 6274 */ 6275 MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12); 6276 6277 /* FID Interface */ 6278 6279 /* reg_ritr_fid_if_fid 6280 * Filtering ID. Used to connect a bridge to the router. Only FIDs from 6281 * the vFID range are supported. 6282 * Access: RW 6283 */ 6284 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16); 6285 6286 static inline void mlxsw_reg_ritr_fid_set(char *payload, 6287 enum mlxsw_reg_ritr_if_type rif_type, 6288 u16 fid) 6289 { 6290 if (rif_type == MLXSW_REG_RITR_FID_IF) 6291 mlxsw_reg_ritr_fid_if_fid_set(payload, fid); 6292 else 6293 mlxsw_reg_ritr_vlan_if_vid_set(payload, fid); 6294 } 6295 6296 /* Sub-port Interface */ 6297 6298 /* reg_ritr_sp_if_lag 6299 * LAG indication. When this bit is set the system_port field holds the 6300 * LAG identifier. 6301 * Access: RW 6302 */ 6303 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1); 6304 6305 /* reg_ritr_sp_system_port 6306 * Port unique indentifier. When lag bit is set, this field holds the 6307 * lag_id in bits 0:9. 6308 * Access: RW 6309 */ 6310 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16); 6311 6312 /* reg_ritr_sp_if_vid 6313 * VLAN ID. 6314 * Access: RW 6315 */ 6316 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12); 6317 6318 /* Loopback Interface */ 6319 6320 enum mlxsw_reg_ritr_loopback_protocol { 6321 /* IPinIP IPv4 underlay Unicast */ 6322 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4, 6323 /* IPinIP IPv6 underlay Unicast */ 6324 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6, 6325 /* IPinIP generic - used for Spectrum-2 underlay RIF */ 6326 MLXSW_REG_RITR_LOOPBACK_GENERIC, 6327 }; 6328 6329 /* reg_ritr_loopback_protocol 6330 * Access: RW 6331 */ 6332 MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4); 6333 6334 enum mlxsw_reg_ritr_loopback_ipip_type { 6335 /* Tunnel is IPinIP. */ 6336 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP, 6337 /* Tunnel is GRE, no key. */ 6338 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP, 6339 /* Tunnel is GRE, with a key. */ 6340 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP, 6341 }; 6342 6343 /* reg_ritr_loopback_ipip_type 6344 * Encapsulation type. 6345 * Access: RW 6346 */ 6347 MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4); 6348 6349 enum mlxsw_reg_ritr_loopback_ipip_options { 6350 /* The key is defined by gre_key. */ 6351 MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET, 6352 }; 6353 6354 /* reg_ritr_loopback_ipip_options 6355 * Access: RW 6356 */ 6357 MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4); 6358 6359 /* reg_ritr_loopback_ipip_uvr 6360 * Underlay Virtual Router ID. 6361 * Range is 0..cap_max_virtual_routers-1. 6362 * Reserved for Spectrum-2. 6363 * Access: RW 6364 */ 6365 MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16); 6366 6367 /* reg_ritr_loopback_ipip_underlay_rif 6368 * Underlay ingress router interface. 6369 * Reserved for Spectrum. 6370 * Access: RW 6371 */ 6372 MLXSW_ITEM32(reg, ritr, loopback_ipip_underlay_rif, 0x14, 0, 16); 6373 6374 /* reg_ritr_loopback_ipip_usip* 6375 * Encapsulation Underlay source IP. 6376 * Access: RW 6377 */ 6378 MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16); 6379 MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32); 6380 6381 /* reg_ritr_loopback_ipip_gre_key 6382 * GRE Key. 6383 * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP. 6384 * Access: RW 6385 */ 6386 MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32); 6387 6388 /* Shared between ingress/egress */ 6389 enum mlxsw_reg_ritr_counter_set_type { 6390 /* No Count. */ 6391 MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0, 6392 /* Basic. Used for router interfaces, counting the following: 6393 * - Error and Discard counters. 6394 * - Unicast, Multicast and Broadcast counters. Sharing the 6395 * same set of counters for the different type of traffic 6396 * (IPv4, IPv6 and mpls). 6397 */ 6398 MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9, 6399 }; 6400 6401 /* reg_ritr_ingress_counter_index 6402 * Counter Index for flow counter. 6403 * Access: RW 6404 */ 6405 MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24); 6406 6407 /* reg_ritr_ingress_counter_set_type 6408 * Igress Counter Set Type for router interface counter. 6409 * Access: RW 6410 */ 6411 MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8); 6412 6413 /* reg_ritr_egress_counter_index 6414 * Counter Index for flow counter. 6415 * Access: RW 6416 */ 6417 MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24); 6418 6419 /* reg_ritr_egress_counter_set_type 6420 * Egress Counter Set Type for router interface counter. 6421 * Access: RW 6422 */ 6423 MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8); 6424 6425 static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index, 6426 bool enable, bool egress) 6427 { 6428 enum mlxsw_reg_ritr_counter_set_type set_type; 6429 6430 if (enable) 6431 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC; 6432 else 6433 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT; 6434 mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type); 6435 6436 if (egress) 6437 mlxsw_reg_ritr_egress_counter_index_set(payload, index); 6438 else 6439 mlxsw_reg_ritr_ingress_counter_index_set(payload, index); 6440 } 6441 6442 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif) 6443 { 6444 MLXSW_REG_ZERO(ritr, payload); 6445 mlxsw_reg_ritr_rif_set(payload, rif); 6446 } 6447 6448 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag, 6449 u16 system_port, u16 vid) 6450 { 6451 mlxsw_reg_ritr_sp_if_lag_set(payload, lag); 6452 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port); 6453 mlxsw_reg_ritr_sp_if_vid_set(payload, vid); 6454 } 6455 6456 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable, 6457 enum mlxsw_reg_ritr_if_type type, 6458 u16 rif, u16 vr_id, u16 mtu) 6459 { 6460 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL; 6461 6462 MLXSW_REG_ZERO(ritr, payload); 6463 mlxsw_reg_ritr_enable_set(payload, enable); 6464 mlxsw_reg_ritr_ipv4_set(payload, 1); 6465 mlxsw_reg_ritr_ipv6_set(payload, 1); 6466 mlxsw_reg_ritr_ipv4_mc_set(payload, 1); 6467 mlxsw_reg_ritr_ipv6_mc_set(payload, 1); 6468 mlxsw_reg_ritr_type_set(payload, type); 6469 mlxsw_reg_ritr_op_set(payload, op); 6470 mlxsw_reg_ritr_rif_set(payload, rif); 6471 mlxsw_reg_ritr_ipv4_fe_set(payload, 1); 6472 mlxsw_reg_ritr_ipv6_fe_set(payload, 1); 6473 mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1); 6474 mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1); 6475 mlxsw_reg_ritr_lb_en_set(payload, 1); 6476 mlxsw_reg_ritr_virtual_router_set(payload, vr_id); 6477 mlxsw_reg_ritr_mtu_set(payload, mtu); 6478 } 6479 6480 static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac) 6481 { 6482 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac); 6483 } 6484 6485 static inline void 6486 mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload, 6487 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 6488 enum mlxsw_reg_ritr_loopback_ipip_options options, 6489 u16 uvr_id, u16 underlay_rif, u32 gre_key) 6490 { 6491 mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type); 6492 mlxsw_reg_ritr_loopback_ipip_options_set(payload, options); 6493 mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id); 6494 mlxsw_reg_ritr_loopback_ipip_underlay_rif_set(payload, underlay_rif); 6495 mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key); 6496 } 6497 6498 static inline void 6499 mlxsw_reg_ritr_loopback_ipip4_pack(char *payload, 6500 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 6501 enum mlxsw_reg_ritr_loopback_ipip_options options, 6502 u16 uvr_id, u16 underlay_rif, u32 usip, u32 gre_key) 6503 { 6504 mlxsw_reg_ritr_loopback_protocol_set(payload, 6505 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4); 6506 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options, 6507 uvr_id, underlay_rif, gre_key); 6508 mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip); 6509 } 6510 6511 /* RTAR - Router TCAM Allocation Register 6512 * -------------------------------------- 6513 * This register is used for allocation of regions in the TCAM table. 6514 */ 6515 #define MLXSW_REG_RTAR_ID 0x8004 6516 #define MLXSW_REG_RTAR_LEN 0x20 6517 6518 MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN); 6519 6520 enum mlxsw_reg_rtar_op { 6521 MLXSW_REG_RTAR_OP_ALLOCATE, 6522 MLXSW_REG_RTAR_OP_RESIZE, 6523 MLXSW_REG_RTAR_OP_DEALLOCATE, 6524 }; 6525 6526 /* reg_rtar_op 6527 * Access: WO 6528 */ 6529 MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4); 6530 6531 enum mlxsw_reg_rtar_key_type { 6532 MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1, 6533 MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3 6534 }; 6535 6536 /* reg_rtar_key_type 6537 * TCAM key type for the region. 6538 * Access: WO 6539 */ 6540 MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8); 6541 6542 /* reg_rtar_region_size 6543 * TCAM region size. When allocating/resizing this is the requested 6544 * size, the response is the actual size. 6545 * Note: Actual size may be larger than requested. 6546 * Reserved for op = Deallocate 6547 * Access: WO 6548 */ 6549 MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16); 6550 6551 static inline void mlxsw_reg_rtar_pack(char *payload, 6552 enum mlxsw_reg_rtar_op op, 6553 enum mlxsw_reg_rtar_key_type key_type, 6554 u16 region_size) 6555 { 6556 MLXSW_REG_ZERO(rtar, payload); 6557 mlxsw_reg_rtar_op_set(payload, op); 6558 mlxsw_reg_rtar_key_type_set(payload, key_type); 6559 mlxsw_reg_rtar_region_size_set(payload, region_size); 6560 } 6561 6562 /* RATR - Router Adjacency Table Register 6563 * -------------------------------------- 6564 * The RATR register is used to configure the Router Adjacency (next-hop) 6565 * Table. 6566 */ 6567 #define MLXSW_REG_RATR_ID 0x8008 6568 #define MLXSW_REG_RATR_LEN 0x2C 6569 6570 MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN); 6571 6572 enum mlxsw_reg_ratr_op { 6573 /* Read */ 6574 MLXSW_REG_RATR_OP_QUERY_READ = 0, 6575 /* Read and clear activity */ 6576 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2, 6577 /* Write Adjacency entry */ 6578 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1, 6579 /* Write Adjacency entry only if the activity is cleared. 6580 * The write may not succeed if the activity is set. There is not 6581 * direct feedback if the write has succeeded or not, however 6582 * the get will reveal the actual entry (SW can compare the get 6583 * response to the set command). 6584 */ 6585 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3, 6586 }; 6587 6588 /* reg_ratr_op 6589 * Note that Write operation may also be used for updating 6590 * counter_set_type and counter_index. In this case all other 6591 * fields must not be updated. 6592 * Access: OP 6593 */ 6594 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4); 6595 6596 /* reg_ratr_v 6597 * Valid bit. Indicates if the adjacency entry is valid. 6598 * Note: the device may need some time before reusing an invalidated 6599 * entry. During this time the entry can not be reused. It is 6600 * recommended to use another entry before reusing an invalidated 6601 * entry (e.g. software can put it at the end of the list for 6602 * reusing). Trying to access an invalidated entry not yet cleared 6603 * by the device results with failure indicating "Try Again" status. 6604 * When valid is '0' then egress_router_interface,trap_action, 6605 * adjacency_parameters and counters are reserved 6606 * Access: RW 6607 */ 6608 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1); 6609 6610 /* reg_ratr_a 6611 * Activity. Set for new entries. Set if a packet lookup has hit on 6612 * the specific entry. To clear the a bit, use "clear activity". 6613 * Access: RO 6614 */ 6615 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1); 6616 6617 enum mlxsw_reg_ratr_type { 6618 /* Ethernet */ 6619 MLXSW_REG_RATR_TYPE_ETHERNET, 6620 /* IPoIB Unicast without GRH. 6621 * Reserved for Spectrum. 6622 */ 6623 MLXSW_REG_RATR_TYPE_IPOIB_UC, 6624 /* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast 6625 * adjacency). 6626 * Reserved for Spectrum. 6627 */ 6628 MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH, 6629 /* IPoIB Multicast. 6630 * Reserved for Spectrum. 6631 */ 6632 MLXSW_REG_RATR_TYPE_IPOIB_MC, 6633 /* MPLS. 6634 * Reserved for SwitchX/-2. 6635 */ 6636 MLXSW_REG_RATR_TYPE_MPLS, 6637 /* IPinIP Encap. 6638 * Reserved for SwitchX/-2. 6639 */ 6640 MLXSW_REG_RATR_TYPE_IPIP, 6641 }; 6642 6643 /* reg_ratr_type 6644 * Adjacency entry type. 6645 * Access: RW 6646 */ 6647 MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4); 6648 6649 /* reg_ratr_adjacency_index_low 6650 * Bits 15:0 of index into the adjacency table. 6651 * For SwitchX and SwitchX-2, the adjacency table is linear and 6652 * used for adjacency entries only. 6653 * For Spectrum, the index is to the KVD linear. 6654 * Access: Index 6655 */ 6656 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16); 6657 6658 /* reg_ratr_egress_router_interface 6659 * Range is 0 .. cap_max_router_interfaces - 1 6660 * Access: RW 6661 */ 6662 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16); 6663 6664 enum mlxsw_reg_ratr_trap_action { 6665 MLXSW_REG_RATR_TRAP_ACTION_NOP, 6666 MLXSW_REG_RATR_TRAP_ACTION_TRAP, 6667 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU, 6668 MLXSW_REG_RATR_TRAP_ACTION_MIRROR, 6669 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS, 6670 }; 6671 6672 /* reg_ratr_trap_action 6673 * see mlxsw_reg_ratr_trap_action 6674 * Access: RW 6675 */ 6676 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4); 6677 6678 /* reg_ratr_adjacency_index_high 6679 * Bits 23:16 of the adjacency_index. 6680 * Access: Index 6681 */ 6682 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8); 6683 6684 enum mlxsw_reg_ratr_trap_id { 6685 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0, 6686 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1, 6687 }; 6688 6689 /* reg_ratr_trap_id 6690 * Trap ID to be reported to CPU. 6691 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 6692 * For trap_action of NOP, MIRROR and DISCARD_ERROR 6693 * Access: RW 6694 */ 6695 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8); 6696 6697 /* reg_ratr_eth_destination_mac 6698 * MAC address of the destination next-hop. 6699 * Access: RW 6700 */ 6701 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6); 6702 6703 enum mlxsw_reg_ratr_ipip_type { 6704 /* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */ 6705 MLXSW_REG_RATR_IPIP_TYPE_IPV4, 6706 /* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */ 6707 MLXSW_REG_RATR_IPIP_TYPE_IPV6, 6708 }; 6709 6710 /* reg_ratr_ipip_type 6711 * Underlay destination ip type. 6712 * Note: the type field must match the protocol of the router interface. 6713 * Access: RW 6714 */ 6715 MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4); 6716 6717 /* reg_ratr_ipip_ipv4_udip 6718 * Underlay ipv4 dip. 6719 * Reserved when ipip_type is IPv6. 6720 * Access: RW 6721 */ 6722 MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32); 6723 6724 /* reg_ratr_ipip_ipv6_ptr 6725 * Pointer to IPv6 underlay destination ip address. 6726 * For Spectrum: Pointer to KVD linear space. 6727 * Access: RW 6728 */ 6729 MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24); 6730 6731 enum mlxsw_reg_flow_counter_set_type { 6732 /* No count */ 6733 MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00, 6734 /* Count packets and bytes */ 6735 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03, 6736 /* Count only packets */ 6737 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05, 6738 }; 6739 6740 /* reg_ratr_counter_set_type 6741 * Counter set type for flow counters 6742 * Access: RW 6743 */ 6744 MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8); 6745 6746 /* reg_ratr_counter_index 6747 * Counter index for flow counters 6748 * Access: RW 6749 */ 6750 MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24); 6751 6752 static inline void 6753 mlxsw_reg_ratr_pack(char *payload, 6754 enum mlxsw_reg_ratr_op op, bool valid, 6755 enum mlxsw_reg_ratr_type type, 6756 u32 adjacency_index, u16 egress_rif) 6757 { 6758 MLXSW_REG_ZERO(ratr, payload); 6759 mlxsw_reg_ratr_op_set(payload, op); 6760 mlxsw_reg_ratr_v_set(payload, valid); 6761 mlxsw_reg_ratr_type_set(payload, type); 6762 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index); 6763 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16); 6764 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif); 6765 } 6766 6767 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload, 6768 const char *dest_mac) 6769 { 6770 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac); 6771 } 6772 6773 static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip) 6774 { 6775 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4); 6776 mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip); 6777 } 6778 6779 static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index, 6780 bool counter_enable) 6781 { 6782 enum mlxsw_reg_flow_counter_set_type set_type; 6783 6784 if (counter_enable) 6785 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES; 6786 else 6787 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT; 6788 6789 mlxsw_reg_ratr_counter_index_set(payload, counter_index); 6790 mlxsw_reg_ratr_counter_set_type_set(payload, set_type); 6791 } 6792 6793 /* RDPM - Router DSCP to Priority Mapping 6794 * -------------------------------------- 6795 * Controls the mapping from DSCP field to switch priority on routed packets 6796 */ 6797 #define MLXSW_REG_RDPM_ID 0x8009 6798 #define MLXSW_REG_RDPM_BASE_LEN 0x00 6799 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01 6800 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64 6801 #define MLXSW_REG_RDPM_LEN 0x40 6802 #define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \ 6803 MLXSW_REG_RDPM_LEN - \ 6804 MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN) 6805 6806 MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN); 6807 6808 /* reg_dscp_entry_e 6809 * Enable update of the specific entry 6810 * Access: Index 6811 */ 6812 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1, 6813 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 6814 6815 /* reg_dscp_entry_prio 6816 * Switch Priority 6817 * Access: RW 6818 */ 6819 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4, 6820 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 6821 6822 static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index, 6823 u8 prio) 6824 { 6825 mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1); 6826 mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio); 6827 } 6828 6829 /* RICNT - Router Interface Counter Register 6830 * ----------------------------------------- 6831 * The RICNT register retrieves per port performance counters 6832 */ 6833 #define MLXSW_REG_RICNT_ID 0x800B 6834 #define MLXSW_REG_RICNT_LEN 0x100 6835 6836 MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN); 6837 6838 /* reg_ricnt_counter_index 6839 * Counter index 6840 * Access: RW 6841 */ 6842 MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24); 6843 6844 enum mlxsw_reg_ricnt_counter_set_type { 6845 /* No Count. */ 6846 MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00, 6847 /* Basic. Used for router interfaces, counting the following: 6848 * - Error and Discard counters. 6849 * - Unicast, Multicast and Broadcast counters. Sharing the 6850 * same set of counters for the different type of traffic 6851 * (IPv4, IPv6 and mpls). 6852 */ 6853 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09, 6854 }; 6855 6856 /* reg_ricnt_counter_set_type 6857 * Counter Set Type for router interface counter 6858 * Access: RW 6859 */ 6860 MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8); 6861 6862 enum mlxsw_reg_ricnt_opcode { 6863 /* Nop. Supported only for read access*/ 6864 MLXSW_REG_RICNT_OPCODE_NOP = 0x00, 6865 /* Clear. Setting the clr bit will reset the counter value for 6866 * all counters of the specified Router Interface. 6867 */ 6868 MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08, 6869 }; 6870 6871 /* reg_ricnt_opcode 6872 * Opcode 6873 * Access: RW 6874 */ 6875 MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4); 6876 6877 /* reg_ricnt_good_unicast_packets 6878 * good unicast packets. 6879 * Access: RW 6880 */ 6881 MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64); 6882 6883 /* reg_ricnt_good_multicast_packets 6884 * good multicast packets. 6885 * Access: RW 6886 */ 6887 MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64); 6888 6889 /* reg_ricnt_good_broadcast_packets 6890 * good broadcast packets 6891 * Access: RW 6892 */ 6893 MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64); 6894 6895 /* reg_ricnt_good_unicast_bytes 6896 * A count of L3 data and padding octets not including L2 headers 6897 * for good unicast frames. 6898 * Access: RW 6899 */ 6900 MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64); 6901 6902 /* reg_ricnt_good_multicast_bytes 6903 * A count of L3 data and padding octets not including L2 headers 6904 * for good multicast frames. 6905 * Access: RW 6906 */ 6907 MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64); 6908 6909 /* reg_ritr_good_broadcast_bytes 6910 * A count of L3 data and padding octets not including L2 headers 6911 * for good broadcast frames. 6912 * Access: RW 6913 */ 6914 MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64); 6915 6916 /* reg_ricnt_error_packets 6917 * A count of errored frames that do not pass the router checks. 6918 * Access: RW 6919 */ 6920 MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64); 6921 6922 /* reg_ricnt_discrad_packets 6923 * A count of non-errored frames that do not pass the router checks. 6924 * Access: RW 6925 */ 6926 MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64); 6927 6928 /* reg_ricnt_error_bytes 6929 * A count of L3 data and padding octets not including L2 headers 6930 * for errored frames. 6931 * Access: RW 6932 */ 6933 MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64); 6934 6935 /* reg_ricnt_discard_bytes 6936 * A count of L3 data and padding octets not including L2 headers 6937 * for non-errored frames that do not pass the router checks. 6938 * Access: RW 6939 */ 6940 MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64); 6941 6942 static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index, 6943 enum mlxsw_reg_ricnt_opcode op) 6944 { 6945 MLXSW_REG_ZERO(ricnt, payload); 6946 mlxsw_reg_ricnt_op_set(payload, op); 6947 mlxsw_reg_ricnt_counter_index_set(payload, index); 6948 mlxsw_reg_ricnt_counter_set_type_set(payload, 6949 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC); 6950 } 6951 6952 /* RRCR - Router Rules Copy Register Layout 6953 * ---------------------------------------- 6954 * This register is used for moving and copying route entry rules. 6955 */ 6956 #define MLXSW_REG_RRCR_ID 0x800F 6957 #define MLXSW_REG_RRCR_LEN 0x24 6958 6959 MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN); 6960 6961 enum mlxsw_reg_rrcr_op { 6962 /* Move rules */ 6963 MLXSW_REG_RRCR_OP_MOVE, 6964 /* Copy rules */ 6965 MLXSW_REG_RRCR_OP_COPY, 6966 }; 6967 6968 /* reg_rrcr_op 6969 * Access: WO 6970 */ 6971 MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4); 6972 6973 /* reg_rrcr_offset 6974 * Offset within the region from which to copy/move. 6975 * Access: Index 6976 */ 6977 MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16); 6978 6979 /* reg_rrcr_size 6980 * The number of rules to copy/move. 6981 * Access: WO 6982 */ 6983 MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16); 6984 6985 /* reg_rrcr_table_id 6986 * Identifier of the table on which to perform the operation. Encoding is the 6987 * same as in RTAR.key_type 6988 * Access: Index 6989 */ 6990 MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4); 6991 6992 /* reg_rrcr_dest_offset 6993 * Offset within the region to which to copy/move 6994 * Access: Index 6995 */ 6996 MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16); 6997 6998 static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op, 6999 u16 offset, u16 size, 7000 enum mlxsw_reg_rtar_key_type table_id, 7001 u16 dest_offset) 7002 { 7003 MLXSW_REG_ZERO(rrcr, payload); 7004 mlxsw_reg_rrcr_op_set(payload, op); 7005 mlxsw_reg_rrcr_offset_set(payload, offset); 7006 mlxsw_reg_rrcr_size_set(payload, size); 7007 mlxsw_reg_rrcr_table_id_set(payload, table_id); 7008 mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset); 7009 } 7010 7011 /* RALTA - Router Algorithmic LPM Tree Allocation Register 7012 * ------------------------------------------------------- 7013 * RALTA is used to allocate the LPM trees of the SHSPM method. 7014 */ 7015 #define MLXSW_REG_RALTA_ID 0x8010 7016 #define MLXSW_REG_RALTA_LEN 0x04 7017 7018 MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN); 7019 7020 /* reg_ralta_op 7021 * opcode (valid for Write, must be 0 on Read) 7022 * 0 - allocate a tree 7023 * 1 - deallocate a tree 7024 * Access: OP 7025 */ 7026 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2); 7027 7028 enum mlxsw_reg_ralxx_protocol { 7029 MLXSW_REG_RALXX_PROTOCOL_IPV4, 7030 MLXSW_REG_RALXX_PROTOCOL_IPV6, 7031 }; 7032 7033 /* reg_ralta_protocol 7034 * Protocol. 7035 * Deallocation opcode: Reserved. 7036 * Access: RW 7037 */ 7038 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4); 7039 7040 /* reg_ralta_tree_id 7041 * An identifier (numbered from 1..cap_shspm_max_trees-1) representing 7042 * the tree identifier (managed by software). 7043 * Note that tree_id 0 is allocated for a default-route tree. 7044 * Access: Index 7045 */ 7046 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8); 7047 7048 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc, 7049 enum mlxsw_reg_ralxx_protocol protocol, 7050 u8 tree_id) 7051 { 7052 MLXSW_REG_ZERO(ralta, payload); 7053 mlxsw_reg_ralta_op_set(payload, !alloc); 7054 mlxsw_reg_ralta_protocol_set(payload, protocol); 7055 mlxsw_reg_ralta_tree_id_set(payload, tree_id); 7056 } 7057 7058 /* RALST - Router Algorithmic LPM Structure Tree Register 7059 * ------------------------------------------------------ 7060 * RALST is used to set and query the structure of an LPM tree. 7061 * The structure of the tree must be sorted as a sorted binary tree, while 7062 * each node is a bin that is tagged as the length of the prefixes the lookup 7063 * will refer to. Therefore, bin X refers to a set of entries with prefixes 7064 * of X bits to match with the destination address. The bin 0 indicates 7065 * the default action, when there is no match of any prefix. 7066 */ 7067 #define MLXSW_REG_RALST_ID 0x8011 7068 #define MLXSW_REG_RALST_LEN 0x104 7069 7070 MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN); 7071 7072 /* reg_ralst_root_bin 7073 * The bin number of the root bin. 7074 * 0<root_bin=<(length of IP address) 7075 * For a default-route tree configure 0xff 7076 * Access: RW 7077 */ 7078 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8); 7079 7080 /* reg_ralst_tree_id 7081 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 7082 * Access: Index 7083 */ 7084 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8); 7085 7086 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff 7087 #define MLXSW_REG_RALST_BIN_OFFSET 0x04 7088 #define MLXSW_REG_RALST_BIN_COUNT 128 7089 7090 /* reg_ralst_left_child_bin 7091 * Holding the children of the bin according to the stored tree's structure. 7092 * For trees composed of less than 4 blocks, the bins in excess are reserved. 7093 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 7094 * Access: RW 7095 */ 7096 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false); 7097 7098 /* reg_ralst_right_child_bin 7099 * Holding the children of the bin according to the stored tree's structure. 7100 * For trees composed of less than 4 blocks, the bins in excess are reserved. 7101 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 7102 * Access: RW 7103 */ 7104 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00, 7105 false); 7106 7107 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id) 7108 { 7109 MLXSW_REG_ZERO(ralst, payload); 7110 7111 /* Initialize all bins to have no left or right child */ 7112 memset(payload + MLXSW_REG_RALST_BIN_OFFSET, 7113 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2); 7114 7115 mlxsw_reg_ralst_root_bin_set(payload, root_bin); 7116 mlxsw_reg_ralst_tree_id_set(payload, tree_id); 7117 } 7118 7119 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number, 7120 u8 left_child_bin, 7121 u8 right_child_bin) 7122 { 7123 int bin_index = bin_number - 1; 7124 7125 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin); 7126 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index, 7127 right_child_bin); 7128 } 7129 7130 /* RALTB - Router Algorithmic LPM Tree Binding Register 7131 * ---------------------------------------------------- 7132 * RALTB is used to bind virtual router and protocol to an allocated LPM tree. 7133 */ 7134 #define MLXSW_REG_RALTB_ID 0x8012 7135 #define MLXSW_REG_RALTB_LEN 0x04 7136 7137 MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN); 7138 7139 /* reg_raltb_virtual_router 7140 * Virtual Router ID 7141 * Range is 0..cap_max_virtual_routers-1 7142 * Access: Index 7143 */ 7144 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16); 7145 7146 /* reg_raltb_protocol 7147 * Protocol. 7148 * Access: Index 7149 */ 7150 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4); 7151 7152 /* reg_raltb_tree_id 7153 * Tree to be used for the {virtual_router, protocol} 7154 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 7155 * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0. 7156 * Access: RW 7157 */ 7158 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8); 7159 7160 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router, 7161 enum mlxsw_reg_ralxx_protocol protocol, 7162 u8 tree_id) 7163 { 7164 MLXSW_REG_ZERO(raltb, payload); 7165 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router); 7166 mlxsw_reg_raltb_protocol_set(payload, protocol); 7167 mlxsw_reg_raltb_tree_id_set(payload, tree_id); 7168 } 7169 7170 /* RALUE - Router Algorithmic LPM Unicast Entry Register 7171 * ----------------------------------------------------- 7172 * RALUE is used to configure and query LPM entries that serve 7173 * the Unicast protocols. 7174 */ 7175 #define MLXSW_REG_RALUE_ID 0x8013 7176 #define MLXSW_REG_RALUE_LEN 0x38 7177 7178 MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN); 7179 7180 /* reg_ralue_protocol 7181 * Protocol. 7182 * Access: Index 7183 */ 7184 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4); 7185 7186 enum mlxsw_reg_ralue_op { 7187 /* Read operation. If entry doesn't exist, the operation fails. */ 7188 MLXSW_REG_RALUE_OP_QUERY_READ = 0, 7189 /* Clear on read operation. Used to read entry and 7190 * clear Activity bit. 7191 */ 7192 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1, 7193 /* Write operation. Used to write a new entry to the table. All RW 7194 * fields are written for new entry. Activity bit is set 7195 * for new entries. 7196 */ 7197 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0, 7198 /* Update operation. Used to update an existing route entry and 7199 * only update the RW fields that are detailed in the field 7200 * op_u_mask. If entry doesn't exist, the operation fails. 7201 */ 7202 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1, 7203 /* Clear activity. The Activity bit (the field a) is cleared 7204 * for the entry. 7205 */ 7206 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2, 7207 /* Delete operation. Used to delete an existing entry. If entry 7208 * doesn't exist, the operation fails. 7209 */ 7210 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3, 7211 }; 7212 7213 /* reg_ralue_op 7214 * Operation. 7215 * Access: OP 7216 */ 7217 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3); 7218 7219 /* reg_ralue_a 7220 * Activity. Set for new entries. Set if a packet lookup has hit on the 7221 * specific entry, only if the entry is a route. To clear the a bit, use 7222 * "clear activity" op. 7223 * Enabled by activity_dis in RGCR 7224 * Access: RO 7225 */ 7226 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1); 7227 7228 /* reg_ralue_virtual_router 7229 * Virtual Router ID 7230 * Range is 0..cap_max_virtual_routers-1 7231 * Access: Index 7232 */ 7233 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16); 7234 7235 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0) 7236 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1) 7237 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2) 7238 7239 /* reg_ralue_op_u_mask 7240 * opcode update mask. 7241 * On read operation, this field is reserved. 7242 * This field is valid for update opcode, otherwise - reserved. 7243 * This field is a bitmask of the fields that should be updated. 7244 * Access: WO 7245 */ 7246 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3); 7247 7248 /* reg_ralue_prefix_len 7249 * Number of bits in the prefix of the LPM route. 7250 * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes 7251 * two entries in the physical HW table. 7252 * Access: Index 7253 */ 7254 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8); 7255 7256 /* reg_ralue_dip* 7257 * The prefix of the route or of the marker that the object of the LPM 7258 * is compared with. The most significant bits of the dip are the prefix. 7259 * The least significant bits must be '0' if the prefix_len is smaller 7260 * than 128 for IPv6 or smaller than 32 for IPv4. 7261 * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved. 7262 * Access: Index 7263 */ 7264 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32); 7265 MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16); 7266 7267 enum mlxsw_reg_ralue_entry_type { 7268 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1, 7269 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2, 7270 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3, 7271 }; 7272 7273 /* reg_ralue_entry_type 7274 * Entry type. 7275 * Note - for Marker entries, the action_type and action fields are reserved. 7276 * Access: RW 7277 */ 7278 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2); 7279 7280 /* reg_ralue_bmp_len 7281 * The best match prefix length in the case that there is no match for 7282 * longer prefixes. 7283 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len 7284 * Note for any update operation with entry_type modification this 7285 * field must be set. 7286 * Access: RW 7287 */ 7288 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8); 7289 7290 enum mlxsw_reg_ralue_action_type { 7291 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE, 7292 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL, 7293 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME, 7294 }; 7295 7296 /* reg_ralue_action_type 7297 * Action Type 7298 * Indicates how the IP address is connected. 7299 * It can be connected to a local subnet through local_erif or can be 7300 * on a remote subnet connected through a next-hop router, 7301 * or transmitted to the CPU. 7302 * Reserved when entry_type = MARKER_ENTRY 7303 * Access: RW 7304 */ 7305 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2); 7306 7307 enum mlxsw_reg_ralue_trap_action { 7308 MLXSW_REG_RALUE_TRAP_ACTION_NOP, 7309 MLXSW_REG_RALUE_TRAP_ACTION_TRAP, 7310 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU, 7311 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR, 7312 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR, 7313 }; 7314 7315 /* reg_ralue_trap_action 7316 * Trap action. 7317 * For IP2ME action, only NOP and MIRROR are possible. 7318 * Access: RW 7319 */ 7320 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4); 7321 7322 /* reg_ralue_trap_id 7323 * Trap ID to be reported to CPU. 7324 * Trap ID is RTR_INGRESS0 or RTR_INGRESS1. 7325 * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved. 7326 * Access: RW 7327 */ 7328 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9); 7329 7330 /* reg_ralue_adjacency_index 7331 * Points to the first entry of the group-based ECMP. 7332 * Only relevant in case of REMOTE action. 7333 * Access: RW 7334 */ 7335 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24); 7336 7337 /* reg_ralue_ecmp_size 7338 * Amount of sequential entries starting 7339 * from the adjacency_index (the number of ECMPs). 7340 * The valid range is 1-64, 512, 1024, 2048 and 4096. 7341 * Reserved when trap_action is TRAP or DISCARD_ERROR. 7342 * Only relevant in case of REMOTE action. 7343 * Access: RW 7344 */ 7345 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13); 7346 7347 /* reg_ralue_local_erif 7348 * Egress Router Interface. 7349 * Only relevant in case of LOCAL action. 7350 * Access: RW 7351 */ 7352 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16); 7353 7354 /* reg_ralue_ip2me_v 7355 * Valid bit for the tunnel_ptr field. 7356 * If valid = 0 then trap to CPU as IP2ME trap ID. 7357 * If valid = 1 and the packet format allows NVE or IPinIP tunnel 7358 * decapsulation then tunnel decapsulation is done. 7359 * If valid = 1 and packet format does not allow NVE or IPinIP tunnel 7360 * decapsulation then trap as IP2ME trap ID. 7361 * Only relevant in case of IP2ME action. 7362 * Access: RW 7363 */ 7364 MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1); 7365 7366 /* reg_ralue_ip2me_tunnel_ptr 7367 * Tunnel Pointer for NVE or IPinIP tunnel decapsulation. 7368 * For Spectrum, pointer to KVD Linear. 7369 * Only relevant in case of IP2ME action. 7370 * Access: RW 7371 */ 7372 MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24); 7373 7374 static inline void mlxsw_reg_ralue_pack(char *payload, 7375 enum mlxsw_reg_ralxx_protocol protocol, 7376 enum mlxsw_reg_ralue_op op, 7377 u16 virtual_router, u8 prefix_len) 7378 { 7379 MLXSW_REG_ZERO(ralue, payload); 7380 mlxsw_reg_ralue_protocol_set(payload, protocol); 7381 mlxsw_reg_ralue_op_set(payload, op); 7382 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router); 7383 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len); 7384 mlxsw_reg_ralue_entry_type_set(payload, 7385 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY); 7386 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len); 7387 } 7388 7389 static inline void mlxsw_reg_ralue_pack4(char *payload, 7390 enum mlxsw_reg_ralxx_protocol protocol, 7391 enum mlxsw_reg_ralue_op op, 7392 u16 virtual_router, u8 prefix_len, 7393 u32 *dip) 7394 { 7395 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 7396 if (dip) 7397 mlxsw_reg_ralue_dip4_set(payload, *dip); 7398 } 7399 7400 static inline void mlxsw_reg_ralue_pack6(char *payload, 7401 enum mlxsw_reg_ralxx_protocol protocol, 7402 enum mlxsw_reg_ralue_op op, 7403 u16 virtual_router, u8 prefix_len, 7404 const void *dip) 7405 { 7406 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 7407 if (dip) 7408 mlxsw_reg_ralue_dip6_memcpy_to(payload, dip); 7409 } 7410 7411 static inline void 7412 mlxsw_reg_ralue_act_remote_pack(char *payload, 7413 enum mlxsw_reg_ralue_trap_action trap_action, 7414 u16 trap_id, u32 adjacency_index, u16 ecmp_size) 7415 { 7416 mlxsw_reg_ralue_action_type_set(payload, 7417 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE); 7418 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 7419 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 7420 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index); 7421 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size); 7422 } 7423 7424 static inline void 7425 mlxsw_reg_ralue_act_local_pack(char *payload, 7426 enum mlxsw_reg_ralue_trap_action trap_action, 7427 u16 trap_id, u16 local_erif) 7428 { 7429 mlxsw_reg_ralue_action_type_set(payload, 7430 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL); 7431 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 7432 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 7433 mlxsw_reg_ralue_local_erif_set(payload, local_erif); 7434 } 7435 7436 static inline void 7437 mlxsw_reg_ralue_act_ip2me_pack(char *payload) 7438 { 7439 mlxsw_reg_ralue_action_type_set(payload, 7440 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 7441 } 7442 7443 static inline void 7444 mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr) 7445 { 7446 mlxsw_reg_ralue_action_type_set(payload, 7447 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 7448 mlxsw_reg_ralue_ip2me_v_set(payload, 1); 7449 mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr); 7450 } 7451 7452 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register 7453 * ---------------------------------------------------------- 7454 * The RAUHT register is used to configure and query the Unicast Host table in 7455 * devices that implement the Algorithmic LPM. 7456 */ 7457 #define MLXSW_REG_RAUHT_ID 0x8014 7458 #define MLXSW_REG_RAUHT_LEN 0x74 7459 7460 MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN); 7461 7462 enum mlxsw_reg_rauht_type { 7463 MLXSW_REG_RAUHT_TYPE_IPV4, 7464 MLXSW_REG_RAUHT_TYPE_IPV6, 7465 }; 7466 7467 /* reg_rauht_type 7468 * Access: Index 7469 */ 7470 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2); 7471 7472 enum mlxsw_reg_rauht_op { 7473 MLXSW_REG_RAUHT_OP_QUERY_READ = 0, 7474 /* Read operation */ 7475 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1, 7476 /* Clear on read operation. Used to read entry and clear 7477 * activity bit. 7478 */ 7479 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0, 7480 /* Add. Used to write a new entry to the table. All R/W fields are 7481 * relevant for new entry. Activity bit is set for new entries. 7482 */ 7483 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1, 7484 /* Update action. Used to update an existing route entry and 7485 * only update the following fields: 7486 * trap_action, trap_id, mac, counter_set_type, counter_index 7487 */ 7488 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2, 7489 /* Clear activity. A bit is cleared for the entry. */ 7490 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3, 7491 /* Delete entry */ 7492 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4, 7493 /* Delete all host entries on a RIF. In this command, dip 7494 * field is reserved. 7495 */ 7496 }; 7497 7498 /* reg_rauht_op 7499 * Access: OP 7500 */ 7501 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3); 7502 7503 /* reg_rauht_a 7504 * Activity. Set for new entries. Set if a packet lookup has hit on 7505 * the specific entry. 7506 * To clear the a bit, use "clear activity" op. 7507 * Enabled by activity_dis in RGCR 7508 * Access: RO 7509 */ 7510 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1); 7511 7512 /* reg_rauht_rif 7513 * Router Interface 7514 * Access: Index 7515 */ 7516 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16); 7517 7518 /* reg_rauht_dip* 7519 * Destination address. 7520 * Access: Index 7521 */ 7522 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32); 7523 MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16); 7524 7525 enum mlxsw_reg_rauht_trap_action { 7526 MLXSW_REG_RAUHT_TRAP_ACTION_NOP, 7527 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP, 7528 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU, 7529 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR, 7530 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS, 7531 }; 7532 7533 /* reg_rauht_trap_action 7534 * Access: RW 7535 */ 7536 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4); 7537 7538 enum mlxsw_reg_rauht_trap_id { 7539 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0, 7540 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1, 7541 }; 7542 7543 /* reg_rauht_trap_id 7544 * Trap ID to be reported to CPU. 7545 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 7546 * For trap_action of NOP, MIRROR and DISCARD_ERROR, 7547 * trap_id is reserved. 7548 * Access: RW 7549 */ 7550 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9); 7551 7552 /* reg_rauht_counter_set_type 7553 * Counter set type for flow counters 7554 * Access: RW 7555 */ 7556 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8); 7557 7558 /* reg_rauht_counter_index 7559 * Counter index for flow counters 7560 * Access: RW 7561 */ 7562 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24); 7563 7564 /* reg_rauht_mac 7565 * MAC address. 7566 * Access: RW 7567 */ 7568 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6); 7569 7570 static inline void mlxsw_reg_rauht_pack(char *payload, 7571 enum mlxsw_reg_rauht_op op, u16 rif, 7572 const char *mac) 7573 { 7574 MLXSW_REG_ZERO(rauht, payload); 7575 mlxsw_reg_rauht_op_set(payload, op); 7576 mlxsw_reg_rauht_rif_set(payload, rif); 7577 mlxsw_reg_rauht_mac_memcpy_to(payload, mac); 7578 } 7579 7580 static inline void mlxsw_reg_rauht_pack4(char *payload, 7581 enum mlxsw_reg_rauht_op op, u16 rif, 7582 const char *mac, u32 dip) 7583 { 7584 mlxsw_reg_rauht_pack(payload, op, rif, mac); 7585 mlxsw_reg_rauht_dip4_set(payload, dip); 7586 } 7587 7588 static inline void mlxsw_reg_rauht_pack6(char *payload, 7589 enum mlxsw_reg_rauht_op op, u16 rif, 7590 const char *mac, const char *dip) 7591 { 7592 mlxsw_reg_rauht_pack(payload, op, rif, mac); 7593 mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6); 7594 mlxsw_reg_rauht_dip6_memcpy_to(payload, dip); 7595 } 7596 7597 static inline void mlxsw_reg_rauht_pack_counter(char *payload, 7598 u64 counter_index) 7599 { 7600 mlxsw_reg_rauht_counter_index_set(payload, counter_index); 7601 mlxsw_reg_rauht_counter_set_type_set(payload, 7602 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 7603 } 7604 7605 /* RALEU - Router Algorithmic LPM ECMP Update Register 7606 * --------------------------------------------------- 7607 * The register enables updating the ECMP section in the action for multiple 7608 * LPM Unicast entries in a single operation. The update is executed to 7609 * all entries of a {virtual router, protocol} tuple using the same ECMP group. 7610 */ 7611 #define MLXSW_REG_RALEU_ID 0x8015 7612 #define MLXSW_REG_RALEU_LEN 0x28 7613 7614 MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN); 7615 7616 /* reg_raleu_protocol 7617 * Protocol. 7618 * Access: Index 7619 */ 7620 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4); 7621 7622 /* reg_raleu_virtual_router 7623 * Virtual Router ID 7624 * Range is 0..cap_max_virtual_routers-1 7625 * Access: Index 7626 */ 7627 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16); 7628 7629 /* reg_raleu_adjacency_index 7630 * Adjacency Index used for matching on the existing entries. 7631 * Access: Index 7632 */ 7633 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24); 7634 7635 /* reg_raleu_ecmp_size 7636 * ECMP Size used for matching on the existing entries. 7637 * Access: Index 7638 */ 7639 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13); 7640 7641 /* reg_raleu_new_adjacency_index 7642 * New Adjacency Index. 7643 * Access: WO 7644 */ 7645 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24); 7646 7647 /* reg_raleu_new_ecmp_size 7648 * New ECMP Size. 7649 * Access: WO 7650 */ 7651 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13); 7652 7653 static inline void mlxsw_reg_raleu_pack(char *payload, 7654 enum mlxsw_reg_ralxx_protocol protocol, 7655 u16 virtual_router, 7656 u32 adjacency_index, u16 ecmp_size, 7657 u32 new_adjacency_index, 7658 u16 new_ecmp_size) 7659 { 7660 MLXSW_REG_ZERO(raleu, payload); 7661 mlxsw_reg_raleu_protocol_set(payload, protocol); 7662 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router); 7663 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index); 7664 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size); 7665 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index); 7666 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size); 7667 } 7668 7669 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register 7670 * ---------------------------------------------------------------- 7671 * The RAUHTD register allows dumping entries from the Router Unicast Host 7672 * Table. For a given session an entry is dumped no more than one time. The 7673 * first RAUHTD access after reset is a new session. A session ends when the 7674 * num_rec response is smaller than num_rec request or for IPv4 when the 7675 * num_entries is smaller than 4. The clear activity affect the current session 7676 * or the last session if a new session has not started. 7677 */ 7678 #define MLXSW_REG_RAUHTD_ID 0x8018 7679 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20 7680 #define MLXSW_REG_RAUHTD_REC_LEN 0x20 7681 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32 7682 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \ 7683 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN) 7684 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4 7685 7686 MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN); 7687 7688 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0) 7689 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3) 7690 7691 /* reg_rauhtd_filter_fields 7692 * if a bit is '0' then the relevant field is ignored and dump is done 7693 * regardless of the field value 7694 * Bit0 - filter by activity: entry_a 7695 * Bit3 - filter by entry rip: entry_rif 7696 * Access: Index 7697 */ 7698 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8); 7699 7700 enum mlxsw_reg_rauhtd_op { 7701 MLXSW_REG_RAUHTD_OP_DUMP, 7702 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR, 7703 }; 7704 7705 /* reg_rauhtd_op 7706 * Access: OP 7707 */ 7708 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2); 7709 7710 /* reg_rauhtd_num_rec 7711 * At request: number of records requested 7712 * At response: number of records dumped 7713 * For IPv4, each record has 4 entries at request and up to 4 entries 7714 * at response 7715 * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM 7716 * Access: Index 7717 */ 7718 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8); 7719 7720 /* reg_rauhtd_entry_a 7721 * Dump only if activity has value of entry_a 7722 * Reserved if filter_fields bit0 is '0' 7723 * Access: Index 7724 */ 7725 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1); 7726 7727 enum mlxsw_reg_rauhtd_type { 7728 MLXSW_REG_RAUHTD_TYPE_IPV4, 7729 MLXSW_REG_RAUHTD_TYPE_IPV6, 7730 }; 7731 7732 /* reg_rauhtd_type 7733 * Dump only if record type is: 7734 * 0 - IPv4 7735 * 1 - IPv6 7736 * Access: Index 7737 */ 7738 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4); 7739 7740 /* reg_rauhtd_entry_rif 7741 * Dump only if RIF has value of entry_rif 7742 * Reserved if filter_fields bit3 is '0' 7743 * Access: Index 7744 */ 7745 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16); 7746 7747 static inline void mlxsw_reg_rauhtd_pack(char *payload, 7748 enum mlxsw_reg_rauhtd_type type) 7749 { 7750 MLXSW_REG_ZERO(rauhtd, payload); 7751 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A); 7752 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR); 7753 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM); 7754 mlxsw_reg_rauhtd_entry_a_set(payload, 1); 7755 mlxsw_reg_rauhtd_type_set(payload, type); 7756 } 7757 7758 /* reg_rauhtd_ipv4_rec_num_entries 7759 * Number of valid entries in this record: 7760 * 0 - 1 valid entry 7761 * 1 - 2 valid entries 7762 * 2 - 3 valid entries 7763 * 3 - 4 valid entries 7764 * Access: RO 7765 */ 7766 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries, 7767 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2, 7768 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 7769 7770 /* reg_rauhtd_rec_type 7771 * Record type. 7772 * 0 - IPv4 7773 * 1 - IPv6 7774 * Access: RO 7775 */ 7776 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2, 7777 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 7778 7779 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8 7780 7781 /* reg_rauhtd_ipv4_ent_a 7782 * Activity. Set for new entries. Set if a packet lookup has hit on the 7783 * specific entry. 7784 * Access: RO 7785 */ 7786 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 7787 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 7788 7789 /* reg_rauhtd_ipv4_ent_rif 7790 * Router interface. 7791 * Access: RO 7792 */ 7793 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 7794 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 7795 7796 /* reg_rauhtd_ipv4_ent_dip 7797 * Destination IPv4 address. 7798 * Access: RO 7799 */ 7800 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0, 7801 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false); 7802 7803 #define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20 7804 7805 /* reg_rauhtd_ipv6_ent_a 7806 * Activity. Set for new entries. Set if a packet lookup has hit on the 7807 * specific entry. 7808 * Access: RO 7809 */ 7810 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 7811 MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 7812 7813 /* reg_rauhtd_ipv6_ent_rif 7814 * Router interface. 7815 * Access: RO 7816 */ 7817 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 7818 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 7819 7820 /* reg_rauhtd_ipv6_ent_dip 7821 * Destination IPv6 address. 7822 * Access: RO 7823 */ 7824 MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 7825 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10); 7826 7827 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload, 7828 int ent_index, u16 *p_rif, 7829 u32 *p_dip) 7830 { 7831 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index); 7832 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index); 7833 } 7834 7835 static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload, 7836 int rec_index, u16 *p_rif, 7837 char *p_dip) 7838 { 7839 *p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index); 7840 mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip); 7841 } 7842 7843 /* RTDP - Routing Tunnel Decap Properties Register 7844 * ----------------------------------------------- 7845 * The RTDP register is used for configuring the tunnel decap properties of NVE 7846 * and IPinIP. 7847 */ 7848 #define MLXSW_REG_RTDP_ID 0x8020 7849 #define MLXSW_REG_RTDP_LEN 0x44 7850 7851 MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN); 7852 7853 enum mlxsw_reg_rtdp_type { 7854 MLXSW_REG_RTDP_TYPE_NVE, 7855 MLXSW_REG_RTDP_TYPE_IPIP, 7856 }; 7857 7858 /* reg_rtdp_type 7859 * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type. 7860 * Access: RW 7861 */ 7862 MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4); 7863 7864 /* reg_rtdp_tunnel_index 7865 * Index to the Decap entry. 7866 * For Spectrum, Index to KVD Linear. 7867 * Access: Index 7868 */ 7869 MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24); 7870 7871 /* reg_rtdp_egress_router_interface 7872 * Underlay egress router interface. 7873 * Valid range is from 0 to cap_max_router_interfaces - 1 7874 * Access: RW 7875 */ 7876 MLXSW_ITEM32(reg, rtdp, egress_router_interface, 0x40, 0, 16); 7877 7878 /* IPinIP */ 7879 7880 /* reg_rtdp_ipip_irif 7881 * Ingress Router Interface for the overlay router 7882 * Access: RW 7883 */ 7884 MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16); 7885 7886 enum mlxsw_reg_rtdp_ipip_sip_check { 7887 /* No sip checks. */ 7888 MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO, 7889 /* Filter packet if underlay is not IPv4 or if underlay SIP does not 7890 * equal ipv4_usip. 7891 */ 7892 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4, 7893 /* Filter packet if underlay is not IPv6 or if underlay SIP does not 7894 * equal ipv6_usip. 7895 */ 7896 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3, 7897 }; 7898 7899 /* reg_rtdp_ipip_sip_check 7900 * SIP check to perform. If decapsulation failed due to these configurations 7901 * then trap_id is IPIP_DECAP_ERROR. 7902 * Access: RW 7903 */ 7904 MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3); 7905 7906 /* If set, allow decapsulation of IPinIP (without GRE). */ 7907 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP BIT(0) 7908 /* If set, allow decapsulation of IPinGREinIP without a key. */ 7909 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE BIT(1) 7910 /* If set, allow decapsulation of IPinGREinIP with a key. */ 7911 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY BIT(2) 7912 7913 /* reg_rtdp_ipip_type_check 7914 * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to 7915 * these configurations then trap_id is IPIP_DECAP_ERROR. 7916 * Access: RW 7917 */ 7918 MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3); 7919 7920 /* reg_rtdp_ipip_gre_key_check 7921 * Whether GRE key should be checked. When check is enabled: 7922 * - A packet received as IPinIP (without GRE) will always pass. 7923 * - A packet received as IPinGREinIP without a key will not pass the check. 7924 * - A packet received as IPinGREinIP with a key will pass the check only if the 7925 * key in the packet is equal to expected_gre_key. 7926 * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR. 7927 * Access: RW 7928 */ 7929 MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1); 7930 7931 /* reg_rtdp_ipip_ipv4_usip 7932 * Underlay IPv4 address for ipv4 source address check. 7933 * Reserved when sip_check is not '1'. 7934 * Access: RW 7935 */ 7936 MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32); 7937 7938 /* reg_rtdp_ipip_ipv6_usip_ptr 7939 * This field is valid when sip_check is "sipv6 check explicitly". This is a 7940 * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index 7941 * is to the KVD linear. 7942 * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6. 7943 * Access: RW 7944 */ 7945 MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24); 7946 7947 /* reg_rtdp_ipip_expected_gre_key 7948 * GRE key for checking. 7949 * Reserved when gre_key_check is '0'. 7950 * Access: RW 7951 */ 7952 MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32); 7953 7954 static inline void mlxsw_reg_rtdp_pack(char *payload, 7955 enum mlxsw_reg_rtdp_type type, 7956 u32 tunnel_index) 7957 { 7958 MLXSW_REG_ZERO(rtdp, payload); 7959 mlxsw_reg_rtdp_type_set(payload, type); 7960 mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index); 7961 } 7962 7963 static inline void 7964 mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif, 7965 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 7966 unsigned int type_check, bool gre_key_check, 7967 u32 ipv4_usip, u32 expected_gre_key) 7968 { 7969 mlxsw_reg_rtdp_ipip_irif_set(payload, irif); 7970 mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check); 7971 mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check); 7972 mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check); 7973 mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip); 7974 mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key); 7975 } 7976 7977 /* RIGR-V2 - Router Interface Group Register Version 2 7978 * --------------------------------------------------- 7979 * The RIGR_V2 register is used to add, remove and query egress interface list 7980 * of a multicast forwarding entry. 7981 */ 7982 #define MLXSW_REG_RIGR2_ID 0x8023 7983 #define MLXSW_REG_RIGR2_LEN 0xB0 7984 7985 #define MLXSW_REG_RIGR2_MAX_ERIFS 32 7986 7987 MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN); 7988 7989 /* reg_rigr2_rigr_index 7990 * KVD Linear index. 7991 * Access: Index 7992 */ 7993 MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24); 7994 7995 /* reg_rigr2_vnext 7996 * Next RIGR Index is valid. 7997 * Access: RW 7998 */ 7999 MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1); 8000 8001 /* reg_rigr2_next_rigr_index 8002 * Next RIGR Index. The index is to the KVD linear. 8003 * Reserved when vnxet = '0'. 8004 * Access: RW 8005 */ 8006 MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24); 8007 8008 /* reg_rigr2_vrmid 8009 * RMID Index is valid. 8010 * Access: RW 8011 */ 8012 MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1); 8013 8014 /* reg_rigr2_rmid_index 8015 * RMID Index. 8016 * Range 0 .. max_mid - 1 8017 * Reserved when vrmid = '0'. 8018 * The index is to the Port Group Table (PGT) 8019 * Access: RW 8020 */ 8021 MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16); 8022 8023 /* reg_rigr2_erif_entry_v 8024 * Egress Router Interface is valid. 8025 * Note that low-entries must be set if high-entries are set. For 8026 * example: if erif_entry[2].v is set then erif_entry[1].v and 8027 * erif_entry[0].v must be set. 8028 * Index can be from 0 to cap_mc_erif_list_entries-1 8029 * Access: RW 8030 */ 8031 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false); 8032 8033 /* reg_rigr2_erif_entry_erif 8034 * Egress Router Interface. 8035 * Valid range is from 0 to cap_max_router_interfaces - 1 8036 * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1 8037 * Access: RW 8038 */ 8039 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false); 8040 8041 static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index, 8042 bool vnext, u32 next_rigr_index) 8043 { 8044 MLXSW_REG_ZERO(rigr2, payload); 8045 mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index); 8046 mlxsw_reg_rigr2_vnext_set(payload, vnext); 8047 mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index); 8048 mlxsw_reg_rigr2_vrmid_set(payload, 0); 8049 mlxsw_reg_rigr2_rmid_index_set(payload, 0); 8050 } 8051 8052 static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index, 8053 bool v, u16 erif) 8054 { 8055 mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v); 8056 mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif); 8057 } 8058 8059 /* RECR-V2 - Router ECMP Configuration Version 2 Register 8060 * ------------------------------------------------------ 8061 */ 8062 #define MLXSW_REG_RECR2_ID 0x8025 8063 #define MLXSW_REG_RECR2_LEN 0x38 8064 8065 MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN); 8066 8067 /* reg_recr2_pp 8068 * Per-port configuration 8069 * Access: Index 8070 */ 8071 MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1); 8072 8073 /* reg_recr2_sh 8074 * Symmetric hash 8075 * Access: RW 8076 */ 8077 MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1); 8078 8079 /* reg_recr2_seed 8080 * Seed 8081 * Access: RW 8082 */ 8083 MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32); 8084 8085 enum { 8086 /* Enable IPv4 fields if packet is not TCP and not UDP */ 8087 MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP = 3, 8088 /* Enable IPv4 fields if packet is TCP or UDP */ 8089 MLXSW_REG_RECR2_IPV4_EN_TCP_UDP = 4, 8090 /* Enable IPv6 fields if packet is not TCP and not UDP */ 8091 MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP = 5, 8092 /* Enable IPv6 fields if packet is TCP or UDP */ 8093 MLXSW_REG_RECR2_IPV6_EN_TCP_UDP = 6, 8094 /* Enable TCP/UDP header fields if packet is IPv4 */ 8095 MLXSW_REG_RECR2_TCP_UDP_EN_IPV4 = 7, 8096 /* Enable TCP/UDP header fields if packet is IPv6 */ 8097 MLXSW_REG_RECR2_TCP_UDP_EN_IPV6 = 8, 8098 }; 8099 8100 /* reg_recr2_outer_header_enables 8101 * Bit mask where each bit enables a specific layer to be included in 8102 * the hash calculation. 8103 * Access: RW 8104 */ 8105 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1); 8106 8107 enum { 8108 /* IPv4 Source IP */ 8109 MLXSW_REG_RECR2_IPV4_SIP0 = 9, 8110 MLXSW_REG_RECR2_IPV4_SIP3 = 12, 8111 /* IPv4 Destination IP */ 8112 MLXSW_REG_RECR2_IPV4_DIP0 = 13, 8113 MLXSW_REG_RECR2_IPV4_DIP3 = 16, 8114 /* IP Protocol */ 8115 MLXSW_REG_RECR2_IPV4_PROTOCOL = 17, 8116 /* IPv6 Source IP */ 8117 MLXSW_REG_RECR2_IPV6_SIP0_7 = 21, 8118 MLXSW_REG_RECR2_IPV6_SIP8 = 29, 8119 MLXSW_REG_RECR2_IPV6_SIP15 = 36, 8120 /* IPv6 Destination IP */ 8121 MLXSW_REG_RECR2_IPV6_DIP0_7 = 37, 8122 MLXSW_REG_RECR2_IPV6_DIP8 = 45, 8123 MLXSW_REG_RECR2_IPV6_DIP15 = 52, 8124 /* IPv6 Next Header */ 8125 MLXSW_REG_RECR2_IPV6_NEXT_HEADER = 53, 8126 /* IPv6 Flow Label */ 8127 MLXSW_REG_RECR2_IPV6_FLOW_LABEL = 57, 8128 /* TCP/UDP Source Port */ 8129 MLXSW_REG_RECR2_TCP_UDP_SPORT = 74, 8130 /* TCP/UDP Destination Port */ 8131 MLXSW_REG_RECR2_TCP_UDP_DPORT = 75, 8132 }; 8133 8134 /* reg_recr2_outer_header_fields_enable 8135 * Packet fields to enable for ECMP hash subject to outer_header_enable. 8136 * Access: RW 8137 */ 8138 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1); 8139 8140 static inline void mlxsw_reg_recr2_ipv4_sip_enable(char *payload) 8141 { 8142 int i; 8143 8144 for (i = MLXSW_REG_RECR2_IPV4_SIP0; i <= MLXSW_REG_RECR2_IPV4_SIP3; i++) 8145 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 8146 true); 8147 } 8148 8149 static inline void mlxsw_reg_recr2_ipv4_dip_enable(char *payload) 8150 { 8151 int i; 8152 8153 for (i = MLXSW_REG_RECR2_IPV4_DIP0; i <= MLXSW_REG_RECR2_IPV4_DIP3; i++) 8154 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 8155 true); 8156 } 8157 8158 static inline void mlxsw_reg_recr2_ipv6_sip_enable(char *payload) 8159 { 8160 int i = MLXSW_REG_RECR2_IPV6_SIP0_7; 8161 8162 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true); 8163 8164 i = MLXSW_REG_RECR2_IPV6_SIP8; 8165 for (; i <= MLXSW_REG_RECR2_IPV6_SIP15; i++) 8166 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 8167 true); 8168 } 8169 8170 static inline void mlxsw_reg_recr2_ipv6_dip_enable(char *payload) 8171 { 8172 int i = MLXSW_REG_RECR2_IPV6_DIP0_7; 8173 8174 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true); 8175 8176 i = MLXSW_REG_RECR2_IPV6_DIP8; 8177 for (; i <= MLXSW_REG_RECR2_IPV6_DIP15; i++) 8178 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 8179 true); 8180 } 8181 8182 static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed) 8183 { 8184 MLXSW_REG_ZERO(recr2, payload); 8185 mlxsw_reg_recr2_pp_set(payload, false); 8186 mlxsw_reg_recr2_sh_set(payload, true); 8187 mlxsw_reg_recr2_seed_set(payload, seed); 8188 } 8189 8190 /* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register 8191 * -------------------------------------------------------------- 8192 * The RMFT_V2 register is used to configure and query the multicast table. 8193 */ 8194 #define MLXSW_REG_RMFT2_ID 0x8027 8195 #define MLXSW_REG_RMFT2_LEN 0x174 8196 8197 MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN); 8198 8199 /* reg_rmft2_v 8200 * Valid 8201 * Access: RW 8202 */ 8203 MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1); 8204 8205 enum mlxsw_reg_rmft2_type { 8206 MLXSW_REG_RMFT2_TYPE_IPV4, 8207 MLXSW_REG_RMFT2_TYPE_IPV6 8208 }; 8209 8210 /* reg_rmft2_type 8211 * Access: Index 8212 */ 8213 MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2); 8214 8215 enum mlxsw_sp_reg_rmft2_op { 8216 /* For Write: 8217 * Write operation. Used to write a new entry to the table. All RW 8218 * fields are relevant for new entry. Activity bit is set for new 8219 * entries - Note write with v (Valid) 0 will delete the entry. 8220 * For Query: 8221 * Read operation 8222 */ 8223 MLXSW_REG_RMFT2_OP_READ_WRITE, 8224 }; 8225 8226 /* reg_rmft2_op 8227 * Operation. 8228 * Access: OP 8229 */ 8230 MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2); 8231 8232 /* reg_rmft2_a 8233 * Activity. Set for new entries. Set if a packet lookup has hit on the specific 8234 * entry. 8235 * Access: RO 8236 */ 8237 MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1); 8238 8239 /* reg_rmft2_offset 8240 * Offset within the multicast forwarding table to write to. 8241 * Access: Index 8242 */ 8243 MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16); 8244 8245 /* reg_rmft2_virtual_router 8246 * Virtual Router ID. Range from 0..cap_max_virtual_routers-1 8247 * Access: RW 8248 */ 8249 MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16); 8250 8251 enum mlxsw_reg_rmft2_irif_mask { 8252 MLXSW_REG_RMFT2_IRIF_MASK_IGNORE, 8253 MLXSW_REG_RMFT2_IRIF_MASK_COMPARE 8254 }; 8255 8256 /* reg_rmft2_irif_mask 8257 * Ingress RIF mask. 8258 * Access: RW 8259 */ 8260 MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1); 8261 8262 /* reg_rmft2_irif 8263 * Ingress RIF index. 8264 * Access: RW 8265 */ 8266 MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16); 8267 8268 /* reg_rmft2_dip{4,6} 8269 * Destination IPv4/6 address 8270 * Access: RW 8271 */ 8272 MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16); 8273 MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32); 8274 8275 /* reg_rmft2_dip{4,6}_mask 8276 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 8277 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 8278 * Access: RW 8279 */ 8280 MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16); 8281 MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32); 8282 8283 /* reg_rmft2_sip{4,6} 8284 * Source IPv4/6 address 8285 * Access: RW 8286 */ 8287 MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16); 8288 MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32); 8289 8290 /* reg_rmft2_sip{4,6}_mask 8291 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 8292 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 8293 * Access: RW 8294 */ 8295 MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16); 8296 MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32); 8297 8298 /* reg_rmft2_flexible_action_set 8299 * ACL action set. The only supported action types in this field and in any 8300 * action-set pointed from here are as follows: 8301 * 00h: ACTION_NULL 8302 * 01h: ACTION_MAC_TTL, only TTL configuration is supported. 8303 * 03h: ACTION_TRAP 8304 * 06h: ACTION_QOS 8305 * 08h: ACTION_POLICING_MONITORING 8306 * 10h: ACTION_ROUTER_MC 8307 * Access: RW 8308 */ 8309 MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80, 8310 MLXSW_REG_FLEX_ACTION_SET_LEN); 8311 8312 static inline void 8313 mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset, 8314 u16 virtual_router, 8315 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 8316 const char *flex_action_set) 8317 { 8318 MLXSW_REG_ZERO(rmft2, payload); 8319 mlxsw_reg_rmft2_v_set(payload, v); 8320 mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE); 8321 mlxsw_reg_rmft2_offset_set(payload, offset); 8322 mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router); 8323 mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask); 8324 mlxsw_reg_rmft2_irif_set(payload, irif); 8325 if (flex_action_set) 8326 mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload, 8327 flex_action_set); 8328 } 8329 8330 static inline void 8331 mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router, 8332 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 8333 u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask, 8334 const char *flexible_action_set) 8335 { 8336 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 8337 irif_mask, irif, flexible_action_set); 8338 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4); 8339 mlxsw_reg_rmft2_dip4_set(payload, dip4); 8340 mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask); 8341 mlxsw_reg_rmft2_sip4_set(payload, sip4); 8342 mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask); 8343 } 8344 8345 static inline void 8346 mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router, 8347 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 8348 struct in6_addr dip6, struct in6_addr dip6_mask, 8349 struct in6_addr sip6, struct in6_addr sip6_mask, 8350 const char *flexible_action_set) 8351 { 8352 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 8353 irif_mask, irif, flexible_action_set); 8354 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6); 8355 mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6); 8356 mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask); 8357 mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6); 8358 mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask); 8359 } 8360 8361 /* Note that XRALXX register position violates the rule of ordering register 8362 * definition by the ID. However, XRALXX pack helpers are using RALXX pack 8363 * helpers, RALXX registers have higher IDs. 8364 */ 8365 8366 /* XRALTA - XM Router Algorithmic LPM Tree Allocation Register 8367 * ----------------------------------------------------------- 8368 * The XRALTA is used to allocate the XLT LPM trees. 8369 * 8370 * This register embeds original RALTA register. 8371 */ 8372 #define MLXSW_REG_XRALTA_ID 0x7811 8373 #define MLXSW_REG_XRALTA_LEN 0x08 8374 #define MLXSW_REG_XRALTA_RALTA_OFFSET 0x04 8375 8376 MLXSW_REG_DEFINE(xralta, MLXSW_REG_XRALTA_ID, MLXSW_REG_XRALTA_LEN); 8377 8378 static inline void mlxsw_reg_xralta_pack(char *payload, bool alloc, 8379 enum mlxsw_reg_ralxx_protocol protocol, 8380 u8 tree_id) 8381 { 8382 char *ralta_payload = payload + MLXSW_REG_XRALTA_RALTA_OFFSET; 8383 8384 MLXSW_REG_ZERO(xralta, payload); 8385 mlxsw_reg_ralta_pack(ralta_payload, alloc, protocol, tree_id); 8386 } 8387 8388 /* XRALST - XM Router Algorithmic LPM Structure Tree Register 8389 * ---------------------------------------------------------- 8390 * The XRALST is used to set and query the structure of an XLT LPM tree. 8391 * 8392 * This register embeds original RALST register. 8393 */ 8394 #define MLXSW_REG_XRALST_ID 0x7812 8395 #define MLXSW_REG_XRALST_LEN 0x108 8396 #define MLXSW_REG_XRALST_RALST_OFFSET 0x04 8397 8398 MLXSW_REG_DEFINE(xralst, MLXSW_REG_XRALST_ID, MLXSW_REG_XRALST_LEN); 8399 8400 static inline void mlxsw_reg_xralst_pack(char *payload, u8 root_bin, u8 tree_id) 8401 { 8402 char *ralst_payload = payload + MLXSW_REG_XRALST_RALST_OFFSET; 8403 8404 MLXSW_REG_ZERO(xralst, payload); 8405 mlxsw_reg_ralst_pack(ralst_payload, root_bin, tree_id); 8406 } 8407 8408 static inline void mlxsw_reg_xralst_bin_pack(char *payload, u8 bin_number, 8409 u8 left_child_bin, 8410 u8 right_child_bin) 8411 { 8412 char *ralst_payload = payload + MLXSW_REG_XRALST_RALST_OFFSET; 8413 8414 mlxsw_reg_ralst_bin_pack(ralst_payload, bin_number, left_child_bin, 8415 right_child_bin); 8416 } 8417 8418 /* XRALTB - XM Router Algorithmic LPM Tree Binding Register 8419 * -------------------------------------------------------- 8420 * The XRALTB register is used to bind virtual router and protocol 8421 * to an allocated LPM tree. 8422 * 8423 * This register embeds original RALTB register. 8424 */ 8425 #define MLXSW_REG_XRALTB_ID 0x7813 8426 #define MLXSW_REG_XRALTB_LEN 0x08 8427 #define MLXSW_REG_XRALTB_RALTB_OFFSET 0x04 8428 8429 MLXSW_REG_DEFINE(xraltb, MLXSW_REG_XRALTB_ID, MLXSW_REG_XRALTB_LEN); 8430 8431 static inline void mlxsw_reg_xraltb_pack(char *payload, u16 virtual_router, 8432 enum mlxsw_reg_ralxx_protocol protocol, 8433 u8 tree_id) 8434 { 8435 char *raltb_payload = payload + MLXSW_REG_XRALTB_RALTB_OFFSET; 8436 8437 MLXSW_REG_ZERO(xraltb, payload); 8438 mlxsw_reg_raltb_pack(raltb_payload, virtual_router, protocol, tree_id); 8439 } 8440 8441 /* MFCR - Management Fan Control Register 8442 * -------------------------------------- 8443 * This register controls the settings of the Fan Speed PWM mechanism. 8444 */ 8445 #define MLXSW_REG_MFCR_ID 0x9001 8446 #define MLXSW_REG_MFCR_LEN 0x08 8447 8448 MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN); 8449 8450 enum mlxsw_reg_mfcr_pwm_frequency { 8451 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00, 8452 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01, 8453 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02, 8454 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40, 8455 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41, 8456 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42, 8457 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43, 8458 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44, 8459 }; 8460 8461 /* reg_mfcr_pwm_frequency 8462 * Controls the frequency of the PWM signal. 8463 * Access: RW 8464 */ 8465 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7); 8466 8467 #define MLXSW_MFCR_TACHOS_MAX 10 8468 8469 /* reg_mfcr_tacho_active 8470 * Indicates which of the tachometer is active (bit per tachometer). 8471 * Access: RO 8472 */ 8473 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX); 8474 8475 #define MLXSW_MFCR_PWMS_MAX 5 8476 8477 /* reg_mfcr_pwm_active 8478 * Indicates which of the PWM control is active (bit per PWM). 8479 * Access: RO 8480 */ 8481 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX); 8482 8483 static inline void 8484 mlxsw_reg_mfcr_pack(char *payload, 8485 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency) 8486 { 8487 MLXSW_REG_ZERO(mfcr, payload); 8488 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency); 8489 } 8490 8491 static inline void 8492 mlxsw_reg_mfcr_unpack(char *payload, 8493 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency, 8494 u16 *p_tacho_active, u8 *p_pwm_active) 8495 { 8496 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload); 8497 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload); 8498 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload); 8499 } 8500 8501 /* MFSC - Management Fan Speed Control Register 8502 * -------------------------------------------- 8503 * This register controls the settings of the Fan Speed PWM mechanism. 8504 */ 8505 #define MLXSW_REG_MFSC_ID 0x9002 8506 #define MLXSW_REG_MFSC_LEN 0x08 8507 8508 MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN); 8509 8510 /* reg_mfsc_pwm 8511 * Fan pwm to control / monitor. 8512 * Access: Index 8513 */ 8514 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3); 8515 8516 /* reg_mfsc_pwm_duty_cycle 8517 * Controls the duty cycle of the PWM. Value range from 0..255 to 8518 * represent duty cycle of 0%...100%. 8519 * Access: RW 8520 */ 8521 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8); 8522 8523 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm, 8524 u8 pwm_duty_cycle) 8525 { 8526 MLXSW_REG_ZERO(mfsc, payload); 8527 mlxsw_reg_mfsc_pwm_set(payload, pwm); 8528 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle); 8529 } 8530 8531 /* MFSM - Management Fan Speed Measurement 8532 * --------------------------------------- 8533 * This register controls the settings of the Tacho measurements and 8534 * enables reading the Tachometer measurements. 8535 */ 8536 #define MLXSW_REG_MFSM_ID 0x9003 8537 #define MLXSW_REG_MFSM_LEN 0x08 8538 8539 MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN); 8540 8541 /* reg_mfsm_tacho 8542 * Fan tachometer index. 8543 * Access: Index 8544 */ 8545 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4); 8546 8547 /* reg_mfsm_rpm 8548 * Fan speed (round per minute). 8549 * Access: RO 8550 */ 8551 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16); 8552 8553 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho) 8554 { 8555 MLXSW_REG_ZERO(mfsm, payload); 8556 mlxsw_reg_mfsm_tacho_set(payload, tacho); 8557 } 8558 8559 /* MFSL - Management Fan Speed Limit Register 8560 * ------------------------------------------ 8561 * The Fan Speed Limit register is used to configure the fan speed 8562 * event / interrupt notification mechanism. Fan speed threshold are 8563 * defined for both under-speed and over-speed. 8564 */ 8565 #define MLXSW_REG_MFSL_ID 0x9004 8566 #define MLXSW_REG_MFSL_LEN 0x0C 8567 8568 MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN); 8569 8570 /* reg_mfsl_tacho 8571 * Fan tachometer index. 8572 * Access: Index 8573 */ 8574 MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4); 8575 8576 /* reg_mfsl_tach_min 8577 * Tachometer minimum value (minimum RPM). 8578 * Access: RW 8579 */ 8580 MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16); 8581 8582 /* reg_mfsl_tach_max 8583 * Tachometer maximum value (maximum RPM). 8584 * Access: RW 8585 */ 8586 MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16); 8587 8588 static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho, 8589 u16 tach_min, u16 tach_max) 8590 { 8591 MLXSW_REG_ZERO(mfsl, payload); 8592 mlxsw_reg_mfsl_tacho_set(payload, tacho); 8593 mlxsw_reg_mfsl_tach_min_set(payload, tach_min); 8594 mlxsw_reg_mfsl_tach_max_set(payload, tach_max); 8595 } 8596 8597 static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho, 8598 u16 *p_tach_min, u16 *p_tach_max) 8599 { 8600 if (p_tach_min) 8601 *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload); 8602 8603 if (p_tach_max) 8604 *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload); 8605 } 8606 8607 /* FORE - Fan Out of Range Event Register 8608 * -------------------------------------- 8609 * This register reports the status of the controlled fans compared to the 8610 * range defined by the MFSL register. 8611 */ 8612 #define MLXSW_REG_FORE_ID 0x9007 8613 #define MLXSW_REG_FORE_LEN 0x0C 8614 8615 MLXSW_REG_DEFINE(fore, MLXSW_REG_FORE_ID, MLXSW_REG_FORE_LEN); 8616 8617 /* fan_under_limit 8618 * Fan speed is below the low limit defined in MFSL register. Each bit relates 8619 * to a single tachometer and indicates the specific tachometer reading is 8620 * below the threshold. 8621 * Access: RO 8622 */ 8623 MLXSW_ITEM32(reg, fore, fan_under_limit, 0x00, 16, 10); 8624 8625 static inline void mlxsw_reg_fore_unpack(char *payload, u8 tacho, 8626 bool *fault) 8627 { 8628 u16 limit; 8629 8630 if (fault) { 8631 limit = mlxsw_reg_fore_fan_under_limit_get(payload); 8632 *fault = limit & BIT(tacho); 8633 } 8634 } 8635 8636 /* MTCAP - Management Temperature Capabilities 8637 * ------------------------------------------- 8638 * This register exposes the capabilities of the device and 8639 * system temperature sensing. 8640 */ 8641 #define MLXSW_REG_MTCAP_ID 0x9009 8642 #define MLXSW_REG_MTCAP_LEN 0x08 8643 8644 MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN); 8645 8646 /* reg_mtcap_sensor_count 8647 * Number of sensors supported by the device. 8648 * This includes the QSFP module sensors (if exists in the QSFP module). 8649 * Access: RO 8650 */ 8651 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7); 8652 8653 /* MTMP - Management Temperature 8654 * ----------------------------- 8655 * This register controls the settings of the temperature measurements 8656 * and enables reading the temperature measurements. Note that temperature 8657 * is in 0.125 degrees Celsius. 8658 */ 8659 #define MLXSW_REG_MTMP_ID 0x900A 8660 #define MLXSW_REG_MTMP_LEN 0x20 8661 8662 MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN); 8663 8664 #define MLXSW_REG_MTMP_MODULE_INDEX_MIN 64 8665 #define MLXSW_REG_MTMP_GBOX_INDEX_MIN 256 8666 /* reg_mtmp_sensor_index 8667 * Sensors index to access. 8668 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially 8669 * (module 0 is mapped to sensor_index 64). 8670 * Access: Index 8671 */ 8672 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 12); 8673 8674 /* Convert to milli degrees Celsius */ 8675 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) ({ typeof(val) v_ = (val); \ 8676 ((v_) >= 0) ? ((v_) * 125) : \ 8677 ((s16)((GENMASK(15, 0) + (v_) + 1) \ 8678 * 125)); }) 8679 8680 /* reg_mtmp_temperature 8681 * Temperature reading from the sensor. Reading is in 0.125 Celsius 8682 * degrees units. 8683 * Access: RO 8684 */ 8685 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16); 8686 8687 /* reg_mtmp_mte 8688 * Max Temperature Enable - enables measuring the max temperature on a sensor. 8689 * Access: RW 8690 */ 8691 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1); 8692 8693 /* reg_mtmp_mtr 8694 * Max Temperature Reset - clears the value of the max temperature register. 8695 * Access: WO 8696 */ 8697 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1); 8698 8699 /* reg_mtmp_max_temperature 8700 * The highest measured temperature from the sensor. 8701 * When the bit mte is cleared, the field max_temperature is reserved. 8702 * Access: RO 8703 */ 8704 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16); 8705 8706 /* reg_mtmp_tee 8707 * Temperature Event Enable. 8708 * 0 - Do not generate event 8709 * 1 - Generate event 8710 * 2 - Generate single event 8711 * Access: RW 8712 */ 8713 8714 enum mlxsw_reg_mtmp_tee { 8715 MLXSW_REG_MTMP_TEE_NO_EVENT, 8716 MLXSW_REG_MTMP_TEE_GENERATE_EVENT, 8717 MLXSW_REG_MTMP_TEE_GENERATE_SINGLE_EVENT, 8718 }; 8719 8720 MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2); 8721 8722 #define MLXSW_REG_MTMP_THRESH_HI 0x348 /* 105 Celsius */ 8723 8724 /* reg_mtmp_temperature_threshold_hi 8725 * High threshold for Temperature Warning Event. In 0.125 Celsius. 8726 * Access: RW 8727 */ 8728 MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16); 8729 8730 #define MLXSW_REG_MTMP_HYSTERESIS_TEMP 0x28 /* 5 Celsius */ 8731 /* reg_mtmp_temperature_threshold_lo 8732 * Low threshold for Temperature Warning Event. In 0.125 Celsius. 8733 * Access: RW 8734 */ 8735 MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16); 8736 8737 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8 8738 8739 /* reg_mtmp_sensor_name 8740 * Sensor Name 8741 * Access: RO 8742 */ 8743 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE); 8744 8745 static inline void mlxsw_reg_mtmp_pack(char *payload, u16 sensor_index, 8746 bool max_temp_enable, 8747 bool max_temp_reset) 8748 { 8749 MLXSW_REG_ZERO(mtmp, payload); 8750 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index); 8751 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable); 8752 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset); 8753 mlxsw_reg_mtmp_temperature_threshold_hi_set(payload, 8754 MLXSW_REG_MTMP_THRESH_HI); 8755 } 8756 8757 static inline void mlxsw_reg_mtmp_unpack(char *payload, int *p_temp, 8758 int *p_max_temp, char *sensor_name) 8759 { 8760 s16 temp; 8761 8762 if (p_temp) { 8763 temp = mlxsw_reg_mtmp_temperature_get(payload); 8764 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 8765 } 8766 if (p_max_temp) { 8767 temp = mlxsw_reg_mtmp_max_temperature_get(payload); 8768 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 8769 } 8770 if (sensor_name) 8771 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name); 8772 } 8773 8774 /* MTWE - Management Temperature Warning Event 8775 * ------------------------------------------- 8776 * This register is used for over temperature warning. 8777 */ 8778 #define MLXSW_REG_MTWE_ID 0x900B 8779 #define MLXSW_REG_MTWE_LEN 0x10 8780 8781 MLXSW_REG_DEFINE(mtwe, MLXSW_REG_MTWE_ID, MLXSW_REG_MTWE_LEN); 8782 8783 /* reg_mtwe_sensor_warning 8784 * Bit vector indicating which of the sensor reading is above threshold. 8785 * Address 00h bit31 is sensor_warning[127]. 8786 * Address 0Ch bit0 is sensor_warning[0]. 8787 * Access: RO 8788 */ 8789 MLXSW_ITEM_BIT_ARRAY(reg, mtwe, sensor_warning, 0x0, 0x10, 1); 8790 8791 /* MTBR - Management Temperature Bulk Register 8792 * ------------------------------------------- 8793 * This register is used for bulk temperature reading. 8794 */ 8795 #define MLXSW_REG_MTBR_ID 0x900F 8796 #define MLXSW_REG_MTBR_BASE_LEN 0x10 /* base length, without records */ 8797 #define MLXSW_REG_MTBR_REC_LEN 0x04 /* record length */ 8798 #define MLXSW_REG_MTBR_REC_MAX_COUNT 47 /* firmware limitation */ 8799 #define MLXSW_REG_MTBR_LEN (MLXSW_REG_MTBR_BASE_LEN + \ 8800 MLXSW_REG_MTBR_REC_LEN * \ 8801 MLXSW_REG_MTBR_REC_MAX_COUNT) 8802 8803 MLXSW_REG_DEFINE(mtbr, MLXSW_REG_MTBR_ID, MLXSW_REG_MTBR_LEN); 8804 8805 /* reg_mtbr_base_sensor_index 8806 * Base sensors index to access (0 - ASIC sensor, 1-63 - ambient sensors, 8807 * 64-127 are mapped to the SFP+/QSFP modules sequentially). 8808 * Access: Index 8809 */ 8810 MLXSW_ITEM32(reg, mtbr, base_sensor_index, 0x00, 0, 12); 8811 8812 /* reg_mtbr_num_rec 8813 * Request: Number of records to read 8814 * Response: Number of records read 8815 * See above description for more details. 8816 * Range 1..255 8817 * Access: RW 8818 */ 8819 MLXSW_ITEM32(reg, mtbr, num_rec, 0x04, 0, 8); 8820 8821 /* reg_mtbr_rec_max_temp 8822 * The highest measured temperature from the sensor. 8823 * When the bit mte is cleared, the field max_temperature is reserved. 8824 * Access: RO 8825 */ 8826 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_max_temp, MLXSW_REG_MTBR_BASE_LEN, 16, 8827 16, MLXSW_REG_MTBR_REC_LEN, 0x00, false); 8828 8829 /* reg_mtbr_rec_temp 8830 * Temperature reading from the sensor. Reading is in 0..125 Celsius 8831 * degrees units. 8832 * Access: RO 8833 */ 8834 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_temp, MLXSW_REG_MTBR_BASE_LEN, 0, 16, 8835 MLXSW_REG_MTBR_REC_LEN, 0x00, false); 8836 8837 static inline void mlxsw_reg_mtbr_pack(char *payload, u16 base_sensor_index, 8838 u8 num_rec) 8839 { 8840 MLXSW_REG_ZERO(mtbr, payload); 8841 mlxsw_reg_mtbr_base_sensor_index_set(payload, base_sensor_index); 8842 mlxsw_reg_mtbr_num_rec_set(payload, num_rec); 8843 } 8844 8845 /* Error codes from temperatute reading */ 8846 enum mlxsw_reg_mtbr_temp_status { 8847 MLXSW_REG_MTBR_NO_CONN = 0x8000, 8848 MLXSW_REG_MTBR_NO_TEMP_SENS = 0x8001, 8849 MLXSW_REG_MTBR_INDEX_NA = 0x8002, 8850 MLXSW_REG_MTBR_BAD_SENS_INFO = 0x8003, 8851 }; 8852 8853 /* Base index for reading modules temperature */ 8854 #define MLXSW_REG_MTBR_BASE_MODULE_INDEX 64 8855 8856 static inline void mlxsw_reg_mtbr_temp_unpack(char *payload, int rec_ind, 8857 u16 *p_temp, u16 *p_max_temp) 8858 { 8859 if (p_temp) 8860 *p_temp = mlxsw_reg_mtbr_rec_temp_get(payload, rec_ind); 8861 if (p_max_temp) 8862 *p_max_temp = mlxsw_reg_mtbr_rec_max_temp_get(payload, rec_ind); 8863 } 8864 8865 /* MCIA - Management Cable Info Access 8866 * ----------------------------------- 8867 * MCIA register is used to access the SFP+ and QSFP connector's EPROM. 8868 */ 8869 8870 #define MLXSW_REG_MCIA_ID 0x9014 8871 #define MLXSW_REG_MCIA_LEN 0x40 8872 8873 MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN); 8874 8875 /* reg_mcia_l 8876 * Lock bit. Setting this bit will lock the access to the specific 8877 * cable. Used for updating a full page in a cable EPROM. Any access 8878 * other then subsequence writes will fail while the port is locked. 8879 * Access: RW 8880 */ 8881 MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1); 8882 8883 /* reg_mcia_module 8884 * Module number. 8885 * Access: Index 8886 */ 8887 MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8); 8888 8889 /* reg_mcia_status 8890 * Module status. 8891 * Access: RO 8892 */ 8893 MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8); 8894 8895 /* reg_mcia_i2c_device_address 8896 * I2C device address. 8897 * Access: RW 8898 */ 8899 MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8); 8900 8901 /* reg_mcia_page_number 8902 * Page number. 8903 * Access: RW 8904 */ 8905 MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8); 8906 8907 /* reg_mcia_device_address 8908 * Device address. 8909 * Access: RW 8910 */ 8911 MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16); 8912 8913 /* reg_mcia_size 8914 * Number of bytes to read/write (up to 48 bytes). 8915 * Access: RW 8916 */ 8917 MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16); 8918 8919 #define MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH 256 8920 #define MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH 128 8921 #define MLXSW_REG_MCIA_EEPROM_SIZE 48 8922 #define MLXSW_REG_MCIA_I2C_ADDR_LOW 0x50 8923 #define MLXSW_REG_MCIA_I2C_ADDR_HIGH 0x51 8924 #define MLXSW_REG_MCIA_PAGE0_LO_OFF 0xa0 8925 #define MLXSW_REG_MCIA_TH_ITEM_SIZE 2 8926 #define MLXSW_REG_MCIA_TH_PAGE_NUM 3 8927 #define MLXSW_REG_MCIA_TH_PAGE_CMIS_NUM 2 8928 #define MLXSW_REG_MCIA_PAGE0_LO 0 8929 #define MLXSW_REG_MCIA_TH_PAGE_OFF 0x80 8930 #define MLXSW_REG_MCIA_EEPROM_CMIS_FLAT_MEMORY BIT(7) 8931 8932 enum mlxsw_reg_mcia_eeprom_module_info_rev_id { 8933 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00, 8934 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01, 8935 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03, 8936 }; 8937 8938 enum mlxsw_reg_mcia_eeprom_module_info_id { 8939 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_SFP = 0x03, 8940 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP = 0x0C, 8941 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D, 8942 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11, 8943 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_DD = 0x18, 8944 }; 8945 8946 enum mlxsw_reg_mcia_eeprom_module_info { 8947 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID, 8948 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID, 8949 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_TYPE_ID, 8950 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_SIZE, 8951 }; 8952 8953 /* reg_mcia_eeprom 8954 * Bytes to read/write. 8955 * Access: RW 8956 */ 8957 MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_REG_MCIA_EEPROM_SIZE); 8958 8959 /* This is used to access the optional upper pages (1-3) in the QSFP+ 8960 * memory map. Page 1 is available on offset 256 through 383, page 2 - 8961 * on offset 384 through 511, page 3 - on offset 512 through 639. 8962 */ 8963 #define MLXSW_REG_MCIA_PAGE_GET(off) (((off) - \ 8964 MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH) / \ 8965 MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH + 1) 8966 8967 static inline void mlxsw_reg_mcia_pack(char *payload, u8 module, u8 lock, 8968 u8 page_number, u16 device_addr, 8969 u8 size, u8 i2c_device_addr) 8970 { 8971 MLXSW_REG_ZERO(mcia, payload); 8972 mlxsw_reg_mcia_module_set(payload, module); 8973 mlxsw_reg_mcia_l_set(payload, lock); 8974 mlxsw_reg_mcia_page_number_set(payload, page_number); 8975 mlxsw_reg_mcia_device_address_set(payload, device_addr); 8976 mlxsw_reg_mcia_size_set(payload, size); 8977 mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr); 8978 } 8979 8980 /* MPAT - Monitoring Port Analyzer Table 8981 * ------------------------------------- 8982 * MPAT Register is used to query and configure the Switch PortAnalyzer Table. 8983 * For an enabled analyzer, all fields except e (enable) cannot be modified. 8984 */ 8985 #define MLXSW_REG_MPAT_ID 0x901A 8986 #define MLXSW_REG_MPAT_LEN 0x78 8987 8988 MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN); 8989 8990 /* reg_mpat_pa_id 8991 * Port Analyzer ID. 8992 * Access: Index 8993 */ 8994 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4); 8995 8996 /* reg_mpat_session_id 8997 * Mirror Session ID. 8998 * Used for MIRROR_SESSION<i> trap. 8999 * Access: RW 9000 */ 9001 MLXSW_ITEM32(reg, mpat, session_id, 0x00, 24, 4); 9002 9003 /* reg_mpat_system_port 9004 * A unique port identifier for the final destination of the packet. 9005 * Access: RW 9006 */ 9007 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16); 9008 9009 /* reg_mpat_e 9010 * Enable. Indicating the Port Analyzer is enabled. 9011 * Access: RW 9012 */ 9013 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1); 9014 9015 /* reg_mpat_qos 9016 * Quality Of Service Mode. 9017 * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation 9018 * PCP, DEI, DSCP or VL) are configured. 9019 * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the 9020 * same as in the original packet that has triggered the mirroring. For 9021 * SPAN also the pcp,dei are maintained. 9022 * Access: RW 9023 */ 9024 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1); 9025 9026 /* reg_mpat_be 9027 * Best effort mode. Indicates mirroring traffic should not cause packet 9028 * drop or back pressure, but will discard the mirrored packets. Mirrored 9029 * packets will be forwarded on a best effort manner. 9030 * 0: Do not discard mirrored packets 9031 * 1: Discard mirrored packets if causing congestion 9032 * Access: RW 9033 */ 9034 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1); 9035 9036 enum mlxsw_reg_mpat_span_type { 9037 /* Local SPAN Ethernet. 9038 * The original packet is not encapsulated. 9039 */ 9040 MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0, 9041 9042 /* Remote SPAN Ethernet VLAN. 9043 * The packet is forwarded to the monitoring port on the monitoring 9044 * VLAN. 9045 */ 9046 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1, 9047 9048 /* Encapsulated Remote SPAN Ethernet L3 GRE. 9049 * The packet is encapsulated with GRE header. 9050 */ 9051 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3, 9052 }; 9053 9054 /* reg_mpat_span_type 9055 * SPAN type. 9056 * Access: RW 9057 */ 9058 MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4); 9059 9060 /* reg_mpat_pide 9061 * Policer enable. 9062 * Access: RW 9063 */ 9064 MLXSW_ITEM32(reg, mpat, pide, 0x0C, 15, 1); 9065 9066 /* reg_mpat_pid 9067 * Policer ID. 9068 * Access: RW 9069 */ 9070 MLXSW_ITEM32(reg, mpat, pid, 0x0C, 0, 14); 9071 9072 /* Remote SPAN - Ethernet VLAN 9073 * - - - - - - - - - - - - - - 9074 */ 9075 9076 /* reg_mpat_eth_rspan_vid 9077 * Encapsulation header VLAN ID. 9078 * Access: RW 9079 */ 9080 MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12); 9081 9082 /* Encapsulated Remote SPAN - Ethernet L2 9083 * - - - - - - - - - - - - - - - - - - - 9084 */ 9085 9086 enum mlxsw_reg_mpat_eth_rspan_version { 9087 MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15, 9088 }; 9089 9090 /* reg_mpat_eth_rspan_version 9091 * RSPAN mirror header version. 9092 * Access: RW 9093 */ 9094 MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4); 9095 9096 /* reg_mpat_eth_rspan_mac 9097 * Destination MAC address. 9098 * Access: RW 9099 */ 9100 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6); 9101 9102 /* reg_mpat_eth_rspan_tp 9103 * Tag Packet. Indicates whether the mirroring header should be VLAN tagged. 9104 * Access: RW 9105 */ 9106 MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1); 9107 9108 /* Encapsulated Remote SPAN - Ethernet L3 9109 * - - - - - - - - - - - - - - - - - - - 9110 */ 9111 9112 enum mlxsw_reg_mpat_eth_rspan_protocol { 9113 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4, 9114 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6, 9115 }; 9116 9117 /* reg_mpat_eth_rspan_protocol 9118 * SPAN encapsulation protocol. 9119 * Access: RW 9120 */ 9121 MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4); 9122 9123 /* reg_mpat_eth_rspan_ttl 9124 * Encapsulation header Time-to-Live/HopLimit. 9125 * Access: RW 9126 */ 9127 MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8); 9128 9129 /* reg_mpat_eth_rspan_smac 9130 * Source MAC address 9131 * Access: RW 9132 */ 9133 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6); 9134 9135 /* reg_mpat_eth_rspan_dip* 9136 * Destination IP address. The IP version is configured by protocol. 9137 * Access: RW 9138 */ 9139 MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32); 9140 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16); 9141 9142 /* reg_mpat_eth_rspan_sip* 9143 * Source IP address. The IP version is configured by protocol. 9144 * Access: RW 9145 */ 9146 MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32); 9147 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16); 9148 9149 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id, 9150 u16 system_port, bool e, 9151 enum mlxsw_reg_mpat_span_type span_type) 9152 { 9153 MLXSW_REG_ZERO(mpat, payload); 9154 mlxsw_reg_mpat_pa_id_set(payload, pa_id); 9155 mlxsw_reg_mpat_system_port_set(payload, system_port); 9156 mlxsw_reg_mpat_e_set(payload, e); 9157 mlxsw_reg_mpat_qos_set(payload, 1); 9158 mlxsw_reg_mpat_be_set(payload, 1); 9159 mlxsw_reg_mpat_span_type_set(payload, span_type); 9160 } 9161 9162 static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid) 9163 { 9164 mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid); 9165 } 9166 9167 static inline void 9168 mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload, 9169 enum mlxsw_reg_mpat_eth_rspan_version version, 9170 const char *mac, 9171 bool tp) 9172 { 9173 mlxsw_reg_mpat_eth_rspan_version_set(payload, version); 9174 mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac); 9175 mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp); 9176 } 9177 9178 static inline void 9179 mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl, 9180 const char *smac, 9181 u32 sip, u32 dip) 9182 { 9183 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 9184 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 9185 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 9186 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4); 9187 mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip); 9188 mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip); 9189 } 9190 9191 static inline void 9192 mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl, 9193 const char *smac, 9194 struct in6_addr sip, struct in6_addr dip) 9195 { 9196 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 9197 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 9198 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 9199 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6); 9200 mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip); 9201 mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip); 9202 } 9203 9204 /* MPAR - Monitoring Port Analyzer Register 9205 * ---------------------------------------- 9206 * MPAR register is used to query and configure the port analyzer port mirroring 9207 * properties. 9208 */ 9209 #define MLXSW_REG_MPAR_ID 0x901B 9210 #define MLXSW_REG_MPAR_LEN 0x0C 9211 9212 MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN); 9213 9214 /* reg_mpar_local_port 9215 * The local port to mirror the packets from. 9216 * Access: Index 9217 */ 9218 MLXSW_ITEM32(reg, mpar, local_port, 0x00, 16, 8); 9219 9220 enum mlxsw_reg_mpar_i_e { 9221 MLXSW_REG_MPAR_TYPE_EGRESS, 9222 MLXSW_REG_MPAR_TYPE_INGRESS, 9223 }; 9224 9225 /* reg_mpar_i_e 9226 * Ingress/Egress 9227 * Access: Index 9228 */ 9229 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4); 9230 9231 /* reg_mpar_enable 9232 * Enable mirroring 9233 * By default, port mirroring is disabled for all ports. 9234 * Access: RW 9235 */ 9236 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1); 9237 9238 /* reg_mpar_pa_id 9239 * Port Analyzer ID. 9240 * Access: RW 9241 */ 9242 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4); 9243 9244 static inline void mlxsw_reg_mpar_pack(char *payload, u8 local_port, 9245 enum mlxsw_reg_mpar_i_e i_e, 9246 bool enable, u8 pa_id) 9247 { 9248 MLXSW_REG_ZERO(mpar, payload); 9249 mlxsw_reg_mpar_local_port_set(payload, local_port); 9250 mlxsw_reg_mpar_enable_set(payload, enable); 9251 mlxsw_reg_mpar_i_e_set(payload, i_e); 9252 mlxsw_reg_mpar_pa_id_set(payload, pa_id); 9253 } 9254 9255 /* MGIR - Management General Information Register 9256 * ---------------------------------------------- 9257 * MGIR register allows software to query the hardware and firmware general 9258 * information. 9259 */ 9260 #define MLXSW_REG_MGIR_ID 0x9020 9261 #define MLXSW_REG_MGIR_LEN 0x9C 9262 9263 MLXSW_REG_DEFINE(mgir, MLXSW_REG_MGIR_ID, MLXSW_REG_MGIR_LEN); 9264 9265 /* reg_mgir_hw_info_device_hw_revision 9266 * Access: RO 9267 */ 9268 MLXSW_ITEM32(reg, mgir, hw_info_device_hw_revision, 0x0, 16, 16); 9269 9270 #define MLXSW_REG_MGIR_FW_INFO_PSID_SIZE 16 9271 9272 /* reg_mgir_fw_info_psid 9273 * PSID (ASCII string). 9274 * Access: RO 9275 */ 9276 MLXSW_ITEM_BUF(reg, mgir, fw_info_psid, 0x30, MLXSW_REG_MGIR_FW_INFO_PSID_SIZE); 9277 9278 /* reg_mgir_fw_info_extended_major 9279 * Access: RO 9280 */ 9281 MLXSW_ITEM32(reg, mgir, fw_info_extended_major, 0x44, 0, 32); 9282 9283 /* reg_mgir_fw_info_extended_minor 9284 * Access: RO 9285 */ 9286 MLXSW_ITEM32(reg, mgir, fw_info_extended_minor, 0x48, 0, 32); 9287 9288 /* reg_mgir_fw_info_extended_sub_minor 9289 * Access: RO 9290 */ 9291 MLXSW_ITEM32(reg, mgir, fw_info_extended_sub_minor, 0x4C, 0, 32); 9292 9293 static inline void mlxsw_reg_mgir_pack(char *payload) 9294 { 9295 MLXSW_REG_ZERO(mgir, payload); 9296 } 9297 9298 static inline void 9299 mlxsw_reg_mgir_unpack(char *payload, u32 *hw_rev, char *fw_info_psid, 9300 u32 *fw_major, u32 *fw_minor, u32 *fw_sub_minor) 9301 { 9302 *hw_rev = mlxsw_reg_mgir_hw_info_device_hw_revision_get(payload); 9303 mlxsw_reg_mgir_fw_info_psid_memcpy_from(payload, fw_info_psid); 9304 *fw_major = mlxsw_reg_mgir_fw_info_extended_major_get(payload); 9305 *fw_minor = mlxsw_reg_mgir_fw_info_extended_minor_get(payload); 9306 *fw_sub_minor = mlxsw_reg_mgir_fw_info_extended_sub_minor_get(payload); 9307 } 9308 9309 /* MRSR - Management Reset and Shutdown Register 9310 * --------------------------------------------- 9311 * MRSR register is used to reset or shutdown the switch or 9312 * the entire system (when applicable). 9313 */ 9314 #define MLXSW_REG_MRSR_ID 0x9023 9315 #define MLXSW_REG_MRSR_LEN 0x08 9316 9317 MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN); 9318 9319 /* reg_mrsr_command 9320 * Reset/shutdown command 9321 * 0 - do nothing 9322 * 1 - software reset 9323 * Access: WO 9324 */ 9325 MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4); 9326 9327 static inline void mlxsw_reg_mrsr_pack(char *payload) 9328 { 9329 MLXSW_REG_ZERO(mrsr, payload); 9330 mlxsw_reg_mrsr_command_set(payload, 1); 9331 } 9332 9333 /* MLCR - Management LED Control Register 9334 * -------------------------------------- 9335 * Controls the system LEDs. 9336 */ 9337 #define MLXSW_REG_MLCR_ID 0x902B 9338 #define MLXSW_REG_MLCR_LEN 0x0C 9339 9340 MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN); 9341 9342 /* reg_mlcr_local_port 9343 * Local port number. 9344 * Access: RW 9345 */ 9346 MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8); 9347 9348 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF 9349 9350 /* reg_mlcr_beacon_duration 9351 * Duration of the beacon to be active, in seconds. 9352 * 0x0 - Will turn off the beacon. 9353 * 0xFFFF - Will turn on the beacon until explicitly turned off. 9354 * Access: RW 9355 */ 9356 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16); 9357 9358 /* reg_mlcr_beacon_remain 9359 * Remaining duration of the beacon, in seconds. 9360 * 0xFFFF indicates an infinite amount of time. 9361 * Access: RO 9362 */ 9363 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16); 9364 9365 static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port, 9366 bool active) 9367 { 9368 MLXSW_REG_ZERO(mlcr, payload); 9369 mlxsw_reg_mlcr_local_port_set(payload, local_port); 9370 mlxsw_reg_mlcr_beacon_duration_set(payload, active ? 9371 MLXSW_REG_MLCR_DURATION_MAX : 0); 9372 } 9373 9374 /* MTPPS - Management Pulse Per Second Register 9375 * -------------------------------------------- 9376 * This register provides the device PPS capabilities, configure the PPS in and 9377 * out modules and holds the PPS in time stamp. 9378 */ 9379 #define MLXSW_REG_MTPPS_ID 0x9053 9380 #define MLXSW_REG_MTPPS_LEN 0x3C 9381 9382 MLXSW_REG_DEFINE(mtpps, MLXSW_REG_MTPPS_ID, MLXSW_REG_MTPPS_LEN); 9383 9384 /* reg_mtpps_enable 9385 * Enables the PPS functionality the specific pin. 9386 * A boolean variable. 9387 * Access: RW 9388 */ 9389 MLXSW_ITEM32(reg, mtpps, enable, 0x20, 31, 1); 9390 9391 enum mlxsw_reg_mtpps_pin_mode { 9392 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN = 0x2, 9393 }; 9394 9395 /* reg_mtpps_pin_mode 9396 * Pin mode to be used. The mode must comply with the supported modes of the 9397 * requested pin. 9398 * Access: RW 9399 */ 9400 MLXSW_ITEM32(reg, mtpps, pin_mode, 0x20, 8, 4); 9401 9402 #define MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN 7 9403 9404 /* reg_mtpps_pin 9405 * Pin to be configured or queried out of the supported pins. 9406 * Access: Index 9407 */ 9408 MLXSW_ITEM32(reg, mtpps, pin, 0x20, 0, 8); 9409 9410 /* reg_mtpps_time_stamp 9411 * When pin_mode = pps_in, the latched device time when it was triggered from 9412 * the external GPIO pin. 9413 * When pin_mode = pps_out or virtual_pin or pps_out_and_virtual_pin, the target 9414 * time to generate next output signal. 9415 * Time is in units of device clock. 9416 * Access: RW 9417 */ 9418 MLXSW_ITEM64(reg, mtpps, time_stamp, 0x28, 0, 64); 9419 9420 static inline void 9421 mlxsw_reg_mtpps_vpin_pack(char *payload, u64 time_stamp) 9422 { 9423 MLXSW_REG_ZERO(mtpps, payload); 9424 mlxsw_reg_mtpps_pin_set(payload, MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN); 9425 mlxsw_reg_mtpps_pin_mode_set(payload, 9426 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN); 9427 mlxsw_reg_mtpps_enable_set(payload, true); 9428 mlxsw_reg_mtpps_time_stamp_set(payload, time_stamp); 9429 } 9430 9431 /* MTUTC - Management UTC Register 9432 * ------------------------------- 9433 * Configures the HW UTC counter. 9434 */ 9435 #define MLXSW_REG_MTUTC_ID 0x9055 9436 #define MLXSW_REG_MTUTC_LEN 0x1C 9437 9438 MLXSW_REG_DEFINE(mtutc, MLXSW_REG_MTUTC_ID, MLXSW_REG_MTUTC_LEN); 9439 9440 enum mlxsw_reg_mtutc_operation { 9441 MLXSW_REG_MTUTC_OPERATION_SET_TIME_AT_NEXT_SEC = 0, 9442 MLXSW_REG_MTUTC_OPERATION_ADJUST_FREQ = 3, 9443 }; 9444 9445 /* reg_mtutc_operation 9446 * Operation. 9447 * Access: OP 9448 */ 9449 MLXSW_ITEM32(reg, mtutc, operation, 0x00, 0, 4); 9450 9451 /* reg_mtutc_freq_adjustment 9452 * Frequency adjustment: Every PPS the HW frequency will be 9453 * adjusted by this value. Units of HW clock, where HW counts 9454 * 10^9 HW clocks for 1 HW second. 9455 * Access: RW 9456 */ 9457 MLXSW_ITEM32(reg, mtutc, freq_adjustment, 0x04, 0, 32); 9458 9459 /* reg_mtutc_utc_sec 9460 * UTC seconds. 9461 * Access: WO 9462 */ 9463 MLXSW_ITEM32(reg, mtutc, utc_sec, 0x10, 0, 32); 9464 9465 static inline void 9466 mlxsw_reg_mtutc_pack(char *payload, enum mlxsw_reg_mtutc_operation oper, 9467 u32 freq_adj, u32 utc_sec) 9468 { 9469 MLXSW_REG_ZERO(mtutc, payload); 9470 mlxsw_reg_mtutc_operation_set(payload, oper); 9471 mlxsw_reg_mtutc_freq_adjustment_set(payload, freq_adj); 9472 mlxsw_reg_mtutc_utc_sec_set(payload, utc_sec); 9473 } 9474 9475 /* MCQI - Management Component Query Information 9476 * --------------------------------------------- 9477 * This register allows querying information about firmware components. 9478 */ 9479 #define MLXSW_REG_MCQI_ID 0x9061 9480 #define MLXSW_REG_MCQI_BASE_LEN 0x18 9481 #define MLXSW_REG_MCQI_CAP_LEN 0x14 9482 #define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN) 9483 9484 MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN); 9485 9486 /* reg_mcqi_component_index 9487 * Index of the accessed component. 9488 * Access: Index 9489 */ 9490 MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16); 9491 9492 enum mlxfw_reg_mcqi_info_type { 9493 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES, 9494 }; 9495 9496 /* reg_mcqi_info_type 9497 * Component properties set. 9498 * Access: RW 9499 */ 9500 MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5); 9501 9502 /* reg_mcqi_offset 9503 * The requested/returned data offset from the section start, given in bytes. 9504 * Must be DWORD aligned. 9505 * Access: RW 9506 */ 9507 MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32); 9508 9509 /* reg_mcqi_data_size 9510 * The requested/returned data size, given in bytes. If data_size is not DWORD 9511 * aligned, the last bytes are zero padded. 9512 * Access: RW 9513 */ 9514 MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16); 9515 9516 /* reg_mcqi_cap_max_component_size 9517 * Maximum size for this component, given in bytes. 9518 * Access: RO 9519 */ 9520 MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32); 9521 9522 /* reg_mcqi_cap_log_mcda_word_size 9523 * Log 2 of the access word size in bytes. Read and write access must be aligned 9524 * to the word size. Write access must be done for an integer number of words. 9525 * Access: RO 9526 */ 9527 MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4); 9528 9529 /* reg_mcqi_cap_mcda_max_write_size 9530 * Maximal write size for MCDA register 9531 * Access: RO 9532 */ 9533 MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16); 9534 9535 static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index) 9536 { 9537 MLXSW_REG_ZERO(mcqi, payload); 9538 mlxsw_reg_mcqi_component_index_set(payload, component_index); 9539 mlxsw_reg_mcqi_info_type_set(payload, 9540 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES); 9541 mlxsw_reg_mcqi_offset_set(payload, 0); 9542 mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN); 9543 } 9544 9545 static inline void mlxsw_reg_mcqi_unpack(char *payload, 9546 u32 *p_cap_max_component_size, 9547 u8 *p_cap_log_mcda_word_size, 9548 u16 *p_cap_mcda_max_write_size) 9549 { 9550 *p_cap_max_component_size = 9551 mlxsw_reg_mcqi_cap_max_component_size_get(payload); 9552 *p_cap_log_mcda_word_size = 9553 mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload); 9554 *p_cap_mcda_max_write_size = 9555 mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload); 9556 } 9557 9558 /* MCC - Management Component Control 9559 * ---------------------------------- 9560 * Controls the firmware component and updates the FSM. 9561 */ 9562 #define MLXSW_REG_MCC_ID 0x9062 9563 #define MLXSW_REG_MCC_LEN 0x1C 9564 9565 MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN); 9566 9567 enum mlxsw_reg_mcc_instruction { 9568 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01, 9569 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02, 9570 MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03, 9571 MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04, 9572 MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06, 9573 MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08, 9574 }; 9575 9576 /* reg_mcc_instruction 9577 * Command to be executed by the FSM. 9578 * Applicable for write operation only. 9579 * Access: RW 9580 */ 9581 MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8); 9582 9583 /* reg_mcc_component_index 9584 * Index of the accessed component. Applicable only for commands that 9585 * refer to components. Otherwise, this field is reserved. 9586 * Access: Index 9587 */ 9588 MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16); 9589 9590 /* reg_mcc_update_handle 9591 * Token representing the current flow executed by the FSM. 9592 * Access: WO 9593 */ 9594 MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24); 9595 9596 /* reg_mcc_error_code 9597 * Indicates the successful completion of the instruction, or the reason it 9598 * failed 9599 * Access: RO 9600 */ 9601 MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8); 9602 9603 /* reg_mcc_control_state 9604 * Current FSM state 9605 * Access: RO 9606 */ 9607 MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4); 9608 9609 /* reg_mcc_component_size 9610 * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying 9611 * the size may shorten the update time. Value 0x0 means that size is 9612 * unspecified. 9613 * Access: WO 9614 */ 9615 MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32); 9616 9617 static inline void mlxsw_reg_mcc_pack(char *payload, 9618 enum mlxsw_reg_mcc_instruction instr, 9619 u16 component_index, u32 update_handle, 9620 u32 component_size) 9621 { 9622 MLXSW_REG_ZERO(mcc, payload); 9623 mlxsw_reg_mcc_instruction_set(payload, instr); 9624 mlxsw_reg_mcc_component_index_set(payload, component_index); 9625 mlxsw_reg_mcc_update_handle_set(payload, update_handle); 9626 mlxsw_reg_mcc_component_size_set(payload, component_size); 9627 } 9628 9629 static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle, 9630 u8 *p_error_code, u8 *p_control_state) 9631 { 9632 if (p_update_handle) 9633 *p_update_handle = mlxsw_reg_mcc_update_handle_get(payload); 9634 if (p_error_code) 9635 *p_error_code = mlxsw_reg_mcc_error_code_get(payload); 9636 if (p_control_state) 9637 *p_control_state = mlxsw_reg_mcc_control_state_get(payload); 9638 } 9639 9640 /* MCDA - Management Component Data Access 9641 * --------------------------------------- 9642 * This register allows reading and writing a firmware component. 9643 */ 9644 #define MLXSW_REG_MCDA_ID 0x9063 9645 #define MLXSW_REG_MCDA_BASE_LEN 0x10 9646 #define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80 9647 #define MLXSW_REG_MCDA_LEN \ 9648 (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN) 9649 9650 MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN); 9651 9652 /* reg_mcda_update_handle 9653 * Token representing the current flow executed by the FSM. 9654 * Access: RW 9655 */ 9656 MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24); 9657 9658 /* reg_mcda_offset 9659 * Offset of accessed address relative to component start. Accesses must be in 9660 * accordance to log_mcda_word_size in MCQI reg. 9661 * Access: RW 9662 */ 9663 MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32); 9664 9665 /* reg_mcda_size 9666 * Size of the data accessed, given in bytes. 9667 * Access: RW 9668 */ 9669 MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16); 9670 9671 /* reg_mcda_data 9672 * Data block accessed. 9673 * Access: RW 9674 */ 9675 MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false); 9676 9677 static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle, 9678 u32 offset, u16 size, u8 *data) 9679 { 9680 int i; 9681 9682 MLXSW_REG_ZERO(mcda, payload); 9683 mlxsw_reg_mcda_update_handle_set(payload, update_handle); 9684 mlxsw_reg_mcda_offset_set(payload, offset); 9685 mlxsw_reg_mcda_size_set(payload, size); 9686 9687 for (i = 0; i < size / 4; i++) 9688 mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]); 9689 } 9690 9691 /* MPSC - Monitoring Packet Sampling Configuration Register 9692 * -------------------------------------------------------- 9693 * MPSC Register is used to configure the Packet Sampling mechanism. 9694 */ 9695 #define MLXSW_REG_MPSC_ID 0x9080 9696 #define MLXSW_REG_MPSC_LEN 0x1C 9697 9698 MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN); 9699 9700 /* reg_mpsc_local_port 9701 * Local port number 9702 * Not supported for CPU port 9703 * Access: Index 9704 */ 9705 MLXSW_ITEM32(reg, mpsc, local_port, 0x00, 16, 8); 9706 9707 /* reg_mpsc_e 9708 * Enable sampling on port local_port 9709 * Access: RW 9710 */ 9711 MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1); 9712 9713 #define MLXSW_REG_MPSC_RATE_MAX 3500000000UL 9714 9715 /* reg_mpsc_rate 9716 * Sampling rate = 1 out of rate packets (with randomization around 9717 * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX 9718 * Access: RW 9719 */ 9720 MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32); 9721 9722 static inline void mlxsw_reg_mpsc_pack(char *payload, u8 local_port, bool e, 9723 u32 rate) 9724 { 9725 MLXSW_REG_ZERO(mpsc, payload); 9726 mlxsw_reg_mpsc_local_port_set(payload, local_port); 9727 mlxsw_reg_mpsc_e_set(payload, e); 9728 mlxsw_reg_mpsc_rate_set(payload, rate); 9729 } 9730 9731 /* MGPC - Monitoring General Purpose Counter Set Register 9732 * The MGPC register retrieves and sets the General Purpose Counter Set. 9733 */ 9734 #define MLXSW_REG_MGPC_ID 0x9081 9735 #define MLXSW_REG_MGPC_LEN 0x18 9736 9737 MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN); 9738 9739 /* reg_mgpc_counter_set_type 9740 * Counter set type. 9741 * Access: OP 9742 */ 9743 MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8); 9744 9745 /* reg_mgpc_counter_index 9746 * Counter index. 9747 * Access: Index 9748 */ 9749 MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24); 9750 9751 enum mlxsw_reg_mgpc_opcode { 9752 /* Nop */ 9753 MLXSW_REG_MGPC_OPCODE_NOP = 0x00, 9754 /* Clear counters */ 9755 MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08, 9756 }; 9757 9758 /* reg_mgpc_opcode 9759 * Opcode. 9760 * Access: OP 9761 */ 9762 MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4); 9763 9764 /* reg_mgpc_byte_counter 9765 * Byte counter value. 9766 * Access: RW 9767 */ 9768 MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64); 9769 9770 /* reg_mgpc_packet_counter 9771 * Packet counter value. 9772 * Access: RW 9773 */ 9774 MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64); 9775 9776 static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index, 9777 enum mlxsw_reg_mgpc_opcode opcode, 9778 enum mlxsw_reg_flow_counter_set_type set_type) 9779 { 9780 MLXSW_REG_ZERO(mgpc, payload); 9781 mlxsw_reg_mgpc_counter_index_set(payload, counter_index); 9782 mlxsw_reg_mgpc_counter_set_type_set(payload, set_type); 9783 mlxsw_reg_mgpc_opcode_set(payload, opcode); 9784 } 9785 9786 /* MPRS - Monitoring Parsing State Register 9787 * ---------------------------------------- 9788 * The MPRS register is used for setting up the parsing for hash, 9789 * policy-engine and routing. 9790 */ 9791 #define MLXSW_REG_MPRS_ID 0x9083 9792 #define MLXSW_REG_MPRS_LEN 0x14 9793 9794 MLXSW_REG_DEFINE(mprs, MLXSW_REG_MPRS_ID, MLXSW_REG_MPRS_LEN); 9795 9796 /* reg_mprs_parsing_depth 9797 * Minimum parsing depth. 9798 * Need to enlarge parsing depth according to L3, MPLS, tunnels, ACL 9799 * rules, traps, hash, etc. Default is 96 bytes. Reserved when SwitchX-2. 9800 * Access: RW 9801 */ 9802 MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16); 9803 9804 /* reg_mprs_parsing_en 9805 * Parsing enable. 9806 * Bit 0 - Enable parsing of NVE of types VxLAN, VxLAN-GPE, GENEVE and 9807 * NVGRE. Default is enabled. Reserved when SwitchX-2. 9808 * Access: RW 9809 */ 9810 MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16); 9811 9812 /* reg_mprs_vxlan_udp_dport 9813 * VxLAN UDP destination port. 9814 * Used for identifying VxLAN packets and for dport field in 9815 * encapsulation. Default is 4789. 9816 * Access: RW 9817 */ 9818 MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16); 9819 9820 static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth, 9821 u16 vxlan_udp_dport) 9822 { 9823 MLXSW_REG_ZERO(mprs, payload); 9824 mlxsw_reg_mprs_parsing_depth_set(payload, parsing_depth); 9825 mlxsw_reg_mprs_parsing_en_set(payload, true); 9826 mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport); 9827 } 9828 9829 /* MOGCR - Monitoring Global Configuration Register 9830 * ------------------------------------------------ 9831 */ 9832 #define MLXSW_REG_MOGCR_ID 0x9086 9833 #define MLXSW_REG_MOGCR_LEN 0x20 9834 9835 MLXSW_REG_DEFINE(mogcr, MLXSW_REG_MOGCR_ID, MLXSW_REG_MOGCR_LEN); 9836 9837 /* reg_mogcr_ptp_iftc 9838 * PTP Ingress FIFO Trap Clear 9839 * The PTP_ING_FIFO trap provides MTPPTR with clr according 9840 * to this value. Default 0. 9841 * Reserved when IB switches and when SwitchX/-2, Spectrum-2 9842 * Access: RW 9843 */ 9844 MLXSW_ITEM32(reg, mogcr, ptp_iftc, 0x00, 1, 1); 9845 9846 /* reg_mogcr_ptp_eftc 9847 * PTP Egress FIFO Trap Clear 9848 * The PTP_EGR_FIFO trap provides MTPPTR with clr according 9849 * to this value. Default 0. 9850 * Reserved when IB switches and when SwitchX/-2, Spectrum-2 9851 * Access: RW 9852 */ 9853 MLXSW_ITEM32(reg, mogcr, ptp_eftc, 0x00, 0, 1); 9854 9855 /* reg_mogcr_mirroring_pid_base 9856 * Base policer id for mirroring policers. 9857 * Must have an even value (e.g. 1000, not 1001). 9858 * Reserved when SwitchX/-2, Switch-IB/2, Spectrum-1 and Quantum. 9859 * Access: RW 9860 */ 9861 MLXSW_ITEM32(reg, mogcr, mirroring_pid_base, 0x0C, 0, 14); 9862 9863 /* MPAGR - Monitoring Port Analyzer Global Register 9864 * ------------------------------------------------ 9865 * This register is used for global port analyzer configurations. 9866 * Note: This register is not supported by current FW versions for Spectrum-1. 9867 */ 9868 #define MLXSW_REG_MPAGR_ID 0x9089 9869 #define MLXSW_REG_MPAGR_LEN 0x0C 9870 9871 MLXSW_REG_DEFINE(mpagr, MLXSW_REG_MPAGR_ID, MLXSW_REG_MPAGR_LEN); 9872 9873 enum mlxsw_reg_mpagr_trigger { 9874 MLXSW_REG_MPAGR_TRIGGER_EGRESS, 9875 MLXSW_REG_MPAGR_TRIGGER_INGRESS, 9876 MLXSW_REG_MPAGR_TRIGGER_INGRESS_WRED, 9877 MLXSW_REG_MPAGR_TRIGGER_INGRESS_SHARED_BUFFER, 9878 MLXSW_REG_MPAGR_TRIGGER_INGRESS_ING_CONG, 9879 MLXSW_REG_MPAGR_TRIGGER_INGRESS_EGR_CONG, 9880 MLXSW_REG_MPAGR_TRIGGER_EGRESS_ECN, 9881 MLXSW_REG_MPAGR_TRIGGER_EGRESS_HIGH_LATENCY, 9882 }; 9883 9884 /* reg_mpagr_trigger 9885 * Mirror trigger. 9886 * Access: Index 9887 */ 9888 MLXSW_ITEM32(reg, mpagr, trigger, 0x00, 0, 4); 9889 9890 /* reg_mpagr_pa_id 9891 * Port analyzer ID. 9892 * Access: RW 9893 */ 9894 MLXSW_ITEM32(reg, mpagr, pa_id, 0x04, 0, 4); 9895 9896 /* reg_mpagr_probability_rate 9897 * Sampling rate. 9898 * Valid values are: 1 to 3.5*10^9 9899 * Value of 1 means "sample all". Default is 1. 9900 * Access: RW 9901 */ 9902 MLXSW_ITEM32(reg, mpagr, probability_rate, 0x08, 0, 32); 9903 9904 static inline void mlxsw_reg_mpagr_pack(char *payload, 9905 enum mlxsw_reg_mpagr_trigger trigger, 9906 u8 pa_id, u32 probability_rate) 9907 { 9908 MLXSW_REG_ZERO(mpagr, payload); 9909 mlxsw_reg_mpagr_trigger_set(payload, trigger); 9910 mlxsw_reg_mpagr_pa_id_set(payload, pa_id); 9911 mlxsw_reg_mpagr_probability_rate_set(payload, probability_rate); 9912 } 9913 9914 /* MOMTE - Monitoring Mirror Trigger Enable Register 9915 * ------------------------------------------------- 9916 * This register is used to configure the mirror enable for different mirror 9917 * reasons. 9918 */ 9919 #define MLXSW_REG_MOMTE_ID 0x908D 9920 #define MLXSW_REG_MOMTE_LEN 0x10 9921 9922 MLXSW_REG_DEFINE(momte, MLXSW_REG_MOMTE_ID, MLXSW_REG_MOMTE_LEN); 9923 9924 /* reg_momte_local_port 9925 * Local port number. 9926 * Access: Index 9927 */ 9928 MLXSW_ITEM32(reg, momte, local_port, 0x00, 16, 8); 9929 9930 enum mlxsw_reg_momte_type { 9931 MLXSW_REG_MOMTE_TYPE_WRED = 0x20, 9932 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS = 0x31, 9933 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS_DESCRIPTORS = 0x32, 9934 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_EGRESS_PORT = 0x33, 9935 MLXSW_REG_MOMTE_TYPE_ING_CONG = 0x40, 9936 MLXSW_REG_MOMTE_TYPE_EGR_CONG = 0x50, 9937 MLXSW_REG_MOMTE_TYPE_ECN = 0x60, 9938 MLXSW_REG_MOMTE_TYPE_HIGH_LATENCY = 0x70, 9939 }; 9940 9941 /* reg_momte_type 9942 * Type of mirroring. 9943 * Access: Index 9944 */ 9945 MLXSW_ITEM32(reg, momte, type, 0x04, 0, 8); 9946 9947 /* reg_momte_tclass_en 9948 * TClass/PG mirror enable. Each bit represents corresponding tclass. 9949 * 0: disable (default) 9950 * 1: enable 9951 * Access: RW 9952 */ 9953 MLXSW_ITEM_BIT_ARRAY(reg, momte, tclass_en, 0x08, 0x08, 1); 9954 9955 static inline void mlxsw_reg_momte_pack(char *payload, u8 local_port, 9956 enum mlxsw_reg_momte_type type) 9957 { 9958 MLXSW_REG_ZERO(momte, payload); 9959 mlxsw_reg_momte_local_port_set(payload, local_port); 9960 mlxsw_reg_momte_type_set(payload, type); 9961 } 9962 9963 /* MTPPPC - Time Precision Packet Port Configuration 9964 * ------------------------------------------------- 9965 * This register serves for configuration of which PTP messages should be 9966 * timestamped. This is a global configuration, despite the register name. 9967 * 9968 * Reserved when Spectrum-2. 9969 */ 9970 #define MLXSW_REG_MTPPPC_ID 0x9090 9971 #define MLXSW_REG_MTPPPC_LEN 0x28 9972 9973 MLXSW_REG_DEFINE(mtpppc, MLXSW_REG_MTPPPC_ID, MLXSW_REG_MTPPPC_LEN); 9974 9975 /* reg_mtpppc_ing_timestamp_message_type 9976 * Bitwise vector of PTP message types to timestamp at ingress. 9977 * MessageType field as defined by IEEE 1588 9978 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req) 9979 * Default all 0 9980 * Access: RW 9981 */ 9982 MLXSW_ITEM32(reg, mtpppc, ing_timestamp_message_type, 0x08, 0, 16); 9983 9984 /* reg_mtpppc_egr_timestamp_message_type 9985 * Bitwise vector of PTP message types to timestamp at egress. 9986 * MessageType field as defined by IEEE 1588 9987 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req) 9988 * Default all 0 9989 * Access: RW 9990 */ 9991 MLXSW_ITEM32(reg, mtpppc, egr_timestamp_message_type, 0x0C, 0, 16); 9992 9993 static inline void mlxsw_reg_mtpppc_pack(char *payload, u16 ing, u16 egr) 9994 { 9995 MLXSW_REG_ZERO(mtpppc, payload); 9996 mlxsw_reg_mtpppc_ing_timestamp_message_type_set(payload, ing); 9997 mlxsw_reg_mtpppc_egr_timestamp_message_type_set(payload, egr); 9998 } 9999 10000 /* MTPPTR - Time Precision Packet Timestamping Reading 10001 * --------------------------------------------------- 10002 * The MTPPTR is used for reading the per port PTP timestamp FIFO. 10003 * There is a trap for packets which are latched to the timestamp FIFO, thus the 10004 * SW knows which FIFO to read. Note that packets enter the FIFO before been 10005 * trapped. The sequence number is used to synchronize the timestamp FIFO 10006 * entries and the trapped packets. 10007 * Reserved when Spectrum-2. 10008 */ 10009 10010 #define MLXSW_REG_MTPPTR_ID 0x9091 10011 #define MLXSW_REG_MTPPTR_BASE_LEN 0x10 /* base length, without records */ 10012 #define MLXSW_REG_MTPPTR_REC_LEN 0x10 /* record length */ 10013 #define MLXSW_REG_MTPPTR_REC_MAX_COUNT 4 10014 #define MLXSW_REG_MTPPTR_LEN (MLXSW_REG_MTPPTR_BASE_LEN + \ 10015 MLXSW_REG_MTPPTR_REC_LEN * MLXSW_REG_MTPPTR_REC_MAX_COUNT) 10016 10017 MLXSW_REG_DEFINE(mtpptr, MLXSW_REG_MTPPTR_ID, MLXSW_REG_MTPPTR_LEN); 10018 10019 /* reg_mtpptr_local_port 10020 * Not supported for CPU port. 10021 * Access: Index 10022 */ 10023 MLXSW_ITEM32(reg, mtpptr, local_port, 0x00, 16, 8); 10024 10025 enum mlxsw_reg_mtpptr_dir { 10026 MLXSW_REG_MTPPTR_DIR_INGRESS, 10027 MLXSW_REG_MTPPTR_DIR_EGRESS, 10028 }; 10029 10030 /* reg_mtpptr_dir 10031 * Direction. 10032 * Access: Index 10033 */ 10034 MLXSW_ITEM32(reg, mtpptr, dir, 0x00, 0, 1); 10035 10036 /* reg_mtpptr_clr 10037 * Clear the records. 10038 * Access: OP 10039 */ 10040 MLXSW_ITEM32(reg, mtpptr, clr, 0x04, 31, 1); 10041 10042 /* reg_mtpptr_num_rec 10043 * Number of valid records in the response 10044 * Range 0.. cap_ptp_timestamp_fifo 10045 * Access: RO 10046 */ 10047 MLXSW_ITEM32(reg, mtpptr, num_rec, 0x08, 0, 4); 10048 10049 /* reg_mtpptr_rec_message_type 10050 * MessageType field as defined by IEEE 1588 Each bit corresponds to a value 10051 * (e.g. Bit0: Sync, Bit1: Delay_Req) 10052 * Access: RO 10053 */ 10054 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_message_type, 10055 MLXSW_REG_MTPPTR_BASE_LEN, 8, 4, 10056 MLXSW_REG_MTPPTR_REC_LEN, 0, false); 10057 10058 /* reg_mtpptr_rec_domain_number 10059 * DomainNumber field as defined by IEEE 1588 10060 * Access: RO 10061 */ 10062 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_domain_number, 10063 MLXSW_REG_MTPPTR_BASE_LEN, 0, 8, 10064 MLXSW_REG_MTPPTR_REC_LEN, 0, false); 10065 10066 /* reg_mtpptr_rec_sequence_id 10067 * SequenceId field as defined by IEEE 1588 10068 * Access: RO 10069 */ 10070 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_sequence_id, 10071 MLXSW_REG_MTPPTR_BASE_LEN, 0, 16, 10072 MLXSW_REG_MTPPTR_REC_LEN, 0x4, false); 10073 10074 /* reg_mtpptr_rec_timestamp_high 10075 * Timestamp of when the PTP packet has passed through the port Units of PLL 10076 * clock time. 10077 * For Spectrum-1 the PLL clock is 156.25Mhz and PLL clock time is 6.4nSec. 10078 * Access: RO 10079 */ 10080 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_high, 10081 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32, 10082 MLXSW_REG_MTPPTR_REC_LEN, 0x8, false); 10083 10084 /* reg_mtpptr_rec_timestamp_low 10085 * See rec_timestamp_high. 10086 * Access: RO 10087 */ 10088 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_low, 10089 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32, 10090 MLXSW_REG_MTPPTR_REC_LEN, 0xC, false); 10091 10092 static inline void mlxsw_reg_mtpptr_unpack(const char *payload, 10093 unsigned int rec, 10094 u8 *p_message_type, 10095 u8 *p_domain_number, 10096 u16 *p_sequence_id, 10097 u64 *p_timestamp) 10098 { 10099 u32 timestamp_high, timestamp_low; 10100 10101 *p_message_type = mlxsw_reg_mtpptr_rec_message_type_get(payload, rec); 10102 *p_domain_number = mlxsw_reg_mtpptr_rec_domain_number_get(payload, rec); 10103 *p_sequence_id = mlxsw_reg_mtpptr_rec_sequence_id_get(payload, rec); 10104 timestamp_high = mlxsw_reg_mtpptr_rec_timestamp_high_get(payload, rec); 10105 timestamp_low = mlxsw_reg_mtpptr_rec_timestamp_low_get(payload, rec); 10106 *p_timestamp = (u64)timestamp_high << 32 | timestamp_low; 10107 } 10108 10109 /* MTPTPT - Monitoring Precision Time Protocol Trap Register 10110 * --------------------------------------------------------- 10111 * This register is used for configuring under which trap to deliver PTP 10112 * packets depending on type of the packet. 10113 */ 10114 #define MLXSW_REG_MTPTPT_ID 0x9092 10115 #define MLXSW_REG_MTPTPT_LEN 0x08 10116 10117 MLXSW_REG_DEFINE(mtptpt, MLXSW_REG_MTPTPT_ID, MLXSW_REG_MTPTPT_LEN); 10118 10119 enum mlxsw_reg_mtptpt_trap_id { 10120 MLXSW_REG_MTPTPT_TRAP_ID_PTP0, 10121 MLXSW_REG_MTPTPT_TRAP_ID_PTP1, 10122 }; 10123 10124 /* reg_mtptpt_trap_id 10125 * Trap id. 10126 * Access: Index 10127 */ 10128 MLXSW_ITEM32(reg, mtptpt, trap_id, 0x00, 0, 4); 10129 10130 /* reg_mtptpt_message_type 10131 * Bitwise vector of PTP message types to trap. This is a necessary but 10132 * non-sufficient condition since need to enable also per port. See MTPPPC. 10133 * Message types are defined by IEEE 1588 Each bit corresponds to a value (e.g. 10134 * Bit0: Sync, Bit1: Delay_Req) 10135 */ 10136 MLXSW_ITEM32(reg, mtptpt, message_type, 0x04, 0, 16); 10137 10138 static inline void mlxsw_reg_mtptptp_pack(char *payload, 10139 enum mlxsw_reg_mtptpt_trap_id trap_id, 10140 u16 message_type) 10141 { 10142 MLXSW_REG_ZERO(mtptpt, payload); 10143 mlxsw_reg_mtptpt_trap_id_set(payload, trap_id); 10144 mlxsw_reg_mtptpt_message_type_set(payload, message_type); 10145 } 10146 10147 /* MFGD - Monitoring FW General Debug Register 10148 * ------------------------------------------- 10149 */ 10150 #define MLXSW_REG_MFGD_ID 0x90F0 10151 #define MLXSW_REG_MFGD_LEN 0x0C 10152 10153 MLXSW_REG_DEFINE(mfgd, MLXSW_REG_MFGD_ID, MLXSW_REG_MFGD_LEN); 10154 10155 /* reg_mfgd_fw_fatal_event_mode 10156 * 0 - don't check FW fatal (default) 10157 * 1 - check FW fatal - enable MFDE trap 10158 * Access: RW 10159 */ 10160 MLXSW_ITEM32(reg, mfgd, fatal_event_mode, 0x00, 9, 2); 10161 10162 /* reg_mfgd_trigger_test 10163 * Access: WO 10164 */ 10165 MLXSW_ITEM32(reg, mfgd, trigger_test, 0x00, 11, 1); 10166 10167 /* MGPIR - Management General Peripheral Information Register 10168 * ---------------------------------------------------------- 10169 * MGPIR register allows software to query the hardware and 10170 * firmware general information of peripheral entities. 10171 */ 10172 #define MLXSW_REG_MGPIR_ID 0x9100 10173 #define MLXSW_REG_MGPIR_LEN 0xA0 10174 10175 MLXSW_REG_DEFINE(mgpir, MLXSW_REG_MGPIR_ID, MLXSW_REG_MGPIR_LEN); 10176 10177 enum mlxsw_reg_mgpir_device_type { 10178 MLXSW_REG_MGPIR_DEVICE_TYPE_NONE, 10179 MLXSW_REG_MGPIR_DEVICE_TYPE_GEARBOX_DIE, 10180 }; 10181 10182 /* device_type 10183 * Access: RO 10184 */ 10185 MLXSW_ITEM32(reg, mgpir, device_type, 0x00, 24, 4); 10186 10187 /* devices_per_flash 10188 * Number of devices of device_type per flash (can be shared by few devices). 10189 * Access: RO 10190 */ 10191 MLXSW_ITEM32(reg, mgpir, devices_per_flash, 0x00, 16, 8); 10192 10193 /* num_of_devices 10194 * Number of devices of device_type. 10195 * Access: RO 10196 */ 10197 MLXSW_ITEM32(reg, mgpir, num_of_devices, 0x00, 0, 8); 10198 10199 /* num_of_modules 10200 * Number of modules. 10201 * Access: RO 10202 */ 10203 MLXSW_ITEM32(reg, mgpir, num_of_modules, 0x04, 0, 8); 10204 10205 static inline void mlxsw_reg_mgpir_pack(char *payload) 10206 { 10207 MLXSW_REG_ZERO(mgpir, payload); 10208 } 10209 10210 static inline void 10211 mlxsw_reg_mgpir_unpack(char *payload, u8 *num_of_devices, 10212 enum mlxsw_reg_mgpir_device_type *device_type, 10213 u8 *devices_per_flash, u8 *num_of_modules) 10214 { 10215 if (num_of_devices) 10216 *num_of_devices = mlxsw_reg_mgpir_num_of_devices_get(payload); 10217 if (device_type) 10218 *device_type = mlxsw_reg_mgpir_device_type_get(payload); 10219 if (devices_per_flash) 10220 *devices_per_flash = 10221 mlxsw_reg_mgpir_devices_per_flash_get(payload); 10222 if (num_of_modules) 10223 *num_of_modules = mlxsw_reg_mgpir_num_of_modules_get(payload); 10224 } 10225 10226 /* MFDE - Monitoring FW Debug Register 10227 * ----------------------------------- 10228 */ 10229 #define MLXSW_REG_MFDE_ID 0x9200 10230 #define MLXSW_REG_MFDE_LEN 0x18 10231 10232 MLXSW_REG_DEFINE(mfde, MLXSW_REG_MFDE_ID, MLXSW_REG_MFDE_LEN); 10233 10234 /* reg_mfde_irisc_id 10235 * Which irisc triggered the event 10236 * Access: RO 10237 */ 10238 MLXSW_ITEM32(reg, mfde, irisc_id, 0x00, 8, 4); 10239 10240 enum mlxsw_reg_mfde_event_id { 10241 MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO = 1, 10242 /* KVD insertion machine stopped */ 10243 MLXSW_REG_MFDE_EVENT_ID_KVD_IM_STOP, 10244 }; 10245 10246 /* reg_mfde_event_id 10247 * Access: RO 10248 */ 10249 MLXSW_ITEM32(reg, mfde, event_id, 0x00, 0, 8); 10250 10251 enum mlxsw_reg_mfde_method { 10252 MLXSW_REG_MFDE_METHOD_QUERY, 10253 MLXSW_REG_MFDE_METHOD_WRITE, 10254 }; 10255 10256 /* reg_mfde_method 10257 * Access: RO 10258 */ 10259 MLXSW_ITEM32(reg, mfde, method, 0x04, 29, 1); 10260 10261 /* reg_mfde_long_process 10262 * Indicates if the command is in long_process mode. 10263 * Access: RO 10264 */ 10265 MLXSW_ITEM32(reg, mfde, long_process, 0x04, 28, 1); 10266 10267 enum mlxsw_reg_mfde_command_type { 10268 MLXSW_REG_MFDE_COMMAND_TYPE_MAD, 10269 MLXSW_REG_MFDE_COMMAND_TYPE_EMAD, 10270 MLXSW_REG_MFDE_COMMAND_TYPE_CMDIF, 10271 }; 10272 10273 /* reg_mfde_command_type 10274 * Access: RO 10275 */ 10276 MLXSW_ITEM32(reg, mfde, command_type, 0x04, 24, 2); 10277 10278 /* reg_mfde_reg_attr_id 10279 * EMAD - register id, MAD - attibute id 10280 * Access: RO 10281 */ 10282 MLXSW_ITEM32(reg, mfde, reg_attr_id, 0x04, 0, 16); 10283 10284 /* reg_mfde_log_address 10285 * crspace address accessed, which resulted in timeout. 10286 * Valid in case event_id == MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO 10287 * Access: RO 10288 */ 10289 MLXSW_ITEM32(reg, mfde, log_address, 0x10, 0, 32); 10290 10291 /* reg_mfde_log_id 10292 * Which irisc triggered the timeout. 10293 * Valid in case event_id == MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO 10294 * Access: RO 10295 */ 10296 MLXSW_ITEM32(reg, mfde, log_id, 0x14, 0, 4); 10297 10298 /* reg_mfde_pipes_mask 10299 * Bit per kvh pipe. 10300 * Access: RO 10301 */ 10302 MLXSW_ITEM32(reg, mfde, pipes_mask, 0x10, 0, 16); 10303 10304 /* TNGCR - Tunneling NVE General Configuration Register 10305 * ---------------------------------------------------- 10306 * The TNGCR register is used for setting up the NVE Tunneling configuration. 10307 */ 10308 #define MLXSW_REG_TNGCR_ID 0xA001 10309 #define MLXSW_REG_TNGCR_LEN 0x44 10310 10311 MLXSW_REG_DEFINE(tngcr, MLXSW_REG_TNGCR_ID, MLXSW_REG_TNGCR_LEN); 10312 10313 enum mlxsw_reg_tngcr_type { 10314 MLXSW_REG_TNGCR_TYPE_VXLAN, 10315 MLXSW_REG_TNGCR_TYPE_VXLAN_GPE, 10316 MLXSW_REG_TNGCR_TYPE_GENEVE, 10317 MLXSW_REG_TNGCR_TYPE_NVGRE, 10318 }; 10319 10320 /* reg_tngcr_type 10321 * Tunnel type for encapsulation and decapsulation. The types are mutually 10322 * exclusive. 10323 * Note: For Spectrum the NVE parsing must be enabled in MPRS. 10324 * Access: RW 10325 */ 10326 MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4); 10327 10328 /* reg_tngcr_nve_valid 10329 * The VTEP is valid. Allows adding FDB entries for tunnel encapsulation. 10330 * Access: RW 10331 */ 10332 MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1); 10333 10334 /* reg_tngcr_nve_ttl_uc 10335 * The TTL for NVE tunnel encapsulation underlay unicast packets. 10336 * Access: RW 10337 */ 10338 MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8); 10339 10340 /* reg_tngcr_nve_ttl_mc 10341 * The TTL for NVE tunnel encapsulation underlay multicast packets. 10342 * Access: RW 10343 */ 10344 MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8); 10345 10346 enum { 10347 /* Do not copy flow label. Calculate flow label using nve_flh. */ 10348 MLXSW_REG_TNGCR_FL_NO_COPY, 10349 /* Copy flow label from inner packet if packet is IPv6 and 10350 * encapsulation is by IPv6. Otherwise, calculate flow label using 10351 * nve_flh. 10352 */ 10353 MLXSW_REG_TNGCR_FL_COPY, 10354 }; 10355 10356 /* reg_tngcr_nve_flc 10357 * For NVE tunnel encapsulation: Flow label copy from inner packet. 10358 * Access: RW 10359 */ 10360 MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1); 10361 10362 enum { 10363 /* Flow label is static. In Spectrum this means '0'. Spectrum-2 10364 * uses {nve_fl_prefix, nve_fl_suffix}. 10365 */ 10366 MLXSW_REG_TNGCR_FL_NO_HASH, 10367 /* 8 LSBs of the flow label are calculated from ECMP hash of the 10368 * inner packet. 12 MSBs are configured by nve_fl_prefix. 10369 */ 10370 MLXSW_REG_TNGCR_FL_HASH, 10371 }; 10372 10373 /* reg_tngcr_nve_flh 10374 * NVE flow label hash. 10375 * Access: RW 10376 */ 10377 MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1); 10378 10379 /* reg_tngcr_nve_fl_prefix 10380 * NVE flow label prefix. Constant 12 MSBs of the flow label. 10381 * Access: RW 10382 */ 10383 MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12); 10384 10385 /* reg_tngcr_nve_fl_suffix 10386 * NVE flow label suffix. Constant 8 LSBs of the flow label. 10387 * Reserved when nve_flh=1 and for Spectrum. 10388 * Access: RW 10389 */ 10390 MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8); 10391 10392 enum { 10393 /* Source UDP port is fixed (default '0') */ 10394 MLXSW_REG_TNGCR_UDP_SPORT_NO_HASH, 10395 /* Source UDP port is calculated based on hash */ 10396 MLXSW_REG_TNGCR_UDP_SPORT_HASH, 10397 }; 10398 10399 /* reg_tngcr_nve_udp_sport_type 10400 * NVE UDP source port type. 10401 * Spectrum uses LAG hash (SLCRv2). Spectrum-2 uses ECMP hash (RECRv2). 10402 * When the source UDP port is calculated based on hash, then the 8 LSBs 10403 * are calculated from hash the 8 MSBs are configured by 10404 * nve_udp_sport_prefix. 10405 * Access: RW 10406 */ 10407 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1); 10408 10409 /* reg_tngcr_nve_udp_sport_prefix 10410 * NVE UDP source port prefix. Constant 8 MSBs of the UDP source port. 10411 * Reserved when NVE type is NVGRE. 10412 * Access: RW 10413 */ 10414 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8); 10415 10416 /* reg_tngcr_nve_group_size_mc 10417 * The amount of sequential linked lists of MC entries. The first linked 10418 * list is configured by SFD.underlay_mc_ptr. 10419 * Valid values: 1, 2, 4, 8, 16, 32, 64 10420 * The linked list are configured by TNUMT. 10421 * The hash is set by LAG hash. 10422 * Access: RW 10423 */ 10424 MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8); 10425 10426 /* reg_tngcr_nve_group_size_flood 10427 * The amount of sequential linked lists of flooding entries. The first 10428 * linked list is configured by SFMR.nve_tunnel_flood_ptr 10429 * Valid values: 1, 2, 4, 8, 16, 32, 64 10430 * The linked list are configured by TNUMT. 10431 * The hash is set by LAG hash. 10432 * Access: RW 10433 */ 10434 MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8); 10435 10436 /* reg_tngcr_learn_enable 10437 * During decapsulation, whether to learn from NVE port. 10438 * Reserved when Spectrum-2. See TNPC. 10439 * Access: RW 10440 */ 10441 MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1); 10442 10443 /* reg_tngcr_underlay_virtual_router 10444 * Underlay virtual router. 10445 * Reserved when Spectrum-2. 10446 * Access: RW 10447 */ 10448 MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16); 10449 10450 /* reg_tngcr_underlay_rif 10451 * Underlay ingress router interface. RIF type should be loopback generic. 10452 * Reserved when Spectrum. 10453 * Access: RW 10454 */ 10455 MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16); 10456 10457 /* reg_tngcr_usipv4 10458 * Underlay source IPv4 address of the NVE. 10459 * Access: RW 10460 */ 10461 MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32); 10462 10463 /* reg_tngcr_usipv6 10464 * Underlay source IPv6 address of the NVE. For Spectrum, must not be 10465 * modified under traffic of NVE tunneling encapsulation. 10466 * Access: RW 10467 */ 10468 MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16); 10469 10470 static inline void mlxsw_reg_tngcr_pack(char *payload, 10471 enum mlxsw_reg_tngcr_type type, 10472 bool valid, u8 ttl) 10473 { 10474 MLXSW_REG_ZERO(tngcr, payload); 10475 mlxsw_reg_tngcr_type_set(payload, type); 10476 mlxsw_reg_tngcr_nve_valid_set(payload, valid); 10477 mlxsw_reg_tngcr_nve_ttl_uc_set(payload, ttl); 10478 mlxsw_reg_tngcr_nve_ttl_mc_set(payload, ttl); 10479 mlxsw_reg_tngcr_nve_flc_set(payload, MLXSW_REG_TNGCR_FL_NO_COPY); 10480 mlxsw_reg_tngcr_nve_flh_set(payload, 0); 10481 mlxsw_reg_tngcr_nve_udp_sport_type_set(payload, 10482 MLXSW_REG_TNGCR_UDP_SPORT_HASH); 10483 mlxsw_reg_tngcr_nve_udp_sport_prefix_set(payload, 0); 10484 mlxsw_reg_tngcr_nve_group_size_mc_set(payload, 1); 10485 mlxsw_reg_tngcr_nve_group_size_flood_set(payload, 1); 10486 } 10487 10488 /* TNUMT - Tunneling NVE Underlay Multicast Table Register 10489 * ------------------------------------------------------- 10490 * The TNUMT register is for building the underlay MC table. It is used 10491 * for MC, flooding and BC traffic into the NVE tunnel. 10492 */ 10493 #define MLXSW_REG_TNUMT_ID 0xA003 10494 #define MLXSW_REG_TNUMT_LEN 0x20 10495 10496 MLXSW_REG_DEFINE(tnumt, MLXSW_REG_TNUMT_ID, MLXSW_REG_TNUMT_LEN); 10497 10498 enum mlxsw_reg_tnumt_record_type { 10499 MLXSW_REG_TNUMT_RECORD_TYPE_IPV4, 10500 MLXSW_REG_TNUMT_RECORD_TYPE_IPV6, 10501 MLXSW_REG_TNUMT_RECORD_TYPE_LABEL, 10502 }; 10503 10504 /* reg_tnumt_record_type 10505 * Record type. 10506 * Access: RW 10507 */ 10508 MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4); 10509 10510 enum mlxsw_reg_tnumt_tunnel_port { 10511 MLXSW_REG_TNUMT_TUNNEL_PORT_NVE, 10512 MLXSW_REG_TNUMT_TUNNEL_PORT_VPLS, 10513 MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL0, 10514 MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL1, 10515 }; 10516 10517 /* reg_tnumt_tunnel_port 10518 * Tunnel port. 10519 * Access: RW 10520 */ 10521 MLXSW_ITEM32(reg, tnumt, tunnel_port, 0x00, 24, 4); 10522 10523 /* reg_tnumt_underlay_mc_ptr 10524 * Index to the underlay multicast table. 10525 * For Spectrum the index is to the KVD linear. 10526 * Access: Index 10527 */ 10528 MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24); 10529 10530 /* reg_tnumt_vnext 10531 * The next_underlay_mc_ptr is valid. 10532 * Access: RW 10533 */ 10534 MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1); 10535 10536 /* reg_tnumt_next_underlay_mc_ptr 10537 * The next index to the underlay multicast table. 10538 * Access: RW 10539 */ 10540 MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24); 10541 10542 /* reg_tnumt_record_size 10543 * Number of IP addresses in the record. 10544 * Range is 1..cap_max_nve_mc_entries_ipv{4,6} 10545 * Access: RW 10546 */ 10547 MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3); 10548 10549 /* reg_tnumt_udip 10550 * The underlay IPv4 addresses. udip[i] is reserved if i >= size 10551 * Access: RW 10552 */ 10553 MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false); 10554 10555 /* reg_tnumt_udip_ptr 10556 * The pointer to the underlay IPv6 addresses. udip_ptr[i] is reserved if 10557 * i >= size. The IPv6 addresses are configured by RIPS. 10558 * Access: RW 10559 */ 10560 MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false); 10561 10562 static inline void mlxsw_reg_tnumt_pack(char *payload, 10563 enum mlxsw_reg_tnumt_record_type type, 10564 enum mlxsw_reg_tnumt_tunnel_port tport, 10565 u32 underlay_mc_ptr, bool vnext, 10566 u32 next_underlay_mc_ptr, 10567 u8 record_size) 10568 { 10569 MLXSW_REG_ZERO(tnumt, payload); 10570 mlxsw_reg_tnumt_record_type_set(payload, type); 10571 mlxsw_reg_tnumt_tunnel_port_set(payload, tport); 10572 mlxsw_reg_tnumt_underlay_mc_ptr_set(payload, underlay_mc_ptr); 10573 mlxsw_reg_tnumt_vnext_set(payload, vnext); 10574 mlxsw_reg_tnumt_next_underlay_mc_ptr_set(payload, next_underlay_mc_ptr); 10575 mlxsw_reg_tnumt_record_size_set(payload, record_size); 10576 } 10577 10578 /* TNQCR - Tunneling NVE QoS Configuration Register 10579 * ------------------------------------------------ 10580 * The TNQCR register configures how QoS is set in encapsulation into the 10581 * underlay network. 10582 */ 10583 #define MLXSW_REG_TNQCR_ID 0xA010 10584 #define MLXSW_REG_TNQCR_LEN 0x0C 10585 10586 MLXSW_REG_DEFINE(tnqcr, MLXSW_REG_TNQCR_ID, MLXSW_REG_TNQCR_LEN); 10587 10588 /* reg_tnqcr_enc_set_dscp 10589 * For encapsulation: How to set DSCP field: 10590 * 0 - Copy the DSCP from the overlay (inner) IP header to the underlay 10591 * (outer) IP header. If there is no IP header, use TNQDR.dscp 10592 * 1 - Set the DSCP field as TNQDR.dscp 10593 * Access: RW 10594 */ 10595 MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1); 10596 10597 static inline void mlxsw_reg_tnqcr_pack(char *payload) 10598 { 10599 MLXSW_REG_ZERO(tnqcr, payload); 10600 mlxsw_reg_tnqcr_enc_set_dscp_set(payload, 0); 10601 } 10602 10603 /* TNQDR - Tunneling NVE QoS Default Register 10604 * ------------------------------------------ 10605 * The TNQDR register configures the default QoS settings for NVE 10606 * encapsulation. 10607 */ 10608 #define MLXSW_REG_TNQDR_ID 0xA011 10609 #define MLXSW_REG_TNQDR_LEN 0x08 10610 10611 MLXSW_REG_DEFINE(tnqdr, MLXSW_REG_TNQDR_ID, MLXSW_REG_TNQDR_LEN); 10612 10613 /* reg_tnqdr_local_port 10614 * Local port number (receive port). CPU port is supported. 10615 * Access: Index 10616 */ 10617 MLXSW_ITEM32(reg, tnqdr, local_port, 0x00, 16, 8); 10618 10619 /* reg_tnqdr_dscp 10620 * For encapsulation, the default DSCP. 10621 * Access: RW 10622 */ 10623 MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6); 10624 10625 static inline void mlxsw_reg_tnqdr_pack(char *payload, u8 local_port) 10626 { 10627 MLXSW_REG_ZERO(tnqdr, payload); 10628 mlxsw_reg_tnqdr_local_port_set(payload, local_port); 10629 mlxsw_reg_tnqdr_dscp_set(payload, 0); 10630 } 10631 10632 /* TNEEM - Tunneling NVE Encapsulation ECN Mapping Register 10633 * -------------------------------------------------------- 10634 * The TNEEM register maps ECN of the IP header at the ingress to the 10635 * encapsulation to the ECN of the underlay network. 10636 */ 10637 #define MLXSW_REG_TNEEM_ID 0xA012 10638 #define MLXSW_REG_TNEEM_LEN 0x0C 10639 10640 MLXSW_REG_DEFINE(tneem, MLXSW_REG_TNEEM_ID, MLXSW_REG_TNEEM_LEN); 10641 10642 /* reg_tneem_overlay_ecn 10643 * ECN of the IP header in the overlay network. 10644 * Access: Index 10645 */ 10646 MLXSW_ITEM32(reg, tneem, overlay_ecn, 0x04, 24, 2); 10647 10648 /* reg_tneem_underlay_ecn 10649 * ECN of the IP header in the underlay network. 10650 * Access: RW 10651 */ 10652 MLXSW_ITEM32(reg, tneem, underlay_ecn, 0x04, 16, 2); 10653 10654 static inline void mlxsw_reg_tneem_pack(char *payload, u8 overlay_ecn, 10655 u8 underlay_ecn) 10656 { 10657 MLXSW_REG_ZERO(tneem, payload); 10658 mlxsw_reg_tneem_overlay_ecn_set(payload, overlay_ecn); 10659 mlxsw_reg_tneem_underlay_ecn_set(payload, underlay_ecn); 10660 } 10661 10662 /* TNDEM - Tunneling NVE Decapsulation ECN Mapping Register 10663 * -------------------------------------------------------- 10664 * The TNDEM register configures the actions that are done in the 10665 * decapsulation. 10666 */ 10667 #define MLXSW_REG_TNDEM_ID 0xA013 10668 #define MLXSW_REG_TNDEM_LEN 0x0C 10669 10670 MLXSW_REG_DEFINE(tndem, MLXSW_REG_TNDEM_ID, MLXSW_REG_TNDEM_LEN); 10671 10672 /* reg_tndem_underlay_ecn 10673 * ECN field of the IP header in the underlay network. 10674 * Access: Index 10675 */ 10676 MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2); 10677 10678 /* reg_tndem_overlay_ecn 10679 * ECN field of the IP header in the overlay network. 10680 * Access: Index 10681 */ 10682 MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2); 10683 10684 /* reg_tndem_eip_ecn 10685 * Egress IP ECN. ECN field of the IP header of the packet which goes out 10686 * from the decapsulation. 10687 * Access: RW 10688 */ 10689 MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2); 10690 10691 /* reg_tndem_trap_en 10692 * Trap enable: 10693 * 0 - No trap due to decap ECN 10694 * 1 - Trap enable with trap_id 10695 * Access: RW 10696 */ 10697 MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4); 10698 10699 /* reg_tndem_trap_id 10700 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 10701 * Reserved when trap_en is '0'. 10702 * Access: RW 10703 */ 10704 MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9); 10705 10706 static inline void mlxsw_reg_tndem_pack(char *payload, u8 underlay_ecn, 10707 u8 overlay_ecn, u8 ecn, bool trap_en, 10708 u16 trap_id) 10709 { 10710 MLXSW_REG_ZERO(tndem, payload); 10711 mlxsw_reg_tndem_underlay_ecn_set(payload, underlay_ecn); 10712 mlxsw_reg_tndem_overlay_ecn_set(payload, overlay_ecn); 10713 mlxsw_reg_tndem_eip_ecn_set(payload, ecn); 10714 mlxsw_reg_tndem_trap_en_set(payload, trap_en); 10715 mlxsw_reg_tndem_trap_id_set(payload, trap_id); 10716 } 10717 10718 /* TNPC - Tunnel Port Configuration Register 10719 * ----------------------------------------- 10720 * The TNPC register is used for tunnel port configuration. 10721 * Reserved when Spectrum. 10722 */ 10723 #define MLXSW_REG_TNPC_ID 0xA020 10724 #define MLXSW_REG_TNPC_LEN 0x18 10725 10726 MLXSW_REG_DEFINE(tnpc, MLXSW_REG_TNPC_ID, MLXSW_REG_TNPC_LEN); 10727 10728 enum mlxsw_reg_tnpc_tunnel_port { 10729 MLXSW_REG_TNPC_TUNNEL_PORT_NVE, 10730 MLXSW_REG_TNPC_TUNNEL_PORT_VPLS, 10731 MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL0, 10732 MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL1, 10733 }; 10734 10735 /* reg_tnpc_tunnel_port 10736 * Tunnel port. 10737 * Access: Index 10738 */ 10739 MLXSW_ITEM32(reg, tnpc, tunnel_port, 0x00, 0, 4); 10740 10741 /* reg_tnpc_learn_enable_v6 10742 * During IPv6 underlay decapsulation, whether to learn from tunnel port. 10743 * Access: RW 10744 */ 10745 MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1); 10746 10747 /* reg_tnpc_learn_enable_v4 10748 * During IPv4 underlay decapsulation, whether to learn from tunnel port. 10749 * Access: RW 10750 */ 10751 MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1); 10752 10753 static inline void mlxsw_reg_tnpc_pack(char *payload, 10754 enum mlxsw_reg_tnpc_tunnel_port tport, 10755 bool learn_enable) 10756 { 10757 MLXSW_REG_ZERO(tnpc, payload); 10758 mlxsw_reg_tnpc_tunnel_port_set(payload, tport); 10759 mlxsw_reg_tnpc_learn_enable_v4_set(payload, learn_enable); 10760 mlxsw_reg_tnpc_learn_enable_v6_set(payload, learn_enable); 10761 } 10762 10763 /* TIGCR - Tunneling IPinIP General Configuration Register 10764 * ------------------------------------------------------- 10765 * The TIGCR register is used for setting up the IPinIP Tunnel configuration. 10766 */ 10767 #define MLXSW_REG_TIGCR_ID 0xA801 10768 #define MLXSW_REG_TIGCR_LEN 0x10 10769 10770 MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN); 10771 10772 /* reg_tigcr_ipip_ttlc 10773 * For IPinIP Tunnel encapsulation: whether to copy the ttl from the packet 10774 * header. 10775 * Access: RW 10776 */ 10777 MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1); 10778 10779 /* reg_tigcr_ipip_ttl_uc 10780 * The TTL for IPinIP Tunnel encapsulation of unicast packets if 10781 * reg_tigcr_ipip_ttlc is unset. 10782 * Access: RW 10783 */ 10784 MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8); 10785 10786 static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc) 10787 { 10788 MLXSW_REG_ZERO(tigcr, payload); 10789 mlxsw_reg_tigcr_ttlc_set(payload, ttlc); 10790 mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc); 10791 } 10792 10793 /* TIEEM - Tunneling IPinIP Encapsulation ECN Mapping Register 10794 * ----------------------------------------------------------- 10795 * The TIEEM register maps ECN of the IP header at the ingress to the 10796 * encapsulation to the ECN of the underlay network. 10797 */ 10798 #define MLXSW_REG_TIEEM_ID 0xA812 10799 #define MLXSW_REG_TIEEM_LEN 0x0C 10800 10801 MLXSW_REG_DEFINE(tieem, MLXSW_REG_TIEEM_ID, MLXSW_REG_TIEEM_LEN); 10802 10803 /* reg_tieem_overlay_ecn 10804 * ECN of the IP header in the overlay network. 10805 * Access: Index 10806 */ 10807 MLXSW_ITEM32(reg, tieem, overlay_ecn, 0x04, 24, 2); 10808 10809 /* reg_tineem_underlay_ecn 10810 * ECN of the IP header in the underlay network. 10811 * Access: RW 10812 */ 10813 MLXSW_ITEM32(reg, tieem, underlay_ecn, 0x04, 16, 2); 10814 10815 static inline void mlxsw_reg_tieem_pack(char *payload, u8 overlay_ecn, 10816 u8 underlay_ecn) 10817 { 10818 MLXSW_REG_ZERO(tieem, payload); 10819 mlxsw_reg_tieem_overlay_ecn_set(payload, overlay_ecn); 10820 mlxsw_reg_tieem_underlay_ecn_set(payload, underlay_ecn); 10821 } 10822 10823 /* TIDEM - Tunneling IPinIP Decapsulation ECN Mapping Register 10824 * ----------------------------------------------------------- 10825 * The TIDEM register configures the actions that are done in the 10826 * decapsulation. 10827 */ 10828 #define MLXSW_REG_TIDEM_ID 0xA813 10829 #define MLXSW_REG_TIDEM_LEN 0x0C 10830 10831 MLXSW_REG_DEFINE(tidem, MLXSW_REG_TIDEM_ID, MLXSW_REG_TIDEM_LEN); 10832 10833 /* reg_tidem_underlay_ecn 10834 * ECN field of the IP header in the underlay network. 10835 * Access: Index 10836 */ 10837 MLXSW_ITEM32(reg, tidem, underlay_ecn, 0x04, 24, 2); 10838 10839 /* reg_tidem_overlay_ecn 10840 * ECN field of the IP header in the overlay network. 10841 * Access: Index 10842 */ 10843 MLXSW_ITEM32(reg, tidem, overlay_ecn, 0x04, 16, 2); 10844 10845 /* reg_tidem_eip_ecn 10846 * Egress IP ECN. ECN field of the IP header of the packet which goes out 10847 * from the decapsulation. 10848 * Access: RW 10849 */ 10850 MLXSW_ITEM32(reg, tidem, eip_ecn, 0x04, 8, 2); 10851 10852 /* reg_tidem_trap_en 10853 * Trap enable: 10854 * 0 - No trap due to decap ECN 10855 * 1 - Trap enable with trap_id 10856 * Access: RW 10857 */ 10858 MLXSW_ITEM32(reg, tidem, trap_en, 0x08, 28, 4); 10859 10860 /* reg_tidem_trap_id 10861 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 10862 * Reserved when trap_en is '0'. 10863 * Access: RW 10864 */ 10865 MLXSW_ITEM32(reg, tidem, trap_id, 0x08, 0, 9); 10866 10867 static inline void mlxsw_reg_tidem_pack(char *payload, u8 underlay_ecn, 10868 u8 overlay_ecn, u8 eip_ecn, 10869 bool trap_en, u16 trap_id) 10870 { 10871 MLXSW_REG_ZERO(tidem, payload); 10872 mlxsw_reg_tidem_underlay_ecn_set(payload, underlay_ecn); 10873 mlxsw_reg_tidem_overlay_ecn_set(payload, overlay_ecn); 10874 mlxsw_reg_tidem_eip_ecn_set(payload, eip_ecn); 10875 mlxsw_reg_tidem_trap_en_set(payload, trap_en); 10876 mlxsw_reg_tidem_trap_id_set(payload, trap_id); 10877 } 10878 10879 /* SBPR - Shared Buffer Pools Register 10880 * ----------------------------------- 10881 * The SBPR configures and retrieves the shared buffer pools and configuration. 10882 */ 10883 #define MLXSW_REG_SBPR_ID 0xB001 10884 #define MLXSW_REG_SBPR_LEN 0x14 10885 10886 MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN); 10887 10888 /* shared direstion enum for SBPR, SBCM, SBPM */ 10889 enum mlxsw_reg_sbxx_dir { 10890 MLXSW_REG_SBXX_DIR_INGRESS, 10891 MLXSW_REG_SBXX_DIR_EGRESS, 10892 }; 10893 10894 /* reg_sbpr_dir 10895 * Direction. 10896 * Access: Index 10897 */ 10898 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2); 10899 10900 /* reg_sbpr_pool 10901 * Pool index. 10902 * Access: Index 10903 */ 10904 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4); 10905 10906 /* reg_sbpr_infi_size 10907 * Size is infinite. 10908 * Access: RW 10909 */ 10910 MLXSW_ITEM32(reg, sbpr, infi_size, 0x04, 31, 1); 10911 10912 /* reg_sbpr_size 10913 * Pool size in buffer cells. 10914 * Reserved when infi_size = 1. 10915 * Access: RW 10916 */ 10917 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24); 10918 10919 enum mlxsw_reg_sbpr_mode { 10920 MLXSW_REG_SBPR_MODE_STATIC, 10921 MLXSW_REG_SBPR_MODE_DYNAMIC, 10922 }; 10923 10924 /* reg_sbpr_mode 10925 * Pool quota calculation mode. 10926 * Access: RW 10927 */ 10928 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4); 10929 10930 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool, 10931 enum mlxsw_reg_sbxx_dir dir, 10932 enum mlxsw_reg_sbpr_mode mode, u32 size, 10933 bool infi_size) 10934 { 10935 MLXSW_REG_ZERO(sbpr, payload); 10936 mlxsw_reg_sbpr_pool_set(payload, pool); 10937 mlxsw_reg_sbpr_dir_set(payload, dir); 10938 mlxsw_reg_sbpr_mode_set(payload, mode); 10939 mlxsw_reg_sbpr_size_set(payload, size); 10940 mlxsw_reg_sbpr_infi_size_set(payload, infi_size); 10941 } 10942 10943 /* SBCM - Shared Buffer Class Management Register 10944 * ---------------------------------------------- 10945 * The SBCM register configures and retrieves the shared buffer allocation 10946 * and configuration according to Port-PG, including the binding to pool 10947 * and definition of the associated quota. 10948 */ 10949 #define MLXSW_REG_SBCM_ID 0xB002 10950 #define MLXSW_REG_SBCM_LEN 0x28 10951 10952 MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN); 10953 10954 /* reg_sbcm_local_port 10955 * Local port number. 10956 * For Ingress: excludes CPU port and Router port 10957 * For Egress: excludes IP Router 10958 * Access: Index 10959 */ 10960 MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8); 10961 10962 /* reg_sbcm_pg_buff 10963 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress) 10964 * For PG buffer: range is 0..cap_max_pg_buffers - 1 10965 * For traffic class: range is 0..cap_max_tclass - 1 10966 * Note that when traffic class is in MC aware mode then the traffic 10967 * classes which are MC aware cannot be configured. 10968 * Access: Index 10969 */ 10970 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6); 10971 10972 /* reg_sbcm_dir 10973 * Direction. 10974 * Access: Index 10975 */ 10976 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2); 10977 10978 /* reg_sbcm_min_buff 10979 * Minimum buffer size for the limiter, in cells. 10980 * Access: RW 10981 */ 10982 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24); 10983 10984 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */ 10985 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1 10986 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14 10987 10988 /* reg_sbcm_infi_max 10989 * Max buffer is infinite. 10990 * Access: RW 10991 */ 10992 MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1); 10993 10994 /* reg_sbcm_max_buff 10995 * When the pool associated to the port-pg/tclass is configured to 10996 * static, Maximum buffer size for the limiter configured in cells. 10997 * When the pool associated to the port-pg/tclass is configured to 10998 * dynamic, the max_buff holds the "alpha" parameter, supporting 10999 * the following values: 11000 * 0: 0 11001 * i: (1/128)*2^(i-1), for i=1..14 11002 * 0xFF: Infinity 11003 * Reserved when infi_max = 1. 11004 * Access: RW 11005 */ 11006 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24); 11007 11008 /* reg_sbcm_pool 11009 * Association of the port-priority to a pool. 11010 * Access: RW 11011 */ 11012 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4); 11013 11014 static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff, 11015 enum mlxsw_reg_sbxx_dir dir, 11016 u32 min_buff, u32 max_buff, 11017 bool infi_max, u8 pool) 11018 { 11019 MLXSW_REG_ZERO(sbcm, payload); 11020 mlxsw_reg_sbcm_local_port_set(payload, local_port); 11021 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff); 11022 mlxsw_reg_sbcm_dir_set(payload, dir); 11023 mlxsw_reg_sbcm_min_buff_set(payload, min_buff); 11024 mlxsw_reg_sbcm_max_buff_set(payload, max_buff); 11025 mlxsw_reg_sbcm_infi_max_set(payload, infi_max); 11026 mlxsw_reg_sbcm_pool_set(payload, pool); 11027 } 11028 11029 /* SBPM - Shared Buffer Port Management Register 11030 * --------------------------------------------- 11031 * The SBPM register configures and retrieves the shared buffer allocation 11032 * and configuration according to Port-Pool, including the definition 11033 * of the associated quota. 11034 */ 11035 #define MLXSW_REG_SBPM_ID 0xB003 11036 #define MLXSW_REG_SBPM_LEN 0x28 11037 11038 MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN); 11039 11040 /* reg_sbpm_local_port 11041 * Local port number. 11042 * For Ingress: excludes CPU port and Router port 11043 * For Egress: excludes IP Router 11044 * Access: Index 11045 */ 11046 MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8); 11047 11048 /* reg_sbpm_pool 11049 * The pool associated to quota counting on the local_port. 11050 * Access: Index 11051 */ 11052 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4); 11053 11054 /* reg_sbpm_dir 11055 * Direction. 11056 * Access: Index 11057 */ 11058 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2); 11059 11060 /* reg_sbpm_buff_occupancy 11061 * Current buffer occupancy in cells. 11062 * Access: RO 11063 */ 11064 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24); 11065 11066 /* reg_sbpm_clr 11067 * Clear Max Buffer Occupancy 11068 * When this bit is set, max_buff_occupancy field is cleared (and a 11069 * new max value is tracked from the time the clear was performed). 11070 * Access: OP 11071 */ 11072 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1); 11073 11074 /* reg_sbpm_max_buff_occupancy 11075 * Maximum value of buffer occupancy in cells monitored. Cleared by 11076 * writing to the clr field. 11077 * Access: RO 11078 */ 11079 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24); 11080 11081 /* reg_sbpm_min_buff 11082 * Minimum buffer size for the limiter, in cells. 11083 * Access: RW 11084 */ 11085 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24); 11086 11087 /* reg_sbpm_max_buff 11088 * When the pool associated to the port-pg/tclass is configured to 11089 * static, Maximum buffer size for the limiter configured in cells. 11090 * When the pool associated to the port-pg/tclass is configured to 11091 * dynamic, the max_buff holds the "alpha" parameter, supporting 11092 * the following values: 11093 * 0: 0 11094 * i: (1/128)*2^(i-1), for i=1..14 11095 * 0xFF: Infinity 11096 * Access: RW 11097 */ 11098 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24); 11099 11100 static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool, 11101 enum mlxsw_reg_sbxx_dir dir, bool clr, 11102 u32 min_buff, u32 max_buff) 11103 { 11104 MLXSW_REG_ZERO(sbpm, payload); 11105 mlxsw_reg_sbpm_local_port_set(payload, local_port); 11106 mlxsw_reg_sbpm_pool_set(payload, pool); 11107 mlxsw_reg_sbpm_dir_set(payload, dir); 11108 mlxsw_reg_sbpm_clr_set(payload, clr); 11109 mlxsw_reg_sbpm_min_buff_set(payload, min_buff); 11110 mlxsw_reg_sbpm_max_buff_set(payload, max_buff); 11111 } 11112 11113 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy, 11114 u32 *p_max_buff_occupancy) 11115 { 11116 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload); 11117 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload); 11118 } 11119 11120 /* SBMM - Shared Buffer Multicast Management Register 11121 * -------------------------------------------------- 11122 * The SBMM register configures and retrieves the shared buffer allocation 11123 * and configuration for MC packets according to Switch-Priority, including 11124 * the binding to pool and definition of the associated quota. 11125 */ 11126 #define MLXSW_REG_SBMM_ID 0xB004 11127 #define MLXSW_REG_SBMM_LEN 0x28 11128 11129 MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN); 11130 11131 /* reg_sbmm_prio 11132 * Switch Priority. 11133 * Access: Index 11134 */ 11135 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4); 11136 11137 /* reg_sbmm_min_buff 11138 * Minimum buffer size for the limiter, in cells. 11139 * Access: RW 11140 */ 11141 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24); 11142 11143 /* reg_sbmm_max_buff 11144 * When the pool associated to the port-pg/tclass is configured to 11145 * static, Maximum buffer size for the limiter configured in cells. 11146 * When the pool associated to the port-pg/tclass is configured to 11147 * dynamic, the max_buff holds the "alpha" parameter, supporting 11148 * the following values: 11149 * 0: 0 11150 * i: (1/128)*2^(i-1), for i=1..14 11151 * 0xFF: Infinity 11152 * Access: RW 11153 */ 11154 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24); 11155 11156 /* reg_sbmm_pool 11157 * Association of the port-priority to a pool. 11158 * Access: RW 11159 */ 11160 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4); 11161 11162 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff, 11163 u32 max_buff, u8 pool) 11164 { 11165 MLXSW_REG_ZERO(sbmm, payload); 11166 mlxsw_reg_sbmm_prio_set(payload, prio); 11167 mlxsw_reg_sbmm_min_buff_set(payload, min_buff); 11168 mlxsw_reg_sbmm_max_buff_set(payload, max_buff); 11169 mlxsw_reg_sbmm_pool_set(payload, pool); 11170 } 11171 11172 /* SBSR - Shared Buffer Status Register 11173 * ------------------------------------ 11174 * The SBSR register retrieves the shared buffer occupancy according to 11175 * Port-Pool. Note that this register enables reading a large amount of data. 11176 * It is the user's responsibility to limit the amount of data to ensure the 11177 * response can match the maximum transfer unit. In case the response exceeds 11178 * the maximum transport unit, it will be truncated with no special notice. 11179 */ 11180 #define MLXSW_REG_SBSR_ID 0xB005 11181 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */ 11182 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */ 11183 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120 11184 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \ 11185 MLXSW_REG_SBSR_REC_LEN * \ 11186 MLXSW_REG_SBSR_REC_MAX_COUNT) 11187 11188 MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN); 11189 11190 /* reg_sbsr_clr 11191 * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy 11192 * field is cleared (and a new max value is tracked from the time the clear 11193 * was performed). 11194 * Access: OP 11195 */ 11196 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1); 11197 11198 /* reg_sbsr_ingress_port_mask 11199 * Bit vector for all ingress network ports. 11200 * Indicates which of the ports (for which the relevant bit is set) 11201 * are affected by the set operation. Configuration of any other port 11202 * does not change. 11203 * Access: Index 11204 */ 11205 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1); 11206 11207 /* reg_sbsr_pg_buff_mask 11208 * Bit vector for all switch priority groups. 11209 * Indicates which of the priorities (for which the relevant bit is set) 11210 * are affected by the set operation. Configuration of any other priority 11211 * does not change. 11212 * Range is 0..cap_max_pg_buffers - 1 11213 * Access: Index 11214 */ 11215 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1); 11216 11217 /* reg_sbsr_egress_port_mask 11218 * Bit vector for all egress network ports. 11219 * Indicates which of the ports (for which the relevant bit is set) 11220 * are affected by the set operation. Configuration of any other port 11221 * does not change. 11222 * Access: Index 11223 */ 11224 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1); 11225 11226 /* reg_sbsr_tclass_mask 11227 * Bit vector for all traffic classes. 11228 * Indicates which of the traffic classes (for which the relevant bit is 11229 * set) are affected by the set operation. Configuration of any other 11230 * traffic class does not change. 11231 * Range is 0..cap_max_tclass - 1 11232 * Access: Index 11233 */ 11234 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1); 11235 11236 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr) 11237 { 11238 MLXSW_REG_ZERO(sbsr, payload); 11239 mlxsw_reg_sbsr_clr_set(payload, clr); 11240 } 11241 11242 /* reg_sbsr_rec_buff_occupancy 11243 * Current buffer occupancy in cells. 11244 * Access: RO 11245 */ 11246 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 11247 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false); 11248 11249 /* reg_sbsr_rec_max_buff_occupancy 11250 * Maximum value of buffer occupancy in cells monitored. Cleared by 11251 * writing to the clr field. 11252 * Access: RO 11253 */ 11254 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 11255 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false); 11256 11257 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index, 11258 u32 *p_buff_occupancy, 11259 u32 *p_max_buff_occupancy) 11260 { 11261 *p_buff_occupancy = 11262 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index); 11263 *p_max_buff_occupancy = 11264 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index); 11265 } 11266 11267 /* SBIB - Shared Buffer Internal Buffer Register 11268 * --------------------------------------------- 11269 * The SBIB register configures per port buffers for internal use. The internal 11270 * buffers consume memory on the port buffers (note that the port buffers are 11271 * used also by PBMC). 11272 * 11273 * For Spectrum this is used for egress mirroring. 11274 */ 11275 #define MLXSW_REG_SBIB_ID 0xB006 11276 #define MLXSW_REG_SBIB_LEN 0x10 11277 11278 MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN); 11279 11280 /* reg_sbib_local_port 11281 * Local port number 11282 * Not supported for CPU port and router port 11283 * Access: Index 11284 */ 11285 MLXSW_ITEM32(reg, sbib, local_port, 0x00, 16, 8); 11286 11287 /* reg_sbib_buff_size 11288 * Units represented in cells 11289 * Allowed range is 0 to (cap_max_headroom_size - 1) 11290 * Default is 0 11291 * Access: RW 11292 */ 11293 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24); 11294 11295 static inline void mlxsw_reg_sbib_pack(char *payload, u8 local_port, 11296 u32 buff_size) 11297 { 11298 MLXSW_REG_ZERO(sbib, payload); 11299 mlxsw_reg_sbib_local_port_set(payload, local_port); 11300 mlxsw_reg_sbib_buff_size_set(payload, buff_size); 11301 } 11302 11303 static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { 11304 MLXSW_REG(sgcr), 11305 MLXSW_REG(spad), 11306 MLXSW_REG(smid), 11307 MLXSW_REG(sspr), 11308 MLXSW_REG(sfdat), 11309 MLXSW_REG(sfd), 11310 MLXSW_REG(sfn), 11311 MLXSW_REG(spms), 11312 MLXSW_REG(spvid), 11313 MLXSW_REG(spvm), 11314 MLXSW_REG(spaft), 11315 MLXSW_REG(sfgc), 11316 MLXSW_REG(sftr), 11317 MLXSW_REG(sfdf), 11318 MLXSW_REG(sldr), 11319 MLXSW_REG(slcr), 11320 MLXSW_REG(slcor), 11321 MLXSW_REG(spmlr), 11322 MLXSW_REG(svfa), 11323 MLXSW_REG(svpe), 11324 MLXSW_REG(sfmr), 11325 MLXSW_REG(spvmlr), 11326 MLXSW_REG(spvc), 11327 MLXSW_REG(cwtp), 11328 MLXSW_REG(cwtpm), 11329 MLXSW_REG(pgcr), 11330 MLXSW_REG(ppbt), 11331 MLXSW_REG(pacl), 11332 MLXSW_REG(pagt), 11333 MLXSW_REG(ptar), 11334 MLXSW_REG(ppbs), 11335 MLXSW_REG(prcr), 11336 MLXSW_REG(pefa), 11337 MLXSW_REG(pemrbt), 11338 MLXSW_REG(ptce2), 11339 MLXSW_REG(perpt), 11340 MLXSW_REG(peabfe), 11341 MLXSW_REG(perar), 11342 MLXSW_REG(ptce3), 11343 MLXSW_REG(percr), 11344 MLXSW_REG(pererp), 11345 MLXSW_REG(iedr), 11346 MLXSW_REG(qpts), 11347 MLXSW_REG(qpcr), 11348 MLXSW_REG(qtct), 11349 MLXSW_REG(qeec), 11350 MLXSW_REG(qrwe), 11351 MLXSW_REG(qpdsm), 11352 MLXSW_REG(qpdp), 11353 MLXSW_REG(qpdpm), 11354 MLXSW_REG(qtctm), 11355 MLXSW_REG(qpsc), 11356 MLXSW_REG(pmlp), 11357 MLXSW_REG(pmtu), 11358 MLXSW_REG(ptys), 11359 MLXSW_REG(ppad), 11360 MLXSW_REG(paos), 11361 MLXSW_REG(pfcc), 11362 MLXSW_REG(ppcnt), 11363 MLXSW_REG(plib), 11364 MLXSW_REG(pptb), 11365 MLXSW_REG(pbmc), 11366 MLXSW_REG(pspa), 11367 MLXSW_REG(pmaos), 11368 MLXSW_REG(pplr), 11369 MLXSW_REG(pmpe), 11370 MLXSW_REG(pddr), 11371 MLXSW_REG(pmtm), 11372 MLXSW_REG(htgt), 11373 MLXSW_REG(hpkt), 11374 MLXSW_REG(rgcr), 11375 MLXSW_REG(ritr), 11376 MLXSW_REG(rtar), 11377 MLXSW_REG(ratr), 11378 MLXSW_REG(rtdp), 11379 MLXSW_REG(rdpm), 11380 MLXSW_REG(ricnt), 11381 MLXSW_REG(rrcr), 11382 MLXSW_REG(ralta), 11383 MLXSW_REG(ralst), 11384 MLXSW_REG(raltb), 11385 MLXSW_REG(ralue), 11386 MLXSW_REG(rauht), 11387 MLXSW_REG(raleu), 11388 MLXSW_REG(rauhtd), 11389 MLXSW_REG(rigr2), 11390 MLXSW_REG(recr2), 11391 MLXSW_REG(rmft2), 11392 MLXSW_REG(xralta), 11393 MLXSW_REG(xralst), 11394 MLXSW_REG(xraltb), 11395 MLXSW_REG(mfcr), 11396 MLXSW_REG(mfsc), 11397 MLXSW_REG(mfsm), 11398 MLXSW_REG(mfsl), 11399 MLXSW_REG(fore), 11400 MLXSW_REG(mtcap), 11401 MLXSW_REG(mtmp), 11402 MLXSW_REG(mtwe), 11403 MLXSW_REG(mtbr), 11404 MLXSW_REG(mcia), 11405 MLXSW_REG(mpat), 11406 MLXSW_REG(mpar), 11407 MLXSW_REG(mgir), 11408 MLXSW_REG(mrsr), 11409 MLXSW_REG(mlcr), 11410 MLXSW_REG(mtpps), 11411 MLXSW_REG(mtutc), 11412 MLXSW_REG(mpsc), 11413 MLXSW_REG(mcqi), 11414 MLXSW_REG(mcc), 11415 MLXSW_REG(mcda), 11416 MLXSW_REG(mgpc), 11417 MLXSW_REG(mprs), 11418 MLXSW_REG(mogcr), 11419 MLXSW_REG(mpagr), 11420 MLXSW_REG(momte), 11421 MLXSW_REG(mtpppc), 11422 MLXSW_REG(mtpptr), 11423 MLXSW_REG(mtptpt), 11424 MLXSW_REG(mfgd), 11425 MLXSW_REG(mgpir), 11426 MLXSW_REG(mfde), 11427 MLXSW_REG(tngcr), 11428 MLXSW_REG(tnumt), 11429 MLXSW_REG(tnqcr), 11430 MLXSW_REG(tnqdr), 11431 MLXSW_REG(tneem), 11432 MLXSW_REG(tndem), 11433 MLXSW_REG(tnpc), 11434 MLXSW_REG(tigcr), 11435 MLXSW_REG(tieem), 11436 MLXSW_REG(tidem), 11437 MLXSW_REG(sbpr), 11438 MLXSW_REG(sbcm), 11439 MLXSW_REG(sbpm), 11440 MLXSW_REG(sbmm), 11441 MLXSW_REG(sbsr), 11442 MLXSW_REG(sbib), 11443 }; 11444 11445 static inline const char *mlxsw_reg_id_str(u16 reg_id) 11446 { 11447 const struct mlxsw_reg_info *reg_info; 11448 int i; 11449 11450 for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) { 11451 reg_info = mlxsw_reg_infos[i]; 11452 if (reg_info->id == reg_id) 11453 return reg_info->name; 11454 } 11455 return "*UNKNOWN*"; 11456 } 11457 11458 /* PUDE - Port Up / Down Event 11459 * --------------------------- 11460 * Reports the operational state change of a port. 11461 */ 11462 #define MLXSW_REG_PUDE_LEN 0x10 11463 11464 /* reg_pude_swid 11465 * Switch partition ID with which to associate the port. 11466 * Access: Index 11467 */ 11468 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8); 11469 11470 /* reg_pude_local_port 11471 * Local port number. 11472 * Access: Index 11473 */ 11474 MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8); 11475 11476 /* reg_pude_admin_status 11477 * Port administrative state (the desired state). 11478 * 1 - Up. 11479 * 2 - Down. 11480 * 3 - Up once. This means that in case of link failure, the port won't go 11481 * into polling mode, but will wait to be re-enabled by software. 11482 * 4 - Disabled by system. Can only be set by hardware. 11483 * Access: RO 11484 */ 11485 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4); 11486 11487 /* reg_pude_oper_status 11488 * Port operatioanl state. 11489 * 1 - Up. 11490 * 2 - Down. 11491 * 3 - Down by port failure. This means that the device will not let the 11492 * port up again until explicitly specified by software. 11493 * Access: RO 11494 */ 11495 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4); 11496 11497 #endif 11498