1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #ifndef _MLXSW_REG_H 5 #define _MLXSW_REG_H 6 7 #include <linux/kernel.h> 8 #include <linux/string.h> 9 #include <linux/bitops.h> 10 #include <linux/if_vlan.h> 11 12 #include "item.h" 13 #include "port.h" 14 15 struct mlxsw_reg_info { 16 u16 id; 17 u16 len; /* In u8 */ 18 const char *name; 19 }; 20 21 #define MLXSW_REG_DEFINE(_name, _id, _len) \ 22 static const struct mlxsw_reg_info mlxsw_reg_##_name = { \ 23 .id = _id, \ 24 .len = _len, \ 25 .name = #_name, \ 26 } 27 28 #define MLXSW_REG(type) (&mlxsw_reg_##type) 29 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len 30 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len) 31 32 /* SGCR - Switch General Configuration Register 33 * -------------------------------------------- 34 * This register is used for configuration of the switch capabilities. 35 */ 36 #define MLXSW_REG_SGCR_ID 0x2000 37 #define MLXSW_REG_SGCR_LEN 0x10 38 39 MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN); 40 41 /* reg_sgcr_llb 42 * Link Local Broadcast (Default=0) 43 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast 44 * packets and ignore the IGMP snooping entries. 45 * Access: RW 46 */ 47 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1); 48 49 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb) 50 { 51 MLXSW_REG_ZERO(sgcr, payload); 52 mlxsw_reg_sgcr_llb_set(payload, !!llb); 53 } 54 55 /* SPAD - Switch Physical Address Register 56 * --------------------------------------- 57 * The SPAD register configures the switch physical MAC address. 58 */ 59 #define MLXSW_REG_SPAD_ID 0x2002 60 #define MLXSW_REG_SPAD_LEN 0x10 61 62 MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN); 63 64 /* reg_spad_base_mac 65 * Base MAC address for the switch partitions. 66 * Per switch partition MAC address is equal to: 67 * base_mac + swid 68 * Access: RW 69 */ 70 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6); 71 72 /* SSPR - Switch System Port Record Register 73 * ----------------------------------------- 74 * Configures the system port to local port mapping. 75 */ 76 #define MLXSW_REG_SSPR_ID 0x2008 77 #define MLXSW_REG_SSPR_LEN 0x8 78 79 MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN); 80 81 /* reg_sspr_m 82 * Master - if set, then the record describes the master system port. 83 * This is needed in case a local port is mapped into several system ports 84 * (for multipathing). That number will be reported as the source system 85 * port when packets are forwarded to the CPU. Only one master port is allowed 86 * per local port. 87 * 88 * Note: Must be set for Spectrum. 89 * Access: RW 90 */ 91 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1); 92 93 /* reg_sspr_local_port 94 * Local port number. 95 * 96 * Access: RW 97 */ 98 MLXSW_ITEM32_LP(reg, sspr, 0x00, 16, 0x00, 12); 99 100 /* reg_sspr_system_port 101 * Unique identifier within the stacking domain that represents all the ports 102 * that are available in the system (external ports). 103 * 104 * Currently, only single-ASIC configurations are supported, so we default to 105 * 1:1 mapping between system ports and local ports. 106 * Access: Index 107 */ 108 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16); 109 110 static inline void mlxsw_reg_sspr_pack(char *payload, u16 local_port) 111 { 112 MLXSW_REG_ZERO(sspr, payload); 113 mlxsw_reg_sspr_m_set(payload, 1); 114 mlxsw_reg_sspr_local_port_set(payload, local_port); 115 mlxsw_reg_sspr_system_port_set(payload, local_port); 116 } 117 118 /* SFDAT - Switch Filtering Database Aging Time 119 * -------------------------------------------- 120 * Controls the Switch aging time. Aging time is able to be set per Switch 121 * Partition. 122 */ 123 #define MLXSW_REG_SFDAT_ID 0x2009 124 #define MLXSW_REG_SFDAT_LEN 0x8 125 126 MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN); 127 128 /* reg_sfdat_swid 129 * Switch partition ID. 130 * Access: Index 131 */ 132 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8); 133 134 /* reg_sfdat_age_time 135 * Aging time in seconds 136 * Min - 10 seconds 137 * Max - 1,000,000 seconds 138 * Default is 300 seconds. 139 * Access: RW 140 */ 141 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20); 142 143 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time) 144 { 145 MLXSW_REG_ZERO(sfdat, payload); 146 mlxsw_reg_sfdat_swid_set(payload, 0); 147 mlxsw_reg_sfdat_age_time_set(payload, age_time); 148 } 149 150 /* SFD - Switch Filtering Database 151 * ------------------------------- 152 * The following register defines the access to the filtering database. 153 * The register supports querying, adding, removing and modifying the database. 154 * The access is optimized for bulk updates in which case more than one 155 * FDB record is present in the same command. 156 */ 157 #define MLXSW_REG_SFD_ID 0x200A 158 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */ 159 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */ 160 #define MLXSW_REG_SFD_REC_MAX_COUNT 64 161 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \ 162 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT) 163 164 MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN); 165 166 /* reg_sfd_swid 167 * Switch partition ID for queries. Reserved on Write. 168 * Access: Index 169 */ 170 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8); 171 172 enum mlxsw_reg_sfd_op { 173 /* Dump entire FDB a (process according to record_locator) */ 174 MLXSW_REG_SFD_OP_QUERY_DUMP = 0, 175 /* Query records by {MAC, VID/FID} value */ 176 MLXSW_REG_SFD_OP_QUERY_QUERY = 1, 177 /* Query and clear activity. Query records by {MAC, VID/FID} value */ 178 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2, 179 /* Test. Response indicates if each of the records could be 180 * added to the FDB. 181 */ 182 MLXSW_REG_SFD_OP_WRITE_TEST = 0, 183 /* Add/modify. Aged-out records cannot be added. This command removes 184 * the learning notification of the {MAC, VID/FID}. Response includes 185 * the entries that were added to the FDB. 186 */ 187 MLXSW_REG_SFD_OP_WRITE_EDIT = 1, 188 /* Remove record by {MAC, VID/FID}. This command also removes 189 * the learning notification and aged-out notifications 190 * of the {MAC, VID/FID}. The response provides current (pre-removal) 191 * entries as non-aged-out. 192 */ 193 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2, 194 /* Remove learned notification by {MAC, VID/FID}. The response provides 195 * the removed learning notification. 196 */ 197 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2, 198 }; 199 200 /* reg_sfd_op 201 * Operation. 202 * Access: OP 203 */ 204 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2); 205 206 /* reg_sfd_record_locator 207 * Used for querying the FDB. Use record_locator=0 to initiate the 208 * query. When a record is returned, a new record_locator is 209 * returned to be used in the subsequent query. 210 * Reserved for database update. 211 * Access: Index 212 */ 213 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30); 214 215 /* reg_sfd_num_rec 216 * Request: Number of records to read/add/modify/remove 217 * Response: Number of records read/added/replaced/removed 218 * See above description for more details. 219 * Ranges 0..64 220 * Access: RW 221 */ 222 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8); 223 224 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op, 225 u32 record_locator) 226 { 227 MLXSW_REG_ZERO(sfd, payload); 228 mlxsw_reg_sfd_op_set(payload, op); 229 mlxsw_reg_sfd_record_locator_set(payload, record_locator); 230 } 231 232 /* reg_sfd_rec_swid 233 * Switch partition ID. 234 * Access: Index 235 */ 236 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8, 237 MLXSW_REG_SFD_REC_LEN, 0x00, false); 238 239 enum mlxsw_reg_sfd_rec_type { 240 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0, 241 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1, 242 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2, 243 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL = 0xC, 244 }; 245 246 /* reg_sfd_rec_type 247 * FDB record type. 248 * Access: RW 249 */ 250 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4, 251 MLXSW_REG_SFD_REC_LEN, 0x00, false); 252 253 enum mlxsw_reg_sfd_rec_policy { 254 /* Replacement disabled, aging disabled. */ 255 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0, 256 /* (mlag remote): Replacement enabled, aging disabled, 257 * learning notification enabled on this port. 258 */ 259 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1, 260 /* (ingress device): Replacement enabled, aging enabled. */ 261 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3, 262 }; 263 264 /* reg_sfd_rec_policy 265 * Policy. 266 * Access: RW 267 */ 268 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2, 269 MLXSW_REG_SFD_REC_LEN, 0x00, false); 270 271 /* reg_sfd_rec_a 272 * Activity. Set for new static entries. Set for static entries if a frame SMAC 273 * lookup hits on the entry. 274 * To clear the a bit, use "query and clear activity" op. 275 * Access: RO 276 */ 277 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1, 278 MLXSW_REG_SFD_REC_LEN, 0x00, false); 279 280 /* reg_sfd_rec_mac 281 * MAC address. 282 * Access: Index 283 */ 284 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6, 285 MLXSW_REG_SFD_REC_LEN, 0x02); 286 287 enum mlxsw_reg_sfd_rec_action { 288 /* forward */ 289 MLXSW_REG_SFD_REC_ACTION_NOP = 0, 290 /* forward and trap, trap_id is FDB_TRAP */ 291 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1, 292 /* trap and do not forward, trap_id is FDB_TRAP */ 293 MLXSW_REG_SFD_REC_ACTION_TRAP = 2, 294 /* forward to IP router */ 295 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3, 296 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15, 297 }; 298 299 /* reg_sfd_rec_action 300 * Action to apply on the packet. 301 * Note: Dynamic entries can only be configured with NOP action. 302 * Access: RW 303 */ 304 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4, 305 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 306 307 /* reg_sfd_uc_sub_port 308 * VEPA channel on local port. 309 * Valid only if local port is a non-stacking port. Must be 0 if multichannel 310 * VEPA is not enabled. 311 * Access: RW 312 */ 313 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 314 MLXSW_REG_SFD_REC_LEN, 0x08, false); 315 316 /* reg_sfd_uc_set_vid 317 * Set VID. 318 * 0 - Do not update VID. 319 * 1 - Set VID. 320 * For Spectrum-2 when set_vid=0 and smpe_valid=1, the smpe will modify the vid. 321 * Access: RW 322 * 323 * Note: Reserved when legacy bridge model is used. 324 */ 325 MLXSW_ITEM32_INDEXED(reg, sfd, uc_set_vid, MLXSW_REG_SFD_BASE_LEN, 31, 1, 326 MLXSW_REG_SFD_REC_LEN, 0x08, false); 327 328 /* reg_sfd_uc_fid_vid 329 * Filtering ID or VLAN ID 330 * For SwitchX and SwitchX-2: 331 * - Dynamic entries (policy 2,3) use FID 332 * - Static entries (policy 0) use VID 333 * - When independent learning is configured, VID=FID 334 * For Spectrum: use FID for both Dynamic and Static entries. 335 * VID should not be used. 336 * Access: Index 337 */ 338 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 339 MLXSW_REG_SFD_REC_LEN, 0x08, false); 340 341 /* reg_sfd_uc_vid 342 * New VID when set_vid=1. 343 * Access: RW 344 * 345 * Note: Reserved when legacy bridge model is used and when set_vid=0. 346 */ 347 MLXSW_ITEM32_INDEXED(reg, sfd, uc_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, 348 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 349 350 /* reg_sfd_uc_system_port 351 * Unique port identifier for the final destination of the packet. 352 * Access: RW 353 */ 354 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16, 355 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 356 357 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index, 358 enum mlxsw_reg_sfd_rec_type rec_type, 359 const char *mac, 360 enum mlxsw_reg_sfd_rec_action action) 361 { 362 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload); 363 364 if (rec_index >= num_rec) 365 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1); 366 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0); 367 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type); 368 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac); 369 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action); 370 } 371 372 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index, 373 enum mlxsw_reg_sfd_rec_policy policy, 374 const char *mac, u16 fid_vid, u16 vid, 375 enum mlxsw_reg_sfd_rec_action action, 376 u16 local_port) 377 { 378 mlxsw_reg_sfd_rec_pack(payload, rec_index, 379 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action); 380 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 381 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0); 382 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid); 383 mlxsw_reg_sfd_uc_set_vid_set(payload, rec_index, vid ? true : false); 384 mlxsw_reg_sfd_uc_vid_set(payload, rec_index, vid); 385 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port); 386 } 387 388 /* reg_sfd_uc_lag_sub_port 389 * LAG sub port. 390 * Must be 0 if multichannel VEPA is not enabled. 391 * Access: RW 392 */ 393 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 394 MLXSW_REG_SFD_REC_LEN, 0x08, false); 395 396 /* reg_sfd_uc_lag_set_vid 397 * Set VID. 398 * 0 - Do not update VID. 399 * 1 - Set VID. 400 * For Spectrum-2 when set_vid=0 and smpe_valid=1, the smpe will modify the vid. 401 * Access: RW 402 * 403 * Note: Reserved when legacy bridge model is used. 404 */ 405 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_set_vid, MLXSW_REG_SFD_BASE_LEN, 31, 1, 406 MLXSW_REG_SFD_REC_LEN, 0x08, false); 407 408 /* reg_sfd_uc_lag_fid_vid 409 * Filtering ID or VLAN ID 410 * For SwitchX and SwitchX-2: 411 * - Dynamic entries (policy 2,3) use FID 412 * - Static entries (policy 0) use VID 413 * - When independent learning is configured, VID=FID 414 * For Spectrum: use FID for both Dynamic and Static entries. 415 * VID should not be used. 416 * Access: Index 417 */ 418 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 419 MLXSW_REG_SFD_REC_LEN, 0x08, false); 420 421 /* reg_sfd_uc_lag_lag_vid 422 * New vlan ID. 423 * Access: RW 424 * 425 * Note: Reserved when legacy bridge model is used and set_vid=0. 426 */ 427 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, 428 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 429 430 /* reg_sfd_uc_lag_lag_id 431 * LAG Identifier - pointer into the LAG descriptor table. 432 * Access: RW 433 */ 434 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10, 435 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 436 437 static inline void 438 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index, 439 enum mlxsw_reg_sfd_rec_policy policy, 440 const char *mac, u16 fid_vid, 441 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid, 442 u16 lag_id) 443 { 444 mlxsw_reg_sfd_rec_pack(payload, rec_index, 445 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG, 446 mac, action); 447 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 448 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0); 449 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid); 450 mlxsw_reg_sfd_uc_lag_set_vid_set(payload, rec_index, true); 451 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid); 452 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id); 453 } 454 455 /* reg_sfd_mc_pgi 456 * 457 * Multicast port group index - index into the port group table. 458 * Value 0x1FFF indicates the pgi should point to the MID entry. 459 * For Spectrum this value must be set to 0x1FFF 460 * Access: RW 461 */ 462 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13, 463 MLXSW_REG_SFD_REC_LEN, 0x08, false); 464 465 /* reg_sfd_mc_fid_vid 466 * 467 * Filtering ID or VLAN ID 468 * Access: Index 469 */ 470 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 471 MLXSW_REG_SFD_REC_LEN, 0x08, false); 472 473 /* reg_sfd_mc_mid 474 * 475 * Multicast identifier - global identifier that represents the multicast 476 * group across all devices. 477 * Access: RW 478 */ 479 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 480 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 481 482 static inline void 483 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index, 484 const char *mac, u16 fid_vid, 485 enum mlxsw_reg_sfd_rec_action action, u16 mid) 486 { 487 mlxsw_reg_sfd_rec_pack(payload, rec_index, 488 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action); 489 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF); 490 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid); 491 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid); 492 } 493 494 /* reg_sfd_uc_tunnel_uip_msb 495 * When protocol is IPv4, the most significant byte of the underlay IPv4 496 * destination IP. 497 * When protocol is IPv6, reserved. 498 * Access: RW 499 */ 500 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24, 501 8, MLXSW_REG_SFD_REC_LEN, 0x08, false); 502 503 /* reg_sfd_uc_tunnel_fid 504 * Filtering ID. 505 * Access: Index 506 */ 507 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 508 MLXSW_REG_SFD_REC_LEN, 0x08, false); 509 510 enum mlxsw_reg_sfd_uc_tunnel_protocol { 511 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4, 512 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6, 513 }; 514 515 /* reg_sfd_uc_tunnel_protocol 516 * IP protocol. 517 * Access: RW 518 */ 519 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27, 520 1, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 521 522 /* reg_sfd_uc_tunnel_uip_lsb 523 * When protocol is IPv4, the least significant bytes of the underlay 524 * IPv4 destination IP. 525 * When protocol is IPv6, pointer to the underlay IPv6 destination IP 526 * which is configured by RIPS. 527 * Access: RW 528 */ 529 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0, 530 24, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 531 532 static inline void 533 mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index, 534 enum mlxsw_reg_sfd_rec_policy policy, 535 const char *mac, u16 fid, 536 enum mlxsw_reg_sfd_rec_action action, 537 enum mlxsw_reg_sfd_uc_tunnel_protocol proto) 538 { 539 mlxsw_reg_sfd_rec_pack(payload, rec_index, 540 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL, mac, 541 action); 542 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 543 mlxsw_reg_sfd_uc_tunnel_fid_set(payload, rec_index, fid); 544 mlxsw_reg_sfd_uc_tunnel_protocol_set(payload, rec_index, proto); 545 } 546 547 static inline void 548 mlxsw_reg_sfd_uc_tunnel_pack4(char *payload, int rec_index, 549 enum mlxsw_reg_sfd_rec_policy policy, 550 const char *mac, u16 fid, 551 enum mlxsw_reg_sfd_rec_action action, u32 uip) 552 { 553 mlxsw_reg_sfd_uc_tunnel_uip_msb_set(payload, rec_index, uip >> 24); 554 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip); 555 mlxsw_reg_sfd_uc_tunnel_pack(payload, rec_index, policy, mac, fid, 556 action, 557 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4); 558 } 559 560 static inline void 561 mlxsw_reg_sfd_uc_tunnel_pack6(char *payload, int rec_index, const char *mac, 562 u16 fid, enum mlxsw_reg_sfd_rec_action action, 563 u32 uip_ptr) 564 { 565 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip_ptr); 566 /* Only static policy is supported for IPv6 unicast tunnel entry. */ 567 mlxsw_reg_sfd_uc_tunnel_pack(payload, rec_index, 568 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY, 569 mac, fid, action, 570 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6); 571 } 572 573 enum mlxsw_reg_tunnel_port { 574 MLXSW_REG_TUNNEL_PORT_NVE, 575 MLXSW_REG_TUNNEL_PORT_VPLS, 576 MLXSW_REG_TUNNEL_PORT_FLEX_TUNNEL0, 577 MLXSW_REG_TUNNEL_PORT_FLEX_TUNNEL1, 578 }; 579 580 /* SFN - Switch FDB Notification Register 581 * ------------------------------------------- 582 * The switch provides notifications on newly learned FDB entries and 583 * aged out entries. The notifications can be polled by software. 584 */ 585 #define MLXSW_REG_SFN_ID 0x200B 586 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */ 587 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */ 588 #define MLXSW_REG_SFN_REC_MAX_COUNT 64 589 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \ 590 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT) 591 592 MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN); 593 594 /* reg_sfn_swid 595 * Switch partition ID. 596 * Access: Index 597 */ 598 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8); 599 600 /* reg_sfn_end 601 * Forces the current session to end. 602 * Access: OP 603 */ 604 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1); 605 606 /* reg_sfn_num_rec 607 * Request: Number of learned notifications and aged-out notification 608 * records requested. 609 * Response: Number of notification records returned (must be smaller 610 * than or equal to the value requested) 611 * Ranges 0..64 612 * Access: OP 613 */ 614 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8); 615 616 static inline void mlxsw_reg_sfn_pack(char *payload) 617 { 618 MLXSW_REG_ZERO(sfn, payload); 619 mlxsw_reg_sfn_swid_set(payload, 0); 620 mlxsw_reg_sfn_end_set(payload, 0); 621 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT); 622 } 623 624 /* reg_sfn_rec_swid 625 * Switch partition ID. 626 * Access: RO 627 */ 628 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8, 629 MLXSW_REG_SFN_REC_LEN, 0x00, false); 630 631 enum mlxsw_reg_sfn_rec_type { 632 /* MAC addresses learned on a regular port. */ 633 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5, 634 /* MAC addresses learned on a LAG port. */ 635 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6, 636 /* Aged-out MAC address on a regular port. */ 637 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7, 638 /* Aged-out MAC address on a LAG port. */ 639 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8, 640 /* Learned unicast tunnel record. */ 641 MLXSW_REG_SFN_REC_TYPE_LEARNED_UNICAST_TUNNEL = 0xD, 642 /* Aged-out unicast tunnel record. */ 643 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_UNICAST_TUNNEL = 0xE, 644 }; 645 646 /* reg_sfn_rec_type 647 * Notification record type. 648 * Access: RO 649 */ 650 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4, 651 MLXSW_REG_SFN_REC_LEN, 0x00, false); 652 653 /* reg_sfn_rec_mac 654 * MAC address. 655 * Access: RO 656 */ 657 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6, 658 MLXSW_REG_SFN_REC_LEN, 0x02); 659 660 /* reg_sfn_mac_sub_port 661 * VEPA channel on the local port. 662 * 0 if multichannel VEPA is not enabled. 663 * Access: RO 664 */ 665 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8, 666 MLXSW_REG_SFN_REC_LEN, 0x08, false); 667 668 /* reg_sfn_mac_fid 669 * Filtering identifier. 670 * Access: RO 671 */ 672 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16, 673 MLXSW_REG_SFN_REC_LEN, 0x08, false); 674 675 /* reg_sfn_mac_system_port 676 * Unique port identifier for the final destination of the packet. 677 * Access: RO 678 */ 679 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16, 680 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 681 682 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index, 683 char *mac, u16 *p_vid, 684 u16 *p_local_port) 685 { 686 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 687 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 688 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index); 689 } 690 691 /* reg_sfn_mac_lag_lag_id 692 * LAG ID (pointer into the LAG descriptor table). 693 * Access: RO 694 */ 695 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10, 696 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 697 698 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index, 699 char *mac, u16 *p_vid, 700 u16 *p_lag_id) 701 { 702 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 703 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 704 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index); 705 } 706 707 /* reg_sfn_uc_tunnel_uip_msb 708 * When protocol is IPv4, the most significant byte of the underlay IPv4 709 * address of the remote VTEP. 710 * When protocol is IPv6, reserved. 711 * Access: RO 712 */ 713 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_msb, MLXSW_REG_SFN_BASE_LEN, 24, 714 8, MLXSW_REG_SFN_REC_LEN, 0x08, false); 715 716 enum mlxsw_reg_sfn_uc_tunnel_protocol { 717 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV4, 718 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV6, 719 }; 720 721 /* reg_sfn_uc_tunnel_protocol 722 * IP protocol. 723 * Access: RO 724 */ 725 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_protocol, MLXSW_REG_SFN_BASE_LEN, 27, 726 1, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 727 728 /* reg_sfn_uc_tunnel_uip_lsb 729 * When protocol is IPv4, the least significant bytes of the underlay 730 * IPv4 address of the remote VTEP. 731 * When protocol is IPv6, ipv6_id to be queried from TNIPSD. 732 * Access: RO 733 */ 734 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0, 735 24, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 736 737 /* reg_sfn_uc_tunnel_port 738 * Tunnel port. 739 * Reserved on Spectrum. 740 * Access: RO 741 */ 742 MLXSW_ITEM32_INDEXED(reg, sfn, tunnel_port, MLXSW_REG_SFN_BASE_LEN, 0, 4, 743 MLXSW_REG_SFN_REC_LEN, 0x10, false); 744 745 static inline void 746 mlxsw_reg_sfn_uc_tunnel_unpack(char *payload, int rec_index, char *mac, 747 u16 *p_fid, u32 *p_uip, 748 enum mlxsw_reg_sfn_uc_tunnel_protocol *p_proto) 749 { 750 u32 uip_msb, uip_lsb; 751 752 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 753 *p_fid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 754 uip_msb = mlxsw_reg_sfn_uc_tunnel_uip_msb_get(payload, rec_index); 755 uip_lsb = mlxsw_reg_sfn_uc_tunnel_uip_lsb_get(payload, rec_index); 756 *p_uip = uip_msb << 24 | uip_lsb; 757 *p_proto = mlxsw_reg_sfn_uc_tunnel_protocol_get(payload, rec_index); 758 } 759 760 /* SPMS - Switch Port MSTP/RSTP State Register 761 * ------------------------------------------- 762 * Configures the spanning tree state of a physical port. 763 */ 764 #define MLXSW_REG_SPMS_ID 0x200D 765 #define MLXSW_REG_SPMS_LEN 0x404 766 767 MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN); 768 769 /* reg_spms_local_port 770 * Local port number. 771 * Access: Index 772 */ 773 MLXSW_ITEM32_LP(reg, spms, 0x00, 16, 0x00, 12); 774 775 enum mlxsw_reg_spms_state { 776 MLXSW_REG_SPMS_STATE_NO_CHANGE, 777 MLXSW_REG_SPMS_STATE_DISCARDING, 778 MLXSW_REG_SPMS_STATE_LEARNING, 779 MLXSW_REG_SPMS_STATE_FORWARDING, 780 }; 781 782 /* reg_spms_state 783 * Spanning tree state of each VLAN ID (VID) of the local port. 784 * 0 - Do not change spanning tree state (used only when writing). 785 * 1 - Discarding. No learning or forwarding to/from this port (default). 786 * 2 - Learning. Port is learning, but not forwarding. 787 * 3 - Forwarding. Port is learning and forwarding. 788 * Access: RW 789 */ 790 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2); 791 792 static inline void mlxsw_reg_spms_pack(char *payload, u16 local_port) 793 { 794 MLXSW_REG_ZERO(spms, payload); 795 mlxsw_reg_spms_local_port_set(payload, local_port); 796 } 797 798 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid, 799 enum mlxsw_reg_spms_state state) 800 { 801 mlxsw_reg_spms_state_set(payload, vid, state); 802 } 803 804 /* SPVID - Switch Port VID 805 * ----------------------- 806 * The switch port VID configures the default VID for a port. 807 */ 808 #define MLXSW_REG_SPVID_ID 0x200E 809 #define MLXSW_REG_SPVID_LEN 0x08 810 811 MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN); 812 813 /* reg_spvid_tport 814 * Port is tunnel port. 815 * Reserved when SwitchX/-2 or Spectrum-1. 816 * Access: Index 817 */ 818 MLXSW_ITEM32(reg, spvid, tport, 0x00, 24, 1); 819 820 /* reg_spvid_local_port 821 * When tport = 0: Local port number. Not supported for CPU port. 822 * When tport = 1: Tunnel port. 823 * Access: Index 824 */ 825 MLXSW_ITEM32_LP(reg, spvid, 0x00, 16, 0x00, 12); 826 827 /* reg_spvid_sub_port 828 * Virtual port within the physical port. 829 * Should be set to 0 when virtual ports are not enabled on the port. 830 * Access: Index 831 */ 832 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8); 833 834 /* reg_spvid_egr_et_set 835 * When VLAN is pushed at ingress (for untagged packets or for 836 * QinQ push mode) then the EtherType is decided at the egress port. 837 * Reserved when Spectrum-1. 838 * Access: RW 839 */ 840 MLXSW_ITEM32(reg, spvid, egr_et_set, 0x04, 24, 1); 841 842 /* reg_spvid_et_vlan 843 * EtherType used for when VLAN is pushed at ingress (for untagged 844 * packets or for QinQ push mode). 845 * 0: ether_type0 - (default) 846 * 1: ether_type1 847 * 2: ether_type2 - Reserved when Spectrum-1, supported by Spectrum-2 848 * Ethertype IDs are configured by SVER. 849 * Reserved when egr_et_set = 1. 850 * Access: RW 851 */ 852 MLXSW_ITEM32(reg, spvid, et_vlan, 0x04, 16, 2); 853 854 /* reg_spvid_pvid 855 * Port default VID 856 * Access: RW 857 */ 858 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12); 859 860 static inline void mlxsw_reg_spvid_pack(char *payload, u16 local_port, u16 pvid, 861 u8 et_vlan) 862 { 863 MLXSW_REG_ZERO(spvid, payload); 864 mlxsw_reg_spvid_local_port_set(payload, local_port); 865 mlxsw_reg_spvid_pvid_set(payload, pvid); 866 mlxsw_reg_spvid_et_vlan_set(payload, et_vlan); 867 } 868 869 /* SPVM - Switch Port VLAN Membership 870 * ---------------------------------- 871 * The Switch Port VLAN Membership register configures the VLAN membership 872 * of a port in a VLAN denoted by VID. VLAN membership is managed per 873 * virtual port. The register can be used to add and remove VID(s) from a port. 874 */ 875 #define MLXSW_REG_SPVM_ID 0x200F 876 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */ 877 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */ 878 #define MLXSW_REG_SPVM_REC_MAX_COUNT 255 879 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \ 880 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT) 881 882 MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN); 883 884 /* reg_spvm_pt 885 * Priority tagged. If this bit is set, packets forwarded to the port with 886 * untagged VLAN membership (u bit is set) will be tagged with priority tag 887 * (VID=0) 888 * Access: RW 889 */ 890 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1); 891 892 /* reg_spvm_pte 893 * Priority Tagged Update Enable. On Write operations, if this bit is cleared, 894 * the pt bit will NOT be updated. To update the pt bit, pte must be set. 895 * Access: WO 896 */ 897 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1); 898 899 /* reg_spvm_local_port 900 * Local port number. 901 * Access: Index 902 */ 903 MLXSW_ITEM32_LP(reg, spvm, 0x00, 16, 0x00, 12); 904 905 /* reg_spvm_sub_port 906 * Virtual port within the physical port. 907 * Should be set to 0 when virtual ports are not enabled on the port. 908 * Access: Index 909 */ 910 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8); 911 912 /* reg_spvm_num_rec 913 * Number of records to update. Each record contains: i, e, u, vid. 914 * Access: OP 915 */ 916 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8); 917 918 /* reg_spvm_rec_i 919 * Ingress membership in VLAN ID. 920 * Access: Index 921 */ 922 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i, 923 MLXSW_REG_SPVM_BASE_LEN, 14, 1, 924 MLXSW_REG_SPVM_REC_LEN, 0, false); 925 926 /* reg_spvm_rec_e 927 * Egress membership in VLAN ID. 928 * Access: Index 929 */ 930 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e, 931 MLXSW_REG_SPVM_BASE_LEN, 13, 1, 932 MLXSW_REG_SPVM_REC_LEN, 0, false); 933 934 /* reg_spvm_rec_u 935 * Untagged - port is an untagged member - egress transmission uses untagged 936 * frames on VID<n> 937 * Access: Index 938 */ 939 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u, 940 MLXSW_REG_SPVM_BASE_LEN, 12, 1, 941 MLXSW_REG_SPVM_REC_LEN, 0, false); 942 943 /* reg_spvm_rec_vid 944 * Egress membership in VLAN ID. 945 * Access: Index 946 */ 947 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid, 948 MLXSW_REG_SPVM_BASE_LEN, 0, 12, 949 MLXSW_REG_SPVM_REC_LEN, 0, false); 950 951 static inline void mlxsw_reg_spvm_pack(char *payload, u16 local_port, 952 u16 vid_begin, u16 vid_end, 953 bool is_member, bool untagged) 954 { 955 int size = vid_end - vid_begin + 1; 956 int i; 957 958 MLXSW_REG_ZERO(spvm, payload); 959 mlxsw_reg_spvm_local_port_set(payload, local_port); 960 mlxsw_reg_spvm_num_rec_set(payload, size); 961 962 for (i = 0; i < size; i++) { 963 mlxsw_reg_spvm_rec_i_set(payload, i, is_member); 964 mlxsw_reg_spvm_rec_e_set(payload, i, is_member); 965 mlxsw_reg_spvm_rec_u_set(payload, i, untagged); 966 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i); 967 } 968 } 969 970 /* SPAFT - Switch Port Acceptable Frame Types 971 * ------------------------------------------ 972 * The Switch Port Acceptable Frame Types register configures the frame 973 * admittance of the port. 974 */ 975 #define MLXSW_REG_SPAFT_ID 0x2010 976 #define MLXSW_REG_SPAFT_LEN 0x08 977 978 MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN); 979 980 /* reg_spaft_local_port 981 * Local port number. 982 * Access: Index 983 * 984 * Note: CPU port is not supported (all tag types are allowed). 985 */ 986 MLXSW_ITEM32_LP(reg, spaft, 0x00, 16, 0x00, 12); 987 988 /* reg_spaft_sub_port 989 * Virtual port within the physical port. 990 * Should be set to 0 when virtual ports are not enabled on the port. 991 * Access: RW 992 */ 993 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8); 994 995 /* reg_spaft_allow_untagged 996 * When set, untagged frames on the ingress are allowed (default). 997 * Access: RW 998 */ 999 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1); 1000 1001 /* reg_spaft_allow_prio_tagged 1002 * When set, priority tagged frames on the ingress are allowed (default). 1003 * Access: RW 1004 */ 1005 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1); 1006 1007 /* reg_spaft_allow_tagged 1008 * When set, tagged frames on the ingress are allowed (default). 1009 * Access: RW 1010 */ 1011 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1); 1012 1013 static inline void mlxsw_reg_spaft_pack(char *payload, u16 local_port, 1014 bool allow_untagged) 1015 { 1016 MLXSW_REG_ZERO(spaft, payload); 1017 mlxsw_reg_spaft_local_port_set(payload, local_port); 1018 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged); 1019 mlxsw_reg_spaft_allow_prio_tagged_set(payload, allow_untagged); 1020 mlxsw_reg_spaft_allow_tagged_set(payload, true); 1021 } 1022 1023 /* SFGC - Switch Flooding Group Configuration 1024 * ------------------------------------------ 1025 * The following register controls the association of flooding tables and MIDs 1026 * to packet types used for flooding. 1027 */ 1028 #define MLXSW_REG_SFGC_ID 0x2011 1029 #define MLXSW_REG_SFGC_LEN 0x14 1030 1031 MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN); 1032 1033 enum mlxsw_reg_sfgc_type { 1034 MLXSW_REG_SFGC_TYPE_BROADCAST, 1035 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST, 1036 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4, 1037 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6, 1038 MLXSW_REG_SFGC_TYPE_RESERVED, 1039 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP, 1040 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL, 1041 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST, 1042 MLXSW_REG_SFGC_TYPE_MAX, 1043 }; 1044 1045 /* reg_sfgc_type 1046 * The traffic type to reach the flooding table. 1047 * Access: Index 1048 */ 1049 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4); 1050 1051 /* bridge_type is used in SFGC and SFMR. */ 1052 enum mlxsw_reg_bridge_type { 1053 MLXSW_REG_BRIDGE_TYPE_0 = 0, /* Used for .1q FIDs. */ 1054 MLXSW_REG_BRIDGE_TYPE_1 = 1, /* Used for .1d FIDs. */ 1055 }; 1056 1057 /* reg_sfgc_bridge_type 1058 * Access: Index 1059 * 1060 * Note: SwitchX-2 only supports 802.1Q mode. 1061 */ 1062 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3); 1063 1064 enum mlxsw_flood_table_type { 1065 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1, 1066 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2, 1067 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0, 1068 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3, 1069 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4, 1070 }; 1071 1072 /* reg_sfgc_table_type 1073 * See mlxsw_flood_table_type 1074 * Access: RW 1075 * 1076 * Note: FID offset and FID types are not supported in SwitchX-2. 1077 */ 1078 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3); 1079 1080 /* reg_sfgc_flood_table 1081 * Flooding table index to associate with the specific type on the specific 1082 * switch partition. 1083 * Access: RW 1084 */ 1085 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6); 1086 1087 /* reg_sfgc_counter_set_type 1088 * Counter Set Type for flow counters. 1089 * Access: RW 1090 */ 1091 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8); 1092 1093 /* reg_sfgc_counter_index 1094 * Counter Index for flow counters. 1095 * Access: RW 1096 */ 1097 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24); 1098 1099 /* reg_sfgc_mid_base 1100 * MID Base. 1101 * Access: RW 1102 * 1103 * Note: Reserved when legacy bridge model is used. 1104 */ 1105 MLXSW_ITEM32(reg, sfgc, mid_base, 0x10, 0, 16); 1106 1107 static inline void 1108 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type, 1109 enum mlxsw_reg_bridge_type bridge_type, 1110 enum mlxsw_flood_table_type table_type, 1111 unsigned int flood_table, u16 mid_base) 1112 { 1113 MLXSW_REG_ZERO(sfgc, payload); 1114 mlxsw_reg_sfgc_type_set(payload, type); 1115 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type); 1116 mlxsw_reg_sfgc_table_type_set(payload, table_type); 1117 mlxsw_reg_sfgc_flood_table_set(payload, flood_table); 1118 mlxsw_reg_sfgc_mid_base_set(payload, mid_base); 1119 } 1120 1121 /* SFDF - Switch Filtering DB Flush 1122 * -------------------------------- 1123 * The switch filtering DB flush register is used to flush the FDB. 1124 * Note that FDB notifications are flushed as well. 1125 */ 1126 #define MLXSW_REG_SFDF_ID 0x2013 1127 #define MLXSW_REG_SFDF_LEN 0x14 1128 1129 MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN); 1130 1131 /* reg_sfdf_swid 1132 * Switch partition ID. 1133 * Access: Index 1134 */ 1135 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8); 1136 1137 enum mlxsw_reg_sfdf_flush_type { 1138 MLXSW_REG_SFDF_FLUSH_PER_SWID, 1139 MLXSW_REG_SFDF_FLUSH_PER_FID, 1140 MLXSW_REG_SFDF_FLUSH_PER_PORT, 1141 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID, 1142 MLXSW_REG_SFDF_FLUSH_PER_LAG, 1143 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID, 1144 MLXSW_REG_SFDF_FLUSH_PER_NVE, 1145 MLXSW_REG_SFDF_FLUSH_PER_NVE_AND_FID, 1146 }; 1147 1148 /* reg_sfdf_flush_type 1149 * Flush type. 1150 * 0 - All SWID dynamic entries are flushed. 1151 * 1 - All FID dynamic entries are flushed. 1152 * 2 - All dynamic entries pointing to port are flushed. 1153 * 3 - All FID dynamic entries pointing to port are flushed. 1154 * 4 - All dynamic entries pointing to LAG are flushed. 1155 * 5 - All FID dynamic entries pointing to LAG are flushed. 1156 * 6 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1157 * flushed. 1158 * 7 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1159 * flushed, per FID. 1160 * Access: RW 1161 */ 1162 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4); 1163 1164 /* reg_sfdf_flush_static 1165 * Static. 1166 * 0 - Flush only dynamic entries. 1167 * 1 - Flush both dynamic and static entries. 1168 * Access: RW 1169 */ 1170 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1); 1171 1172 static inline void mlxsw_reg_sfdf_pack(char *payload, 1173 enum mlxsw_reg_sfdf_flush_type type) 1174 { 1175 MLXSW_REG_ZERO(sfdf, payload); 1176 mlxsw_reg_sfdf_flush_type_set(payload, type); 1177 mlxsw_reg_sfdf_flush_static_set(payload, true); 1178 } 1179 1180 /* reg_sfdf_fid 1181 * FID to flush. 1182 * Access: RW 1183 */ 1184 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16); 1185 1186 /* reg_sfdf_system_port 1187 * Port to flush. 1188 * Access: RW 1189 */ 1190 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16); 1191 1192 /* reg_sfdf_port_fid_system_port 1193 * Port to flush, pointed to by FID. 1194 * Access: RW 1195 */ 1196 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16); 1197 1198 /* reg_sfdf_lag_id 1199 * LAG ID to flush. 1200 * Access: RW 1201 */ 1202 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10); 1203 1204 /* reg_sfdf_lag_fid_lag_id 1205 * LAG ID to flush, pointed to by FID. 1206 * Access: RW 1207 */ 1208 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10); 1209 1210 /* SLDR - Switch LAG Descriptor Register 1211 * ----------------------------------------- 1212 * The switch LAG descriptor register is populated by LAG descriptors. 1213 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to 1214 * max_lag-1. 1215 */ 1216 #define MLXSW_REG_SLDR_ID 0x2014 1217 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */ 1218 1219 MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN); 1220 1221 enum mlxsw_reg_sldr_op { 1222 /* Indicates a creation of a new LAG-ID, lag_id must be valid */ 1223 MLXSW_REG_SLDR_OP_LAG_CREATE, 1224 MLXSW_REG_SLDR_OP_LAG_DESTROY, 1225 /* Ports that appear in the list have the Distributor enabled */ 1226 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST, 1227 /* Removes ports from the disributor list */ 1228 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST, 1229 }; 1230 1231 /* reg_sldr_op 1232 * Operation. 1233 * Access: RW 1234 */ 1235 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3); 1236 1237 /* reg_sldr_lag_id 1238 * LAG identifier. The lag_id is the index into the LAG descriptor table. 1239 * Access: Index 1240 */ 1241 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10); 1242 1243 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id) 1244 { 1245 MLXSW_REG_ZERO(sldr, payload); 1246 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE); 1247 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1248 } 1249 1250 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id) 1251 { 1252 MLXSW_REG_ZERO(sldr, payload); 1253 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY); 1254 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1255 } 1256 1257 /* reg_sldr_num_ports 1258 * The number of member ports of the LAG. 1259 * Reserved for Create / Destroy operations 1260 * For Add / Remove operations - indicates the number of ports in the list. 1261 * Access: RW 1262 */ 1263 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8); 1264 1265 /* reg_sldr_system_port 1266 * System port. 1267 * Access: RW 1268 */ 1269 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false); 1270 1271 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id, 1272 u16 local_port) 1273 { 1274 MLXSW_REG_ZERO(sldr, payload); 1275 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST); 1276 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1277 mlxsw_reg_sldr_num_ports_set(payload, 1); 1278 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1279 } 1280 1281 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id, 1282 u16 local_port) 1283 { 1284 MLXSW_REG_ZERO(sldr, payload); 1285 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST); 1286 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1287 mlxsw_reg_sldr_num_ports_set(payload, 1); 1288 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1289 } 1290 1291 /* SLCR - Switch LAG Configuration 2 Register 1292 * ------------------------------------------- 1293 * The Switch LAG Configuration register is used for configuring the 1294 * LAG properties of the switch. 1295 */ 1296 #define MLXSW_REG_SLCR_ID 0x2015 1297 #define MLXSW_REG_SLCR_LEN 0x10 1298 1299 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN); 1300 1301 enum mlxsw_reg_slcr_pp { 1302 /* Global Configuration (for all ports) */ 1303 MLXSW_REG_SLCR_PP_GLOBAL, 1304 /* Per port configuration, based on local_port field */ 1305 MLXSW_REG_SLCR_PP_PER_PORT, 1306 }; 1307 1308 /* reg_slcr_pp 1309 * Per Port Configuration 1310 * Note: Reading at Global mode results in reading port 1 configuration. 1311 * Access: Index 1312 */ 1313 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1); 1314 1315 /* reg_slcr_local_port 1316 * Local port number 1317 * Supported from CPU port 1318 * Not supported from router port 1319 * Reserved when pp = Global Configuration 1320 * Access: Index 1321 */ 1322 MLXSW_ITEM32_LP(reg, slcr, 0x00, 16, 0x00, 12); 1323 1324 enum mlxsw_reg_slcr_type { 1325 MLXSW_REG_SLCR_TYPE_CRC, /* default */ 1326 MLXSW_REG_SLCR_TYPE_XOR, 1327 MLXSW_REG_SLCR_TYPE_RANDOM, 1328 }; 1329 1330 /* reg_slcr_type 1331 * Hash type 1332 * Access: RW 1333 */ 1334 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4); 1335 1336 /* Ingress port */ 1337 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0) 1338 /* SMAC - for IPv4 and IPv6 packets */ 1339 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1) 1340 /* SMAC - for non-IP packets */ 1341 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2) 1342 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \ 1343 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \ 1344 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP) 1345 /* DMAC - for IPv4 and IPv6 packets */ 1346 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3) 1347 /* DMAC - for non-IP packets */ 1348 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4) 1349 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \ 1350 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \ 1351 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP) 1352 /* Ethertype - for IPv4 and IPv6 packets */ 1353 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5) 1354 /* Ethertype - for non-IP packets */ 1355 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6) 1356 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \ 1357 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \ 1358 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP) 1359 /* VLAN ID - for IPv4 and IPv6 packets */ 1360 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7) 1361 /* VLAN ID - for non-IP packets */ 1362 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8) 1363 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \ 1364 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \ 1365 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP) 1366 /* Source IP address (can be IPv4 or IPv6) */ 1367 #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9) 1368 /* Destination IP address (can be IPv4 or IPv6) */ 1369 #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10) 1370 /* TCP/UDP source port */ 1371 #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11) 1372 /* TCP/UDP destination port*/ 1373 #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12) 1374 /* IPv4 Protocol/IPv6 Next Header */ 1375 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13) 1376 /* IPv6 Flow label */ 1377 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14) 1378 /* SID - FCoE source ID */ 1379 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15) 1380 /* DID - FCoE destination ID */ 1381 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16) 1382 /* OXID - FCoE originator exchange ID */ 1383 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17) 1384 /* Destination QP number - for RoCE packets */ 1385 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19) 1386 1387 /* reg_slcr_lag_hash 1388 * LAG hashing configuration. This is a bitmask, in which each set 1389 * bit includes the corresponding item in the LAG hash calculation. 1390 * The default lag_hash contains SMAC, DMAC, VLANID and 1391 * Ethertype (for all packet types). 1392 * Access: RW 1393 */ 1394 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20); 1395 1396 /* reg_slcr_seed 1397 * LAG seed value. The seed is the same for all ports. 1398 * Access: RW 1399 */ 1400 MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32); 1401 1402 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed) 1403 { 1404 MLXSW_REG_ZERO(slcr, payload); 1405 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL); 1406 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC); 1407 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash); 1408 mlxsw_reg_slcr_seed_set(payload, seed); 1409 } 1410 1411 /* SLCOR - Switch LAG Collector Register 1412 * ------------------------------------- 1413 * The Switch LAG Collector register controls the Local Port membership 1414 * in a LAG and enablement of the collector. 1415 */ 1416 #define MLXSW_REG_SLCOR_ID 0x2016 1417 #define MLXSW_REG_SLCOR_LEN 0x10 1418 1419 MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN); 1420 1421 enum mlxsw_reg_slcor_col { 1422 /* Port is added with collector disabled */ 1423 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT, 1424 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED, 1425 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED, 1426 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT, 1427 }; 1428 1429 /* reg_slcor_col 1430 * Collector configuration 1431 * Access: RW 1432 */ 1433 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2); 1434 1435 /* reg_slcor_local_port 1436 * Local port number 1437 * Not supported for CPU port 1438 * Access: Index 1439 */ 1440 MLXSW_ITEM32_LP(reg, slcor, 0x00, 16, 0x00, 12); 1441 1442 /* reg_slcor_lag_id 1443 * LAG Identifier. Index into the LAG descriptor table. 1444 * Access: Index 1445 */ 1446 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10); 1447 1448 /* reg_slcor_port_index 1449 * Port index in the LAG list. Only valid on Add Port to LAG col. 1450 * Valid range is from 0 to cap_max_lag_members-1 1451 * Access: RW 1452 */ 1453 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10); 1454 1455 static inline void mlxsw_reg_slcor_pack(char *payload, 1456 u16 local_port, u16 lag_id, 1457 enum mlxsw_reg_slcor_col col) 1458 { 1459 MLXSW_REG_ZERO(slcor, payload); 1460 mlxsw_reg_slcor_col_set(payload, col); 1461 mlxsw_reg_slcor_local_port_set(payload, local_port); 1462 mlxsw_reg_slcor_lag_id_set(payload, lag_id); 1463 } 1464 1465 static inline void mlxsw_reg_slcor_port_add_pack(char *payload, 1466 u16 local_port, u16 lag_id, 1467 u8 port_index) 1468 { 1469 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1470 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT); 1471 mlxsw_reg_slcor_port_index_set(payload, port_index); 1472 } 1473 1474 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload, 1475 u16 local_port, u16 lag_id) 1476 { 1477 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1478 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT); 1479 } 1480 1481 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload, 1482 u16 local_port, u16 lag_id) 1483 { 1484 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1485 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1486 } 1487 1488 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload, 1489 u16 local_port, u16 lag_id) 1490 { 1491 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1492 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1493 } 1494 1495 /* SPMLR - Switch Port MAC Learning Register 1496 * ----------------------------------------- 1497 * Controls the Switch MAC learning policy per port. 1498 */ 1499 #define MLXSW_REG_SPMLR_ID 0x2018 1500 #define MLXSW_REG_SPMLR_LEN 0x8 1501 1502 MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN); 1503 1504 /* reg_spmlr_local_port 1505 * Local port number. 1506 * Access: Index 1507 */ 1508 MLXSW_ITEM32_LP(reg, spmlr, 0x00, 16, 0x00, 12); 1509 1510 /* reg_spmlr_sub_port 1511 * Virtual port within the physical port. 1512 * Should be set to 0 when virtual ports are not enabled on the port. 1513 * Access: Index 1514 */ 1515 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8); 1516 1517 enum mlxsw_reg_spmlr_learn_mode { 1518 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0, 1519 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2, 1520 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3, 1521 }; 1522 1523 /* reg_spmlr_learn_mode 1524 * Learning mode on the port. 1525 * 0 - Learning disabled. 1526 * 2 - Learning enabled. 1527 * 3 - Security mode. 1528 * 1529 * In security mode the switch does not learn MACs on the port, but uses the 1530 * SMAC to see if it exists on another ingress port. If so, the packet is 1531 * classified as a bad packet and is discarded unless the software registers 1532 * to receive port security error packets usign HPKT. 1533 */ 1534 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2); 1535 1536 static inline void mlxsw_reg_spmlr_pack(char *payload, u16 local_port, 1537 enum mlxsw_reg_spmlr_learn_mode mode) 1538 { 1539 MLXSW_REG_ZERO(spmlr, payload); 1540 mlxsw_reg_spmlr_local_port_set(payload, local_port); 1541 mlxsw_reg_spmlr_sub_port_set(payload, 0); 1542 mlxsw_reg_spmlr_learn_mode_set(payload, mode); 1543 } 1544 1545 /* SVFA - Switch VID to FID Allocation Register 1546 * -------------------------------------------- 1547 * Controls the VID to FID mapping and {Port, VID} to FID mapping for 1548 * virtualized ports. 1549 */ 1550 #define MLXSW_REG_SVFA_ID 0x201C 1551 #define MLXSW_REG_SVFA_LEN 0x18 1552 1553 MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN); 1554 1555 /* reg_svfa_swid 1556 * Switch partition ID. 1557 * Access: Index 1558 */ 1559 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8); 1560 1561 /* reg_svfa_local_port 1562 * Local port number. 1563 * Access: Index 1564 * 1565 * Note: Reserved for 802.1Q FIDs. 1566 */ 1567 MLXSW_ITEM32_LP(reg, svfa, 0x00, 16, 0x00, 12); 1568 1569 enum mlxsw_reg_svfa_mt { 1570 MLXSW_REG_SVFA_MT_VID_TO_FID, 1571 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, 1572 MLXSW_REG_SVFA_MT_VNI_TO_FID, 1573 }; 1574 1575 /* reg_svfa_mapping_table 1576 * Mapping table: 1577 * 0 - VID to FID 1578 * 1 - {Port, VID} to FID 1579 * Access: Index 1580 * 1581 * Note: Reserved for SwitchX-2. 1582 */ 1583 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3); 1584 1585 /* reg_svfa_v 1586 * Valid. 1587 * Valid if set. 1588 * Access: RW 1589 * 1590 * Note: Reserved for SwitchX-2. 1591 */ 1592 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1); 1593 1594 /* reg_svfa_fid 1595 * Filtering ID. 1596 * Access: RW 1597 */ 1598 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16); 1599 1600 /* reg_svfa_vid 1601 * VLAN ID. 1602 * Access: Index 1603 */ 1604 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12); 1605 1606 /* reg_svfa_counter_set_type 1607 * Counter set type for flow counters. 1608 * Access: RW 1609 * 1610 * Note: Reserved for SwitchX-2. 1611 */ 1612 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8); 1613 1614 /* reg_svfa_counter_index 1615 * Counter index for flow counters. 1616 * Access: RW 1617 * 1618 * Note: Reserved for SwitchX-2. 1619 */ 1620 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24); 1621 1622 /* reg_svfa_vni 1623 * Virtual Network Identifier. 1624 * Access: Index 1625 * 1626 * Note: Reserved when mapping_table is not 2 (VNI mapping table). 1627 */ 1628 MLXSW_ITEM32(reg, svfa, vni, 0x10, 0, 24); 1629 1630 /* reg_svfa_irif_v 1631 * Ingress RIF valid. 1632 * 0 - Ingress RIF is not valid, no ingress RIF assigned. 1633 * 1 - Ingress RIF valid. 1634 * Must not be set for a non enabled RIF. 1635 * Access: RW 1636 * 1637 * Note: Reserved when legacy bridge model is used. 1638 */ 1639 MLXSW_ITEM32(reg, svfa, irif_v, 0x14, 24, 1); 1640 1641 /* reg_svfa_irif 1642 * Ingress RIF (Router Interface). 1643 * Range is 0..cap_max_router_interfaces-1. 1644 * Access: RW 1645 * 1646 * Note: Reserved when legacy bridge model is used and when irif_v=0. 1647 */ 1648 MLXSW_ITEM32(reg, svfa, irif, 0x14, 0, 16); 1649 1650 static inline void __mlxsw_reg_svfa_pack(char *payload, 1651 enum mlxsw_reg_svfa_mt mt, bool valid, 1652 u16 fid, bool irif_v, u16 irif) 1653 { 1654 MLXSW_REG_ZERO(svfa, payload); 1655 mlxsw_reg_svfa_swid_set(payload, 0); 1656 mlxsw_reg_svfa_mapping_table_set(payload, mt); 1657 mlxsw_reg_svfa_v_set(payload, valid); 1658 mlxsw_reg_svfa_fid_set(payload, fid); 1659 mlxsw_reg_svfa_irif_v_set(payload, irif_v); 1660 mlxsw_reg_svfa_irif_set(payload, irif_v ? irif : 0); 1661 } 1662 1663 static inline void mlxsw_reg_svfa_port_vid_pack(char *payload, u16 local_port, 1664 bool valid, u16 fid, u16 vid, 1665 bool irif_v, u16 irif) 1666 { 1667 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID; 1668 1669 __mlxsw_reg_svfa_pack(payload, mt, valid, fid, irif_v, irif); 1670 mlxsw_reg_svfa_local_port_set(payload, local_port); 1671 mlxsw_reg_svfa_vid_set(payload, vid); 1672 } 1673 1674 static inline void mlxsw_reg_svfa_vid_pack(char *payload, bool valid, u16 fid, 1675 u16 vid, bool irif_v, u16 irif) 1676 { 1677 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_VID_TO_FID; 1678 1679 __mlxsw_reg_svfa_pack(payload, mt, valid, fid, irif_v, irif); 1680 mlxsw_reg_svfa_vid_set(payload, vid); 1681 } 1682 1683 static inline void mlxsw_reg_svfa_vni_pack(char *payload, bool valid, u16 fid, 1684 u32 vni, bool irif_v, u16 irif) 1685 { 1686 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_VNI_TO_FID; 1687 1688 __mlxsw_reg_svfa_pack(payload, mt, valid, fid, irif_v, irif); 1689 mlxsw_reg_svfa_vni_set(payload, vni); 1690 } 1691 1692 /* SPVTR - Switch Port VLAN Stacking Register 1693 * ------------------------------------------ 1694 * The Switch Port VLAN Stacking register configures the VLAN mode of the port 1695 * to enable VLAN stacking. 1696 */ 1697 #define MLXSW_REG_SPVTR_ID 0x201D 1698 #define MLXSW_REG_SPVTR_LEN 0x10 1699 1700 MLXSW_REG_DEFINE(spvtr, MLXSW_REG_SPVTR_ID, MLXSW_REG_SPVTR_LEN); 1701 1702 /* reg_spvtr_tport 1703 * Port is tunnel port. 1704 * Access: Index 1705 * 1706 * Note: Reserved when SwitchX/-2 or Spectrum-1. 1707 */ 1708 MLXSW_ITEM32(reg, spvtr, tport, 0x00, 24, 1); 1709 1710 /* reg_spvtr_local_port 1711 * When tport = 0: local port number (Not supported from/to CPU). 1712 * When tport = 1: tunnel port. 1713 * Access: Index 1714 */ 1715 MLXSW_ITEM32_LP(reg, spvtr, 0x00, 16, 0x00, 12); 1716 1717 /* reg_spvtr_ippe 1718 * Ingress Port Prio Mode Update Enable. 1719 * When set, the Port Prio Mode is updated with the provided ipprio_mode field. 1720 * Reserved on Get operations. 1721 * Access: OP 1722 */ 1723 MLXSW_ITEM32(reg, spvtr, ippe, 0x04, 31, 1); 1724 1725 /* reg_spvtr_ipve 1726 * Ingress Port VID Mode Update Enable. 1727 * When set, the Ingress Port VID Mode is updated with the provided ipvid_mode 1728 * field. 1729 * Reserved on Get operations. 1730 * Access: OP 1731 */ 1732 MLXSW_ITEM32(reg, spvtr, ipve, 0x04, 30, 1); 1733 1734 /* reg_spvtr_epve 1735 * Egress Port VID Mode Update Enable. 1736 * When set, the Egress Port VID Mode is updated with the provided epvid_mode 1737 * field. 1738 * Access: OP 1739 */ 1740 MLXSW_ITEM32(reg, spvtr, epve, 0x04, 29, 1); 1741 1742 /* reg_spvtr_ipprio_mode 1743 * Ingress Port Priority Mode. 1744 * This controls the PCP and DEI of the new outer VLAN 1745 * Note: for SwitchX/-2 the DEI is not affected. 1746 * 0: use port default PCP and DEI (configured by QPDPC). 1747 * 1: use C-VLAN PCP and DEI. 1748 * Has no effect when ipvid_mode = 0. 1749 * Reserved when tport = 1. 1750 * Access: RW 1751 */ 1752 MLXSW_ITEM32(reg, spvtr, ipprio_mode, 0x04, 20, 4); 1753 1754 enum mlxsw_reg_spvtr_ipvid_mode { 1755 /* IEEE Compliant PVID (default) */ 1756 MLXSW_REG_SPVTR_IPVID_MODE_IEEE_COMPLIANT_PVID, 1757 /* Push VLAN (for VLAN stacking, except prio tagged packets) */ 1758 MLXSW_REG_SPVTR_IPVID_MODE_PUSH_VLAN_FOR_UNTAGGED_PACKET, 1759 /* Always push VLAN (also for prio tagged packets) */ 1760 MLXSW_REG_SPVTR_IPVID_MODE_ALWAYS_PUSH_VLAN, 1761 }; 1762 1763 /* reg_spvtr_ipvid_mode 1764 * Ingress Port VLAN-ID Mode. 1765 * For Spectrum family, this affects the values of SPVM.i 1766 * Access: RW 1767 */ 1768 MLXSW_ITEM32(reg, spvtr, ipvid_mode, 0x04, 16, 4); 1769 1770 enum mlxsw_reg_spvtr_epvid_mode { 1771 /* IEEE Compliant VLAN membership */ 1772 MLXSW_REG_SPVTR_EPVID_MODE_IEEE_COMPLIANT_VLAN_MEMBERSHIP, 1773 /* Pop VLAN (for VLAN stacking) */ 1774 MLXSW_REG_SPVTR_EPVID_MODE_POP_VLAN, 1775 }; 1776 1777 /* reg_spvtr_epvid_mode 1778 * Egress Port VLAN-ID Mode. 1779 * For Spectrum family, this affects the values of SPVM.e,u,pt. 1780 * Access: WO 1781 */ 1782 MLXSW_ITEM32(reg, spvtr, epvid_mode, 0x04, 0, 4); 1783 1784 static inline void mlxsw_reg_spvtr_pack(char *payload, bool tport, 1785 u16 local_port, 1786 enum mlxsw_reg_spvtr_ipvid_mode ipvid_mode) 1787 { 1788 MLXSW_REG_ZERO(spvtr, payload); 1789 mlxsw_reg_spvtr_tport_set(payload, tport); 1790 mlxsw_reg_spvtr_local_port_set(payload, local_port); 1791 mlxsw_reg_spvtr_ipvid_mode_set(payload, ipvid_mode); 1792 mlxsw_reg_spvtr_ipve_set(payload, true); 1793 } 1794 1795 /* SVPE - Switch Virtual-Port Enabling Register 1796 * -------------------------------------------- 1797 * Enables port virtualization. 1798 */ 1799 #define MLXSW_REG_SVPE_ID 0x201E 1800 #define MLXSW_REG_SVPE_LEN 0x4 1801 1802 MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN); 1803 1804 /* reg_svpe_local_port 1805 * Local port number 1806 * Access: Index 1807 * 1808 * Note: CPU port is not supported (uses VLAN mode only). 1809 */ 1810 MLXSW_ITEM32_LP(reg, svpe, 0x00, 16, 0x00, 12); 1811 1812 /* reg_svpe_vp_en 1813 * Virtual port enable. 1814 * 0 - Disable, VLAN mode (VID to FID). 1815 * 1 - Enable, Virtual port mode ({Port, VID} to FID). 1816 * Access: RW 1817 */ 1818 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1); 1819 1820 static inline void mlxsw_reg_svpe_pack(char *payload, u16 local_port, 1821 bool enable) 1822 { 1823 MLXSW_REG_ZERO(svpe, payload); 1824 mlxsw_reg_svpe_local_port_set(payload, local_port); 1825 mlxsw_reg_svpe_vp_en_set(payload, enable); 1826 } 1827 1828 /* SFMR - Switch FID Management Register 1829 * ------------------------------------- 1830 * Creates and configures FIDs. 1831 */ 1832 #define MLXSW_REG_SFMR_ID 0x201F 1833 #define MLXSW_REG_SFMR_LEN 0x30 1834 1835 MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN); 1836 1837 enum mlxsw_reg_sfmr_op { 1838 MLXSW_REG_SFMR_OP_CREATE_FID, 1839 MLXSW_REG_SFMR_OP_DESTROY_FID, 1840 }; 1841 1842 /* reg_sfmr_op 1843 * Operation. 1844 * 0 - Create or edit FID. 1845 * 1 - Destroy FID. 1846 * Access: WO 1847 */ 1848 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4); 1849 1850 /* reg_sfmr_fid 1851 * Filtering ID. 1852 * Access: Index 1853 */ 1854 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16); 1855 1856 /* reg_sfmr_flood_rsp 1857 * Router sub-port flooding table. 1858 * 0 - Regular flooding table. 1859 * 1 - Router sub-port flooding table. For this FID the flooding is per 1860 * router-sub-port local_port. Must not be set for a FID which is not a 1861 * router-sub-port and must be set prior to enabling the relevant RIF. 1862 * Access: RW 1863 * 1864 * Note: Reserved when legacy bridge model is used. 1865 */ 1866 MLXSW_ITEM32(reg, sfmr, flood_rsp, 0x08, 31, 1); 1867 1868 /* reg_sfmr_flood_bridge_type 1869 * Flood bridge type (see SFGC.bridge_type). 1870 * 0 - type_0. 1871 * 1 - type_1. 1872 * Access: RW 1873 * 1874 * Note: Reserved when legacy bridge model is used and when flood_rsp=1. 1875 */ 1876 MLXSW_ITEM32(reg, sfmr, flood_bridge_type, 0x08, 28, 1); 1877 1878 /* reg_sfmr_fid_offset 1879 * FID offset. 1880 * Used to point into the flooding table selected by SFGC register if 1881 * the table is of type FID-Offset. Otherwise, this field is reserved. 1882 * Access: RW 1883 */ 1884 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16); 1885 1886 /* reg_sfmr_vtfp 1887 * Valid Tunnel Flood Pointer. 1888 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL. 1889 * Access: RW 1890 * 1891 * Note: Reserved for 802.1Q FIDs. 1892 */ 1893 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1); 1894 1895 /* reg_sfmr_nve_tunnel_flood_ptr 1896 * Underlay Flooding and BC Pointer. 1897 * Used as a pointer to the first entry of the group based link lists of 1898 * flooding or BC entries (for NVE tunnels). 1899 * Access: RW 1900 */ 1901 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24); 1902 1903 /* reg_sfmr_vv 1904 * VNI Valid. 1905 * If not set, then vni is reserved. 1906 * Access: RW 1907 * 1908 * Note: Reserved for 802.1Q FIDs. 1909 */ 1910 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1); 1911 1912 /* reg_sfmr_vni 1913 * Virtual Network Identifier. 1914 * When legacy bridge model is used, a given VNI can only be assigned to one 1915 * FID. When unified bridge model is used, it configures only the FID->VNI, 1916 * the VNI->FID is done by SVFA. 1917 * Access: RW 1918 */ 1919 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24); 1920 1921 /* reg_sfmr_irif_v 1922 * Ingress RIF valid. 1923 * 0 - Ingress RIF is not valid, no ingress RIF assigned. 1924 * 1 - Ingress RIF valid. 1925 * Must not be set for a non valid RIF. 1926 * Access: RW 1927 * 1928 * Note: Reserved when legacy bridge model is used. 1929 */ 1930 MLXSW_ITEM32(reg, sfmr, irif_v, 0x14, 24, 1); 1931 1932 /* reg_sfmr_irif 1933 * Ingress RIF (Router Interface). 1934 * Range is 0..cap_max_router_interfaces-1. 1935 * Access: RW 1936 * 1937 * Note: Reserved when legacy bridge model is used and when irif_v=0. 1938 */ 1939 MLXSW_ITEM32(reg, sfmr, irif, 0x14, 0, 16); 1940 1941 /* reg_sfmr_smpe_valid 1942 * SMPE is valid. 1943 * Access: RW 1944 * 1945 * Note: Reserved when legacy bridge model is used, when flood_rsp=1 and on 1946 * Spectrum-1. 1947 */ 1948 MLXSW_ITEM32(reg, sfmr, smpe_valid, 0x28, 20, 1); 1949 1950 /* reg_sfmr_smpe 1951 * Switch multicast port to egress VID. 1952 * Range is 0..cap_max_rmpe-1 1953 * Access: RW 1954 * 1955 * Note: Reserved when legacy bridge model is used, when flood_rsp=1 and on 1956 * Spectrum-1. 1957 */ 1958 MLXSW_ITEM32(reg, sfmr, smpe, 0x28, 0, 16); 1959 1960 static inline void mlxsw_reg_sfmr_pack(char *payload, 1961 enum mlxsw_reg_sfmr_op op, u16 fid, 1962 u16 fid_offset, bool flood_rsp, 1963 enum mlxsw_reg_bridge_type bridge_type, 1964 bool smpe_valid, u16 smpe) 1965 { 1966 MLXSW_REG_ZERO(sfmr, payload); 1967 mlxsw_reg_sfmr_op_set(payload, op); 1968 mlxsw_reg_sfmr_fid_set(payload, fid); 1969 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset); 1970 mlxsw_reg_sfmr_vtfp_set(payload, false); 1971 mlxsw_reg_sfmr_vv_set(payload, false); 1972 mlxsw_reg_sfmr_flood_rsp_set(payload, flood_rsp); 1973 mlxsw_reg_sfmr_flood_bridge_type_set(payload, bridge_type); 1974 mlxsw_reg_sfmr_smpe_valid_set(payload, smpe_valid); 1975 mlxsw_reg_sfmr_smpe_set(payload, smpe); 1976 } 1977 1978 /* SPVMLR - Switch Port VLAN MAC Learning Register 1979 * ----------------------------------------------- 1980 * Controls the switch MAC learning policy per {Port, VID}. 1981 */ 1982 #define MLXSW_REG_SPVMLR_ID 0x2020 1983 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */ 1984 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */ 1985 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255 1986 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \ 1987 MLXSW_REG_SPVMLR_REC_LEN * \ 1988 MLXSW_REG_SPVMLR_REC_MAX_COUNT) 1989 1990 MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN); 1991 1992 /* reg_spvmlr_local_port 1993 * Local ingress port. 1994 * Access: Index 1995 * 1996 * Note: CPU port is not supported. 1997 */ 1998 MLXSW_ITEM32_LP(reg, spvmlr, 0x00, 16, 0x00, 12); 1999 2000 /* reg_spvmlr_num_rec 2001 * Number of records to update. 2002 * Access: OP 2003 */ 2004 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8); 2005 2006 /* reg_spvmlr_rec_learn_enable 2007 * 0 - Disable learning for {Port, VID}. 2008 * 1 - Enable learning for {Port, VID}. 2009 * Access: RW 2010 */ 2011 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN, 2012 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 2013 2014 /* reg_spvmlr_rec_vid 2015 * VLAN ID to be added/removed from port or for querying. 2016 * Access: Index 2017 */ 2018 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12, 2019 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 2020 2021 static inline void mlxsw_reg_spvmlr_pack(char *payload, u16 local_port, 2022 u16 vid_begin, u16 vid_end, 2023 bool learn_enable) 2024 { 2025 int num_rec = vid_end - vid_begin + 1; 2026 int i; 2027 2028 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT); 2029 2030 MLXSW_REG_ZERO(spvmlr, payload); 2031 mlxsw_reg_spvmlr_local_port_set(payload, local_port); 2032 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec); 2033 2034 for (i = 0; i < num_rec; i++) { 2035 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable); 2036 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i); 2037 } 2038 } 2039 2040 /* SPFSR - Switch Port FDB Security Register 2041 * ----------------------------------------- 2042 * Configures the security mode per port. 2043 */ 2044 #define MLXSW_REG_SPFSR_ID 0x2023 2045 #define MLXSW_REG_SPFSR_LEN 0x08 2046 2047 MLXSW_REG_DEFINE(spfsr, MLXSW_REG_SPFSR_ID, MLXSW_REG_SPFSR_LEN); 2048 2049 /* reg_spfsr_local_port 2050 * Local port. 2051 * Access: Index 2052 * 2053 * Note: not supported for CPU port. 2054 */ 2055 MLXSW_ITEM32_LP(reg, spfsr, 0x00, 16, 0x00, 12); 2056 2057 /* reg_spfsr_security 2058 * Security checks. 2059 * 0: disabled (default) 2060 * 1: enabled 2061 * Access: RW 2062 */ 2063 MLXSW_ITEM32(reg, spfsr, security, 0x04, 31, 1); 2064 2065 static inline void mlxsw_reg_spfsr_pack(char *payload, u16 local_port, 2066 bool security) 2067 { 2068 MLXSW_REG_ZERO(spfsr, payload); 2069 mlxsw_reg_spfsr_local_port_set(payload, local_port); 2070 mlxsw_reg_spfsr_security_set(payload, security); 2071 } 2072 2073 /* SPVC - Switch Port VLAN Classification Register 2074 * ----------------------------------------------- 2075 * Configures the port to identify packets as untagged / single tagged / 2076 * double packets based on the packet EtherTypes. 2077 * Ethertype IDs are configured by SVER. 2078 */ 2079 #define MLXSW_REG_SPVC_ID 0x2026 2080 #define MLXSW_REG_SPVC_LEN 0x0C 2081 2082 MLXSW_REG_DEFINE(spvc, MLXSW_REG_SPVC_ID, MLXSW_REG_SPVC_LEN); 2083 2084 /* reg_spvc_local_port 2085 * Local port. 2086 * Access: Index 2087 * 2088 * Note: applies both to Rx port and Tx port, so if a packet traverses 2089 * through Rx port i and a Tx port j then port i and port j must have the 2090 * same configuration. 2091 */ 2092 MLXSW_ITEM32_LP(reg, spvc, 0x00, 16, 0x00, 12); 2093 2094 /* reg_spvc_inner_et2 2095 * Vlan Tag1 EtherType2 enable. 2096 * Packet is initially classified as double VLAN Tag if in addition to 2097 * being classified with a tag0 VLAN Tag its tag1 EtherType value is 2098 * equal to ether_type2. 2099 * 0: disable (default) 2100 * 1: enable 2101 * Access: RW 2102 */ 2103 MLXSW_ITEM32(reg, spvc, inner_et2, 0x08, 17, 1); 2104 2105 /* reg_spvc_et2 2106 * Vlan Tag0 EtherType2 enable. 2107 * Packet is initially classified as VLAN Tag if its tag0 EtherType is 2108 * equal to ether_type2. 2109 * 0: disable (default) 2110 * 1: enable 2111 * Access: RW 2112 */ 2113 MLXSW_ITEM32(reg, spvc, et2, 0x08, 16, 1); 2114 2115 /* reg_spvc_inner_et1 2116 * Vlan Tag1 EtherType1 enable. 2117 * Packet is initially classified as double VLAN Tag if in addition to 2118 * being classified with a tag0 VLAN Tag its tag1 EtherType value is 2119 * equal to ether_type1. 2120 * 0: disable 2121 * 1: enable (default) 2122 * Access: RW 2123 */ 2124 MLXSW_ITEM32(reg, spvc, inner_et1, 0x08, 9, 1); 2125 2126 /* reg_spvc_et1 2127 * Vlan Tag0 EtherType1 enable. 2128 * Packet is initially classified as VLAN Tag if its tag0 EtherType is 2129 * equal to ether_type1. 2130 * 0: disable 2131 * 1: enable (default) 2132 * Access: RW 2133 */ 2134 MLXSW_ITEM32(reg, spvc, et1, 0x08, 8, 1); 2135 2136 /* reg_inner_et0 2137 * Vlan Tag1 EtherType0 enable. 2138 * Packet is initially classified as double VLAN Tag if in addition to 2139 * being classified with a tag0 VLAN Tag its tag1 EtherType value is 2140 * equal to ether_type0. 2141 * 0: disable 2142 * 1: enable (default) 2143 * Access: RW 2144 */ 2145 MLXSW_ITEM32(reg, spvc, inner_et0, 0x08, 1, 1); 2146 2147 /* reg_et0 2148 * Vlan Tag0 EtherType0 enable. 2149 * Packet is initially classified as VLAN Tag if its tag0 EtherType is 2150 * equal to ether_type0. 2151 * 0: disable 2152 * 1: enable (default) 2153 * Access: RW 2154 */ 2155 MLXSW_ITEM32(reg, spvc, et0, 0x08, 0, 1); 2156 2157 static inline void mlxsw_reg_spvc_pack(char *payload, u16 local_port, bool et1, 2158 bool et0) 2159 { 2160 MLXSW_REG_ZERO(spvc, payload); 2161 mlxsw_reg_spvc_local_port_set(payload, local_port); 2162 /* Enable inner_et1 and inner_et0 to enable identification of double 2163 * tagged packets. 2164 */ 2165 mlxsw_reg_spvc_inner_et1_set(payload, 1); 2166 mlxsw_reg_spvc_inner_et0_set(payload, 1); 2167 mlxsw_reg_spvc_et1_set(payload, et1); 2168 mlxsw_reg_spvc_et0_set(payload, et0); 2169 } 2170 2171 /* SPEVET - Switch Port Egress VLAN EtherType 2172 * ------------------------------------------ 2173 * The switch port egress VLAN EtherType configures which EtherType to push at 2174 * egress for packets incoming through a local port for which 'SPVID.egr_et_set' 2175 * is set. 2176 */ 2177 #define MLXSW_REG_SPEVET_ID 0x202A 2178 #define MLXSW_REG_SPEVET_LEN 0x08 2179 2180 MLXSW_REG_DEFINE(spevet, MLXSW_REG_SPEVET_ID, MLXSW_REG_SPEVET_LEN); 2181 2182 /* reg_spevet_local_port 2183 * Egress Local port number. 2184 * Not supported to CPU port. 2185 * Access: Index 2186 */ 2187 MLXSW_ITEM32_LP(reg, spevet, 0x00, 16, 0x00, 12); 2188 2189 /* reg_spevet_et_vlan 2190 * Egress EtherType VLAN to push when SPVID.egr_et_set field set for the packet: 2191 * 0: ether_type0 - (default) 2192 * 1: ether_type1 2193 * 2: ether_type2 2194 * Access: RW 2195 */ 2196 MLXSW_ITEM32(reg, spevet, et_vlan, 0x04, 16, 2); 2197 2198 static inline void mlxsw_reg_spevet_pack(char *payload, u16 local_port, 2199 u8 et_vlan) 2200 { 2201 MLXSW_REG_ZERO(spevet, payload); 2202 mlxsw_reg_spevet_local_port_set(payload, local_port); 2203 mlxsw_reg_spevet_et_vlan_set(payload, et_vlan); 2204 } 2205 2206 /* SMPE - Switch Multicast Port to Egress VID 2207 * ------------------------------------------ 2208 * The switch multicast port to egress VID maps 2209 * {egress_port, SMPE index} -> {VID}. 2210 */ 2211 #define MLXSW_REG_SMPE_ID 0x202B 2212 #define MLXSW_REG_SMPE_LEN 0x0C 2213 2214 MLXSW_REG_DEFINE(smpe, MLXSW_REG_SMPE_ID, MLXSW_REG_SMPE_LEN); 2215 2216 /* reg_smpe_local_port 2217 * Local port number. 2218 * CPU port is not supported. 2219 * Access: Index 2220 */ 2221 MLXSW_ITEM32_LP(reg, smpe, 0x00, 16, 0x00, 12); 2222 2223 /* reg_smpe_smpe_index 2224 * Switch multicast port to egress VID. 2225 * Range is 0..cap_max_rmpe-1. 2226 * Access: Index 2227 */ 2228 MLXSW_ITEM32(reg, smpe, smpe_index, 0x04, 0, 16); 2229 2230 /* reg_smpe_evid 2231 * Egress VID. 2232 * Access: RW 2233 */ 2234 MLXSW_ITEM32(reg, smpe, evid, 0x08, 0, 12); 2235 2236 static inline void mlxsw_reg_smpe_pack(char *payload, u16 local_port, 2237 u16 smpe_index, u16 evid) 2238 { 2239 MLXSW_REG_ZERO(smpe, payload); 2240 mlxsw_reg_smpe_local_port_set(payload, local_port); 2241 mlxsw_reg_smpe_smpe_index_set(payload, smpe_index); 2242 mlxsw_reg_smpe_evid_set(payload, evid); 2243 } 2244 2245 /* SMID-V2 - Switch Multicast ID Version 2 Register 2246 * ------------------------------------------------ 2247 * The MID record maps from a MID (Multicast ID), which is a unique identifier 2248 * of the multicast group within the stacking domain, into a list of local 2249 * ports into which the packet is replicated. 2250 */ 2251 #define MLXSW_REG_SMID2_ID 0x2034 2252 #define MLXSW_REG_SMID2_LEN 0x120 2253 2254 MLXSW_REG_DEFINE(smid2, MLXSW_REG_SMID2_ID, MLXSW_REG_SMID2_LEN); 2255 2256 /* reg_smid2_swid 2257 * Switch partition ID. 2258 * Access: Index 2259 */ 2260 MLXSW_ITEM32(reg, smid2, swid, 0x00, 24, 8); 2261 2262 /* reg_smid2_mid 2263 * Multicast identifier - global identifier that represents the multicast group 2264 * across all devices. 2265 * Access: Index 2266 */ 2267 MLXSW_ITEM32(reg, smid2, mid, 0x00, 0, 16); 2268 2269 /* reg_smid2_smpe_valid 2270 * SMPE is valid. 2271 * When not valid, the egress VID will not be modified by the SMPE table. 2272 * Access: RW 2273 * 2274 * Note: Reserved when legacy bridge model is used and on Spectrum-2. 2275 */ 2276 MLXSW_ITEM32(reg, smid2, smpe_valid, 0x08, 20, 1); 2277 2278 /* reg_smid2_smpe 2279 * Switch multicast port to egress VID. 2280 * Access: RW 2281 * 2282 * Note: Reserved when legacy bridge model is used and on Spectrum-2. 2283 */ 2284 MLXSW_ITEM32(reg, smid2, smpe, 0x08, 0, 16); 2285 2286 /* reg_smid2_port 2287 * Local port memebership (1 bit per port). 2288 * Access: RW 2289 */ 2290 MLXSW_ITEM_BIT_ARRAY(reg, smid2, port, 0x20, 0x80, 1); 2291 2292 /* reg_smid2_port_mask 2293 * Local port mask (1 bit per port). 2294 * Access: WO 2295 */ 2296 MLXSW_ITEM_BIT_ARRAY(reg, smid2, port_mask, 0xA0, 0x80, 1); 2297 2298 static inline void mlxsw_reg_smid2_pack(char *payload, u16 mid, u16 port, 2299 bool set, bool smpe_valid, u16 smpe) 2300 { 2301 MLXSW_REG_ZERO(smid2, payload); 2302 mlxsw_reg_smid2_swid_set(payload, 0); 2303 mlxsw_reg_smid2_mid_set(payload, mid); 2304 mlxsw_reg_smid2_port_set(payload, port, set); 2305 mlxsw_reg_smid2_port_mask_set(payload, port, 1); 2306 mlxsw_reg_smid2_smpe_valid_set(payload, smpe_valid); 2307 mlxsw_reg_smid2_smpe_set(payload, smpe_valid ? smpe : 0); 2308 } 2309 2310 /* CWTP - Congetion WRED ECN TClass Profile 2311 * ---------------------------------------- 2312 * Configures the profiles for queues of egress port and traffic class 2313 */ 2314 #define MLXSW_REG_CWTP_ID 0x2802 2315 #define MLXSW_REG_CWTP_BASE_LEN 0x28 2316 #define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08 2317 #define MLXSW_REG_CWTP_LEN 0x40 2318 2319 MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN); 2320 2321 /* reg_cwtp_local_port 2322 * Local port number 2323 * Not supported for CPU port 2324 * Access: Index 2325 */ 2326 MLXSW_ITEM32_LP(reg, cwtp, 0x00, 16, 0x00, 12); 2327 2328 /* reg_cwtp_traffic_class 2329 * Traffic Class to configure 2330 * Access: Index 2331 */ 2332 MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8); 2333 2334 /* reg_cwtp_profile_min 2335 * Minimum Average Queue Size of the profile in cells. 2336 * Access: RW 2337 */ 2338 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN, 2339 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false); 2340 2341 /* reg_cwtp_profile_percent 2342 * Percentage of WRED and ECN marking for maximum Average Queue size 2343 * Range is 0 to 100, units of integer percentage 2344 * Access: RW 2345 */ 2346 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN, 2347 24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 2348 2349 /* reg_cwtp_profile_max 2350 * Maximum Average Queue size of the profile in cells 2351 * Access: RW 2352 */ 2353 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN, 2354 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 2355 2356 #define MLXSW_REG_CWTP_MIN_VALUE 64 2357 #define MLXSW_REG_CWTP_MAX_PROFILE 2 2358 #define MLXSW_REG_CWTP_DEFAULT_PROFILE 1 2359 2360 static inline void mlxsw_reg_cwtp_pack(char *payload, u16 local_port, 2361 u8 traffic_class) 2362 { 2363 int i; 2364 2365 MLXSW_REG_ZERO(cwtp, payload); 2366 mlxsw_reg_cwtp_local_port_set(payload, local_port); 2367 mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class); 2368 2369 for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) { 2370 mlxsw_reg_cwtp_profile_min_set(payload, i, 2371 MLXSW_REG_CWTP_MIN_VALUE); 2372 mlxsw_reg_cwtp_profile_max_set(payload, i, 2373 MLXSW_REG_CWTP_MIN_VALUE); 2374 } 2375 } 2376 2377 #define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1) 2378 2379 static inline void 2380 mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max, 2381 u32 probability) 2382 { 2383 u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile); 2384 2385 mlxsw_reg_cwtp_profile_min_set(payload, index, min); 2386 mlxsw_reg_cwtp_profile_max_set(payload, index, max); 2387 mlxsw_reg_cwtp_profile_percent_set(payload, index, probability); 2388 } 2389 2390 /* CWTPM - Congestion WRED ECN TClass and Pool Mapping 2391 * --------------------------------------------------- 2392 * The CWTPM register maps each egress port and traffic class to profile num. 2393 */ 2394 #define MLXSW_REG_CWTPM_ID 0x2803 2395 #define MLXSW_REG_CWTPM_LEN 0x44 2396 2397 MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN); 2398 2399 /* reg_cwtpm_local_port 2400 * Local port number 2401 * Not supported for CPU port 2402 * Access: Index 2403 */ 2404 MLXSW_ITEM32_LP(reg, cwtpm, 0x00, 16, 0x00, 12); 2405 2406 /* reg_cwtpm_traffic_class 2407 * Traffic Class to configure 2408 * Access: Index 2409 */ 2410 MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8); 2411 2412 /* reg_cwtpm_ew 2413 * Control enablement of WRED for traffic class: 2414 * 0 - Disable 2415 * 1 - Enable 2416 * Access: RW 2417 */ 2418 MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1); 2419 2420 /* reg_cwtpm_ee 2421 * Control enablement of ECN for traffic class: 2422 * 0 - Disable 2423 * 1 - Enable 2424 * Access: RW 2425 */ 2426 MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1); 2427 2428 /* reg_cwtpm_tcp_g 2429 * TCP Green Profile. 2430 * Index of the profile within {port, traffic class} to use. 2431 * 0 for disabling both WRED and ECN for this type of traffic. 2432 * Access: RW 2433 */ 2434 MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2); 2435 2436 /* reg_cwtpm_tcp_y 2437 * TCP Yellow Profile. 2438 * Index of the profile within {port, traffic class} to use. 2439 * 0 for disabling both WRED and ECN for this type of traffic. 2440 * Access: RW 2441 */ 2442 MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2); 2443 2444 /* reg_cwtpm_tcp_r 2445 * TCP Red Profile. 2446 * Index of the profile within {port, traffic class} to use. 2447 * 0 for disabling both WRED and ECN for this type of traffic. 2448 * Access: RW 2449 */ 2450 MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2); 2451 2452 /* reg_cwtpm_ntcp_g 2453 * Non-TCP Green Profile. 2454 * Index of the profile within {port, traffic class} to use. 2455 * 0 for disabling both WRED and ECN for this type of traffic. 2456 * Access: RW 2457 */ 2458 MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2); 2459 2460 /* reg_cwtpm_ntcp_y 2461 * Non-TCP Yellow Profile. 2462 * Index of the profile within {port, traffic class} to use. 2463 * 0 for disabling both WRED and ECN for this type of traffic. 2464 * Access: RW 2465 */ 2466 MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2); 2467 2468 /* reg_cwtpm_ntcp_r 2469 * Non-TCP Red Profile. 2470 * Index of the profile within {port, traffic class} to use. 2471 * 0 for disabling both WRED and ECN for this type of traffic. 2472 * Access: RW 2473 */ 2474 MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2); 2475 2476 #define MLXSW_REG_CWTPM_RESET_PROFILE 0 2477 2478 static inline void mlxsw_reg_cwtpm_pack(char *payload, u16 local_port, 2479 u8 traffic_class, u8 profile, 2480 bool wred, bool ecn) 2481 { 2482 MLXSW_REG_ZERO(cwtpm, payload); 2483 mlxsw_reg_cwtpm_local_port_set(payload, local_port); 2484 mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class); 2485 mlxsw_reg_cwtpm_ew_set(payload, wred); 2486 mlxsw_reg_cwtpm_ee_set(payload, ecn); 2487 mlxsw_reg_cwtpm_tcp_g_set(payload, profile); 2488 mlxsw_reg_cwtpm_tcp_y_set(payload, profile); 2489 mlxsw_reg_cwtpm_tcp_r_set(payload, profile); 2490 mlxsw_reg_cwtpm_ntcp_g_set(payload, profile); 2491 mlxsw_reg_cwtpm_ntcp_y_set(payload, profile); 2492 mlxsw_reg_cwtpm_ntcp_r_set(payload, profile); 2493 } 2494 2495 /* PGCR - Policy-Engine General Configuration Register 2496 * --------------------------------------------------- 2497 * This register configures general Policy-Engine settings. 2498 */ 2499 #define MLXSW_REG_PGCR_ID 0x3001 2500 #define MLXSW_REG_PGCR_LEN 0x20 2501 2502 MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN); 2503 2504 /* reg_pgcr_default_action_pointer_base 2505 * Default action pointer base. Each region has a default action pointer 2506 * which is equal to default_action_pointer_base + region_id. 2507 * Access: RW 2508 */ 2509 MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24); 2510 2511 static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base) 2512 { 2513 MLXSW_REG_ZERO(pgcr, payload); 2514 mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base); 2515 } 2516 2517 /* PPBT - Policy-Engine Port Binding Table 2518 * --------------------------------------- 2519 * This register is used for configuration of the Port Binding Table. 2520 */ 2521 #define MLXSW_REG_PPBT_ID 0x3002 2522 #define MLXSW_REG_PPBT_LEN 0x14 2523 2524 MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN); 2525 2526 enum mlxsw_reg_pxbt_e { 2527 MLXSW_REG_PXBT_E_IACL, 2528 MLXSW_REG_PXBT_E_EACL, 2529 }; 2530 2531 /* reg_ppbt_e 2532 * Access: Index 2533 */ 2534 MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1); 2535 2536 enum mlxsw_reg_pxbt_op { 2537 MLXSW_REG_PXBT_OP_BIND, 2538 MLXSW_REG_PXBT_OP_UNBIND, 2539 }; 2540 2541 /* reg_ppbt_op 2542 * Access: RW 2543 */ 2544 MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3); 2545 2546 /* reg_ppbt_local_port 2547 * Local port. Not including CPU port. 2548 * Access: Index 2549 */ 2550 MLXSW_ITEM32_LP(reg, ppbt, 0x00, 16, 0x00, 12); 2551 2552 /* reg_ppbt_g 2553 * group - When set, the binding is of an ACL group. When cleared, 2554 * the binding is of an ACL. 2555 * Must be set to 1 for Spectrum. 2556 * Access: RW 2557 */ 2558 MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1); 2559 2560 /* reg_ppbt_acl_info 2561 * ACL/ACL group identifier. If the g bit is set, this field should hold 2562 * the acl_group_id, else it should hold the acl_id. 2563 * Access: RW 2564 */ 2565 MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16); 2566 2567 static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e, 2568 enum mlxsw_reg_pxbt_op op, 2569 u16 local_port, u16 acl_info) 2570 { 2571 MLXSW_REG_ZERO(ppbt, payload); 2572 mlxsw_reg_ppbt_e_set(payload, e); 2573 mlxsw_reg_ppbt_op_set(payload, op); 2574 mlxsw_reg_ppbt_local_port_set(payload, local_port); 2575 mlxsw_reg_ppbt_g_set(payload, true); 2576 mlxsw_reg_ppbt_acl_info_set(payload, acl_info); 2577 } 2578 2579 /* PACL - Policy-Engine ACL Register 2580 * --------------------------------- 2581 * This register is used for configuration of the ACL. 2582 */ 2583 #define MLXSW_REG_PACL_ID 0x3004 2584 #define MLXSW_REG_PACL_LEN 0x70 2585 2586 MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN); 2587 2588 /* reg_pacl_v 2589 * Valid. Setting the v bit makes the ACL valid. It should not be cleared 2590 * while the ACL is bounded to either a port, VLAN or ACL rule. 2591 * Access: RW 2592 */ 2593 MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1); 2594 2595 /* reg_pacl_acl_id 2596 * An identifier representing the ACL (managed by software) 2597 * Range 0 .. cap_max_acl_regions - 1 2598 * Access: Index 2599 */ 2600 MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16); 2601 2602 #define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16 2603 2604 /* reg_pacl_tcam_region_info 2605 * Opaque object that represents a TCAM region. 2606 * Obtained through PTAR register. 2607 * Access: RW 2608 */ 2609 MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30, 2610 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2611 2612 static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id, 2613 bool valid, const char *tcam_region_info) 2614 { 2615 MLXSW_REG_ZERO(pacl, payload); 2616 mlxsw_reg_pacl_acl_id_set(payload, acl_id); 2617 mlxsw_reg_pacl_v_set(payload, valid); 2618 mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info); 2619 } 2620 2621 /* PAGT - Policy-Engine ACL Group Table 2622 * ------------------------------------ 2623 * This register is used for configuration of the ACL Group Table. 2624 */ 2625 #define MLXSW_REG_PAGT_ID 0x3005 2626 #define MLXSW_REG_PAGT_BASE_LEN 0x30 2627 #define MLXSW_REG_PAGT_ACL_LEN 4 2628 #define MLXSW_REG_PAGT_ACL_MAX_NUM 16 2629 #define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \ 2630 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN) 2631 2632 MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN); 2633 2634 /* reg_pagt_size 2635 * Number of ACLs in the group. 2636 * Size 0 invalidates a group. 2637 * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now) 2638 * Total number of ACLs in all groups must be lower or equal 2639 * to cap_max_acl_tot_groups 2640 * Note: a group which is binded must not be invalidated 2641 * Access: Index 2642 */ 2643 MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8); 2644 2645 /* reg_pagt_acl_group_id 2646 * An identifier (numbered from 0..cap_max_acl_groups-1) representing 2647 * the ACL Group identifier (managed by software). 2648 * Access: Index 2649 */ 2650 MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16); 2651 2652 /* reg_pagt_multi 2653 * Multi-ACL 2654 * 0 - This ACL is the last ACL in the multi-ACL 2655 * 1 - This ACL is part of a multi-ACL 2656 * Access: RW 2657 */ 2658 MLXSW_ITEM32_INDEXED(reg, pagt, multi, 0x30, 31, 1, 0x04, 0x00, false); 2659 2660 /* reg_pagt_acl_id 2661 * ACL identifier 2662 * Access: RW 2663 */ 2664 MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false); 2665 2666 static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id) 2667 { 2668 MLXSW_REG_ZERO(pagt, payload); 2669 mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id); 2670 } 2671 2672 static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index, 2673 u16 acl_id, bool multi) 2674 { 2675 u8 size = mlxsw_reg_pagt_size_get(payload); 2676 2677 if (index >= size) 2678 mlxsw_reg_pagt_size_set(payload, index + 1); 2679 mlxsw_reg_pagt_multi_set(payload, index, multi); 2680 mlxsw_reg_pagt_acl_id_set(payload, index, acl_id); 2681 } 2682 2683 /* PTAR - Policy-Engine TCAM Allocation Register 2684 * --------------------------------------------- 2685 * This register is used for allocation of regions in the TCAM. 2686 * Note: Query method is not supported on this register. 2687 */ 2688 #define MLXSW_REG_PTAR_ID 0x3006 2689 #define MLXSW_REG_PTAR_BASE_LEN 0x20 2690 #define MLXSW_REG_PTAR_KEY_ID_LEN 1 2691 #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16 2692 #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \ 2693 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN) 2694 2695 MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN); 2696 2697 enum mlxsw_reg_ptar_op { 2698 /* allocate a TCAM region */ 2699 MLXSW_REG_PTAR_OP_ALLOC, 2700 /* resize a TCAM region */ 2701 MLXSW_REG_PTAR_OP_RESIZE, 2702 /* deallocate TCAM region */ 2703 MLXSW_REG_PTAR_OP_FREE, 2704 /* test allocation */ 2705 MLXSW_REG_PTAR_OP_TEST, 2706 }; 2707 2708 /* reg_ptar_op 2709 * Access: OP 2710 */ 2711 MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4); 2712 2713 /* reg_ptar_action_set_type 2714 * Type of action set to be used on this region. 2715 * For Spectrum and Spectrum-2, this is always type 2 - "flexible" 2716 * Access: WO 2717 */ 2718 MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8); 2719 2720 enum mlxsw_reg_ptar_key_type { 2721 MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50, /* Spetrum */ 2722 MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51, /* Spectrum-2 */ 2723 }; 2724 2725 /* reg_ptar_key_type 2726 * TCAM key type for the region. 2727 * Access: WO 2728 */ 2729 MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8); 2730 2731 /* reg_ptar_region_size 2732 * TCAM region size. When allocating/resizing this is the requested size, 2733 * the response is the actual size. Note that actual size may be 2734 * larger than requested. 2735 * Allowed range 1 .. cap_max_rules-1 2736 * Reserved during op deallocate. 2737 * Access: WO 2738 */ 2739 MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16); 2740 2741 /* reg_ptar_region_id 2742 * Region identifier 2743 * Range 0 .. cap_max_regions-1 2744 * Access: Index 2745 */ 2746 MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16); 2747 2748 /* reg_ptar_tcam_region_info 2749 * Opaque object that represents the TCAM region. 2750 * Returned when allocating a region. 2751 * Provided by software for ACL generation and region deallocation and resize. 2752 * Access: RW 2753 */ 2754 MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10, 2755 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2756 2757 /* reg_ptar_flexible_key_id 2758 * Identifier of the Flexible Key. 2759 * Only valid if key_type == "FLEX_KEY" 2760 * The key size will be rounded up to one of the following values: 2761 * 9B, 18B, 36B, 54B. 2762 * This field is reserved for in resize operation. 2763 * Access: WO 2764 */ 2765 MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8, 2766 MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false); 2767 2768 static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op, 2769 enum mlxsw_reg_ptar_key_type key_type, 2770 u16 region_size, u16 region_id, 2771 const char *tcam_region_info) 2772 { 2773 MLXSW_REG_ZERO(ptar, payload); 2774 mlxsw_reg_ptar_op_set(payload, op); 2775 mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */ 2776 mlxsw_reg_ptar_key_type_set(payload, key_type); 2777 mlxsw_reg_ptar_region_size_set(payload, region_size); 2778 mlxsw_reg_ptar_region_id_set(payload, region_id); 2779 mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info); 2780 } 2781 2782 static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index, 2783 u16 key_id) 2784 { 2785 mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id); 2786 } 2787 2788 static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info) 2789 { 2790 mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info); 2791 } 2792 2793 /* PPRR - Policy-Engine Port Range Register 2794 * ---------------------------------------- 2795 * This register is used for configuring port range identification. 2796 */ 2797 #define MLXSW_REG_PPRR_ID 0x3008 2798 #define MLXSW_REG_PPRR_LEN 0x14 2799 2800 MLXSW_REG_DEFINE(pprr, MLXSW_REG_PPRR_ID, MLXSW_REG_PPRR_LEN); 2801 2802 /* reg_pprr_ipv4 2803 * Apply port range register to IPv4 packets. 2804 * Access: RW 2805 */ 2806 MLXSW_ITEM32(reg, pprr, ipv4, 0x00, 31, 1); 2807 2808 /* reg_pprr_ipv6 2809 * Apply port range register to IPv6 packets. 2810 * Access: RW 2811 */ 2812 MLXSW_ITEM32(reg, pprr, ipv6, 0x00, 30, 1); 2813 2814 /* reg_pprr_src 2815 * Apply port range register to source L4 ports. 2816 * Access: RW 2817 */ 2818 MLXSW_ITEM32(reg, pprr, src, 0x00, 29, 1); 2819 2820 /* reg_pprr_dst 2821 * Apply port range register to destination L4 ports. 2822 * Access: RW 2823 */ 2824 MLXSW_ITEM32(reg, pprr, dst, 0x00, 28, 1); 2825 2826 /* reg_pprr_tcp 2827 * Apply port range register to TCP packets. 2828 * Access: RW 2829 */ 2830 MLXSW_ITEM32(reg, pprr, tcp, 0x00, 27, 1); 2831 2832 /* reg_pprr_udp 2833 * Apply port range register to UDP packets. 2834 * Access: RW 2835 */ 2836 MLXSW_ITEM32(reg, pprr, udp, 0x00, 26, 1); 2837 2838 /* reg_pprr_register_index 2839 * Index of Port Range Register being accessed. 2840 * Range is 0..cap_max_acl_l4_port_range-1. 2841 * Access: Index 2842 */ 2843 MLXSW_ITEM32(reg, pprr, register_index, 0x00, 0, 8); 2844 2845 /* reg_prrr_port_range_min 2846 * Minimum port range for comparison. 2847 * Match is defined as: 2848 * port_range_min <= packet_port <= port_range_max. 2849 * Access: RW 2850 */ 2851 MLXSW_ITEM32(reg, pprr, port_range_min, 0x04, 16, 16); 2852 2853 /* reg_prrr_port_range_max 2854 * Maximum port range for comparison. 2855 * Access: RW 2856 */ 2857 MLXSW_ITEM32(reg, pprr, port_range_max, 0x04, 0, 16); 2858 2859 static inline void mlxsw_reg_pprr_pack(char *payload, u8 register_index) 2860 { 2861 MLXSW_REG_ZERO(pprr, payload); 2862 mlxsw_reg_pprr_register_index_set(payload, register_index); 2863 } 2864 2865 /* PPBS - Policy-Engine Policy Based Switching Register 2866 * ---------------------------------------------------- 2867 * This register retrieves and sets Policy Based Switching Table entries. 2868 */ 2869 #define MLXSW_REG_PPBS_ID 0x300C 2870 #define MLXSW_REG_PPBS_LEN 0x14 2871 2872 MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN); 2873 2874 /* reg_ppbs_pbs_ptr 2875 * Index into the PBS table. 2876 * For Spectrum, the index points to the KVD Linear. 2877 * Access: Index 2878 */ 2879 MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24); 2880 2881 /* reg_ppbs_system_port 2882 * Unique port identifier for the final destination of the packet. 2883 * Access: RW 2884 */ 2885 MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16); 2886 2887 static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr, 2888 u16 system_port) 2889 { 2890 MLXSW_REG_ZERO(ppbs, payload); 2891 mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr); 2892 mlxsw_reg_ppbs_system_port_set(payload, system_port); 2893 } 2894 2895 /* PRCR - Policy-Engine Rules Copy Register 2896 * ---------------------------------------- 2897 * This register is used for accessing rules within a TCAM region. 2898 */ 2899 #define MLXSW_REG_PRCR_ID 0x300D 2900 #define MLXSW_REG_PRCR_LEN 0x40 2901 2902 MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN); 2903 2904 enum mlxsw_reg_prcr_op { 2905 /* Move rules. Moves the rules from "tcam_region_info" starting 2906 * at offset "offset" to "dest_tcam_region_info" 2907 * at offset "dest_offset." 2908 */ 2909 MLXSW_REG_PRCR_OP_MOVE, 2910 /* Copy rules. Copies the rules from "tcam_region_info" starting 2911 * at offset "offset" to "dest_tcam_region_info" 2912 * at offset "dest_offset." 2913 */ 2914 MLXSW_REG_PRCR_OP_COPY, 2915 }; 2916 2917 /* reg_prcr_op 2918 * Access: OP 2919 */ 2920 MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4); 2921 2922 /* reg_prcr_offset 2923 * Offset within the source region to copy/move from. 2924 * Access: Index 2925 */ 2926 MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16); 2927 2928 /* reg_prcr_size 2929 * The number of rules to copy/move. 2930 * Access: WO 2931 */ 2932 MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16); 2933 2934 /* reg_prcr_tcam_region_info 2935 * Opaque object that represents the source TCAM region. 2936 * Access: Index 2937 */ 2938 MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10, 2939 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2940 2941 /* reg_prcr_dest_offset 2942 * Offset within the source region to copy/move to. 2943 * Access: Index 2944 */ 2945 MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16); 2946 2947 /* reg_prcr_dest_tcam_region_info 2948 * Opaque object that represents the destination TCAM region. 2949 * Access: Index 2950 */ 2951 MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30, 2952 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2953 2954 static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op, 2955 const char *src_tcam_region_info, 2956 u16 src_offset, 2957 const char *dest_tcam_region_info, 2958 u16 dest_offset, u16 size) 2959 { 2960 MLXSW_REG_ZERO(prcr, payload); 2961 mlxsw_reg_prcr_op_set(payload, op); 2962 mlxsw_reg_prcr_offset_set(payload, src_offset); 2963 mlxsw_reg_prcr_size_set(payload, size); 2964 mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload, 2965 src_tcam_region_info); 2966 mlxsw_reg_prcr_dest_offset_set(payload, dest_offset); 2967 mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload, 2968 dest_tcam_region_info); 2969 } 2970 2971 /* PEFA - Policy-Engine Extended Flexible Action Register 2972 * ------------------------------------------------------ 2973 * This register is used for accessing an extended flexible action entry 2974 * in the central KVD Linear Database. 2975 */ 2976 #define MLXSW_REG_PEFA_ID 0x300F 2977 #define MLXSW_REG_PEFA_LEN 0xB0 2978 2979 MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN); 2980 2981 /* reg_pefa_index 2982 * Index in the KVD Linear Centralized Database. 2983 * Access: Index 2984 */ 2985 MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24); 2986 2987 /* reg_pefa_a 2988 * Index in the KVD Linear Centralized Database. 2989 * Activity 2990 * For a new entry: set if ca=0, clear if ca=1 2991 * Set if a packet lookup has hit on the specific entry 2992 * Access: RO 2993 */ 2994 MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1); 2995 2996 /* reg_pefa_ca 2997 * Clear activity 2998 * When write: activity is according to this field 2999 * When read: after reading the activity is cleared according to ca 3000 * Access: OP 3001 */ 3002 MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1); 3003 3004 #define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8 3005 3006 /* reg_pefa_flex_action_set 3007 * Action-set to perform when rule is matched. 3008 * Must be zero padded if action set is shorter. 3009 * Access: RW 3010 */ 3011 MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN); 3012 3013 static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca, 3014 const char *flex_action_set) 3015 { 3016 MLXSW_REG_ZERO(pefa, payload); 3017 mlxsw_reg_pefa_index_set(payload, index); 3018 mlxsw_reg_pefa_ca_set(payload, ca); 3019 if (flex_action_set) 3020 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload, 3021 flex_action_set); 3022 } 3023 3024 static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a) 3025 { 3026 *p_a = mlxsw_reg_pefa_a_get(payload); 3027 } 3028 3029 /* PEMRBT - Policy-Engine Multicast Router Binding Table Register 3030 * -------------------------------------------------------------- 3031 * This register is used for binding Multicast router to an ACL group 3032 * that serves the MC router. 3033 * This register is not supported by SwitchX/-2 and Spectrum. 3034 */ 3035 #define MLXSW_REG_PEMRBT_ID 0x3014 3036 #define MLXSW_REG_PEMRBT_LEN 0x14 3037 3038 MLXSW_REG_DEFINE(pemrbt, MLXSW_REG_PEMRBT_ID, MLXSW_REG_PEMRBT_LEN); 3039 3040 enum mlxsw_reg_pemrbt_protocol { 3041 MLXSW_REG_PEMRBT_PROTO_IPV4, 3042 MLXSW_REG_PEMRBT_PROTO_IPV6, 3043 }; 3044 3045 /* reg_pemrbt_protocol 3046 * Access: Index 3047 */ 3048 MLXSW_ITEM32(reg, pemrbt, protocol, 0x00, 0, 1); 3049 3050 /* reg_pemrbt_group_id 3051 * ACL group identifier. 3052 * Range 0..cap_max_acl_groups-1 3053 * Access: RW 3054 */ 3055 MLXSW_ITEM32(reg, pemrbt, group_id, 0x10, 0, 16); 3056 3057 static inline void 3058 mlxsw_reg_pemrbt_pack(char *payload, enum mlxsw_reg_pemrbt_protocol protocol, 3059 u16 group_id) 3060 { 3061 MLXSW_REG_ZERO(pemrbt, payload); 3062 mlxsw_reg_pemrbt_protocol_set(payload, protocol); 3063 mlxsw_reg_pemrbt_group_id_set(payload, group_id); 3064 } 3065 3066 /* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2 3067 * ----------------------------------------------------- 3068 * This register is used for accessing rules within a TCAM region. 3069 * It is a new version of PTCE in order to support wider key, 3070 * mask and action within a TCAM region. This register is not supported 3071 * by SwitchX and SwitchX-2. 3072 */ 3073 #define MLXSW_REG_PTCE2_ID 0x3017 3074 #define MLXSW_REG_PTCE2_LEN 0x1D8 3075 3076 MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN); 3077 3078 /* reg_ptce2_v 3079 * Valid. 3080 * Access: RW 3081 */ 3082 MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1); 3083 3084 /* reg_ptce2_a 3085 * Activity. Set if a packet lookup has hit on the specific entry. 3086 * To clear the "a" bit, use "clear activity" op or "clear on read" op. 3087 * Access: RO 3088 */ 3089 MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1); 3090 3091 enum mlxsw_reg_ptce2_op { 3092 /* Read operation. */ 3093 MLXSW_REG_PTCE2_OP_QUERY_READ = 0, 3094 /* clear on read operation. Used to read entry 3095 * and clear Activity bit. 3096 */ 3097 MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1, 3098 /* Write operation. Used to write a new entry to the table. 3099 * All R/W fields are relevant for new entry. Activity bit is set 3100 * for new entries - Note write with v = 0 will delete the entry. 3101 */ 3102 MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0, 3103 /* Update action. Only action set will be updated. */ 3104 MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1, 3105 /* Clear activity. A bit is cleared for the entry. */ 3106 MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2, 3107 }; 3108 3109 /* reg_ptce2_op 3110 * Access: OP 3111 */ 3112 MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3); 3113 3114 /* reg_ptce2_offset 3115 * Access: Index 3116 */ 3117 MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16); 3118 3119 /* reg_ptce2_priority 3120 * Priority of the rule, higher values win. The range is 1..cap_kvd_size-1. 3121 * Note: priority does not have to be unique per rule. 3122 * Within a region, higher priority should have lower offset (no limitation 3123 * between regions in a multi-region). 3124 * Access: RW 3125 */ 3126 MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24); 3127 3128 /* reg_ptce2_tcam_region_info 3129 * Opaque object that represents the TCAM region. 3130 * Access: Index 3131 */ 3132 MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10, 3133 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 3134 3135 #define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 96 3136 3137 /* reg_ptce2_flex_key_blocks 3138 * ACL Key. 3139 * Access: RW 3140 */ 3141 MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20, 3142 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 3143 3144 /* reg_ptce2_mask 3145 * mask- in the same size as key. A bit that is set directs the TCAM 3146 * to compare the corresponding bit in key. A bit that is clear directs 3147 * the TCAM to ignore the corresponding bit in key. 3148 * Access: RW 3149 */ 3150 MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80, 3151 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 3152 3153 /* reg_ptce2_flex_action_set 3154 * ACL action set. 3155 * Access: RW 3156 */ 3157 MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0, 3158 MLXSW_REG_FLEX_ACTION_SET_LEN); 3159 3160 static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid, 3161 enum mlxsw_reg_ptce2_op op, 3162 const char *tcam_region_info, 3163 u16 offset, u32 priority) 3164 { 3165 MLXSW_REG_ZERO(ptce2, payload); 3166 mlxsw_reg_ptce2_v_set(payload, valid); 3167 mlxsw_reg_ptce2_op_set(payload, op); 3168 mlxsw_reg_ptce2_offset_set(payload, offset); 3169 mlxsw_reg_ptce2_priority_set(payload, priority); 3170 mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info); 3171 } 3172 3173 /* PERPT - Policy-Engine ERP Table Register 3174 * ---------------------------------------- 3175 * This register adds and removes eRPs from the eRP table. 3176 */ 3177 #define MLXSW_REG_PERPT_ID 0x3021 3178 #define MLXSW_REG_PERPT_LEN 0x80 3179 3180 MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN); 3181 3182 /* reg_perpt_erpt_bank 3183 * eRP table bank. 3184 * Range 0 .. cap_max_erp_table_banks - 1 3185 * Access: Index 3186 */ 3187 MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4); 3188 3189 /* reg_perpt_erpt_index 3190 * Index to eRP table within the eRP bank. 3191 * Range is 0 .. cap_max_erp_table_bank_size - 1 3192 * Access: Index 3193 */ 3194 MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8); 3195 3196 enum mlxsw_reg_perpt_key_size { 3197 MLXSW_REG_PERPT_KEY_SIZE_2KB, 3198 MLXSW_REG_PERPT_KEY_SIZE_4KB, 3199 MLXSW_REG_PERPT_KEY_SIZE_8KB, 3200 MLXSW_REG_PERPT_KEY_SIZE_12KB, 3201 }; 3202 3203 /* reg_perpt_key_size 3204 * Access: OP 3205 */ 3206 MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4); 3207 3208 /* reg_perpt_bf_bypass 3209 * 0 - The eRP is used only if bloom filter state is set for the given 3210 * rule. 3211 * 1 - The eRP is used regardless of bloom filter state. 3212 * The bypass is an OR condition of region_id or eRP. See PERCR.bf_bypass 3213 * Access: RW 3214 */ 3215 MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1); 3216 3217 /* reg_perpt_erp_id 3218 * eRP ID for use by the rules. 3219 * Access: RW 3220 */ 3221 MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4); 3222 3223 /* reg_perpt_erpt_base_bank 3224 * Base eRP table bank, points to head of erp_vector 3225 * Range is 0 .. cap_max_erp_table_banks - 1 3226 * Access: OP 3227 */ 3228 MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4); 3229 3230 /* reg_perpt_erpt_base_index 3231 * Base index to eRP table within the eRP bank 3232 * Range is 0 .. cap_max_erp_table_bank_size - 1 3233 * Access: OP 3234 */ 3235 MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8); 3236 3237 /* reg_perpt_erp_index_in_vector 3238 * eRP index in the vector. 3239 * Access: OP 3240 */ 3241 MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4); 3242 3243 /* reg_perpt_erp_vector 3244 * eRP vector. 3245 * Access: OP 3246 */ 3247 MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1); 3248 3249 /* reg_perpt_mask 3250 * Mask 3251 * 0 - A-TCAM will ignore the bit in key 3252 * 1 - A-TCAM will compare the bit in key 3253 * Access: RW 3254 */ 3255 MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 3256 3257 static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload, 3258 unsigned long *erp_vector, 3259 unsigned long size) 3260 { 3261 unsigned long bit; 3262 3263 for_each_set_bit(bit, erp_vector, size) 3264 mlxsw_reg_perpt_erp_vector_set(payload, bit, true); 3265 } 3266 3267 static inline void 3268 mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index, 3269 enum mlxsw_reg_perpt_key_size key_size, u8 erp_id, 3270 u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index, 3271 char *mask) 3272 { 3273 MLXSW_REG_ZERO(perpt, payload); 3274 mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank); 3275 mlxsw_reg_perpt_erpt_index_set(payload, erpt_index); 3276 mlxsw_reg_perpt_key_size_set(payload, key_size); 3277 mlxsw_reg_perpt_bf_bypass_set(payload, false); 3278 mlxsw_reg_perpt_erp_id_set(payload, erp_id); 3279 mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank); 3280 mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index); 3281 mlxsw_reg_perpt_erp_index_in_vector_set(payload, erp_index); 3282 mlxsw_reg_perpt_mask_memcpy_to(payload, mask); 3283 } 3284 3285 /* PERAR - Policy-Engine Region Association Register 3286 * ------------------------------------------------- 3287 * This register associates a hw region for region_id's. Changing on the fly 3288 * is supported by the device. 3289 */ 3290 #define MLXSW_REG_PERAR_ID 0x3026 3291 #define MLXSW_REG_PERAR_LEN 0x08 3292 3293 MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN); 3294 3295 /* reg_perar_region_id 3296 * Region identifier 3297 * Range 0 .. cap_max_regions-1 3298 * Access: Index 3299 */ 3300 MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16); 3301 3302 static inline unsigned int 3303 mlxsw_reg_perar_hw_regions_needed(unsigned int block_num) 3304 { 3305 return DIV_ROUND_UP(block_num, 4); 3306 } 3307 3308 /* reg_perar_hw_region 3309 * HW Region 3310 * Range 0 .. cap_max_regions-1 3311 * Default: hw_region = region_id 3312 * For a 8 key block region, 2 consecutive regions are used 3313 * For a 12 key block region, 3 consecutive regions are used 3314 * Access: RW 3315 */ 3316 MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16); 3317 3318 static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id, 3319 u16 hw_region) 3320 { 3321 MLXSW_REG_ZERO(perar, payload); 3322 mlxsw_reg_perar_region_id_set(payload, region_id); 3323 mlxsw_reg_perar_hw_region_set(payload, hw_region); 3324 } 3325 3326 /* PTCE-V3 - Policy-Engine TCAM Entry Register Version 3 3327 * ----------------------------------------------------- 3328 * This register is a new version of PTCE-V2 in order to support the 3329 * A-TCAM. This register is not supported by SwitchX/-2 and Spectrum. 3330 */ 3331 #define MLXSW_REG_PTCE3_ID 0x3027 3332 #define MLXSW_REG_PTCE3_LEN 0xF0 3333 3334 MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN); 3335 3336 /* reg_ptce3_v 3337 * Valid. 3338 * Access: RW 3339 */ 3340 MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1); 3341 3342 enum mlxsw_reg_ptce3_op { 3343 /* Write operation. Used to write a new entry to the table. 3344 * All R/W fields are relevant for new entry. Activity bit is set 3345 * for new entries. Write with v = 0 will delete the entry. Must 3346 * not be used if an entry exists. 3347 */ 3348 MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0, 3349 /* Update operation */ 3350 MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1, 3351 /* Read operation */ 3352 MLXSW_REG_PTCE3_OP_QUERY_READ = 0, 3353 }; 3354 3355 /* reg_ptce3_op 3356 * Access: OP 3357 */ 3358 MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3); 3359 3360 /* reg_ptce3_priority 3361 * Priority of the rule. Higher values win. 3362 * For Spectrum-2 range is 1..cap_kvd_size - 1 3363 * Note: Priority does not have to be unique per rule. 3364 * Access: RW 3365 */ 3366 MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24); 3367 3368 /* reg_ptce3_tcam_region_info 3369 * Opaque object that represents the TCAM region. 3370 * Access: Index 3371 */ 3372 MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10, 3373 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 3374 3375 /* reg_ptce3_flex2_key_blocks 3376 * ACL key. The key must be masked according to eRP (if exists) or 3377 * according to master mask. 3378 * Access: Index 3379 */ 3380 MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20, 3381 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 3382 3383 /* reg_ptce3_erp_id 3384 * eRP ID. 3385 * Access: Index 3386 */ 3387 MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4); 3388 3389 /* reg_ptce3_delta_start 3390 * Start point of delta_value and delta_mask, in bits. Must not exceed 3391 * num_key_blocks * 36 - 8. Reserved when delta_mask = 0. 3392 * Access: Index 3393 */ 3394 MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10); 3395 3396 /* reg_ptce3_delta_mask 3397 * Delta mask. 3398 * 0 - Ignore relevant bit in delta_value 3399 * 1 - Compare relevant bit in delta_value 3400 * Delta mask must not be set for reserved fields in the key blocks. 3401 * Note: No delta when no eRPs. Thus, for regions with 3402 * PERERP.erpt_pointer_valid = 0 the delta mask must be 0. 3403 * Access: Index 3404 */ 3405 MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8); 3406 3407 /* reg_ptce3_delta_value 3408 * Delta value. 3409 * Bits which are masked by delta_mask must be 0. 3410 * Access: Index 3411 */ 3412 MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8); 3413 3414 /* reg_ptce3_prune_vector 3415 * Pruning vector relative to the PERPT.erp_id. 3416 * Used for reducing lookups. 3417 * 0 - NEED: Do a lookup using the eRP. 3418 * 1 - PRUNE: Do not perform a lookup using the eRP. 3419 * Maybe be modified by PEAPBL and PEAPBM. 3420 * Note: In Spectrum-2, a region of 8 key blocks must be set to either 3421 * all 1's or all 0's. 3422 * Access: RW 3423 */ 3424 MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1); 3425 3426 /* reg_ptce3_prune_ctcam 3427 * Pruning on C-TCAM. Used for reducing lookups. 3428 * 0 - NEED: Do a lookup in the C-TCAM. 3429 * 1 - PRUNE: Do not perform a lookup in the C-TCAM. 3430 * Access: RW 3431 */ 3432 MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1); 3433 3434 /* reg_ptce3_large_exists 3435 * Large entry key ID exists. 3436 * Within the region: 3437 * 0 - SINGLE: The large_entry_key_id is not currently in use. 3438 * For rule insert: The MSB of the key (blocks 6..11) will be added. 3439 * For rule delete: The MSB of the key will be removed. 3440 * 1 - NON_SINGLE: The large_entry_key_id is currently in use. 3441 * For rule insert: The MSB of the key (blocks 6..11) will not be added. 3442 * For rule delete: The MSB of the key will not be removed. 3443 * Access: WO 3444 */ 3445 MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1); 3446 3447 /* reg_ptce3_large_entry_key_id 3448 * Large entry key ID. 3449 * A key for 12 key blocks rules. Reserved when region has less than 12 key 3450 * blocks. Must be different for different keys which have the same common 3451 * 6 key blocks (MSB, blocks 6..11) key within a region. 3452 * Range is 0..cap_max_pe_large_key_id - 1 3453 * Access: RW 3454 */ 3455 MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24); 3456 3457 /* reg_ptce3_action_pointer 3458 * Pointer to action. 3459 * Range is 0..cap_max_kvd_action_sets - 1 3460 * Access: RW 3461 */ 3462 MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24); 3463 3464 static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid, 3465 enum mlxsw_reg_ptce3_op op, 3466 u32 priority, 3467 const char *tcam_region_info, 3468 const char *key, u8 erp_id, 3469 u16 delta_start, u8 delta_mask, 3470 u8 delta_value, bool large_exists, 3471 u32 lkey_id, u32 action_pointer) 3472 { 3473 MLXSW_REG_ZERO(ptce3, payload); 3474 mlxsw_reg_ptce3_v_set(payload, valid); 3475 mlxsw_reg_ptce3_op_set(payload, op); 3476 mlxsw_reg_ptce3_priority_set(payload, priority); 3477 mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info); 3478 mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key); 3479 mlxsw_reg_ptce3_erp_id_set(payload, erp_id); 3480 mlxsw_reg_ptce3_delta_start_set(payload, delta_start); 3481 mlxsw_reg_ptce3_delta_mask_set(payload, delta_mask); 3482 mlxsw_reg_ptce3_delta_value_set(payload, delta_value); 3483 mlxsw_reg_ptce3_large_exists_set(payload, large_exists); 3484 mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id); 3485 mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer); 3486 } 3487 3488 /* PERCR - Policy-Engine Region Configuration Register 3489 * --------------------------------------------------- 3490 * This register configures the region parameters. The region_id must be 3491 * allocated. 3492 */ 3493 #define MLXSW_REG_PERCR_ID 0x302A 3494 #define MLXSW_REG_PERCR_LEN 0x80 3495 3496 MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN); 3497 3498 /* reg_percr_region_id 3499 * Region identifier. 3500 * Range 0..cap_max_regions-1 3501 * Access: Index 3502 */ 3503 MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16); 3504 3505 /* reg_percr_atcam_ignore_prune 3506 * Ignore prune_vector by other A-TCAM rules. Used e.g., for a new rule. 3507 * Access: RW 3508 */ 3509 MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1); 3510 3511 /* reg_percr_ctcam_ignore_prune 3512 * Ignore prune_ctcam by other A-TCAM rules. Used e.g., for a new rule. 3513 * Access: RW 3514 */ 3515 MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1); 3516 3517 /* reg_percr_bf_bypass 3518 * Bloom filter bypass. 3519 * 0 - Bloom filter is used (default) 3520 * 1 - Bloom filter is bypassed. The bypass is an OR condition of 3521 * region_id or eRP. See PERPT.bf_bypass 3522 * Access: RW 3523 */ 3524 MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1); 3525 3526 /* reg_percr_master_mask 3527 * Master mask. Logical OR mask of all masks of all rules of a region 3528 * (both A-TCAM and C-TCAM). When there are no eRPs 3529 * (erpt_pointer_valid = 0), then this provides the mask. 3530 * Access: RW 3531 */ 3532 MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96); 3533 3534 static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id) 3535 { 3536 MLXSW_REG_ZERO(percr, payload); 3537 mlxsw_reg_percr_region_id_set(payload, region_id); 3538 mlxsw_reg_percr_atcam_ignore_prune_set(payload, false); 3539 mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false); 3540 mlxsw_reg_percr_bf_bypass_set(payload, false); 3541 } 3542 3543 /* PERERP - Policy-Engine Region eRP Register 3544 * ------------------------------------------ 3545 * This register configures the region eRP. The region_id must be 3546 * allocated. 3547 */ 3548 #define MLXSW_REG_PERERP_ID 0x302B 3549 #define MLXSW_REG_PERERP_LEN 0x1C 3550 3551 MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN); 3552 3553 /* reg_pererp_region_id 3554 * Region identifier. 3555 * Range 0..cap_max_regions-1 3556 * Access: Index 3557 */ 3558 MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16); 3559 3560 /* reg_pererp_ctcam_le 3561 * C-TCAM lookup enable. Reserved when erpt_pointer_valid = 0. 3562 * Access: RW 3563 */ 3564 MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1); 3565 3566 /* reg_pererp_erpt_pointer_valid 3567 * erpt_pointer is valid. 3568 * Access: RW 3569 */ 3570 MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1); 3571 3572 /* reg_pererp_erpt_bank_pointer 3573 * Pointer to eRP table bank. May be modified at any time. 3574 * Range 0..cap_max_erp_table_banks-1 3575 * Reserved when erpt_pointer_valid = 0 3576 */ 3577 MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4); 3578 3579 /* reg_pererp_erpt_pointer 3580 * Pointer to eRP table within the eRP bank. Can be changed for an 3581 * existing region. 3582 * Range 0..cap_max_erp_table_size-1 3583 * Reserved when erpt_pointer_valid = 0 3584 * Access: RW 3585 */ 3586 MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8); 3587 3588 /* reg_pererp_erpt_vector 3589 * Vector of allowed eRP indexes starting from erpt_pointer within the 3590 * erpt_bank_pointer. Next entries will be in next bank. 3591 * Note that eRP index is used and not eRP ID. 3592 * Reserved when erpt_pointer_valid = 0 3593 * Access: RW 3594 */ 3595 MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1); 3596 3597 /* reg_pererp_master_rp_id 3598 * Master RP ID. When there are no eRPs, then this provides the eRP ID 3599 * for the lookup. Can be changed for an existing region. 3600 * Reserved when erpt_pointer_valid = 1 3601 * Access: RW 3602 */ 3603 MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4); 3604 3605 static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload, 3606 unsigned long *erp_vector, 3607 unsigned long size) 3608 { 3609 unsigned long bit; 3610 3611 for_each_set_bit(bit, erp_vector, size) 3612 mlxsw_reg_pererp_erpt_vector_set(payload, bit, true); 3613 } 3614 3615 static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id, 3616 bool ctcam_le, bool erpt_pointer_valid, 3617 u8 erpt_bank_pointer, u8 erpt_pointer, 3618 u8 master_rp_id) 3619 { 3620 MLXSW_REG_ZERO(pererp, payload); 3621 mlxsw_reg_pererp_region_id_set(payload, region_id); 3622 mlxsw_reg_pererp_ctcam_le_set(payload, ctcam_le); 3623 mlxsw_reg_pererp_erpt_pointer_valid_set(payload, erpt_pointer_valid); 3624 mlxsw_reg_pererp_erpt_bank_pointer_set(payload, erpt_bank_pointer); 3625 mlxsw_reg_pererp_erpt_pointer_set(payload, erpt_pointer); 3626 mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id); 3627 } 3628 3629 /* PEABFE - Policy-Engine Algorithmic Bloom Filter Entries Register 3630 * ---------------------------------------------------------------- 3631 * This register configures the Bloom filter entries. 3632 */ 3633 #define MLXSW_REG_PEABFE_ID 0x3022 3634 #define MLXSW_REG_PEABFE_BASE_LEN 0x10 3635 #define MLXSW_REG_PEABFE_BF_REC_LEN 0x4 3636 #define MLXSW_REG_PEABFE_BF_REC_MAX_COUNT 256 3637 #define MLXSW_REG_PEABFE_LEN (MLXSW_REG_PEABFE_BASE_LEN + \ 3638 MLXSW_REG_PEABFE_BF_REC_LEN * \ 3639 MLXSW_REG_PEABFE_BF_REC_MAX_COUNT) 3640 3641 MLXSW_REG_DEFINE(peabfe, MLXSW_REG_PEABFE_ID, MLXSW_REG_PEABFE_LEN); 3642 3643 /* reg_peabfe_size 3644 * Number of BF entries to be updated. 3645 * Range 1..256 3646 * Access: Op 3647 */ 3648 MLXSW_ITEM32(reg, peabfe, size, 0x00, 0, 9); 3649 3650 /* reg_peabfe_bf_entry_state 3651 * Bloom filter state 3652 * 0 - Clear 3653 * 1 - Set 3654 * Access: RW 3655 */ 3656 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_state, 3657 MLXSW_REG_PEABFE_BASE_LEN, 31, 1, 3658 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3659 3660 /* reg_peabfe_bf_entry_bank 3661 * Bloom filter bank ID 3662 * Range 0..cap_max_erp_table_banks-1 3663 * Access: Index 3664 */ 3665 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_bank, 3666 MLXSW_REG_PEABFE_BASE_LEN, 24, 4, 3667 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3668 3669 /* reg_peabfe_bf_entry_index 3670 * Bloom filter entry index 3671 * Range 0..2^cap_max_bf_log-1 3672 * Access: Index 3673 */ 3674 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_index, 3675 MLXSW_REG_PEABFE_BASE_LEN, 0, 24, 3676 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3677 3678 static inline void mlxsw_reg_peabfe_pack(char *payload) 3679 { 3680 MLXSW_REG_ZERO(peabfe, payload); 3681 } 3682 3683 static inline void mlxsw_reg_peabfe_rec_pack(char *payload, int rec_index, 3684 u8 state, u8 bank, u32 bf_index) 3685 { 3686 u8 num_rec = mlxsw_reg_peabfe_size_get(payload); 3687 3688 if (rec_index >= num_rec) 3689 mlxsw_reg_peabfe_size_set(payload, rec_index + 1); 3690 mlxsw_reg_peabfe_bf_entry_state_set(payload, rec_index, state); 3691 mlxsw_reg_peabfe_bf_entry_bank_set(payload, rec_index, bank); 3692 mlxsw_reg_peabfe_bf_entry_index_set(payload, rec_index, bf_index); 3693 } 3694 3695 /* IEDR - Infrastructure Entry Delete Register 3696 * ---------------------------------------------------- 3697 * This register is used for deleting entries from the entry tables. 3698 * It is legitimate to attempt to delete a nonexisting entry (the device will 3699 * respond as a good flow). 3700 */ 3701 #define MLXSW_REG_IEDR_ID 0x3804 3702 #define MLXSW_REG_IEDR_BASE_LEN 0x10 /* base length, without records */ 3703 #define MLXSW_REG_IEDR_REC_LEN 0x8 /* record length */ 3704 #define MLXSW_REG_IEDR_REC_MAX_COUNT 64 3705 #define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN + \ 3706 MLXSW_REG_IEDR_REC_LEN * \ 3707 MLXSW_REG_IEDR_REC_MAX_COUNT) 3708 3709 MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN); 3710 3711 /* reg_iedr_num_rec 3712 * Number of records. 3713 * Access: OP 3714 */ 3715 MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8); 3716 3717 /* reg_iedr_rec_type 3718 * Resource type. 3719 * Access: OP 3720 */ 3721 MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8, 3722 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3723 3724 /* reg_iedr_rec_size 3725 * Size of entries do be deleted. The unit is 1 entry, regardless of entry type. 3726 * Access: OP 3727 */ 3728 MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 13, 3729 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3730 3731 /* reg_iedr_rec_index_start 3732 * Resource index start. 3733 * Access: OP 3734 */ 3735 MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24, 3736 MLXSW_REG_IEDR_REC_LEN, 0x04, false); 3737 3738 static inline void mlxsw_reg_iedr_pack(char *payload) 3739 { 3740 MLXSW_REG_ZERO(iedr, payload); 3741 } 3742 3743 static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index, 3744 u8 rec_type, u16 rec_size, 3745 u32 rec_index_start) 3746 { 3747 u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload); 3748 3749 if (rec_index >= num_rec) 3750 mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1); 3751 mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type); 3752 mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size); 3753 mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start); 3754 } 3755 3756 /* QPTS - QoS Priority Trust State Register 3757 * ---------------------------------------- 3758 * This register controls the port policy to calculate the switch priority and 3759 * packet color based on incoming packet fields. 3760 */ 3761 #define MLXSW_REG_QPTS_ID 0x4002 3762 #define MLXSW_REG_QPTS_LEN 0x8 3763 3764 MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN); 3765 3766 /* reg_qpts_local_port 3767 * Local port number. 3768 * Access: Index 3769 * 3770 * Note: CPU port is supported. 3771 */ 3772 MLXSW_ITEM32_LP(reg, qpts, 0x00, 16, 0x00, 12); 3773 3774 enum mlxsw_reg_qpts_trust_state { 3775 MLXSW_REG_QPTS_TRUST_STATE_PCP = 1, 3776 MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2, /* For MPLS, trust EXP. */ 3777 }; 3778 3779 /* reg_qpts_trust_state 3780 * Trust state for a given port. 3781 * Access: RW 3782 */ 3783 MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3); 3784 3785 static inline void mlxsw_reg_qpts_pack(char *payload, u16 local_port, 3786 enum mlxsw_reg_qpts_trust_state ts) 3787 { 3788 MLXSW_REG_ZERO(qpts, payload); 3789 3790 mlxsw_reg_qpts_local_port_set(payload, local_port); 3791 mlxsw_reg_qpts_trust_state_set(payload, ts); 3792 } 3793 3794 /* QPCR - QoS Policer Configuration Register 3795 * ----------------------------------------- 3796 * The QPCR register is used to create policers - that limit 3797 * the rate of bytes or packets via some trap group. 3798 */ 3799 #define MLXSW_REG_QPCR_ID 0x4004 3800 #define MLXSW_REG_QPCR_LEN 0x28 3801 3802 MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN); 3803 3804 enum mlxsw_reg_qpcr_g { 3805 MLXSW_REG_QPCR_G_GLOBAL = 2, 3806 MLXSW_REG_QPCR_G_STORM_CONTROL = 3, 3807 }; 3808 3809 /* reg_qpcr_g 3810 * The policer type. 3811 * Access: Index 3812 */ 3813 MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2); 3814 3815 /* reg_qpcr_pid 3816 * Policer ID. 3817 * Access: Index 3818 */ 3819 MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14); 3820 3821 /* reg_qpcr_clear_counter 3822 * Clear counters. 3823 * Access: OP 3824 */ 3825 MLXSW_ITEM32(reg, qpcr, clear_counter, 0x04, 31, 1); 3826 3827 /* reg_qpcr_color_aware 3828 * Is the policer aware of colors. 3829 * Must be 0 (unaware) for cpu port. 3830 * Access: RW for unbounded policer. RO for bounded policer. 3831 */ 3832 MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1); 3833 3834 /* reg_qpcr_bytes 3835 * Is policer limit is for bytes per sec or packets per sec. 3836 * 0 - packets 3837 * 1 - bytes 3838 * Access: RW for unbounded policer. RO for bounded policer. 3839 */ 3840 MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1); 3841 3842 enum mlxsw_reg_qpcr_ir_units { 3843 MLXSW_REG_QPCR_IR_UNITS_M, 3844 MLXSW_REG_QPCR_IR_UNITS_K, 3845 }; 3846 3847 /* reg_qpcr_ir_units 3848 * Policer's units for cir and eir fields (for bytes limits only) 3849 * 1 - 10^3 3850 * 0 - 10^6 3851 * Access: OP 3852 */ 3853 MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1); 3854 3855 enum mlxsw_reg_qpcr_rate_type { 3856 MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1, 3857 MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2, 3858 }; 3859 3860 /* reg_qpcr_rate_type 3861 * Policer can have one limit (single rate) or 2 limits with specific operation 3862 * for packets that exceed the lower rate but not the upper one. 3863 * (For cpu port must be single rate) 3864 * Access: RW for unbounded policer. RO for bounded policer. 3865 */ 3866 MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2); 3867 3868 /* reg_qpc_cbs 3869 * Policer's committed burst size. 3870 * The policer is working with time slices of 50 nano sec. By default every 3871 * slice is granted the proportionate share of the committed rate. If we want to 3872 * allow a slice to exceed that share (while still keeping the rate per sec) we 3873 * can allow burst. The burst size is between the default proportionate share 3874 * (and no lower than 8) to 32Gb. (Even though giving a number higher than the 3875 * committed rate will result in exceeding the rate). The burst size must be a 3876 * log of 2 and will be determined by 2^cbs. 3877 * Access: RW 3878 */ 3879 MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6); 3880 3881 /* reg_qpcr_cir 3882 * Policer's committed rate. 3883 * The rate used for sungle rate, the lower rate for double rate. 3884 * For bytes limits, the rate will be this value * the unit from ir_units. 3885 * (Resolution error is up to 1%). 3886 * Access: RW 3887 */ 3888 MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32); 3889 3890 /* reg_qpcr_eir 3891 * Policer's exceed rate. 3892 * The higher rate for double rate, reserved for single rate. 3893 * Lower rate for double rate policer. 3894 * For bytes limits, the rate will be this value * the unit from ir_units. 3895 * (Resolution error is up to 1%). 3896 * Access: RW 3897 */ 3898 MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32); 3899 3900 #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2 3901 3902 /* reg_qpcr_exceed_action. 3903 * What to do with packets between the 2 limits for double rate. 3904 * Access: RW for unbounded policer. RO for bounded policer. 3905 */ 3906 MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4); 3907 3908 enum mlxsw_reg_qpcr_action { 3909 /* Discard */ 3910 MLXSW_REG_QPCR_ACTION_DISCARD = 1, 3911 /* Forward and set color to red. 3912 * If the packet is intended to cpu port, it will be dropped. 3913 */ 3914 MLXSW_REG_QPCR_ACTION_FORWARD = 2, 3915 }; 3916 3917 /* reg_qpcr_violate_action 3918 * What to do with packets that cross the cir limit (for single rate) or the eir 3919 * limit (for double rate). 3920 * Access: RW for unbounded policer. RO for bounded policer. 3921 */ 3922 MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4); 3923 3924 /* reg_qpcr_violate_count 3925 * Counts the number of times violate_action happened on this PID. 3926 * Access: RW 3927 */ 3928 MLXSW_ITEM64(reg, qpcr, violate_count, 0x20, 0, 64); 3929 3930 /* Packets */ 3931 #define MLXSW_REG_QPCR_LOWEST_CIR 1 3932 #define MLXSW_REG_QPCR_HIGHEST_CIR (2 * 1000 * 1000 * 1000) /* 2Gpps */ 3933 #define MLXSW_REG_QPCR_LOWEST_CBS 4 3934 #define MLXSW_REG_QPCR_HIGHEST_CBS 24 3935 3936 /* Bandwidth */ 3937 #define MLXSW_REG_QPCR_LOWEST_CIR_BITS 1024 /* bps */ 3938 #define MLXSW_REG_QPCR_HIGHEST_CIR_BITS 2000000000000ULL /* 2Tbps */ 3939 #define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP1 4 3940 #define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP2 4 3941 #define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP1 25 3942 #define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP2 31 3943 3944 static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid, 3945 enum mlxsw_reg_qpcr_ir_units ir_units, 3946 bool bytes, u32 cir, u16 cbs) 3947 { 3948 MLXSW_REG_ZERO(qpcr, payload); 3949 mlxsw_reg_qpcr_pid_set(payload, pid); 3950 mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL); 3951 mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE); 3952 mlxsw_reg_qpcr_violate_action_set(payload, 3953 MLXSW_REG_QPCR_ACTION_DISCARD); 3954 mlxsw_reg_qpcr_cir_set(payload, cir); 3955 mlxsw_reg_qpcr_ir_units_set(payload, ir_units); 3956 mlxsw_reg_qpcr_bytes_set(payload, bytes); 3957 mlxsw_reg_qpcr_cbs_set(payload, cbs); 3958 } 3959 3960 /* QTCT - QoS Switch Traffic Class Table 3961 * ------------------------------------- 3962 * Configures the mapping between the packet switch priority and the 3963 * traffic class on the transmit port. 3964 */ 3965 #define MLXSW_REG_QTCT_ID 0x400A 3966 #define MLXSW_REG_QTCT_LEN 0x08 3967 3968 MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN); 3969 3970 /* reg_qtct_local_port 3971 * Local port number. 3972 * Access: Index 3973 * 3974 * Note: CPU port is not supported. 3975 */ 3976 MLXSW_ITEM32_LP(reg, qtct, 0x00, 16, 0x00, 12); 3977 3978 /* reg_qtct_sub_port 3979 * Virtual port within the physical port. 3980 * Should be set to 0 when virtual ports are not enabled on the port. 3981 * Access: Index 3982 */ 3983 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8); 3984 3985 /* reg_qtct_switch_prio 3986 * Switch priority. 3987 * Access: Index 3988 */ 3989 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4); 3990 3991 /* reg_qtct_tclass 3992 * Traffic class. 3993 * Default values: 3994 * switch_prio 0 : tclass 1 3995 * switch_prio 1 : tclass 0 3996 * switch_prio i : tclass i, for i > 1 3997 * Access: RW 3998 */ 3999 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4); 4000 4001 static inline void mlxsw_reg_qtct_pack(char *payload, u16 local_port, 4002 u8 switch_prio, u8 tclass) 4003 { 4004 MLXSW_REG_ZERO(qtct, payload); 4005 mlxsw_reg_qtct_local_port_set(payload, local_port); 4006 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio); 4007 mlxsw_reg_qtct_tclass_set(payload, tclass); 4008 } 4009 4010 /* QEEC - QoS ETS Element Configuration Register 4011 * --------------------------------------------- 4012 * Configures the ETS elements. 4013 */ 4014 #define MLXSW_REG_QEEC_ID 0x400D 4015 #define MLXSW_REG_QEEC_LEN 0x20 4016 4017 MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN); 4018 4019 /* reg_qeec_local_port 4020 * Local port number. 4021 * Access: Index 4022 * 4023 * Note: CPU port is supported. 4024 */ 4025 MLXSW_ITEM32_LP(reg, qeec, 0x00, 16, 0x00, 12); 4026 4027 enum mlxsw_reg_qeec_hr { 4028 MLXSW_REG_QEEC_HR_PORT, 4029 MLXSW_REG_QEEC_HR_GROUP, 4030 MLXSW_REG_QEEC_HR_SUBGROUP, 4031 MLXSW_REG_QEEC_HR_TC, 4032 }; 4033 4034 /* reg_qeec_element_hierarchy 4035 * 0 - Port 4036 * 1 - Group 4037 * 2 - Subgroup 4038 * 3 - Traffic Class 4039 * Access: Index 4040 */ 4041 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4); 4042 4043 /* reg_qeec_element_index 4044 * The index of the element in the hierarchy. 4045 * Access: Index 4046 */ 4047 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8); 4048 4049 /* reg_qeec_next_element_index 4050 * The index of the next (lower) element in the hierarchy. 4051 * Access: RW 4052 * 4053 * Note: Reserved for element_hierarchy 0. 4054 */ 4055 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8); 4056 4057 /* reg_qeec_mise 4058 * Min shaper configuration enable. Enables configuration of the min 4059 * shaper on this ETS element 4060 * 0 - Disable 4061 * 1 - Enable 4062 * Access: RW 4063 */ 4064 MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1); 4065 4066 /* reg_qeec_ptps 4067 * PTP shaper 4068 * 0: regular shaper mode 4069 * 1: PTP oriented shaper 4070 * Allowed only for hierarchy 0 4071 * Not supported for CPU port 4072 * Note that ptps mode may affect the shaper rates of all hierarchies 4073 * Supported only on Spectrum-1 4074 * Access: RW 4075 */ 4076 MLXSW_ITEM32(reg, qeec, ptps, 0x0C, 29, 1); 4077 4078 enum { 4079 MLXSW_REG_QEEC_BYTES_MODE, 4080 MLXSW_REG_QEEC_PACKETS_MODE, 4081 }; 4082 4083 /* reg_qeec_pb 4084 * Packets or bytes mode. 4085 * 0 - Bytes mode 4086 * 1 - Packets mode 4087 * Access: RW 4088 * 4089 * Note: Used for max shaper configuration. For Spectrum, packets mode 4090 * is supported only for traffic classes of CPU port. 4091 */ 4092 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1); 4093 4094 /* The smallest permitted min shaper rate. */ 4095 #define MLXSW_REG_QEEC_MIS_MIN 200000 /* Kbps */ 4096 4097 /* reg_qeec_min_shaper_rate 4098 * Min shaper information rate. 4099 * For CPU port, can only be configured for port hierarchy. 4100 * When in bytes mode, value is specified in units of 1000bps. 4101 * Access: RW 4102 */ 4103 MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28); 4104 4105 /* reg_qeec_mase 4106 * Max shaper configuration enable. Enables configuration of the max 4107 * shaper on this ETS element. 4108 * 0 - Disable 4109 * 1 - Enable 4110 * Access: RW 4111 */ 4112 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1); 4113 4114 /* The largest max shaper value possible to disable the shaper. */ 4115 #define MLXSW_REG_QEEC_MAS_DIS ((1u << 31) - 1) /* Kbps */ 4116 4117 /* reg_qeec_max_shaper_rate 4118 * Max shaper information rate. 4119 * For CPU port, can only be configured for port hierarchy. 4120 * When in bytes mode, value is specified in units of 1000bps. 4121 * Access: RW 4122 */ 4123 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 31); 4124 4125 /* reg_qeec_de 4126 * DWRR configuration enable. Enables configuration of the dwrr and 4127 * dwrr_weight. 4128 * 0 - Disable 4129 * 1 - Enable 4130 * Access: RW 4131 */ 4132 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1); 4133 4134 /* reg_qeec_dwrr 4135 * Transmission selection algorithm to use on the link going down from 4136 * the ETS element. 4137 * 0 - Strict priority 4138 * 1 - DWRR 4139 * Access: RW 4140 */ 4141 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1); 4142 4143 /* reg_qeec_dwrr_weight 4144 * DWRR weight on the link going down from the ETS element. The 4145 * percentage of bandwidth guaranteed to an ETS element within 4146 * its hierarchy. The sum of all weights across all ETS elements 4147 * within one hierarchy should be equal to 100. Reserved when 4148 * transmission selection algorithm is strict priority. 4149 * Access: RW 4150 */ 4151 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8); 4152 4153 /* reg_qeec_max_shaper_bs 4154 * Max shaper burst size 4155 * Burst size is 2^max_shaper_bs * 512 bits 4156 * For Spectrum-1: Range is: 5..25 4157 * For Spectrum-2: Range is: 11..25 4158 * Reserved when ptps = 1 4159 * Access: RW 4160 */ 4161 MLXSW_ITEM32(reg, qeec, max_shaper_bs, 0x1C, 0, 6); 4162 4163 #define MLXSW_REG_QEEC_HIGHEST_SHAPER_BS 25 4164 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1 5 4165 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2 11 4166 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3 11 4167 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP4 11 4168 4169 static inline void mlxsw_reg_qeec_pack(char *payload, u16 local_port, 4170 enum mlxsw_reg_qeec_hr hr, u8 index, 4171 u8 next_index) 4172 { 4173 MLXSW_REG_ZERO(qeec, payload); 4174 mlxsw_reg_qeec_local_port_set(payload, local_port); 4175 mlxsw_reg_qeec_element_hierarchy_set(payload, hr); 4176 mlxsw_reg_qeec_element_index_set(payload, index); 4177 mlxsw_reg_qeec_next_element_index_set(payload, next_index); 4178 } 4179 4180 static inline void mlxsw_reg_qeec_ptps_pack(char *payload, u16 local_port, 4181 bool ptps) 4182 { 4183 MLXSW_REG_ZERO(qeec, payload); 4184 mlxsw_reg_qeec_local_port_set(payload, local_port); 4185 mlxsw_reg_qeec_element_hierarchy_set(payload, MLXSW_REG_QEEC_HR_PORT); 4186 mlxsw_reg_qeec_ptps_set(payload, ptps); 4187 } 4188 4189 /* QRWE - QoS ReWrite Enable 4190 * ------------------------- 4191 * This register configures the rewrite enable per receive port. 4192 */ 4193 #define MLXSW_REG_QRWE_ID 0x400F 4194 #define MLXSW_REG_QRWE_LEN 0x08 4195 4196 MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN); 4197 4198 /* reg_qrwe_local_port 4199 * Local port number. 4200 * Access: Index 4201 * 4202 * Note: CPU port is supported. No support for router port. 4203 */ 4204 MLXSW_ITEM32_LP(reg, qrwe, 0x00, 16, 0x00, 12); 4205 4206 /* reg_qrwe_dscp 4207 * Whether to enable DSCP rewrite (default is 0, don't rewrite). 4208 * Access: RW 4209 */ 4210 MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1); 4211 4212 /* reg_qrwe_pcp 4213 * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite). 4214 * Access: RW 4215 */ 4216 MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1); 4217 4218 static inline void mlxsw_reg_qrwe_pack(char *payload, u16 local_port, 4219 bool rewrite_pcp, bool rewrite_dscp) 4220 { 4221 MLXSW_REG_ZERO(qrwe, payload); 4222 mlxsw_reg_qrwe_local_port_set(payload, local_port); 4223 mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp); 4224 mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp); 4225 } 4226 4227 /* QPDSM - QoS Priority to DSCP Mapping 4228 * ------------------------------------ 4229 * QoS Priority to DSCP Mapping Register 4230 */ 4231 #define MLXSW_REG_QPDSM_ID 0x4011 4232 #define MLXSW_REG_QPDSM_BASE_LEN 0x04 /* base length, without records */ 4233 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4 /* record length */ 4234 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 16 4235 #define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN + \ 4236 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN * \ 4237 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT) 4238 4239 MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN); 4240 4241 /* reg_qpdsm_local_port 4242 * Local Port. Supported for data packets from CPU port. 4243 * Access: Index 4244 */ 4245 MLXSW_ITEM32_LP(reg, qpdsm, 0x00, 16, 0x00, 12); 4246 4247 /* reg_qpdsm_prio_entry_color0_e 4248 * Enable update of the entry for color 0 and a given port. 4249 * Access: WO 4250 */ 4251 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e, 4252 MLXSW_REG_QPDSM_BASE_LEN, 31, 1, 4253 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4254 4255 /* reg_qpdsm_prio_entry_color0_dscp 4256 * DSCP field in the outer label of the packet for color 0 and a given port. 4257 * Reserved when e=0. 4258 * Access: RW 4259 */ 4260 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp, 4261 MLXSW_REG_QPDSM_BASE_LEN, 24, 6, 4262 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4263 4264 /* reg_qpdsm_prio_entry_color1_e 4265 * Enable update of the entry for color 1 and a given port. 4266 * Access: WO 4267 */ 4268 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e, 4269 MLXSW_REG_QPDSM_BASE_LEN, 23, 1, 4270 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4271 4272 /* reg_qpdsm_prio_entry_color1_dscp 4273 * DSCP field in the outer label of the packet for color 1 and a given port. 4274 * Reserved when e=0. 4275 * Access: RW 4276 */ 4277 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp, 4278 MLXSW_REG_QPDSM_BASE_LEN, 16, 6, 4279 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4280 4281 /* reg_qpdsm_prio_entry_color2_e 4282 * Enable update of the entry for color 2 and a given port. 4283 * Access: WO 4284 */ 4285 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e, 4286 MLXSW_REG_QPDSM_BASE_LEN, 15, 1, 4287 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4288 4289 /* reg_qpdsm_prio_entry_color2_dscp 4290 * DSCP field in the outer label of the packet for color 2 and a given port. 4291 * Reserved when e=0. 4292 * Access: RW 4293 */ 4294 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp, 4295 MLXSW_REG_QPDSM_BASE_LEN, 8, 6, 4296 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4297 4298 static inline void mlxsw_reg_qpdsm_pack(char *payload, u16 local_port) 4299 { 4300 MLXSW_REG_ZERO(qpdsm, payload); 4301 mlxsw_reg_qpdsm_local_port_set(payload, local_port); 4302 } 4303 4304 static inline void 4305 mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp) 4306 { 4307 mlxsw_reg_qpdsm_prio_entry_color0_e_set(payload, prio, 1); 4308 mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(payload, prio, dscp); 4309 mlxsw_reg_qpdsm_prio_entry_color1_e_set(payload, prio, 1); 4310 mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(payload, prio, dscp); 4311 mlxsw_reg_qpdsm_prio_entry_color2_e_set(payload, prio, 1); 4312 mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp); 4313 } 4314 4315 /* QPDP - QoS Port DSCP to Priority Mapping Register 4316 * ------------------------------------------------- 4317 * This register controls the port default Switch Priority and Color. The 4318 * default Switch Priority and Color are used for frames where the trust state 4319 * uses default values. All member ports of a LAG should be configured with the 4320 * same default values. 4321 */ 4322 #define MLXSW_REG_QPDP_ID 0x4007 4323 #define MLXSW_REG_QPDP_LEN 0x8 4324 4325 MLXSW_REG_DEFINE(qpdp, MLXSW_REG_QPDP_ID, MLXSW_REG_QPDP_LEN); 4326 4327 /* reg_qpdp_local_port 4328 * Local Port. Supported for data packets from CPU port. 4329 * Access: Index 4330 */ 4331 MLXSW_ITEM32_LP(reg, qpdp, 0x00, 16, 0x00, 12); 4332 4333 /* reg_qpdp_switch_prio 4334 * Default port Switch Priority (default 0) 4335 * Access: RW 4336 */ 4337 MLXSW_ITEM32(reg, qpdp, switch_prio, 0x04, 0, 4); 4338 4339 static inline void mlxsw_reg_qpdp_pack(char *payload, u16 local_port, 4340 u8 switch_prio) 4341 { 4342 MLXSW_REG_ZERO(qpdp, payload); 4343 mlxsw_reg_qpdp_local_port_set(payload, local_port); 4344 mlxsw_reg_qpdp_switch_prio_set(payload, switch_prio); 4345 } 4346 4347 /* QPDPM - QoS Port DSCP to Priority Mapping Register 4348 * -------------------------------------------------- 4349 * This register controls the mapping from DSCP field to 4350 * Switch Priority for IP packets. 4351 */ 4352 #define MLXSW_REG_QPDPM_ID 0x4013 4353 #define MLXSW_REG_QPDPM_BASE_LEN 0x4 /* base length, without records */ 4354 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2 /* record length */ 4355 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64 4356 #define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN + \ 4357 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN * \ 4358 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT) 4359 4360 MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN); 4361 4362 /* reg_qpdpm_local_port 4363 * Local Port. Supported for data packets from CPU port. 4364 * Access: Index 4365 */ 4366 MLXSW_ITEM32_LP(reg, qpdpm, 0x00, 16, 0x00, 12); 4367 4368 /* reg_qpdpm_dscp_e 4369 * Enable update of the specific entry. When cleared, the switch_prio and color 4370 * fields are ignored and the previous switch_prio and color values are 4371 * preserved. 4372 * Access: WO 4373 */ 4374 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1, 4375 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 4376 4377 /* reg_qpdpm_dscp_prio 4378 * The new Switch Priority value for the relevant DSCP value. 4379 * Access: RW 4380 */ 4381 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio, 4382 MLXSW_REG_QPDPM_BASE_LEN, 0, 4, 4383 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 4384 4385 static inline void mlxsw_reg_qpdpm_pack(char *payload, u16 local_port) 4386 { 4387 MLXSW_REG_ZERO(qpdpm, payload); 4388 mlxsw_reg_qpdpm_local_port_set(payload, local_port); 4389 } 4390 4391 static inline void 4392 mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio) 4393 { 4394 mlxsw_reg_qpdpm_dscp_entry_e_set(payload, dscp, 1); 4395 mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio); 4396 } 4397 4398 /* QTCTM - QoS Switch Traffic Class Table is Multicast-Aware Register 4399 * ------------------------------------------------------------------ 4400 * This register configures if the Switch Priority to Traffic Class mapping is 4401 * based on Multicast packet indication. If so, then multicast packets will get 4402 * a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by 4403 * QTCT. 4404 * By default, Switch Priority to Traffic Class mapping is not based on 4405 * Multicast packet indication. 4406 */ 4407 #define MLXSW_REG_QTCTM_ID 0x401A 4408 #define MLXSW_REG_QTCTM_LEN 0x08 4409 4410 MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN); 4411 4412 /* reg_qtctm_local_port 4413 * Local port number. 4414 * No support for CPU port. 4415 * Access: Index 4416 */ 4417 MLXSW_ITEM32_LP(reg, qtctm, 0x00, 16, 0x00, 12); 4418 4419 /* reg_qtctm_mc 4420 * Multicast Mode 4421 * Whether Switch Priority to Traffic Class mapping is based on Multicast packet 4422 * indication (default is 0, not based on Multicast packet indication). 4423 */ 4424 MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1); 4425 4426 static inline void 4427 mlxsw_reg_qtctm_pack(char *payload, u16 local_port, bool mc) 4428 { 4429 MLXSW_REG_ZERO(qtctm, payload); 4430 mlxsw_reg_qtctm_local_port_set(payload, local_port); 4431 mlxsw_reg_qtctm_mc_set(payload, mc); 4432 } 4433 4434 /* QPSC - QoS PTP Shaper Configuration Register 4435 * -------------------------------------------- 4436 * The QPSC allows advanced configuration of the shapers when QEEC.ptps=1. 4437 * Supported only on Spectrum-1. 4438 */ 4439 #define MLXSW_REG_QPSC_ID 0x401B 4440 #define MLXSW_REG_QPSC_LEN 0x28 4441 4442 MLXSW_REG_DEFINE(qpsc, MLXSW_REG_QPSC_ID, MLXSW_REG_QPSC_LEN); 4443 4444 enum mlxsw_reg_qpsc_port_speed { 4445 MLXSW_REG_QPSC_PORT_SPEED_100M, 4446 MLXSW_REG_QPSC_PORT_SPEED_1G, 4447 MLXSW_REG_QPSC_PORT_SPEED_10G, 4448 MLXSW_REG_QPSC_PORT_SPEED_25G, 4449 }; 4450 4451 /* reg_qpsc_port_speed 4452 * Port speed. 4453 * Access: Index 4454 */ 4455 MLXSW_ITEM32(reg, qpsc, port_speed, 0x00, 0, 4); 4456 4457 /* reg_qpsc_shaper_time_exp 4458 * The base-time-interval for updating the shapers tokens (for all hierarchies). 4459 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec 4460 * shaper_rate = 64bit * shaper_inc / shaper_update_rate 4461 * Access: RW 4462 */ 4463 MLXSW_ITEM32(reg, qpsc, shaper_time_exp, 0x04, 16, 4); 4464 4465 /* reg_qpsc_shaper_time_mantissa 4466 * The base-time-interval for updating the shapers tokens (for all hierarchies). 4467 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec 4468 * shaper_rate = 64bit * shaper_inc / shaper_update_rate 4469 * Access: RW 4470 */ 4471 MLXSW_ITEM32(reg, qpsc, shaper_time_mantissa, 0x04, 0, 5); 4472 4473 /* reg_qpsc_shaper_inc 4474 * Number of tokens added to shaper on each update. 4475 * Units of 8B. 4476 * Access: RW 4477 */ 4478 MLXSW_ITEM32(reg, qpsc, shaper_inc, 0x08, 0, 5); 4479 4480 /* reg_qpsc_shaper_bs 4481 * Max shaper Burst size. 4482 * Burst size is 2 ^ max_shaper_bs * 512 [bits] 4483 * Range is: 5..25 (from 2KB..2GB) 4484 * Access: RW 4485 */ 4486 MLXSW_ITEM32(reg, qpsc, shaper_bs, 0x0C, 0, 6); 4487 4488 /* reg_qpsc_ptsc_we 4489 * Write enable to port_to_shaper_credits. 4490 * Access: WO 4491 */ 4492 MLXSW_ITEM32(reg, qpsc, ptsc_we, 0x10, 31, 1); 4493 4494 /* reg_qpsc_port_to_shaper_credits 4495 * For split ports: range 1..57 4496 * For non-split ports: range 1..112 4497 * Written only when ptsc_we is set. 4498 * Access: RW 4499 */ 4500 MLXSW_ITEM32(reg, qpsc, port_to_shaper_credits, 0x10, 0, 8); 4501 4502 /* reg_qpsc_ing_timestamp_inc 4503 * Ingress timestamp increment. 4504 * 2's complement. 4505 * The timestamp of MTPPTR at ingress will be incremented by this value. Global 4506 * value for all ports. 4507 * Same units as used by MTPPTR. 4508 * Access: RW 4509 */ 4510 MLXSW_ITEM32(reg, qpsc, ing_timestamp_inc, 0x20, 0, 32); 4511 4512 /* reg_qpsc_egr_timestamp_inc 4513 * Egress timestamp increment. 4514 * 2's complement. 4515 * The timestamp of MTPPTR at egress will be incremented by this value. Global 4516 * value for all ports. 4517 * Same units as used by MTPPTR. 4518 * Access: RW 4519 */ 4520 MLXSW_ITEM32(reg, qpsc, egr_timestamp_inc, 0x24, 0, 32); 4521 4522 static inline void 4523 mlxsw_reg_qpsc_pack(char *payload, enum mlxsw_reg_qpsc_port_speed port_speed, 4524 u8 shaper_time_exp, u8 shaper_time_mantissa, u8 shaper_inc, 4525 u8 shaper_bs, u8 port_to_shaper_credits, 4526 int ing_timestamp_inc, int egr_timestamp_inc) 4527 { 4528 MLXSW_REG_ZERO(qpsc, payload); 4529 mlxsw_reg_qpsc_port_speed_set(payload, port_speed); 4530 mlxsw_reg_qpsc_shaper_time_exp_set(payload, shaper_time_exp); 4531 mlxsw_reg_qpsc_shaper_time_mantissa_set(payload, shaper_time_mantissa); 4532 mlxsw_reg_qpsc_shaper_inc_set(payload, shaper_inc); 4533 mlxsw_reg_qpsc_shaper_bs_set(payload, shaper_bs); 4534 mlxsw_reg_qpsc_ptsc_we_set(payload, true); 4535 mlxsw_reg_qpsc_port_to_shaper_credits_set(payload, port_to_shaper_credits); 4536 mlxsw_reg_qpsc_ing_timestamp_inc_set(payload, ing_timestamp_inc); 4537 mlxsw_reg_qpsc_egr_timestamp_inc_set(payload, egr_timestamp_inc); 4538 } 4539 4540 /* PMLP - Ports Module to Local Port Register 4541 * ------------------------------------------ 4542 * Configures the assignment of modules to local ports. 4543 */ 4544 #define MLXSW_REG_PMLP_ID 0x5002 4545 #define MLXSW_REG_PMLP_LEN 0x40 4546 4547 MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN); 4548 4549 /* reg_pmlp_rxtx 4550 * 0 - Tx value is used for both Tx and Rx. 4551 * 1 - Rx value is taken from a separte field. 4552 * Access: RW 4553 */ 4554 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1); 4555 4556 /* reg_pmlp_local_port 4557 * Local port number. 4558 * Access: Index 4559 */ 4560 MLXSW_ITEM32_LP(reg, pmlp, 0x00, 16, 0x00, 12); 4561 4562 /* reg_pmlp_width 4563 * 0 - Unmap local port. 4564 * 1 - Lane 0 is used. 4565 * 2 - Lanes 0 and 1 are used. 4566 * 4 - Lanes 0, 1, 2 and 3 are used. 4567 * 8 - Lanes 0-7 are used. 4568 * Access: RW 4569 */ 4570 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8); 4571 4572 /* reg_pmlp_module 4573 * Module number. 4574 * Access: RW 4575 */ 4576 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false); 4577 4578 /* reg_pmlp_slot_index 4579 * Module number. 4580 * Slot_index 4581 * Slot_index = 0 represent the onboard (motherboard). 4582 * In case of non-modular system only slot_index = 0 is available. 4583 * Access: RW 4584 */ 4585 MLXSW_ITEM32_INDEXED(reg, pmlp, slot_index, 0x04, 8, 4, 0x04, 0x00, false); 4586 4587 /* reg_pmlp_tx_lane 4588 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well. 4589 * Access: RW 4590 */ 4591 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 4, 0x04, 0x00, false); 4592 4593 /* reg_pmlp_rx_lane 4594 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is 4595 * equal to Tx lane. 4596 * Access: RW 4597 */ 4598 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 4, 0x04, 0x00, false); 4599 4600 static inline void mlxsw_reg_pmlp_pack(char *payload, u16 local_port) 4601 { 4602 MLXSW_REG_ZERO(pmlp, payload); 4603 mlxsw_reg_pmlp_local_port_set(payload, local_port); 4604 } 4605 4606 /* PMTU - Port MTU Register 4607 * ------------------------ 4608 * Configures and reports the port MTU. 4609 */ 4610 #define MLXSW_REG_PMTU_ID 0x5003 4611 #define MLXSW_REG_PMTU_LEN 0x10 4612 4613 MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN); 4614 4615 /* reg_pmtu_local_port 4616 * Local port number. 4617 * Access: Index 4618 */ 4619 MLXSW_ITEM32_LP(reg, pmtu, 0x00, 16, 0x00, 12); 4620 4621 /* reg_pmtu_max_mtu 4622 * Maximum MTU. 4623 * When port type (e.g. Ethernet) is configured, the relevant MTU is 4624 * reported, otherwise the minimum between the max_mtu of the different 4625 * types is reported. 4626 * Access: RO 4627 */ 4628 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16); 4629 4630 /* reg_pmtu_admin_mtu 4631 * MTU value to set port to. Must be smaller or equal to max_mtu. 4632 * Note: If port type is Infiniband, then port must be disabled, when its 4633 * MTU is set. 4634 * Access: RW 4635 */ 4636 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16); 4637 4638 /* reg_pmtu_oper_mtu 4639 * The actual MTU configured on the port. Packets exceeding this size 4640 * will be dropped. 4641 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband 4642 * oper_mtu might be smaller than admin_mtu. 4643 * Access: RO 4644 */ 4645 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16); 4646 4647 static inline void mlxsw_reg_pmtu_pack(char *payload, u16 local_port, 4648 u16 new_mtu) 4649 { 4650 MLXSW_REG_ZERO(pmtu, payload); 4651 mlxsw_reg_pmtu_local_port_set(payload, local_port); 4652 mlxsw_reg_pmtu_max_mtu_set(payload, 0); 4653 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu); 4654 mlxsw_reg_pmtu_oper_mtu_set(payload, 0); 4655 } 4656 4657 /* PTYS - Port Type and Speed Register 4658 * ----------------------------------- 4659 * Configures and reports the port speed type. 4660 * 4661 * Note: When set while the link is up, the changes will not take effect 4662 * until the port transitions from down to up state. 4663 */ 4664 #define MLXSW_REG_PTYS_ID 0x5004 4665 #define MLXSW_REG_PTYS_LEN 0x40 4666 4667 MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN); 4668 4669 /* an_disable_admin 4670 * Auto negotiation disable administrative configuration 4671 * 0 - Device doesn't support AN disable. 4672 * 1 - Device supports AN disable. 4673 * Access: RW 4674 */ 4675 MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1); 4676 4677 /* reg_ptys_local_port 4678 * Local port number. 4679 * Access: Index 4680 */ 4681 MLXSW_ITEM32_LP(reg, ptys, 0x00, 16, 0x00, 12); 4682 4683 #define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0) 4684 #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2) 4685 4686 /* reg_ptys_proto_mask 4687 * Protocol mask. Indicates which protocol is used. 4688 * 0 - Infiniband. 4689 * 1 - Fibre Channel. 4690 * 2 - Ethernet. 4691 * Access: Index 4692 */ 4693 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3); 4694 4695 enum { 4696 MLXSW_REG_PTYS_AN_STATUS_NA, 4697 MLXSW_REG_PTYS_AN_STATUS_OK, 4698 MLXSW_REG_PTYS_AN_STATUS_FAIL, 4699 }; 4700 4701 /* reg_ptys_an_status 4702 * Autonegotiation status. 4703 * Access: RO 4704 */ 4705 MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4); 4706 4707 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M BIT(0) 4708 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII BIT(1) 4709 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R BIT(3) 4710 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G BIT(4) 4711 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G BIT(5) 4712 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR BIT(6) 4713 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 BIT(7) 4714 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR BIT(8) 4715 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4 BIT(9) 4716 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2 BIT(10) 4717 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4 BIT(12) 4718 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_8 BIT(15) 4719 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_800GAUI_8 BIT(19) 4720 4721 /* reg_ptys_ext_eth_proto_cap 4722 * Extended Ethernet port supported speeds and protocols. 4723 * Access: RO 4724 */ 4725 MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32); 4726 4727 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0) 4728 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1) 4729 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2) 4730 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3) 4731 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4) 4732 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6) 4733 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7) 4734 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12) 4735 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13) 4736 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14) 4737 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15) 4738 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16) 4739 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18) 4740 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19) 4741 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20) 4742 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21) 4743 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22) 4744 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23) 4745 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(24) 4746 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_T BIT(25) 4747 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27) 4748 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28) 4749 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29) 4750 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30) 4751 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31) 4752 4753 /* reg_ptys_eth_proto_cap 4754 * Ethernet port supported speeds and protocols. 4755 * Access: RO 4756 */ 4757 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32); 4758 4759 /* reg_ptys_ext_eth_proto_admin 4760 * Extended speed and protocol to set port to. 4761 * Access: RW 4762 */ 4763 MLXSW_ITEM32(reg, ptys, ext_eth_proto_admin, 0x14, 0, 32); 4764 4765 /* reg_ptys_eth_proto_admin 4766 * Speed and protocol to set port to. 4767 * Access: RW 4768 */ 4769 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32); 4770 4771 /* reg_ptys_ext_eth_proto_oper 4772 * The extended current speed and protocol configured for the port. 4773 * Access: RO 4774 */ 4775 MLXSW_ITEM32(reg, ptys, ext_eth_proto_oper, 0x20, 0, 32); 4776 4777 /* reg_ptys_eth_proto_oper 4778 * The current speed and protocol configured for the port. 4779 * Access: RO 4780 */ 4781 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32); 4782 4783 enum mlxsw_reg_ptys_connector_type { 4784 MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR, 4785 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE, 4786 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP, 4787 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI, 4788 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC, 4789 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII, 4790 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE, 4791 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA, 4792 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER, 4793 }; 4794 4795 /* reg_ptys_connector_type 4796 * Connector type indication. 4797 * Access: RO 4798 */ 4799 MLXSW_ITEM32(reg, ptys, connector_type, 0x2C, 0, 4); 4800 4801 static inline void mlxsw_reg_ptys_eth_pack(char *payload, u16 local_port, 4802 u32 proto_admin, bool autoneg) 4803 { 4804 MLXSW_REG_ZERO(ptys, payload); 4805 mlxsw_reg_ptys_local_port_set(payload, local_port); 4806 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4807 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin); 4808 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4809 } 4810 4811 static inline void mlxsw_reg_ptys_ext_eth_pack(char *payload, u16 local_port, 4812 u32 proto_admin, bool autoneg) 4813 { 4814 MLXSW_REG_ZERO(ptys, payload); 4815 mlxsw_reg_ptys_local_port_set(payload, local_port); 4816 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4817 mlxsw_reg_ptys_ext_eth_proto_admin_set(payload, proto_admin); 4818 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4819 } 4820 4821 static inline void mlxsw_reg_ptys_eth_unpack(char *payload, 4822 u32 *p_eth_proto_cap, 4823 u32 *p_eth_proto_admin, 4824 u32 *p_eth_proto_oper) 4825 { 4826 if (p_eth_proto_cap) 4827 *p_eth_proto_cap = 4828 mlxsw_reg_ptys_eth_proto_cap_get(payload); 4829 if (p_eth_proto_admin) 4830 *p_eth_proto_admin = 4831 mlxsw_reg_ptys_eth_proto_admin_get(payload); 4832 if (p_eth_proto_oper) 4833 *p_eth_proto_oper = 4834 mlxsw_reg_ptys_eth_proto_oper_get(payload); 4835 } 4836 4837 static inline void mlxsw_reg_ptys_ext_eth_unpack(char *payload, 4838 u32 *p_eth_proto_cap, 4839 u32 *p_eth_proto_admin, 4840 u32 *p_eth_proto_oper) 4841 { 4842 if (p_eth_proto_cap) 4843 *p_eth_proto_cap = 4844 mlxsw_reg_ptys_ext_eth_proto_cap_get(payload); 4845 if (p_eth_proto_admin) 4846 *p_eth_proto_admin = 4847 mlxsw_reg_ptys_ext_eth_proto_admin_get(payload); 4848 if (p_eth_proto_oper) 4849 *p_eth_proto_oper = 4850 mlxsw_reg_ptys_ext_eth_proto_oper_get(payload); 4851 } 4852 4853 /* PPAD - Port Physical Address Register 4854 * ------------------------------------- 4855 * The PPAD register configures the per port physical MAC address. 4856 */ 4857 #define MLXSW_REG_PPAD_ID 0x5005 4858 #define MLXSW_REG_PPAD_LEN 0x10 4859 4860 MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN); 4861 4862 /* reg_ppad_single_base_mac 4863 * 0: base_mac, local port should be 0 and mac[7:0] is 4864 * reserved. HW will set incremental 4865 * 1: single_mac - mac of the local_port 4866 * Access: RW 4867 */ 4868 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1); 4869 4870 /* reg_ppad_local_port 4871 * port number, if single_base_mac = 0 then local_port is reserved 4872 * Access: RW 4873 */ 4874 MLXSW_ITEM32_LP(reg, ppad, 0x00, 16, 0x00, 24); 4875 4876 /* reg_ppad_mac 4877 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved. 4878 * If single_base_mac = 1 - the per port MAC address 4879 * Access: RW 4880 */ 4881 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6); 4882 4883 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac, 4884 u16 local_port) 4885 { 4886 MLXSW_REG_ZERO(ppad, payload); 4887 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac); 4888 mlxsw_reg_ppad_local_port_set(payload, local_port); 4889 } 4890 4891 /* PAOS - Ports Administrative and Operational Status Register 4892 * ----------------------------------------------------------- 4893 * Configures and retrieves per port administrative and operational status. 4894 */ 4895 #define MLXSW_REG_PAOS_ID 0x5006 4896 #define MLXSW_REG_PAOS_LEN 0x10 4897 4898 MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN); 4899 4900 /* reg_paos_swid 4901 * Switch partition ID with which to associate the port. 4902 * Note: while external ports uses unique local port numbers (and thus swid is 4903 * redundant), router ports use the same local port number where swid is the 4904 * only indication for the relevant port. 4905 * Access: Index 4906 */ 4907 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8); 4908 4909 /* reg_paos_local_port 4910 * Local port number. 4911 * Access: Index 4912 */ 4913 MLXSW_ITEM32_LP(reg, paos, 0x00, 16, 0x00, 12); 4914 4915 /* reg_paos_admin_status 4916 * Port administrative state (the desired state of the port): 4917 * 1 - Up. 4918 * 2 - Down. 4919 * 3 - Up once. This means that in case of link failure, the port won't go 4920 * into polling mode, but will wait to be re-enabled by software. 4921 * 4 - Disabled by system. Can only be set by hardware. 4922 * Access: RW 4923 */ 4924 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4); 4925 4926 /* reg_paos_oper_status 4927 * Port operational state (the current state): 4928 * 1 - Up. 4929 * 2 - Down. 4930 * 3 - Down by port failure. This means that the device will not let the 4931 * port up again until explicitly specified by software. 4932 * Access: RO 4933 */ 4934 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4); 4935 4936 /* reg_paos_ase 4937 * Admin state update enabled. 4938 * Access: WO 4939 */ 4940 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1); 4941 4942 /* reg_paos_ee 4943 * Event update enable. If this bit is set, event generation will be 4944 * updated based on the e field. 4945 * Access: WO 4946 */ 4947 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1); 4948 4949 /* reg_paos_e 4950 * Event generation on operational state change: 4951 * 0 - Do not generate event. 4952 * 1 - Generate Event. 4953 * 2 - Generate Single Event. 4954 * Access: RW 4955 */ 4956 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2); 4957 4958 static inline void mlxsw_reg_paos_pack(char *payload, u16 local_port, 4959 enum mlxsw_port_admin_status status) 4960 { 4961 MLXSW_REG_ZERO(paos, payload); 4962 mlxsw_reg_paos_swid_set(payload, 0); 4963 mlxsw_reg_paos_local_port_set(payload, local_port); 4964 mlxsw_reg_paos_admin_status_set(payload, status); 4965 mlxsw_reg_paos_oper_status_set(payload, 0); 4966 mlxsw_reg_paos_ase_set(payload, 1); 4967 mlxsw_reg_paos_ee_set(payload, 1); 4968 mlxsw_reg_paos_e_set(payload, 1); 4969 } 4970 4971 /* PFCC - Ports Flow Control Configuration Register 4972 * ------------------------------------------------ 4973 * Configures and retrieves the per port flow control configuration. 4974 */ 4975 #define MLXSW_REG_PFCC_ID 0x5007 4976 #define MLXSW_REG_PFCC_LEN 0x20 4977 4978 MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN); 4979 4980 /* reg_pfcc_local_port 4981 * Local port number. 4982 * Access: Index 4983 */ 4984 MLXSW_ITEM32_LP(reg, pfcc, 0x00, 16, 0x00, 12); 4985 4986 /* reg_pfcc_pnat 4987 * Port number access type. Determines the way local_port is interpreted: 4988 * 0 - Local port number. 4989 * 1 - IB / label port number. 4990 * Access: Index 4991 */ 4992 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2); 4993 4994 /* reg_pfcc_shl_cap 4995 * Send to higher layers capabilities: 4996 * 0 - No capability of sending Pause and PFC frames to higher layers. 4997 * 1 - Device has capability of sending Pause and PFC frames to higher 4998 * layers. 4999 * Access: RO 5000 */ 5001 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1); 5002 5003 /* reg_pfcc_shl_opr 5004 * Send to higher layers operation: 5005 * 0 - Pause and PFC frames are handled by the port (default). 5006 * 1 - Pause and PFC frames are handled by the port and also sent to 5007 * higher layers. Only valid if shl_cap = 1. 5008 * Access: RW 5009 */ 5010 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1); 5011 5012 /* reg_pfcc_ppan 5013 * Pause policy auto negotiation. 5014 * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx. 5015 * 1 - Enabled. When auto-negotiation is performed, set the Pause policy 5016 * based on the auto-negotiation resolution. 5017 * Access: RW 5018 * 5019 * Note: The auto-negotiation advertisement is set according to pptx and 5020 * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0. 5021 */ 5022 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4); 5023 5024 /* reg_pfcc_prio_mask_tx 5025 * Bit per priority indicating if Tx flow control policy should be 5026 * updated based on bit pfctx. 5027 * Access: WO 5028 */ 5029 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8); 5030 5031 /* reg_pfcc_prio_mask_rx 5032 * Bit per priority indicating if Rx flow control policy should be 5033 * updated based on bit pfcrx. 5034 * Access: WO 5035 */ 5036 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8); 5037 5038 /* reg_pfcc_pptx 5039 * Admin Pause policy on Tx. 5040 * 0 - Never generate Pause frames (default). 5041 * 1 - Generate Pause frames according to Rx buffer threshold. 5042 * Access: RW 5043 */ 5044 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1); 5045 5046 /* reg_pfcc_aptx 5047 * Active (operational) Pause policy on Tx. 5048 * 0 - Never generate Pause frames. 5049 * 1 - Generate Pause frames according to Rx buffer threshold. 5050 * Access: RO 5051 */ 5052 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1); 5053 5054 /* reg_pfcc_pfctx 5055 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask: 5056 * 0 - Never generate priority Pause frames on the specified priority 5057 * (default). 5058 * 1 - Generate priority Pause frames according to Rx buffer threshold on 5059 * the specified priority. 5060 * Access: RW 5061 * 5062 * Note: pfctx and pptx must be mutually exclusive. 5063 */ 5064 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8); 5065 5066 /* reg_pfcc_pprx 5067 * Admin Pause policy on Rx. 5068 * 0 - Ignore received Pause frames (default). 5069 * 1 - Respect received Pause frames. 5070 * Access: RW 5071 */ 5072 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1); 5073 5074 /* reg_pfcc_aprx 5075 * Active (operational) Pause policy on Rx. 5076 * 0 - Ignore received Pause frames. 5077 * 1 - Respect received Pause frames. 5078 * Access: RO 5079 */ 5080 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1); 5081 5082 /* reg_pfcc_pfcrx 5083 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask: 5084 * 0 - Ignore incoming priority Pause frames on the specified priority 5085 * (default). 5086 * 1 - Respect incoming priority Pause frames on the specified priority. 5087 * Access: RW 5088 */ 5089 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8); 5090 5091 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF 5092 5093 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en) 5094 { 5095 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 5096 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 5097 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en); 5098 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en); 5099 } 5100 5101 static inline void mlxsw_reg_pfcc_pack(char *payload, u16 local_port) 5102 { 5103 MLXSW_REG_ZERO(pfcc, payload); 5104 mlxsw_reg_pfcc_local_port_set(payload, local_port); 5105 } 5106 5107 /* PPCNT - Ports Performance Counters Register 5108 * ------------------------------------------- 5109 * The PPCNT register retrieves per port performance counters. 5110 */ 5111 #define MLXSW_REG_PPCNT_ID 0x5008 5112 #define MLXSW_REG_PPCNT_LEN 0x100 5113 #define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08 5114 5115 MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN); 5116 5117 /* reg_ppcnt_swid 5118 * For HCA: must be always 0. 5119 * Switch partition ID to associate port with. 5120 * Switch partitions are numbered from 0 to 7 inclusively. 5121 * Switch partition 254 indicates stacking ports. 5122 * Switch partition 255 indicates all switch partitions. 5123 * Only valid on Set() operation with local_port=255. 5124 * Access: Index 5125 */ 5126 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8); 5127 5128 /* reg_ppcnt_local_port 5129 * Local port number. 5130 * Access: Index 5131 */ 5132 MLXSW_ITEM32_LP(reg, ppcnt, 0x00, 16, 0x00, 12); 5133 5134 /* reg_ppcnt_pnat 5135 * Port number access type: 5136 * 0 - Local port number 5137 * 1 - IB port number 5138 * Access: Index 5139 */ 5140 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2); 5141 5142 enum mlxsw_reg_ppcnt_grp { 5143 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0, 5144 MLXSW_REG_PPCNT_RFC_2863_CNT = 0x1, 5145 MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2, 5146 MLXSW_REG_PPCNT_RFC_3635_CNT = 0x3, 5147 MLXSW_REG_PPCNT_EXT_CNT = 0x5, 5148 MLXSW_REG_PPCNT_DISCARD_CNT = 0x6, 5149 MLXSW_REG_PPCNT_PRIO_CNT = 0x10, 5150 MLXSW_REG_PPCNT_TC_CNT = 0x11, 5151 MLXSW_REG_PPCNT_TC_CONG_CNT = 0x13, 5152 }; 5153 5154 /* reg_ppcnt_grp 5155 * Performance counter group. 5156 * Group 63 indicates all groups. Only valid on Set() operation with 5157 * clr bit set. 5158 * 0x0: IEEE 802.3 Counters 5159 * 0x1: RFC 2863 Counters 5160 * 0x2: RFC 2819 Counters 5161 * 0x3: RFC 3635 Counters 5162 * 0x5: Ethernet Extended Counters 5163 * 0x6: Ethernet Discard Counters 5164 * 0x8: Link Level Retransmission Counters 5165 * 0x10: Per Priority Counters 5166 * 0x11: Per Traffic Class Counters 5167 * 0x12: Physical Layer Counters 5168 * 0x13: Per Traffic Class Congestion Counters 5169 * Access: Index 5170 */ 5171 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6); 5172 5173 /* reg_ppcnt_clr 5174 * Clear counters. Setting the clr bit will reset the counter value 5175 * for all counters in the counter group. This bit can be set 5176 * for both Set() and Get() operation. 5177 * Access: OP 5178 */ 5179 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1); 5180 5181 /* reg_ppcnt_lp_gl 5182 * Local port global variable. 5183 * 0: local_port 255 = all ports of the device. 5184 * 1: local_port indicates local port number for all ports. 5185 * Access: OP 5186 */ 5187 MLXSW_ITEM32(reg, ppcnt, lp_gl, 0x04, 30, 1); 5188 5189 /* reg_ppcnt_prio_tc 5190 * Priority for counter set that support per priority, valid values: 0-7. 5191 * Traffic class for counter set that support per traffic class, 5192 * valid values: 0- cap_max_tclass-1 . 5193 * For HCA: cap_max_tclass is always 8. 5194 * Otherwise must be 0. 5195 * Access: Index 5196 */ 5197 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5); 5198 5199 /* Ethernet IEEE 802.3 Counter Group */ 5200 5201 /* reg_ppcnt_a_frames_transmitted_ok 5202 * Access: RO 5203 */ 5204 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok, 5205 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5206 5207 /* reg_ppcnt_a_frames_received_ok 5208 * Access: RO 5209 */ 5210 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok, 5211 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5212 5213 /* reg_ppcnt_a_frame_check_sequence_errors 5214 * Access: RO 5215 */ 5216 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors, 5217 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 5218 5219 /* reg_ppcnt_a_alignment_errors 5220 * Access: RO 5221 */ 5222 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors, 5223 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 5224 5225 /* reg_ppcnt_a_octets_transmitted_ok 5226 * Access: RO 5227 */ 5228 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok, 5229 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5230 5231 /* reg_ppcnt_a_octets_received_ok 5232 * Access: RO 5233 */ 5234 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok, 5235 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5236 5237 /* reg_ppcnt_a_multicast_frames_xmitted_ok 5238 * Access: RO 5239 */ 5240 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok, 5241 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 5242 5243 /* reg_ppcnt_a_broadcast_frames_xmitted_ok 5244 * Access: RO 5245 */ 5246 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok, 5247 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 5248 5249 /* reg_ppcnt_a_multicast_frames_received_ok 5250 * Access: RO 5251 */ 5252 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok, 5253 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5254 5255 /* reg_ppcnt_a_broadcast_frames_received_ok 5256 * Access: RO 5257 */ 5258 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok, 5259 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 5260 5261 /* reg_ppcnt_a_in_range_length_errors 5262 * Access: RO 5263 */ 5264 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors, 5265 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5266 5267 /* reg_ppcnt_a_out_of_range_length_field 5268 * Access: RO 5269 */ 5270 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field, 5271 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5272 5273 /* reg_ppcnt_a_frame_too_long_errors 5274 * Access: RO 5275 */ 5276 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors, 5277 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5278 5279 /* reg_ppcnt_a_symbol_error_during_carrier 5280 * Access: RO 5281 */ 5282 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier, 5283 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5284 5285 /* reg_ppcnt_a_mac_control_frames_transmitted 5286 * Access: RO 5287 */ 5288 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted, 5289 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5290 5291 /* reg_ppcnt_a_mac_control_frames_received 5292 * Access: RO 5293 */ 5294 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received, 5295 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 5296 5297 /* reg_ppcnt_a_unsupported_opcodes_received 5298 * Access: RO 5299 */ 5300 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received, 5301 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 5302 5303 /* reg_ppcnt_a_pause_mac_ctrl_frames_received 5304 * Access: RO 5305 */ 5306 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received, 5307 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 5308 5309 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted 5310 * Access: RO 5311 */ 5312 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted, 5313 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 5314 5315 /* Ethernet RFC 2863 Counter Group */ 5316 5317 /* reg_ppcnt_if_in_discards 5318 * Access: RO 5319 */ 5320 MLXSW_ITEM64(reg, ppcnt, if_in_discards, 5321 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 5322 5323 /* reg_ppcnt_if_out_discards 5324 * Access: RO 5325 */ 5326 MLXSW_ITEM64(reg, ppcnt, if_out_discards, 5327 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 5328 5329 /* reg_ppcnt_if_out_errors 5330 * Access: RO 5331 */ 5332 MLXSW_ITEM64(reg, ppcnt, if_out_errors, 5333 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5334 5335 /* Ethernet RFC 2819 Counter Group */ 5336 5337 /* reg_ppcnt_ether_stats_undersize_pkts 5338 * Access: RO 5339 */ 5340 MLXSW_ITEM64(reg, ppcnt, ether_stats_undersize_pkts, 5341 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 5342 5343 /* reg_ppcnt_ether_stats_oversize_pkts 5344 * Access: RO 5345 */ 5346 MLXSW_ITEM64(reg, ppcnt, ether_stats_oversize_pkts, 5347 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 5348 5349 /* reg_ppcnt_ether_stats_fragments 5350 * Access: RO 5351 */ 5352 MLXSW_ITEM64(reg, ppcnt, ether_stats_fragments, 5353 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5354 5355 /* reg_ppcnt_ether_stats_pkts64octets 5356 * Access: RO 5357 */ 5358 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets, 5359 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5360 5361 /* reg_ppcnt_ether_stats_pkts65to127octets 5362 * Access: RO 5363 */ 5364 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets, 5365 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5366 5367 /* reg_ppcnt_ether_stats_pkts128to255octets 5368 * Access: RO 5369 */ 5370 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets, 5371 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5372 5373 /* reg_ppcnt_ether_stats_pkts256to511octets 5374 * Access: RO 5375 */ 5376 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets, 5377 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5378 5379 /* reg_ppcnt_ether_stats_pkts512to1023octets 5380 * Access: RO 5381 */ 5382 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets, 5383 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 5384 5385 /* reg_ppcnt_ether_stats_pkts1024to1518octets 5386 * Access: RO 5387 */ 5388 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets, 5389 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 5390 5391 /* reg_ppcnt_ether_stats_pkts1519to2047octets 5392 * Access: RO 5393 */ 5394 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets, 5395 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 5396 5397 /* reg_ppcnt_ether_stats_pkts2048to4095octets 5398 * Access: RO 5399 */ 5400 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets, 5401 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 5402 5403 /* reg_ppcnt_ether_stats_pkts4096to8191octets 5404 * Access: RO 5405 */ 5406 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets, 5407 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64); 5408 5409 /* reg_ppcnt_ether_stats_pkts8192to10239octets 5410 * Access: RO 5411 */ 5412 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets, 5413 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64); 5414 5415 /* Ethernet RFC 3635 Counter Group */ 5416 5417 /* reg_ppcnt_dot3stats_fcs_errors 5418 * Access: RO 5419 */ 5420 MLXSW_ITEM64(reg, ppcnt, dot3stats_fcs_errors, 5421 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5422 5423 /* reg_ppcnt_dot3stats_symbol_errors 5424 * Access: RO 5425 */ 5426 MLXSW_ITEM64(reg, ppcnt, dot3stats_symbol_errors, 5427 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5428 5429 /* reg_ppcnt_dot3control_in_unknown_opcodes 5430 * Access: RO 5431 */ 5432 MLXSW_ITEM64(reg, ppcnt, dot3control_in_unknown_opcodes, 5433 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5434 5435 /* reg_ppcnt_dot3in_pause_frames 5436 * Access: RO 5437 */ 5438 MLXSW_ITEM64(reg, ppcnt, dot3in_pause_frames, 5439 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5440 5441 /* Ethernet Extended Counter Group Counters */ 5442 5443 /* reg_ppcnt_ecn_marked 5444 * Access: RO 5445 */ 5446 MLXSW_ITEM64(reg, ppcnt, ecn_marked, 5447 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5448 5449 /* Ethernet Discard Counter Group Counters */ 5450 5451 /* reg_ppcnt_ingress_general 5452 * Access: RO 5453 */ 5454 MLXSW_ITEM64(reg, ppcnt, ingress_general, 5455 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5456 5457 /* reg_ppcnt_ingress_policy_engine 5458 * Access: RO 5459 */ 5460 MLXSW_ITEM64(reg, ppcnt, ingress_policy_engine, 5461 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5462 5463 /* reg_ppcnt_ingress_vlan_membership 5464 * Access: RO 5465 */ 5466 MLXSW_ITEM64(reg, ppcnt, ingress_vlan_membership, 5467 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 5468 5469 /* reg_ppcnt_ingress_tag_frame_type 5470 * Access: RO 5471 */ 5472 MLXSW_ITEM64(reg, ppcnt, ingress_tag_frame_type, 5473 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 5474 5475 /* reg_ppcnt_egress_vlan_membership 5476 * Access: RO 5477 */ 5478 MLXSW_ITEM64(reg, ppcnt, egress_vlan_membership, 5479 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5480 5481 /* reg_ppcnt_loopback_filter 5482 * Access: RO 5483 */ 5484 MLXSW_ITEM64(reg, ppcnt, loopback_filter, 5485 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5486 5487 /* reg_ppcnt_egress_general 5488 * Access: RO 5489 */ 5490 MLXSW_ITEM64(reg, ppcnt, egress_general, 5491 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 5492 5493 /* reg_ppcnt_egress_hoq 5494 * Access: RO 5495 */ 5496 MLXSW_ITEM64(reg, ppcnt, egress_hoq, 5497 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5498 5499 /* reg_ppcnt_egress_policy_engine 5500 * Access: RO 5501 */ 5502 MLXSW_ITEM64(reg, ppcnt, egress_policy_engine, 5503 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5504 5505 /* reg_ppcnt_ingress_tx_link_down 5506 * Access: RO 5507 */ 5508 MLXSW_ITEM64(reg, ppcnt, ingress_tx_link_down, 5509 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5510 5511 /* reg_ppcnt_egress_stp_filter 5512 * Access: RO 5513 */ 5514 MLXSW_ITEM64(reg, ppcnt, egress_stp_filter, 5515 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5516 5517 /* reg_ppcnt_egress_sll 5518 * Access: RO 5519 */ 5520 MLXSW_ITEM64(reg, ppcnt, egress_sll, 5521 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5522 5523 /* Ethernet Per Priority Group Counters */ 5524 5525 /* reg_ppcnt_rx_octets 5526 * Access: RO 5527 */ 5528 MLXSW_ITEM64(reg, ppcnt, rx_octets, 5529 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5530 5531 /* reg_ppcnt_rx_frames 5532 * Access: RO 5533 */ 5534 MLXSW_ITEM64(reg, ppcnt, rx_frames, 5535 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5536 5537 /* reg_ppcnt_tx_octets 5538 * Access: RO 5539 */ 5540 MLXSW_ITEM64(reg, ppcnt, tx_octets, 5541 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5542 5543 /* reg_ppcnt_tx_frames 5544 * Access: RO 5545 */ 5546 MLXSW_ITEM64(reg, ppcnt, tx_frames, 5547 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 5548 5549 /* reg_ppcnt_rx_pause 5550 * Access: RO 5551 */ 5552 MLXSW_ITEM64(reg, ppcnt, rx_pause, 5553 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5554 5555 /* reg_ppcnt_rx_pause_duration 5556 * Access: RO 5557 */ 5558 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration, 5559 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5560 5561 /* reg_ppcnt_tx_pause 5562 * Access: RO 5563 */ 5564 MLXSW_ITEM64(reg, ppcnt, tx_pause, 5565 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5566 5567 /* reg_ppcnt_tx_pause_duration 5568 * Access: RO 5569 */ 5570 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration, 5571 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5572 5573 /* reg_ppcnt_rx_pause_transition 5574 * Access: RO 5575 */ 5576 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition, 5577 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5578 5579 /* Ethernet Per Traffic Class Counters */ 5580 5581 /* reg_ppcnt_tc_transmit_queue 5582 * Contains the transmit queue depth in cells of traffic class 5583 * selected by prio_tc and the port selected by local_port. 5584 * The field cannot be cleared. 5585 * Access: RO 5586 */ 5587 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue, 5588 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5589 5590 /* reg_ppcnt_tc_no_buffer_discard_uc 5591 * The number of unicast packets dropped due to lack of shared 5592 * buffer resources. 5593 * Access: RO 5594 */ 5595 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc, 5596 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5597 5598 /* Ethernet Per Traffic Class Congestion Group Counters */ 5599 5600 /* reg_ppcnt_wred_discard 5601 * Access: RO 5602 */ 5603 MLXSW_ITEM64(reg, ppcnt, wred_discard, 5604 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5605 5606 /* reg_ppcnt_ecn_marked_tc 5607 * Access: RO 5608 */ 5609 MLXSW_ITEM64(reg, ppcnt, ecn_marked_tc, 5610 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5611 5612 static inline void mlxsw_reg_ppcnt_pack(char *payload, u16 local_port, 5613 enum mlxsw_reg_ppcnt_grp grp, 5614 u8 prio_tc) 5615 { 5616 MLXSW_REG_ZERO(ppcnt, payload); 5617 mlxsw_reg_ppcnt_swid_set(payload, 0); 5618 mlxsw_reg_ppcnt_local_port_set(payload, local_port); 5619 mlxsw_reg_ppcnt_pnat_set(payload, 0); 5620 mlxsw_reg_ppcnt_grp_set(payload, grp); 5621 mlxsw_reg_ppcnt_clr_set(payload, 0); 5622 mlxsw_reg_ppcnt_lp_gl_set(payload, 1); 5623 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc); 5624 } 5625 5626 /* PPTB - Port Prio To Buffer Register 5627 * ----------------------------------- 5628 * Configures the switch priority to buffer table. 5629 */ 5630 #define MLXSW_REG_PPTB_ID 0x500B 5631 #define MLXSW_REG_PPTB_LEN 0x10 5632 5633 MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN); 5634 5635 enum { 5636 MLXSW_REG_PPTB_MM_UM, 5637 MLXSW_REG_PPTB_MM_UNICAST, 5638 MLXSW_REG_PPTB_MM_MULTICAST, 5639 }; 5640 5641 /* reg_pptb_mm 5642 * Mapping mode. 5643 * 0 - Map both unicast and multicast packets to the same buffer. 5644 * 1 - Map only unicast packets. 5645 * 2 - Map only multicast packets. 5646 * Access: Index 5647 * 5648 * Note: SwitchX-2 only supports the first option. 5649 */ 5650 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2); 5651 5652 /* reg_pptb_local_port 5653 * Local port number. 5654 * Access: Index 5655 */ 5656 MLXSW_ITEM32_LP(reg, pptb, 0x00, 16, 0x00, 12); 5657 5658 /* reg_pptb_um 5659 * Enables the update of the untagged_buf field. 5660 * Access: RW 5661 */ 5662 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1); 5663 5664 /* reg_pptb_pm 5665 * Enables the update of the prio_to_buff field. 5666 * Bit <i> is a flag for updating the mapping for switch priority <i>. 5667 * Access: RW 5668 */ 5669 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8); 5670 5671 /* reg_pptb_prio_to_buff 5672 * Mapping of switch priority <i> to one of the allocated receive port 5673 * buffers. 5674 * Access: RW 5675 */ 5676 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4); 5677 5678 /* reg_pptb_pm_msb 5679 * Enables the update of the prio_to_buff field. 5680 * Bit <i> is a flag for updating the mapping for switch priority <i+8>. 5681 * Access: RW 5682 */ 5683 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8); 5684 5685 /* reg_pptb_untagged_buff 5686 * Mapping of untagged frames to one of the allocated receive port buffers. 5687 * Access: RW 5688 * 5689 * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for 5690 * Spectrum, as it maps untagged packets based on the default switch priority. 5691 */ 5692 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4); 5693 5694 /* reg_pptb_prio_to_buff_msb 5695 * Mapping of switch priority <i+8> to one of the allocated receive port 5696 * buffers. 5697 * Access: RW 5698 */ 5699 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4); 5700 5701 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF 5702 5703 static inline void mlxsw_reg_pptb_pack(char *payload, u16 local_port) 5704 { 5705 MLXSW_REG_ZERO(pptb, payload); 5706 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM); 5707 mlxsw_reg_pptb_local_port_set(payload, local_port); 5708 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 5709 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 5710 } 5711 5712 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio, 5713 u8 buff) 5714 { 5715 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff); 5716 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff); 5717 } 5718 5719 /* PBMC - Port Buffer Management Control Register 5720 * ---------------------------------------------- 5721 * The PBMC register configures and retrieves the port packet buffer 5722 * allocation for different Prios, and the Pause threshold management. 5723 */ 5724 #define MLXSW_REG_PBMC_ID 0x500C 5725 #define MLXSW_REG_PBMC_LEN 0x6C 5726 5727 MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN); 5728 5729 /* reg_pbmc_local_port 5730 * Local port number. 5731 * Access: Index 5732 */ 5733 MLXSW_ITEM32_LP(reg, pbmc, 0x00, 16, 0x00, 12); 5734 5735 /* reg_pbmc_xoff_timer_value 5736 * When device generates a pause frame, it uses this value as the pause 5737 * timer (time for the peer port to pause in quota-512 bit time). 5738 * Access: RW 5739 */ 5740 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16); 5741 5742 /* reg_pbmc_xoff_refresh 5743 * The time before a new pause frame should be sent to refresh the pause RW 5744 * state. Using the same units as xoff_timer_value above (in quota-512 bit 5745 * time). 5746 * Access: RW 5747 */ 5748 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16); 5749 5750 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11 5751 5752 /* reg_pbmc_buf_lossy 5753 * The field indicates if the buffer is lossy. 5754 * 0 - Lossless 5755 * 1 - Lossy 5756 * Access: RW 5757 */ 5758 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false); 5759 5760 /* reg_pbmc_buf_epsb 5761 * Eligible for Port Shared buffer. 5762 * If epsb is set, packets assigned to buffer are allowed to insert the port 5763 * shared buffer. 5764 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved. 5765 * Access: RW 5766 */ 5767 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false); 5768 5769 /* reg_pbmc_buf_size 5770 * The part of the packet buffer array is allocated for the specific buffer. 5771 * Units are represented in cells. 5772 * Access: RW 5773 */ 5774 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false); 5775 5776 /* reg_pbmc_buf_xoff_threshold 5777 * Once the amount of data in the buffer goes above this value, device 5778 * starts sending PFC frames for all priorities associated with the 5779 * buffer. Units are represented in cells. Reserved in case of lossy 5780 * buffer. 5781 * Access: RW 5782 * 5783 * Note: In Spectrum, reserved for buffer[9]. 5784 */ 5785 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16, 5786 0x08, 0x04, false); 5787 5788 /* reg_pbmc_buf_xon_threshold 5789 * When the amount of data in the buffer goes below this value, device 5790 * stops sending PFC frames for the priorities associated with the 5791 * buffer. Units are represented in cells. Reserved in case of lossy 5792 * buffer. 5793 * Access: RW 5794 * 5795 * Note: In Spectrum, reserved for buffer[9]. 5796 */ 5797 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16, 5798 0x08, 0x04, false); 5799 5800 static inline void mlxsw_reg_pbmc_pack(char *payload, u16 local_port, 5801 u16 xoff_timer_value, u16 xoff_refresh) 5802 { 5803 MLXSW_REG_ZERO(pbmc, payload); 5804 mlxsw_reg_pbmc_local_port_set(payload, local_port); 5805 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value); 5806 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh); 5807 } 5808 5809 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload, 5810 int buf_index, 5811 u16 size) 5812 { 5813 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1); 5814 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5815 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5816 } 5817 5818 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload, 5819 int buf_index, u16 size, 5820 u16 threshold) 5821 { 5822 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0); 5823 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5824 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5825 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold); 5826 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold); 5827 } 5828 5829 /* PSPA - Port Switch Partition Allocation 5830 * --------------------------------------- 5831 * Controls the association of a port with a switch partition and enables 5832 * configuring ports as stacking ports. 5833 */ 5834 #define MLXSW_REG_PSPA_ID 0x500D 5835 #define MLXSW_REG_PSPA_LEN 0x8 5836 5837 MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN); 5838 5839 /* reg_pspa_swid 5840 * Switch partition ID. 5841 * Access: RW 5842 */ 5843 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8); 5844 5845 /* reg_pspa_local_port 5846 * Local port number. 5847 * Access: Index 5848 */ 5849 MLXSW_ITEM32_LP(reg, pspa, 0x00, 16, 0x00, 0); 5850 5851 /* reg_pspa_sub_port 5852 * Virtual port within the local port. Set to 0 when virtual ports are 5853 * disabled on the local port. 5854 * Access: Index 5855 */ 5856 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8); 5857 5858 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u16 local_port) 5859 { 5860 MLXSW_REG_ZERO(pspa, payload); 5861 mlxsw_reg_pspa_swid_set(payload, swid); 5862 mlxsw_reg_pspa_local_port_set(payload, local_port); 5863 mlxsw_reg_pspa_sub_port_set(payload, 0); 5864 } 5865 5866 /* PMAOS - Ports Module Administrative and Operational Status 5867 * ---------------------------------------------------------- 5868 * This register configures and retrieves the per module status. 5869 */ 5870 #define MLXSW_REG_PMAOS_ID 0x5012 5871 #define MLXSW_REG_PMAOS_LEN 0x10 5872 5873 MLXSW_REG_DEFINE(pmaos, MLXSW_REG_PMAOS_ID, MLXSW_REG_PMAOS_LEN); 5874 5875 /* reg_pmaos_rst 5876 * Module reset toggle. 5877 * Note: Setting reset while module is plugged-in will result in transition to 5878 * "initializing" operational state. 5879 * Access: OP 5880 */ 5881 MLXSW_ITEM32(reg, pmaos, rst, 0x00, 31, 1); 5882 5883 /* reg_pmaos_slot_index 5884 * Slot index. 5885 * Access: Index 5886 */ 5887 MLXSW_ITEM32(reg, pmaos, slot_index, 0x00, 24, 4); 5888 5889 /* reg_pmaos_module 5890 * Module number. 5891 * Access: Index 5892 */ 5893 MLXSW_ITEM32(reg, pmaos, module, 0x00, 16, 8); 5894 5895 enum mlxsw_reg_pmaos_admin_status { 5896 MLXSW_REG_PMAOS_ADMIN_STATUS_ENABLED = 1, 5897 MLXSW_REG_PMAOS_ADMIN_STATUS_DISABLED = 2, 5898 /* If the module is active and then unplugged, or experienced an error 5899 * event, the operational status should go to "disabled" and can only 5900 * be enabled upon explicit enable command. 5901 */ 5902 MLXSW_REG_PMAOS_ADMIN_STATUS_ENABLED_ONCE = 3, 5903 }; 5904 5905 /* reg_pmaos_admin_status 5906 * Module administrative state (the desired state of the module). 5907 * Note: To disable a module, all ports associated with the port must be 5908 * administatively down first. 5909 * Access: RW 5910 */ 5911 MLXSW_ITEM32(reg, pmaos, admin_status, 0x00, 8, 4); 5912 5913 /* reg_pmaos_ase 5914 * Admin state update enable. 5915 * If this bit is set, admin state will be updated based on admin_state field. 5916 * Only relevant on Set() operations. 5917 * Access: WO 5918 */ 5919 MLXSW_ITEM32(reg, pmaos, ase, 0x04, 31, 1); 5920 5921 /* reg_pmaos_ee 5922 * Event update enable. 5923 * If this bit is set, event generation will be updated based on the e field. 5924 * Only relevant on Set operations. 5925 * Access: WO 5926 */ 5927 MLXSW_ITEM32(reg, pmaos, ee, 0x04, 30, 1); 5928 5929 enum mlxsw_reg_pmaos_e { 5930 MLXSW_REG_PMAOS_E_DO_NOT_GENERATE_EVENT, 5931 MLXSW_REG_PMAOS_E_GENERATE_EVENT, 5932 MLXSW_REG_PMAOS_E_GENERATE_SINGLE_EVENT, 5933 }; 5934 5935 /* reg_pmaos_e 5936 * Event Generation on operational state change. 5937 * Access: RW 5938 */ 5939 MLXSW_ITEM32(reg, pmaos, e, 0x04, 0, 2); 5940 5941 static inline void mlxsw_reg_pmaos_pack(char *payload, u8 slot_index, u8 module) 5942 { 5943 MLXSW_REG_ZERO(pmaos, payload); 5944 mlxsw_reg_pmaos_slot_index_set(payload, slot_index); 5945 mlxsw_reg_pmaos_module_set(payload, module); 5946 } 5947 5948 /* PPLR - Port Physical Loopback Register 5949 * -------------------------------------- 5950 * This register allows configuration of the port's loopback mode. 5951 */ 5952 #define MLXSW_REG_PPLR_ID 0x5018 5953 #define MLXSW_REG_PPLR_LEN 0x8 5954 5955 MLXSW_REG_DEFINE(pplr, MLXSW_REG_PPLR_ID, MLXSW_REG_PPLR_LEN); 5956 5957 /* reg_pplr_local_port 5958 * Local port number. 5959 * Access: Index 5960 */ 5961 MLXSW_ITEM32_LP(reg, pplr, 0x00, 16, 0x00, 12); 5962 5963 /* Phy local loopback. When set the port's egress traffic is looped back 5964 * to the receiver and the port transmitter is disabled. 5965 */ 5966 #define MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL BIT(1) 5967 5968 /* reg_pplr_lb_en 5969 * Loopback enable. 5970 * Access: RW 5971 */ 5972 MLXSW_ITEM32(reg, pplr, lb_en, 0x04, 0, 8); 5973 5974 static inline void mlxsw_reg_pplr_pack(char *payload, u16 local_port, 5975 bool phy_local) 5976 { 5977 MLXSW_REG_ZERO(pplr, payload); 5978 mlxsw_reg_pplr_local_port_set(payload, local_port); 5979 mlxsw_reg_pplr_lb_en_set(payload, 5980 phy_local ? 5981 MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL : 0); 5982 } 5983 5984 /* PMTDB - Port Module To local DataBase Register 5985 * ---------------------------------------------- 5986 * The PMTDB register allows to query the possible module<->local port 5987 * mapping than can be used in PMLP. It does not represent the actual/current 5988 * mapping of the local to module. Actual mapping is only defined by PMLP. 5989 */ 5990 #define MLXSW_REG_PMTDB_ID 0x501A 5991 #define MLXSW_REG_PMTDB_LEN 0x40 5992 5993 MLXSW_REG_DEFINE(pmtdb, MLXSW_REG_PMTDB_ID, MLXSW_REG_PMTDB_LEN); 5994 5995 /* reg_pmtdb_slot_index 5996 * Slot index (0: Main board). 5997 * Access: Index 5998 */ 5999 MLXSW_ITEM32(reg, pmtdb, slot_index, 0x00, 24, 4); 6000 6001 /* reg_pmtdb_module 6002 * Module number. 6003 * Access: Index 6004 */ 6005 MLXSW_ITEM32(reg, pmtdb, module, 0x00, 16, 8); 6006 6007 /* reg_pmtdb_ports_width 6008 * Port's width 6009 * Access: Index 6010 */ 6011 MLXSW_ITEM32(reg, pmtdb, ports_width, 0x00, 12, 4); 6012 6013 /* reg_pmtdb_num_ports 6014 * Number of ports in a single module (split/breakout) 6015 * Access: Index 6016 */ 6017 MLXSW_ITEM32(reg, pmtdb, num_ports, 0x00, 8, 4); 6018 6019 enum mlxsw_reg_pmtdb_status { 6020 MLXSW_REG_PMTDB_STATUS_SUCCESS, 6021 }; 6022 6023 /* reg_pmtdb_status 6024 * Status 6025 * Access: RO 6026 */ 6027 MLXSW_ITEM32(reg, pmtdb, status, 0x00, 0, 4); 6028 6029 /* reg_pmtdb_port_num 6030 * The local_port value which can be assigned to the module. 6031 * In case of more than one port, port<x> represent the /<x> port of 6032 * the module. 6033 * Access: RO 6034 */ 6035 MLXSW_ITEM16_INDEXED(reg, pmtdb, port_num, 0x04, 0, 10, 0x02, 0x00, false); 6036 6037 static inline void mlxsw_reg_pmtdb_pack(char *payload, u8 slot_index, u8 module, 6038 u8 ports_width, u8 num_ports) 6039 { 6040 MLXSW_REG_ZERO(pmtdb, payload); 6041 mlxsw_reg_pmtdb_slot_index_set(payload, slot_index); 6042 mlxsw_reg_pmtdb_module_set(payload, module); 6043 mlxsw_reg_pmtdb_ports_width_set(payload, ports_width); 6044 mlxsw_reg_pmtdb_num_ports_set(payload, num_ports); 6045 } 6046 6047 /* PMECR - Ports Mapping Event Configuration Register 6048 * -------------------------------------------------- 6049 * The PMECR register is used to enable/disable event triggering 6050 * in case of local port mapping change. 6051 */ 6052 #define MLXSW_REG_PMECR_ID 0x501B 6053 #define MLXSW_REG_PMECR_LEN 0x20 6054 6055 MLXSW_REG_DEFINE(pmecr, MLXSW_REG_PMECR_ID, MLXSW_REG_PMECR_LEN); 6056 6057 /* reg_pmecr_local_port 6058 * Local port number. 6059 * Access: Index 6060 */ 6061 MLXSW_ITEM32_LP(reg, pmecr, 0x00, 16, 0x00, 12); 6062 6063 /* reg_pmecr_ee 6064 * Event update enable. If this bit is set, event generation will be updated 6065 * based on the e field. Only relevant on Set operations. 6066 * Access: WO 6067 */ 6068 MLXSW_ITEM32(reg, pmecr, ee, 0x04, 30, 1); 6069 6070 /* reg_pmecr_eswi 6071 * Software ignore enable bit. If this bit is set, the value of swi is used. 6072 * If this bit is clear, the value of swi is ignored. 6073 * Only relevant on Set operations. 6074 * Access: WO 6075 */ 6076 MLXSW_ITEM32(reg, pmecr, eswi, 0x04, 24, 1); 6077 6078 /* reg_pmecr_swi 6079 * Software ignore. If this bit is set, the device shouldn't generate events 6080 * in case of PMLP SET operation but only upon self local port mapping change 6081 * (if applicable according to e configuration). This is supplementary 6082 * configuration on top of e value. 6083 * Access: RW 6084 */ 6085 MLXSW_ITEM32(reg, pmecr, swi, 0x04, 8, 1); 6086 6087 enum mlxsw_reg_pmecr_e { 6088 MLXSW_REG_PMECR_E_DO_NOT_GENERATE_EVENT, 6089 MLXSW_REG_PMECR_E_GENERATE_EVENT, 6090 MLXSW_REG_PMECR_E_GENERATE_SINGLE_EVENT, 6091 }; 6092 6093 /* reg_pmecr_e 6094 * Event generation on local port mapping change. 6095 * Access: RW 6096 */ 6097 MLXSW_ITEM32(reg, pmecr, e, 0x04, 0, 2); 6098 6099 static inline void mlxsw_reg_pmecr_pack(char *payload, u16 local_port, 6100 enum mlxsw_reg_pmecr_e e) 6101 { 6102 MLXSW_REG_ZERO(pmecr, payload); 6103 mlxsw_reg_pmecr_local_port_set(payload, local_port); 6104 mlxsw_reg_pmecr_e_set(payload, e); 6105 mlxsw_reg_pmecr_ee_set(payload, true); 6106 mlxsw_reg_pmecr_swi_set(payload, true); 6107 mlxsw_reg_pmecr_eswi_set(payload, true); 6108 } 6109 6110 /* PMPE - Port Module Plug/Unplug Event Register 6111 * --------------------------------------------- 6112 * This register reports any operational status change of a module. 6113 * A change in the module’s state will generate an event only if the change 6114 * happens after arming the event mechanism. Any changes to the module state 6115 * while the event mechanism is not armed will not be reported. Software can 6116 * query the PMPE register for module status. 6117 */ 6118 #define MLXSW_REG_PMPE_ID 0x5024 6119 #define MLXSW_REG_PMPE_LEN 0x10 6120 6121 MLXSW_REG_DEFINE(pmpe, MLXSW_REG_PMPE_ID, MLXSW_REG_PMPE_LEN); 6122 6123 /* reg_pmpe_slot_index 6124 * Slot index. 6125 * Access: Index 6126 */ 6127 MLXSW_ITEM32(reg, pmpe, slot_index, 0x00, 24, 4); 6128 6129 /* reg_pmpe_module 6130 * Module number. 6131 * Access: Index 6132 */ 6133 MLXSW_ITEM32(reg, pmpe, module, 0x00, 16, 8); 6134 6135 enum mlxsw_reg_pmpe_module_status { 6136 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_ENABLED = 1, 6137 MLXSW_REG_PMPE_MODULE_STATUS_UNPLUGGED, 6138 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_ERROR, 6139 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_DISABLED, 6140 }; 6141 6142 /* reg_pmpe_module_status 6143 * Module status. 6144 * Access: RO 6145 */ 6146 MLXSW_ITEM32(reg, pmpe, module_status, 0x00, 0, 4); 6147 6148 /* reg_pmpe_error_type 6149 * Module error details. 6150 * Access: RO 6151 */ 6152 MLXSW_ITEM32(reg, pmpe, error_type, 0x04, 8, 4); 6153 6154 /* PDDR - Port Diagnostics Database Register 6155 * ----------------------------------------- 6156 * The PDDR enables to read the Phy debug database 6157 */ 6158 #define MLXSW_REG_PDDR_ID 0x5031 6159 #define MLXSW_REG_PDDR_LEN 0x100 6160 6161 MLXSW_REG_DEFINE(pddr, MLXSW_REG_PDDR_ID, MLXSW_REG_PDDR_LEN); 6162 6163 /* reg_pddr_local_port 6164 * Local port number. 6165 * Access: Index 6166 */ 6167 MLXSW_ITEM32_LP(reg, pddr, 0x00, 16, 0x00, 12); 6168 6169 enum mlxsw_reg_pddr_page_select { 6170 MLXSW_REG_PDDR_PAGE_SELECT_TROUBLESHOOTING_INFO = 1, 6171 }; 6172 6173 /* reg_pddr_page_select 6174 * Page select index. 6175 * Access: Index 6176 */ 6177 MLXSW_ITEM32(reg, pddr, page_select, 0x04, 0, 8); 6178 6179 enum mlxsw_reg_pddr_trblsh_group_opcode { 6180 /* Monitor opcodes */ 6181 MLXSW_REG_PDDR_TRBLSH_GROUP_OPCODE_MONITOR, 6182 }; 6183 6184 /* reg_pddr_group_opcode 6185 * Group selector. 6186 * Access: Index 6187 */ 6188 MLXSW_ITEM32(reg, pddr, trblsh_group_opcode, 0x08, 0, 16); 6189 6190 /* reg_pddr_status_opcode 6191 * Group selector. 6192 * Access: RO 6193 */ 6194 MLXSW_ITEM32(reg, pddr, trblsh_status_opcode, 0x0C, 0, 16); 6195 6196 static inline void mlxsw_reg_pddr_pack(char *payload, u16 local_port, 6197 u8 page_select) 6198 { 6199 MLXSW_REG_ZERO(pddr, payload); 6200 mlxsw_reg_pddr_local_port_set(payload, local_port); 6201 mlxsw_reg_pddr_page_select_set(payload, page_select); 6202 } 6203 6204 /* PMMP - Port Module Memory Map Properties Register 6205 * ------------------------------------------------- 6206 * The PMMP register allows to override the module memory map advertisement. 6207 * The register can only be set when the module is disabled by PMAOS register. 6208 */ 6209 #define MLXSW_REG_PMMP_ID 0x5044 6210 #define MLXSW_REG_PMMP_LEN 0x2C 6211 6212 MLXSW_REG_DEFINE(pmmp, MLXSW_REG_PMMP_ID, MLXSW_REG_PMMP_LEN); 6213 6214 /* reg_pmmp_module 6215 * Module number. 6216 * Access: Index 6217 */ 6218 MLXSW_ITEM32(reg, pmmp, module, 0x00, 16, 8); 6219 6220 /* reg_pmmp_slot_index 6221 * Slot index. 6222 * Access: Index 6223 */ 6224 MLXSW_ITEM32(reg, pmmp, slot_index, 0x00, 24, 4); 6225 6226 /* reg_pmmp_sticky 6227 * When set, will keep eeprom_override values after plug-out event. 6228 * Access: OP 6229 */ 6230 MLXSW_ITEM32(reg, pmmp, sticky, 0x00, 0, 1); 6231 6232 /* reg_pmmp_eeprom_override_mask 6233 * Write mask bit (negative polarity). 6234 * 0 - Allow write 6235 * 1 - Ignore write 6236 * On write, indicates which of the bits from eeprom_override field are 6237 * updated. 6238 * Access: WO 6239 */ 6240 MLXSW_ITEM32(reg, pmmp, eeprom_override_mask, 0x04, 16, 16); 6241 6242 enum { 6243 /* Set module to low power mode */ 6244 MLXSW_REG_PMMP_EEPROM_OVERRIDE_LOW_POWER_MASK = BIT(8), 6245 }; 6246 6247 /* reg_pmmp_eeprom_override 6248 * Override / ignore EEPROM advertisement properties bitmask 6249 * Access: RW 6250 */ 6251 MLXSW_ITEM32(reg, pmmp, eeprom_override, 0x04, 0, 16); 6252 6253 static inline void mlxsw_reg_pmmp_pack(char *payload, u8 slot_index, u8 module) 6254 { 6255 MLXSW_REG_ZERO(pmmp, payload); 6256 mlxsw_reg_pmmp_slot_index_set(payload, slot_index); 6257 mlxsw_reg_pmmp_module_set(payload, module); 6258 } 6259 6260 /* PLLP - Port Local port to Label Port mapping Register 6261 * ----------------------------------------------------- 6262 * The PLLP register returns the mapping from Local Port into Label Port. 6263 */ 6264 #define MLXSW_REG_PLLP_ID 0x504A 6265 #define MLXSW_REG_PLLP_LEN 0x10 6266 6267 MLXSW_REG_DEFINE(pllp, MLXSW_REG_PLLP_ID, MLXSW_REG_PLLP_LEN); 6268 6269 /* reg_pllp_local_port 6270 * Local port number. 6271 * Access: Index 6272 */ 6273 MLXSW_ITEM32_LP(reg, pllp, 0x00, 16, 0x00, 12); 6274 6275 /* reg_pllp_label_port 6276 * Front panel label of the port. 6277 * Access: RO 6278 */ 6279 MLXSW_ITEM32(reg, pllp, label_port, 0x00, 0, 8); 6280 6281 /* reg_pllp_split_num 6282 * Label split mapping for local_port. 6283 * Access: RO 6284 */ 6285 MLXSW_ITEM32(reg, pllp, split_num, 0x04, 0, 4); 6286 6287 /* reg_pllp_slot_index 6288 * Slot index (0: Main board). 6289 * Access: RO 6290 */ 6291 MLXSW_ITEM32(reg, pllp, slot_index, 0x08, 0, 4); 6292 6293 static inline void mlxsw_reg_pllp_pack(char *payload, u16 local_port) 6294 { 6295 MLXSW_REG_ZERO(pllp, payload); 6296 mlxsw_reg_pllp_local_port_set(payload, local_port); 6297 } 6298 6299 static inline void mlxsw_reg_pllp_unpack(char *payload, u8 *label_port, 6300 u8 *split_num, u8 *slot_index) 6301 { 6302 *label_port = mlxsw_reg_pllp_label_port_get(payload); 6303 *split_num = mlxsw_reg_pllp_split_num_get(payload); 6304 *slot_index = mlxsw_reg_pllp_slot_index_get(payload); 6305 } 6306 6307 /* PMTM - Port Module Type Mapping Register 6308 * ---------------------------------------- 6309 * The PMTM register allows query or configuration of module types. 6310 * The register can only be set when the module is disabled by PMAOS register 6311 */ 6312 #define MLXSW_REG_PMTM_ID 0x5067 6313 #define MLXSW_REG_PMTM_LEN 0x10 6314 6315 MLXSW_REG_DEFINE(pmtm, MLXSW_REG_PMTM_ID, MLXSW_REG_PMTM_LEN); 6316 6317 /* reg_pmtm_slot_index 6318 * Slot index. 6319 * Access: Index 6320 */ 6321 MLXSW_ITEM32(reg, pmtm, slot_index, 0x00, 24, 4); 6322 6323 /* reg_pmtm_module 6324 * Module number. 6325 * Access: Index 6326 */ 6327 MLXSW_ITEM32(reg, pmtm, module, 0x00, 16, 8); 6328 6329 enum mlxsw_reg_pmtm_module_type { 6330 MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_4_LANES = 0, 6331 MLXSW_REG_PMTM_MODULE_TYPE_QSFP = 1, 6332 MLXSW_REG_PMTM_MODULE_TYPE_SFP = 2, 6333 MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_SINGLE_LANE = 4, 6334 MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_2_LANES = 8, 6335 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP4X = 10, 6336 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP2X = 11, 6337 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP1X = 12, 6338 MLXSW_REG_PMTM_MODULE_TYPE_QSFP_DD = 14, 6339 MLXSW_REG_PMTM_MODULE_TYPE_OSFP = 15, 6340 MLXSW_REG_PMTM_MODULE_TYPE_SFP_DD = 16, 6341 MLXSW_REG_PMTM_MODULE_TYPE_DSFP = 17, 6342 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP8X = 18, 6343 MLXSW_REG_PMTM_MODULE_TYPE_TWISTED_PAIR = 19, 6344 }; 6345 6346 /* reg_pmtm_module_type 6347 * Module type. 6348 * Access: RW 6349 */ 6350 MLXSW_ITEM32(reg, pmtm, module_type, 0x04, 0, 5); 6351 6352 static inline void mlxsw_reg_pmtm_pack(char *payload, u8 slot_index, u8 module) 6353 { 6354 MLXSW_REG_ZERO(pmtm, payload); 6355 mlxsw_reg_pmtm_slot_index_set(payload, slot_index); 6356 mlxsw_reg_pmtm_module_set(payload, module); 6357 } 6358 6359 /* HTGT - Host Trap Group Table 6360 * ---------------------------- 6361 * Configures the properties for forwarding to CPU. 6362 */ 6363 #define MLXSW_REG_HTGT_ID 0x7002 6364 #define MLXSW_REG_HTGT_LEN 0x20 6365 6366 MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN); 6367 6368 /* reg_htgt_swid 6369 * Switch partition ID. 6370 * Access: Index 6371 */ 6372 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8); 6373 6374 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */ 6375 6376 /* reg_htgt_type 6377 * CPU path type. 6378 * Access: RW 6379 */ 6380 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4); 6381 6382 enum mlxsw_reg_htgt_trap_group { 6383 MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 6384 MLXSW_REG_HTGT_TRAP_GROUP_CORE_EVENT, 6385 MLXSW_REG_HTGT_TRAP_GROUP_SP_STP, 6386 MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP, 6387 MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP, 6388 MLXSW_REG_HTGT_TRAP_GROUP_SP_MC_SNOOPING, 6389 MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP, 6390 MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF, 6391 MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM, 6392 MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST, 6393 MLXSW_REG_HTGT_TRAP_GROUP_SP_NEIGH_DISCOVERY, 6394 MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP, 6395 MLXSW_REG_HTGT_TRAP_GROUP_SP_EXTERNAL_ROUTE, 6396 MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME, 6397 MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP, 6398 MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT, 6399 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6, 6400 MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR, 6401 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0, 6402 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1, 6403 MLXSW_REG_HTGT_TRAP_GROUP_SP_VRRP, 6404 MLXSW_REG_HTGT_TRAP_GROUP_SP_PKT_SAMPLE, 6405 MLXSW_REG_HTGT_TRAP_GROUP_SP_FLOW_LOGGING, 6406 MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS, 6407 MLXSW_REG_HTGT_TRAP_GROUP_SP_BFD, 6408 MLXSW_REG_HTGT_TRAP_GROUP_SP_DUMMY, 6409 MLXSW_REG_HTGT_TRAP_GROUP_SP_L2_DISCARDS, 6410 MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_DISCARDS, 6411 MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_EXCEPTIONS, 6412 MLXSW_REG_HTGT_TRAP_GROUP_SP_TUNNEL_DISCARDS, 6413 MLXSW_REG_HTGT_TRAP_GROUP_SP_ACL_DISCARDS, 6414 MLXSW_REG_HTGT_TRAP_GROUP_SP_BUFFER_DISCARDS, 6415 MLXSW_REG_HTGT_TRAP_GROUP_SP_EAPOL, 6416 6417 __MLXSW_REG_HTGT_TRAP_GROUP_MAX, 6418 MLXSW_REG_HTGT_TRAP_GROUP_MAX = __MLXSW_REG_HTGT_TRAP_GROUP_MAX - 1 6419 }; 6420 6421 /* reg_htgt_trap_group 6422 * Trap group number. User defined number specifying which trap groups 6423 * should be forwarded to the CPU. The mapping between trap IDs and trap 6424 * groups is configured using HPKT register. 6425 * Access: Index 6426 */ 6427 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8); 6428 6429 enum { 6430 MLXSW_REG_HTGT_POLICER_DISABLE, 6431 MLXSW_REG_HTGT_POLICER_ENABLE, 6432 }; 6433 6434 /* reg_htgt_pide 6435 * Enable policer ID specified using 'pid' field. 6436 * Access: RW 6437 */ 6438 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1); 6439 6440 #define MLXSW_REG_HTGT_INVALID_POLICER 0xff 6441 6442 /* reg_htgt_pid 6443 * Policer ID for the trap group. 6444 * Access: RW 6445 */ 6446 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8); 6447 6448 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0 6449 6450 /* reg_htgt_mirror_action 6451 * Mirror action to use. 6452 * 0 - Trap to CPU. 6453 * 1 - Trap to CPU and mirror to a mirroring agent. 6454 * 2 - Mirror to a mirroring agent and do not trap to CPU. 6455 * Access: RW 6456 * 6457 * Note: Mirroring to a mirroring agent is only supported in Spectrum. 6458 */ 6459 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2); 6460 6461 /* reg_htgt_mirroring_agent 6462 * Mirroring agent. 6463 * Access: RW 6464 */ 6465 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3); 6466 6467 #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0 6468 6469 /* reg_htgt_priority 6470 * Trap group priority. 6471 * In case a packet matches multiple classification rules, the packet will 6472 * only be trapped once, based on the trap ID associated with the group (via 6473 * register HPKT) with the highest priority. 6474 * Supported values are 0-7, with 7 represnting the highest priority. 6475 * Access: RW 6476 * 6477 * Note: In SwitchX-2 this field is ignored and the priority value is replaced 6478 * by the 'trap_group' field. 6479 */ 6480 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4); 6481 6482 #define MLXSW_REG_HTGT_DEFAULT_TC 7 6483 6484 /* reg_htgt_local_path_cpu_tclass 6485 * CPU ingress traffic class for the trap group. 6486 * Access: RW 6487 */ 6488 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6); 6489 6490 enum mlxsw_reg_htgt_local_path_rdq { 6491 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13, 6492 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14, 6493 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15, 6494 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15, 6495 }; 6496 /* reg_htgt_local_path_rdq 6497 * Receive descriptor queue (RDQ) to use for the trap group. 6498 * Access: RW 6499 */ 6500 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6); 6501 6502 static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id, 6503 u8 priority, u8 tc) 6504 { 6505 MLXSW_REG_ZERO(htgt, payload); 6506 6507 if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) { 6508 mlxsw_reg_htgt_pide_set(payload, 6509 MLXSW_REG_HTGT_POLICER_DISABLE); 6510 } else { 6511 mlxsw_reg_htgt_pide_set(payload, 6512 MLXSW_REG_HTGT_POLICER_ENABLE); 6513 mlxsw_reg_htgt_pid_set(payload, policer_id); 6514 } 6515 6516 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL); 6517 mlxsw_reg_htgt_trap_group_set(payload, group); 6518 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU); 6519 mlxsw_reg_htgt_mirroring_agent_set(payload, 0); 6520 mlxsw_reg_htgt_priority_set(payload, priority); 6521 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc); 6522 mlxsw_reg_htgt_local_path_rdq_set(payload, group); 6523 } 6524 6525 /* HPKT - Host Packet Trap 6526 * ----------------------- 6527 * Configures trap IDs inside trap groups. 6528 */ 6529 #define MLXSW_REG_HPKT_ID 0x7003 6530 #define MLXSW_REG_HPKT_LEN 0x10 6531 6532 MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN); 6533 6534 enum { 6535 MLXSW_REG_HPKT_ACK_NOT_REQUIRED, 6536 MLXSW_REG_HPKT_ACK_REQUIRED, 6537 }; 6538 6539 /* reg_hpkt_ack 6540 * Require acknowledgements from the host for events. 6541 * If set, then the device will wait for the event it sent to be acknowledged 6542 * by the host. This option is only relevant for event trap IDs. 6543 * Access: RW 6544 * 6545 * Note: Currently not supported by firmware. 6546 */ 6547 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1); 6548 6549 enum mlxsw_reg_hpkt_action { 6550 MLXSW_REG_HPKT_ACTION_FORWARD, 6551 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU, 6552 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU, 6553 MLXSW_REG_HPKT_ACTION_DISCARD, 6554 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD, 6555 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD, 6556 MLXSW_REG_HPKT_ACTION_TRAP_EXCEPTION_TO_CPU, 6557 MLXSW_REG_HPKT_ACTION_SET_FW_DEFAULT = 15, 6558 }; 6559 6560 /* reg_hpkt_action 6561 * Action to perform on packet when trapped. 6562 * 0 - No action. Forward to CPU based on switching rules. 6563 * 1 - Trap to CPU (CPU receives sole copy). 6564 * 2 - Mirror to CPU (CPU receives a replica of the packet). 6565 * 3 - Discard. 6566 * 4 - Soft discard (allow other traps to act on the packet). 6567 * 5 - Trap and soft discard (allow other traps to overwrite this trap). 6568 * 6 - Trap to CPU (CPU receives sole copy) and count it as error. 6569 * 15 - Restore the firmware's default action. 6570 * Access: RW 6571 * 6572 * Note: Must be set to 0 (forward) for event trap IDs, as they are already 6573 * addressed to the CPU. 6574 */ 6575 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3); 6576 6577 /* reg_hpkt_trap_group 6578 * Trap group to associate the trap with. 6579 * Access: RW 6580 */ 6581 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6); 6582 6583 /* reg_hpkt_trap_id 6584 * Trap ID. 6585 * Access: Index 6586 * 6587 * Note: A trap ID can only be associated with a single trap group. The device 6588 * will associate the trap ID with the last trap group configured. 6589 */ 6590 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 10); 6591 6592 enum { 6593 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT, 6594 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER, 6595 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER, 6596 }; 6597 6598 /* reg_hpkt_ctrl 6599 * Configure dedicated buffer resources for control packets. 6600 * Ignored by SwitchX-2. 6601 * 0 - Keep factory defaults. 6602 * 1 - Do not use control buffer for this trap ID. 6603 * 2 - Use control buffer for this trap ID. 6604 * Access: RW 6605 */ 6606 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2); 6607 6608 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id, 6609 enum mlxsw_reg_htgt_trap_group trap_group, 6610 bool is_ctrl) 6611 { 6612 MLXSW_REG_ZERO(hpkt, payload); 6613 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED); 6614 mlxsw_reg_hpkt_action_set(payload, action); 6615 mlxsw_reg_hpkt_trap_group_set(payload, trap_group); 6616 mlxsw_reg_hpkt_trap_id_set(payload, trap_id); 6617 mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ? 6618 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER : 6619 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER); 6620 } 6621 6622 /* RGCR - Router General Configuration Register 6623 * -------------------------------------------- 6624 * The register is used for setting up the router configuration. 6625 */ 6626 #define MLXSW_REG_RGCR_ID 0x8001 6627 #define MLXSW_REG_RGCR_LEN 0x28 6628 6629 MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN); 6630 6631 /* reg_rgcr_ipv4_en 6632 * IPv4 router enable. 6633 * Access: RW 6634 */ 6635 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1); 6636 6637 /* reg_rgcr_ipv6_en 6638 * IPv6 router enable. 6639 * Access: RW 6640 */ 6641 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1); 6642 6643 /* reg_rgcr_max_router_interfaces 6644 * Defines the maximum number of active router interfaces for all virtual 6645 * routers. 6646 * Access: RW 6647 */ 6648 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16); 6649 6650 /* reg_rgcr_usp 6651 * Update switch priority and packet color. 6652 * 0 - Preserve the value of Switch Priority and packet color. 6653 * 1 - Recalculate the value of Switch Priority and packet color. 6654 * Access: RW 6655 * 6656 * Note: Not supported by SwitchX and SwitchX-2. 6657 */ 6658 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1); 6659 6660 /* reg_rgcr_pcp_rw 6661 * Indicates how to handle the pcp_rewrite_en value: 6662 * 0 - Preserve the value of pcp_rewrite_en. 6663 * 2 - Disable PCP rewrite. 6664 * 3 - Enable PCP rewrite. 6665 * Access: RW 6666 * 6667 * Note: Not supported by SwitchX and SwitchX-2. 6668 */ 6669 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2); 6670 6671 /* reg_rgcr_activity_dis 6672 * Activity disable: 6673 * 0 - Activity will be set when an entry is hit (default). 6674 * 1 - Activity will not be set when an entry is hit. 6675 * 6676 * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry 6677 * (RALUE). 6678 * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host 6679 * Entry (RAUHT). 6680 * Bits 2:7 are reserved. 6681 * Access: RW 6682 * 6683 * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB. 6684 */ 6685 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8); 6686 6687 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en, 6688 bool ipv6_en) 6689 { 6690 MLXSW_REG_ZERO(rgcr, payload); 6691 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en); 6692 mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en); 6693 } 6694 6695 /* RITR - Router Interface Table Register 6696 * -------------------------------------- 6697 * The register is used to configure the router interface table. 6698 */ 6699 #define MLXSW_REG_RITR_ID 0x8002 6700 #define MLXSW_REG_RITR_LEN 0x40 6701 6702 MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN); 6703 6704 /* reg_ritr_enable 6705 * Enables routing on the router interface. 6706 * Access: RW 6707 */ 6708 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1); 6709 6710 /* reg_ritr_ipv4 6711 * IPv4 routing enable. Enables routing of IPv4 traffic on the router 6712 * interface. 6713 * Access: RW 6714 */ 6715 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1); 6716 6717 /* reg_ritr_ipv6 6718 * IPv6 routing enable. Enables routing of IPv6 traffic on the router 6719 * interface. 6720 * Access: RW 6721 */ 6722 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1); 6723 6724 /* reg_ritr_ipv4_mc 6725 * IPv4 multicast routing enable. 6726 * Access: RW 6727 */ 6728 MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1); 6729 6730 /* reg_ritr_ipv6_mc 6731 * IPv6 multicast routing enable. 6732 * Access: RW 6733 */ 6734 MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1); 6735 6736 enum mlxsw_reg_ritr_if_type { 6737 /* VLAN interface. */ 6738 MLXSW_REG_RITR_VLAN_IF, 6739 /* FID interface. */ 6740 MLXSW_REG_RITR_FID_IF, 6741 /* Sub-port interface. */ 6742 MLXSW_REG_RITR_SP_IF, 6743 /* Loopback Interface. */ 6744 MLXSW_REG_RITR_LOOPBACK_IF, 6745 }; 6746 6747 /* reg_ritr_type 6748 * Router interface type as per enum mlxsw_reg_ritr_if_type. 6749 * Access: RW 6750 */ 6751 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3); 6752 6753 enum { 6754 MLXSW_REG_RITR_RIF_CREATE, 6755 MLXSW_REG_RITR_RIF_DEL, 6756 }; 6757 6758 /* reg_ritr_op 6759 * Opcode: 6760 * 0 - Create or edit RIF. 6761 * 1 - Delete RIF. 6762 * Reserved for SwitchX-2. For Spectrum, editing of interface properties 6763 * is not supported. An interface must be deleted and re-created in order 6764 * to update properties. 6765 * Access: WO 6766 */ 6767 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2); 6768 6769 /* reg_ritr_rif 6770 * Router interface index. A pointer to the Router Interface Table. 6771 * Access: Index 6772 */ 6773 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16); 6774 6775 /* reg_ritr_ipv4_fe 6776 * IPv4 Forwarding Enable. 6777 * Enables routing of IPv4 traffic on the router interface. When disabled, 6778 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 6779 * Not supported in SwitchX-2. 6780 * Access: RW 6781 */ 6782 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1); 6783 6784 /* reg_ritr_ipv6_fe 6785 * IPv6 Forwarding Enable. 6786 * Enables routing of IPv6 traffic on the router interface. When disabled, 6787 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 6788 * Not supported in SwitchX-2. 6789 * Access: RW 6790 */ 6791 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1); 6792 6793 /* reg_ritr_ipv4_mc_fe 6794 * IPv4 Multicast Forwarding Enable. 6795 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 6796 * will be enabled. 6797 * Access: RW 6798 */ 6799 MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1); 6800 6801 /* reg_ritr_ipv6_mc_fe 6802 * IPv6 Multicast Forwarding Enable. 6803 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 6804 * will be enabled. 6805 * Access: RW 6806 */ 6807 MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1); 6808 6809 /* reg_ritr_lb_en 6810 * Loop-back filter enable for unicast packets. 6811 * If the flag is set then loop-back filter for unicast packets is 6812 * implemented on the RIF. Multicast packets are always subject to 6813 * loop-back filtering. 6814 * Access: RW 6815 */ 6816 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1); 6817 6818 /* reg_ritr_virtual_router 6819 * Virtual router ID associated with the router interface. 6820 * Access: RW 6821 */ 6822 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16); 6823 6824 /* reg_ritr_mtu 6825 * Router interface MTU. 6826 * Access: RW 6827 */ 6828 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16); 6829 6830 /* reg_ritr_if_swid 6831 * Switch partition ID. 6832 * Access: RW 6833 */ 6834 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8); 6835 6836 /* reg_ritr_if_mac_profile_id 6837 * MAC msb profile ID. 6838 * Access: RW 6839 */ 6840 MLXSW_ITEM32(reg, ritr, if_mac_profile_id, 0x10, 16, 4); 6841 6842 /* reg_ritr_if_mac 6843 * Router interface MAC address. 6844 * In Spectrum, all MAC addresses must have the same 38 MSBits. 6845 * Access: RW 6846 */ 6847 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6); 6848 6849 /* reg_ritr_if_vrrp_id_ipv6 6850 * VRRP ID for IPv6 6851 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 6852 * Access: RW 6853 */ 6854 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8); 6855 6856 /* reg_ritr_if_vrrp_id_ipv4 6857 * VRRP ID for IPv4 6858 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 6859 * Access: RW 6860 */ 6861 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8); 6862 6863 /* VLAN Interface */ 6864 6865 /* reg_ritr_vlan_if_vlan_id 6866 * VLAN ID. 6867 * Access: RW 6868 */ 6869 MLXSW_ITEM32(reg, ritr, vlan_if_vlan_id, 0x08, 0, 12); 6870 6871 /* reg_ritr_vlan_if_efid 6872 * Egress FID. 6873 * Used to connect the RIF to a bridge. 6874 * Access: RW 6875 * 6876 * Note: Reserved when legacy bridge model is used and on Spectrum-1. 6877 */ 6878 MLXSW_ITEM32(reg, ritr, vlan_if_efid, 0x0C, 0, 16); 6879 6880 /* FID Interface */ 6881 6882 /* reg_ritr_fid_if_fid 6883 * Filtering ID. Used to connect a bridge to the router. 6884 * When legacy bridge model is used, only FIDs from the vFID range are 6885 * supported. When unified bridge model is used, this is the egress FID for 6886 * router to bridge. 6887 * Access: RW 6888 */ 6889 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16); 6890 6891 /* Sub-port Interface */ 6892 6893 /* reg_ritr_sp_if_lag 6894 * LAG indication. When this bit is set the system_port field holds the 6895 * LAG identifier. 6896 * Access: RW 6897 */ 6898 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1); 6899 6900 /* reg_ritr_sp_system_port 6901 * Port unique indentifier. When lag bit is set, this field holds the 6902 * lag_id in bits 0:9. 6903 * Access: RW 6904 */ 6905 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16); 6906 6907 /* reg_ritr_sp_if_efid 6908 * Egress filtering ID. 6909 * Used to connect the eRIF to a bridge if eRIF-ACL has modified the DMAC or 6910 * the VID. 6911 * Access: RW 6912 * 6913 * Note: Reserved when legacy bridge model is used. 6914 */ 6915 MLXSW_ITEM32(reg, ritr, sp_if_efid, 0x0C, 0, 16); 6916 6917 /* reg_ritr_sp_if_vid 6918 * VLAN ID. 6919 * Access: RW 6920 */ 6921 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12); 6922 6923 /* Loopback Interface */ 6924 6925 enum mlxsw_reg_ritr_loopback_protocol { 6926 /* IPinIP IPv4 underlay Unicast */ 6927 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4, 6928 /* IPinIP IPv6 underlay Unicast */ 6929 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6, 6930 /* IPinIP generic - used for Spectrum-2 underlay RIF */ 6931 MLXSW_REG_RITR_LOOPBACK_GENERIC, 6932 }; 6933 6934 /* reg_ritr_loopback_protocol 6935 * Access: RW 6936 */ 6937 MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4); 6938 6939 enum mlxsw_reg_ritr_loopback_ipip_type { 6940 /* Tunnel is IPinIP. */ 6941 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP, 6942 /* Tunnel is GRE, no key. */ 6943 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP, 6944 /* Tunnel is GRE, with a key. */ 6945 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP, 6946 }; 6947 6948 /* reg_ritr_loopback_ipip_type 6949 * Encapsulation type. 6950 * Access: RW 6951 */ 6952 MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4); 6953 6954 enum mlxsw_reg_ritr_loopback_ipip_options { 6955 /* The key is defined by gre_key. */ 6956 MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET, 6957 }; 6958 6959 /* reg_ritr_loopback_ipip_options 6960 * Access: RW 6961 */ 6962 MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4); 6963 6964 /* reg_ritr_loopback_ipip_uvr 6965 * Underlay Virtual Router ID. 6966 * Range is 0..cap_max_virtual_routers-1. 6967 * Reserved for Spectrum-2. 6968 * Access: RW 6969 */ 6970 MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16); 6971 6972 /* reg_ritr_loopback_ipip_underlay_rif 6973 * Underlay ingress router interface. 6974 * Reserved for Spectrum. 6975 * Access: RW 6976 */ 6977 MLXSW_ITEM32(reg, ritr, loopback_ipip_underlay_rif, 0x14, 0, 16); 6978 6979 /* reg_ritr_loopback_ipip_usip* 6980 * Encapsulation Underlay source IP. 6981 * Access: RW 6982 */ 6983 MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16); 6984 MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32); 6985 6986 /* reg_ritr_loopback_ipip_gre_key 6987 * GRE Key. 6988 * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP. 6989 * Access: RW 6990 */ 6991 MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32); 6992 6993 /* Shared between ingress/egress */ 6994 enum mlxsw_reg_ritr_counter_set_type { 6995 /* No Count. */ 6996 MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0, 6997 /* Basic. Used for router interfaces, counting the following: 6998 * - Error and Discard counters. 6999 * - Unicast, Multicast and Broadcast counters. Sharing the 7000 * same set of counters for the different type of traffic 7001 * (IPv4, IPv6 and mpls). 7002 */ 7003 MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9, 7004 }; 7005 7006 /* reg_ritr_ingress_counter_index 7007 * Counter Index for flow counter. 7008 * Access: RW 7009 */ 7010 MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24); 7011 7012 /* reg_ritr_ingress_counter_set_type 7013 * Igress Counter Set Type for router interface counter. 7014 * Access: RW 7015 */ 7016 MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8); 7017 7018 /* reg_ritr_egress_counter_index 7019 * Counter Index for flow counter. 7020 * Access: RW 7021 */ 7022 MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24); 7023 7024 /* reg_ritr_egress_counter_set_type 7025 * Egress Counter Set Type for router interface counter. 7026 * Access: RW 7027 */ 7028 MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8); 7029 7030 static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index, 7031 bool enable, bool egress) 7032 { 7033 enum mlxsw_reg_ritr_counter_set_type set_type; 7034 7035 if (enable) 7036 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC; 7037 else 7038 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT; 7039 7040 if (egress) { 7041 mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type); 7042 mlxsw_reg_ritr_egress_counter_index_set(payload, index); 7043 } else { 7044 mlxsw_reg_ritr_ingress_counter_set_type_set(payload, set_type); 7045 mlxsw_reg_ritr_ingress_counter_index_set(payload, index); 7046 } 7047 } 7048 7049 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif) 7050 { 7051 MLXSW_REG_ZERO(ritr, payload); 7052 mlxsw_reg_ritr_rif_set(payload, rif); 7053 } 7054 7055 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag, 7056 u16 system_port, u16 efid, u16 vid) 7057 { 7058 mlxsw_reg_ritr_sp_if_lag_set(payload, lag); 7059 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port); 7060 mlxsw_reg_ritr_sp_if_efid_set(payload, efid); 7061 mlxsw_reg_ritr_sp_if_vid_set(payload, vid); 7062 } 7063 7064 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable, 7065 enum mlxsw_reg_ritr_if_type type, 7066 u16 rif, u16 vr_id, u16 mtu) 7067 { 7068 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL; 7069 7070 MLXSW_REG_ZERO(ritr, payload); 7071 mlxsw_reg_ritr_enable_set(payload, enable); 7072 mlxsw_reg_ritr_ipv4_set(payload, 1); 7073 mlxsw_reg_ritr_ipv6_set(payload, 1); 7074 mlxsw_reg_ritr_ipv4_mc_set(payload, 1); 7075 mlxsw_reg_ritr_ipv6_mc_set(payload, 1); 7076 mlxsw_reg_ritr_type_set(payload, type); 7077 mlxsw_reg_ritr_op_set(payload, op); 7078 mlxsw_reg_ritr_rif_set(payload, rif); 7079 mlxsw_reg_ritr_ipv4_fe_set(payload, 1); 7080 mlxsw_reg_ritr_ipv6_fe_set(payload, 1); 7081 mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1); 7082 mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1); 7083 mlxsw_reg_ritr_lb_en_set(payload, 1); 7084 mlxsw_reg_ritr_virtual_router_set(payload, vr_id); 7085 mlxsw_reg_ritr_mtu_set(payload, mtu); 7086 } 7087 7088 static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac) 7089 { 7090 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac); 7091 } 7092 7093 static inline void 7094 mlxsw_reg_ritr_vlan_if_pack(char *payload, bool enable, u16 rif, u16 vr_id, 7095 u16 mtu, const char *mac, u8 mac_profile_id, 7096 u16 vlan_id, u16 efid) 7097 { 7098 enum mlxsw_reg_ritr_if_type type = MLXSW_REG_RITR_VLAN_IF; 7099 7100 mlxsw_reg_ritr_pack(payload, enable, type, rif, vr_id, mtu); 7101 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac); 7102 mlxsw_reg_ritr_if_mac_profile_id_set(payload, mac_profile_id); 7103 mlxsw_reg_ritr_vlan_if_vlan_id_set(payload, vlan_id); 7104 mlxsw_reg_ritr_vlan_if_efid_set(payload, efid); 7105 } 7106 7107 static inline void 7108 mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload, 7109 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 7110 enum mlxsw_reg_ritr_loopback_ipip_options options, 7111 u16 uvr_id, u16 underlay_rif, u32 gre_key) 7112 { 7113 mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type); 7114 mlxsw_reg_ritr_loopback_ipip_options_set(payload, options); 7115 mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id); 7116 mlxsw_reg_ritr_loopback_ipip_underlay_rif_set(payload, underlay_rif); 7117 mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key); 7118 } 7119 7120 static inline void 7121 mlxsw_reg_ritr_loopback_ipip4_pack(char *payload, 7122 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 7123 enum mlxsw_reg_ritr_loopback_ipip_options options, 7124 u16 uvr_id, u16 underlay_rif, u32 usip, u32 gre_key) 7125 { 7126 mlxsw_reg_ritr_loopback_protocol_set(payload, 7127 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4); 7128 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options, 7129 uvr_id, underlay_rif, gre_key); 7130 mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip); 7131 } 7132 7133 static inline void 7134 mlxsw_reg_ritr_loopback_ipip6_pack(char *payload, 7135 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 7136 enum mlxsw_reg_ritr_loopback_ipip_options options, 7137 u16 uvr_id, u16 underlay_rif, 7138 const struct in6_addr *usip, u32 gre_key) 7139 { 7140 enum mlxsw_reg_ritr_loopback_protocol protocol = 7141 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6; 7142 7143 mlxsw_reg_ritr_loopback_protocol_set(payload, protocol); 7144 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options, 7145 uvr_id, underlay_rif, gre_key); 7146 mlxsw_reg_ritr_loopback_ipip_usip6_memcpy_to(payload, 7147 (const char *)usip); 7148 } 7149 7150 /* RTAR - Router TCAM Allocation Register 7151 * -------------------------------------- 7152 * This register is used for allocation of regions in the TCAM table. 7153 */ 7154 #define MLXSW_REG_RTAR_ID 0x8004 7155 #define MLXSW_REG_RTAR_LEN 0x20 7156 7157 MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN); 7158 7159 enum mlxsw_reg_rtar_op { 7160 MLXSW_REG_RTAR_OP_ALLOCATE, 7161 MLXSW_REG_RTAR_OP_RESIZE, 7162 MLXSW_REG_RTAR_OP_DEALLOCATE, 7163 }; 7164 7165 /* reg_rtar_op 7166 * Access: WO 7167 */ 7168 MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4); 7169 7170 enum mlxsw_reg_rtar_key_type { 7171 MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1, 7172 MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3 7173 }; 7174 7175 /* reg_rtar_key_type 7176 * TCAM key type for the region. 7177 * Access: WO 7178 */ 7179 MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8); 7180 7181 /* reg_rtar_region_size 7182 * TCAM region size. When allocating/resizing this is the requested 7183 * size, the response is the actual size. 7184 * Note: Actual size may be larger than requested. 7185 * Reserved for op = Deallocate 7186 * Access: WO 7187 */ 7188 MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16); 7189 7190 static inline void mlxsw_reg_rtar_pack(char *payload, 7191 enum mlxsw_reg_rtar_op op, 7192 enum mlxsw_reg_rtar_key_type key_type, 7193 u16 region_size) 7194 { 7195 MLXSW_REG_ZERO(rtar, payload); 7196 mlxsw_reg_rtar_op_set(payload, op); 7197 mlxsw_reg_rtar_key_type_set(payload, key_type); 7198 mlxsw_reg_rtar_region_size_set(payload, region_size); 7199 } 7200 7201 /* RATR - Router Adjacency Table Register 7202 * -------------------------------------- 7203 * The RATR register is used to configure the Router Adjacency (next-hop) 7204 * Table. 7205 */ 7206 #define MLXSW_REG_RATR_ID 0x8008 7207 #define MLXSW_REG_RATR_LEN 0x2C 7208 7209 MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN); 7210 7211 enum mlxsw_reg_ratr_op { 7212 /* Read */ 7213 MLXSW_REG_RATR_OP_QUERY_READ = 0, 7214 /* Read and clear activity */ 7215 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2, 7216 /* Write Adjacency entry */ 7217 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1, 7218 /* Write Adjacency entry only if the activity is cleared. 7219 * The write may not succeed if the activity is set. There is not 7220 * direct feedback if the write has succeeded or not, however 7221 * the get will reveal the actual entry (SW can compare the get 7222 * response to the set command). 7223 */ 7224 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3, 7225 }; 7226 7227 /* reg_ratr_op 7228 * Note that Write operation may also be used for updating 7229 * counter_set_type and counter_index. In this case all other 7230 * fields must not be updated. 7231 * Access: OP 7232 */ 7233 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4); 7234 7235 /* reg_ratr_v 7236 * Valid bit. Indicates if the adjacency entry is valid. 7237 * Note: the device may need some time before reusing an invalidated 7238 * entry. During this time the entry can not be reused. It is 7239 * recommended to use another entry before reusing an invalidated 7240 * entry (e.g. software can put it at the end of the list for 7241 * reusing). Trying to access an invalidated entry not yet cleared 7242 * by the device results with failure indicating "Try Again" status. 7243 * When valid is '0' then egress_router_interface,trap_action, 7244 * adjacency_parameters and counters are reserved 7245 * Access: RW 7246 */ 7247 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1); 7248 7249 /* reg_ratr_a 7250 * Activity. Set for new entries. Set if a packet lookup has hit on 7251 * the specific entry. To clear the a bit, use "clear activity". 7252 * Access: RO 7253 */ 7254 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1); 7255 7256 enum mlxsw_reg_ratr_type { 7257 /* Ethernet */ 7258 MLXSW_REG_RATR_TYPE_ETHERNET, 7259 /* IPoIB Unicast without GRH. 7260 * Reserved for Spectrum. 7261 */ 7262 MLXSW_REG_RATR_TYPE_IPOIB_UC, 7263 /* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast 7264 * adjacency). 7265 * Reserved for Spectrum. 7266 */ 7267 MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH, 7268 /* IPoIB Multicast. 7269 * Reserved for Spectrum. 7270 */ 7271 MLXSW_REG_RATR_TYPE_IPOIB_MC, 7272 /* MPLS. 7273 * Reserved for SwitchX/-2. 7274 */ 7275 MLXSW_REG_RATR_TYPE_MPLS, 7276 /* IPinIP Encap. 7277 * Reserved for SwitchX/-2. 7278 */ 7279 MLXSW_REG_RATR_TYPE_IPIP, 7280 }; 7281 7282 /* reg_ratr_type 7283 * Adjacency entry type. 7284 * Access: RW 7285 */ 7286 MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4); 7287 7288 /* reg_ratr_adjacency_index_low 7289 * Bits 15:0 of index into the adjacency table. 7290 * For SwitchX and SwitchX-2, the adjacency table is linear and 7291 * used for adjacency entries only. 7292 * For Spectrum, the index is to the KVD linear. 7293 * Access: Index 7294 */ 7295 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16); 7296 7297 /* reg_ratr_egress_router_interface 7298 * Range is 0 .. cap_max_router_interfaces - 1 7299 * Access: RW 7300 */ 7301 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16); 7302 7303 enum mlxsw_reg_ratr_trap_action { 7304 MLXSW_REG_RATR_TRAP_ACTION_NOP, 7305 MLXSW_REG_RATR_TRAP_ACTION_TRAP, 7306 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU, 7307 MLXSW_REG_RATR_TRAP_ACTION_MIRROR, 7308 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS, 7309 }; 7310 7311 /* reg_ratr_trap_action 7312 * see mlxsw_reg_ratr_trap_action 7313 * Access: RW 7314 */ 7315 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4); 7316 7317 /* reg_ratr_adjacency_index_high 7318 * Bits 23:16 of the adjacency_index. 7319 * Access: Index 7320 */ 7321 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8); 7322 7323 enum mlxsw_reg_ratr_trap_id { 7324 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0, 7325 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1, 7326 }; 7327 7328 /* reg_ratr_trap_id 7329 * Trap ID to be reported to CPU. 7330 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 7331 * For trap_action of NOP, MIRROR and DISCARD_ERROR 7332 * Access: RW 7333 */ 7334 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8); 7335 7336 /* reg_ratr_eth_destination_mac 7337 * MAC address of the destination next-hop. 7338 * Access: RW 7339 */ 7340 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6); 7341 7342 enum mlxsw_reg_ratr_ipip_type { 7343 /* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */ 7344 MLXSW_REG_RATR_IPIP_TYPE_IPV4, 7345 /* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */ 7346 MLXSW_REG_RATR_IPIP_TYPE_IPV6, 7347 }; 7348 7349 /* reg_ratr_ipip_type 7350 * Underlay destination ip type. 7351 * Note: the type field must match the protocol of the router interface. 7352 * Access: RW 7353 */ 7354 MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4); 7355 7356 /* reg_ratr_ipip_ipv4_udip 7357 * Underlay ipv4 dip. 7358 * Reserved when ipip_type is IPv6. 7359 * Access: RW 7360 */ 7361 MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32); 7362 7363 /* reg_ratr_ipip_ipv6_ptr 7364 * Pointer to IPv6 underlay destination ip address. 7365 * For Spectrum: Pointer to KVD linear space. 7366 * Access: RW 7367 */ 7368 MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24); 7369 7370 enum mlxsw_reg_flow_counter_set_type { 7371 /* No count */ 7372 MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00, 7373 /* Count packets and bytes */ 7374 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03, 7375 /* Count only packets */ 7376 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05, 7377 }; 7378 7379 /* reg_ratr_counter_set_type 7380 * Counter set type for flow counters 7381 * Access: RW 7382 */ 7383 MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8); 7384 7385 /* reg_ratr_counter_index 7386 * Counter index for flow counters 7387 * Access: RW 7388 */ 7389 MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24); 7390 7391 static inline void 7392 mlxsw_reg_ratr_pack(char *payload, 7393 enum mlxsw_reg_ratr_op op, bool valid, 7394 enum mlxsw_reg_ratr_type type, 7395 u32 adjacency_index, u16 egress_rif) 7396 { 7397 MLXSW_REG_ZERO(ratr, payload); 7398 mlxsw_reg_ratr_op_set(payload, op); 7399 mlxsw_reg_ratr_v_set(payload, valid); 7400 mlxsw_reg_ratr_type_set(payload, type); 7401 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index); 7402 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16); 7403 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif); 7404 } 7405 7406 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload, 7407 const char *dest_mac) 7408 { 7409 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac); 7410 } 7411 7412 static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip) 7413 { 7414 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4); 7415 mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip); 7416 } 7417 7418 static inline void mlxsw_reg_ratr_ipip6_entry_pack(char *payload, u32 ipv6_ptr) 7419 { 7420 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV6); 7421 mlxsw_reg_ratr_ipip_ipv6_ptr_set(payload, ipv6_ptr); 7422 } 7423 7424 static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index, 7425 bool counter_enable) 7426 { 7427 enum mlxsw_reg_flow_counter_set_type set_type; 7428 7429 if (counter_enable) 7430 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES; 7431 else 7432 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT; 7433 7434 mlxsw_reg_ratr_counter_index_set(payload, counter_index); 7435 mlxsw_reg_ratr_counter_set_type_set(payload, set_type); 7436 } 7437 7438 /* RDPM - Router DSCP to Priority Mapping 7439 * -------------------------------------- 7440 * Controls the mapping from DSCP field to switch priority on routed packets 7441 */ 7442 #define MLXSW_REG_RDPM_ID 0x8009 7443 #define MLXSW_REG_RDPM_BASE_LEN 0x00 7444 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01 7445 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64 7446 #define MLXSW_REG_RDPM_LEN 0x40 7447 #define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \ 7448 MLXSW_REG_RDPM_LEN - \ 7449 MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN) 7450 7451 MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN); 7452 7453 /* reg_dscp_entry_e 7454 * Enable update of the specific entry 7455 * Access: Index 7456 */ 7457 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1, 7458 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 7459 7460 /* reg_dscp_entry_prio 7461 * Switch Priority 7462 * Access: RW 7463 */ 7464 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4, 7465 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 7466 7467 static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index, 7468 u8 prio) 7469 { 7470 mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1); 7471 mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio); 7472 } 7473 7474 /* RICNT - Router Interface Counter Register 7475 * ----------------------------------------- 7476 * The RICNT register retrieves per port performance counters 7477 */ 7478 #define MLXSW_REG_RICNT_ID 0x800B 7479 #define MLXSW_REG_RICNT_LEN 0x100 7480 7481 MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN); 7482 7483 /* reg_ricnt_counter_index 7484 * Counter index 7485 * Access: RW 7486 */ 7487 MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24); 7488 7489 enum mlxsw_reg_ricnt_counter_set_type { 7490 /* No Count. */ 7491 MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00, 7492 /* Basic. Used for router interfaces, counting the following: 7493 * - Error and Discard counters. 7494 * - Unicast, Multicast and Broadcast counters. Sharing the 7495 * same set of counters for the different type of traffic 7496 * (IPv4, IPv6 and mpls). 7497 */ 7498 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09, 7499 }; 7500 7501 /* reg_ricnt_counter_set_type 7502 * Counter Set Type for router interface counter 7503 * Access: RW 7504 */ 7505 MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8); 7506 7507 enum mlxsw_reg_ricnt_opcode { 7508 /* Nop. Supported only for read access*/ 7509 MLXSW_REG_RICNT_OPCODE_NOP = 0x00, 7510 /* Clear. Setting the clr bit will reset the counter value for 7511 * all counters of the specified Router Interface. 7512 */ 7513 MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08, 7514 }; 7515 7516 /* reg_ricnt_opcode 7517 * Opcode 7518 * Access: RW 7519 */ 7520 MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4); 7521 7522 /* reg_ricnt_good_unicast_packets 7523 * good unicast packets. 7524 * Access: RW 7525 */ 7526 MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64); 7527 7528 /* reg_ricnt_good_multicast_packets 7529 * good multicast packets. 7530 * Access: RW 7531 */ 7532 MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64); 7533 7534 /* reg_ricnt_good_broadcast_packets 7535 * good broadcast packets 7536 * Access: RW 7537 */ 7538 MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64); 7539 7540 /* reg_ricnt_good_unicast_bytes 7541 * A count of L3 data and padding octets not including L2 headers 7542 * for good unicast frames. 7543 * Access: RW 7544 */ 7545 MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64); 7546 7547 /* reg_ricnt_good_multicast_bytes 7548 * A count of L3 data and padding octets not including L2 headers 7549 * for good multicast frames. 7550 * Access: RW 7551 */ 7552 MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64); 7553 7554 /* reg_ritr_good_broadcast_bytes 7555 * A count of L3 data and padding octets not including L2 headers 7556 * for good broadcast frames. 7557 * Access: RW 7558 */ 7559 MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64); 7560 7561 /* reg_ricnt_error_packets 7562 * A count of errored frames that do not pass the router checks. 7563 * Access: RW 7564 */ 7565 MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64); 7566 7567 /* reg_ricnt_discrad_packets 7568 * A count of non-errored frames that do not pass the router checks. 7569 * Access: RW 7570 */ 7571 MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64); 7572 7573 /* reg_ricnt_error_bytes 7574 * A count of L3 data and padding octets not including L2 headers 7575 * for errored frames. 7576 * Access: RW 7577 */ 7578 MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64); 7579 7580 /* reg_ricnt_discard_bytes 7581 * A count of L3 data and padding octets not including L2 headers 7582 * for non-errored frames that do not pass the router checks. 7583 * Access: RW 7584 */ 7585 MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64); 7586 7587 static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index, 7588 enum mlxsw_reg_ricnt_opcode op) 7589 { 7590 MLXSW_REG_ZERO(ricnt, payload); 7591 mlxsw_reg_ricnt_op_set(payload, op); 7592 mlxsw_reg_ricnt_counter_index_set(payload, index); 7593 mlxsw_reg_ricnt_counter_set_type_set(payload, 7594 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC); 7595 } 7596 7597 /* RRCR - Router Rules Copy Register Layout 7598 * ---------------------------------------- 7599 * This register is used for moving and copying route entry rules. 7600 */ 7601 #define MLXSW_REG_RRCR_ID 0x800F 7602 #define MLXSW_REG_RRCR_LEN 0x24 7603 7604 MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN); 7605 7606 enum mlxsw_reg_rrcr_op { 7607 /* Move rules */ 7608 MLXSW_REG_RRCR_OP_MOVE, 7609 /* Copy rules */ 7610 MLXSW_REG_RRCR_OP_COPY, 7611 }; 7612 7613 /* reg_rrcr_op 7614 * Access: WO 7615 */ 7616 MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4); 7617 7618 /* reg_rrcr_offset 7619 * Offset within the region from which to copy/move. 7620 * Access: Index 7621 */ 7622 MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16); 7623 7624 /* reg_rrcr_size 7625 * The number of rules to copy/move. 7626 * Access: WO 7627 */ 7628 MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16); 7629 7630 /* reg_rrcr_table_id 7631 * Identifier of the table on which to perform the operation. Encoding is the 7632 * same as in RTAR.key_type 7633 * Access: Index 7634 */ 7635 MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4); 7636 7637 /* reg_rrcr_dest_offset 7638 * Offset within the region to which to copy/move 7639 * Access: Index 7640 */ 7641 MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16); 7642 7643 static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op, 7644 u16 offset, u16 size, 7645 enum mlxsw_reg_rtar_key_type table_id, 7646 u16 dest_offset) 7647 { 7648 MLXSW_REG_ZERO(rrcr, payload); 7649 mlxsw_reg_rrcr_op_set(payload, op); 7650 mlxsw_reg_rrcr_offset_set(payload, offset); 7651 mlxsw_reg_rrcr_size_set(payload, size); 7652 mlxsw_reg_rrcr_table_id_set(payload, table_id); 7653 mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset); 7654 } 7655 7656 /* RALTA - Router Algorithmic LPM Tree Allocation Register 7657 * ------------------------------------------------------- 7658 * RALTA is used to allocate the LPM trees of the SHSPM method. 7659 */ 7660 #define MLXSW_REG_RALTA_ID 0x8010 7661 #define MLXSW_REG_RALTA_LEN 0x04 7662 7663 MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN); 7664 7665 /* reg_ralta_op 7666 * opcode (valid for Write, must be 0 on Read) 7667 * 0 - allocate a tree 7668 * 1 - deallocate a tree 7669 * Access: OP 7670 */ 7671 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2); 7672 7673 enum mlxsw_reg_ralxx_protocol { 7674 MLXSW_REG_RALXX_PROTOCOL_IPV4, 7675 MLXSW_REG_RALXX_PROTOCOL_IPV6, 7676 }; 7677 7678 /* reg_ralta_protocol 7679 * Protocol. 7680 * Deallocation opcode: Reserved. 7681 * Access: RW 7682 */ 7683 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4); 7684 7685 /* reg_ralta_tree_id 7686 * An identifier (numbered from 1..cap_shspm_max_trees-1) representing 7687 * the tree identifier (managed by software). 7688 * Note that tree_id 0 is allocated for a default-route tree. 7689 * Access: Index 7690 */ 7691 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8); 7692 7693 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc, 7694 enum mlxsw_reg_ralxx_protocol protocol, 7695 u8 tree_id) 7696 { 7697 MLXSW_REG_ZERO(ralta, payload); 7698 mlxsw_reg_ralta_op_set(payload, !alloc); 7699 mlxsw_reg_ralta_protocol_set(payload, protocol); 7700 mlxsw_reg_ralta_tree_id_set(payload, tree_id); 7701 } 7702 7703 /* RALST - Router Algorithmic LPM Structure Tree Register 7704 * ------------------------------------------------------ 7705 * RALST is used to set and query the structure of an LPM tree. 7706 * The structure of the tree must be sorted as a sorted binary tree, while 7707 * each node is a bin that is tagged as the length of the prefixes the lookup 7708 * will refer to. Therefore, bin X refers to a set of entries with prefixes 7709 * of X bits to match with the destination address. The bin 0 indicates 7710 * the default action, when there is no match of any prefix. 7711 */ 7712 #define MLXSW_REG_RALST_ID 0x8011 7713 #define MLXSW_REG_RALST_LEN 0x104 7714 7715 MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN); 7716 7717 /* reg_ralst_root_bin 7718 * The bin number of the root bin. 7719 * 0<root_bin=<(length of IP address) 7720 * For a default-route tree configure 0xff 7721 * Access: RW 7722 */ 7723 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8); 7724 7725 /* reg_ralst_tree_id 7726 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 7727 * Access: Index 7728 */ 7729 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8); 7730 7731 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff 7732 #define MLXSW_REG_RALST_BIN_OFFSET 0x04 7733 #define MLXSW_REG_RALST_BIN_COUNT 128 7734 7735 /* reg_ralst_left_child_bin 7736 * Holding the children of the bin according to the stored tree's structure. 7737 * For trees composed of less than 4 blocks, the bins in excess are reserved. 7738 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 7739 * Access: RW 7740 */ 7741 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false); 7742 7743 /* reg_ralst_right_child_bin 7744 * Holding the children of the bin according to the stored tree's structure. 7745 * For trees composed of less than 4 blocks, the bins in excess are reserved. 7746 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 7747 * Access: RW 7748 */ 7749 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00, 7750 false); 7751 7752 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id) 7753 { 7754 MLXSW_REG_ZERO(ralst, payload); 7755 7756 /* Initialize all bins to have no left or right child */ 7757 memset(payload + MLXSW_REG_RALST_BIN_OFFSET, 7758 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2); 7759 7760 mlxsw_reg_ralst_root_bin_set(payload, root_bin); 7761 mlxsw_reg_ralst_tree_id_set(payload, tree_id); 7762 } 7763 7764 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number, 7765 u8 left_child_bin, 7766 u8 right_child_bin) 7767 { 7768 int bin_index = bin_number - 1; 7769 7770 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin); 7771 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index, 7772 right_child_bin); 7773 } 7774 7775 /* RALTB - Router Algorithmic LPM Tree Binding Register 7776 * ---------------------------------------------------- 7777 * RALTB is used to bind virtual router and protocol to an allocated LPM tree. 7778 */ 7779 #define MLXSW_REG_RALTB_ID 0x8012 7780 #define MLXSW_REG_RALTB_LEN 0x04 7781 7782 MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN); 7783 7784 /* reg_raltb_virtual_router 7785 * Virtual Router ID 7786 * Range is 0..cap_max_virtual_routers-1 7787 * Access: Index 7788 */ 7789 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16); 7790 7791 /* reg_raltb_protocol 7792 * Protocol. 7793 * Access: Index 7794 */ 7795 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4); 7796 7797 /* reg_raltb_tree_id 7798 * Tree to be used for the {virtual_router, protocol} 7799 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 7800 * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0. 7801 * Access: RW 7802 */ 7803 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8); 7804 7805 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router, 7806 enum mlxsw_reg_ralxx_protocol protocol, 7807 u8 tree_id) 7808 { 7809 MLXSW_REG_ZERO(raltb, payload); 7810 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router); 7811 mlxsw_reg_raltb_protocol_set(payload, protocol); 7812 mlxsw_reg_raltb_tree_id_set(payload, tree_id); 7813 } 7814 7815 /* RALUE - Router Algorithmic LPM Unicast Entry Register 7816 * ----------------------------------------------------- 7817 * RALUE is used to configure and query LPM entries that serve 7818 * the Unicast protocols. 7819 */ 7820 #define MLXSW_REG_RALUE_ID 0x8013 7821 #define MLXSW_REG_RALUE_LEN 0x38 7822 7823 MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN); 7824 7825 /* reg_ralue_protocol 7826 * Protocol. 7827 * Access: Index 7828 */ 7829 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4); 7830 7831 enum mlxsw_reg_ralue_op { 7832 /* Read operation. If entry doesn't exist, the operation fails. */ 7833 MLXSW_REG_RALUE_OP_QUERY_READ = 0, 7834 /* Clear on read operation. Used to read entry and 7835 * clear Activity bit. 7836 */ 7837 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1, 7838 /* Write operation. Used to write a new entry to the table. All RW 7839 * fields are written for new entry. Activity bit is set 7840 * for new entries. 7841 */ 7842 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0, 7843 /* Update operation. Used to update an existing route entry and 7844 * only update the RW fields that are detailed in the field 7845 * op_u_mask. If entry doesn't exist, the operation fails. 7846 */ 7847 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1, 7848 /* Clear activity. The Activity bit (the field a) is cleared 7849 * for the entry. 7850 */ 7851 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2, 7852 /* Delete operation. Used to delete an existing entry. If entry 7853 * doesn't exist, the operation fails. 7854 */ 7855 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3, 7856 }; 7857 7858 /* reg_ralue_op 7859 * Operation. 7860 * Access: OP 7861 */ 7862 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3); 7863 7864 /* reg_ralue_a 7865 * Activity. Set for new entries. Set if a packet lookup has hit on the 7866 * specific entry, only if the entry is a route. To clear the a bit, use 7867 * "clear activity" op. 7868 * Enabled by activity_dis in RGCR 7869 * Access: RO 7870 */ 7871 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1); 7872 7873 /* reg_ralue_virtual_router 7874 * Virtual Router ID 7875 * Range is 0..cap_max_virtual_routers-1 7876 * Access: Index 7877 */ 7878 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16); 7879 7880 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0) 7881 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1) 7882 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2) 7883 7884 /* reg_ralue_op_u_mask 7885 * opcode update mask. 7886 * On read operation, this field is reserved. 7887 * This field is valid for update opcode, otherwise - reserved. 7888 * This field is a bitmask of the fields that should be updated. 7889 * Access: WO 7890 */ 7891 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3); 7892 7893 /* reg_ralue_prefix_len 7894 * Number of bits in the prefix of the LPM route. 7895 * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes 7896 * two entries in the physical HW table. 7897 * Access: Index 7898 */ 7899 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8); 7900 7901 /* reg_ralue_dip* 7902 * The prefix of the route or of the marker that the object of the LPM 7903 * is compared with. The most significant bits of the dip are the prefix. 7904 * The least significant bits must be '0' if the prefix_len is smaller 7905 * than 128 for IPv6 or smaller than 32 for IPv4. 7906 * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved. 7907 * Access: Index 7908 */ 7909 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32); 7910 MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16); 7911 7912 enum mlxsw_reg_ralue_entry_type { 7913 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1, 7914 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2, 7915 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3, 7916 }; 7917 7918 /* reg_ralue_entry_type 7919 * Entry type. 7920 * Note - for Marker entries, the action_type and action fields are reserved. 7921 * Access: RW 7922 */ 7923 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2); 7924 7925 /* reg_ralue_bmp_len 7926 * The best match prefix length in the case that there is no match for 7927 * longer prefixes. 7928 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len 7929 * Note for any update operation with entry_type modification this 7930 * field must be set. 7931 * Access: RW 7932 */ 7933 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8); 7934 7935 enum mlxsw_reg_ralue_action_type { 7936 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE, 7937 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL, 7938 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME, 7939 }; 7940 7941 /* reg_ralue_action_type 7942 * Action Type 7943 * Indicates how the IP address is connected. 7944 * It can be connected to a local subnet through local_erif or can be 7945 * on a remote subnet connected through a next-hop router, 7946 * or transmitted to the CPU. 7947 * Reserved when entry_type = MARKER_ENTRY 7948 * Access: RW 7949 */ 7950 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2); 7951 7952 enum mlxsw_reg_ralue_trap_action { 7953 MLXSW_REG_RALUE_TRAP_ACTION_NOP, 7954 MLXSW_REG_RALUE_TRAP_ACTION_TRAP, 7955 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU, 7956 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR, 7957 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR, 7958 }; 7959 7960 /* reg_ralue_trap_action 7961 * Trap action. 7962 * For IP2ME action, only NOP and MIRROR are possible. 7963 * Access: RW 7964 */ 7965 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4); 7966 7967 /* reg_ralue_trap_id 7968 * Trap ID to be reported to CPU. 7969 * Trap ID is RTR_INGRESS0 or RTR_INGRESS1. 7970 * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved. 7971 * Access: RW 7972 */ 7973 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9); 7974 7975 /* reg_ralue_adjacency_index 7976 * Points to the first entry of the group-based ECMP. 7977 * Only relevant in case of REMOTE action. 7978 * Access: RW 7979 */ 7980 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24); 7981 7982 /* reg_ralue_ecmp_size 7983 * Amount of sequential entries starting 7984 * from the adjacency_index (the number of ECMPs). 7985 * The valid range is 1-64, 512, 1024, 2048 and 4096. 7986 * Reserved when trap_action is TRAP or DISCARD_ERROR. 7987 * Only relevant in case of REMOTE action. 7988 * Access: RW 7989 */ 7990 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13); 7991 7992 /* reg_ralue_local_erif 7993 * Egress Router Interface. 7994 * Only relevant in case of LOCAL action. 7995 * Access: RW 7996 */ 7997 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16); 7998 7999 /* reg_ralue_ip2me_v 8000 * Valid bit for the tunnel_ptr field. 8001 * If valid = 0 then trap to CPU as IP2ME trap ID. 8002 * If valid = 1 and the packet format allows NVE or IPinIP tunnel 8003 * decapsulation then tunnel decapsulation is done. 8004 * If valid = 1 and packet format does not allow NVE or IPinIP tunnel 8005 * decapsulation then trap as IP2ME trap ID. 8006 * Only relevant in case of IP2ME action. 8007 * Access: RW 8008 */ 8009 MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1); 8010 8011 /* reg_ralue_ip2me_tunnel_ptr 8012 * Tunnel Pointer for NVE or IPinIP tunnel decapsulation. 8013 * For Spectrum, pointer to KVD Linear. 8014 * Only relevant in case of IP2ME action. 8015 * Access: RW 8016 */ 8017 MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24); 8018 8019 static inline void mlxsw_reg_ralue_pack(char *payload, 8020 enum mlxsw_reg_ralxx_protocol protocol, 8021 enum mlxsw_reg_ralue_op op, 8022 u16 virtual_router, u8 prefix_len) 8023 { 8024 MLXSW_REG_ZERO(ralue, payload); 8025 mlxsw_reg_ralue_protocol_set(payload, protocol); 8026 mlxsw_reg_ralue_op_set(payload, op); 8027 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router); 8028 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len); 8029 mlxsw_reg_ralue_entry_type_set(payload, 8030 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY); 8031 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len); 8032 } 8033 8034 static inline void mlxsw_reg_ralue_pack4(char *payload, 8035 enum mlxsw_reg_ralxx_protocol protocol, 8036 enum mlxsw_reg_ralue_op op, 8037 u16 virtual_router, u8 prefix_len, 8038 u32 dip) 8039 { 8040 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 8041 mlxsw_reg_ralue_dip4_set(payload, dip); 8042 } 8043 8044 static inline void mlxsw_reg_ralue_pack6(char *payload, 8045 enum mlxsw_reg_ralxx_protocol protocol, 8046 enum mlxsw_reg_ralue_op op, 8047 u16 virtual_router, u8 prefix_len, 8048 const void *dip) 8049 { 8050 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 8051 mlxsw_reg_ralue_dip6_memcpy_to(payload, dip); 8052 } 8053 8054 static inline void 8055 mlxsw_reg_ralue_act_remote_pack(char *payload, 8056 enum mlxsw_reg_ralue_trap_action trap_action, 8057 u16 trap_id, u32 adjacency_index, u16 ecmp_size) 8058 { 8059 mlxsw_reg_ralue_action_type_set(payload, 8060 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE); 8061 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 8062 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 8063 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index); 8064 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size); 8065 } 8066 8067 static inline void 8068 mlxsw_reg_ralue_act_local_pack(char *payload, 8069 enum mlxsw_reg_ralue_trap_action trap_action, 8070 u16 trap_id, u16 local_erif) 8071 { 8072 mlxsw_reg_ralue_action_type_set(payload, 8073 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL); 8074 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 8075 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 8076 mlxsw_reg_ralue_local_erif_set(payload, local_erif); 8077 } 8078 8079 static inline void 8080 mlxsw_reg_ralue_act_ip2me_pack(char *payload) 8081 { 8082 mlxsw_reg_ralue_action_type_set(payload, 8083 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 8084 } 8085 8086 static inline void 8087 mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr) 8088 { 8089 mlxsw_reg_ralue_action_type_set(payload, 8090 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 8091 mlxsw_reg_ralue_ip2me_v_set(payload, 1); 8092 mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr); 8093 } 8094 8095 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register 8096 * ---------------------------------------------------------- 8097 * The RAUHT register is used to configure and query the Unicast Host table in 8098 * devices that implement the Algorithmic LPM. 8099 */ 8100 #define MLXSW_REG_RAUHT_ID 0x8014 8101 #define MLXSW_REG_RAUHT_LEN 0x74 8102 8103 MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN); 8104 8105 enum mlxsw_reg_rauht_type { 8106 MLXSW_REG_RAUHT_TYPE_IPV4, 8107 MLXSW_REG_RAUHT_TYPE_IPV6, 8108 }; 8109 8110 /* reg_rauht_type 8111 * Access: Index 8112 */ 8113 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2); 8114 8115 enum mlxsw_reg_rauht_op { 8116 MLXSW_REG_RAUHT_OP_QUERY_READ = 0, 8117 /* Read operation */ 8118 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1, 8119 /* Clear on read operation. Used to read entry and clear 8120 * activity bit. 8121 */ 8122 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0, 8123 /* Add. Used to write a new entry to the table. All R/W fields are 8124 * relevant for new entry. Activity bit is set for new entries. 8125 */ 8126 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1, 8127 /* Update action. Used to update an existing route entry and 8128 * only update the following fields: 8129 * trap_action, trap_id, mac, counter_set_type, counter_index 8130 */ 8131 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2, 8132 /* Clear activity. A bit is cleared for the entry. */ 8133 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3, 8134 /* Delete entry */ 8135 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4, 8136 /* Delete all host entries on a RIF. In this command, dip 8137 * field is reserved. 8138 */ 8139 }; 8140 8141 /* reg_rauht_op 8142 * Access: OP 8143 */ 8144 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3); 8145 8146 /* reg_rauht_a 8147 * Activity. Set for new entries. Set if a packet lookup has hit on 8148 * the specific entry. 8149 * To clear the a bit, use "clear activity" op. 8150 * Enabled by activity_dis in RGCR 8151 * Access: RO 8152 */ 8153 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1); 8154 8155 /* reg_rauht_rif 8156 * Router Interface 8157 * Access: Index 8158 */ 8159 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16); 8160 8161 /* reg_rauht_dip* 8162 * Destination address. 8163 * Access: Index 8164 */ 8165 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32); 8166 MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16); 8167 8168 enum mlxsw_reg_rauht_trap_action { 8169 MLXSW_REG_RAUHT_TRAP_ACTION_NOP, 8170 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP, 8171 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU, 8172 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR, 8173 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS, 8174 }; 8175 8176 /* reg_rauht_trap_action 8177 * Access: RW 8178 */ 8179 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4); 8180 8181 enum mlxsw_reg_rauht_trap_id { 8182 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0, 8183 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1, 8184 }; 8185 8186 /* reg_rauht_trap_id 8187 * Trap ID to be reported to CPU. 8188 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 8189 * For trap_action of NOP, MIRROR and DISCARD_ERROR, 8190 * trap_id is reserved. 8191 * Access: RW 8192 */ 8193 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9); 8194 8195 /* reg_rauht_counter_set_type 8196 * Counter set type for flow counters 8197 * Access: RW 8198 */ 8199 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8); 8200 8201 /* reg_rauht_counter_index 8202 * Counter index for flow counters 8203 * Access: RW 8204 */ 8205 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24); 8206 8207 /* reg_rauht_mac 8208 * MAC address. 8209 * Access: RW 8210 */ 8211 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6); 8212 8213 static inline void mlxsw_reg_rauht_pack(char *payload, 8214 enum mlxsw_reg_rauht_op op, u16 rif, 8215 const char *mac) 8216 { 8217 MLXSW_REG_ZERO(rauht, payload); 8218 mlxsw_reg_rauht_op_set(payload, op); 8219 mlxsw_reg_rauht_rif_set(payload, rif); 8220 mlxsw_reg_rauht_mac_memcpy_to(payload, mac); 8221 } 8222 8223 static inline void mlxsw_reg_rauht_pack4(char *payload, 8224 enum mlxsw_reg_rauht_op op, u16 rif, 8225 const char *mac, u32 dip) 8226 { 8227 mlxsw_reg_rauht_pack(payload, op, rif, mac); 8228 mlxsw_reg_rauht_dip4_set(payload, dip); 8229 } 8230 8231 static inline void mlxsw_reg_rauht_pack6(char *payload, 8232 enum mlxsw_reg_rauht_op op, u16 rif, 8233 const char *mac, const char *dip) 8234 { 8235 mlxsw_reg_rauht_pack(payload, op, rif, mac); 8236 mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6); 8237 mlxsw_reg_rauht_dip6_memcpy_to(payload, dip); 8238 } 8239 8240 static inline void mlxsw_reg_rauht_pack_counter(char *payload, 8241 u64 counter_index) 8242 { 8243 mlxsw_reg_rauht_counter_index_set(payload, counter_index); 8244 mlxsw_reg_rauht_counter_set_type_set(payload, 8245 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 8246 } 8247 8248 /* RALEU - Router Algorithmic LPM ECMP Update Register 8249 * --------------------------------------------------- 8250 * The register enables updating the ECMP section in the action for multiple 8251 * LPM Unicast entries in a single operation. The update is executed to 8252 * all entries of a {virtual router, protocol} tuple using the same ECMP group. 8253 */ 8254 #define MLXSW_REG_RALEU_ID 0x8015 8255 #define MLXSW_REG_RALEU_LEN 0x28 8256 8257 MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN); 8258 8259 /* reg_raleu_protocol 8260 * Protocol. 8261 * Access: Index 8262 */ 8263 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4); 8264 8265 /* reg_raleu_virtual_router 8266 * Virtual Router ID 8267 * Range is 0..cap_max_virtual_routers-1 8268 * Access: Index 8269 */ 8270 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16); 8271 8272 /* reg_raleu_adjacency_index 8273 * Adjacency Index used for matching on the existing entries. 8274 * Access: Index 8275 */ 8276 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24); 8277 8278 /* reg_raleu_ecmp_size 8279 * ECMP Size used for matching on the existing entries. 8280 * Access: Index 8281 */ 8282 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13); 8283 8284 /* reg_raleu_new_adjacency_index 8285 * New Adjacency Index. 8286 * Access: WO 8287 */ 8288 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24); 8289 8290 /* reg_raleu_new_ecmp_size 8291 * New ECMP Size. 8292 * Access: WO 8293 */ 8294 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13); 8295 8296 static inline void mlxsw_reg_raleu_pack(char *payload, 8297 enum mlxsw_reg_ralxx_protocol protocol, 8298 u16 virtual_router, 8299 u32 adjacency_index, u16 ecmp_size, 8300 u32 new_adjacency_index, 8301 u16 new_ecmp_size) 8302 { 8303 MLXSW_REG_ZERO(raleu, payload); 8304 mlxsw_reg_raleu_protocol_set(payload, protocol); 8305 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router); 8306 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index); 8307 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size); 8308 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index); 8309 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size); 8310 } 8311 8312 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register 8313 * ---------------------------------------------------------------- 8314 * The RAUHTD register allows dumping entries from the Router Unicast Host 8315 * Table. For a given session an entry is dumped no more than one time. The 8316 * first RAUHTD access after reset is a new session. A session ends when the 8317 * num_rec response is smaller than num_rec request or for IPv4 when the 8318 * num_entries is smaller than 4. The clear activity affect the current session 8319 * or the last session if a new session has not started. 8320 */ 8321 #define MLXSW_REG_RAUHTD_ID 0x8018 8322 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20 8323 #define MLXSW_REG_RAUHTD_REC_LEN 0x20 8324 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32 8325 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \ 8326 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN) 8327 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4 8328 8329 MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN); 8330 8331 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0) 8332 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3) 8333 8334 /* reg_rauhtd_filter_fields 8335 * if a bit is '0' then the relevant field is ignored and dump is done 8336 * regardless of the field value 8337 * Bit0 - filter by activity: entry_a 8338 * Bit3 - filter by entry rip: entry_rif 8339 * Access: Index 8340 */ 8341 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8); 8342 8343 enum mlxsw_reg_rauhtd_op { 8344 MLXSW_REG_RAUHTD_OP_DUMP, 8345 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR, 8346 }; 8347 8348 /* reg_rauhtd_op 8349 * Access: OP 8350 */ 8351 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2); 8352 8353 /* reg_rauhtd_num_rec 8354 * At request: number of records requested 8355 * At response: number of records dumped 8356 * For IPv4, each record has 4 entries at request and up to 4 entries 8357 * at response 8358 * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM 8359 * Access: Index 8360 */ 8361 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8); 8362 8363 /* reg_rauhtd_entry_a 8364 * Dump only if activity has value of entry_a 8365 * Reserved if filter_fields bit0 is '0' 8366 * Access: Index 8367 */ 8368 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1); 8369 8370 enum mlxsw_reg_rauhtd_type { 8371 MLXSW_REG_RAUHTD_TYPE_IPV4, 8372 MLXSW_REG_RAUHTD_TYPE_IPV6, 8373 }; 8374 8375 /* reg_rauhtd_type 8376 * Dump only if record type is: 8377 * 0 - IPv4 8378 * 1 - IPv6 8379 * Access: Index 8380 */ 8381 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4); 8382 8383 /* reg_rauhtd_entry_rif 8384 * Dump only if RIF has value of entry_rif 8385 * Reserved if filter_fields bit3 is '0' 8386 * Access: Index 8387 */ 8388 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16); 8389 8390 static inline void mlxsw_reg_rauhtd_pack(char *payload, 8391 enum mlxsw_reg_rauhtd_type type) 8392 { 8393 MLXSW_REG_ZERO(rauhtd, payload); 8394 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A); 8395 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR); 8396 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM); 8397 mlxsw_reg_rauhtd_entry_a_set(payload, 1); 8398 mlxsw_reg_rauhtd_type_set(payload, type); 8399 } 8400 8401 /* reg_rauhtd_ipv4_rec_num_entries 8402 * Number of valid entries in this record: 8403 * 0 - 1 valid entry 8404 * 1 - 2 valid entries 8405 * 2 - 3 valid entries 8406 * 3 - 4 valid entries 8407 * Access: RO 8408 */ 8409 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries, 8410 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2, 8411 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 8412 8413 /* reg_rauhtd_rec_type 8414 * Record type. 8415 * 0 - IPv4 8416 * 1 - IPv6 8417 * Access: RO 8418 */ 8419 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2, 8420 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 8421 8422 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8 8423 8424 /* reg_rauhtd_ipv4_ent_a 8425 * Activity. Set for new entries. Set if a packet lookup has hit on the 8426 * specific entry. 8427 * Access: RO 8428 */ 8429 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 8430 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 8431 8432 /* reg_rauhtd_ipv4_ent_rif 8433 * Router interface. 8434 * Access: RO 8435 */ 8436 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 8437 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 8438 8439 /* reg_rauhtd_ipv4_ent_dip 8440 * Destination IPv4 address. 8441 * Access: RO 8442 */ 8443 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0, 8444 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false); 8445 8446 #define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20 8447 8448 /* reg_rauhtd_ipv6_ent_a 8449 * Activity. Set for new entries. Set if a packet lookup has hit on the 8450 * specific entry. 8451 * Access: RO 8452 */ 8453 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 8454 MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 8455 8456 /* reg_rauhtd_ipv6_ent_rif 8457 * Router interface. 8458 * Access: RO 8459 */ 8460 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 8461 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 8462 8463 /* reg_rauhtd_ipv6_ent_dip 8464 * Destination IPv6 address. 8465 * Access: RO 8466 */ 8467 MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 8468 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10); 8469 8470 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload, 8471 int ent_index, u16 *p_rif, 8472 u32 *p_dip) 8473 { 8474 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index); 8475 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index); 8476 } 8477 8478 static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload, 8479 int rec_index, u16 *p_rif, 8480 char *p_dip) 8481 { 8482 *p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index); 8483 mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip); 8484 } 8485 8486 /* RTDP - Routing Tunnel Decap Properties Register 8487 * ----------------------------------------------- 8488 * The RTDP register is used for configuring the tunnel decap properties of NVE 8489 * and IPinIP. 8490 */ 8491 #define MLXSW_REG_RTDP_ID 0x8020 8492 #define MLXSW_REG_RTDP_LEN 0x44 8493 8494 MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN); 8495 8496 enum mlxsw_reg_rtdp_type { 8497 MLXSW_REG_RTDP_TYPE_NVE, 8498 MLXSW_REG_RTDP_TYPE_IPIP, 8499 }; 8500 8501 /* reg_rtdp_type 8502 * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type. 8503 * Access: RW 8504 */ 8505 MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4); 8506 8507 /* reg_rtdp_tunnel_index 8508 * Index to the Decap entry. 8509 * For Spectrum, Index to KVD Linear. 8510 * Access: Index 8511 */ 8512 MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24); 8513 8514 /* reg_rtdp_egress_router_interface 8515 * Underlay egress router interface. 8516 * Valid range is from 0 to cap_max_router_interfaces - 1 8517 * Access: RW 8518 */ 8519 MLXSW_ITEM32(reg, rtdp, egress_router_interface, 0x40, 0, 16); 8520 8521 /* IPinIP */ 8522 8523 /* reg_rtdp_ipip_irif 8524 * Ingress Router Interface for the overlay router 8525 * Access: RW 8526 */ 8527 MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16); 8528 8529 enum mlxsw_reg_rtdp_ipip_sip_check { 8530 /* No sip checks. */ 8531 MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO, 8532 /* Filter packet if underlay is not IPv4 or if underlay SIP does not 8533 * equal ipv4_usip. 8534 */ 8535 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4, 8536 /* Filter packet if underlay is not IPv6 or if underlay SIP does not 8537 * equal ipv6_usip. 8538 */ 8539 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3, 8540 }; 8541 8542 /* reg_rtdp_ipip_sip_check 8543 * SIP check to perform. If decapsulation failed due to these configurations 8544 * then trap_id is IPIP_DECAP_ERROR. 8545 * Access: RW 8546 */ 8547 MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3); 8548 8549 /* If set, allow decapsulation of IPinIP (without GRE). */ 8550 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP BIT(0) 8551 /* If set, allow decapsulation of IPinGREinIP without a key. */ 8552 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE BIT(1) 8553 /* If set, allow decapsulation of IPinGREinIP with a key. */ 8554 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY BIT(2) 8555 8556 /* reg_rtdp_ipip_type_check 8557 * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to 8558 * these configurations then trap_id is IPIP_DECAP_ERROR. 8559 * Access: RW 8560 */ 8561 MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3); 8562 8563 /* reg_rtdp_ipip_gre_key_check 8564 * Whether GRE key should be checked. When check is enabled: 8565 * - A packet received as IPinIP (without GRE) will always pass. 8566 * - A packet received as IPinGREinIP without a key will not pass the check. 8567 * - A packet received as IPinGREinIP with a key will pass the check only if the 8568 * key in the packet is equal to expected_gre_key. 8569 * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR. 8570 * Access: RW 8571 */ 8572 MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1); 8573 8574 /* reg_rtdp_ipip_ipv4_usip 8575 * Underlay IPv4 address for ipv4 source address check. 8576 * Reserved when sip_check is not '1'. 8577 * Access: RW 8578 */ 8579 MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32); 8580 8581 /* reg_rtdp_ipip_ipv6_usip_ptr 8582 * This field is valid when sip_check is "sipv6 check explicitly". This is a 8583 * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index 8584 * is to the KVD linear. 8585 * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6. 8586 * Access: RW 8587 */ 8588 MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24); 8589 8590 /* reg_rtdp_ipip_expected_gre_key 8591 * GRE key for checking. 8592 * Reserved when gre_key_check is '0'. 8593 * Access: RW 8594 */ 8595 MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32); 8596 8597 static inline void mlxsw_reg_rtdp_pack(char *payload, 8598 enum mlxsw_reg_rtdp_type type, 8599 u32 tunnel_index) 8600 { 8601 MLXSW_REG_ZERO(rtdp, payload); 8602 mlxsw_reg_rtdp_type_set(payload, type); 8603 mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index); 8604 } 8605 8606 static inline void 8607 mlxsw_reg_rtdp_ipip_pack(char *payload, u16 irif, 8608 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 8609 unsigned int type_check, bool gre_key_check, 8610 u32 expected_gre_key) 8611 { 8612 mlxsw_reg_rtdp_ipip_irif_set(payload, irif); 8613 mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check); 8614 mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check); 8615 mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check); 8616 mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key); 8617 } 8618 8619 static inline void 8620 mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif, 8621 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 8622 unsigned int type_check, bool gre_key_check, 8623 u32 ipv4_usip, u32 expected_gre_key) 8624 { 8625 mlxsw_reg_rtdp_ipip_pack(payload, irif, sip_check, type_check, 8626 gre_key_check, expected_gre_key); 8627 mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip); 8628 } 8629 8630 static inline void 8631 mlxsw_reg_rtdp_ipip6_pack(char *payload, u16 irif, 8632 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 8633 unsigned int type_check, bool gre_key_check, 8634 u32 ipv6_usip_ptr, u32 expected_gre_key) 8635 { 8636 mlxsw_reg_rtdp_ipip_pack(payload, irif, sip_check, type_check, 8637 gre_key_check, expected_gre_key); 8638 mlxsw_reg_rtdp_ipip_ipv6_usip_ptr_set(payload, ipv6_usip_ptr); 8639 } 8640 8641 /* RIPS - Router IP version Six Register 8642 * ------------------------------------- 8643 * The RIPS register is used to store IPv6 addresses for use by the NVE and 8644 * IPinIP 8645 */ 8646 #define MLXSW_REG_RIPS_ID 0x8021 8647 #define MLXSW_REG_RIPS_LEN 0x14 8648 8649 MLXSW_REG_DEFINE(rips, MLXSW_REG_RIPS_ID, MLXSW_REG_RIPS_LEN); 8650 8651 /* reg_rips_index 8652 * Index to IPv6 address. 8653 * For Spectrum, the index is to the KVD linear. 8654 * Access: Index 8655 */ 8656 MLXSW_ITEM32(reg, rips, index, 0x00, 0, 24); 8657 8658 /* reg_rips_ipv6 8659 * IPv6 address 8660 * Access: RW 8661 */ 8662 MLXSW_ITEM_BUF(reg, rips, ipv6, 0x04, 16); 8663 8664 static inline void mlxsw_reg_rips_pack(char *payload, u32 index, 8665 const struct in6_addr *ipv6) 8666 { 8667 MLXSW_REG_ZERO(rips, payload); 8668 mlxsw_reg_rips_index_set(payload, index); 8669 mlxsw_reg_rips_ipv6_memcpy_to(payload, (const char *)ipv6); 8670 } 8671 8672 /* RATRAD - Router Adjacency Table Activity Dump Register 8673 * ------------------------------------------------------ 8674 * The RATRAD register is used to dump and optionally clear activity bits of 8675 * router adjacency table entries. 8676 */ 8677 #define MLXSW_REG_RATRAD_ID 0x8022 8678 #define MLXSW_REG_RATRAD_LEN 0x210 8679 8680 MLXSW_REG_DEFINE(ratrad, MLXSW_REG_RATRAD_ID, MLXSW_REG_RATRAD_LEN); 8681 8682 enum { 8683 /* Read activity */ 8684 MLXSW_REG_RATRAD_OP_READ_ACTIVITY, 8685 /* Read and clear activity */ 8686 MLXSW_REG_RATRAD_OP_READ_CLEAR_ACTIVITY, 8687 }; 8688 8689 /* reg_ratrad_op 8690 * Access: Operation 8691 */ 8692 MLXSW_ITEM32(reg, ratrad, op, 0x00, 30, 2); 8693 8694 /* reg_ratrad_ecmp_size 8695 * ecmp_size is the amount of sequential entries from adjacency_index. Valid 8696 * ranges: 8697 * Spectrum-1: 32-64, 512, 1024, 2048, 4096 8698 * Spectrum-2/3: 32-128, 256, 512, 1024, 2048, 4096 8699 * Access: Index 8700 */ 8701 MLXSW_ITEM32(reg, ratrad, ecmp_size, 0x00, 0, 13); 8702 8703 /* reg_ratrad_adjacency_index 8704 * Index into the adjacency table. 8705 * Access: Index 8706 */ 8707 MLXSW_ITEM32(reg, ratrad, adjacency_index, 0x04, 0, 24); 8708 8709 /* reg_ratrad_activity_vector 8710 * Activity bit per adjacency index. 8711 * Bits higher than ecmp_size are reserved. 8712 * Access: RO 8713 */ 8714 MLXSW_ITEM_BIT_ARRAY(reg, ratrad, activity_vector, 0x10, 0x200, 1); 8715 8716 static inline void mlxsw_reg_ratrad_pack(char *payload, u32 adjacency_index, 8717 u16 ecmp_size) 8718 { 8719 MLXSW_REG_ZERO(ratrad, payload); 8720 mlxsw_reg_ratrad_op_set(payload, 8721 MLXSW_REG_RATRAD_OP_READ_CLEAR_ACTIVITY); 8722 mlxsw_reg_ratrad_ecmp_size_set(payload, ecmp_size); 8723 mlxsw_reg_ratrad_adjacency_index_set(payload, adjacency_index); 8724 } 8725 8726 /* RIGR-V2 - Router Interface Group Register Version 2 8727 * --------------------------------------------------- 8728 * The RIGR_V2 register is used to add, remove and query egress interface list 8729 * of a multicast forwarding entry. 8730 */ 8731 #define MLXSW_REG_RIGR2_ID 0x8023 8732 #define MLXSW_REG_RIGR2_LEN 0xB0 8733 8734 #define MLXSW_REG_RIGR2_MAX_ERIFS 32 8735 8736 MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN); 8737 8738 /* reg_rigr2_rigr_index 8739 * KVD Linear index. 8740 * Access: Index 8741 */ 8742 MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24); 8743 8744 /* reg_rigr2_vnext 8745 * Next RIGR Index is valid. 8746 * Access: RW 8747 */ 8748 MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1); 8749 8750 /* reg_rigr2_next_rigr_index 8751 * Next RIGR Index. The index is to the KVD linear. 8752 * Reserved when vnxet = '0'. 8753 * Access: RW 8754 */ 8755 MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24); 8756 8757 /* reg_rigr2_vrmid 8758 * RMID Index is valid. 8759 * Access: RW 8760 */ 8761 MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1); 8762 8763 /* reg_rigr2_rmid_index 8764 * RMID Index. 8765 * Range 0 .. max_mid - 1 8766 * Reserved when vrmid = '0'. 8767 * The index is to the Port Group Table (PGT) 8768 * Access: RW 8769 */ 8770 MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16); 8771 8772 /* reg_rigr2_erif_entry_v 8773 * Egress Router Interface is valid. 8774 * Note that low-entries must be set if high-entries are set. For 8775 * example: if erif_entry[2].v is set then erif_entry[1].v and 8776 * erif_entry[0].v must be set. 8777 * Index can be from 0 to cap_mc_erif_list_entries-1 8778 * Access: RW 8779 */ 8780 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false); 8781 8782 /* reg_rigr2_erif_entry_erif 8783 * Egress Router Interface. 8784 * Valid range is from 0 to cap_max_router_interfaces - 1 8785 * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1 8786 * Access: RW 8787 */ 8788 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false); 8789 8790 static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index, 8791 bool vnext, u32 next_rigr_index) 8792 { 8793 MLXSW_REG_ZERO(rigr2, payload); 8794 mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index); 8795 mlxsw_reg_rigr2_vnext_set(payload, vnext); 8796 mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index); 8797 mlxsw_reg_rigr2_vrmid_set(payload, 0); 8798 mlxsw_reg_rigr2_rmid_index_set(payload, 0); 8799 } 8800 8801 static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index, 8802 bool v, u16 erif) 8803 { 8804 mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v); 8805 mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif); 8806 } 8807 8808 /* RECR-V2 - Router ECMP Configuration Version 2 Register 8809 * ------------------------------------------------------ 8810 */ 8811 #define MLXSW_REG_RECR2_ID 0x8025 8812 #define MLXSW_REG_RECR2_LEN 0x38 8813 8814 MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN); 8815 8816 /* reg_recr2_pp 8817 * Per-port configuration 8818 * Access: Index 8819 */ 8820 MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1); 8821 8822 /* reg_recr2_sh 8823 * Symmetric hash 8824 * Access: RW 8825 */ 8826 MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1); 8827 8828 /* reg_recr2_seed 8829 * Seed 8830 * Access: RW 8831 */ 8832 MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32); 8833 8834 enum { 8835 /* Enable IPv4 fields if packet is not TCP and not UDP */ 8836 MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP = 3, 8837 /* Enable IPv4 fields if packet is TCP or UDP */ 8838 MLXSW_REG_RECR2_IPV4_EN_TCP_UDP = 4, 8839 /* Enable IPv6 fields if packet is not TCP and not UDP */ 8840 MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP = 5, 8841 /* Enable IPv6 fields if packet is TCP or UDP */ 8842 MLXSW_REG_RECR2_IPV6_EN_TCP_UDP = 6, 8843 /* Enable TCP/UDP header fields if packet is IPv4 */ 8844 MLXSW_REG_RECR2_TCP_UDP_EN_IPV4 = 7, 8845 /* Enable TCP/UDP header fields if packet is IPv6 */ 8846 MLXSW_REG_RECR2_TCP_UDP_EN_IPV6 = 8, 8847 8848 __MLXSW_REG_RECR2_HEADER_CNT, 8849 }; 8850 8851 /* reg_recr2_outer_header_enables 8852 * Bit mask where each bit enables a specific layer to be included in 8853 * the hash calculation. 8854 * Access: RW 8855 */ 8856 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1); 8857 8858 enum { 8859 /* IPv4 Source IP */ 8860 MLXSW_REG_RECR2_IPV4_SIP0 = 9, 8861 MLXSW_REG_RECR2_IPV4_SIP3 = 12, 8862 /* IPv4 Destination IP */ 8863 MLXSW_REG_RECR2_IPV4_DIP0 = 13, 8864 MLXSW_REG_RECR2_IPV4_DIP3 = 16, 8865 /* IP Protocol */ 8866 MLXSW_REG_RECR2_IPV4_PROTOCOL = 17, 8867 /* IPv6 Source IP */ 8868 MLXSW_REG_RECR2_IPV6_SIP0_7 = 21, 8869 MLXSW_REG_RECR2_IPV6_SIP8 = 29, 8870 MLXSW_REG_RECR2_IPV6_SIP15 = 36, 8871 /* IPv6 Destination IP */ 8872 MLXSW_REG_RECR2_IPV6_DIP0_7 = 37, 8873 MLXSW_REG_RECR2_IPV6_DIP8 = 45, 8874 MLXSW_REG_RECR2_IPV6_DIP15 = 52, 8875 /* IPv6 Next Header */ 8876 MLXSW_REG_RECR2_IPV6_NEXT_HEADER = 53, 8877 /* IPv6 Flow Label */ 8878 MLXSW_REG_RECR2_IPV6_FLOW_LABEL = 57, 8879 /* TCP/UDP Source Port */ 8880 MLXSW_REG_RECR2_TCP_UDP_SPORT = 74, 8881 /* TCP/UDP Destination Port */ 8882 MLXSW_REG_RECR2_TCP_UDP_DPORT = 75, 8883 8884 __MLXSW_REG_RECR2_FIELD_CNT, 8885 }; 8886 8887 /* reg_recr2_outer_header_fields_enable 8888 * Packet fields to enable for ECMP hash subject to outer_header_enable. 8889 * Access: RW 8890 */ 8891 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1); 8892 8893 /* reg_recr2_inner_header_enables 8894 * Bit mask where each bit enables a specific inner layer to be included in the 8895 * hash calculation. Same values as reg_recr2_outer_header_enables. 8896 * Access: RW 8897 */ 8898 MLXSW_ITEM_BIT_ARRAY(reg, recr2, inner_header_enables, 0x2C, 0x04, 1); 8899 8900 enum { 8901 /* Inner IPv4 Source IP */ 8902 MLXSW_REG_RECR2_INNER_IPV4_SIP0 = 3, 8903 MLXSW_REG_RECR2_INNER_IPV4_SIP3 = 6, 8904 /* Inner IPv4 Destination IP */ 8905 MLXSW_REG_RECR2_INNER_IPV4_DIP0 = 7, 8906 MLXSW_REG_RECR2_INNER_IPV4_DIP3 = 10, 8907 /* Inner IP Protocol */ 8908 MLXSW_REG_RECR2_INNER_IPV4_PROTOCOL = 11, 8909 /* Inner IPv6 Source IP */ 8910 MLXSW_REG_RECR2_INNER_IPV6_SIP0_7 = 12, 8911 MLXSW_REG_RECR2_INNER_IPV6_SIP8 = 20, 8912 MLXSW_REG_RECR2_INNER_IPV6_SIP15 = 27, 8913 /* Inner IPv6 Destination IP */ 8914 MLXSW_REG_RECR2_INNER_IPV6_DIP0_7 = 28, 8915 MLXSW_REG_RECR2_INNER_IPV6_DIP8 = 36, 8916 MLXSW_REG_RECR2_INNER_IPV6_DIP15 = 43, 8917 /* Inner IPv6 Next Header */ 8918 MLXSW_REG_RECR2_INNER_IPV6_NEXT_HEADER = 44, 8919 /* Inner IPv6 Flow Label */ 8920 MLXSW_REG_RECR2_INNER_IPV6_FLOW_LABEL = 45, 8921 /* Inner TCP/UDP Source Port */ 8922 MLXSW_REG_RECR2_INNER_TCP_UDP_SPORT = 46, 8923 /* Inner TCP/UDP Destination Port */ 8924 MLXSW_REG_RECR2_INNER_TCP_UDP_DPORT = 47, 8925 8926 __MLXSW_REG_RECR2_INNER_FIELD_CNT, 8927 }; 8928 8929 /* reg_recr2_inner_header_fields_enable 8930 * Inner packet fields to enable for ECMP hash subject to inner_header_enables. 8931 * Access: RW 8932 */ 8933 MLXSW_ITEM_BIT_ARRAY(reg, recr2, inner_header_fields_enable, 0x30, 0x08, 1); 8934 8935 static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed) 8936 { 8937 MLXSW_REG_ZERO(recr2, payload); 8938 mlxsw_reg_recr2_pp_set(payload, false); 8939 mlxsw_reg_recr2_sh_set(payload, true); 8940 mlxsw_reg_recr2_seed_set(payload, seed); 8941 } 8942 8943 /* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register 8944 * -------------------------------------------------------------- 8945 * The RMFT_V2 register is used to configure and query the multicast table. 8946 */ 8947 #define MLXSW_REG_RMFT2_ID 0x8027 8948 #define MLXSW_REG_RMFT2_LEN 0x174 8949 8950 MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN); 8951 8952 /* reg_rmft2_v 8953 * Valid 8954 * Access: RW 8955 */ 8956 MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1); 8957 8958 enum mlxsw_reg_rmft2_type { 8959 MLXSW_REG_RMFT2_TYPE_IPV4, 8960 MLXSW_REG_RMFT2_TYPE_IPV6 8961 }; 8962 8963 /* reg_rmft2_type 8964 * Access: Index 8965 */ 8966 MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2); 8967 8968 enum mlxsw_sp_reg_rmft2_op { 8969 /* For Write: 8970 * Write operation. Used to write a new entry to the table. All RW 8971 * fields are relevant for new entry. Activity bit is set for new 8972 * entries - Note write with v (Valid) 0 will delete the entry. 8973 * For Query: 8974 * Read operation 8975 */ 8976 MLXSW_REG_RMFT2_OP_READ_WRITE, 8977 }; 8978 8979 /* reg_rmft2_op 8980 * Operation. 8981 * Access: OP 8982 */ 8983 MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2); 8984 8985 /* reg_rmft2_a 8986 * Activity. Set for new entries. Set if a packet lookup has hit on the specific 8987 * entry. 8988 * Access: RO 8989 */ 8990 MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1); 8991 8992 /* reg_rmft2_offset 8993 * Offset within the multicast forwarding table to write to. 8994 * Access: Index 8995 */ 8996 MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16); 8997 8998 /* reg_rmft2_virtual_router 8999 * Virtual Router ID. Range from 0..cap_max_virtual_routers-1 9000 * Access: RW 9001 */ 9002 MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16); 9003 9004 enum mlxsw_reg_rmft2_irif_mask { 9005 MLXSW_REG_RMFT2_IRIF_MASK_IGNORE, 9006 MLXSW_REG_RMFT2_IRIF_MASK_COMPARE 9007 }; 9008 9009 /* reg_rmft2_irif_mask 9010 * Ingress RIF mask. 9011 * Access: RW 9012 */ 9013 MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1); 9014 9015 /* reg_rmft2_irif 9016 * Ingress RIF index. 9017 * Access: RW 9018 */ 9019 MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16); 9020 9021 /* reg_rmft2_dip{4,6} 9022 * Destination IPv4/6 address 9023 * Access: RW 9024 */ 9025 MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16); 9026 MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32); 9027 9028 /* reg_rmft2_dip{4,6}_mask 9029 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 9030 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 9031 * Access: RW 9032 */ 9033 MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16); 9034 MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32); 9035 9036 /* reg_rmft2_sip{4,6} 9037 * Source IPv4/6 address 9038 * Access: RW 9039 */ 9040 MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16); 9041 MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32); 9042 9043 /* reg_rmft2_sip{4,6}_mask 9044 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 9045 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 9046 * Access: RW 9047 */ 9048 MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16); 9049 MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32); 9050 9051 /* reg_rmft2_flexible_action_set 9052 * ACL action set. The only supported action types in this field and in any 9053 * action-set pointed from here are as follows: 9054 * 00h: ACTION_NULL 9055 * 01h: ACTION_MAC_TTL, only TTL configuration is supported. 9056 * 03h: ACTION_TRAP 9057 * 06h: ACTION_QOS 9058 * 08h: ACTION_POLICING_MONITORING 9059 * 10h: ACTION_ROUTER_MC 9060 * Access: RW 9061 */ 9062 MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80, 9063 MLXSW_REG_FLEX_ACTION_SET_LEN); 9064 9065 static inline void 9066 mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset, 9067 u16 virtual_router, 9068 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 9069 const char *flex_action_set) 9070 { 9071 MLXSW_REG_ZERO(rmft2, payload); 9072 mlxsw_reg_rmft2_v_set(payload, v); 9073 mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE); 9074 mlxsw_reg_rmft2_offset_set(payload, offset); 9075 mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router); 9076 mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask); 9077 mlxsw_reg_rmft2_irif_set(payload, irif); 9078 if (flex_action_set) 9079 mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload, 9080 flex_action_set); 9081 } 9082 9083 static inline void 9084 mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router, 9085 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 9086 u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask, 9087 const char *flexible_action_set) 9088 { 9089 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 9090 irif_mask, irif, flexible_action_set); 9091 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4); 9092 mlxsw_reg_rmft2_dip4_set(payload, dip4); 9093 mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask); 9094 mlxsw_reg_rmft2_sip4_set(payload, sip4); 9095 mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask); 9096 } 9097 9098 static inline void 9099 mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router, 9100 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 9101 struct in6_addr dip6, struct in6_addr dip6_mask, 9102 struct in6_addr sip6, struct in6_addr sip6_mask, 9103 const char *flexible_action_set) 9104 { 9105 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 9106 irif_mask, irif, flexible_action_set); 9107 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6); 9108 mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6); 9109 mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask); 9110 mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6); 9111 mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask); 9112 } 9113 9114 /* REIV - Router Egress Interface to VID Register 9115 * ---------------------------------------------- 9116 * The REIV register maps {eRIF, egress_port} -> VID. 9117 * This mapping is done at the egress, after the ACLs. 9118 * This mapping always takes effect after router, regardless of cast 9119 * (for unicast/multicast/port-base multicast), regardless of eRIF type and 9120 * regardless of bridge decisions (e.g. SFD for unicast or SMPE). 9121 * Reserved when the RIF is a loopback RIF. 9122 * 9123 * Note: Reserved when legacy bridge model is used. 9124 */ 9125 #define MLXSW_REG_REIV_ID 0x8034 9126 #define MLXSW_REG_REIV_BASE_LEN 0x20 /* base length, without records */ 9127 #define MLXSW_REG_REIV_REC_LEN 0x04 /* record length */ 9128 #define MLXSW_REG_REIV_REC_MAX_COUNT 256 /* firmware limitation */ 9129 #define MLXSW_REG_REIV_LEN (MLXSW_REG_REIV_BASE_LEN + \ 9130 MLXSW_REG_REIV_REC_LEN * \ 9131 MLXSW_REG_REIV_REC_MAX_COUNT) 9132 9133 MLXSW_REG_DEFINE(reiv, MLXSW_REG_REIV_ID, MLXSW_REG_REIV_LEN); 9134 9135 /* reg_reiv_port_page 9136 * Port page - elport_record[0] is 256*port_page. 9137 * Access: Index 9138 */ 9139 MLXSW_ITEM32(reg, reiv, port_page, 0x00, 0, 4); 9140 9141 /* reg_reiv_erif 9142 * Egress RIF. 9143 * Range is 0..cap_max_router_interfaces-1. 9144 * Access: Index 9145 */ 9146 MLXSW_ITEM32(reg, reiv, erif, 0x04, 0, 16); 9147 9148 /* reg_reiv_rec_update 9149 * Update enable (when write): 9150 * 0 - Do not update the entry. 9151 * 1 - Update the entry. 9152 * Access: OP 9153 */ 9154 MLXSW_ITEM32_INDEXED(reg, reiv, rec_update, MLXSW_REG_REIV_BASE_LEN, 31, 1, 9155 MLXSW_REG_REIV_REC_LEN, 0x00, false); 9156 9157 /* reg_reiv_rec_evid 9158 * Egress VID. 9159 * Range is 0..4095. 9160 * Access: RW 9161 */ 9162 MLXSW_ITEM32_INDEXED(reg, reiv, rec_evid, MLXSW_REG_REIV_BASE_LEN, 0, 12, 9163 MLXSW_REG_REIV_REC_LEN, 0x00, false); 9164 9165 static inline void mlxsw_reg_reiv_pack(char *payload, u8 port_page, u16 erif) 9166 { 9167 MLXSW_REG_ZERO(reiv, payload); 9168 mlxsw_reg_reiv_port_page_set(payload, port_page); 9169 mlxsw_reg_reiv_erif_set(payload, erif); 9170 } 9171 9172 /* MFCR - Management Fan Control Register 9173 * -------------------------------------- 9174 * This register controls the settings of the Fan Speed PWM mechanism. 9175 */ 9176 #define MLXSW_REG_MFCR_ID 0x9001 9177 #define MLXSW_REG_MFCR_LEN 0x08 9178 9179 MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN); 9180 9181 enum mlxsw_reg_mfcr_pwm_frequency { 9182 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00, 9183 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01, 9184 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02, 9185 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40, 9186 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41, 9187 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42, 9188 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43, 9189 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44, 9190 }; 9191 9192 /* reg_mfcr_pwm_frequency 9193 * Controls the frequency of the PWM signal. 9194 * Access: RW 9195 */ 9196 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7); 9197 9198 #define MLXSW_MFCR_TACHOS_MAX 10 9199 9200 /* reg_mfcr_tacho_active 9201 * Indicates which of the tachometer is active (bit per tachometer). 9202 * Access: RO 9203 */ 9204 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX); 9205 9206 #define MLXSW_MFCR_PWMS_MAX 5 9207 9208 /* reg_mfcr_pwm_active 9209 * Indicates which of the PWM control is active (bit per PWM). 9210 * Access: RO 9211 */ 9212 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX); 9213 9214 static inline void 9215 mlxsw_reg_mfcr_pack(char *payload, 9216 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency) 9217 { 9218 MLXSW_REG_ZERO(mfcr, payload); 9219 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency); 9220 } 9221 9222 static inline void 9223 mlxsw_reg_mfcr_unpack(char *payload, 9224 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency, 9225 u16 *p_tacho_active, u8 *p_pwm_active) 9226 { 9227 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload); 9228 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload); 9229 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload); 9230 } 9231 9232 /* MFSC - Management Fan Speed Control Register 9233 * -------------------------------------------- 9234 * This register controls the settings of the Fan Speed PWM mechanism. 9235 */ 9236 #define MLXSW_REG_MFSC_ID 0x9002 9237 #define MLXSW_REG_MFSC_LEN 0x08 9238 9239 MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN); 9240 9241 /* reg_mfsc_pwm 9242 * Fan pwm to control / monitor. 9243 * Access: Index 9244 */ 9245 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3); 9246 9247 /* reg_mfsc_pwm_duty_cycle 9248 * Controls the duty cycle of the PWM. Value range from 0..255 to 9249 * represent duty cycle of 0%...100%. 9250 * Access: RW 9251 */ 9252 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8); 9253 9254 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm, 9255 u8 pwm_duty_cycle) 9256 { 9257 MLXSW_REG_ZERO(mfsc, payload); 9258 mlxsw_reg_mfsc_pwm_set(payload, pwm); 9259 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle); 9260 } 9261 9262 /* MFSM - Management Fan Speed Measurement 9263 * --------------------------------------- 9264 * This register controls the settings of the Tacho measurements and 9265 * enables reading the Tachometer measurements. 9266 */ 9267 #define MLXSW_REG_MFSM_ID 0x9003 9268 #define MLXSW_REG_MFSM_LEN 0x08 9269 9270 MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN); 9271 9272 /* reg_mfsm_tacho 9273 * Fan tachometer index. 9274 * Access: Index 9275 */ 9276 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4); 9277 9278 /* reg_mfsm_rpm 9279 * Fan speed (round per minute). 9280 * Access: RO 9281 */ 9282 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16); 9283 9284 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho) 9285 { 9286 MLXSW_REG_ZERO(mfsm, payload); 9287 mlxsw_reg_mfsm_tacho_set(payload, tacho); 9288 } 9289 9290 /* MFSL - Management Fan Speed Limit Register 9291 * ------------------------------------------ 9292 * The Fan Speed Limit register is used to configure the fan speed 9293 * event / interrupt notification mechanism. Fan speed threshold are 9294 * defined for both under-speed and over-speed. 9295 */ 9296 #define MLXSW_REG_MFSL_ID 0x9004 9297 #define MLXSW_REG_MFSL_LEN 0x0C 9298 9299 MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN); 9300 9301 /* reg_mfsl_tacho 9302 * Fan tachometer index. 9303 * Access: Index 9304 */ 9305 MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4); 9306 9307 /* reg_mfsl_tach_min 9308 * Tachometer minimum value (minimum RPM). 9309 * Access: RW 9310 */ 9311 MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16); 9312 9313 /* reg_mfsl_tach_max 9314 * Tachometer maximum value (maximum RPM). 9315 * Access: RW 9316 */ 9317 MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16); 9318 9319 static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho, 9320 u16 tach_min, u16 tach_max) 9321 { 9322 MLXSW_REG_ZERO(mfsl, payload); 9323 mlxsw_reg_mfsl_tacho_set(payload, tacho); 9324 mlxsw_reg_mfsl_tach_min_set(payload, tach_min); 9325 mlxsw_reg_mfsl_tach_max_set(payload, tach_max); 9326 } 9327 9328 static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho, 9329 u16 *p_tach_min, u16 *p_tach_max) 9330 { 9331 if (p_tach_min) 9332 *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload); 9333 9334 if (p_tach_max) 9335 *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload); 9336 } 9337 9338 /* FORE - Fan Out of Range Event Register 9339 * -------------------------------------- 9340 * This register reports the status of the controlled fans compared to the 9341 * range defined by the MFSL register. 9342 */ 9343 #define MLXSW_REG_FORE_ID 0x9007 9344 #define MLXSW_REG_FORE_LEN 0x0C 9345 9346 MLXSW_REG_DEFINE(fore, MLXSW_REG_FORE_ID, MLXSW_REG_FORE_LEN); 9347 9348 /* fan_under_limit 9349 * Fan speed is below the low limit defined in MFSL register. Each bit relates 9350 * to a single tachometer and indicates the specific tachometer reading is 9351 * below the threshold. 9352 * Access: RO 9353 */ 9354 MLXSW_ITEM32(reg, fore, fan_under_limit, 0x00, 16, 10); 9355 9356 static inline void mlxsw_reg_fore_unpack(char *payload, u8 tacho, 9357 bool *fault) 9358 { 9359 u16 limit; 9360 9361 if (fault) { 9362 limit = mlxsw_reg_fore_fan_under_limit_get(payload); 9363 *fault = limit & BIT(tacho); 9364 } 9365 } 9366 9367 /* MTCAP - Management Temperature Capabilities 9368 * ------------------------------------------- 9369 * This register exposes the capabilities of the device and 9370 * system temperature sensing. 9371 */ 9372 #define MLXSW_REG_MTCAP_ID 0x9009 9373 #define MLXSW_REG_MTCAP_LEN 0x08 9374 9375 MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN); 9376 9377 /* reg_mtcap_sensor_count 9378 * Number of sensors supported by the device. 9379 * This includes the QSFP module sensors (if exists in the QSFP module). 9380 * Access: RO 9381 */ 9382 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7); 9383 9384 /* MTMP - Management Temperature 9385 * ----------------------------- 9386 * This register controls the settings of the temperature measurements 9387 * and enables reading the temperature measurements. Note that temperature 9388 * is in 0.125 degrees Celsius. 9389 */ 9390 #define MLXSW_REG_MTMP_ID 0x900A 9391 #define MLXSW_REG_MTMP_LEN 0x20 9392 9393 MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN); 9394 9395 /* reg_mtmp_slot_index 9396 * Slot index (0: Main board). 9397 * Access: Index 9398 */ 9399 MLXSW_ITEM32(reg, mtmp, slot_index, 0x00, 16, 4); 9400 9401 #define MLXSW_REG_MTMP_MODULE_INDEX_MIN 64 9402 #define MLXSW_REG_MTMP_GBOX_INDEX_MIN 256 9403 /* reg_mtmp_sensor_index 9404 * Sensors index to access. 9405 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially 9406 * (module 0 is mapped to sensor_index 64). 9407 * Access: Index 9408 */ 9409 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 12); 9410 9411 /* Convert to milli degrees Celsius */ 9412 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) ({ typeof(val) v_ = (val); \ 9413 ((v_) >= 0) ? ((v_) * 125) : \ 9414 ((s16)((GENMASK(15, 0) + (v_) + 1) \ 9415 * 125)); }) 9416 9417 /* reg_mtmp_max_operational_temperature 9418 * The highest temperature in the nominal operational range. Reading is in 9419 * 0.125 Celsius degrees units. 9420 * In case of module this is SFF critical temperature threshold. 9421 * Access: RO 9422 */ 9423 MLXSW_ITEM32(reg, mtmp, max_operational_temperature, 0x04, 16, 16); 9424 9425 /* reg_mtmp_temperature 9426 * Temperature reading from the sensor. Reading is in 0.125 Celsius 9427 * degrees units. 9428 * Access: RO 9429 */ 9430 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16); 9431 9432 /* reg_mtmp_mte 9433 * Max Temperature Enable - enables measuring the max temperature on a sensor. 9434 * Access: RW 9435 */ 9436 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1); 9437 9438 /* reg_mtmp_mtr 9439 * Max Temperature Reset - clears the value of the max temperature register. 9440 * Access: WO 9441 */ 9442 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1); 9443 9444 /* reg_mtmp_max_temperature 9445 * The highest measured temperature from the sensor. 9446 * When the bit mte is cleared, the field max_temperature is reserved. 9447 * Access: RO 9448 */ 9449 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16); 9450 9451 /* reg_mtmp_tee 9452 * Temperature Event Enable. 9453 * 0 - Do not generate event 9454 * 1 - Generate event 9455 * 2 - Generate single event 9456 * Access: RW 9457 */ 9458 9459 enum mlxsw_reg_mtmp_tee { 9460 MLXSW_REG_MTMP_TEE_NO_EVENT, 9461 MLXSW_REG_MTMP_TEE_GENERATE_EVENT, 9462 MLXSW_REG_MTMP_TEE_GENERATE_SINGLE_EVENT, 9463 }; 9464 9465 MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2); 9466 9467 #define MLXSW_REG_MTMP_THRESH_HI 0x348 /* 105 Celsius */ 9468 9469 /* reg_mtmp_temperature_threshold_hi 9470 * High threshold for Temperature Warning Event. In 0.125 Celsius. 9471 * Access: RW 9472 */ 9473 MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16); 9474 9475 #define MLXSW_REG_MTMP_HYSTERESIS_TEMP 0x28 /* 5 Celsius */ 9476 /* reg_mtmp_temperature_threshold_lo 9477 * Low threshold for Temperature Warning Event. In 0.125 Celsius. 9478 * Access: RW 9479 */ 9480 MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16); 9481 9482 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8 9483 9484 /* reg_mtmp_sensor_name 9485 * Sensor Name 9486 * Access: RO 9487 */ 9488 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE); 9489 9490 static inline void mlxsw_reg_mtmp_pack(char *payload, u8 slot_index, 9491 u16 sensor_index, bool max_temp_enable, 9492 bool max_temp_reset) 9493 { 9494 MLXSW_REG_ZERO(mtmp, payload); 9495 mlxsw_reg_mtmp_slot_index_set(payload, slot_index); 9496 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index); 9497 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable); 9498 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset); 9499 mlxsw_reg_mtmp_temperature_threshold_hi_set(payload, 9500 MLXSW_REG_MTMP_THRESH_HI); 9501 } 9502 9503 static inline void mlxsw_reg_mtmp_unpack(char *payload, int *p_temp, 9504 int *p_max_temp, int *p_temp_hi, 9505 int *p_max_oper_temp, 9506 char *sensor_name) 9507 { 9508 s16 temp; 9509 9510 if (p_temp) { 9511 temp = mlxsw_reg_mtmp_temperature_get(payload); 9512 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9513 } 9514 if (p_max_temp) { 9515 temp = mlxsw_reg_mtmp_max_temperature_get(payload); 9516 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9517 } 9518 if (p_temp_hi) { 9519 temp = mlxsw_reg_mtmp_temperature_threshold_hi_get(payload); 9520 *p_temp_hi = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9521 } 9522 if (p_max_oper_temp) { 9523 temp = mlxsw_reg_mtmp_max_operational_temperature_get(payload); 9524 *p_max_oper_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9525 } 9526 if (sensor_name) 9527 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name); 9528 } 9529 9530 /* MTWE - Management Temperature Warning Event 9531 * ------------------------------------------- 9532 * This register is used for over temperature warning. 9533 */ 9534 #define MLXSW_REG_MTWE_ID 0x900B 9535 #define MLXSW_REG_MTWE_LEN 0x10 9536 9537 MLXSW_REG_DEFINE(mtwe, MLXSW_REG_MTWE_ID, MLXSW_REG_MTWE_LEN); 9538 9539 /* reg_mtwe_sensor_warning 9540 * Bit vector indicating which of the sensor reading is above threshold. 9541 * Address 00h bit31 is sensor_warning[127]. 9542 * Address 0Ch bit0 is sensor_warning[0]. 9543 * Access: RO 9544 */ 9545 MLXSW_ITEM_BIT_ARRAY(reg, mtwe, sensor_warning, 0x0, 0x10, 1); 9546 9547 /* MTBR - Management Temperature Bulk Register 9548 * ------------------------------------------- 9549 * This register is used for bulk temperature reading. 9550 */ 9551 #define MLXSW_REG_MTBR_ID 0x900F 9552 #define MLXSW_REG_MTBR_BASE_LEN 0x10 /* base length, without records */ 9553 #define MLXSW_REG_MTBR_REC_LEN 0x04 /* record length */ 9554 #define MLXSW_REG_MTBR_REC_MAX_COUNT 47 /* firmware limitation */ 9555 #define MLXSW_REG_MTBR_LEN (MLXSW_REG_MTBR_BASE_LEN + \ 9556 MLXSW_REG_MTBR_REC_LEN * \ 9557 MLXSW_REG_MTBR_REC_MAX_COUNT) 9558 9559 MLXSW_REG_DEFINE(mtbr, MLXSW_REG_MTBR_ID, MLXSW_REG_MTBR_LEN); 9560 9561 /* reg_mtbr_slot_index 9562 * Slot index (0: Main board). 9563 * Access: Index 9564 */ 9565 MLXSW_ITEM32(reg, mtbr, slot_index, 0x00, 16, 4); 9566 9567 /* reg_mtbr_base_sensor_index 9568 * Base sensors index to access (0 - ASIC sensor, 1-63 - ambient sensors, 9569 * 64-127 are mapped to the SFP+/QSFP modules sequentially). 9570 * Access: Index 9571 */ 9572 MLXSW_ITEM32(reg, mtbr, base_sensor_index, 0x00, 0, 12); 9573 9574 /* reg_mtbr_num_rec 9575 * Request: Number of records to read 9576 * Response: Number of records read 9577 * See above description for more details. 9578 * Range 1..255 9579 * Access: RW 9580 */ 9581 MLXSW_ITEM32(reg, mtbr, num_rec, 0x04, 0, 8); 9582 9583 /* reg_mtbr_rec_max_temp 9584 * The highest measured temperature from the sensor. 9585 * When the bit mte is cleared, the field max_temperature is reserved. 9586 * Access: RO 9587 */ 9588 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_max_temp, MLXSW_REG_MTBR_BASE_LEN, 16, 9589 16, MLXSW_REG_MTBR_REC_LEN, 0x00, false); 9590 9591 /* reg_mtbr_rec_temp 9592 * Temperature reading from the sensor. Reading is in 0..125 Celsius 9593 * degrees units. 9594 * Access: RO 9595 */ 9596 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_temp, MLXSW_REG_MTBR_BASE_LEN, 0, 16, 9597 MLXSW_REG_MTBR_REC_LEN, 0x00, false); 9598 9599 static inline void mlxsw_reg_mtbr_pack(char *payload, u8 slot_index, 9600 u16 base_sensor_index, u8 num_rec) 9601 { 9602 MLXSW_REG_ZERO(mtbr, payload); 9603 mlxsw_reg_mtbr_slot_index_set(payload, slot_index); 9604 mlxsw_reg_mtbr_base_sensor_index_set(payload, base_sensor_index); 9605 mlxsw_reg_mtbr_num_rec_set(payload, num_rec); 9606 } 9607 9608 /* Error codes from temperatute reading */ 9609 enum mlxsw_reg_mtbr_temp_status { 9610 MLXSW_REG_MTBR_NO_CONN = 0x8000, 9611 MLXSW_REG_MTBR_NO_TEMP_SENS = 0x8001, 9612 MLXSW_REG_MTBR_INDEX_NA = 0x8002, 9613 MLXSW_REG_MTBR_BAD_SENS_INFO = 0x8003, 9614 }; 9615 9616 /* Base index for reading modules temperature */ 9617 #define MLXSW_REG_MTBR_BASE_MODULE_INDEX 64 9618 9619 static inline void mlxsw_reg_mtbr_temp_unpack(char *payload, int rec_ind, 9620 u16 *p_temp, u16 *p_max_temp) 9621 { 9622 if (p_temp) 9623 *p_temp = mlxsw_reg_mtbr_rec_temp_get(payload, rec_ind); 9624 if (p_max_temp) 9625 *p_max_temp = mlxsw_reg_mtbr_rec_max_temp_get(payload, rec_ind); 9626 } 9627 9628 /* MCIA - Management Cable Info Access 9629 * ----------------------------------- 9630 * MCIA register is used to access the SFP+ and QSFP connector's EPROM. 9631 */ 9632 9633 #define MLXSW_REG_MCIA_ID 0x9014 9634 #define MLXSW_REG_MCIA_LEN 0x94 9635 9636 MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN); 9637 9638 /* reg_mcia_module 9639 * Module number. 9640 * Access: Index 9641 */ 9642 MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8); 9643 9644 /* reg_mcia_slot_index 9645 * Slot index (0: Main board) 9646 * Access: Index 9647 */ 9648 MLXSW_ITEM32(reg, mcia, slot, 0x00, 12, 4); 9649 9650 enum { 9651 MLXSW_REG_MCIA_STATUS_GOOD = 0, 9652 /* No response from module's EEPROM. */ 9653 MLXSW_REG_MCIA_STATUS_NO_EEPROM_MODULE = 1, 9654 /* Module type not supported by the device. */ 9655 MLXSW_REG_MCIA_STATUS_MODULE_NOT_SUPPORTED = 2, 9656 /* No module present indication. */ 9657 MLXSW_REG_MCIA_STATUS_MODULE_NOT_CONNECTED = 3, 9658 /* Error occurred while trying to access module's EEPROM using I2C. */ 9659 MLXSW_REG_MCIA_STATUS_I2C_ERROR = 9, 9660 /* Module is disabled. */ 9661 MLXSW_REG_MCIA_STATUS_MODULE_DISABLED = 16, 9662 }; 9663 9664 /* reg_mcia_status 9665 * Module status. 9666 * Access: RO 9667 */ 9668 MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8); 9669 9670 /* reg_mcia_i2c_device_address 9671 * I2C device address. 9672 * Access: RW 9673 */ 9674 MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8); 9675 9676 /* reg_mcia_page_number 9677 * Page number. 9678 * Access: RW 9679 */ 9680 MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8); 9681 9682 /* reg_mcia_device_address 9683 * Device address. 9684 * Access: RW 9685 */ 9686 MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16); 9687 9688 /* reg_mcia_bank_number 9689 * Bank number. 9690 * Access: Index 9691 */ 9692 MLXSW_ITEM32(reg, mcia, bank_number, 0x08, 16, 8); 9693 9694 /* reg_mcia_size 9695 * Number of bytes to read/write (up to 48 bytes). 9696 * Access: RW 9697 */ 9698 MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16); 9699 9700 #define MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH 256 9701 #define MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH 128 9702 #define MLXSW_REG_MCIA_I2C_ADDR_LOW 0x50 9703 #define MLXSW_REG_MCIA_I2C_ADDR_HIGH 0x51 9704 #define MLXSW_REG_MCIA_PAGE0_LO_OFF 0xa0 9705 #define MLXSW_REG_MCIA_TH_ITEM_SIZE 2 9706 #define MLXSW_REG_MCIA_TH_PAGE_NUM 3 9707 #define MLXSW_REG_MCIA_TH_PAGE_CMIS_NUM 2 9708 #define MLXSW_REG_MCIA_PAGE0_LO 0 9709 #define MLXSW_REG_MCIA_TH_PAGE_OFF 0x80 9710 #define MLXSW_REG_MCIA_EEPROM_CMIS_FLAT_MEMORY BIT(7) 9711 9712 enum mlxsw_reg_mcia_eeprom_module_info_rev_id { 9713 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00, 9714 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01, 9715 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03, 9716 }; 9717 9718 enum mlxsw_reg_mcia_eeprom_module_info_id { 9719 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_SFP = 0x03, 9720 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP = 0x0C, 9721 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D, 9722 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11, 9723 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_DD = 0x18, 9724 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_OSFP = 0x19, 9725 }; 9726 9727 enum mlxsw_reg_mcia_eeprom_module_info { 9728 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID, 9729 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID, 9730 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_TYPE_ID, 9731 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_SIZE, 9732 }; 9733 9734 /* reg_mcia_eeprom 9735 * Bytes to read/write. 9736 * Access: RW 9737 */ 9738 MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, 128); 9739 9740 /* This is used to access the optional upper pages (1-3) in the QSFP+ 9741 * memory map. Page 1 is available on offset 256 through 383, page 2 - 9742 * on offset 384 through 511, page 3 - on offset 512 through 639. 9743 */ 9744 #define MLXSW_REG_MCIA_PAGE_GET(off) (((off) - \ 9745 MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH) / \ 9746 MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH + 1) 9747 9748 static inline void mlxsw_reg_mcia_pack(char *payload, u8 slot_index, u8 module, 9749 u8 page_number, u16 device_addr, u8 size, 9750 u8 i2c_device_addr) 9751 { 9752 MLXSW_REG_ZERO(mcia, payload); 9753 mlxsw_reg_mcia_slot_set(payload, slot_index); 9754 mlxsw_reg_mcia_module_set(payload, module); 9755 mlxsw_reg_mcia_page_number_set(payload, page_number); 9756 mlxsw_reg_mcia_device_address_set(payload, device_addr); 9757 mlxsw_reg_mcia_size_set(payload, size); 9758 mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr); 9759 } 9760 9761 /* MPAT - Monitoring Port Analyzer Table 9762 * ------------------------------------- 9763 * MPAT Register is used to query and configure the Switch PortAnalyzer Table. 9764 * For an enabled analyzer, all fields except e (enable) cannot be modified. 9765 */ 9766 #define MLXSW_REG_MPAT_ID 0x901A 9767 #define MLXSW_REG_MPAT_LEN 0x78 9768 9769 MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN); 9770 9771 /* reg_mpat_pa_id 9772 * Port Analyzer ID. 9773 * Access: Index 9774 */ 9775 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4); 9776 9777 /* reg_mpat_session_id 9778 * Mirror Session ID. 9779 * Used for MIRROR_SESSION<i> trap. 9780 * Access: RW 9781 */ 9782 MLXSW_ITEM32(reg, mpat, session_id, 0x00, 24, 4); 9783 9784 /* reg_mpat_system_port 9785 * A unique port identifier for the final destination of the packet. 9786 * Access: RW 9787 */ 9788 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16); 9789 9790 /* reg_mpat_e 9791 * Enable. Indicating the Port Analyzer is enabled. 9792 * Access: RW 9793 */ 9794 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1); 9795 9796 /* reg_mpat_qos 9797 * Quality Of Service Mode. 9798 * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation 9799 * PCP, DEI, DSCP or VL) are configured. 9800 * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the 9801 * same as in the original packet that has triggered the mirroring. For 9802 * SPAN also the pcp,dei are maintained. 9803 * Access: RW 9804 */ 9805 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1); 9806 9807 /* reg_mpat_be 9808 * Best effort mode. Indicates mirroring traffic should not cause packet 9809 * drop or back pressure, but will discard the mirrored packets. Mirrored 9810 * packets will be forwarded on a best effort manner. 9811 * 0: Do not discard mirrored packets 9812 * 1: Discard mirrored packets if causing congestion 9813 * Access: RW 9814 */ 9815 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1); 9816 9817 enum mlxsw_reg_mpat_span_type { 9818 /* Local SPAN Ethernet. 9819 * The original packet is not encapsulated. 9820 */ 9821 MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0, 9822 9823 /* Remote SPAN Ethernet VLAN. 9824 * The packet is forwarded to the monitoring port on the monitoring 9825 * VLAN. 9826 */ 9827 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1, 9828 9829 /* Encapsulated Remote SPAN Ethernet L3 GRE. 9830 * The packet is encapsulated with GRE header. 9831 */ 9832 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3, 9833 }; 9834 9835 /* reg_mpat_span_type 9836 * SPAN type. 9837 * Access: RW 9838 */ 9839 MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4); 9840 9841 /* reg_mpat_pide 9842 * Policer enable. 9843 * Access: RW 9844 */ 9845 MLXSW_ITEM32(reg, mpat, pide, 0x0C, 15, 1); 9846 9847 /* reg_mpat_pid 9848 * Policer ID. 9849 * Access: RW 9850 */ 9851 MLXSW_ITEM32(reg, mpat, pid, 0x0C, 0, 14); 9852 9853 /* Remote SPAN - Ethernet VLAN 9854 * - - - - - - - - - - - - - - 9855 */ 9856 9857 /* reg_mpat_eth_rspan_vid 9858 * Encapsulation header VLAN ID. 9859 * Access: RW 9860 */ 9861 MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12); 9862 9863 /* Encapsulated Remote SPAN - Ethernet L2 9864 * - - - - - - - - - - - - - - - - - - - 9865 */ 9866 9867 enum mlxsw_reg_mpat_eth_rspan_version { 9868 MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15, 9869 }; 9870 9871 /* reg_mpat_eth_rspan_version 9872 * RSPAN mirror header version. 9873 * Access: RW 9874 */ 9875 MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4); 9876 9877 /* reg_mpat_eth_rspan_mac 9878 * Destination MAC address. 9879 * Access: RW 9880 */ 9881 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6); 9882 9883 /* reg_mpat_eth_rspan_tp 9884 * Tag Packet. Indicates whether the mirroring header should be VLAN tagged. 9885 * Access: RW 9886 */ 9887 MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1); 9888 9889 /* Encapsulated Remote SPAN - Ethernet L3 9890 * - - - - - - - - - - - - - - - - - - - 9891 */ 9892 9893 enum mlxsw_reg_mpat_eth_rspan_protocol { 9894 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4, 9895 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6, 9896 }; 9897 9898 /* reg_mpat_eth_rspan_protocol 9899 * SPAN encapsulation protocol. 9900 * Access: RW 9901 */ 9902 MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4); 9903 9904 /* reg_mpat_eth_rspan_ttl 9905 * Encapsulation header Time-to-Live/HopLimit. 9906 * Access: RW 9907 */ 9908 MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8); 9909 9910 /* reg_mpat_eth_rspan_smac 9911 * Source MAC address 9912 * Access: RW 9913 */ 9914 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6); 9915 9916 /* reg_mpat_eth_rspan_dip* 9917 * Destination IP address. The IP version is configured by protocol. 9918 * Access: RW 9919 */ 9920 MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32); 9921 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16); 9922 9923 /* reg_mpat_eth_rspan_sip* 9924 * Source IP address. The IP version is configured by protocol. 9925 * Access: RW 9926 */ 9927 MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32); 9928 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16); 9929 9930 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id, 9931 u16 system_port, bool e, 9932 enum mlxsw_reg_mpat_span_type span_type) 9933 { 9934 MLXSW_REG_ZERO(mpat, payload); 9935 mlxsw_reg_mpat_pa_id_set(payload, pa_id); 9936 mlxsw_reg_mpat_system_port_set(payload, system_port); 9937 mlxsw_reg_mpat_e_set(payload, e); 9938 mlxsw_reg_mpat_qos_set(payload, 1); 9939 mlxsw_reg_mpat_be_set(payload, 1); 9940 mlxsw_reg_mpat_span_type_set(payload, span_type); 9941 } 9942 9943 static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid) 9944 { 9945 mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid); 9946 } 9947 9948 static inline void 9949 mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload, 9950 enum mlxsw_reg_mpat_eth_rspan_version version, 9951 const char *mac, 9952 bool tp) 9953 { 9954 mlxsw_reg_mpat_eth_rspan_version_set(payload, version); 9955 mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac); 9956 mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp); 9957 } 9958 9959 static inline void 9960 mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl, 9961 const char *smac, 9962 u32 sip, u32 dip) 9963 { 9964 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 9965 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 9966 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 9967 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4); 9968 mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip); 9969 mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip); 9970 } 9971 9972 static inline void 9973 mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl, 9974 const char *smac, 9975 struct in6_addr sip, struct in6_addr dip) 9976 { 9977 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 9978 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 9979 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 9980 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6); 9981 mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip); 9982 mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip); 9983 } 9984 9985 /* MPAR - Monitoring Port Analyzer Register 9986 * ---------------------------------------- 9987 * MPAR register is used to query and configure the port analyzer port mirroring 9988 * properties. 9989 */ 9990 #define MLXSW_REG_MPAR_ID 0x901B 9991 #define MLXSW_REG_MPAR_LEN 0x0C 9992 9993 MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN); 9994 9995 /* reg_mpar_local_port 9996 * The local port to mirror the packets from. 9997 * Access: Index 9998 */ 9999 MLXSW_ITEM32_LP(reg, mpar, 0x00, 16, 0x00, 4); 10000 10001 enum mlxsw_reg_mpar_i_e { 10002 MLXSW_REG_MPAR_TYPE_EGRESS, 10003 MLXSW_REG_MPAR_TYPE_INGRESS, 10004 }; 10005 10006 /* reg_mpar_i_e 10007 * Ingress/Egress 10008 * Access: Index 10009 */ 10010 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4); 10011 10012 /* reg_mpar_enable 10013 * Enable mirroring 10014 * By default, port mirroring is disabled for all ports. 10015 * Access: RW 10016 */ 10017 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1); 10018 10019 /* reg_mpar_pa_id 10020 * Port Analyzer ID. 10021 * Access: RW 10022 */ 10023 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4); 10024 10025 #define MLXSW_REG_MPAR_RATE_MAX 3500000000UL 10026 10027 /* reg_mpar_probability_rate 10028 * Sampling rate. 10029 * Valid values are: 1 to 3.5*10^9 10030 * Value of 1 means "sample all". Default is 1. 10031 * Reserved when Spectrum-1. 10032 * Access: RW 10033 */ 10034 MLXSW_ITEM32(reg, mpar, probability_rate, 0x08, 0, 32); 10035 10036 static inline void mlxsw_reg_mpar_pack(char *payload, u16 local_port, 10037 enum mlxsw_reg_mpar_i_e i_e, 10038 bool enable, u8 pa_id, 10039 u32 probability_rate) 10040 { 10041 MLXSW_REG_ZERO(mpar, payload); 10042 mlxsw_reg_mpar_local_port_set(payload, local_port); 10043 mlxsw_reg_mpar_enable_set(payload, enable); 10044 mlxsw_reg_mpar_i_e_set(payload, i_e); 10045 mlxsw_reg_mpar_pa_id_set(payload, pa_id); 10046 mlxsw_reg_mpar_probability_rate_set(payload, probability_rate); 10047 } 10048 10049 /* MGIR - Management General Information Register 10050 * ---------------------------------------------- 10051 * MGIR register allows software to query the hardware and firmware general 10052 * information. 10053 */ 10054 #define MLXSW_REG_MGIR_ID 0x9020 10055 #define MLXSW_REG_MGIR_LEN 0x9C 10056 10057 MLXSW_REG_DEFINE(mgir, MLXSW_REG_MGIR_ID, MLXSW_REG_MGIR_LEN); 10058 10059 /* reg_mgir_hw_info_device_hw_revision 10060 * Access: RO 10061 */ 10062 MLXSW_ITEM32(reg, mgir, hw_info_device_hw_revision, 0x0, 16, 16); 10063 10064 /* reg_mgir_fw_info_latency_tlv 10065 * When set, latency-TLV is supported. 10066 * Access: RO 10067 */ 10068 MLXSW_ITEM32(reg, mgir, fw_info_latency_tlv, 0x20, 29, 1); 10069 10070 /* reg_mgir_fw_info_string_tlv 10071 * When set, string-TLV is supported. 10072 * Access: RO 10073 */ 10074 MLXSW_ITEM32(reg, mgir, fw_info_string_tlv, 0x20, 28, 1); 10075 10076 #define MLXSW_REG_MGIR_FW_INFO_PSID_SIZE 16 10077 10078 /* reg_mgir_fw_info_psid 10079 * PSID (ASCII string). 10080 * Access: RO 10081 */ 10082 MLXSW_ITEM_BUF(reg, mgir, fw_info_psid, 0x30, MLXSW_REG_MGIR_FW_INFO_PSID_SIZE); 10083 10084 /* reg_mgir_fw_info_extended_major 10085 * Access: RO 10086 */ 10087 MLXSW_ITEM32(reg, mgir, fw_info_extended_major, 0x44, 0, 32); 10088 10089 /* reg_mgir_fw_info_extended_minor 10090 * Access: RO 10091 */ 10092 MLXSW_ITEM32(reg, mgir, fw_info_extended_minor, 0x48, 0, 32); 10093 10094 /* reg_mgir_fw_info_extended_sub_minor 10095 * Access: RO 10096 */ 10097 MLXSW_ITEM32(reg, mgir, fw_info_extended_sub_minor, 0x4C, 0, 32); 10098 10099 static inline void mlxsw_reg_mgir_pack(char *payload) 10100 { 10101 MLXSW_REG_ZERO(mgir, payload); 10102 } 10103 10104 static inline void 10105 mlxsw_reg_mgir_unpack(char *payload, u32 *hw_rev, char *fw_info_psid, 10106 u32 *fw_major, u32 *fw_minor, u32 *fw_sub_minor) 10107 { 10108 *hw_rev = mlxsw_reg_mgir_hw_info_device_hw_revision_get(payload); 10109 mlxsw_reg_mgir_fw_info_psid_memcpy_from(payload, fw_info_psid); 10110 *fw_major = mlxsw_reg_mgir_fw_info_extended_major_get(payload); 10111 *fw_minor = mlxsw_reg_mgir_fw_info_extended_minor_get(payload); 10112 *fw_sub_minor = mlxsw_reg_mgir_fw_info_extended_sub_minor_get(payload); 10113 } 10114 10115 /* MRSR - Management Reset and Shutdown Register 10116 * --------------------------------------------- 10117 * MRSR register is used to reset or shutdown the switch or 10118 * the entire system (when applicable). 10119 */ 10120 #define MLXSW_REG_MRSR_ID 0x9023 10121 #define MLXSW_REG_MRSR_LEN 0x08 10122 10123 MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN); 10124 10125 /* reg_mrsr_command 10126 * Reset/shutdown command 10127 * 0 - do nothing 10128 * 1 - software reset 10129 * Access: WO 10130 */ 10131 MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4); 10132 10133 static inline void mlxsw_reg_mrsr_pack(char *payload) 10134 { 10135 MLXSW_REG_ZERO(mrsr, payload); 10136 mlxsw_reg_mrsr_command_set(payload, 1); 10137 } 10138 10139 /* MLCR - Management LED Control Register 10140 * -------------------------------------- 10141 * Controls the system LEDs. 10142 */ 10143 #define MLXSW_REG_MLCR_ID 0x902B 10144 #define MLXSW_REG_MLCR_LEN 0x0C 10145 10146 MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN); 10147 10148 /* reg_mlcr_local_port 10149 * Local port number. 10150 * Access: RW 10151 */ 10152 MLXSW_ITEM32_LP(reg, mlcr, 0x00, 16, 0x00, 24); 10153 10154 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF 10155 10156 /* reg_mlcr_beacon_duration 10157 * Duration of the beacon to be active, in seconds. 10158 * 0x0 - Will turn off the beacon. 10159 * 0xFFFF - Will turn on the beacon until explicitly turned off. 10160 * Access: RW 10161 */ 10162 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16); 10163 10164 /* reg_mlcr_beacon_remain 10165 * Remaining duration of the beacon, in seconds. 10166 * 0xFFFF indicates an infinite amount of time. 10167 * Access: RO 10168 */ 10169 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16); 10170 10171 static inline void mlxsw_reg_mlcr_pack(char *payload, u16 local_port, 10172 bool active) 10173 { 10174 MLXSW_REG_ZERO(mlcr, payload); 10175 mlxsw_reg_mlcr_local_port_set(payload, local_port); 10176 mlxsw_reg_mlcr_beacon_duration_set(payload, active ? 10177 MLXSW_REG_MLCR_DURATION_MAX : 0); 10178 } 10179 10180 /* MCION - Management Cable IO and Notifications Register 10181 * ------------------------------------------------------ 10182 * The MCION register is used to query transceiver modules' IO pins and other 10183 * notifications. 10184 */ 10185 #define MLXSW_REG_MCION_ID 0x9052 10186 #define MLXSW_REG_MCION_LEN 0x18 10187 10188 MLXSW_REG_DEFINE(mcion, MLXSW_REG_MCION_ID, MLXSW_REG_MCION_LEN); 10189 10190 /* reg_mcion_module 10191 * Module number. 10192 * Access: Index 10193 */ 10194 MLXSW_ITEM32(reg, mcion, module, 0x00, 16, 8); 10195 10196 /* reg_mcion_slot_index 10197 * Slot index. 10198 * Access: Index 10199 */ 10200 MLXSW_ITEM32(reg, mcion, slot_index, 0x00, 12, 4); 10201 10202 enum { 10203 MLXSW_REG_MCION_MODULE_STATUS_BITS_PRESENT_MASK = BIT(0), 10204 MLXSW_REG_MCION_MODULE_STATUS_BITS_LOW_POWER_MASK = BIT(8), 10205 }; 10206 10207 /* reg_mcion_module_status_bits 10208 * Module IO status as defined by SFF. 10209 * Access: RO 10210 */ 10211 MLXSW_ITEM32(reg, mcion, module_status_bits, 0x04, 0, 16); 10212 10213 static inline void mlxsw_reg_mcion_pack(char *payload, u8 slot_index, u8 module) 10214 { 10215 MLXSW_REG_ZERO(mcion, payload); 10216 mlxsw_reg_mcion_slot_index_set(payload, slot_index); 10217 mlxsw_reg_mcion_module_set(payload, module); 10218 } 10219 10220 /* MTPPS - Management Pulse Per Second Register 10221 * -------------------------------------------- 10222 * This register provides the device PPS capabilities, configure the PPS in and 10223 * out modules and holds the PPS in time stamp. 10224 */ 10225 #define MLXSW_REG_MTPPS_ID 0x9053 10226 #define MLXSW_REG_MTPPS_LEN 0x3C 10227 10228 MLXSW_REG_DEFINE(mtpps, MLXSW_REG_MTPPS_ID, MLXSW_REG_MTPPS_LEN); 10229 10230 /* reg_mtpps_enable 10231 * Enables the PPS functionality the specific pin. 10232 * A boolean variable. 10233 * Access: RW 10234 */ 10235 MLXSW_ITEM32(reg, mtpps, enable, 0x20, 31, 1); 10236 10237 enum mlxsw_reg_mtpps_pin_mode { 10238 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN = 0x2, 10239 }; 10240 10241 /* reg_mtpps_pin_mode 10242 * Pin mode to be used. The mode must comply with the supported modes of the 10243 * requested pin. 10244 * Access: RW 10245 */ 10246 MLXSW_ITEM32(reg, mtpps, pin_mode, 0x20, 8, 4); 10247 10248 #define MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN 7 10249 10250 /* reg_mtpps_pin 10251 * Pin to be configured or queried out of the supported pins. 10252 * Access: Index 10253 */ 10254 MLXSW_ITEM32(reg, mtpps, pin, 0x20, 0, 8); 10255 10256 /* reg_mtpps_time_stamp 10257 * When pin_mode = pps_in, the latched device time when it was triggered from 10258 * the external GPIO pin. 10259 * When pin_mode = pps_out or virtual_pin or pps_out_and_virtual_pin, the target 10260 * time to generate next output signal. 10261 * Time is in units of device clock. 10262 * Access: RW 10263 */ 10264 MLXSW_ITEM64(reg, mtpps, time_stamp, 0x28, 0, 64); 10265 10266 static inline void 10267 mlxsw_reg_mtpps_vpin_pack(char *payload, u64 time_stamp) 10268 { 10269 MLXSW_REG_ZERO(mtpps, payload); 10270 mlxsw_reg_mtpps_pin_set(payload, MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN); 10271 mlxsw_reg_mtpps_pin_mode_set(payload, 10272 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN); 10273 mlxsw_reg_mtpps_enable_set(payload, true); 10274 mlxsw_reg_mtpps_time_stamp_set(payload, time_stamp); 10275 } 10276 10277 /* MTUTC - Management UTC Register 10278 * ------------------------------- 10279 * Configures the HW UTC counter. 10280 */ 10281 #define MLXSW_REG_MTUTC_ID 0x9055 10282 #define MLXSW_REG_MTUTC_LEN 0x1C 10283 10284 MLXSW_REG_DEFINE(mtutc, MLXSW_REG_MTUTC_ID, MLXSW_REG_MTUTC_LEN); 10285 10286 enum mlxsw_reg_mtutc_operation { 10287 MLXSW_REG_MTUTC_OPERATION_SET_TIME_AT_NEXT_SEC = 0, 10288 MLXSW_REG_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 1, 10289 MLXSW_REG_MTUTC_OPERATION_ADJUST_TIME = 2, 10290 MLXSW_REG_MTUTC_OPERATION_ADJUST_FREQ = 3, 10291 }; 10292 10293 /* reg_mtutc_operation 10294 * Operation. 10295 * Access: OP 10296 */ 10297 MLXSW_ITEM32(reg, mtutc, operation, 0x00, 0, 4); 10298 10299 /* reg_mtutc_freq_adjustment 10300 * Frequency adjustment: Every PPS the HW frequency will be 10301 * adjusted by this value. Units of HW clock, where HW counts 10302 * 10^9 HW clocks for 1 HW second. Range is from -50,000,000 to +50,000,000. 10303 * In Spectrum-2, the field is reversed, positive values mean to decrease the 10304 * frequency. 10305 * Access: RW 10306 */ 10307 MLXSW_ITEM32(reg, mtutc, freq_adjustment, 0x04, 0, 32); 10308 10309 #define MLXSW_REG_MTUTC_MAX_FREQ_ADJ (50 * 1000 * 1000) 10310 10311 /* reg_mtutc_utc_sec 10312 * UTC seconds. 10313 * Access: WO 10314 */ 10315 MLXSW_ITEM32(reg, mtutc, utc_sec, 0x10, 0, 32); 10316 10317 /* reg_mtutc_utc_nsec 10318 * UTC nSecs. 10319 * Range 0..(10^9-1) 10320 * Updated when operation is SET_TIME_IMMEDIATE. 10321 * Reserved on Spectrum-1. 10322 * Access: WO 10323 */ 10324 MLXSW_ITEM32(reg, mtutc, utc_nsec, 0x14, 0, 30); 10325 10326 /* reg_mtutc_time_adjustment 10327 * Time adjustment. 10328 * Units of nSec. 10329 * Range is from -32768 to +32767. 10330 * Updated when operation is ADJUST_TIME. 10331 * Reserved on Spectrum-1. 10332 * Access: WO 10333 */ 10334 MLXSW_ITEM32(reg, mtutc, time_adjustment, 0x18, 0, 32); 10335 10336 static inline void 10337 mlxsw_reg_mtutc_pack(char *payload, enum mlxsw_reg_mtutc_operation oper, 10338 u32 freq_adj, u32 utc_sec, u32 utc_nsec, u32 time_adj) 10339 { 10340 MLXSW_REG_ZERO(mtutc, payload); 10341 mlxsw_reg_mtutc_operation_set(payload, oper); 10342 mlxsw_reg_mtutc_freq_adjustment_set(payload, freq_adj); 10343 mlxsw_reg_mtutc_utc_sec_set(payload, utc_sec); 10344 mlxsw_reg_mtutc_utc_nsec_set(payload, utc_nsec); 10345 mlxsw_reg_mtutc_time_adjustment_set(payload, time_adj); 10346 } 10347 10348 /* MCQI - Management Component Query Information 10349 * --------------------------------------------- 10350 * This register allows querying information about firmware components. 10351 */ 10352 #define MLXSW_REG_MCQI_ID 0x9061 10353 #define MLXSW_REG_MCQI_BASE_LEN 0x18 10354 #define MLXSW_REG_MCQI_CAP_LEN 0x14 10355 #define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN) 10356 10357 MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN); 10358 10359 /* reg_mcqi_component_index 10360 * Index of the accessed component. 10361 * Access: Index 10362 */ 10363 MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16); 10364 10365 enum mlxfw_reg_mcqi_info_type { 10366 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES, 10367 }; 10368 10369 /* reg_mcqi_info_type 10370 * Component properties set. 10371 * Access: RW 10372 */ 10373 MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5); 10374 10375 /* reg_mcqi_offset 10376 * The requested/returned data offset from the section start, given in bytes. 10377 * Must be DWORD aligned. 10378 * Access: RW 10379 */ 10380 MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32); 10381 10382 /* reg_mcqi_data_size 10383 * The requested/returned data size, given in bytes. If data_size is not DWORD 10384 * aligned, the last bytes are zero padded. 10385 * Access: RW 10386 */ 10387 MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16); 10388 10389 /* reg_mcqi_cap_max_component_size 10390 * Maximum size for this component, given in bytes. 10391 * Access: RO 10392 */ 10393 MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32); 10394 10395 /* reg_mcqi_cap_log_mcda_word_size 10396 * Log 2 of the access word size in bytes. Read and write access must be aligned 10397 * to the word size. Write access must be done for an integer number of words. 10398 * Access: RO 10399 */ 10400 MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4); 10401 10402 /* reg_mcqi_cap_mcda_max_write_size 10403 * Maximal write size for MCDA register 10404 * Access: RO 10405 */ 10406 MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16); 10407 10408 static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index) 10409 { 10410 MLXSW_REG_ZERO(mcqi, payload); 10411 mlxsw_reg_mcqi_component_index_set(payload, component_index); 10412 mlxsw_reg_mcqi_info_type_set(payload, 10413 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES); 10414 mlxsw_reg_mcqi_offset_set(payload, 0); 10415 mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN); 10416 } 10417 10418 static inline void mlxsw_reg_mcqi_unpack(char *payload, 10419 u32 *p_cap_max_component_size, 10420 u8 *p_cap_log_mcda_word_size, 10421 u16 *p_cap_mcda_max_write_size) 10422 { 10423 *p_cap_max_component_size = 10424 mlxsw_reg_mcqi_cap_max_component_size_get(payload); 10425 *p_cap_log_mcda_word_size = 10426 mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload); 10427 *p_cap_mcda_max_write_size = 10428 mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload); 10429 } 10430 10431 /* MCC - Management Component Control 10432 * ---------------------------------- 10433 * Controls the firmware component and updates the FSM. 10434 */ 10435 #define MLXSW_REG_MCC_ID 0x9062 10436 #define MLXSW_REG_MCC_LEN 0x1C 10437 10438 MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN); 10439 10440 enum mlxsw_reg_mcc_instruction { 10441 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01, 10442 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02, 10443 MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03, 10444 MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04, 10445 MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06, 10446 MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08, 10447 }; 10448 10449 /* reg_mcc_instruction 10450 * Command to be executed by the FSM. 10451 * Applicable for write operation only. 10452 * Access: RW 10453 */ 10454 MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8); 10455 10456 /* reg_mcc_component_index 10457 * Index of the accessed component. Applicable only for commands that 10458 * refer to components. Otherwise, this field is reserved. 10459 * Access: Index 10460 */ 10461 MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16); 10462 10463 /* reg_mcc_update_handle 10464 * Token representing the current flow executed by the FSM. 10465 * Access: WO 10466 */ 10467 MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24); 10468 10469 /* reg_mcc_error_code 10470 * Indicates the successful completion of the instruction, or the reason it 10471 * failed 10472 * Access: RO 10473 */ 10474 MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8); 10475 10476 /* reg_mcc_control_state 10477 * Current FSM state 10478 * Access: RO 10479 */ 10480 MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4); 10481 10482 /* reg_mcc_component_size 10483 * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying 10484 * the size may shorten the update time. Value 0x0 means that size is 10485 * unspecified. 10486 * Access: WO 10487 */ 10488 MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32); 10489 10490 static inline void mlxsw_reg_mcc_pack(char *payload, 10491 enum mlxsw_reg_mcc_instruction instr, 10492 u16 component_index, u32 update_handle, 10493 u32 component_size) 10494 { 10495 MLXSW_REG_ZERO(mcc, payload); 10496 mlxsw_reg_mcc_instruction_set(payload, instr); 10497 mlxsw_reg_mcc_component_index_set(payload, component_index); 10498 mlxsw_reg_mcc_update_handle_set(payload, update_handle); 10499 mlxsw_reg_mcc_component_size_set(payload, component_size); 10500 } 10501 10502 static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle, 10503 u8 *p_error_code, u8 *p_control_state) 10504 { 10505 if (p_update_handle) 10506 *p_update_handle = mlxsw_reg_mcc_update_handle_get(payload); 10507 if (p_error_code) 10508 *p_error_code = mlxsw_reg_mcc_error_code_get(payload); 10509 if (p_control_state) 10510 *p_control_state = mlxsw_reg_mcc_control_state_get(payload); 10511 } 10512 10513 /* MCDA - Management Component Data Access 10514 * --------------------------------------- 10515 * This register allows reading and writing a firmware component. 10516 */ 10517 #define MLXSW_REG_MCDA_ID 0x9063 10518 #define MLXSW_REG_MCDA_BASE_LEN 0x10 10519 #define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80 10520 #define MLXSW_REG_MCDA_LEN \ 10521 (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN) 10522 10523 MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN); 10524 10525 /* reg_mcda_update_handle 10526 * Token representing the current flow executed by the FSM. 10527 * Access: RW 10528 */ 10529 MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24); 10530 10531 /* reg_mcda_offset 10532 * Offset of accessed address relative to component start. Accesses must be in 10533 * accordance to log_mcda_word_size in MCQI reg. 10534 * Access: RW 10535 */ 10536 MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32); 10537 10538 /* reg_mcda_size 10539 * Size of the data accessed, given in bytes. 10540 * Access: RW 10541 */ 10542 MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16); 10543 10544 /* reg_mcda_data 10545 * Data block accessed. 10546 * Access: RW 10547 */ 10548 MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false); 10549 10550 static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle, 10551 u32 offset, u16 size, u8 *data) 10552 { 10553 int i; 10554 10555 MLXSW_REG_ZERO(mcda, payload); 10556 mlxsw_reg_mcda_update_handle_set(payload, update_handle); 10557 mlxsw_reg_mcda_offset_set(payload, offset); 10558 mlxsw_reg_mcda_size_set(payload, size); 10559 10560 for (i = 0; i < size / 4; i++) 10561 mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]); 10562 } 10563 10564 /* MCAM - Management Capabilities Mask Register 10565 * -------------------------------------------- 10566 * Reports the device supported management features. 10567 */ 10568 #define MLXSW_REG_MCAM_ID 0x907F 10569 #define MLXSW_REG_MCAM_LEN 0x48 10570 10571 MLXSW_REG_DEFINE(mcam, MLXSW_REG_MCAM_ID, MLXSW_REG_MCAM_LEN); 10572 10573 enum mlxsw_reg_mcam_feature_group { 10574 /* Enhanced features. */ 10575 MLXSW_REG_MCAM_FEATURE_GROUP_ENHANCED_FEATURES, 10576 }; 10577 10578 /* reg_mcam_feature_group 10579 * Feature list mask index. 10580 * Access: Index 10581 */ 10582 MLXSW_ITEM32(reg, mcam, feature_group, 0x00, 16, 8); 10583 10584 enum mlxsw_reg_mcam_mng_feature_cap_mask_bits { 10585 /* If set, MCIA supports 128 bytes payloads. Otherwise, 48 bytes. */ 10586 MLXSW_REG_MCAM_MCIA_128B = 34, 10587 }; 10588 10589 #define MLXSW_REG_BYTES_PER_DWORD 0x4 10590 10591 /* reg_mcam_mng_feature_cap_mask 10592 * Supported port's enhanced features. 10593 * Based on feature_group index. 10594 * When bit is set, the feature is supported in the device. 10595 * Access: RO 10596 */ 10597 #define MLXSW_REG_MCAM_MNG_FEATURE_CAP_MASK_DWORD(_dw_num, _offset) \ 10598 MLXSW_ITEM_BIT_ARRAY(reg, mcam, mng_feature_cap_mask_dw##_dw_num, \ 10599 _offset, MLXSW_REG_BYTES_PER_DWORD, 1) 10600 10601 /* The access to the bits in the field 'mng_feature_cap_mask' is not same to 10602 * other mask fields in other registers. In most of the cases bit #0 is the 10603 * first one in the last dword. In MCAM register, the first dword contains bits 10604 * #0-#31 and so on, so the access to the bits is simpler using bit array per 10605 * dword. Declare each dword of 'mng_feature_cap_mask' field separately. 10606 */ 10607 MLXSW_REG_MCAM_MNG_FEATURE_CAP_MASK_DWORD(0, 0x28); 10608 MLXSW_REG_MCAM_MNG_FEATURE_CAP_MASK_DWORD(1, 0x2C); 10609 MLXSW_REG_MCAM_MNG_FEATURE_CAP_MASK_DWORD(2, 0x30); 10610 MLXSW_REG_MCAM_MNG_FEATURE_CAP_MASK_DWORD(3, 0x34); 10611 10612 static inline void 10613 mlxsw_reg_mcam_pack(char *payload, enum mlxsw_reg_mcam_feature_group feat_group) 10614 { 10615 MLXSW_REG_ZERO(mcam, payload); 10616 mlxsw_reg_mcam_feature_group_set(payload, feat_group); 10617 } 10618 10619 static inline void 10620 mlxsw_reg_mcam_unpack(char *payload, 10621 enum mlxsw_reg_mcam_mng_feature_cap_mask_bits bit, 10622 bool *p_mng_feature_cap_val) 10623 { 10624 int offset = bit % (MLXSW_REG_BYTES_PER_DWORD * BITS_PER_BYTE); 10625 int dword = bit / (MLXSW_REG_BYTES_PER_DWORD * BITS_PER_BYTE); 10626 u8 (*getters[])(const char *, u16) = { 10627 mlxsw_reg_mcam_mng_feature_cap_mask_dw0_get, 10628 mlxsw_reg_mcam_mng_feature_cap_mask_dw1_get, 10629 mlxsw_reg_mcam_mng_feature_cap_mask_dw2_get, 10630 mlxsw_reg_mcam_mng_feature_cap_mask_dw3_get, 10631 }; 10632 10633 if (!WARN_ON_ONCE(dword >= ARRAY_SIZE(getters))) 10634 *p_mng_feature_cap_val = getters[dword](payload, offset); 10635 } 10636 10637 /* MPSC - Monitoring Packet Sampling Configuration Register 10638 * -------------------------------------------------------- 10639 * MPSC Register is used to configure the Packet Sampling mechanism. 10640 */ 10641 #define MLXSW_REG_MPSC_ID 0x9080 10642 #define MLXSW_REG_MPSC_LEN 0x1C 10643 10644 MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN); 10645 10646 /* reg_mpsc_local_port 10647 * Local port number 10648 * Not supported for CPU port 10649 * Access: Index 10650 */ 10651 MLXSW_ITEM32_LP(reg, mpsc, 0x00, 16, 0x00, 12); 10652 10653 /* reg_mpsc_e 10654 * Enable sampling on port local_port 10655 * Access: RW 10656 */ 10657 MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1); 10658 10659 #define MLXSW_REG_MPSC_RATE_MAX 3500000000UL 10660 10661 /* reg_mpsc_rate 10662 * Sampling rate = 1 out of rate packets (with randomization around 10663 * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX 10664 * Access: RW 10665 */ 10666 MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32); 10667 10668 static inline void mlxsw_reg_mpsc_pack(char *payload, u16 local_port, bool e, 10669 u32 rate) 10670 { 10671 MLXSW_REG_ZERO(mpsc, payload); 10672 mlxsw_reg_mpsc_local_port_set(payload, local_port); 10673 mlxsw_reg_mpsc_e_set(payload, e); 10674 mlxsw_reg_mpsc_rate_set(payload, rate); 10675 } 10676 10677 /* MGPC - Monitoring General Purpose Counter Set Register 10678 * The MGPC register retrieves and sets the General Purpose Counter Set. 10679 */ 10680 #define MLXSW_REG_MGPC_ID 0x9081 10681 #define MLXSW_REG_MGPC_LEN 0x18 10682 10683 MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN); 10684 10685 /* reg_mgpc_counter_set_type 10686 * Counter set type. 10687 * Access: OP 10688 */ 10689 MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8); 10690 10691 /* reg_mgpc_counter_index 10692 * Counter index. 10693 * Access: Index 10694 */ 10695 MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24); 10696 10697 enum mlxsw_reg_mgpc_opcode { 10698 /* Nop */ 10699 MLXSW_REG_MGPC_OPCODE_NOP = 0x00, 10700 /* Clear counters */ 10701 MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08, 10702 }; 10703 10704 /* reg_mgpc_opcode 10705 * Opcode. 10706 * Access: OP 10707 */ 10708 MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4); 10709 10710 /* reg_mgpc_byte_counter 10711 * Byte counter value. 10712 * Access: RW 10713 */ 10714 MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64); 10715 10716 /* reg_mgpc_packet_counter 10717 * Packet counter value. 10718 * Access: RW 10719 */ 10720 MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64); 10721 10722 static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index, 10723 enum mlxsw_reg_mgpc_opcode opcode, 10724 enum mlxsw_reg_flow_counter_set_type set_type) 10725 { 10726 MLXSW_REG_ZERO(mgpc, payload); 10727 mlxsw_reg_mgpc_counter_index_set(payload, counter_index); 10728 mlxsw_reg_mgpc_counter_set_type_set(payload, set_type); 10729 mlxsw_reg_mgpc_opcode_set(payload, opcode); 10730 } 10731 10732 /* MPRS - Monitoring Parsing State Register 10733 * ---------------------------------------- 10734 * The MPRS register is used for setting up the parsing for hash, 10735 * policy-engine and routing. 10736 */ 10737 #define MLXSW_REG_MPRS_ID 0x9083 10738 #define MLXSW_REG_MPRS_LEN 0x14 10739 10740 MLXSW_REG_DEFINE(mprs, MLXSW_REG_MPRS_ID, MLXSW_REG_MPRS_LEN); 10741 10742 /* reg_mprs_parsing_depth 10743 * Minimum parsing depth. 10744 * Need to enlarge parsing depth according to L3, MPLS, tunnels, ACL 10745 * rules, traps, hash, etc. Default is 96 bytes. Reserved when SwitchX-2. 10746 * Access: RW 10747 */ 10748 MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16); 10749 10750 /* reg_mprs_parsing_en 10751 * Parsing enable. 10752 * Bit 0 - Enable parsing of NVE of types VxLAN, VxLAN-GPE, GENEVE and 10753 * NVGRE. Default is enabled. Reserved when SwitchX-2. 10754 * Access: RW 10755 */ 10756 MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16); 10757 10758 /* reg_mprs_vxlan_udp_dport 10759 * VxLAN UDP destination port. 10760 * Used for identifying VxLAN packets and for dport field in 10761 * encapsulation. Default is 4789. 10762 * Access: RW 10763 */ 10764 MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16); 10765 10766 static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth, 10767 u16 vxlan_udp_dport) 10768 { 10769 MLXSW_REG_ZERO(mprs, payload); 10770 mlxsw_reg_mprs_parsing_depth_set(payload, parsing_depth); 10771 mlxsw_reg_mprs_parsing_en_set(payload, true); 10772 mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport); 10773 } 10774 10775 /* MOGCR - Monitoring Global Configuration Register 10776 * ------------------------------------------------ 10777 */ 10778 #define MLXSW_REG_MOGCR_ID 0x9086 10779 #define MLXSW_REG_MOGCR_LEN 0x20 10780 10781 MLXSW_REG_DEFINE(mogcr, MLXSW_REG_MOGCR_ID, MLXSW_REG_MOGCR_LEN); 10782 10783 /* reg_mogcr_ptp_iftc 10784 * PTP Ingress FIFO Trap Clear 10785 * The PTP_ING_FIFO trap provides MTPPTR with clr according 10786 * to this value. Default 0. 10787 * Reserved when IB switches and when SwitchX/-2, Spectrum-2 10788 * Access: RW 10789 */ 10790 MLXSW_ITEM32(reg, mogcr, ptp_iftc, 0x00, 1, 1); 10791 10792 /* reg_mogcr_ptp_eftc 10793 * PTP Egress FIFO Trap Clear 10794 * The PTP_EGR_FIFO trap provides MTPPTR with clr according 10795 * to this value. Default 0. 10796 * Reserved when IB switches and when SwitchX/-2, Spectrum-2 10797 * Access: RW 10798 */ 10799 MLXSW_ITEM32(reg, mogcr, ptp_eftc, 0x00, 0, 1); 10800 10801 /* reg_mogcr_mirroring_pid_base 10802 * Base policer id for mirroring policers. 10803 * Must have an even value (e.g. 1000, not 1001). 10804 * Reserved when SwitchX/-2, Switch-IB/2, Spectrum-1 and Quantum. 10805 * Access: RW 10806 */ 10807 MLXSW_ITEM32(reg, mogcr, mirroring_pid_base, 0x0C, 0, 14); 10808 10809 /* MPAGR - Monitoring Port Analyzer Global Register 10810 * ------------------------------------------------ 10811 * This register is used for global port analyzer configurations. 10812 * Note: This register is not supported by current FW versions for Spectrum-1. 10813 */ 10814 #define MLXSW_REG_MPAGR_ID 0x9089 10815 #define MLXSW_REG_MPAGR_LEN 0x0C 10816 10817 MLXSW_REG_DEFINE(mpagr, MLXSW_REG_MPAGR_ID, MLXSW_REG_MPAGR_LEN); 10818 10819 enum mlxsw_reg_mpagr_trigger { 10820 MLXSW_REG_MPAGR_TRIGGER_EGRESS, 10821 MLXSW_REG_MPAGR_TRIGGER_INGRESS, 10822 MLXSW_REG_MPAGR_TRIGGER_INGRESS_WRED, 10823 MLXSW_REG_MPAGR_TRIGGER_INGRESS_SHARED_BUFFER, 10824 MLXSW_REG_MPAGR_TRIGGER_INGRESS_ING_CONG, 10825 MLXSW_REG_MPAGR_TRIGGER_INGRESS_EGR_CONG, 10826 MLXSW_REG_MPAGR_TRIGGER_EGRESS_ECN, 10827 MLXSW_REG_MPAGR_TRIGGER_EGRESS_HIGH_LATENCY, 10828 }; 10829 10830 /* reg_mpagr_trigger 10831 * Mirror trigger. 10832 * Access: Index 10833 */ 10834 MLXSW_ITEM32(reg, mpagr, trigger, 0x00, 0, 4); 10835 10836 /* reg_mpagr_pa_id 10837 * Port analyzer ID. 10838 * Access: RW 10839 */ 10840 MLXSW_ITEM32(reg, mpagr, pa_id, 0x04, 0, 4); 10841 10842 #define MLXSW_REG_MPAGR_RATE_MAX 3500000000UL 10843 10844 /* reg_mpagr_probability_rate 10845 * Sampling rate. 10846 * Valid values are: 1 to 3.5*10^9 10847 * Value of 1 means "sample all". Default is 1. 10848 * Access: RW 10849 */ 10850 MLXSW_ITEM32(reg, mpagr, probability_rate, 0x08, 0, 32); 10851 10852 static inline void mlxsw_reg_mpagr_pack(char *payload, 10853 enum mlxsw_reg_mpagr_trigger trigger, 10854 u8 pa_id, u32 probability_rate) 10855 { 10856 MLXSW_REG_ZERO(mpagr, payload); 10857 mlxsw_reg_mpagr_trigger_set(payload, trigger); 10858 mlxsw_reg_mpagr_pa_id_set(payload, pa_id); 10859 mlxsw_reg_mpagr_probability_rate_set(payload, probability_rate); 10860 } 10861 10862 /* MOMTE - Monitoring Mirror Trigger Enable Register 10863 * ------------------------------------------------- 10864 * This register is used to configure the mirror enable for different mirror 10865 * reasons. 10866 */ 10867 #define MLXSW_REG_MOMTE_ID 0x908D 10868 #define MLXSW_REG_MOMTE_LEN 0x10 10869 10870 MLXSW_REG_DEFINE(momte, MLXSW_REG_MOMTE_ID, MLXSW_REG_MOMTE_LEN); 10871 10872 /* reg_momte_local_port 10873 * Local port number. 10874 * Access: Index 10875 */ 10876 MLXSW_ITEM32_LP(reg, momte, 0x00, 16, 0x00, 12); 10877 10878 enum mlxsw_reg_momte_type { 10879 MLXSW_REG_MOMTE_TYPE_WRED = 0x20, 10880 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS = 0x31, 10881 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS_DESCRIPTORS = 0x32, 10882 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_EGRESS_PORT = 0x33, 10883 MLXSW_REG_MOMTE_TYPE_ING_CONG = 0x40, 10884 MLXSW_REG_MOMTE_TYPE_EGR_CONG = 0x50, 10885 MLXSW_REG_MOMTE_TYPE_ECN = 0x60, 10886 MLXSW_REG_MOMTE_TYPE_HIGH_LATENCY = 0x70, 10887 }; 10888 10889 /* reg_momte_type 10890 * Type of mirroring. 10891 * Access: Index 10892 */ 10893 MLXSW_ITEM32(reg, momte, type, 0x04, 0, 8); 10894 10895 /* reg_momte_tclass_en 10896 * TClass/PG mirror enable. Each bit represents corresponding tclass. 10897 * 0: disable (default) 10898 * 1: enable 10899 * Access: RW 10900 */ 10901 MLXSW_ITEM_BIT_ARRAY(reg, momte, tclass_en, 0x08, 0x08, 1); 10902 10903 static inline void mlxsw_reg_momte_pack(char *payload, u16 local_port, 10904 enum mlxsw_reg_momte_type type) 10905 { 10906 MLXSW_REG_ZERO(momte, payload); 10907 mlxsw_reg_momte_local_port_set(payload, local_port); 10908 mlxsw_reg_momte_type_set(payload, type); 10909 } 10910 10911 /* MTPPPC - Time Precision Packet Port Configuration 10912 * ------------------------------------------------- 10913 * This register serves for configuration of which PTP messages should be 10914 * timestamped. This is a global configuration, despite the register name. 10915 * 10916 * Reserved when Spectrum-2. 10917 */ 10918 #define MLXSW_REG_MTPPPC_ID 0x9090 10919 #define MLXSW_REG_MTPPPC_LEN 0x28 10920 10921 MLXSW_REG_DEFINE(mtpppc, MLXSW_REG_MTPPPC_ID, MLXSW_REG_MTPPPC_LEN); 10922 10923 /* reg_mtpppc_ing_timestamp_message_type 10924 * Bitwise vector of PTP message types to timestamp at ingress. 10925 * MessageType field as defined by IEEE 1588 10926 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req) 10927 * Default all 0 10928 * Access: RW 10929 */ 10930 MLXSW_ITEM32(reg, mtpppc, ing_timestamp_message_type, 0x08, 0, 16); 10931 10932 /* reg_mtpppc_egr_timestamp_message_type 10933 * Bitwise vector of PTP message types to timestamp at egress. 10934 * MessageType field as defined by IEEE 1588 10935 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req) 10936 * Default all 0 10937 * Access: RW 10938 */ 10939 MLXSW_ITEM32(reg, mtpppc, egr_timestamp_message_type, 0x0C, 0, 16); 10940 10941 static inline void mlxsw_reg_mtpppc_pack(char *payload, u16 ing, u16 egr) 10942 { 10943 MLXSW_REG_ZERO(mtpppc, payload); 10944 mlxsw_reg_mtpppc_ing_timestamp_message_type_set(payload, ing); 10945 mlxsw_reg_mtpppc_egr_timestamp_message_type_set(payload, egr); 10946 } 10947 10948 /* MTPPTR - Time Precision Packet Timestamping Reading 10949 * --------------------------------------------------- 10950 * The MTPPTR is used for reading the per port PTP timestamp FIFO. 10951 * There is a trap for packets which are latched to the timestamp FIFO, thus the 10952 * SW knows which FIFO to read. Note that packets enter the FIFO before been 10953 * trapped. The sequence number is used to synchronize the timestamp FIFO 10954 * entries and the trapped packets. 10955 * Reserved when Spectrum-2. 10956 */ 10957 10958 #define MLXSW_REG_MTPPTR_ID 0x9091 10959 #define MLXSW_REG_MTPPTR_BASE_LEN 0x10 /* base length, without records */ 10960 #define MLXSW_REG_MTPPTR_REC_LEN 0x10 /* record length */ 10961 #define MLXSW_REG_MTPPTR_REC_MAX_COUNT 4 10962 #define MLXSW_REG_MTPPTR_LEN (MLXSW_REG_MTPPTR_BASE_LEN + \ 10963 MLXSW_REG_MTPPTR_REC_LEN * MLXSW_REG_MTPPTR_REC_MAX_COUNT) 10964 10965 MLXSW_REG_DEFINE(mtpptr, MLXSW_REG_MTPPTR_ID, MLXSW_REG_MTPPTR_LEN); 10966 10967 /* reg_mtpptr_local_port 10968 * Not supported for CPU port. 10969 * Access: Index 10970 */ 10971 MLXSW_ITEM32_LP(reg, mtpptr, 0x00, 16, 0x00, 12); 10972 10973 enum mlxsw_reg_mtpptr_dir { 10974 MLXSW_REG_MTPPTR_DIR_INGRESS, 10975 MLXSW_REG_MTPPTR_DIR_EGRESS, 10976 }; 10977 10978 /* reg_mtpptr_dir 10979 * Direction. 10980 * Access: Index 10981 */ 10982 MLXSW_ITEM32(reg, mtpptr, dir, 0x00, 0, 1); 10983 10984 /* reg_mtpptr_clr 10985 * Clear the records. 10986 * Access: OP 10987 */ 10988 MLXSW_ITEM32(reg, mtpptr, clr, 0x04, 31, 1); 10989 10990 /* reg_mtpptr_num_rec 10991 * Number of valid records in the response 10992 * Range 0.. cap_ptp_timestamp_fifo 10993 * Access: RO 10994 */ 10995 MLXSW_ITEM32(reg, mtpptr, num_rec, 0x08, 0, 4); 10996 10997 /* reg_mtpptr_rec_message_type 10998 * MessageType field as defined by IEEE 1588 Each bit corresponds to a value 10999 * (e.g. Bit0: Sync, Bit1: Delay_Req) 11000 * Access: RO 11001 */ 11002 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_message_type, 11003 MLXSW_REG_MTPPTR_BASE_LEN, 8, 4, 11004 MLXSW_REG_MTPPTR_REC_LEN, 0, false); 11005 11006 /* reg_mtpptr_rec_domain_number 11007 * DomainNumber field as defined by IEEE 1588 11008 * Access: RO 11009 */ 11010 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_domain_number, 11011 MLXSW_REG_MTPPTR_BASE_LEN, 0, 8, 11012 MLXSW_REG_MTPPTR_REC_LEN, 0, false); 11013 11014 /* reg_mtpptr_rec_sequence_id 11015 * SequenceId field as defined by IEEE 1588 11016 * Access: RO 11017 */ 11018 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_sequence_id, 11019 MLXSW_REG_MTPPTR_BASE_LEN, 0, 16, 11020 MLXSW_REG_MTPPTR_REC_LEN, 0x4, false); 11021 11022 /* reg_mtpptr_rec_timestamp_high 11023 * Timestamp of when the PTP packet has passed through the port Units of PLL 11024 * clock time. 11025 * For Spectrum-1 the PLL clock is 156.25Mhz and PLL clock time is 6.4nSec. 11026 * Access: RO 11027 */ 11028 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_high, 11029 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32, 11030 MLXSW_REG_MTPPTR_REC_LEN, 0x8, false); 11031 11032 /* reg_mtpptr_rec_timestamp_low 11033 * See rec_timestamp_high. 11034 * Access: RO 11035 */ 11036 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_low, 11037 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32, 11038 MLXSW_REG_MTPPTR_REC_LEN, 0xC, false); 11039 11040 static inline void mlxsw_reg_mtpptr_unpack(const char *payload, 11041 unsigned int rec, 11042 u8 *p_message_type, 11043 u8 *p_domain_number, 11044 u16 *p_sequence_id, 11045 u64 *p_timestamp) 11046 { 11047 u32 timestamp_high, timestamp_low; 11048 11049 *p_message_type = mlxsw_reg_mtpptr_rec_message_type_get(payload, rec); 11050 *p_domain_number = mlxsw_reg_mtpptr_rec_domain_number_get(payload, rec); 11051 *p_sequence_id = mlxsw_reg_mtpptr_rec_sequence_id_get(payload, rec); 11052 timestamp_high = mlxsw_reg_mtpptr_rec_timestamp_high_get(payload, rec); 11053 timestamp_low = mlxsw_reg_mtpptr_rec_timestamp_low_get(payload, rec); 11054 *p_timestamp = (u64)timestamp_high << 32 | timestamp_low; 11055 } 11056 11057 /* MTPTPT - Monitoring Precision Time Protocol Trap Register 11058 * --------------------------------------------------------- 11059 * This register is used for configuring under which trap to deliver PTP 11060 * packets depending on type of the packet. 11061 */ 11062 #define MLXSW_REG_MTPTPT_ID 0x9092 11063 #define MLXSW_REG_MTPTPT_LEN 0x08 11064 11065 MLXSW_REG_DEFINE(mtptpt, MLXSW_REG_MTPTPT_ID, MLXSW_REG_MTPTPT_LEN); 11066 11067 enum mlxsw_reg_mtptpt_trap_id { 11068 MLXSW_REG_MTPTPT_TRAP_ID_PTP0, 11069 MLXSW_REG_MTPTPT_TRAP_ID_PTP1, 11070 }; 11071 11072 /* reg_mtptpt_trap_id 11073 * Trap id. 11074 * Access: Index 11075 */ 11076 MLXSW_ITEM32(reg, mtptpt, trap_id, 0x00, 0, 4); 11077 11078 /* reg_mtptpt_message_type 11079 * Bitwise vector of PTP message types to trap. This is a necessary but 11080 * non-sufficient condition since need to enable also per port. See MTPPPC. 11081 * Message types are defined by IEEE 1588 Each bit corresponds to a value (e.g. 11082 * Bit0: Sync, Bit1: Delay_Req) 11083 */ 11084 MLXSW_ITEM32(reg, mtptpt, message_type, 0x04, 0, 16); 11085 11086 static inline void mlxsw_reg_mtptpt_pack(char *payload, 11087 enum mlxsw_reg_mtptpt_trap_id trap_id, 11088 u16 message_type) 11089 { 11090 MLXSW_REG_ZERO(mtptpt, payload); 11091 mlxsw_reg_mtptpt_trap_id_set(payload, trap_id); 11092 mlxsw_reg_mtptpt_message_type_set(payload, message_type); 11093 } 11094 11095 /* MTPCPC - Monitoring Time Precision Correction Port Configuration Register 11096 * ------------------------------------------------------------------------- 11097 */ 11098 #define MLXSW_REG_MTPCPC_ID 0x9093 11099 #define MLXSW_REG_MTPCPC_LEN 0x2C 11100 11101 MLXSW_REG_DEFINE(mtpcpc, MLXSW_REG_MTPCPC_ID, MLXSW_REG_MTPCPC_LEN); 11102 11103 /* reg_mtpcpc_pport 11104 * Per port: 11105 * 0: config is global. When reading - the local_port is 1. 11106 * 1: config is per port. 11107 * Access: Index 11108 */ 11109 MLXSW_ITEM32(reg, mtpcpc, pport, 0x00, 31, 1); 11110 11111 /* reg_mtpcpc_local_port 11112 * Local port number. 11113 * Supported to/from CPU port. 11114 * Reserved when pport = 0. 11115 * Access: Index 11116 */ 11117 MLXSW_ITEM32_LP(reg, mtpcpc, 0x00, 16, 0x00, 12); 11118 11119 /* reg_mtpcpc_ptp_trap_en 11120 * Enable PTP traps. 11121 * The trap_id is configured by MTPTPT. 11122 * Access: RW 11123 */ 11124 MLXSW_ITEM32(reg, mtpcpc, ptp_trap_en, 0x04, 0, 1); 11125 11126 /* reg_mtpcpc_ing_correction_message_type 11127 * Bitwise vector of PTP message types to update correction-field at ingress. 11128 * MessageType field as defined by IEEE 1588 Each bit corresponds to a value 11129 * (e.g. Bit0: Sync, Bit1: Delay_Req). Supported also from CPU port. 11130 * Default all 0 11131 * Access: RW 11132 */ 11133 MLXSW_ITEM32(reg, mtpcpc, ing_correction_message_type, 0x10, 0, 16); 11134 11135 /* reg_mtpcpc_egr_correction_message_type 11136 * Bitwise vector of PTP message types to update correction-field at egress. 11137 * MessageType field as defined by IEEE 1588 Each bit corresponds to a value 11138 * (e.g. Bit0: Sync, Bit1: Delay_Req). Supported also from CPU port. 11139 * Default all 0 11140 * Access: RW 11141 */ 11142 MLXSW_ITEM32(reg, mtpcpc, egr_correction_message_type, 0x14, 0, 16); 11143 11144 static inline void mlxsw_reg_mtpcpc_pack(char *payload, bool pport, 11145 u16 local_port, bool ptp_trap_en, 11146 u16 ing, u16 egr) 11147 { 11148 MLXSW_REG_ZERO(mtpcpc, payload); 11149 mlxsw_reg_mtpcpc_pport_set(payload, pport); 11150 mlxsw_reg_mtpcpc_local_port_set(payload, pport ? local_port : 0); 11151 mlxsw_reg_mtpcpc_ptp_trap_en_set(payload, ptp_trap_en); 11152 mlxsw_reg_mtpcpc_ing_correction_message_type_set(payload, ing); 11153 mlxsw_reg_mtpcpc_egr_correction_message_type_set(payload, egr); 11154 } 11155 11156 /* MFGD - Monitoring FW General Debug Register 11157 * ------------------------------------------- 11158 */ 11159 #define MLXSW_REG_MFGD_ID 0x90F0 11160 #define MLXSW_REG_MFGD_LEN 0x0C 11161 11162 MLXSW_REG_DEFINE(mfgd, MLXSW_REG_MFGD_ID, MLXSW_REG_MFGD_LEN); 11163 11164 /* reg_mfgd_fw_fatal_event_mode 11165 * 0 - don't check FW fatal (default) 11166 * 1 - check FW fatal - enable MFDE trap 11167 * Access: RW 11168 */ 11169 MLXSW_ITEM32(reg, mfgd, fatal_event_mode, 0x00, 9, 2); 11170 11171 /* reg_mfgd_trigger_test 11172 * Access: WO 11173 */ 11174 MLXSW_ITEM32(reg, mfgd, trigger_test, 0x00, 11, 1); 11175 11176 /* MGPIR - Management General Peripheral Information Register 11177 * ---------------------------------------------------------- 11178 * MGPIR register allows software to query the hardware and 11179 * firmware general information of peripheral entities. 11180 */ 11181 #define MLXSW_REG_MGPIR_ID 0x9100 11182 #define MLXSW_REG_MGPIR_LEN 0xA0 11183 11184 MLXSW_REG_DEFINE(mgpir, MLXSW_REG_MGPIR_ID, MLXSW_REG_MGPIR_LEN); 11185 11186 enum mlxsw_reg_mgpir_device_type { 11187 MLXSW_REG_MGPIR_DEVICE_TYPE_NONE, 11188 MLXSW_REG_MGPIR_DEVICE_TYPE_GEARBOX_DIE, 11189 }; 11190 11191 /* mgpir_slot_index 11192 * Slot index (0: Main board). 11193 * Access: Index 11194 */ 11195 MLXSW_ITEM32(reg, mgpir, slot_index, 0x00, 28, 4); 11196 11197 /* mgpir_device_type 11198 * Access: RO 11199 */ 11200 MLXSW_ITEM32(reg, mgpir, device_type, 0x00, 24, 4); 11201 11202 /* mgpir_devices_per_flash 11203 * Number of devices of device_type per flash (can be shared by few devices). 11204 * Access: RO 11205 */ 11206 MLXSW_ITEM32(reg, mgpir, devices_per_flash, 0x00, 16, 8); 11207 11208 /* mgpir_num_of_devices 11209 * Number of devices of device_type. 11210 * Access: RO 11211 */ 11212 MLXSW_ITEM32(reg, mgpir, num_of_devices, 0x00, 0, 8); 11213 11214 /* max_modules_per_slot 11215 * Maximum number of modules that can be connected per slot. 11216 * Access: RO 11217 */ 11218 MLXSW_ITEM32(reg, mgpir, max_modules_per_slot, 0x04, 16, 8); 11219 11220 /* mgpir_num_of_slots 11221 * Number of slots in the system. 11222 * Access: RO 11223 */ 11224 MLXSW_ITEM32(reg, mgpir, num_of_slots, 0x04, 8, 8); 11225 11226 /* mgpir_num_of_modules 11227 * Number of modules. 11228 * Access: RO 11229 */ 11230 MLXSW_ITEM32(reg, mgpir, num_of_modules, 0x04, 0, 8); 11231 11232 static inline void mlxsw_reg_mgpir_pack(char *payload, u8 slot_index) 11233 { 11234 MLXSW_REG_ZERO(mgpir, payload); 11235 mlxsw_reg_mgpir_slot_index_set(payload, slot_index); 11236 } 11237 11238 static inline void 11239 mlxsw_reg_mgpir_unpack(char *payload, u8 *num_of_devices, 11240 enum mlxsw_reg_mgpir_device_type *device_type, 11241 u8 *devices_per_flash, u8 *num_of_modules, 11242 u8 *num_of_slots) 11243 { 11244 if (num_of_devices) 11245 *num_of_devices = mlxsw_reg_mgpir_num_of_devices_get(payload); 11246 if (device_type) 11247 *device_type = mlxsw_reg_mgpir_device_type_get(payload); 11248 if (devices_per_flash) 11249 *devices_per_flash = 11250 mlxsw_reg_mgpir_devices_per_flash_get(payload); 11251 if (num_of_modules) 11252 *num_of_modules = mlxsw_reg_mgpir_num_of_modules_get(payload); 11253 if (num_of_slots) 11254 *num_of_slots = mlxsw_reg_mgpir_num_of_slots_get(payload); 11255 } 11256 11257 /* MBCT - Management Binary Code Transfer Register 11258 * ----------------------------------------------- 11259 * This register allows to transfer binary codes from the host to 11260 * the management FW by transferring it by chunks of maximum 1KB. 11261 */ 11262 #define MLXSW_REG_MBCT_ID 0x9120 11263 #define MLXSW_REG_MBCT_LEN 0x420 11264 11265 MLXSW_REG_DEFINE(mbct, MLXSW_REG_MBCT_ID, MLXSW_REG_MBCT_LEN); 11266 11267 /* reg_mbct_slot_index 11268 * Slot index. 0 is reserved. 11269 * Access: Index 11270 */ 11271 MLXSW_ITEM32(reg, mbct, slot_index, 0x00, 0, 4); 11272 11273 /* reg_mbct_data_size 11274 * Actual data field size in bytes for the current data transfer. 11275 * Access: WO 11276 */ 11277 MLXSW_ITEM32(reg, mbct, data_size, 0x04, 0, 11); 11278 11279 enum mlxsw_reg_mbct_op { 11280 MLXSW_REG_MBCT_OP_ERASE_INI_IMAGE = 1, 11281 MLXSW_REG_MBCT_OP_DATA_TRANSFER, /* Download */ 11282 MLXSW_REG_MBCT_OP_ACTIVATE, 11283 MLXSW_REG_MBCT_OP_CLEAR_ERRORS = 6, 11284 MLXSW_REG_MBCT_OP_QUERY_STATUS, 11285 }; 11286 11287 /* reg_mbct_op 11288 * Access: WO 11289 */ 11290 MLXSW_ITEM32(reg, mbct, op, 0x08, 28, 4); 11291 11292 /* reg_mbct_last 11293 * Indicates that the current data field is the last chunk of the INI. 11294 * Access: WO 11295 */ 11296 MLXSW_ITEM32(reg, mbct, last, 0x08, 26, 1); 11297 11298 /* reg_mbct_oee 11299 * Opcode Event Enable. When set a BCTOE event will be sent once the opcode 11300 * was executed and the fsm_state has changed. 11301 * Access: WO 11302 */ 11303 MLXSW_ITEM32(reg, mbct, oee, 0x08, 25, 1); 11304 11305 enum mlxsw_reg_mbct_status { 11306 /* Partial data transfer completed successfully and ready for next 11307 * data transfer. 11308 */ 11309 MLXSW_REG_MBCT_STATUS_PART_DATA = 2, 11310 MLXSW_REG_MBCT_STATUS_LAST_DATA, 11311 MLXSW_REG_MBCT_STATUS_ERASE_COMPLETE, 11312 /* Error - trying to erase INI while it being used. */ 11313 MLXSW_REG_MBCT_STATUS_ERROR_INI_IN_USE, 11314 /* Last data transfer completed, applying magic pattern. */ 11315 MLXSW_REG_MBCT_STATUS_ERASE_FAILED = 7, 11316 MLXSW_REG_MBCT_STATUS_INI_ERROR, 11317 MLXSW_REG_MBCT_STATUS_ACTIVATION_FAILED, 11318 MLXSW_REG_MBCT_STATUS_ILLEGAL_OPERATION = 11, 11319 }; 11320 11321 /* reg_mbct_status 11322 * Status. 11323 * Access: RO 11324 */ 11325 MLXSW_ITEM32(reg, mbct, status, 0x0C, 24, 5); 11326 11327 enum mlxsw_reg_mbct_fsm_state { 11328 MLXSW_REG_MBCT_FSM_STATE_INI_IN_USE = 5, 11329 MLXSW_REG_MBCT_FSM_STATE_ERROR, 11330 }; 11331 11332 /* reg_mbct_fsm_state 11333 * FSM state. 11334 * Access: RO 11335 */ 11336 MLXSW_ITEM32(reg, mbct, fsm_state, 0x0C, 16, 4); 11337 11338 #define MLXSW_REG_MBCT_DATA_LEN 1024 11339 11340 /* reg_mbct_data 11341 * Up to 1KB of data. 11342 * Access: WO 11343 */ 11344 MLXSW_ITEM_BUF(reg, mbct, data, 0x20, MLXSW_REG_MBCT_DATA_LEN); 11345 11346 static inline void mlxsw_reg_mbct_pack(char *payload, u8 slot_index, 11347 enum mlxsw_reg_mbct_op op, bool oee) 11348 { 11349 MLXSW_REG_ZERO(mbct, payload); 11350 mlxsw_reg_mbct_slot_index_set(payload, slot_index); 11351 mlxsw_reg_mbct_op_set(payload, op); 11352 mlxsw_reg_mbct_oee_set(payload, oee); 11353 } 11354 11355 static inline void mlxsw_reg_mbct_dt_pack(char *payload, 11356 u16 data_size, bool last, 11357 const char *data) 11358 { 11359 if (WARN_ON(data_size > MLXSW_REG_MBCT_DATA_LEN)) 11360 return; 11361 mlxsw_reg_mbct_data_size_set(payload, data_size); 11362 mlxsw_reg_mbct_last_set(payload, last); 11363 mlxsw_reg_mbct_data_memcpy_to(payload, data); 11364 } 11365 11366 static inline void 11367 mlxsw_reg_mbct_unpack(const char *payload, u8 *p_slot_index, 11368 enum mlxsw_reg_mbct_status *p_status, 11369 enum mlxsw_reg_mbct_fsm_state *p_fsm_state) 11370 { 11371 if (p_slot_index) 11372 *p_slot_index = mlxsw_reg_mbct_slot_index_get(payload); 11373 *p_status = mlxsw_reg_mbct_status_get(payload); 11374 if (p_fsm_state) 11375 *p_fsm_state = mlxsw_reg_mbct_fsm_state_get(payload); 11376 } 11377 11378 /* MDDT - Management DownStream Device Tunneling Register 11379 * ------------------------------------------------------ 11380 * This register allows to deliver query and request messages (PRM registers, 11381 * commands) to a DownStream device. 11382 */ 11383 #define MLXSW_REG_MDDT_ID 0x9160 11384 #define MLXSW_REG_MDDT_LEN 0x110 11385 11386 MLXSW_REG_DEFINE(mddt, MLXSW_REG_MDDT_ID, MLXSW_REG_MDDT_LEN); 11387 11388 /* reg_mddt_slot_index 11389 * Slot index. 11390 * Access: Index 11391 */ 11392 MLXSW_ITEM32(reg, mddt, slot_index, 0x00, 8, 4); 11393 11394 /* reg_mddt_device_index 11395 * Device index. 11396 * Access: Index 11397 */ 11398 MLXSW_ITEM32(reg, mddt, device_index, 0x00, 0, 8); 11399 11400 /* reg_mddt_read_size 11401 * Read size in D-Words. 11402 * Access: OP 11403 */ 11404 MLXSW_ITEM32(reg, mddt, read_size, 0x04, 24, 8); 11405 11406 /* reg_mddt_write_size 11407 * Write size in D-Words. 11408 * Access: OP 11409 */ 11410 MLXSW_ITEM32(reg, mddt, write_size, 0x04, 16, 8); 11411 11412 enum mlxsw_reg_mddt_status { 11413 MLXSW_REG_MDDT_STATUS_OK, 11414 }; 11415 11416 /* reg_mddt_status 11417 * Return code of the Downstream Device to the register that was sent. 11418 * Access: RO 11419 */ 11420 MLXSW_ITEM32(reg, mddt, status, 0x0C, 24, 8); 11421 11422 enum mlxsw_reg_mddt_method { 11423 MLXSW_REG_MDDT_METHOD_QUERY, 11424 MLXSW_REG_MDDT_METHOD_WRITE, 11425 }; 11426 11427 /* reg_mddt_method 11428 * Access: OP 11429 */ 11430 MLXSW_ITEM32(reg, mddt, method, 0x0C, 22, 2); 11431 11432 /* reg_mddt_register_id 11433 * Access: Index 11434 */ 11435 MLXSW_ITEM32(reg, mddt, register_id, 0x0C, 0, 16); 11436 11437 #define MLXSW_REG_MDDT_PAYLOAD_OFFSET 0x0C 11438 #define MLXSW_REG_MDDT_PRM_REGISTER_HEADER_LEN 4 11439 11440 static inline char *mlxsw_reg_mddt_inner_payload(char *payload) 11441 { 11442 return payload + MLXSW_REG_MDDT_PAYLOAD_OFFSET + 11443 MLXSW_REG_MDDT_PRM_REGISTER_HEADER_LEN; 11444 } 11445 11446 static inline void mlxsw_reg_mddt_pack(char *payload, u8 slot_index, 11447 u8 device_index, 11448 enum mlxsw_reg_mddt_method method, 11449 const struct mlxsw_reg_info *reg, 11450 char **inner_payload) 11451 { 11452 int len = reg->len + MLXSW_REG_MDDT_PRM_REGISTER_HEADER_LEN; 11453 11454 if (WARN_ON(len + MLXSW_REG_MDDT_PAYLOAD_OFFSET > MLXSW_REG_MDDT_LEN)) 11455 len = MLXSW_REG_MDDT_LEN - MLXSW_REG_MDDT_PAYLOAD_OFFSET; 11456 11457 MLXSW_REG_ZERO(mddt, payload); 11458 mlxsw_reg_mddt_slot_index_set(payload, slot_index); 11459 mlxsw_reg_mddt_device_index_set(payload, device_index); 11460 mlxsw_reg_mddt_method_set(payload, method); 11461 mlxsw_reg_mddt_register_id_set(payload, reg->id); 11462 mlxsw_reg_mddt_read_size_set(payload, len / 4); 11463 mlxsw_reg_mddt_write_size_set(payload, len / 4); 11464 *inner_payload = mlxsw_reg_mddt_inner_payload(payload); 11465 } 11466 11467 /* MDDQ - Management DownStream Device Query Register 11468 * -------------------------------------------------- 11469 * This register allows to query the DownStream device properties. The desired 11470 * information is chosen upon the query_type field and is delivered by 32B 11471 * of data blocks. 11472 */ 11473 #define MLXSW_REG_MDDQ_ID 0x9161 11474 #define MLXSW_REG_MDDQ_LEN 0x30 11475 11476 MLXSW_REG_DEFINE(mddq, MLXSW_REG_MDDQ_ID, MLXSW_REG_MDDQ_LEN); 11477 11478 /* reg_mddq_sie 11479 * Slot info event enable. 11480 * When set to '1', each change in the slot_info.provisioned / sr_valid / 11481 * active / ready will generate a DSDSC event. 11482 * Access: RW 11483 */ 11484 MLXSW_ITEM32(reg, mddq, sie, 0x00, 31, 1); 11485 11486 enum mlxsw_reg_mddq_query_type { 11487 MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_INFO = 1, 11488 MLXSW_REG_MDDQ_QUERY_TYPE_DEVICE_INFO, /* If there are no devices 11489 * on the slot, data_valid 11490 * will be '0'. 11491 */ 11492 MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_NAME, 11493 }; 11494 11495 /* reg_mddq_query_type 11496 * Access: Index 11497 */ 11498 MLXSW_ITEM32(reg, mddq, query_type, 0x00, 16, 8); 11499 11500 /* reg_mddq_slot_index 11501 * Slot index. 0 is reserved. 11502 * Access: Index 11503 */ 11504 MLXSW_ITEM32(reg, mddq, slot_index, 0x00, 0, 4); 11505 11506 /* reg_mddq_response_msg_seq 11507 * Response message sequential number. For a specific request, the response 11508 * message sequential number is the following one. In addition, the last 11509 * message should be 0. 11510 * Access: RO 11511 */ 11512 MLXSW_ITEM32(reg, mddq, response_msg_seq, 0x04, 16, 8); 11513 11514 /* reg_mddq_request_msg_seq 11515 * Request message sequential number. 11516 * The first message number should be 0. 11517 * Access: Index 11518 */ 11519 MLXSW_ITEM32(reg, mddq, request_msg_seq, 0x04, 0, 8); 11520 11521 /* reg_mddq_data_valid 11522 * If set, the data in the data field is valid and contain the information 11523 * for the queried index. 11524 * Access: RO 11525 */ 11526 MLXSW_ITEM32(reg, mddq, data_valid, 0x08, 31, 1); 11527 11528 /* reg_mddq_slot_info_provisioned 11529 * If set, the INI file is applied and the card is provisioned. 11530 * Access: RO 11531 */ 11532 MLXSW_ITEM32(reg, mddq, slot_info_provisioned, 0x10, 31, 1); 11533 11534 /* reg_mddq_slot_info_sr_valid 11535 * If set, Shift Register is valid (after being provisioned) and data 11536 * can be sent from the switch ASIC to the line-card CPLD over Shift-Register. 11537 * Access: RO 11538 */ 11539 MLXSW_ITEM32(reg, mddq, slot_info_sr_valid, 0x10, 30, 1); 11540 11541 enum mlxsw_reg_mddq_slot_info_ready { 11542 MLXSW_REG_MDDQ_SLOT_INFO_READY_NOT_READY, 11543 MLXSW_REG_MDDQ_SLOT_INFO_READY_READY, 11544 MLXSW_REG_MDDQ_SLOT_INFO_READY_ERROR, 11545 }; 11546 11547 /* reg_mddq_slot_info_lc_ready 11548 * If set, the LC is powered on, matching the INI version and a new FW 11549 * version can be burnt (if necessary). 11550 * Access: RO 11551 */ 11552 MLXSW_ITEM32(reg, mddq, slot_info_lc_ready, 0x10, 28, 2); 11553 11554 /* reg_mddq_slot_info_active 11555 * If set, the FW has completed the MDDC.device_enable command. 11556 * Access: RO 11557 */ 11558 MLXSW_ITEM32(reg, mddq, slot_info_active, 0x10, 27, 1); 11559 11560 /* reg_mddq_slot_info_hw_revision 11561 * Major user-configured version number of the current INI file. 11562 * Valid only when active or ready are '1'. 11563 * Access: RO 11564 */ 11565 MLXSW_ITEM32(reg, mddq, slot_info_hw_revision, 0x14, 16, 16); 11566 11567 /* reg_mddq_slot_info_ini_file_version 11568 * User-configured version number of the current INI file. 11569 * Valid only when active or lc_ready are '1'. 11570 * Access: RO 11571 */ 11572 MLXSW_ITEM32(reg, mddq, slot_info_ini_file_version, 0x14, 0, 16); 11573 11574 /* reg_mddq_slot_info_card_type 11575 * Access: RO 11576 */ 11577 MLXSW_ITEM32(reg, mddq, slot_info_card_type, 0x18, 0, 8); 11578 11579 static inline void 11580 __mlxsw_reg_mddq_pack(char *payload, u8 slot_index, 11581 enum mlxsw_reg_mddq_query_type query_type) 11582 { 11583 MLXSW_REG_ZERO(mddq, payload); 11584 mlxsw_reg_mddq_slot_index_set(payload, slot_index); 11585 mlxsw_reg_mddq_query_type_set(payload, query_type); 11586 } 11587 11588 static inline void 11589 mlxsw_reg_mddq_slot_info_pack(char *payload, u8 slot_index, bool sie) 11590 { 11591 __mlxsw_reg_mddq_pack(payload, slot_index, 11592 MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_INFO); 11593 mlxsw_reg_mddq_sie_set(payload, sie); 11594 } 11595 11596 static inline void 11597 mlxsw_reg_mddq_slot_info_unpack(const char *payload, u8 *p_slot_index, 11598 bool *p_provisioned, bool *p_sr_valid, 11599 enum mlxsw_reg_mddq_slot_info_ready *p_lc_ready, 11600 bool *p_active, u16 *p_hw_revision, 11601 u16 *p_ini_file_version, 11602 u8 *p_card_type) 11603 { 11604 *p_slot_index = mlxsw_reg_mddq_slot_index_get(payload); 11605 *p_provisioned = mlxsw_reg_mddq_slot_info_provisioned_get(payload); 11606 *p_sr_valid = mlxsw_reg_mddq_slot_info_sr_valid_get(payload); 11607 *p_lc_ready = mlxsw_reg_mddq_slot_info_lc_ready_get(payload); 11608 *p_active = mlxsw_reg_mddq_slot_info_active_get(payload); 11609 *p_hw_revision = mlxsw_reg_mddq_slot_info_hw_revision_get(payload); 11610 *p_ini_file_version = mlxsw_reg_mddq_slot_info_ini_file_version_get(payload); 11611 *p_card_type = mlxsw_reg_mddq_slot_info_card_type_get(payload); 11612 } 11613 11614 /* reg_mddq_device_info_flash_owner 11615 * If set, the device is the flash owner. Otherwise, a shared flash 11616 * is used by this device (another device is the flash owner). 11617 * Access: RO 11618 */ 11619 MLXSW_ITEM32(reg, mddq, device_info_flash_owner, 0x10, 30, 1); 11620 11621 /* reg_mddq_device_info_device_index 11622 * Device index. The first device should number 0. 11623 * Access: RO 11624 */ 11625 MLXSW_ITEM32(reg, mddq, device_info_device_index, 0x10, 0, 8); 11626 11627 /* reg_mddq_device_info_fw_major 11628 * Major FW version number. 11629 * Access: RO 11630 */ 11631 MLXSW_ITEM32(reg, mddq, device_info_fw_major, 0x14, 16, 16); 11632 11633 /* reg_mddq_device_info_fw_minor 11634 * Minor FW version number. 11635 * Access: RO 11636 */ 11637 MLXSW_ITEM32(reg, mddq, device_info_fw_minor, 0x18, 16, 16); 11638 11639 /* reg_mddq_device_info_fw_sub_minor 11640 * Sub-minor FW version number. 11641 * Access: RO 11642 */ 11643 MLXSW_ITEM32(reg, mddq, device_info_fw_sub_minor, 0x18, 0, 16); 11644 11645 static inline void 11646 mlxsw_reg_mddq_device_info_pack(char *payload, u8 slot_index, 11647 u8 request_msg_seq) 11648 { 11649 __mlxsw_reg_mddq_pack(payload, slot_index, 11650 MLXSW_REG_MDDQ_QUERY_TYPE_DEVICE_INFO); 11651 mlxsw_reg_mddq_request_msg_seq_set(payload, request_msg_seq); 11652 } 11653 11654 static inline void 11655 mlxsw_reg_mddq_device_info_unpack(const char *payload, u8 *p_response_msg_seq, 11656 bool *p_data_valid, bool *p_flash_owner, 11657 u8 *p_device_index, u16 *p_fw_major, 11658 u16 *p_fw_minor, u16 *p_fw_sub_minor) 11659 { 11660 *p_response_msg_seq = mlxsw_reg_mddq_response_msg_seq_get(payload); 11661 *p_data_valid = mlxsw_reg_mddq_data_valid_get(payload); 11662 *p_flash_owner = mlxsw_reg_mddq_device_info_flash_owner_get(payload); 11663 *p_device_index = mlxsw_reg_mddq_device_info_device_index_get(payload); 11664 *p_fw_major = mlxsw_reg_mddq_device_info_fw_major_get(payload); 11665 *p_fw_minor = mlxsw_reg_mddq_device_info_fw_minor_get(payload); 11666 *p_fw_sub_minor = mlxsw_reg_mddq_device_info_fw_sub_minor_get(payload); 11667 } 11668 11669 #define MLXSW_REG_MDDQ_SLOT_ASCII_NAME_LEN 20 11670 11671 /* reg_mddq_slot_ascii_name 11672 * Slot's ASCII name. 11673 * Access: RO 11674 */ 11675 MLXSW_ITEM_BUF(reg, mddq, slot_ascii_name, 0x10, 11676 MLXSW_REG_MDDQ_SLOT_ASCII_NAME_LEN); 11677 11678 static inline void 11679 mlxsw_reg_mddq_slot_name_pack(char *payload, u8 slot_index) 11680 { 11681 __mlxsw_reg_mddq_pack(payload, slot_index, 11682 MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_NAME); 11683 } 11684 11685 static inline void 11686 mlxsw_reg_mddq_slot_name_unpack(const char *payload, char *slot_ascii_name) 11687 { 11688 mlxsw_reg_mddq_slot_ascii_name_memcpy_from(payload, slot_ascii_name); 11689 } 11690 11691 /* MDDC - Management DownStream Device Control Register 11692 * ---------------------------------------------------- 11693 * This register allows to control downstream devices and line cards. 11694 */ 11695 #define MLXSW_REG_MDDC_ID 0x9163 11696 #define MLXSW_REG_MDDC_LEN 0x30 11697 11698 MLXSW_REG_DEFINE(mddc, MLXSW_REG_MDDC_ID, MLXSW_REG_MDDC_LEN); 11699 11700 /* reg_mddc_slot_index 11701 * Slot index. 0 is reserved. 11702 * Access: Index 11703 */ 11704 MLXSW_ITEM32(reg, mddc, slot_index, 0x00, 0, 4); 11705 11706 /* reg_mddc_rst 11707 * Reset request. 11708 * Access: OP 11709 */ 11710 MLXSW_ITEM32(reg, mddc, rst, 0x04, 29, 1); 11711 11712 /* reg_mddc_device_enable 11713 * When set, FW is the manager and allowed to program the downstream device. 11714 * Access: RW 11715 */ 11716 MLXSW_ITEM32(reg, mddc, device_enable, 0x04, 28, 1); 11717 11718 static inline void mlxsw_reg_mddc_pack(char *payload, u8 slot_index, bool rst, 11719 bool device_enable) 11720 { 11721 MLXSW_REG_ZERO(mddc, payload); 11722 mlxsw_reg_mddc_slot_index_set(payload, slot_index); 11723 mlxsw_reg_mddc_rst_set(payload, rst); 11724 mlxsw_reg_mddc_device_enable_set(payload, device_enable); 11725 } 11726 11727 /* MFDE - Monitoring FW Debug Register 11728 * ----------------------------------- 11729 */ 11730 #define MLXSW_REG_MFDE_ID 0x9200 11731 #define MLXSW_REG_MFDE_LEN 0x30 11732 11733 MLXSW_REG_DEFINE(mfde, MLXSW_REG_MFDE_ID, MLXSW_REG_MFDE_LEN); 11734 11735 /* reg_mfde_irisc_id 11736 * Which irisc triggered the event 11737 * Access: RO 11738 */ 11739 MLXSW_ITEM32(reg, mfde, irisc_id, 0x00, 24, 8); 11740 11741 enum mlxsw_reg_mfde_severity { 11742 /* Unrecoverable switch behavior */ 11743 MLXSW_REG_MFDE_SEVERITY_FATL = 2, 11744 /* Unexpected state with possible systemic failure */ 11745 MLXSW_REG_MFDE_SEVERITY_NRML = 3, 11746 /* Unexpected state without systemic failure */ 11747 MLXSW_REG_MFDE_SEVERITY_INTR = 5, 11748 }; 11749 11750 /* reg_mfde_severity 11751 * The severity of the event. 11752 * Access: RO 11753 */ 11754 MLXSW_ITEM32(reg, mfde, severity, 0x00, 16, 8); 11755 11756 enum mlxsw_reg_mfde_event_id { 11757 /* CRspace timeout */ 11758 MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO = 1, 11759 /* KVD insertion machine stopped */ 11760 MLXSW_REG_MFDE_EVENT_ID_KVD_IM_STOP, 11761 /* Triggered by MFGD.trigger_test */ 11762 MLXSW_REG_MFDE_EVENT_ID_TEST, 11763 /* Triggered when firmware hits an assert */ 11764 MLXSW_REG_MFDE_EVENT_ID_FW_ASSERT, 11765 /* Fatal error interrupt from hardware */ 11766 MLXSW_REG_MFDE_EVENT_ID_FATAL_CAUSE, 11767 }; 11768 11769 /* reg_mfde_event_id 11770 * Access: RO 11771 */ 11772 MLXSW_ITEM32(reg, mfde, event_id, 0x00, 0, 16); 11773 11774 enum mlxsw_reg_mfde_method { 11775 MLXSW_REG_MFDE_METHOD_QUERY, 11776 MLXSW_REG_MFDE_METHOD_WRITE, 11777 }; 11778 11779 /* reg_mfde_method 11780 * Access: RO 11781 */ 11782 MLXSW_ITEM32(reg, mfde, method, 0x04, 29, 1); 11783 11784 /* reg_mfde_long_process 11785 * Indicates if the command is in long_process mode. 11786 * Access: RO 11787 */ 11788 MLXSW_ITEM32(reg, mfde, long_process, 0x04, 28, 1); 11789 11790 enum mlxsw_reg_mfde_command_type { 11791 MLXSW_REG_MFDE_COMMAND_TYPE_MAD, 11792 MLXSW_REG_MFDE_COMMAND_TYPE_EMAD, 11793 MLXSW_REG_MFDE_COMMAND_TYPE_CMDIF, 11794 }; 11795 11796 /* reg_mfde_command_type 11797 * Access: RO 11798 */ 11799 MLXSW_ITEM32(reg, mfde, command_type, 0x04, 24, 2); 11800 11801 /* reg_mfde_reg_attr_id 11802 * EMAD - register id, MAD - attibute id 11803 * Access: RO 11804 */ 11805 MLXSW_ITEM32(reg, mfde, reg_attr_id, 0x04, 0, 16); 11806 11807 /* reg_mfde_crspace_to_log_address 11808 * crspace address accessed, which resulted in timeout. 11809 * Access: RO 11810 */ 11811 MLXSW_ITEM32(reg, mfde, crspace_to_log_address, 0x10, 0, 32); 11812 11813 /* reg_mfde_crspace_to_oe 11814 * 0 - New event 11815 * 1 - Old event, occurred before MFGD activation. 11816 * Access: RO 11817 */ 11818 MLXSW_ITEM32(reg, mfde, crspace_to_oe, 0x14, 24, 1); 11819 11820 /* reg_mfde_crspace_to_log_id 11821 * Which irisc triggered the timeout. 11822 * Access: RO 11823 */ 11824 MLXSW_ITEM32(reg, mfde, crspace_to_log_id, 0x14, 0, 4); 11825 11826 /* reg_mfde_crspace_to_log_ip 11827 * IP (instruction pointer) that triggered the timeout. 11828 * Access: RO 11829 */ 11830 MLXSW_ITEM64(reg, mfde, crspace_to_log_ip, 0x18, 0, 64); 11831 11832 /* reg_mfde_kvd_im_stop_oe 11833 * 0 - New event 11834 * 1 - Old event, occurred before MFGD activation. 11835 * Access: RO 11836 */ 11837 MLXSW_ITEM32(reg, mfde, kvd_im_stop_oe, 0x10, 24, 1); 11838 11839 /* reg_mfde_kvd_im_stop_pipes_mask 11840 * Bit per kvh pipe. 11841 * Access: RO 11842 */ 11843 MLXSW_ITEM32(reg, mfde, kvd_im_stop_pipes_mask, 0x10, 0, 16); 11844 11845 /* reg_mfde_fw_assert_var0-4 11846 * Variables passed to assert. 11847 * Access: RO 11848 */ 11849 MLXSW_ITEM32(reg, mfde, fw_assert_var0, 0x10, 0, 32); 11850 MLXSW_ITEM32(reg, mfde, fw_assert_var1, 0x14, 0, 32); 11851 MLXSW_ITEM32(reg, mfde, fw_assert_var2, 0x18, 0, 32); 11852 MLXSW_ITEM32(reg, mfde, fw_assert_var3, 0x1C, 0, 32); 11853 MLXSW_ITEM32(reg, mfde, fw_assert_var4, 0x20, 0, 32); 11854 11855 /* reg_mfde_fw_assert_existptr 11856 * The instruction pointer when assert was triggered. 11857 * Access: RO 11858 */ 11859 MLXSW_ITEM32(reg, mfde, fw_assert_existptr, 0x24, 0, 32); 11860 11861 /* reg_mfde_fw_assert_callra 11862 * The return address after triggering assert. 11863 * Access: RO 11864 */ 11865 MLXSW_ITEM32(reg, mfde, fw_assert_callra, 0x28, 0, 32); 11866 11867 /* reg_mfde_fw_assert_oe 11868 * 0 - New event 11869 * 1 - Old event, occurred before MFGD activation. 11870 * Access: RO 11871 */ 11872 MLXSW_ITEM32(reg, mfde, fw_assert_oe, 0x2C, 24, 1); 11873 11874 /* reg_mfde_fw_assert_tile_v 11875 * 0: The assert was from main 11876 * 1: The assert was from a tile 11877 * Access: RO 11878 */ 11879 MLXSW_ITEM32(reg, mfde, fw_assert_tile_v, 0x2C, 23, 1); 11880 11881 /* reg_mfde_fw_assert_tile_index 11882 * When tile_v=1, the tile_index that caused the assert. 11883 * Access: RO 11884 */ 11885 MLXSW_ITEM32(reg, mfde, fw_assert_tile_index, 0x2C, 16, 6); 11886 11887 /* reg_mfde_fw_assert_ext_synd 11888 * A generated one-to-one identifier which is specific per-assert. 11889 * Access: RO 11890 */ 11891 MLXSW_ITEM32(reg, mfde, fw_assert_ext_synd, 0x2C, 0, 16); 11892 11893 /* reg_mfde_fatal_cause_id 11894 * HW interrupt cause id. 11895 * Access: RO 11896 */ 11897 MLXSW_ITEM32(reg, mfde, fatal_cause_id, 0x10, 0, 18); 11898 11899 /* reg_mfde_fatal_cause_tile_v 11900 * 0: The assert was from main 11901 * 1: The assert was from a tile 11902 * Access: RO 11903 */ 11904 MLXSW_ITEM32(reg, mfde, fatal_cause_tile_v, 0x14, 23, 1); 11905 11906 /* reg_mfde_fatal_cause_tile_index 11907 * When tile_v=1, the tile_index that caused the assert. 11908 * Access: RO 11909 */ 11910 MLXSW_ITEM32(reg, mfde, fatal_cause_tile_index, 0x14, 16, 6); 11911 11912 /* TNGCR - Tunneling NVE General Configuration Register 11913 * ---------------------------------------------------- 11914 * The TNGCR register is used for setting up the NVE Tunneling configuration. 11915 */ 11916 #define MLXSW_REG_TNGCR_ID 0xA001 11917 #define MLXSW_REG_TNGCR_LEN 0x44 11918 11919 MLXSW_REG_DEFINE(tngcr, MLXSW_REG_TNGCR_ID, MLXSW_REG_TNGCR_LEN); 11920 11921 enum mlxsw_reg_tngcr_type { 11922 MLXSW_REG_TNGCR_TYPE_VXLAN, 11923 MLXSW_REG_TNGCR_TYPE_VXLAN_GPE, 11924 MLXSW_REG_TNGCR_TYPE_GENEVE, 11925 MLXSW_REG_TNGCR_TYPE_NVGRE, 11926 }; 11927 11928 /* reg_tngcr_type 11929 * Tunnel type for encapsulation and decapsulation. The types are mutually 11930 * exclusive. 11931 * Note: For Spectrum the NVE parsing must be enabled in MPRS. 11932 * Access: RW 11933 */ 11934 MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4); 11935 11936 /* reg_tngcr_nve_valid 11937 * The VTEP is valid. Allows adding FDB entries for tunnel encapsulation. 11938 * Access: RW 11939 */ 11940 MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1); 11941 11942 /* reg_tngcr_nve_ttl_uc 11943 * The TTL for NVE tunnel encapsulation underlay unicast packets. 11944 * Access: RW 11945 */ 11946 MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8); 11947 11948 /* reg_tngcr_nve_ttl_mc 11949 * The TTL for NVE tunnel encapsulation underlay multicast packets. 11950 * Access: RW 11951 */ 11952 MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8); 11953 11954 enum { 11955 /* Do not copy flow label. Calculate flow label using nve_flh. */ 11956 MLXSW_REG_TNGCR_FL_NO_COPY, 11957 /* Copy flow label from inner packet if packet is IPv6 and 11958 * encapsulation is by IPv6. Otherwise, calculate flow label using 11959 * nve_flh. 11960 */ 11961 MLXSW_REG_TNGCR_FL_COPY, 11962 }; 11963 11964 /* reg_tngcr_nve_flc 11965 * For NVE tunnel encapsulation: Flow label copy from inner packet. 11966 * Access: RW 11967 */ 11968 MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1); 11969 11970 enum { 11971 /* Flow label is static. In Spectrum this means '0'. Spectrum-2 11972 * uses {nve_fl_prefix, nve_fl_suffix}. 11973 */ 11974 MLXSW_REG_TNGCR_FL_NO_HASH, 11975 /* 8 LSBs of the flow label are calculated from ECMP hash of the 11976 * inner packet. 12 MSBs are configured by nve_fl_prefix. 11977 */ 11978 MLXSW_REG_TNGCR_FL_HASH, 11979 }; 11980 11981 /* reg_tngcr_nve_flh 11982 * NVE flow label hash. 11983 * Access: RW 11984 */ 11985 MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1); 11986 11987 /* reg_tngcr_nve_fl_prefix 11988 * NVE flow label prefix. Constant 12 MSBs of the flow label. 11989 * Access: RW 11990 */ 11991 MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12); 11992 11993 /* reg_tngcr_nve_fl_suffix 11994 * NVE flow label suffix. Constant 8 LSBs of the flow label. 11995 * Reserved when nve_flh=1 and for Spectrum. 11996 * Access: RW 11997 */ 11998 MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8); 11999 12000 enum { 12001 /* Source UDP port is fixed (default '0') */ 12002 MLXSW_REG_TNGCR_UDP_SPORT_NO_HASH, 12003 /* Source UDP port is calculated based on hash */ 12004 MLXSW_REG_TNGCR_UDP_SPORT_HASH, 12005 }; 12006 12007 /* reg_tngcr_nve_udp_sport_type 12008 * NVE UDP source port type. 12009 * Spectrum uses LAG hash (SLCRv2). Spectrum-2 uses ECMP hash (RECRv2). 12010 * When the source UDP port is calculated based on hash, then the 8 LSBs 12011 * are calculated from hash the 8 MSBs are configured by 12012 * nve_udp_sport_prefix. 12013 * Access: RW 12014 */ 12015 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1); 12016 12017 /* reg_tngcr_nve_udp_sport_prefix 12018 * NVE UDP source port prefix. Constant 8 MSBs of the UDP source port. 12019 * Reserved when NVE type is NVGRE. 12020 * Access: RW 12021 */ 12022 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8); 12023 12024 /* reg_tngcr_nve_group_size_mc 12025 * The amount of sequential linked lists of MC entries. The first linked 12026 * list is configured by SFD.underlay_mc_ptr. 12027 * Valid values: 1, 2, 4, 8, 16, 32, 64 12028 * The linked list are configured by TNUMT. 12029 * The hash is set by LAG hash. 12030 * Access: RW 12031 */ 12032 MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8); 12033 12034 /* reg_tngcr_nve_group_size_flood 12035 * The amount of sequential linked lists of flooding entries. The first 12036 * linked list is configured by SFMR.nve_tunnel_flood_ptr 12037 * Valid values: 1, 2, 4, 8, 16, 32, 64 12038 * The linked list are configured by TNUMT. 12039 * The hash is set by LAG hash. 12040 * Access: RW 12041 */ 12042 MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8); 12043 12044 /* reg_tngcr_learn_enable 12045 * During decapsulation, whether to learn from NVE port. 12046 * Reserved when Spectrum-2. See TNPC. 12047 * Access: RW 12048 */ 12049 MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1); 12050 12051 /* reg_tngcr_underlay_virtual_router 12052 * Underlay virtual router. 12053 * Reserved when Spectrum-2. 12054 * Access: RW 12055 */ 12056 MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16); 12057 12058 /* reg_tngcr_underlay_rif 12059 * Underlay ingress router interface. RIF type should be loopback generic. 12060 * Reserved when Spectrum. 12061 * Access: RW 12062 */ 12063 MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16); 12064 12065 /* reg_tngcr_usipv4 12066 * Underlay source IPv4 address of the NVE. 12067 * Access: RW 12068 */ 12069 MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32); 12070 12071 /* reg_tngcr_usipv6 12072 * Underlay source IPv6 address of the NVE. For Spectrum, must not be 12073 * modified under traffic of NVE tunneling encapsulation. 12074 * Access: RW 12075 */ 12076 MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16); 12077 12078 static inline void mlxsw_reg_tngcr_pack(char *payload, 12079 enum mlxsw_reg_tngcr_type type, 12080 bool valid, u8 ttl) 12081 { 12082 MLXSW_REG_ZERO(tngcr, payload); 12083 mlxsw_reg_tngcr_type_set(payload, type); 12084 mlxsw_reg_tngcr_nve_valid_set(payload, valid); 12085 mlxsw_reg_tngcr_nve_ttl_uc_set(payload, ttl); 12086 mlxsw_reg_tngcr_nve_ttl_mc_set(payload, ttl); 12087 mlxsw_reg_tngcr_nve_flc_set(payload, MLXSW_REG_TNGCR_FL_NO_COPY); 12088 mlxsw_reg_tngcr_nve_flh_set(payload, 0); 12089 mlxsw_reg_tngcr_nve_udp_sport_type_set(payload, 12090 MLXSW_REG_TNGCR_UDP_SPORT_HASH); 12091 mlxsw_reg_tngcr_nve_udp_sport_prefix_set(payload, 0); 12092 mlxsw_reg_tngcr_nve_group_size_mc_set(payload, 1); 12093 mlxsw_reg_tngcr_nve_group_size_flood_set(payload, 1); 12094 } 12095 12096 /* TNUMT - Tunneling NVE Underlay Multicast Table Register 12097 * ------------------------------------------------------- 12098 * The TNUMT register is for building the underlay MC table. It is used 12099 * for MC, flooding and BC traffic into the NVE tunnel. 12100 */ 12101 #define MLXSW_REG_TNUMT_ID 0xA003 12102 #define MLXSW_REG_TNUMT_LEN 0x20 12103 12104 MLXSW_REG_DEFINE(tnumt, MLXSW_REG_TNUMT_ID, MLXSW_REG_TNUMT_LEN); 12105 12106 enum mlxsw_reg_tnumt_record_type { 12107 MLXSW_REG_TNUMT_RECORD_TYPE_IPV4, 12108 MLXSW_REG_TNUMT_RECORD_TYPE_IPV6, 12109 MLXSW_REG_TNUMT_RECORD_TYPE_LABEL, 12110 }; 12111 12112 /* reg_tnumt_record_type 12113 * Record type. 12114 * Access: RW 12115 */ 12116 MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4); 12117 12118 /* reg_tnumt_tunnel_port 12119 * Tunnel port. 12120 * Access: RW 12121 */ 12122 MLXSW_ITEM32(reg, tnumt, tunnel_port, 0x00, 24, 4); 12123 12124 /* reg_tnumt_underlay_mc_ptr 12125 * Index to the underlay multicast table. 12126 * For Spectrum the index is to the KVD linear. 12127 * Access: Index 12128 */ 12129 MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24); 12130 12131 /* reg_tnumt_vnext 12132 * The next_underlay_mc_ptr is valid. 12133 * Access: RW 12134 */ 12135 MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1); 12136 12137 /* reg_tnumt_next_underlay_mc_ptr 12138 * The next index to the underlay multicast table. 12139 * Access: RW 12140 */ 12141 MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24); 12142 12143 /* reg_tnumt_record_size 12144 * Number of IP addresses in the record. 12145 * Range is 1..cap_max_nve_mc_entries_ipv{4,6} 12146 * Access: RW 12147 */ 12148 MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3); 12149 12150 /* reg_tnumt_udip 12151 * The underlay IPv4 addresses. udip[i] is reserved if i >= size 12152 * Access: RW 12153 */ 12154 MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false); 12155 12156 /* reg_tnumt_udip_ptr 12157 * The pointer to the underlay IPv6 addresses. udip_ptr[i] is reserved if 12158 * i >= size. The IPv6 addresses are configured by RIPS. 12159 * Access: RW 12160 */ 12161 MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false); 12162 12163 static inline void mlxsw_reg_tnumt_pack(char *payload, 12164 enum mlxsw_reg_tnumt_record_type type, 12165 enum mlxsw_reg_tunnel_port tport, 12166 u32 underlay_mc_ptr, bool vnext, 12167 u32 next_underlay_mc_ptr, 12168 u8 record_size) 12169 { 12170 MLXSW_REG_ZERO(tnumt, payload); 12171 mlxsw_reg_tnumt_record_type_set(payload, type); 12172 mlxsw_reg_tnumt_tunnel_port_set(payload, tport); 12173 mlxsw_reg_tnumt_underlay_mc_ptr_set(payload, underlay_mc_ptr); 12174 mlxsw_reg_tnumt_vnext_set(payload, vnext); 12175 mlxsw_reg_tnumt_next_underlay_mc_ptr_set(payload, next_underlay_mc_ptr); 12176 mlxsw_reg_tnumt_record_size_set(payload, record_size); 12177 } 12178 12179 /* TNQCR - Tunneling NVE QoS Configuration Register 12180 * ------------------------------------------------ 12181 * The TNQCR register configures how QoS is set in encapsulation into the 12182 * underlay network. 12183 */ 12184 #define MLXSW_REG_TNQCR_ID 0xA010 12185 #define MLXSW_REG_TNQCR_LEN 0x0C 12186 12187 MLXSW_REG_DEFINE(tnqcr, MLXSW_REG_TNQCR_ID, MLXSW_REG_TNQCR_LEN); 12188 12189 /* reg_tnqcr_enc_set_dscp 12190 * For encapsulation: How to set DSCP field: 12191 * 0 - Copy the DSCP from the overlay (inner) IP header to the underlay 12192 * (outer) IP header. If there is no IP header, use TNQDR.dscp 12193 * 1 - Set the DSCP field as TNQDR.dscp 12194 * Access: RW 12195 */ 12196 MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1); 12197 12198 static inline void mlxsw_reg_tnqcr_pack(char *payload) 12199 { 12200 MLXSW_REG_ZERO(tnqcr, payload); 12201 mlxsw_reg_tnqcr_enc_set_dscp_set(payload, 0); 12202 } 12203 12204 /* TNQDR - Tunneling NVE QoS Default Register 12205 * ------------------------------------------ 12206 * The TNQDR register configures the default QoS settings for NVE 12207 * encapsulation. 12208 */ 12209 #define MLXSW_REG_TNQDR_ID 0xA011 12210 #define MLXSW_REG_TNQDR_LEN 0x08 12211 12212 MLXSW_REG_DEFINE(tnqdr, MLXSW_REG_TNQDR_ID, MLXSW_REG_TNQDR_LEN); 12213 12214 /* reg_tnqdr_local_port 12215 * Local port number (receive port). CPU port is supported. 12216 * Access: Index 12217 */ 12218 MLXSW_ITEM32_LP(reg, tnqdr, 0x00, 16, 0x00, 12); 12219 12220 /* reg_tnqdr_dscp 12221 * For encapsulation, the default DSCP. 12222 * Access: RW 12223 */ 12224 MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6); 12225 12226 static inline void mlxsw_reg_tnqdr_pack(char *payload, u16 local_port) 12227 { 12228 MLXSW_REG_ZERO(tnqdr, payload); 12229 mlxsw_reg_tnqdr_local_port_set(payload, local_port); 12230 mlxsw_reg_tnqdr_dscp_set(payload, 0); 12231 } 12232 12233 /* TNEEM - Tunneling NVE Encapsulation ECN Mapping Register 12234 * -------------------------------------------------------- 12235 * The TNEEM register maps ECN of the IP header at the ingress to the 12236 * encapsulation to the ECN of the underlay network. 12237 */ 12238 #define MLXSW_REG_TNEEM_ID 0xA012 12239 #define MLXSW_REG_TNEEM_LEN 0x0C 12240 12241 MLXSW_REG_DEFINE(tneem, MLXSW_REG_TNEEM_ID, MLXSW_REG_TNEEM_LEN); 12242 12243 /* reg_tneem_overlay_ecn 12244 * ECN of the IP header in the overlay network. 12245 * Access: Index 12246 */ 12247 MLXSW_ITEM32(reg, tneem, overlay_ecn, 0x04, 24, 2); 12248 12249 /* reg_tneem_underlay_ecn 12250 * ECN of the IP header in the underlay network. 12251 * Access: RW 12252 */ 12253 MLXSW_ITEM32(reg, tneem, underlay_ecn, 0x04, 16, 2); 12254 12255 static inline void mlxsw_reg_tneem_pack(char *payload, u8 overlay_ecn, 12256 u8 underlay_ecn) 12257 { 12258 MLXSW_REG_ZERO(tneem, payload); 12259 mlxsw_reg_tneem_overlay_ecn_set(payload, overlay_ecn); 12260 mlxsw_reg_tneem_underlay_ecn_set(payload, underlay_ecn); 12261 } 12262 12263 /* TNDEM - Tunneling NVE Decapsulation ECN Mapping Register 12264 * -------------------------------------------------------- 12265 * The TNDEM register configures the actions that are done in the 12266 * decapsulation. 12267 */ 12268 #define MLXSW_REG_TNDEM_ID 0xA013 12269 #define MLXSW_REG_TNDEM_LEN 0x0C 12270 12271 MLXSW_REG_DEFINE(tndem, MLXSW_REG_TNDEM_ID, MLXSW_REG_TNDEM_LEN); 12272 12273 /* reg_tndem_underlay_ecn 12274 * ECN field of the IP header in the underlay network. 12275 * Access: Index 12276 */ 12277 MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2); 12278 12279 /* reg_tndem_overlay_ecn 12280 * ECN field of the IP header in the overlay network. 12281 * Access: Index 12282 */ 12283 MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2); 12284 12285 /* reg_tndem_eip_ecn 12286 * Egress IP ECN. ECN field of the IP header of the packet which goes out 12287 * from the decapsulation. 12288 * Access: RW 12289 */ 12290 MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2); 12291 12292 /* reg_tndem_trap_en 12293 * Trap enable: 12294 * 0 - No trap due to decap ECN 12295 * 1 - Trap enable with trap_id 12296 * Access: RW 12297 */ 12298 MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4); 12299 12300 /* reg_tndem_trap_id 12301 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 12302 * Reserved when trap_en is '0'. 12303 * Access: RW 12304 */ 12305 MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9); 12306 12307 static inline void mlxsw_reg_tndem_pack(char *payload, u8 underlay_ecn, 12308 u8 overlay_ecn, u8 ecn, bool trap_en, 12309 u16 trap_id) 12310 { 12311 MLXSW_REG_ZERO(tndem, payload); 12312 mlxsw_reg_tndem_underlay_ecn_set(payload, underlay_ecn); 12313 mlxsw_reg_tndem_overlay_ecn_set(payload, overlay_ecn); 12314 mlxsw_reg_tndem_eip_ecn_set(payload, ecn); 12315 mlxsw_reg_tndem_trap_en_set(payload, trap_en); 12316 mlxsw_reg_tndem_trap_id_set(payload, trap_id); 12317 } 12318 12319 /* TNPC - Tunnel Port Configuration Register 12320 * ----------------------------------------- 12321 * The TNPC register is used for tunnel port configuration. 12322 * Reserved when Spectrum. 12323 */ 12324 #define MLXSW_REG_TNPC_ID 0xA020 12325 #define MLXSW_REG_TNPC_LEN 0x18 12326 12327 MLXSW_REG_DEFINE(tnpc, MLXSW_REG_TNPC_ID, MLXSW_REG_TNPC_LEN); 12328 12329 /* reg_tnpc_tunnel_port 12330 * Tunnel port. 12331 * Access: Index 12332 */ 12333 MLXSW_ITEM32(reg, tnpc, tunnel_port, 0x00, 0, 4); 12334 12335 /* reg_tnpc_learn_enable_v6 12336 * During IPv6 underlay decapsulation, whether to learn from tunnel port. 12337 * Access: RW 12338 */ 12339 MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1); 12340 12341 /* reg_tnpc_learn_enable_v4 12342 * During IPv4 underlay decapsulation, whether to learn from tunnel port. 12343 * Access: RW 12344 */ 12345 MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1); 12346 12347 static inline void mlxsw_reg_tnpc_pack(char *payload, 12348 enum mlxsw_reg_tunnel_port tport, 12349 bool learn_enable) 12350 { 12351 MLXSW_REG_ZERO(tnpc, payload); 12352 mlxsw_reg_tnpc_tunnel_port_set(payload, tport); 12353 mlxsw_reg_tnpc_learn_enable_v4_set(payload, learn_enable); 12354 mlxsw_reg_tnpc_learn_enable_v6_set(payload, learn_enable); 12355 } 12356 12357 /* TIGCR - Tunneling IPinIP General Configuration Register 12358 * ------------------------------------------------------- 12359 * The TIGCR register is used for setting up the IPinIP Tunnel configuration. 12360 */ 12361 #define MLXSW_REG_TIGCR_ID 0xA801 12362 #define MLXSW_REG_TIGCR_LEN 0x10 12363 12364 MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN); 12365 12366 /* reg_tigcr_ipip_ttlc 12367 * For IPinIP Tunnel encapsulation: whether to copy the ttl from the packet 12368 * header. 12369 * Access: RW 12370 */ 12371 MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1); 12372 12373 /* reg_tigcr_ipip_ttl_uc 12374 * The TTL for IPinIP Tunnel encapsulation of unicast packets if 12375 * reg_tigcr_ipip_ttlc is unset. 12376 * Access: RW 12377 */ 12378 MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8); 12379 12380 static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc) 12381 { 12382 MLXSW_REG_ZERO(tigcr, payload); 12383 mlxsw_reg_tigcr_ttlc_set(payload, ttlc); 12384 mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc); 12385 } 12386 12387 /* TIEEM - Tunneling IPinIP Encapsulation ECN Mapping Register 12388 * ----------------------------------------------------------- 12389 * The TIEEM register maps ECN of the IP header at the ingress to the 12390 * encapsulation to the ECN of the underlay network. 12391 */ 12392 #define MLXSW_REG_TIEEM_ID 0xA812 12393 #define MLXSW_REG_TIEEM_LEN 0x0C 12394 12395 MLXSW_REG_DEFINE(tieem, MLXSW_REG_TIEEM_ID, MLXSW_REG_TIEEM_LEN); 12396 12397 /* reg_tieem_overlay_ecn 12398 * ECN of the IP header in the overlay network. 12399 * Access: Index 12400 */ 12401 MLXSW_ITEM32(reg, tieem, overlay_ecn, 0x04, 24, 2); 12402 12403 /* reg_tineem_underlay_ecn 12404 * ECN of the IP header in the underlay network. 12405 * Access: RW 12406 */ 12407 MLXSW_ITEM32(reg, tieem, underlay_ecn, 0x04, 16, 2); 12408 12409 static inline void mlxsw_reg_tieem_pack(char *payload, u8 overlay_ecn, 12410 u8 underlay_ecn) 12411 { 12412 MLXSW_REG_ZERO(tieem, payload); 12413 mlxsw_reg_tieem_overlay_ecn_set(payload, overlay_ecn); 12414 mlxsw_reg_tieem_underlay_ecn_set(payload, underlay_ecn); 12415 } 12416 12417 /* TIDEM - Tunneling IPinIP Decapsulation ECN Mapping Register 12418 * ----------------------------------------------------------- 12419 * The TIDEM register configures the actions that are done in the 12420 * decapsulation. 12421 */ 12422 #define MLXSW_REG_TIDEM_ID 0xA813 12423 #define MLXSW_REG_TIDEM_LEN 0x0C 12424 12425 MLXSW_REG_DEFINE(tidem, MLXSW_REG_TIDEM_ID, MLXSW_REG_TIDEM_LEN); 12426 12427 /* reg_tidem_underlay_ecn 12428 * ECN field of the IP header in the underlay network. 12429 * Access: Index 12430 */ 12431 MLXSW_ITEM32(reg, tidem, underlay_ecn, 0x04, 24, 2); 12432 12433 /* reg_tidem_overlay_ecn 12434 * ECN field of the IP header in the overlay network. 12435 * Access: Index 12436 */ 12437 MLXSW_ITEM32(reg, tidem, overlay_ecn, 0x04, 16, 2); 12438 12439 /* reg_tidem_eip_ecn 12440 * Egress IP ECN. ECN field of the IP header of the packet which goes out 12441 * from the decapsulation. 12442 * Access: RW 12443 */ 12444 MLXSW_ITEM32(reg, tidem, eip_ecn, 0x04, 8, 2); 12445 12446 /* reg_tidem_trap_en 12447 * Trap enable: 12448 * 0 - No trap due to decap ECN 12449 * 1 - Trap enable with trap_id 12450 * Access: RW 12451 */ 12452 MLXSW_ITEM32(reg, tidem, trap_en, 0x08, 28, 4); 12453 12454 /* reg_tidem_trap_id 12455 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 12456 * Reserved when trap_en is '0'. 12457 * Access: RW 12458 */ 12459 MLXSW_ITEM32(reg, tidem, trap_id, 0x08, 0, 9); 12460 12461 static inline void mlxsw_reg_tidem_pack(char *payload, u8 underlay_ecn, 12462 u8 overlay_ecn, u8 eip_ecn, 12463 bool trap_en, u16 trap_id) 12464 { 12465 MLXSW_REG_ZERO(tidem, payload); 12466 mlxsw_reg_tidem_underlay_ecn_set(payload, underlay_ecn); 12467 mlxsw_reg_tidem_overlay_ecn_set(payload, overlay_ecn); 12468 mlxsw_reg_tidem_eip_ecn_set(payload, eip_ecn); 12469 mlxsw_reg_tidem_trap_en_set(payload, trap_en); 12470 mlxsw_reg_tidem_trap_id_set(payload, trap_id); 12471 } 12472 12473 /* SBPR - Shared Buffer Pools Register 12474 * ----------------------------------- 12475 * The SBPR configures and retrieves the shared buffer pools and configuration. 12476 */ 12477 #define MLXSW_REG_SBPR_ID 0xB001 12478 #define MLXSW_REG_SBPR_LEN 0x14 12479 12480 MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN); 12481 12482 /* reg_sbpr_desc 12483 * When set, configures descriptor buffer. 12484 * Access: Index 12485 */ 12486 MLXSW_ITEM32(reg, sbpr, desc, 0x00, 31, 1); 12487 12488 /* shared direstion enum for SBPR, SBCM, SBPM */ 12489 enum mlxsw_reg_sbxx_dir { 12490 MLXSW_REG_SBXX_DIR_INGRESS, 12491 MLXSW_REG_SBXX_DIR_EGRESS, 12492 }; 12493 12494 /* reg_sbpr_dir 12495 * Direction. 12496 * Access: Index 12497 */ 12498 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2); 12499 12500 /* reg_sbpr_pool 12501 * Pool index. 12502 * Access: Index 12503 */ 12504 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4); 12505 12506 /* reg_sbpr_infi_size 12507 * Size is infinite. 12508 * Access: RW 12509 */ 12510 MLXSW_ITEM32(reg, sbpr, infi_size, 0x04, 31, 1); 12511 12512 /* reg_sbpr_size 12513 * Pool size in buffer cells. 12514 * Reserved when infi_size = 1. 12515 * Access: RW 12516 */ 12517 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24); 12518 12519 enum mlxsw_reg_sbpr_mode { 12520 MLXSW_REG_SBPR_MODE_STATIC, 12521 MLXSW_REG_SBPR_MODE_DYNAMIC, 12522 }; 12523 12524 /* reg_sbpr_mode 12525 * Pool quota calculation mode. 12526 * Access: RW 12527 */ 12528 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4); 12529 12530 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool, 12531 enum mlxsw_reg_sbxx_dir dir, 12532 enum mlxsw_reg_sbpr_mode mode, u32 size, 12533 bool infi_size) 12534 { 12535 MLXSW_REG_ZERO(sbpr, payload); 12536 mlxsw_reg_sbpr_pool_set(payload, pool); 12537 mlxsw_reg_sbpr_dir_set(payload, dir); 12538 mlxsw_reg_sbpr_mode_set(payload, mode); 12539 mlxsw_reg_sbpr_size_set(payload, size); 12540 mlxsw_reg_sbpr_infi_size_set(payload, infi_size); 12541 } 12542 12543 /* SBCM - Shared Buffer Class Management Register 12544 * ---------------------------------------------- 12545 * The SBCM register configures and retrieves the shared buffer allocation 12546 * and configuration according to Port-PG, including the binding to pool 12547 * and definition of the associated quota. 12548 */ 12549 #define MLXSW_REG_SBCM_ID 0xB002 12550 #define MLXSW_REG_SBCM_LEN 0x28 12551 12552 MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN); 12553 12554 /* reg_sbcm_local_port 12555 * Local port number. 12556 * For Ingress: excludes CPU port and Router port 12557 * For Egress: excludes IP Router 12558 * Access: Index 12559 */ 12560 MLXSW_ITEM32_LP(reg, sbcm, 0x00, 16, 0x00, 4); 12561 12562 /* reg_sbcm_pg_buff 12563 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress) 12564 * For PG buffer: range is 0..cap_max_pg_buffers - 1 12565 * For traffic class: range is 0..cap_max_tclass - 1 12566 * Note that when traffic class is in MC aware mode then the traffic 12567 * classes which are MC aware cannot be configured. 12568 * Access: Index 12569 */ 12570 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6); 12571 12572 /* reg_sbcm_dir 12573 * Direction. 12574 * Access: Index 12575 */ 12576 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2); 12577 12578 /* reg_sbcm_min_buff 12579 * Minimum buffer size for the limiter, in cells. 12580 * Access: RW 12581 */ 12582 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24); 12583 12584 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */ 12585 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1 12586 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14 12587 12588 /* reg_sbcm_infi_max 12589 * Max buffer is infinite. 12590 * Access: RW 12591 */ 12592 MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1); 12593 12594 /* reg_sbcm_max_buff 12595 * When the pool associated to the port-pg/tclass is configured to 12596 * static, Maximum buffer size for the limiter configured in cells. 12597 * When the pool associated to the port-pg/tclass is configured to 12598 * dynamic, the max_buff holds the "alpha" parameter, supporting 12599 * the following values: 12600 * 0: 0 12601 * i: (1/128)*2^(i-1), for i=1..14 12602 * 0xFF: Infinity 12603 * Reserved when infi_max = 1. 12604 * Access: RW 12605 */ 12606 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24); 12607 12608 /* reg_sbcm_pool 12609 * Association of the port-priority to a pool. 12610 * Access: RW 12611 */ 12612 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4); 12613 12614 static inline void mlxsw_reg_sbcm_pack(char *payload, u16 local_port, u8 pg_buff, 12615 enum mlxsw_reg_sbxx_dir dir, 12616 u32 min_buff, u32 max_buff, 12617 bool infi_max, u8 pool) 12618 { 12619 MLXSW_REG_ZERO(sbcm, payload); 12620 mlxsw_reg_sbcm_local_port_set(payload, local_port); 12621 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff); 12622 mlxsw_reg_sbcm_dir_set(payload, dir); 12623 mlxsw_reg_sbcm_min_buff_set(payload, min_buff); 12624 mlxsw_reg_sbcm_max_buff_set(payload, max_buff); 12625 mlxsw_reg_sbcm_infi_max_set(payload, infi_max); 12626 mlxsw_reg_sbcm_pool_set(payload, pool); 12627 } 12628 12629 /* SBPM - Shared Buffer Port Management Register 12630 * --------------------------------------------- 12631 * The SBPM register configures and retrieves the shared buffer allocation 12632 * and configuration according to Port-Pool, including the definition 12633 * of the associated quota. 12634 */ 12635 #define MLXSW_REG_SBPM_ID 0xB003 12636 #define MLXSW_REG_SBPM_LEN 0x28 12637 12638 MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN); 12639 12640 /* reg_sbpm_local_port 12641 * Local port number. 12642 * For Ingress: excludes CPU port and Router port 12643 * For Egress: excludes IP Router 12644 * Access: Index 12645 */ 12646 MLXSW_ITEM32_LP(reg, sbpm, 0x00, 16, 0x00, 12); 12647 12648 /* reg_sbpm_pool 12649 * The pool associated to quota counting on the local_port. 12650 * Access: Index 12651 */ 12652 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4); 12653 12654 /* reg_sbpm_dir 12655 * Direction. 12656 * Access: Index 12657 */ 12658 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2); 12659 12660 /* reg_sbpm_buff_occupancy 12661 * Current buffer occupancy in cells. 12662 * Access: RO 12663 */ 12664 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24); 12665 12666 /* reg_sbpm_clr 12667 * Clear Max Buffer Occupancy 12668 * When this bit is set, max_buff_occupancy field is cleared (and a 12669 * new max value is tracked from the time the clear was performed). 12670 * Access: OP 12671 */ 12672 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1); 12673 12674 /* reg_sbpm_max_buff_occupancy 12675 * Maximum value of buffer occupancy in cells monitored. Cleared by 12676 * writing to the clr field. 12677 * Access: RO 12678 */ 12679 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24); 12680 12681 /* reg_sbpm_min_buff 12682 * Minimum buffer size for the limiter, in cells. 12683 * Access: RW 12684 */ 12685 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24); 12686 12687 /* reg_sbpm_max_buff 12688 * When the pool associated to the port-pg/tclass is configured to 12689 * static, Maximum buffer size for the limiter configured in cells. 12690 * When the pool associated to the port-pg/tclass is configured to 12691 * dynamic, the max_buff holds the "alpha" parameter, supporting 12692 * the following values: 12693 * 0: 0 12694 * i: (1/128)*2^(i-1), for i=1..14 12695 * 0xFF: Infinity 12696 * Access: RW 12697 */ 12698 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24); 12699 12700 static inline void mlxsw_reg_sbpm_pack(char *payload, u16 local_port, u8 pool, 12701 enum mlxsw_reg_sbxx_dir dir, bool clr, 12702 u32 min_buff, u32 max_buff) 12703 { 12704 MLXSW_REG_ZERO(sbpm, payload); 12705 mlxsw_reg_sbpm_local_port_set(payload, local_port); 12706 mlxsw_reg_sbpm_pool_set(payload, pool); 12707 mlxsw_reg_sbpm_dir_set(payload, dir); 12708 mlxsw_reg_sbpm_clr_set(payload, clr); 12709 mlxsw_reg_sbpm_min_buff_set(payload, min_buff); 12710 mlxsw_reg_sbpm_max_buff_set(payload, max_buff); 12711 } 12712 12713 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy, 12714 u32 *p_max_buff_occupancy) 12715 { 12716 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload); 12717 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload); 12718 } 12719 12720 /* SBMM - Shared Buffer Multicast Management Register 12721 * -------------------------------------------------- 12722 * The SBMM register configures and retrieves the shared buffer allocation 12723 * and configuration for MC packets according to Switch-Priority, including 12724 * the binding to pool and definition of the associated quota. 12725 */ 12726 #define MLXSW_REG_SBMM_ID 0xB004 12727 #define MLXSW_REG_SBMM_LEN 0x28 12728 12729 MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN); 12730 12731 /* reg_sbmm_prio 12732 * Switch Priority. 12733 * Access: Index 12734 */ 12735 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4); 12736 12737 /* reg_sbmm_min_buff 12738 * Minimum buffer size for the limiter, in cells. 12739 * Access: RW 12740 */ 12741 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24); 12742 12743 /* reg_sbmm_max_buff 12744 * When the pool associated to the port-pg/tclass is configured to 12745 * static, Maximum buffer size for the limiter configured in cells. 12746 * When the pool associated to the port-pg/tclass is configured to 12747 * dynamic, the max_buff holds the "alpha" parameter, supporting 12748 * the following values: 12749 * 0: 0 12750 * i: (1/128)*2^(i-1), for i=1..14 12751 * 0xFF: Infinity 12752 * Access: RW 12753 */ 12754 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24); 12755 12756 /* reg_sbmm_pool 12757 * Association of the port-priority to a pool. 12758 * Access: RW 12759 */ 12760 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4); 12761 12762 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff, 12763 u32 max_buff, u8 pool) 12764 { 12765 MLXSW_REG_ZERO(sbmm, payload); 12766 mlxsw_reg_sbmm_prio_set(payload, prio); 12767 mlxsw_reg_sbmm_min_buff_set(payload, min_buff); 12768 mlxsw_reg_sbmm_max_buff_set(payload, max_buff); 12769 mlxsw_reg_sbmm_pool_set(payload, pool); 12770 } 12771 12772 /* SBSR - Shared Buffer Status Register 12773 * ------------------------------------ 12774 * The SBSR register retrieves the shared buffer occupancy according to 12775 * Port-Pool. Note that this register enables reading a large amount of data. 12776 * It is the user's responsibility to limit the amount of data to ensure the 12777 * response can match the maximum transfer unit. In case the response exceeds 12778 * the maximum transport unit, it will be truncated with no special notice. 12779 */ 12780 #define MLXSW_REG_SBSR_ID 0xB005 12781 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */ 12782 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */ 12783 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120 12784 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \ 12785 MLXSW_REG_SBSR_REC_LEN * \ 12786 MLXSW_REG_SBSR_REC_MAX_COUNT) 12787 12788 MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN); 12789 12790 /* reg_sbsr_clr 12791 * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy 12792 * field is cleared (and a new max value is tracked from the time the clear 12793 * was performed). 12794 * Access: OP 12795 */ 12796 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1); 12797 12798 #define MLXSW_REG_SBSR_NUM_PORTS_IN_PAGE 256 12799 12800 /* reg_sbsr_port_page 12801 * Determines the range of the ports specified in the 'ingress_port_mask' 12802 * and 'egress_port_mask' bit masks. 12803 * {ingress,egress}_port_mask[x] is (256 * port_page) + x 12804 * Access: Index 12805 */ 12806 MLXSW_ITEM32(reg, sbsr, port_page, 0x04, 0, 4); 12807 12808 /* reg_sbsr_ingress_port_mask 12809 * Bit vector for all ingress network ports. 12810 * Indicates which of the ports (for which the relevant bit is set) 12811 * are affected by the set operation. Configuration of any other port 12812 * does not change. 12813 * Access: Index 12814 */ 12815 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1); 12816 12817 /* reg_sbsr_pg_buff_mask 12818 * Bit vector for all switch priority groups. 12819 * Indicates which of the priorities (for which the relevant bit is set) 12820 * are affected by the set operation. Configuration of any other priority 12821 * does not change. 12822 * Range is 0..cap_max_pg_buffers - 1 12823 * Access: Index 12824 */ 12825 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1); 12826 12827 /* reg_sbsr_egress_port_mask 12828 * Bit vector for all egress network ports. 12829 * Indicates which of the ports (for which the relevant bit is set) 12830 * are affected by the set operation. Configuration of any other port 12831 * does not change. 12832 * Access: Index 12833 */ 12834 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1); 12835 12836 /* reg_sbsr_tclass_mask 12837 * Bit vector for all traffic classes. 12838 * Indicates which of the traffic classes (for which the relevant bit is 12839 * set) are affected by the set operation. Configuration of any other 12840 * traffic class does not change. 12841 * Range is 0..cap_max_tclass - 1 12842 * Access: Index 12843 */ 12844 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1); 12845 12846 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr) 12847 { 12848 MLXSW_REG_ZERO(sbsr, payload); 12849 mlxsw_reg_sbsr_clr_set(payload, clr); 12850 } 12851 12852 /* reg_sbsr_rec_buff_occupancy 12853 * Current buffer occupancy in cells. 12854 * Access: RO 12855 */ 12856 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 12857 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false); 12858 12859 /* reg_sbsr_rec_max_buff_occupancy 12860 * Maximum value of buffer occupancy in cells monitored. Cleared by 12861 * writing to the clr field. 12862 * Access: RO 12863 */ 12864 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 12865 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false); 12866 12867 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index, 12868 u32 *p_buff_occupancy, 12869 u32 *p_max_buff_occupancy) 12870 { 12871 *p_buff_occupancy = 12872 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index); 12873 *p_max_buff_occupancy = 12874 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index); 12875 } 12876 12877 /* SBIB - Shared Buffer Internal Buffer Register 12878 * --------------------------------------------- 12879 * The SBIB register configures per port buffers for internal use. The internal 12880 * buffers consume memory on the port buffers (note that the port buffers are 12881 * used also by PBMC). 12882 * 12883 * For Spectrum this is used for egress mirroring. 12884 */ 12885 #define MLXSW_REG_SBIB_ID 0xB006 12886 #define MLXSW_REG_SBIB_LEN 0x10 12887 12888 MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN); 12889 12890 /* reg_sbib_local_port 12891 * Local port number 12892 * Not supported for CPU port and router port 12893 * Access: Index 12894 */ 12895 MLXSW_ITEM32_LP(reg, sbib, 0x00, 16, 0x00, 12); 12896 12897 /* reg_sbib_buff_size 12898 * Units represented in cells 12899 * Allowed range is 0 to (cap_max_headroom_size - 1) 12900 * Default is 0 12901 * Access: RW 12902 */ 12903 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24); 12904 12905 static inline void mlxsw_reg_sbib_pack(char *payload, u16 local_port, 12906 u32 buff_size) 12907 { 12908 MLXSW_REG_ZERO(sbib, payload); 12909 mlxsw_reg_sbib_local_port_set(payload, local_port); 12910 mlxsw_reg_sbib_buff_size_set(payload, buff_size); 12911 } 12912 12913 static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { 12914 MLXSW_REG(sgcr), 12915 MLXSW_REG(spad), 12916 MLXSW_REG(sspr), 12917 MLXSW_REG(sfdat), 12918 MLXSW_REG(sfd), 12919 MLXSW_REG(sfn), 12920 MLXSW_REG(spms), 12921 MLXSW_REG(spvid), 12922 MLXSW_REG(spvm), 12923 MLXSW_REG(spaft), 12924 MLXSW_REG(sfgc), 12925 MLXSW_REG(sfdf), 12926 MLXSW_REG(sldr), 12927 MLXSW_REG(slcr), 12928 MLXSW_REG(slcor), 12929 MLXSW_REG(spmlr), 12930 MLXSW_REG(svfa), 12931 MLXSW_REG(spvtr), 12932 MLXSW_REG(svpe), 12933 MLXSW_REG(sfmr), 12934 MLXSW_REG(spvmlr), 12935 MLXSW_REG(spfsr), 12936 MLXSW_REG(spvc), 12937 MLXSW_REG(spevet), 12938 MLXSW_REG(smpe), 12939 MLXSW_REG(smid2), 12940 MLXSW_REG(cwtp), 12941 MLXSW_REG(cwtpm), 12942 MLXSW_REG(pgcr), 12943 MLXSW_REG(ppbt), 12944 MLXSW_REG(pacl), 12945 MLXSW_REG(pagt), 12946 MLXSW_REG(ptar), 12947 MLXSW_REG(pprr), 12948 MLXSW_REG(ppbs), 12949 MLXSW_REG(prcr), 12950 MLXSW_REG(pefa), 12951 MLXSW_REG(pemrbt), 12952 MLXSW_REG(ptce2), 12953 MLXSW_REG(perpt), 12954 MLXSW_REG(peabfe), 12955 MLXSW_REG(perar), 12956 MLXSW_REG(ptce3), 12957 MLXSW_REG(percr), 12958 MLXSW_REG(pererp), 12959 MLXSW_REG(iedr), 12960 MLXSW_REG(qpts), 12961 MLXSW_REG(qpcr), 12962 MLXSW_REG(qtct), 12963 MLXSW_REG(qeec), 12964 MLXSW_REG(qrwe), 12965 MLXSW_REG(qpdsm), 12966 MLXSW_REG(qpdp), 12967 MLXSW_REG(qpdpm), 12968 MLXSW_REG(qtctm), 12969 MLXSW_REG(qpsc), 12970 MLXSW_REG(pmlp), 12971 MLXSW_REG(pmtu), 12972 MLXSW_REG(ptys), 12973 MLXSW_REG(ppad), 12974 MLXSW_REG(paos), 12975 MLXSW_REG(pfcc), 12976 MLXSW_REG(ppcnt), 12977 MLXSW_REG(pptb), 12978 MLXSW_REG(pbmc), 12979 MLXSW_REG(pspa), 12980 MLXSW_REG(pmaos), 12981 MLXSW_REG(pplr), 12982 MLXSW_REG(pmtdb), 12983 MLXSW_REG(pmecr), 12984 MLXSW_REG(pmpe), 12985 MLXSW_REG(pddr), 12986 MLXSW_REG(pmmp), 12987 MLXSW_REG(pllp), 12988 MLXSW_REG(pmtm), 12989 MLXSW_REG(htgt), 12990 MLXSW_REG(hpkt), 12991 MLXSW_REG(rgcr), 12992 MLXSW_REG(ritr), 12993 MLXSW_REG(rtar), 12994 MLXSW_REG(ratr), 12995 MLXSW_REG(rtdp), 12996 MLXSW_REG(rips), 12997 MLXSW_REG(ratrad), 12998 MLXSW_REG(rdpm), 12999 MLXSW_REG(ricnt), 13000 MLXSW_REG(rrcr), 13001 MLXSW_REG(ralta), 13002 MLXSW_REG(ralst), 13003 MLXSW_REG(raltb), 13004 MLXSW_REG(ralue), 13005 MLXSW_REG(rauht), 13006 MLXSW_REG(raleu), 13007 MLXSW_REG(rauhtd), 13008 MLXSW_REG(rigr2), 13009 MLXSW_REG(recr2), 13010 MLXSW_REG(rmft2), 13011 MLXSW_REG(reiv), 13012 MLXSW_REG(mfcr), 13013 MLXSW_REG(mfsc), 13014 MLXSW_REG(mfsm), 13015 MLXSW_REG(mfsl), 13016 MLXSW_REG(fore), 13017 MLXSW_REG(mtcap), 13018 MLXSW_REG(mtmp), 13019 MLXSW_REG(mtwe), 13020 MLXSW_REG(mtbr), 13021 MLXSW_REG(mcia), 13022 MLXSW_REG(mpat), 13023 MLXSW_REG(mpar), 13024 MLXSW_REG(mgir), 13025 MLXSW_REG(mrsr), 13026 MLXSW_REG(mlcr), 13027 MLXSW_REG(mcion), 13028 MLXSW_REG(mtpps), 13029 MLXSW_REG(mtutc), 13030 MLXSW_REG(mcqi), 13031 MLXSW_REG(mcc), 13032 MLXSW_REG(mcda), 13033 MLXSW_REG(mcam), 13034 MLXSW_REG(mpsc), 13035 MLXSW_REG(mgpc), 13036 MLXSW_REG(mprs), 13037 MLXSW_REG(mogcr), 13038 MLXSW_REG(mpagr), 13039 MLXSW_REG(momte), 13040 MLXSW_REG(mtpppc), 13041 MLXSW_REG(mtpptr), 13042 MLXSW_REG(mtptpt), 13043 MLXSW_REG(mtpcpc), 13044 MLXSW_REG(mfgd), 13045 MLXSW_REG(mgpir), 13046 MLXSW_REG(mbct), 13047 MLXSW_REG(mddt), 13048 MLXSW_REG(mddq), 13049 MLXSW_REG(mddc), 13050 MLXSW_REG(mfde), 13051 MLXSW_REG(tngcr), 13052 MLXSW_REG(tnumt), 13053 MLXSW_REG(tnqcr), 13054 MLXSW_REG(tnqdr), 13055 MLXSW_REG(tneem), 13056 MLXSW_REG(tndem), 13057 MLXSW_REG(tnpc), 13058 MLXSW_REG(tigcr), 13059 MLXSW_REG(tieem), 13060 MLXSW_REG(tidem), 13061 MLXSW_REG(sbpr), 13062 MLXSW_REG(sbcm), 13063 MLXSW_REG(sbpm), 13064 MLXSW_REG(sbmm), 13065 MLXSW_REG(sbsr), 13066 MLXSW_REG(sbib), 13067 }; 13068 13069 static inline const char *mlxsw_reg_id_str(u16 reg_id) 13070 { 13071 const struct mlxsw_reg_info *reg_info; 13072 int i; 13073 13074 for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) { 13075 reg_info = mlxsw_reg_infos[i]; 13076 if (reg_info->id == reg_id) 13077 return reg_info->name; 13078 } 13079 return "*UNKNOWN*"; 13080 } 13081 13082 /* PUDE - Port Up / Down Event 13083 * --------------------------- 13084 * Reports the operational state change of a port. 13085 */ 13086 #define MLXSW_REG_PUDE_LEN 0x10 13087 13088 /* reg_pude_swid 13089 * Switch partition ID with which to associate the port. 13090 * Access: Index 13091 */ 13092 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8); 13093 13094 /* reg_pude_local_port 13095 * Local port number. 13096 * Access: Index 13097 */ 13098 MLXSW_ITEM32_LP(reg, pude, 0x00, 16, 0x00, 12); 13099 13100 /* reg_pude_admin_status 13101 * Port administrative state (the desired state). 13102 * 1 - Up. 13103 * 2 - Down. 13104 * 3 - Up once. This means that in case of link failure, the port won't go 13105 * into polling mode, but will wait to be re-enabled by software. 13106 * 4 - Disabled by system. Can only be set by hardware. 13107 * Access: RO 13108 */ 13109 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4); 13110 13111 /* reg_pude_oper_status 13112 * Port operatioanl state. 13113 * 1 - Up. 13114 * 2 - Down. 13115 * 3 - Down by port failure. This means that the device will not let the 13116 * port up again until explicitly specified by software. 13117 * Access: RO 13118 */ 13119 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4); 13120 13121 #endif 13122