1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #ifndef _MLXSW_REG_H 5 #define _MLXSW_REG_H 6 7 #include <linux/kernel.h> 8 #include <linux/string.h> 9 #include <linux/bitops.h> 10 #include <linux/if_vlan.h> 11 12 #include "item.h" 13 #include "port.h" 14 15 struct mlxsw_reg_info { 16 u16 id; 17 u16 len; /* In u8 */ 18 const char *name; 19 }; 20 21 #define MLXSW_REG_DEFINE(_name, _id, _len) \ 22 static const struct mlxsw_reg_info mlxsw_reg_##_name = { \ 23 .id = _id, \ 24 .len = _len, \ 25 .name = #_name, \ 26 } 27 28 #define MLXSW_REG(type) (&mlxsw_reg_##type) 29 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len 30 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len) 31 32 /* SGCR - Switch General Configuration Register 33 * -------------------------------------------- 34 * This register is used for configuration of the switch capabilities. 35 */ 36 #define MLXSW_REG_SGCR_ID 0x2000 37 #define MLXSW_REG_SGCR_LEN 0x10 38 39 MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN); 40 41 /* reg_sgcr_llb 42 * Link Local Broadcast (Default=0) 43 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast 44 * packets and ignore the IGMP snooping entries. 45 * Access: RW 46 */ 47 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1); 48 49 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb) 50 { 51 MLXSW_REG_ZERO(sgcr, payload); 52 mlxsw_reg_sgcr_llb_set(payload, !!llb); 53 } 54 55 /* SPAD - Switch Physical Address Register 56 * --------------------------------------- 57 * The SPAD register configures the switch physical MAC address. 58 */ 59 #define MLXSW_REG_SPAD_ID 0x2002 60 #define MLXSW_REG_SPAD_LEN 0x10 61 62 MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN); 63 64 /* reg_spad_base_mac 65 * Base MAC address for the switch partitions. 66 * Per switch partition MAC address is equal to: 67 * base_mac + swid 68 * Access: RW 69 */ 70 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6); 71 72 /* SMID - Switch Multicast ID 73 * -------------------------- 74 * The MID record maps from a MID (Multicast ID), which is a unique identifier 75 * of the multicast group within the stacking domain, into a list of local 76 * ports into which the packet is replicated. 77 */ 78 #define MLXSW_REG_SMID_ID 0x2007 79 #define MLXSW_REG_SMID_LEN 0x240 80 81 MLXSW_REG_DEFINE(smid, MLXSW_REG_SMID_ID, MLXSW_REG_SMID_LEN); 82 83 /* reg_smid_swid 84 * Switch partition ID. 85 * Access: Index 86 */ 87 MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8); 88 89 /* reg_smid_mid 90 * Multicast identifier - global identifier that represents the multicast group 91 * across all devices. 92 * Access: Index 93 */ 94 MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16); 95 96 /* reg_smid_port 97 * Local port memebership (1 bit per port). 98 * Access: RW 99 */ 100 MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1); 101 102 /* reg_smid_port_mask 103 * Local port mask (1 bit per port). 104 * Access: W 105 */ 106 MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1); 107 108 static inline void mlxsw_reg_smid_pack(char *payload, u16 mid, 109 u8 port, bool set) 110 { 111 MLXSW_REG_ZERO(smid, payload); 112 mlxsw_reg_smid_swid_set(payload, 0); 113 mlxsw_reg_smid_mid_set(payload, mid); 114 mlxsw_reg_smid_port_set(payload, port, set); 115 mlxsw_reg_smid_port_mask_set(payload, port, 1); 116 } 117 118 /* SSPR - Switch System Port Record Register 119 * ----------------------------------------- 120 * Configures the system port to local port mapping. 121 */ 122 #define MLXSW_REG_SSPR_ID 0x2008 123 #define MLXSW_REG_SSPR_LEN 0x8 124 125 MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN); 126 127 /* reg_sspr_m 128 * Master - if set, then the record describes the master system port. 129 * This is needed in case a local port is mapped into several system ports 130 * (for multipathing). That number will be reported as the source system 131 * port when packets are forwarded to the CPU. Only one master port is allowed 132 * per local port. 133 * 134 * Note: Must be set for Spectrum. 135 * Access: RW 136 */ 137 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1); 138 139 /* reg_sspr_local_port 140 * Local port number. 141 * 142 * Access: RW 143 */ 144 MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8); 145 146 /* reg_sspr_sub_port 147 * Virtual port within the physical port. 148 * Should be set to 0 when virtual ports are not enabled on the port. 149 * 150 * Access: RW 151 */ 152 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8); 153 154 /* reg_sspr_system_port 155 * Unique identifier within the stacking domain that represents all the ports 156 * that are available in the system (external ports). 157 * 158 * Currently, only single-ASIC configurations are supported, so we default to 159 * 1:1 mapping between system ports and local ports. 160 * Access: Index 161 */ 162 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16); 163 164 static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port) 165 { 166 MLXSW_REG_ZERO(sspr, payload); 167 mlxsw_reg_sspr_m_set(payload, 1); 168 mlxsw_reg_sspr_local_port_set(payload, local_port); 169 mlxsw_reg_sspr_sub_port_set(payload, 0); 170 mlxsw_reg_sspr_system_port_set(payload, local_port); 171 } 172 173 /* SFDAT - Switch Filtering Database Aging Time 174 * -------------------------------------------- 175 * Controls the Switch aging time. Aging time is able to be set per Switch 176 * Partition. 177 */ 178 #define MLXSW_REG_SFDAT_ID 0x2009 179 #define MLXSW_REG_SFDAT_LEN 0x8 180 181 MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN); 182 183 /* reg_sfdat_swid 184 * Switch partition ID. 185 * Access: Index 186 */ 187 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8); 188 189 /* reg_sfdat_age_time 190 * Aging time in seconds 191 * Min - 10 seconds 192 * Max - 1,000,000 seconds 193 * Default is 300 seconds. 194 * Access: RW 195 */ 196 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20); 197 198 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time) 199 { 200 MLXSW_REG_ZERO(sfdat, payload); 201 mlxsw_reg_sfdat_swid_set(payload, 0); 202 mlxsw_reg_sfdat_age_time_set(payload, age_time); 203 } 204 205 /* SFD - Switch Filtering Database 206 * ------------------------------- 207 * The following register defines the access to the filtering database. 208 * The register supports querying, adding, removing and modifying the database. 209 * The access is optimized for bulk updates in which case more than one 210 * FDB record is present in the same command. 211 */ 212 #define MLXSW_REG_SFD_ID 0x200A 213 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */ 214 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */ 215 #define MLXSW_REG_SFD_REC_MAX_COUNT 64 216 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \ 217 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT) 218 219 MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN); 220 221 /* reg_sfd_swid 222 * Switch partition ID for queries. Reserved on Write. 223 * Access: Index 224 */ 225 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8); 226 227 enum mlxsw_reg_sfd_op { 228 /* Dump entire FDB a (process according to record_locator) */ 229 MLXSW_REG_SFD_OP_QUERY_DUMP = 0, 230 /* Query records by {MAC, VID/FID} value */ 231 MLXSW_REG_SFD_OP_QUERY_QUERY = 1, 232 /* Query and clear activity. Query records by {MAC, VID/FID} value */ 233 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2, 234 /* Test. Response indicates if each of the records could be 235 * added to the FDB. 236 */ 237 MLXSW_REG_SFD_OP_WRITE_TEST = 0, 238 /* Add/modify. Aged-out records cannot be added. This command removes 239 * the learning notification of the {MAC, VID/FID}. Response includes 240 * the entries that were added to the FDB. 241 */ 242 MLXSW_REG_SFD_OP_WRITE_EDIT = 1, 243 /* Remove record by {MAC, VID/FID}. This command also removes 244 * the learning notification and aged-out notifications 245 * of the {MAC, VID/FID}. The response provides current (pre-removal) 246 * entries as non-aged-out. 247 */ 248 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2, 249 /* Remove learned notification by {MAC, VID/FID}. The response provides 250 * the removed learning notification. 251 */ 252 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2, 253 }; 254 255 /* reg_sfd_op 256 * Operation. 257 * Access: OP 258 */ 259 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2); 260 261 /* reg_sfd_record_locator 262 * Used for querying the FDB. Use record_locator=0 to initiate the 263 * query. When a record is returned, a new record_locator is 264 * returned to be used in the subsequent query. 265 * Reserved for database update. 266 * Access: Index 267 */ 268 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30); 269 270 /* reg_sfd_num_rec 271 * Request: Number of records to read/add/modify/remove 272 * Response: Number of records read/added/replaced/removed 273 * See above description for more details. 274 * Ranges 0..64 275 * Access: RW 276 */ 277 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8); 278 279 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op, 280 u32 record_locator) 281 { 282 MLXSW_REG_ZERO(sfd, payload); 283 mlxsw_reg_sfd_op_set(payload, op); 284 mlxsw_reg_sfd_record_locator_set(payload, record_locator); 285 } 286 287 /* reg_sfd_rec_swid 288 * Switch partition ID. 289 * Access: Index 290 */ 291 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8, 292 MLXSW_REG_SFD_REC_LEN, 0x00, false); 293 294 enum mlxsw_reg_sfd_rec_type { 295 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0, 296 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1, 297 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2, 298 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL = 0xC, 299 }; 300 301 /* reg_sfd_rec_type 302 * FDB record type. 303 * Access: RW 304 */ 305 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4, 306 MLXSW_REG_SFD_REC_LEN, 0x00, false); 307 308 enum mlxsw_reg_sfd_rec_policy { 309 /* Replacement disabled, aging disabled. */ 310 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0, 311 /* (mlag remote): Replacement enabled, aging disabled, 312 * learning notification enabled on this port. 313 */ 314 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1, 315 /* (ingress device): Replacement enabled, aging enabled. */ 316 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3, 317 }; 318 319 /* reg_sfd_rec_policy 320 * Policy. 321 * Access: RW 322 */ 323 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2, 324 MLXSW_REG_SFD_REC_LEN, 0x00, false); 325 326 /* reg_sfd_rec_a 327 * Activity. Set for new static entries. Set for static entries if a frame SMAC 328 * lookup hits on the entry. 329 * To clear the a bit, use "query and clear activity" op. 330 * Access: RO 331 */ 332 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1, 333 MLXSW_REG_SFD_REC_LEN, 0x00, false); 334 335 /* reg_sfd_rec_mac 336 * MAC address. 337 * Access: Index 338 */ 339 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6, 340 MLXSW_REG_SFD_REC_LEN, 0x02); 341 342 enum mlxsw_reg_sfd_rec_action { 343 /* forward */ 344 MLXSW_REG_SFD_REC_ACTION_NOP = 0, 345 /* forward and trap, trap_id is FDB_TRAP */ 346 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1, 347 /* trap and do not forward, trap_id is FDB_TRAP */ 348 MLXSW_REG_SFD_REC_ACTION_TRAP = 2, 349 /* forward to IP router */ 350 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3, 351 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15, 352 }; 353 354 /* reg_sfd_rec_action 355 * Action to apply on the packet. 356 * Note: Dynamic entries can only be configured with NOP action. 357 * Access: RW 358 */ 359 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4, 360 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 361 362 /* reg_sfd_uc_sub_port 363 * VEPA channel on local port. 364 * Valid only if local port is a non-stacking port. Must be 0 if multichannel 365 * VEPA is not enabled. 366 * Access: RW 367 */ 368 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 369 MLXSW_REG_SFD_REC_LEN, 0x08, false); 370 371 /* reg_sfd_uc_fid_vid 372 * Filtering ID or VLAN ID 373 * For SwitchX and SwitchX-2: 374 * - Dynamic entries (policy 2,3) use FID 375 * - Static entries (policy 0) use VID 376 * - When independent learning is configured, VID=FID 377 * For Spectrum: use FID for both Dynamic and Static entries. 378 * VID should not be used. 379 * Access: Index 380 */ 381 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 382 MLXSW_REG_SFD_REC_LEN, 0x08, false); 383 384 /* reg_sfd_uc_system_port 385 * Unique port identifier for the final destination of the packet. 386 * Access: RW 387 */ 388 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16, 389 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 390 391 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index, 392 enum mlxsw_reg_sfd_rec_type rec_type, 393 const char *mac, 394 enum mlxsw_reg_sfd_rec_action action) 395 { 396 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload); 397 398 if (rec_index >= num_rec) 399 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1); 400 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0); 401 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type); 402 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac); 403 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action); 404 } 405 406 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index, 407 enum mlxsw_reg_sfd_rec_policy policy, 408 const char *mac, u16 fid_vid, 409 enum mlxsw_reg_sfd_rec_action action, 410 u8 local_port) 411 { 412 mlxsw_reg_sfd_rec_pack(payload, rec_index, 413 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action); 414 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 415 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0); 416 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid); 417 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port); 418 } 419 420 static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index, 421 char *mac, u16 *p_fid_vid, 422 u8 *p_local_port) 423 { 424 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 425 *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index); 426 *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index); 427 } 428 429 /* reg_sfd_uc_lag_sub_port 430 * LAG sub port. 431 * Must be 0 if multichannel VEPA is not enabled. 432 * Access: RW 433 */ 434 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 435 MLXSW_REG_SFD_REC_LEN, 0x08, false); 436 437 /* reg_sfd_uc_lag_fid_vid 438 * Filtering ID or VLAN ID 439 * For SwitchX and SwitchX-2: 440 * - Dynamic entries (policy 2,3) use FID 441 * - Static entries (policy 0) use VID 442 * - When independent learning is configured, VID=FID 443 * For Spectrum: use FID for both Dynamic and Static entries. 444 * VID should not be used. 445 * Access: Index 446 */ 447 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 448 MLXSW_REG_SFD_REC_LEN, 0x08, false); 449 450 /* reg_sfd_uc_lag_lag_vid 451 * Indicates VID in case of vFIDs. Reserved for FIDs. 452 * Access: RW 453 */ 454 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, 455 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 456 457 /* reg_sfd_uc_lag_lag_id 458 * LAG Identifier - pointer into the LAG descriptor table. 459 * Access: RW 460 */ 461 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10, 462 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 463 464 static inline void 465 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index, 466 enum mlxsw_reg_sfd_rec_policy policy, 467 const char *mac, u16 fid_vid, 468 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid, 469 u16 lag_id) 470 { 471 mlxsw_reg_sfd_rec_pack(payload, rec_index, 472 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG, 473 mac, action); 474 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 475 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0); 476 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid); 477 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid); 478 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id); 479 } 480 481 static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index, 482 char *mac, u16 *p_vid, 483 u16 *p_lag_id) 484 { 485 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 486 *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index); 487 *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index); 488 } 489 490 /* reg_sfd_mc_pgi 491 * 492 * Multicast port group index - index into the port group table. 493 * Value 0x1FFF indicates the pgi should point to the MID entry. 494 * For Spectrum this value must be set to 0x1FFF 495 * Access: RW 496 */ 497 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13, 498 MLXSW_REG_SFD_REC_LEN, 0x08, false); 499 500 /* reg_sfd_mc_fid_vid 501 * 502 * Filtering ID or VLAN ID 503 * Access: Index 504 */ 505 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 506 MLXSW_REG_SFD_REC_LEN, 0x08, false); 507 508 /* reg_sfd_mc_mid 509 * 510 * Multicast identifier - global identifier that represents the multicast 511 * group across all devices. 512 * Access: RW 513 */ 514 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 515 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 516 517 static inline void 518 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index, 519 const char *mac, u16 fid_vid, 520 enum mlxsw_reg_sfd_rec_action action, u16 mid) 521 { 522 mlxsw_reg_sfd_rec_pack(payload, rec_index, 523 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action); 524 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF); 525 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid); 526 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid); 527 } 528 529 /* reg_sfd_uc_tunnel_uip_msb 530 * When protocol is IPv4, the most significant byte of the underlay IPv4 531 * destination IP. 532 * When protocol is IPv6, reserved. 533 * Access: RW 534 */ 535 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24, 536 8, MLXSW_REG_SFD_REC_LEN, 0x08, false); 537 538 /* reg_sfd_uc_tunnel_fid 539 * Filtering ID. 540 * Access: Index 541 */ 542 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 543 MLXSW_REG_SFD_REC_LEN, 0x08, false); 544 545 enum mlxsw_reg_sfd_uc_tunnel_protocol { 546 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4, 547 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6, 548 }; 549 550 /* reg_sfd_uc_tunnel_protocol 551 * IP protocol. 552 * Access: RW 553 */ 554 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27, 555 1, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 556 557 /* reg_sfd_uc_tunnel_uip_lsb 558 * When protocol is IPv4, the least significant bytes of the underlay 559 * IPv4 destination IP. 560 * When protocol is IPv6, pointer to the underlay IPv6 destination IP 561 * which is configured by RIPS. 562 * Access: RW 563 */ 564 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0, 565 24, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 566 567 static inline void 568 mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index, 569 enum mlxsw_reg_sfd_rec_policy policy, 570 const char *mac, u16 fid, 571 enum mlxsw_reg_sfd_rec_action action, u32 uip, 572 enum mlxsw_reg_sfd_uc_tunnel_protocol proto) 573 { 574 mlxsw_reg_sfd_rec_pack(payload, rec_index, 575 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL, mac, 576 action); 577 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 578 mlxsw_reg_sfd_uc_tunnel_uip_msb_set(payload, rec_index, uip >> 24); 579 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip); 580 mlxsw_reg_sfd_uc_tunnel_fid_set(payload, rec_index, fid); 581 mlxsw_reg_sfd_uc_tunnel_protocol_set(payload, rec_index, proto); 582 } 583 584 /* SFN - Switch FDB Notification Register 585 * ------------------------------------------- 586 * The switch provides notifications on newly learned FDB entries and 587 * aged out entries. The notifications can be polled by software. 588 */ 589 #define MLXSW_REG_SFN_ID 0x200B 590 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */ 591 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */ 592 #define MLXSW_REG_SFN_REC_MAX_COUNT 64 593 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \ 594 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT) 595 596 MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN); 597 598 /* reg_sfn_swid 599 * Switch partition ID. 600 * Access: Index 601 */ 602 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8); 603 604 /* reg_sfn_end 605 * Forces the current session to end. 606 * Access: OP 607 */ 608 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1); 609 610 /* reg_sfn_num_rec 611 * Request: Number of learned notifications and aged-out notification 612 * records requested. 613 * Response: Number of notification records returned (must be smaller 614 * than or equal to the value requested) 615 * Ranges 0..64 616 * Access: OP 617 */ 618 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8); 619 620 static inline void mlxsw_reg_sfn_pack(char *payload) 621 { 622 MLXSW_REG_ZERO(sfn, payload); 623 mlxsw_reg_sfn_swid_set(payload, 0); 624 mlxsw_reg_sfn_end_set(payload, 1); 625 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT); 626 } 627 628 /* reg_sfn_rec_swid 629 * Switch partition ID. 630 * Access: RO 631 */ 632 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8, 633 MLXSW_REG_SFN_REC_LEN, 0x00, false); 634 635 enum mlxsw_reg_sfn_rec_type { 636 /* MAC addresses learned on a regular port. */ 637 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5, 638 /* MAC addresses learned on a LAG port. */ 639 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6, 640 /* Aged-out MAC address on a regular port. */ 641 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7, 642 /* Aged-out MAC address on a LAG port. */ 643 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8, 644 /* Learned unicast tunnel record. */ 645 MLXSW_REG_SFN_REC_TYPE_LEARNED_UNICAST_TUNNEL = 0xD, 646 /* Aged-out unicast tunnel record. */ 647 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_UNICAST_TUNNEL = 0xE, 648 }; 649 650 /* reg_sfn_rec_type 651 * Notification record type. 652 * Access: RO 653 */ 654 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4, 655 MLXSW_REG_SFN_REC_LEN, 0x00, false); 656 657 /* reg_sfn_rec_mac 658 * MAC address. 659 * Access: RO 660 */ 661 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6, 662 MLXSW_REG_SFN_REC_LEN, 0x02); 663 664 /* reg_sfn_mac_sub_port 665 * VEPA channel on the local port. 666 * 0 if multichannel VEPA is not enabled. 667 * Access: RO 668 */ 669 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8, 670 MLXSW_REG_SFN_REC_LEN, 0x08, false); 671 672 /* reg_sfn_mac_fid 673 * Filtering identifier. 674 * Access: RO 675 */ 676 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16, 677 MLXSW_REG_SFN_REC_LEN, 0x08, false); 678 679 /* reg_sfn_mac_system_port 680 * Unique port identifier for the final destination of the packet. 681 * Access: RO 682 */ 683 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16, 684 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 685 686 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index, 687 char *mac, u16 *p_vid, 688 u8 *p_local_port) 689 { 690 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 691 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 692 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index); 693 } 694 695 /* reg_sfn_mac_lag_lag_id 696 * LAG ID (pointer into the LAG descriptor table). 697 * Access: RO 698 */ 699 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10, 700 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 701 702 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index, 703 char *mac, u16 *p_vid, 704 u16 *p_lag_id) 705 { 706 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 707 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 708 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index); 709 } 710 711 /* reg_sfn_uc_tunnel_uip_msb 712 * When protocol is IPv4, the most significant byte of the underlay IPv4 713 * address of the remote VTEP. 714 * When protocol is IPv6, reserved. 715 * Access: RO 716 */ 717 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_msb, MLXSW_REG_SFN_BASE_LEN, 24, 718 8, MLXSW_REG_SFN_REC_LEN, 0x08, false); 719 720 enum mlxsw_reg_sfn_uc_tunnel_protocol { 721 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV4, 722 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV6, 723 }; 724 725 /* reg_sfn_uc_tunnel_protocol 726 * IP protocol. 727 * Access: RO 728 */ 729 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_protocol, MLXSW_REG_SFN_BASE_LEN, 27, 730 1, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 731 732 /* reg_sfn_uc_tunnel_uip_lsb 733 * When protocol is IPv4, the least significant bytes of the underlay 734 * IPv4 address of the remote VTEP. 735 * When protocol is IPv6, ipv6_id to be queried from TNIPSD. 736 * Access: RO 737 */ 738 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0, 739 24, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 740 741 enum mlxsw_reg_sfn_tunnel_port { 742 MLXSW_REG_SFN_TUNNEL_PORT_NVE, 743 MLXSW_REG_SFN_TUNNEL_PORT_VPLS, 744 MLXSW_REG_SFN_TUNNEL_FLEX_TUNNEL0, 745 MLXSW_REG_SFN_TUNNEL_FLEX_TUNNEL1, 746 }; 747 748 /* reg_sfn_uc_tunnel_port 749 * Tunnel port. 750 * Reserved on Spectrum. 751 * Access: RO 752 */ 753 MLXSW_ITEM32_INDEXED(reg, sfn, tunnel_port, MLXSW_REG_SFN_BASE_LEN, 0, 4, 754 MLXSW_REG_SFN_REC_LEN, 0x10, false); 755 756 static inline void 757 mlxsw_reg_sfn_uc_tunnel_unpack(char *payload, int rec_index, char *mac, 758 u16 *p_fid, u32 *p_uip, 759 enum mlxsw_reg_sfn_uc_tunnel_protocol *p_proto) 760 { 761 u32 uip_msb, uip_lsb; 762 763 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 764 *p_fid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 765 uip_msb = mlxsw_reg_sfn_uc_tunnel_uip_msb_get(payload, rec_index); 766 uip_lsb = mlxsw_reg_sfn_uc_tunnel_uip_lsb_get(payload, rec_index); 767 *p_uip = uip_msb << 24 | uip_lsb; 768 *p_proto = mlxsw_reg_sfn_uc_tunnel_protocol_get(payload, rec_index); 769 } 770 771 /* SPMS - Switch Port MSTP/RSTP State Register 772 * ------------------------------------------- 773 * Configures the spanning tree state of a physical port. 774 */ 775 #define MLXSW_REG_SPMS_ID 0x200D 776 #define MLXSW_REG_SPMS_LEN 0x404 777 778 MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN); 779 780 /* reg_spms_local_port 781 * Local port number. 782 * Access: Index 783 */ 784 MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8); 785 786 enum mlxsw_reg_spms_state { 787 MLXSW_REG_SPMS_STATE_NO_CHANGE, 788 MLXSW_REG_SPMS_STATE_DISCARDING, 789 MLXSW_REG_SPMS_STATE_LEARNING, 790 MLXSW_REG_SPMS_STATE_FORWARDING, 791 }; 792 793 /* reg_spms_state 794 * Spanning tree state of each VLAN ID (VID) of the local port. 795 * 0 - Do not change spanning tree state (used only when writing). 796 * 1 - Discarding. No learning or forwarding to/from this port (default). 797 * 2 - Learning. Port is learning, but not forwarding. 798 * 3 - Forwarding. Port is learning and forwarding. 799 * Access: RW 800 */ 801 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2); 802 803 static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port) 804 { 805 MLXSW_REG_ZERO(spms, payload); 806 mlxsw_reg_spms_local_port_set(payload, local_port); 807 } 808 809 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid, 810 enum mlxsw_reg_spms_state state) 811 { 812 mlxsw_reg_spms_state_set(payload, vid, state); 813 } 814 815 /* SPVID - Switch Port VID 816 * ----------------------- 817 * The switch port VID configures the default VID for a port. 818 */ 819 #define MLXSW_REG_SPVID_ID 0x200E 820 #define MLXSW_REG_SPVID_LEN 0x08 821 822 MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN); 823 824 /* reg_spvid_local_port 825 * Local port number. 826 * Access: Index 827 */ 828 MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8); 829 830 /* reg_spvid_sub_port 831 * Virtual port within the physical port. 832 * Should be set to 0 when virtual ports are not enabled on the port. 833 * Access: Index 834 */ 835 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8); 836 837 /* reg_spvid_pvid 838 * Port default VID 839 * Access: RW 840 */ 841 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12); 842 843 static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid) 844 { 845 MLXSW_REG_ZERO(spvid, payload); 846 mlxsw_reg_spvid_local_port_set(payload, local_port); 847 mlxsw_reg_spvid_pvid_set(payload, pvid); 848 } 849 850 /* SPVM - Switch Port VLAN Membership 851 * ---------------------------------- 852 * The Switch Port VLAN Membership register configures the VLAN membership 853 * of a port in a VLAN denoted by VID. VLAN membership is managed per 854 * virtual port. The register can be used to add and remove VID(s) from a port. 855 */ 856 #define MLXSW_REG_SPVM_ID 0x200F 857 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */ 858 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */ 859 #define MLXSW_REG_SPVM_REC_MAX_COUNT 255 860 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \ 861 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT) 862 863 MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN); 864 865 /* reg_spvm_pt 866 * Priority tagged. If this bit is set, packets forwarded to the port with 867 * untagged VLAN membership (u bit is set) will be tagged with priority tag 868 * (VID=0) 869 * Access: RW 870 */ 871 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1); 872 873 /* reg_spvm_pte 874 * Priority Tagged Update Enable. On Write operations, if this bit is cleared, 875 * the pt bit will NOT be updated. To update the pt bit, pte must be set. 876 * Access: WO 877 */ 878 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1); 879 880 /* reg_spvm_local_port 881 * Local port number. 882 * Access: Index 883 */ 884 MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8); 885 886 /* reg_spvm_sub_port 887 * Virtual port within the physical port. 888 * Should be set to 0 when virtual ports are not enabled on the port. 889 * Access: Index 890 */ 891 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8); 892 893 /* reg_spvm_num_rec 894 * Number of records to update. Each record contains: i, e, u, vid. 895 * Access: OP 896 */ 897 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8); 898 899 /* reg_spvm_rec_i 900 * Ingress membership in VLAN ID. 901 * Access: Index 902 */ 903 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i, 904 MLXSW_REG_SPVM_BASE_LEN, 14, 1, 905 MLXSW_REG_SPVM_REC_LEN, 0, false); 906 907 /* reg_spvm_rec_e 908 * Egress membership in VLAN ID. 909 * Access: Index 910 */ 911 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e, 912 MLXSW_REG_SPVM_BASE_LEN, 13, 1, 913 MLXSW_REG_SPVM_REC_LEN, 0, false); 914 915 /* reg_spvm_rec_u 916 * Untagged - port is an untagged member - egress transmission uses untagged 917 * frames on VID<n> 918 * Access: Index 919 */ 920 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u, 921 MLXSW_REG_SPVM_BASE_LEN, 12, 1, 922 MLXSW_REG_SPVM_REC_LEN, 0, false); 923 924 /* reg_spvm_rec_vid 925 * Egress membership in VLAN ID. 926 * Access: Index 927 */ 928 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid, 929 MLXSW_REG_SPVM_BASE_LEN, 0, 12, 930 MLXSW_REG_SPVM_REC_LEN, 0, false); 931 932 static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port, 933 u16 vid_begin, u16 vid_end, 934 bool is_member, bool untagged) 935 { 936 int size = vid_end - vid_begin + 1; 937 int i; 938 939 MLXSW_REG_ZERO(spvm, payload); 940 mlxsw_reg_spvm_local_port_set(payload, local_port); 941 mlxsw_reg_spvm_num_rec_set(payload, size); 942 943 for (i = 0; i < size; i++) { 944 mlxsw_reg_spvm_rec_i_set(payload, i, is_member); 945 mlxsw_reg_spvm_rec_e_set(payload, i, is_member); 946 mlxsw_reg_spvm_rec_u_set(payload, i, untagged); 947 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i); 948 } 949 } 950 951 /* SPAFT - Switch Port Acceptable Frame Types 952 * ------------------------------------------ 953 * The Switch Port Acceptable Frame Types register configures the frame 954 * admittance of the port. 955 */ 956 #define MLXSW_REG_SPAFT_ID 0x2010 957 #define MLXSW_REG_SPAFT_LEN 0x08 958 959 MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN); 960 961 /* reg_spaft_local_port 962 * Local port number. 963 * Access: Index 964 * 965 * Note: CPU port is not supported (all tag types are allowed). 966 */ 967 MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8); 968 969 /* reg_spaft_sub_port 970 * Virtual port within the physical port. 971 * Should be set to 0 when virtual ports are not enabled on the port. 972 * Access: RW 973 */ 974 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8); 975 976 /* reg_spaft_allow_untagged 977 * When set, untagged frames on the ingress are allowed (default). 978 * Access: RW 979 */ 980 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1); 981 982 /* reg_spaft_allow_prio_tagged 983 * When set, priority tagged frames on the ingress are allowed (default). 984 * Access: RW 985 */ 986 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1); 987 988 /* reg_spaft_allow_tagged 989 * When set, tagged frames on the ingress are allowed (default). 990 * Access: RW 991 */ 992 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1); 993 994 static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port, 995 bool allow_untagged) 996 { 997 MLXSW_REG_ZERO(spaft, payload); 998 mlxsw_reg_spaft_local_port_set(payload, local_port); 999 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged); 1000 mlxsw_reg_spaft_allow_prio_tagged_set(payload, allow_untagged); 1001 mlxsw_reg_spaft_allow_tagged_set(payload, true); 1002 } 1003 1004 /* SFGC - Switch Flooding Group Configuration 1005 * ------------------------------------------ 1006 * The following register controls the association of flooding tables and MIDs 1007 * to packet types used for flooding. 1008 */ 1009 #define MLXSW_REG_SFGC_ID 0x2011 1010 #define MLXSW_REG_SFGC_LEN 0x10 1011 1012 MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN); 1013 1014 enum mlxsw_reg_sfgc_type { 1015 MLXSW_REG_SFGC_TYPE_BROADCAST, 1016 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST, 1017 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4, 1018 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6, 1019 MLXSW_REG_SFGC_TYPE_RESERVED, 1020 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP, 1021 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL, 1022 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST, 1023 MLXSW_REG_SFGC_TYPE_MAX, 1024 }; 1025 1026 /* reg_sfgc_type 1027 * The traffic type to reach the flooding table. 1028 * Access: Index 1029 */ 1030 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4); 1031 1032 enum mlxsw_reg_sfgc_bridge_type { 1033 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0, 1034 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1, 1035 }; 1036 1037 /* reg_sfgc_bridge_type 1038 * Access: Index 1039 * 1040 * Note: SwitchX-2 only supports 802.1Q mode. 1041 */ 1042 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3); 1043 1044 enum mlxsw_flood_table_type { 1045 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1, 1046 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2, 1047 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0, 1048 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3, 1049 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4, 1050 }; 1051 1052 /* reg_sfgc_table_type 1053 * See mlxsw_flood_table_type 1054 * Access: RW 1055 * 1056 * Note: FID offset and FID types are not supported in SwitchX-2. 1057 */ 1058 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3); 1059 1060 /* reg_sfgc_flood_table 1061 * Flooding table index to associate with the specific type on the specific 1062 * switch partition. 1063 * Access: RW 1064 */ 1065 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6); 1066 1067 /* reg_sfgc_mid 1068 * The multicast ID for the swid. Not supported for Spectrum 1069 * Access: RW 1070 */ 1071 MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16); 1072 1073 /* reg_sfgc_counter_set_type 1074 * Counter Set Type for flow counters. 1075 * Access: RW 1076 */ 1077 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8); 1078 1079 /* reg_sfgc_counter_index 1080 * Counter Index for flow counters. 1081 * Access: RW 1082 */ 1083 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24); 1084 1085 static inline void 1086 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type, 1087 enum mlxsw_reg_sfgc_bridge_type bridge_type, 1088 enum mlxsw_flood_table_type table_type, 1089 unsigned int flood_table) 1090 { 1091 MLXSW_REG_ZERO(sfgc, payload); 1092 mlxsw_reg_sfgc_type_set(payload, type); 1093 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type); 1094 mlxsw_reg_sfgc_table_type_set(payload, table_type); 1095 mlxsw_reg_sfgc_flood_table_set(payload, flood_table); 1096 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID); 1097 } 1098 1099 /* SFTR - Switch Flooding Table Register 1100 * ------------------------------------- 1101 * The switch flooding table is used for flooding packet replication. The table 1102 * defines a bit mask of ports for packet replication. 1103 */ 1104 #define MLXSW_REG_SFTR_ID 0x2012 1105 #define MLXSW_REG_SFTR_LEN 0x420 1106 1107 MLXSW_REG_DEFINE(sftr, MLXSW_REG_SFTR_ID, MLXSW_REG_SFTR_LEN); 1108 1109 /* reg_sftr_swid 1110 * Switch partition ID with which to associate the port. 1111 * Access: Index 1112 */ 1113 MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8); 1114 1115 /* reg_sftr_flood_table 1116 * Flooding table index to associate with the specific type on the specific 1117 * switch partition. 1118 * Access: Index 1119 */ 1120 MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6); 1121 1122 /* reg_sftr_index 1123 * Index. Used as an index into the Flooding Table in case the table is 1124 * configured to use VID / FID or FID Offset. 1125 * Access: Index 1126 */ 1127 MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16); 1128 1129 /* reg_sftr_table_type 1130 * See mlxsw_flood_table_type 1131 * Access: RW 1132 */ 1133 MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3); 1134 1135 /* reg_sftr_range 1136 * Range of entries to update 1137 * Access: Index 1138 */ 1139 MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16); 1140 1141 /* reg_sftr_port 1142 * Local port membership (1 bit per port). 1143 * Access: RW 1144 */ 1145 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1); 1146 1147 /* reg_sftr_cpu_port_mask 1148 * CPU port mask (1 bit per port). 1149 * Access: W 1150 */ 1151 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1); 1152 1153 static inline void mlxsw_reg_sftr_pack(char *payload, 1154 unsigned int flood_table, 1155 unsigned int index, 1156 enum mlxsw_flood_table_type table_type, 1157 unsigned int range, u8 port, bool set) 1158 { 1159 MLXSW_REG_ZERO(sftr, payload); 1160 mlxsw_reg_sftr_swid_set(payload, 0); 1161 mlxsw_reg_sftr_flood_table_set(payload, flood_table); 1162 mlxsw_reg_sftr_index_set(payload, index); 1163 mlxsw_reg_sftr_table_type_set(payload, table_type); 1164 mlxsw_reg_sftr_range_set(payload, range); 1165 mlxsw_reg_sftr_port_set(payload, port, set); 1166 mlxsw_reg_sftr_port_mask_set(payload, port, 1); 1167 } 1168 1169 /* SFDF - Switch Filtering DB Flush 1170 * -------------------------------- 1171 * The switch filtering DB flush register is used to flush the FDB. 1172 * Note that FDB notifications are flushed as well. 1173 */ 1174 #define MLXSW_REG_SFDF_ID 0x2013 1175 #define MLXSW_REG_SFDF_LEN 0x14 1176 1177 MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN); 1178 1179 /* reg_sfdf_swid 1180 * Switch partition ID. 1181 * Access: Index 1182 */ 1183 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8); 1184 1185 enum mlxsw_reg_sfdf_flush_type { 1186 MLXSW_REG_SFDF_FLUSH_PER_SWID, 1187 MLXSW_REG_SFDF_FLUSH_PER_FID, 1188 MLXSW_REG_SFDF_FLUSH_PER_PORT, 1189 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID, 1190 MLXSW_REG_SFDF_FLUSH_PER_LAG, 1191 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID, 1192 MLXSW_REG_SFDF_FLUSH_PER_NVE, 1193 MLXSW_REG_SFDF_FLUSH_PER_NVE_AND_FID, 1194 }; 1195 1196 /* reg_sfdf_flush_type 1197 * Flush type. 1198 * 0 - All SWID dynamic entries are flushed. 1199 * 1 - All FID dynamic entries are flushed. 1200 * 2 - All dynamic entries pointing to port are flushed. 1201 * 3 - All FID dynamic entries pointing to port are flushed. 1202 * 4 - All dynamic entries pointing to LAG are flushed. 1203 * 5 - All FID dynamic entries pointing to LAG are flushed. 1204 * 6 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1205 * flushed. 1206 * 7 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1207 * flushed, per FID. 1208 * Access: RW 1209 */ 1210 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4); 1211 1212 /* reg_sfdf_flush_static 1213 * Static. 1214 * 0 - Flush only dynamic entries. 1215 * 1 - Flush both dynamic and static entries. 1216 * Access: RW 1217 */ 1218 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1); 1219 1220 static inline void mlxsw_reg_sfdf_pack(char *payload, 1221 enum mlxsw_reg_sfdf_flush_type type) 1222 { 1223 MLXSW_REG_ZERO(sfdf, payload); 1224 mlxsw_reg_sfdf_flush_type_set(payload, type); 1225 mlxsw_reg_sfdf_flush_static_set(payload, true); 1226 } 1227 1228 /* reg_sfdf_fid 1229 * FID to flush. 1230 * Access: RW 1231 */ 1232 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16); 1233 1234 /* reg_sfdf_system_port 1235 * Port to flush. 1236 * Access: RW 1237 */ 1238 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16); 1239 1240 /* reg_sfdf_port_fid_system_port 1241 * Port to flush, pointed to by FID. 1242 * Access: RW 1243 */ 1244 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16); 1245 1246 /* reg_sfdf_lag_id 1247 * LAG ID to flush. 1248 * Access: RW 1249 */ 1250 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10); 1251 1252 /* reg_sfdf_lag_fid_lag_id 1253 * LAG ID to flush, pointed to by FID. 1254 * Access: RW 1255 */ 1256 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10); 1257 1258 /* SLDR - Switch LAG Descriptor Register 1259 * ----------------------------------------- 1260 * The switch LAG descriptor register is populated by LAG descriptors. 1261 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to 1262 * max_lag-1. 1263 */ 1264 #define MLXSW_REG_SLDR_ID 0x2014 1265 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */ 1266 1267 MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN); 1268 1269 enum mlxsw_reg_sldr_op { 1270 /* Indicates a creation of a new LAG-ID, lag_id must be valid */ 1271 MLXSW_REG_SLDR_OP_LAG_CREATE, 1272 MLXSW_REG_SLDR_OP_LAG_DESTROY, 1273 /* Ports that appear in the list have the Distributor enabled */ 1274 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST, 1275 /* Removes ports from the disributor list */ 1276 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST, 1277 }; 1278 1279 /* reg_sldr_op 1280 * Operation. 1281 * Access: RW 1282 */ 1283 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3); 1284 1285 /* reg_sldr_lag_id 1286 * LAG identifier. The lag_id is the index into the LAG descriptor table. 1287 * Access: Index 1288 */ 1289 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10); 1290 1291 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id) 1292 { 1293 MLXSW_REG_ZERO(sldr, payload); 1294 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE); 1295 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1296 } 1297 1298 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id) 1299 { 1300 MLXSW_REG_ZERO(sldr, payload); 1301 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY); 1302 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1303 } 1304 1305 /* reg_sldr_num_ports 1306 * The number of member ports of the LAG. 1307 * Reserved for Create / Destroy operations 1308 * For Add / Remove operations - indicates the number of ports in the list. 1309 * Access: RW 1310 */ 1311 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8); 1312 1313 /* reg_sldr_system_port 1314 * System port. 1315 * Access: RW 1316 */ 1317 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false); 1318 1319 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id, 1320 u8 local_port) 1321 { 1322 MLXSW_REG_ZERO(sldr, payload); 1323 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST); 1324 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1325 mlxsw_reg_sldr_num_ports_set(payload, 1); 1326 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1327 } 1328 1329 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id, 1330 u8 local_port) 1331 { 1332 MLXSW_REG_ZERO(sldr, payload); 1333 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST); 1334 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1335 mlxsw_reg_sldr_num_ports_set(payload, 1); 1336 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1337 } 1338 1339 /* SLCR - Switch LAG Configuration 2 Register 1340 * ------------------------------------------- 1341 * The Switch LAG Configuration register is used for configuring the 1342 * LAG properties of the switch. 1343 */ 1344 #define MLXSW_REG_SLCR_ID 0x2015 1345 #define MLXSW_REG_SLCR_LEN 0x10 1346 1347 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN); 1348 1349 enum mlxsw_reg_slcr_pp { 1350 /* Global Configuration (for all ports) */ 1351 MLXSW_REG_SLCR_PP_GLOBAL, 1352 /* Per port configuration, based on local_port field */ 1353 MLXSW_REG_SLCR_PP_PER_PORT, 1354 }; 1355 1356 /* reg_slcr_pp 1357 * Per Port Configuration 1358 * Note: Reading at Global mode results in reading port 1 configuration. 1359 * Access: Index 1360 */ 1361 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1); 1362 1363 /* reg_slcr_local_port 1364 * Local port number 1365 * Supported from CPU port 1366 * Not supported from router port 1367 * Reserved when pp = Global Configuration 1368 * Access: Index 1369 */ 1370 MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8); 1371 1372 enum mlxsw_reg_slcr_type { 1373 MLXSW_REG_SLCR_TYPE_CRC, /* default */ 1374 MLXSW_REG_SLCR_TYPE_XOR, 1375 MLXSW_REG_SLCR_TYPE_RANDOM, 1376 }; 1377 1378 /* reg_slcr_type 1379 * Hash type 1380 * Access: RW 1381 */ 1382 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4); 1383 1384 /* Ingress port */ 1385 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0) 1386 /* SMAC - for IPv4 and IPv6 packets */ 1387 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1) 1388 /* SMAC - for non-IP packets */ 1389 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2) 1390 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \ 1391 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \ 1392 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP) 1393 /* DMAC - for IPv4 and IPv6 packets */ 1394 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3) 1395 /* DMAC - for non-IP packets */ 1396 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4) 1397 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \ 1398 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \ 1399 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP) 1400 /* Ethertype - for IPv4 and IPv6 packets */ 1401 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5) 1402 /* Ethertype - for non-IP packets */ 1403 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6) 1404 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \ 1405 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \ 1406 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP) 1407 /* VLAN ID - for IPv4 and IPv6 packets */ 1408 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7) 1409 /* VLAN ID - for non-IP packets */ 1410 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8) 1411 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \ 1412 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \ 1413 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP) 1414 /* Source IP address (can be IPv4 or IPv6) */ 1415 #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9) 1416 /* Destination IP address (can be IPv4 or IPv6) */ 1417 #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10) 1418 /* TCP/UDP source port */ 1419 #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11) 1420 /* TCP/UDP destination port*/ 1421 #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12) 1422 /* IPv4 Protocol/IPv6 Next Header */ 1423 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13) 1424 /* IPv6 Flow label */ 1425 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14) 1426 /* SID - FCoE source ID */ 1427 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15) 1428 /* DID - FCoE destination ID */ 1429 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16) 1430 /* OXID - FCoE originator exchange ID */ 1431 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17) 1432 /* Destination QP number - for RoCE packets */ 1433 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19) 1434 1435 /* reg_slcr_lag_hash 1436 * LAG hashing configuration. This is a bitmask, in which each set 1437 * bit includes the corresponding item in the LAG hash calculation. 1438 * The default lag_hash contains SMAC, DMAC, VLANID and 1439 * Ethertype (for all packet types). 1440 * Access: RW 1441 */ 1442 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20); 1443 1444 /* reg_slcr_seed 1445 * LAG seed value. The seed is the same for all ports. 1446 * Access: RW 1447 */ 1448 MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32); 1449 1450 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed) 1451 { 1452 MLXSW_REG_ZERO(slcr, payload); 1453 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL); 1454 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC); 1455 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash); 1456 mlxsw_reg_slcr_seed_set(payload, seed); 1457 } 1458 1459 /* SLCOR - Switch LAG Collector Register 1460 * ------------------------------------- 1461 * The Switch LAG Collector register controls the Local Port membership 1462 * in a LAG and enablement of the collector. 1463 */ 1464 #define MLXSW_REG_SLCOR_ID 0x2016 1465 #define MLXSW_REG_SLCOR_LEN 0x10 1466 1467 MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN); 1468 1469 enum mlxsw_reg_slcor_col { 1470 /* Port is added with collector disabled */ 1471 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT, 1472 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED, 1473 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED, 1474 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT, 1475 }; 1476 1477 /* reg_slcor_col 1478 * Collector configuration 1479 * Access: RW 1480 */ 1481 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2); 1482 1483 /* reg_slcor_local_port 1484 * Local port number 1485 * Not supported for CPU port 1486 * Access: Index 1487 */ 1488 MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8); 1489 1490 /* reg_slcor_lag_id 1491 * LAG Identifier. Index into the LAG descriptor table. 1492 * Access: Index 1493 */ 1494 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10); 1495 1496 /* reg_slcor_port_index 1497 * Port index in the LAG list. Only valid on Add Port to LAG col. 1498 * Valid range is from 0 to cap_max_lag_members-1 1499 * Access: RW 1500 */ 1501 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10); 1502 1503 static inline void mlxsw_reg_slcor_pack(char *payload, 1504 u8 local_port, u16 lag_id, 1505 enum mlxsw_reg_slcor_col col) 1506 { 1507 MLXSW_REG_ZERO(slcor, payload); 1508 mlxsw_reg_slcor_col_set(payload, col); 1509 mlxsw_reg_slcor_local_port_set(payload, local_port); 1510 mlxsw_reg_slcor_lag_id_set(payload, lag_id); 1511 } 1512 1513 static inline void mlxsw_reg_slcor_port_add_pack(char *payload, 1514 u8 local_port, u16 lag_id, 1515 u8 port_index) 1516 { 1517 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1518 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT); 1519 mlxsw_reg_slcor_port_index_set(payload, port_index); 1520 } 1521 1522 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload, 1523 u8 local_port, u16 lag_id) 1524 { 1525 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1526 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT); 1527 } 1528 1529 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload, 1530 u8 local_port, u16 lag_id) 1531 { 1532 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1533 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1534 } 1535 1536 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload, 1537 u8 local_port, u16 lag_id) 1538 { 1539 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1540 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1541 } 1542 1543 /* SPMLR - Switch Port MAC Learning Register 1544 * ----------------------------------------- 1545 * Controls the Switch MAC learning policy per port. 1546 */ 1547 #define MLXSW_REG_SPMLR_ID 0x2018 1548 #define MLXSW_REG_SPMLR_LEN 0x8 1549 1550 MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN); 1551 1552 /* reg_spmlr_local_port 1553 * Local port number. 1554 * Access: Index 1555 */ 1556 MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8); 1557 1558 /* reg_spmlr_sub_port 1559 * Virtual port within the physical port. 1560 * Should be set to 0 when virtual ports are not enabled on the port. 1561 * Access: Index 1562 */ 1563 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8); 1564 1565 enum mlxsw_reg_spmlr_learn_mode { 1566 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0, 1567 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2, 1568 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3, 1569 }; 1570 1571 /* reg_spmlr_learn_mode 1572 * Learning mode on the port. 1573 * 0 - Learning disabled. 1574 * 2 - Learning enabled. 1575 * 3 - Security mode. 1576 * 1577 * In security mode the switch does not learn MACs on the port, but uses the 1578 * SMAC to see if it exists on another ingress port. If so, the packet is 1579 * classified as a bad packet and is discarded unless the software registers 1580 * to receive port security error packets usign HPKT. 1581 */ 1582 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2); 1583 1584 static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port, 1585 enum mlxsw_reg_spmlr_learn_mode mode) 1586 { 1587 MLXSW_REG_ZERO(spmlr, payload); 1588 mlxsw_reg_spmlr_local_port_set(payload, local_port); 1589 mlxsw_reg_spmlr_sub_port_set(payload, 0); 1590 mlxsw_reg_spmlr_learn_mode_set(payload, mode); 1591 } 1592 1593 /* SVFA - Switch VID to FID Allocation Register 1594 * -------------------------------------------- 1595 * Controls the VID to FID mapping and {Port, VID} to FID mapping for 1596 * virtualized ports. 1597 */ 1598 #define MLXSW_REG_SVFA_ID 0x201C 1599 #define MLXSW_REG_SVFA_LEN 0x10 1600 1601 MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN); 1602 1603 /* reg_svfa_swid 1604 * Switch partition ID. 1605 * Access: Index 1606 */ 1607 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8); 1608 1609 /* reg_svfa_local_port 1610 * Local port number. 1611 * Access: Index 1612 * 1613 * Note: Reserved for 802.1Q FIDs. 1614 */ 1615 MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8); 1616 1617 enum mlxsw_reg_svfa_mt { 1618 MLXSW_REG_SVFA_MT_VID_TO_FID, 1619 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, 1620 }; 1621 1622 /* reg_svfa_mapping_table 1623 * Mapping table: 1624 * 0 - VID to FID 1625 * 1 - {Port, VID} to FID 1626 * Access: Index 1627 * 1628 * Note: Reserved for SwitchX-2. 1629 */ 1630 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3); 1631 1632 /* reg_svfa_v 1633 * Valid. 1634 * Valid if set. 1635 * Access: RW 1636 * 1637 * Note: Reserved for SwitchX-2. 1638 */ 1639 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1); 1640 1641 /* reg_svfa_fid 1642 * Filtering ID. 1643 * Access: RW 1644 */ 1645 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16); 1646 1647 /* reg_svfa_vid 1648 * VLAN ID. 1649 * Access: Index 1650 */ 1651 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12); 1652 1653 /* reg_svfa_counter_set_type 1654 * Counter set type for flow counters. 1655 * Access: RW 1656 * 1657 * Note: Reserved for SwitchX-2. 1658 */ 1659 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8); 1660 1661 /* reg_svfa_counter_index 1662 * Counter index for flow counters. 1663 * Access: RW 1664 * 1665 * Note: Reserved for SwitchX-2. 1666 */ 1667 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24); 1668 1669 static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port, 1670 enum mlxsw_reg_svfa_mt mt, bool valid, 1671 u16 fid, u16 vid) 1672 { 1673 MLXSW_REG_ZERO(svfa, payload); 1674 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port; 1675 mlxsw_reg_svfa_swid_set(payload, 0); 1676 mlxsw_reg_svfa_local_port_set(payload, local_port); 1677 mlxsw_reg_svfa_mapping_table_set(payload, mt); 1678 mlxsw_reg_svfa_v_set(payload, valid); 1679 mlxsw_reg_svfa_fid_set(payload, fid); 1680 mlxsw_reg_svfa_vid_set(payload, vid); 1681 } 1682 1683 /* SVPE - Switch Virtual-Port Enabling Register 1684 * -------------------------------------------- 1685 * Enables port virtualization. 1686 */ 1687 #define MLXSW_REG_SVPE_ID 0x201E 1688 #define MLXSW_REG_SVPE_LEN 0x4 1689 1690 MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN); 1691 1692 /* reg_svpe_local_port 1693 * Local port number 1694 * Access: Index 1695 * 1696 * Note: CPU port is not supported (uses VLAN mode only). 1697 */ 1698 MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8); 1699 1700 /* reg_svpe_vp_en 1701 * Virtual port enable. 1702 * 0 - Disable, VLAN mode (VID to FID). 1703 * 1 - Enable, Virtual port mode ({Port, VID} to FID). 1704 * Access: RW 1705 */ 1706 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1); 1707 1708 static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port, 1709 bool enable) 1710 { 1711 MLXSW_REG_ZERO(svpe, payload); 1712 mlxsw_reg_svpe_local_port_set(payload, local_port); 1713 mlxsw_reg_svpe_vp_en_set(payload, enable); 1714 } 1715 1716 /* SFMR - Switch FID Management Register 1717 * ------------------------------------- 1718 * Creates and configures FIDs. 1719 */ 1720 #define MLXSW_REG_SFMR_ID 0x201F 1721 #define MLXSW_REG_SFMR_LEN 0x18 1722 1723 MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN); 1724 1725 enum mlxsw_reg_sfmr_op { 1726 MLXSW_REG_SFMR_OP_CREATE_FID, 1727 MLXSW_REG_SFMR_OP_DESTROY_FID, 1728 }; 1729 1730 /* reg_sfmr_op 1731 * Operation. 1732 * 0 - Create or edit FID. 1733 * 1 - Destroy FID. 1734 * Access: WO 1735 */ 1736 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4); 1737 1738 /* reg_sfmr_fid 1739 * Filtering ID. 1740 * Access: Index 1741 */ 1742 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16); 1743 1744 /* reg_sfmr_fid_offset 1745 * FID offset. 1746 * Used to point into the flooding table selected by SFGC register if 1747 * the table is of type FID-Offset. Otherwise, this field is reserved. 1748 * Access: RW 1749 */ 1750 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16); 1751 1752 /* reg_sfmr_vtfp 1753 * Valid Tunnel Flood Pointer. 1754 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL. 1755 * Access: RW 1756 * 1757 * Note: Reserved for 802.1Q FIDs. 1758 */ 1759 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1); 1760 1761 /* reg_sfmr_nve_tunnel_flood_ptr 1762 * Underlay Flooding and BC Pointer. 1763 * Used as a pointer to the first entry of the group based link lists of 1764 * flooding or BC entries (for NVE tunnels). 1765 * Access: RW 1766 */ 1767 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24); 1768 1769 /* reg_sfmr_vv 1770 * VNI Valid. 1771 * If not set, then vni is reserved. 1772 * Access: RW 1773 * 1774 * Note: Reserved for 802.1Q FIDs. 1775 */ 1776 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1); 1777 1778 /* reg_sfmr_vni 1779 * Virtual Network Identifier. 1780 * Access: RW 1781 * 1782 * Note: A given VNI can only be assigned to one FID. 1783 */ 1784 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24); 1785 1786 static inline void mlxsw_reg_sfmr_pack(char *payload, 1787 enum mlxsw_reg_sfmr_op op, u16 fid, 1788 u16 fid_offset) 1789 { 1790 MLXSW_REG_ZERO(sfmr, payload); 1791 mlxsw_reg_sfmr_op_set(payload, op); 1792 mlxsw_reg_sfmr_fid_set(payload, fid); 1793 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset); 1794 mlxsw_reg_sfmr_vtfp_set(payload, false); 1795 mlxsw_reg_sfmr_vv_set(payload, false); 1796 } 1797 1798 /* SPVMLR - Switch Port VLAN MAC Learning Register 1799 * ----------------------------------------------- 1800 * Controls the switch MAC learning policy per {Port, VID}. 1801 */ 1802 #define MLXSW_REG_SPVMLR_ID 0x2020 1803 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */ 1804 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */ 1805 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255 1806 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \ 1807 MLXSW_REG_SPVMLR_REC_LEN * \ 1808 MLXSW_REG_SPVMLR_REC_MAX_COUNT) 1809 1810 MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN); 1811 1812 /* reg_spvmlr_local_port 1813 * Local ingress port. 1814 * Access: Index 1815 * 1816 * Note: CPU port is not supported. 1817 */ 1818 MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8); 1819 1820 /* reg_spvmlr_num_rec 1821 * Number of records to update. 1822 * Access: OP 1823 */ 1824 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8); 1825 1826 /* reg_spvmlr_rec_learn_enable 1827 * 0 - Disable learning for {Port, VID}. 1828 * 1 - Enable learning for {Port, VID}. 1829 * Access: RW 1830 */ 1831 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN, 1832 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1833 1834 /* reg_spvmlr_rec_vid 1835 * VLAN ID to be added/removed from port or for querying. 1836 * Access: Index 1837 */ 1838 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12, 1839 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1840 1841 static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port, 1842 u16 vid_begin, u16 vid_end, 1843 bool learn_enable) 1844 { 1845 int num_rec = vid_end - vid_begin + 1; 1846 int i; 1847 1848 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT); 1849 1850 MLXSW_REG_ZERO(spvmlr, payload); 1851 mlxsw_reg_spvmlr_local_port_set(payload, local_port); 1852 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec); 1853 1854 for (i = 0; i < num_rec; i++) { 1855 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable); 1856 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i); 1857 } 1858 } 1859 1860 /* CWTP - Congetion WRED ECN TClass Profile 1861 * ---------------------------------------- 1862 * Configures the profiles for queues of egress port and traffic class 1863 */ 1864 #define MLXSW_REG_CWTP_ID 0x2802 1865 #define MLXSW_REG_CWTP_BASE_LEN 0x28 1866 #define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08 1867 #define MLXSW_REG_CWTP_LEN 0x40 1868 1869 MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN); 1870 1871 /* reg_cwtp_local_port 1872 * Local port number 1873 * Not supported for CPU port 1874 * Access: Index 1875 */ 1876 MLXSW_ITEM32(reg, cwtp, local_port, 0, 16, 8); 1877 1878 /* reg_cwtp_traffic_class 1879 * Traffic Class to configure 1880 * Access: Index 1881 */ 1882 MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8); 1883 1884 /* reg_cwtp_profile_min 1885 * Minimum Average Queue Size of the profile in cells. 1886 * Access: RW 1887 */ 1888 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN, 1889 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false); 1890 1891 /* reg_cwtp_profile_percent 1892 * Percentage of WRED and ECN marking for maximum Average Queue size 1893 * Range is 0 to 100, units of integer percentage 1894 * Access: RW 1895 */ 1896 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN, 1897 24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 1898 1899 /* reg_cwtp_profile_max 1900 * Maximum Average Queue size of the profile in cells 1901 * Access: RW 1902 */ 1903 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN, 1904 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 1905 1906 #define MLXSW_REG_CWTP_MIN_VALUE 64 1907 #define MLXSW_REG_CWTP_MAX_PROFILE 2 1908 #define MLXSW_REG_CWTP_DEFAULT_PROFILE 1 1909 1910 static inline void mlxsw_reg_cwtp_pack(char *payload, u8 local_port, 1911 u8 traffic_class) 1912 { 1913 int i; 1914 1915 MLXSW_REG_ZERO(cwtp, payload); 1916 mlxsw_reg_cwtp_local_port_set(payload, local_port); 1917 mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class); 1918 1919 for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) { 1920 mlxsw_reg_cwtp_profile_min_set(payload, i, 1921 MLXSW_REG_CWTP_MIN_VALUE); 1922 mlxsw_reg_cwtp_profile_max_set(payload, i, 1923 MLXSW_REG_CWTP_MIN_VALUE); 1924 } 1925 } 1926 1927 #define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1) 1928 1929 static inline void 1930 mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max, 1931 u32 probability) 1932 { 1933 u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile); 1934 1935 mlxsw_reg_cwtp_profile_min_set(payload, index, min); 1936 mlxsw_reg_cwtp_profile_max_set(payload, index, max); 1937 mlxsw_reg_cwtp_profile_percent_set(payload, index, probability); 1938 } 1939 1940 /* CWTPM - Congestion WRED ECN TClass and Pool Mapping 1941 * --------------------------------------------------- 1942 * The CWTPM register maps each egress port and traffic class to profile num. 1943 */ 1944 #define MLXSW_REG_CWTPM_ID 0x2803 1945 #define MLXSW_REG_CWTPM_LEN 0x44 1946 1947 MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN); 1948 1949 /* reg_cwtpm_local_port 1950 * Local port number 1951 * Not supported for CPU port 1952 * Access: Index 1953 */ 1954 MLXSW_ITEM32(reg, cwtpm, local_port, 0, 16, 8); 1955 1956 /* reg_cwtpm_traffic_class 1957 * Traffic Class to configure 1958 * Access: Index 1959 */ 1960 MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8); 1961 1962 /* reg_cwtpm_ew 1963 * Control enablement of WRED for traffic class: 1964 * 0 - Disable 1965 * 1 - Enable 1966 * Access: RW 1967 */ 1968 MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1); 1969 1970 /* reg_cwtpm_ee 1971 * Control enablement of ECN for traffic class: 1972 * 0 - Disable 1973 * 1 - Enable 1974 * Access: RW 1975 */ 1976 MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1); 1977 1978 /* reg_cwtpm_tcp_g 1979 * TCP Green Profile. 1980 * Index of the profile within {port, traffic class} to use. 1981 * 0 for disabling both WRED and ECN for this type of traffic. 1982 * Access: RW 1983 */ 1984 MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2); 1985 1986 /* reg_cwtpm_tcp_y 1987 * TCP Yellow Profile. 1988 * Index of the profile within {port, traffic class} to use. 1989 * 0 for disabling both WRED and ECN for this type of traffic. 1990 * Access: RW 1991 */ 1992 MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2); 1993 1994 /* reg_cwtpm_tcp_r 1995 * TCP Red Profile. 1996 * Index of the profile within {port, traffic class} to use. 1997 * 0 for disabling both WRED and ECN for this type of traffic. 1998 * Access: RW 1999 */ 2000 MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2); 2001 2002 /* reg_cwtpm_ntcp_g 2003 * Non-TCP Green Profile. 2004 * Index of the profile within {port, traffic class} to use. 2005 * 0 for disabling both WRED and ECN for this type of traffic. 2006 * Access: RW 2007 */ 2008 MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2); 2009 2010 /* reg_cwtpm_ntcp_y 2011 * Non-TCP Yellow Profile. 2012 * Index of the profile within {port, traffic class} to use. 2013 * 0 for disabling both WRED and ECN for this type of traffic. 2014 * Access: RW 2015 */ 2016 MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2); 2017 2018 /* reg_cwtpm_ntcp_r 2019 * Non-TCP Red Profile. 2020 * Index of the profile within {port, traffic class} to use. 2021 * 0 for disabling both WRED and ECN for this type of traffic. 2022 * Access: RW 2023 */ 2024 MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2); 2025 2026 #define MLXSW_REG_CWTPM_RESET_PROFILE 0 2027 2028 static inline void mlxsw_reg_cwtpm_pack(char *payload, u8 local_port, 2029 u8 traffic_class, u8 profile, 2030 bool wred, bool ecn) 2031 { 2032 MLXSW_REG_ZERO(cwtpm, payload); 2033 mlxsw_reg_cwtpm_local_port_set(payload, local_port); 2034 mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class); 2035 mlxsw_reg_cwtpm_ew_set(payload, wred); 2036 mlxsw_reg_cwtpm_ee_set(payload, ecn); 2037 mlxsw_reg_cwtpm_tcp_g_set(payload, profile); 2038 mlxsw_reg_cwtpm_tcp_y_set(payload, profile); 2039 mlxsw_reg_cwtpm_tcp_r_set(payload, profile); 2040 mlxsw_reg_cwtpm_ntcp_g_set(payload, profile); 2041 mlxsw_reg_cwtpm_ntcp_y_set(payload, profile); 2042 mlxsw_reg_cwtpm_ntcp_r_set(payload, profile); 2043 } 2044 2045 /* PGCR - Policy-Engine General Configuration Register 2046 * --------------------------------------------------- 2047 * This register configures general Policy-Engine settings. 2048 */ 2049 #define MLXSW_REG_PGCR_ID 0x3001 2050 #define MLXSW_REG_PGCR_LEN 0x20 2051 2052 MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN); 2053 2054 /* reg_pgcr_default_action_pointer_base 2055 * Default action pointer base. Each region has a default action pointer 2056 * which is equal to default_action_pointer_base + region_id. 2057 * Access: RW 2058 */ 2059 MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24); 2060 2061 static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base) 2062 { 2063 MLXSW_REG_ZERO(pgcr, payload); 2064 mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base); 2065 } 2066 2067 /* PPBT - Policy-Engine Port Binding Table 2068 * --------------------------------------- 2069 * This register is used for configuration of the Port Binding Table. 2070 */ 2071 #define MLXSW_REG_PPBT_ID 0x3002 2072 #define MLXSW_REG_PPBT_LEN 0x14 2073 2074 MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN); 2075 2076 enum mlxsw_reg_pxbt_e { 2077 MLXSW_REG_PXBT_E_IACL, 2078 MLXSW_REG_PXBT_E_EACL, 2079 }; 2080 2081 /* reg_ppbt_e 2082 * Access: Index 2083 */ 2084 MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1); 2085 2086 enum mlxsw_reg_pxbt_op { 2087 MLXSW_REG_PXBT_OP_BIND, 2088 MLXSW_REG_PXBT_OP_UNBIND, 2089 }; 2090 2091 /* reg_ppbt_op 2092 * Access: RW 2093 */ 2094 MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3); 2095 2096 /* reg_ppbt_local_port 2097 * Local port. Not including CPU port. 2098 * Access: Index 2099 */ 2100 MLXSW_ITEM32(reg, ppbt, local_port, 0x00, 16, 8); 2101 2102 /* reg_ppbt_g 2103 * group - When set, the binding is of an ACL group. When cleared, 2104 * the binding is of an ACL. 2105 * Must be set to 1 for Spectrum. 2106 * Access: RW 2107 */ 2108 MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1); 2109 2110 /* reg_ppbt_acl_info 2111 * ACL/ACL group identifier. If the g bit is set, this field should hold 2112 * the acl_group_id, else it should hold the acl_id. 2113 * Access: RW 2114 */ 2115 MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16); 2116 2117 static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e, 2118 enum mlxsw_reg_pxbt_op op, 2119 u8 local_port, u16 acl_info) 2120 { 2121 MLXSW_REG_ZERO(ppbt, payload); 2122 mlxsw_reg_ppbt_e_set(payload, e); 2123 mlxsw_reg_ppbt_op_set(payload, op); 2124 mlxsw_reg_ppbt_local_port_set(payload, local_port); 2125 mlxsw_reg_ppbt_g_set(payload, true); 2126 mlxsw_reg_ppbt_acl_info_set(payload, acl_info); 2127 } 2128 2129 /* PACL - Policy-Engine ACL Register 2130 * --------------------------------- 2131 * This register is used for configuration of the ACL. 2132 */ 2133 #define MLXSW_REG_PACL_ID 0x3004 2134 #define MLXSW_REG_PACL_LEN 0x70 2135 2136 MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN); 2137 2138 /* reg_pacl_v 2139 * Valid. Setting the v bit makes the ACL valid. It should not be cleared 2140 * while the ACL is bounded to either a port, VLAN or ACL rule. 2141 * Access: RW 2142 */ 2143 MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1); 2144 2145 /* reg_pacl_acl_id 2146 * An identifier representing the ACL (managed by software) 2147 * Range 0 .. cap_max_acl_regions - 1 2148 * Access: Index 2149 */ 2150 MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16); 2151 2152 #define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16 2153 2154 /* reg_pacl_tcam_region_info 2155 * Opaque object that represents a TCAM region. 2156 * Obtained through PTAR register. 2157 * Access: RW 2158 */ 2159 MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30, 2160 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2161 2162 static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id, 2163 bool valid, const char *tcam_region_info) 2164 { 2165 MLXSW_REG_ZERO(pacl, payload); 2166 mlxsw_reg_pacl_acl_id_set(payload, acl_id); 2167 mlxsw_reg_pacl_v_set(payload, valid); 2168 mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info); 2169 } 2170 2171 /* PAGT - Policy-Engine ACL Group Table 2172 * ------------------------------------ 2173 * This register is used for configuration of the ACL Group Table. 2174 */ 2175 #define MLXSW_REG_PAGT_ID 0x3005 2176 #define MLXSW_REG_PAGT_BASE_LEN 0x30 2177 #define MLXSW_REG_PAGT_ACL_LEN 4 2178 #define MLXSW_REG_PAGT_ACL_MAX_NUM 16 2179 #define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \ 2180 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN) 2181 2182 MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN); 2183 2184 /* reg_pagt_size 2185 * Number of ACLs in the group. 2186 * Size 0 invalidates a group. 2187 * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now) 2188 * Total number of ACLs in all groups must be lower or equal 2189 * to cap_max_acl_tot_groups 2190 * Note: a group which is binded must not be invalidated 2191 * Access: Index 2192 */ 2193 MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8); 2194 2195 /* reg_pagt_acl_group_id 2196 * An identifier (numbered from 0..cap_max_acl_groups-1) representing 2197 * the ACL Group identifier (managed by software). 2198 * Access: Index 2199 */ 2200 MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16); 2201 2202 /* reg_pagt_multi 2203 * Multi-ACL 2204 * 0 - This ACL is the last ACL in the multi-ACL 2205 * 1 - This ACL is part of a multi-ACL 2206 * Access: RW 2207 */ 2208 MLXSW_ITEM32_INDEXED(reg, pagt, multi, 0x30, 31, 1, 0x04, 0x00, false); 2209 2210 /* reg_pagt_acl_id 2211 * ACL identifier 2212 * Access: RW 2213 */ 2214 MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false); 2215 2216 static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id) 2217 { 2218 MLXSW_REG_ZERO(pagt, payload); 2219 mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id); 2220 } 2221 2222 static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index, 2223 u16 acl_id, bool multi) 2224 { 2225 u8 size = mlxsw_reg_pagt_size_get(payload); 2226 2227 if (index >= size) 2228 mlxsw_reg_pagt_size_set(payload, index + 1); 2229 mlxsw_reg_pagt_multi_set(payload, index, multi); 2230 mlxsw_reg_pagt_acl_id_set(payload, index, acl_id); 2231 } 2232 2233 /* PTAR - Policy-Engine TCAM Allocation Register 2234 * --------------------------------------------- 2235 * This register is used for allocation of regions in the TCAM. 2236 * Note: Query method is not supported on this register. 2237 */ 2238 #define MLXSW_REG_PTAR_ID 0x3006 2239 #define MLXSW_REG_PTAR_BASE_LEN 0x20 2240 #define MLXSW_REG_PTAR_KEY_ID_LEN 1 2241 #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16 2242 #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \ 2243 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN) 2244 2245 MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN); 2246 2247 enum mlxsw_reg_ptar_op { 2248 /* allocate a TCAM region */ 2249 MLXSW_REG_PTAR_OP_ALLOC, 2250 /* resize a TCAM region */ 2251 MLXSW_REG_PTAR_OP_RESIZE, 2252 /* deallocate TCAM region */ 2253 MLXSW_REG_PTAR_OP_FREE, 2254 /* test allocation */ 2255 MLXSW_REG_PTAR_OP_TEST, 2256 }; 2257 2258 /* reg_ptar_op 2259 * Access: OP 2260 */ 2261 MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4); 2262 2263 /* reg_ptar_action_set_type 2264 * Type of action set to be used on this region. 2265 * For Spectrum and Spectrum-2, this is always type 2 - "flexible" 2266 * Access: WO 2267 */ 2268 MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8); 2269 2270 enum mlxsw_reg_ptar_key_type { 2271 MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50, /* Spetrum */ 2272 MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51, /* Spectrum-2 */ 2273 }; 2274 2275 /* reg_ptar_key_type 2276 * TCAM key type for the region. 2277 * Access: WO 2278 */ 2279 MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8); 2280 2281 /* reg_ptar_region_size 2282 * TCAM region size. When allocating/resizing this is the requested size, 2283 * the response is the actual size. Note that actual size may be 2284 * larger than requested. 2285 * Allowed range 1 .. cap_max_rules-1 2286 * Reserved during op deallocate. 2287 * Access: WO 2288 */ 2289 MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16); 2290 2291 /* reg_ptar_region_id 2292 * Region identifier 2293 * Range 0 .. cap_max_regions-1 2294 * Access: Index 2295 */ 2296 MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16); 2297 2298 /* reg_ptar_tcam_region_info 2299 * Opaque object that represents the TCAM region. 2300 * Returned when allocating a region. 2301 * Provided by software for ACL generation and region deallocation and resize. 2302 * Access: RW 2303 */ 2304 MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10, 2305 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2306 2307 /* reg_ptar_flexible_key_id 2308 * Identifier of the Flexible Key. 2309 * Only valid if key_type == "FLEX_KEY" 2310 * The key size will be rounded up to one of the following values: 2311 * 9B, 18B, 36B, 54B. 2312 * This field is reserved for in resize operation. 2313 * Access: WO 2314 */ 2315 MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8, 2316 MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false); 2317 2318 static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op, 2319 enum mlxsw_reg_ptar_key_type key_type, 2320 u16 region_size, u16 region_id, 2321 const char *tcam_region_info) 2322 { 2323 MLXSW_REG_ZERO(ptar, payload); 2324 mlxsw_reg_ptar_op_set(payload, op); 2325 mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */ 2326 mlxsw_reg_ptar_key_type_set(payload, key_type); 2327 mlxsw_reg_ptar_region_size_set(payload, region_size); 2328 mlxsw_reg_ptar_region_id_set(payload, region_id); 2329 mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info); 2330 } 2331 2332 static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index, 2333 u16 key_id) 2334 { 2335 mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id); 2336 } 2337 2338 static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info) 2339 { 2340 mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info); 2341 } 2342 2343 /* PPBS - Policy-Engine Policy Based Switching Register 2344 * ---------------------------------------------------- 2345 * This register retrieves and sets Policy Based Switching Table entries. 2346 */ 2347 #define MLXSW_REG_PPBS_ID 0x300C 2348 #define MLXSW_REG_PPBS_LEN 0x14 2349 2350 MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN); 2351 2352 /* reg_ppbs_pbs_ptr 2353 * Index into the PBS table. 2354 * For Spectrum, the index points to the KVD Linear. 2355 * Access: Index 2356 */ 2357 MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24); 2358 2359 /* reg_ppbs_system_port 2360 * Unique port identifier for the final destination of the packet. 2361 * Access: RW 2362 */ 2363 MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16); 2364 2365 static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr, 2366 u16 system_port) 2367 { 2368 MLXSW_REG_ZERO(ppbs, payload); 2369 mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr); 2370 mlxsw_reg_ppbs_system_port_set(payload, system_port); 2371 } 2372 2373 /* PRCR - Policy-Engine Rules Copy Register 2374 * ---------------------------------------- 2375 * This register is used for accessing rules within a TCAM region. 2376 */ 2377 #define MLXSW_REG_PRCR_ID 0x300D 2378 #define MLXSW_REG_PRCR_LEN 0x40 2379 2380 MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN); 2381 2382 enum mlxsw_reg_prcr_op { 2383 /* Move rules. Moves the rules from "tcam_region_info" starting 2384 * at offset "offset" to "dest_tcam_region_info" 2385 * at offset "dest_offset." 2386 */ 2387 MLXSW_REG_PRCR_OP_MOVE, 2388 /* Copy rules. Copies the rules from "tcam_region_info" starting 2389 * at offset "offset" to "dest_tcam_region_info" 2390 * at offset "dest_offset." 2391 */ 2392 MLXSW_REG_PRCR_OP_COPY, 2393 }; 2394 2395 /* reg_prcr_op 2396 * Access: OP 2397 */ 2398 MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4); 2399 2400 /* reg_prcr_offset 2401 * Offset within the source region to copy/move from. 2402 * Access: Index 2403 */ 2404 MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16); 2405 2406 /* reg_prcr_size 2407 * The number of rules to copy/move. 2408 * Access: WO 2409 */ 2410 MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16); 2411 2412 /* reg_prcr_tcam_region_info 2413 * Opaque object that represents the source TCAM region. 2414 * Access: Index 2415 */ 2416 MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10, 2417 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2418 2419 /* reg_prcr_dest_offset 2420 * Offset within the source region to copy/move to. 2421 * Access: Index 2422 */ 2423 MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16); 2424 2425 /* reg_prcr_dest_tcam_region_info 2426 * Opaque object that represents the destination TCAM region. 2427 * Access: Index 2428 */ 2429 MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30, 2430 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2431 2432 static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op, 2433 const char *src_tcam_region_info, 2434 u16 src_offset, 2435 const char *dest_tcam_region_info, 2436 u16 dest_offset, u16 size) 2437 { 2438 MLXSW_REG_ZERO(prcr, payload); 2439 mlxsw_reg_prcr_op_set(payload, op); 2440 mlxsw_reg_prcr_offset_set(payload, src_offset); 2441 mlxsw_reg_prcr_size_set(payload, size); 2442 mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload, 2443 src_tcam_region_info); 2444 mlxsw_reg_prcr_dest_offset_set(payload, dest_offset); 2445 mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload, 2446 dest_tcam_region_info); 2447 } 2448 2449 /* PEFA - Policy-Engine Extended Flexible Action Register 2450 * ------------------------------------------------------ 2451 * This register is used for accessing an extended flexible action entry 2452 * in the central KVD Linear Database. 2453 */ 2454 #define MLXSW_REG_PEFA_ID 0x300F 2455 #define MLXSW_REG_PEFA_LEN 0xB0 2456 2457 MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN); 2458 2459 /* reg_pefa_index 2460 * Index in the KVD Linear Centralized Database. 2461 * Access: Index 2462 */ 2463 MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24); 2464 2465 /* reg_pefa_a 2466 * Index in the KVD Linear Centralized Database. 2467 * Activity 2468 * For a new entry: set if ca=0, clear if ca=1 2469 * Set if a packet lookup has hit on the specific entry 2470 * Access: RO 2471 */ 2472 MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1); 2473 2474 /* reg_pefa_ca 2475 * Clear activity 2476 * When write: activity is according to this field 2477 * When read: after reading the activity is cleared according to ca 2478 * Access: OP 2479 */ 2480 MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1); 2481 2482 #define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8 2483 2484 /* reg_pefa_flex_action_set 2485 * Action-set to perform when rule is matched. 2486 * Must be zero padded if action set is shorter. 2487 * Access: RW 2488 */ 2489 MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN); 2490 2491 static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca, 2492 const char *flex_action_set) 2493 { 2494 MLXSW_REG_ZERO(pefa, payload); 2495 mlxsw_reg_pefa_index_set(payload, index); 2496 mlxsw_reg_pefa_ca_set(payload, ca); 2497 if (flex_action_set) 2498 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload, 2499 flex_action_set); 2500 } 2501 2502 static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a) 2503 { 2504 *p_a = mlxsw_reg_pefa_a_get(payload); 2505 } 2506 2507 /* PEMRBT - Policy-Engine Multicast Router Binding Table Register 2508 * -------------------------------------------------------------- 2509 * This register is used for binding Multicast router to an ACL group 2510 * that serves the MC router. 2511 * This register is not supported by SwitchX/-2 and Spectrum. 2512 */ 2513 #define MLXSW_REG_PEMRBT_ID 0x3014 2514 #define MLXSW_REG_PEMRBT_LEN 0x14 2515 2516 MLXSW_REG_DEFINE(pemrbt, MLXSW_REG_PEMRBT_ID, MLXSW_REG_PEMRBT_LEN); 2517 2518 enum mlxsw_reg_pemrbt_protocol { 2519 MLXSW_REG_PEMRBT_PROTO_IPV4, 2520 MLXSW_REG_PEMRBT_PROTO_IPV6, 2521 }; 2522 2523 /* reg_pemrbt_protocol 2524 * Access: Index 2525 */ 2526 MLXSW_ITEM32(reg, pemrbt, protocol, 0x00, 0, 1); 2527 2528 /* reg_pemrbt_group_id 2529 * ACL group identifier. 2530 * Range 0..cap_max_acl_groups-1 2531 * Access: RW 2532 */ 2533 MLXSW_ITEM32(reg, pemrbt, group_id, 0x10, 0, 16); 2534 2535 static inline void 2536 mlxsw_reg_pemrbt_pack(char *payload, enum mlxsw_reg_pemrbt_protocol protocol, 2537 u16 group_id) 2538 { 2539 MLXSW_REG_ZERO(pemrbt, payload); 2540 mlxsw_reg_pemrbt_protocol_set(payload, protocol); 2541 mlxsw_reg_pemrbt_group_id_set(payload, group_id); 2542 } 2543 2544 /* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2 2545 * ----------------------------------------------------- 2546 * This register is used for accessing rules within a TCAM region. 2547 * It is a new version of PTCE in order to support wider key, 2548 * mask and action within a TCAM region. This register is not supported 2549 * by SwitchX and SwitchX-2. 2550 */ 2551 #define MLXSW_REG_PTCE2_ID 0x3017 2552 #define MLXSW_REG_PTCE2_LEN 0x1D8 2553 2554 MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN); 2555 2556 /* reg_ptce2_v 2557 * Valid. 2558 * Access: RW 2559 */ 2560 MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1); 2561 2562 /* reg_ptce2_a 2563 * Activity. Set if a packet lookup has hit on the specific entry. 2564 * To clear the "a" bit, use "clear activity" op or "clear on read" op. 2565 * Access: RO 2566 */ 2567 MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1); 2568 2569 enum mlxsw_reg_ptce2_op { 2570 /* Read operation. */ 2571 MLXSW_REG_PTCE2_OP_QUERY_READ = 0, 2572 /* clear on read operation. Used to read entry 2573 * and clear Activity bit. 2574 */ 2575 MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1, 2576 /* Write operation. Used to write a new entry to the table. 2577 * All R/W fields are relevant for new entry. Activity bit is set 2578 * for new entries - Note write with v = 0 will delete the entry. 2579 */ 2580 MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0, 2581 /* Update action. Only action set will be updated. */ 2582 MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1, 2583 /* Clear activity. A bit is cleared for the entry. */ 2584 MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2, 2585 }; 2586 2587 /* reg_ptce2_op 2588 * Access: OP 2589 */ 2590 MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3); 2591 2592 /* reg_ptce2_offset 2593 * Access: Index 2594 */ 2595 MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16); 2596 2597 /* reg_ptce2_priority 2598 * Priority of the rule, higher values win. The range is 1..cap_kvd_size-1. 2599 * Note: priority does not have to be unique per rule. 2600 * Within a region, higher priority should have lower offset (no limitation 2601 * between regions in a multi-region). 2602 * Access: RW 2603 */ 2604 MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24); 2605 2606 /* reg_ptce2_tcam_region_info 2607 * Opaque object that represents the TCAM region. 2608 * Access: Index 2609 */ 2610 MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10, 2611 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2612 2613 #define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 96 2614 2615 /* reg_ptce2_flex_key_blocks 2616 * ACL Key. 2617 * Access: RW 2618 */ 2619 MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20, 2620 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2621 2622 /* reg_ptce2_mask 2623 * mask- in the same size as key. A bit that is set directs the TCAM 2624 * to compare the corresponding bit in key. A bit that is clear directs 2625 * the TCAM to ignore the corresponding bit in key. 2626 * Access: RW 2627 */ 2628 MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80, 2629 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2630 2631 /* reg_ptce2_flex_action_set 2632 * ACL action set. 2633 * Access: RW 2634 */ 2635 MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0, 2636 MLXSW_REG_FLEX_ACTION_SET_LEN); 2637 2638 static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid, 2639 enum mlxsw_reg_ptce2_op op, 2640 const char *tcam_region_info, 2641 u16 offset, u32 priority) 2642 { 2643 MLXSW_REG_ZERO(ptce2, payload); 2644 mlxsw_reg_ptce2_v_set(payload, valid); 2645 mlxsw_reg_ptce2_op_set(payload, op); 2646 mlxsw_reg_ptce2_offset_set(payload, offset); 2647 mlxsw_reg_ptce2_priority_set(payload, priority); 2648 mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info); 2649 } 2650 2651 /* PERPT - Policy-Engine ERP Table Register 2652 * ---------------------------------------- 2653 * This register adds and removes eRPs from the eRP table. 2654 */ 2655 #define MLXSW_REG_PERPT_ID 0x3021 2656 #define MLXSW_REG_PERPT_LEN 0x80 2657 2658 MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN); 2659 2660 /* reg_perpt_erpt_bank 2661 * eRP table bank. 2662 * Range 0 .. cap_max_erp_table_banks - 1 2663 * Access: Index 2664 */ 2665 MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4); 2666 2667 /* reg_perpt_erpt_index 2668 * Index to eRP table within the eRP bank. 2669 * Range is 0 .. cap_max_erp_table_bank_size - 1 2670 * Access: Index 2671 */ 2672 MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8); 2673 2674 enum mlxsw_reg_perpt_key_size { 2675 MLXSW_REG_PERPT_KEY_SIZE_2KB, 2676 MLXSW_REG_PERPT_KEY_SIZE_4KB, 2677 MLXSW_REG_PERPT_KEY_SIZE_8KB, 2678 MLXSW_REG_PERPT_KEY_SIZE_12KB, 2679 }; 2680 2681 /* reg_perpt_key_size 2682 * Access: OP 2683 */ 2684 MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4); 2685 2686 /* reg_perpt_bf_bypass 2687 * 0 - The eRP is used only if bloom filter state is set for the given 2688 * rule. 2689 * 1 - The eRP is used regardless of bloom filter state. 2690 * The bypass is an OR condition of region_id or eRP. See PERCR.bf_bypass 2691 * Access: RW 2692 */ 2693 MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1); 2694 2695 /* reg_perpt_erp_id 2696 * eRP ID for use by the rules. 2697 * Access: RW 2698 */ 2699 MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4); 2700 2701 /* reg_perpt_erpt_base_bank 2702 * Base eRP table bank, points to head of erp_vector 2703 * Range is 0 .. cap_max_erp_table_banks - 1 2704 * Access: OP 2705 */ 2706 MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4); 2707 2708 /* reg_perpt_erpt_base_index 2709 * Base index to eRP table within the eRP bank 2710 * Range is 0 .. cap_max_erp_table_bank_size - 1 2711 * Access: OP 2712 */ 2713 MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8); 2714 2715 /* reg_perpt_erp_index_in_vector 2716 * eRP index in the vector. 2717 * Access: OP 2718 */ 2719 MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4); 2720 2721 /* reg_perpt_erp_vector 2722 * eRP vector. 2723 * Access: OP 2724 */ 2725 MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1); 2726 2727 /* reg_perpt_mask 2728 * Mask 2729 * 0 - A-TCAM will ignore the bit in key 2730 * 1 - A-TCAM will compare the bit in key 2731 * Access: RW 2732 */ 2733 MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2734 2735 static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload, 2736 unsigned long *erp_vector, 2737 unsigned long size) 2738 { 2739 unsigned long bit; 2740 2741 for_each_set_bit(bit, erp_vector, size) 2742 mlxsw_reg_perpt_erp_vector_set(payload, bit, true); 2743 } 2744 2745 static inline void 2746 mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index, 2747 enum mlxsw_reg_perpt_key_size key_size, u8 erp_id, 2748 u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index, 2749 char *mask) 2750 { 2751 MLXSW_REG_ZERO(perpt, payload); 2752 mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank); 2753 mlxsw_reg_perpt_erpt_index_set(payload, erpt_index); 2754 mlxsw_reg_perpt_key_size_set(payload, key_size); 2755 mlxsw_reg_perpt_bf_bypass_set(payload, false); 2756 mlxsw_reg_perpt_erp_id_set(payload, erp_id); 2757 mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank); 2758 mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index); 2759 mlxsw_reg_perpt_erp_index_in_vector_set(payload, erp_index); 2760 mlxsw_reg_perpt_mask_memcpy_to(payload, mask); 2761 } 2762 2763 /* PERAR - Policy-Engine Region Association Register 2764 * ------------------------------------------------- 2765 * This register associates a hw region for region_id's. Changing on the fly 2766 * is supported by the device. 2767 */ 2768 #define MLXSW_REG_PERAR_ID 0x3026 2769 #define MLXSW_REG_PERAR_LEN 0x08 2770 2771 MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN); 2772 2773 /* reg_perar_region_id 2774 * Region identifier 2775 * Range 0 .. cap_max_regions-1 2776 * Access: Index 2777 */ 2778 MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16); 2779 2780 static inline unsigned int 2781 mlxsw_reg_perar_hw_regions_needed(unsigned int block_num) 2782 { 2783 return DIV_ROUND_UP(block_num, 4); 2784 } 2785 2786 /* reg_perar_hw_region 2787 * HW Region 2788 * Range 0 .. cap_max_regions-1 2789 * Default: hw_region = region_id 2790 * For a 8 key block region, 2 consecutive regions are used 2791 * For a 12 key block region, 3 consecutive regions are used 2792 * Access: RW 2793 */ 2794 MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16); 2795 2796 static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id, 2797 u16 hw_region) 2798 { 2799 MLXSW_REG_ZERO(perar, payload); 2800 mlxsw_reg_perar_region_id_set(payload, region_id); 2801 mlxsw_reg_perar_hw_region_set(payload, hw_region); 2802 } 2803 2804 /* PTCE-V3 - Policy-Engine TCAM Entry Register Version 3 2805 * ----------------------------------------------------- 2806 * This register is a new version of PTCE-V2 in order to support the 2807 * A-TCAM. This register is not supported by SwitchX/-2 and Spectrum. 2808 */ 2809 #define MLXSW_REG_PTCE3_ID 0x3027 2810 #define MLXSW_REG_PTCE3_LEN 0xF0 2811 2812 MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN); 2813 2814 /* reg_ptce3_v 2815 * Valid. 2816 * Access: RW 2817 */ 2818 MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1); 2819 2820 enum mlxsw_reg_ptce3_op { 2821 /* Write operation. Used to write a new entry to the table. 2822 * All R/W fields are relevant for new entry. Activity bit is set 2823 * for new entries. Write with v = 0 will delete the entry. Must 2824 * not be used if an entry exists. 2825 */ 2826 MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0, 2827 /* Update operation */ 2828 MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1, 2829 /* Read operation */ 2830 MLXSW_REG_PTCE3_OP_QUERY_READ = 0, 2831 }; 2832 2833 /* reg_ptce3_op 2834 * Access: OP 2835 */ 2836 MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3); 2837 2838 /* reg_ptce3_priority 2839 * Priority of the rule. Higher values win. 2840 * For Spectrum-2 range is 1..cap_kvd_size - 1 2841 * Note: Priority does not have to be unique per rule. 2842 * Access: RW 2843 */ 2844 MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24); 2845 2846 /* reg_ptce3_tcam_region_info 2847 * Opaque object that represents the TCAM region. 2848 * Access: Index 2849 */ 2850 MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10, 2851 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2852 2853 /* reg_ptce3_flex2_key_blocks 2854 * ACL key. The key must be masked according to eRP (if exists) or 2855 * according to master mask. 2856 * Access: Index 2857 */ 2858 MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20, 2859 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2860 2861 /* reg_ptce3_erp_id 2862 * eRP ID. 2863 * Access: Index 2864 */ 2865 MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4); 2866 2867 /* reg_ptce3_delta_start 2868 * Start point of delta_value and delta_mask, in bits. Must not exceed 2869 * num_key_blocks * 36 - 8. Reserved when delta_mask = 0. 2870 * Access: Index 2871 */ 2872 MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10); 2873 2874 /* reg_ptce3_delta_mask 2875 * Delta mask. 2876 * 0 - Ignore relevant bit in delta_value 2877 * 1 - Compare relevant bit in delta_value 2878 * Delta mask must not be set for reserved fields in the key blocks. 2879 * Note: No delta when no eRPs. Thus, for regions with 2880 * PERERP.erpt_pointer_valid = 0 the delta mask must be 0. 2881 * Access: Index 2882 */ 2883 MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8); 2884 2885 /* reg_ptce3_delta_value 2886 * Delta value. 2887 * Bits which are masked by delta_mask must be 0. 2888 * Access: Index 2889 */ 2890 MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8); 2891 2892 /* reg_ptce3_prune_vector 2893 * Pruning vector relative to the PERPT.erp_id. 2894 * Used for reducing lookups. 2895 * 0 - NEED: Do a lookup using the eRP. 2896 * 1 - PRUNE: Do not perform a lookup using the eRP. 2897 * Maybe be modified by PEAPBL and PEAPBM. 2898 * Note: In Spectrum-2, a region of 8 key blocks must be set to either 2899 * all 1's or all 0's. 2900 * Access: RW 2901 */ 2902 MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1); 2903 2904 /* reg_ptce3_prune_ctcam 2905 * Pruning on C-TCAM. Used for reducing lookups. 2906 * 0 - NEED: Do a lookup in the C-TCAM. 2907 * 1 - PRUNE: Do not perform a lookup in the C-TCAM. 2908 * Access: RW 2909 */ 2910 MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1); 2911 2912 /* reg_ptce3_large_exists 2913 * Large entry key ID exists. 2914 * Within the region: 2915 * 0 - SINGLE: The large_entry_key_id is not currently in use. 2916 * For rule insert: The MSB of the key (blocks 6..11) will be added. 2917 * For rule delete: The MSB of the key will be removed. 2918 * 1 - NON_SINGLE: The large_entry_key_id is currently in use. 2919 * For rule insert: The MSB of the key (blocks 6..11) will not be added. 2920 * For rule delete: The MSB of the key will not be removed. 2921 * Access: WO 2922 */ 2923 MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1); 2924 2925 /* reg_ptce3_large_entry_key_id 2926 * Large entry key ID. 2927 * A key for 12 key blocks rules. Reserved when region has less than 12 key 2928 * blocks. Must be different for different keys which have the same common 2929 * 6 key blocks (MSB, blocks 6..11) key within a region. 2930 * Range is 0..cap_max_pe_large_key_id - 1 2931 * Access: RW 2932 */ 2933 MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24); 2934 2935 /* reg_ptce3_action_pointer 2936 * Pointer to action. 2937 * Range is 0..cap_max_kvd_action_sets - 1 2938 * Access: RW 2939 */ 2940 MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24); 2941 2942 static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid, 2943 enum mlxsw_reg_ptce3_op op, 2944 u32 priority, 2945 const char *tcam_region_info, 2946 const char *key, u8 erp_id, 2947 u16 delta_start, u8 delta_mask, 2948 u8 delta_value, bool large_exists, 2949 u32 lkey_id, u32 action_pointer) 2950 { 2951 MLXSW_REG_ZERO(ptce3, payload); 2952 mlxsw_reg_ptce3_v_set(payload, valid); 2953 mlxsw_reg_ptce3_op_set(payload, op); 2954 mlxsw_reg_ptce3_priority_set(payload, priority); 2955 mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info); 2956 mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key); 2957 mlxsw_reg_ptce3_erp_id_set(payload, erp_id); 2958 mlxsw_reg_ptce3_delta_start_set(payload, delta_start); 2959 mlxsw_reg_ptce3_delta_mask_set(payload, delta_mask); 2960 mlxsw_reg_ptce3_delta_value_set(payload, delta_value); 2961 mlxsw_reg_ptce3_large_exists_set(payload, large_exists); 2962 mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id); 2963 mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer); 2964 } 2965 2966 /* PERCR - Policy-Engine Region Configuration Register 2967 * --------------------------------------------------- 2968 * This register configures the region parameters. The region_id must be 2969 * allocated. 2970 */ 2971 #define MLXSW_REG_PERCR_ID 0x302A 2972 #define MLXSW_REG_PERCR_LEN 0x80 2973 2974 MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN); 2975 2976 /* reg_percr_region_id 2977 * Region identifier. 2978 * Range 0..cap_max_regions-1 2979 * Access: Index 2980 */ 2981 MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16); 2982 2983 /* reg_percr_atcam_ignore_prune 2984 * Ignore prune_vector by other A-TCAM rules. Used e.g., for a new rule. 2985 * Access: RW 2986 */ 2987 MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1); 2988 2989 /* reg_percr_ctcam_ignore_prune 2990 * Ignore prune_ctcam by other A-TCAM rules. Used e.g., for a new rule. 2991 * Access: RW 2992 */ 2993 MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1); 2994 2995 /* reg_percr_bf_bypass 2996 * Bloom filter bypass. 2997 * 0 - Bloom filter is used (default) 2998 * 1 - Bloom filter is bypassed. The bypass is an OR condition of 2999 * region_id or eRP. See PERPT.bf_bypass 3000 * Access: RW 3001 */ 3002 MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1); 3003 3004 /* reg_percr_master_mask 3005 * Master mask. Logical OR mask of all masks of all rules of a region 3006 * (both A-TCAM and C-TCAM). When there are no eRPs 3007 * (erpt_pointer_valid = 0), then this provides the mask. 3008 * Access: RW 3009 */ 3010 MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96); 3011 3012 static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id) 3013 { 3014 MLXSW_REG_ZERO(percr, payload); 3015 mlxsw_reg_percr_region_id_set(payload, region_id); 3016 mlxsw_reg_percr_atcam_ignore_prune_set(payload, false); 3017 mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false); 3018 mlxsw_reg_percr_bf_bypass_set(payload, false); 3019 } 3020 3021 /* PERERP - Policy-Engine Region eRP Register 3022 * ------------------------------------------ 3023 * This register configures the region eRP. The region_id must be 3024 * allocated. 3025 */ 3026 #define MLXSW_REG_PERERP_ID 0x302B 3027 #define MLXSW_REG_PERERP_LEN 0x1C 3028 3029 MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN); 3030 3031 /* reg_pererp_region_id 3032 * Region identifier. 3033 * Range 0..cap_max_regions-1 3034 * Access: Index 3035 */ 3036 MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16); 3037 3038 /* reg_pererp_ctcam_le 3039 * C-TCAM lookup enable. Reserved when erpt_pointer_valid = 0. 3040 * Access: RW 3041 */ 3042 MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1); 3043 3044 /* reg_pererp_erpt_pointer_valid 3045 * erpt_pointer is valid. 3046 * Access: RW 3047 */ 3048 MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1); 3049 3050 /* reg_pererp_erpt_bank_pointer 3051 * Pointer to eRP table bank. May be modified at any time. 3052 * Range 0..cap_max_erp_table_banks-1 3053 * Reserved when erpt_pointer_valid = 0 3054 */ 3055 MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4); 3056 3057 /* reg_pererp_erpt_pointer 3058 * Pointer to eRP table within the eRP bank. Can be changed for an 3059 * existing region. 3060 * Range 0..cap_max_erp_table_size-1 3061 * Reserved when erpt_pointer_valid = 0 3062 * Access: RW 3063 */ 3064 MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8); 3065 3066 /* reg_pererp_erpt_vector 3067 * Vector of allowed eRP indexes starting from erpt_pointer within the 3068 * erpt_bank_pointer. Next entries will be in next bank. 3069 * Note that eRP index is used and not eRP ID. 3070 * Reserved when erpt_pointer_valid = 0 3071 * Access: RW 3072 */ 3073 MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1); 3074 3075 /* reg_pererp_master_rp_id 3076 * Master RP ID. When there are no eRPs, then this provides the eRP ID 3077 * for the lookup. Can be changed for an existing region. 3078 * Reserved when erpt_pointer_valid = 1 3079 * Access: RW 3080 */ 3081 MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4); 3082 3083 static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload, 3084 unsigned long *erp_vector, 3085 unsigned long size) 3086 { 3087 unsigned long bit; 3088 3089 for_each_set_bit(bit, erp_vector, size) 3090 mlxsw_reg_pererp_erpt_vector_set(payload, bit, true); 3091 } 3092 3093 static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id, 3094 bool ctcam_le, bool erpt_pointer_valid, 3095 u8 erpt_bank_pointer, u8 erpt_pointer, 3096 u8 master_rp_id) 3097 { 3098 MLXSW_REG_ZERO(pererp, payload); 3099 mlxsw_reg_pererp_region_id_set(payload, region_id); 3100 mlxsw_reg_pererp_ctcam_le_set(payload, ctcam_le); 3101 mlxsw_reg_pererp_erpt_pointer_valid_set(payload, erpt_pointer_valid); 3102 mlxsw_reg_pererp_erpt_bank_pointer_set(payload, erpt_bank_pointer); 3103 mlxsw_reg_pererp_erpt_pointer_set(payload, erpt_pointer); 3104 mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id); 3105 } 3106 3107 /* PEABFE - Policy-Engine Algorithmic Bloom Filter Entries Register 3108 * ---------------------------------------------------------------- 3109 * This register configures the Bloom filter entries. 3110 */ 3111 #define MLXSW_REG_PEABFE_ID 0x3022 3112 #define MLXSW_REG_PEABFE_BASE_LEN 0x10 3113 #define MLXSW_REG_PEABFE_BF_REC_LEN 0x4 3114 #define MLXSW_REG_PEABFE_BF_REC_MAX_COUNT 256 3115 #define MLXSW_REG_PEABFE_LEN (MLXSW_REG_PEABFE_BASE_LEN + \ 3116 MLXSW_REG_PEABFE_BF_REC_LEN * \ 3117 MLXSW_REG_PEABFE_BF_REC_MAX_COUNT) 3118 3119 MLXSW_REG_DEFINE(peabfe, MLXSW_REG_PEABFE_ID, MLXSW_REG_PEABFE_LEN); 3120 3121 /* reg_peabfe_size 3122 * Number of BF entries to be updated. 3123 * Range 1..256 3124 * Access: Op 3125 */ 3126 MLXSW_ITEM32(reg, peabfe, size, 0x00, 0, 9); 3127 3128 /* reg_peabfe_bf_entry_state 3129 * Bloom filter state 3130 * 0 - Clear 3131 * 1 - Set 3132 * Access: RW 3133 */ 3134 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_state, 3135 MLXSW_REG_PEABFE_BASE_LEN, 31, 1, 3136 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3137 3138 /* reg_peabfe_bf_entry_bank 3139 * Bloom filter bank ID 3140 * Range 0..cap_max_erp_table_banks-1 3141 * Access: Index 3142 */ 3143 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_bank, 3144 MLXSW_REG_PEABFE_BASE_LEN, 24, 4, 3145 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3146 3147 /* reg_peabfe_bf_entry_index 3148 * Bloom filter entry index 3149 * Range 0..2^cap_max_bf_log-1 3150 * Access: Index 3151 */ 3152 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_index, 3153 MLXSW_REG_PEABFE_BASE_LEN, 0, 24, 3154 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3155 3156 static inline void mlxsw_reg_peabfe_pack(char *payload) 3157 { 3158 MLXSW_REG_ZERO(peabfe, payload); 3159 } 3160 3161 static inline void mlxsw_reg_peabfe_rec_pack(char *payload, int rec_index, 3162 u8 state, u8 bank, u32 bf_index) 3163 { 3164 u8 num_rec = mlxsw_reg_peabfe_size_get(payload); 3165 3166 if (rec_index >= num_rec) 3167 mlxsw_reg_peabfe_size_set(payload, rec_index + 1); 3168 mlxsw_reg_peabfe_bf_entry_state_set(payload, rec_index, state); 3169 mlxsw_reg_peabfe_bf_entry_bank_set(payload, rec_index, bank); 3170 mlxsw_reg_peabfe_bf_entry_index_set(payload, rec_index, bf_index); 3171 } 3172 3173 /* IEDR - Infrastructure Entry Delete Register 3174 * ---------------------------------------------------- 3175 * This register is used for deleting entries from the entry tables. 3176 * It is legitimate to attempt to delete a nonexisting entry (the device will 3177 * respond as a good flow). 3178 */ 3179 #define MLXSW_REG_IEDR_ID 0x3804 3180 #define MLXSW_REG_IEDR_BASE_LEN 0x10 /* base length, without records */ 3181 #define MLXSW_REG_IEDR_REC_LEN 0x8 /* record length */ 3182 #define MLXSW_REG_IEDR_REC_MAX_COUNT 64 3183 #define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN + \ 3184 MLXSW_REG_IEDR_REC_LEN * \ 3185 MLXSW_REG_IEDR_REC_MAX_COUNT) 3186 3187 MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN); 3188 3189 /* reg_iedr_num_rec 3190 * Number of records. 3191 * Access: OP 3192 */ 3193 MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8); 3194 3195 /* reg_iedr_rec_type 3196 * Resource type. 3197 * Access: OP 3198 */ 3199 MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8, 3200 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3201 3202 /* reg_iedr_rec_size 3203 * Size of entries do be deleted. The unit is 1 entry, regardless of entry type. 3204 * Access: OP 3205 */ 3206 MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 11, 3207 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3208 3209 /* reg_iedr_rec_index_start 3210 * Resource index start. 3211 * Access: OP 3212 */ 3213 MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24, 3214 MLXSW_REG_IEDR_REC_LEN, 0x04, false); 3215 3216 static inline void mlxsw_reg_iedr_pack(char *payload) 3217 { 3218 MLXSW_REG_ZERO(iedr, payload); 3219 } 3220 3221 static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index, 3222 u8 rec_type, u16 rec_size, 3223 u32 rec_index_start) 3224 { 3225 u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload); 3226 3227 if (rec_index >= num_rec) 3228 mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1); 3229 mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type); 3230 mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size); 3231 mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start); 3232 } 3233 3234 /* QPTS - QoS Priority Trust State Register 3235 * ---------------------------------------- 3236 * This register controls the port policy to calculate the switch priority and 3237 * packet color based on incoming packet fields. 3238 */ 3239 #define MLXSW_REG_QPTS_ID 0x4002 3240 #define MLXSW_REG_QPTS_LEN 0x8 3241 3242 MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN); 3243 3244 /* reg_qpts_local_port 3245 * Local port number. 3246 * Access: Index 3247 * 3248 * Note: CPU port is supported. 3249 */ 3250 MLXSW_ITEM32(reg, qpts, local_port, 0x00, 16, 8); 3251 3252 enum mlxsw_reg_qpts_trust_state { 3253 MLXSW_REG_QPTS_TRUST_STATE_PCP = 1, 3254 MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2, /* For MPLS, trust EXP. */ 3255 }; 3256 3257 /* reg_qpts_trust_state 3258 * Trust state for a given port. 3259 * Access: RW 3260 */ 3261 MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3); 3262 3263 static inline void mlxsw_reg_qpts_pack(char *payload, u8 local_port, 3264 enum mlxsw_reg_qpts_trust_state ts) 3265 { 3266 MLXSW_REG_ZERO(qpts, payload); 3267 3268 mlxsw_reg_qpts_local_port_set(payload, local_port); 3269 mlxsw_reg_qpts_trust_state_set(payload, ts); 3270 } 3271 3272 /* QPCR - QoS Policer Configuration Register 3273 * ----------------------------------------- 3274 * The QPCR register is used to create policers - that limit 3275 * the rate of bytes or packets via some trap group. 3276 */ 3277 #define MLXSW_REG_QPCR_ID 0x4004 3278 #define MLXSW_REG_QPCR_LEN 0x28 3279 3280 MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN); 3281 3282 enum mlxsw_reg_qpcr_g { 3283 MLXSW_REG_QPCR_G_GLOBAL = 2, 3284 MLXSW_REG_QPCR_G_STORM_CONTROL = 3, 3285 }; 3286 3287 /* reg_qpcr_g 3288 * The policer type. 3289 * Access: Index 3290 */ 3291 MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2); 3292 3293 /* reg_qpcr_pid 3294 * Policer ID. 3295 * Access: Index 3296 */ 3297 MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14); 3298 3299 /* reg_qpcr_color_aware 3300 * Is the policer aware of colors. 3301 * Must be 0 (unaware) for cpu port. 3302 * Access: RW for unbounded policer. RO for bounded policer. 3303 */ 3304 MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1); 3305 3306 /* reg_qpcr_bytes 3307 * Is policer limit is for bytes per sec or packets per sec. 3308 * 0 - packets 3309 * 1 - bytes 3310 * Access: RW for unbounded policer. RO for bounded policer. 3311 */ 3312 MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1); 3313 3314 enum mlxsw_reg_qpcr_ir_units { 3315 MLXSW_REG_QPCR_IR_UNITS_M, 3316 MLXSW_REG_QPCR_IR_UNITS_K, 3317 }; 3318 3319 /* reg_qpcr_ir_units 3320 * Policer's units for cir and eir fields (for bytes limits only) 3321 * 1 - 10^3 3322 * 0 - 10^6 3323 * Access: OP 3324 */ 3325 MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1); 3326 3327 enum mlxsw_reg_qpcr_rate_type { 3328 MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1, 3329 MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2, 3330 }; 3331 3332 /* reg_qpcr_rate_type 3333 * Policer can have one limit (single rate) or 2 limits with specific operation 3334 * for packets that exceed the lower rate but not the upper one. 3335 * (For cpu port must be single rate) 3336 * Access: RW for unbounded policer. RO for bounded policer. 3337 */ 3338 MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2); 3339 3340 /* reg_qpc_cbs 3341 * Policer's committed burst size. 3342 * The policer is working with time slices of 50 nano sec. By default every 3343 * slice is granted the proportionate share of the committed rate. If we want to 3344 * allow a slice to exceed that share (while still keeping the rate per sec) we 3345 * can allow burst. The burst size is between the default proportionate share 3346 * (and no lower than 8) to 32Gb. (Even though giving a number higher than the 3347 * committed rate will result in exceeding the rate). The burst size must be a 3348 * log of 2 and will be determined by 2^cbs. 3349 * Access: RW 3350 */ 3351 MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6); 3352 3353 /* reg_qpcr_cir 3354 * Policer's committed rate. 3355 * The rate used for sungle rate, the lower rate for double rate. 3356 * For bytes limits, the rate will be this value * the unit from ir_units. 3357 * (Resolution error is up to 1%). 3358 * Access: RW 3359 */ 3360 MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32); 3361 3362 /* reg_qpcr_eir 3363 * Policer's exceed rate. 3364 * The higher rate for double rate, reserved for single rate. 3365 * Lower rate for double rate policer. 3366 * For bytes limits, the rate will be this value * the unit from ir_units. 3367 * (Resolution error is up to 1%). 3368 * Access: RW 3369 */ 3370 MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32); 3371 3372 #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2 3373 3374 /* reg_qpcr_exceed_action. 3375 * What to do with packets between the 2 limits for double rate. 3376 * Access: RW for unbounded policer. RO for bounded policer. 3377 */ 3378 MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4); 3379 3380 enum mlxsw_reg_qpcr_action { 3381 /* Discard */ 3382 MLXSW_REG_QPCR_ACTION_DISCARD = 1, 3383 /* Forward and set color to red. 3384 * If the packet is intended to cpu port, it will be dropped. 3385 */ 3386 MLXSW_REG_QPCR_ACTION_FORWARD = 2, 3387 }; 3388 3389 /* reg_qpcr_violate_action 3390 * What to do with packets that cross the cir limit (for single rate) or the eir 3391 * limit (for double rate). 3392 * Access: RW for unbounded policer. RO for bounded policer. 3393 */ 3394 MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4); 3395 3396 static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid, 3397 enum mlxsw_reg_qpcr_ir_units ir_units, 3398 bool bytes, u32 cir, u16 cbs) 3399 { 3400 MLXSW_REG_ZERO(qpcr, payload); 3401 mlxsw_reg_qpcr_pid_set(payload, pid); 3402 mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL); 3403 mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE); 3404 mlxsw_reg_qpcr_violate_action_set(payload, 3405 MLXSW_REG_QPCR_ACTION_DISCARD); 3406 mlxsw_reg_qpcr_cir_set(payload, cir); 3407 mlxsw_reg_qpcr_ir_units_set(payload, ir_units); 3408 mlxsw_reg_qpcr_bytes_set(payload, bytes); 3409 mlxsw_reg_qpcr_cbs_set(payload, cbs); 3410 } 3411 3412 /* QTCT - QoS Switch Traffic Class Table 3413 * ------------------------------------- 3414 * Configures the mapping between the packet switch priority and the 3415 * traffic class on the transmit port. 3416 */ 3417 #define MLXSW_REG_QTCT_ID 0x400A 3418 #define MLXSW_REG_QTCT_LEN 0x08 3419 3420 MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN); 3421 3422 /* reg_qtct_local_port 3423 * Local port number. 3424 * Access: Index 3425 * 3426 * Note: CPU port is not supported. 3427 */ 3428 MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8); 3429 3430 /* reg_qtct_sub_port 3431 * Virtual port within the physical port. 3432 * Should be set to 0 when virtual ports are not enabled on the port. 3433 * Access: Index 3434 */ 3435 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8); 3436 3437 /* reg_qtct_switch_prio 3438 * Switch priority. 3439 * Access: Index 3440 */ 3441 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4); 3442 3443 /* reg_qtct_tclass 3444 * Traffic class. 3445 * Default values: 3446 * switch_prio 0 : tclass 1 3447 * switch_prio 1 : tclass 0 3448 * switch_prio i : tclass i, for i > 1 3449 * Access: RW 3450 */ 3451 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4); 3452 3453 static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port, 3454 u8 switch_prio, u8 tclass) 3455 { 3456 MLXSW_REG_ZERO(qtct, payload); 3457 mlxsw_reg_qtct_local_port_set(payload, local_port); 3458 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio); 3459 mlxsw_reg_qtct_tclass_set(payload, tclass); 3460 } 3461 3462 /* QEEC - QoS ETS Element Configuration Register 3463 * --------------------------------------------- 3464 * Configures the ETS elements. 3465 */ 3466 #define MLXSW_REG_QEEC_ID 0x400D 3467 #define MLXSW_REG_QEEC_LEN 0x20 3468 3469 MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN); 3470 3471 /* reg_qeec_local_port 3472 * Local port number. 3473 * Access: Index 3474 * 3475 * Note: CPU port is supported. 3476 */ 3477 MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8); 3478 3479 enum mlxsw_reg_qeec_hr { 3480 MLXSW_REG_QEEC_HR_PORT, 3481 MLXSW_REG_QEEC_HR_GROUP, 3482 MLXSW_REG_QEEC_HR_SUBGROUP, 3483 MLXSW_REG_QEEC_HR_TC, 3484 }; 3485 3486 /* reg_qeec_element_hierarchy 3487 * 0 - Port 3488 * 1 - Group 3489 * 2 - Subgroup 3490 * 3 - Traffic Class 3491 * Access: Index 3492 */ 3493 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4); 3494 3495 /* reg_qeec_element_index 3496 * The index of the element in the hierarchy. 3497 * Access: Index 3498 */ 3499 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8); 3500 3501 /* reg_qeec_next_element_index 3502 * The index of the next (lower) element in the hierarchy. 3503 * Access: RW 3504 * 3505 * Note: Reserved for element_hierarchy 0. 3506 */ 3507 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8); 3508 3509 /* reg_qeec_mise 3510 * Min shaper configuration enable. Enables configuration of the min 3511 * shaper on this ETS element 3512 * 0 - Disable 3513 * 1 - Enable 3514 * Access: RW 3515 */ 3516 MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1); 3517 3518 /* reg_qeec_ptps 3519 * PTP shaper 3520 * 0: regular shaper mode 3521 * 1: PTP oriented shaper 3522 * Allowed only for hierarchy 0 3523 * Not supported for CPU port 3524 * Note that ptps mode may affect the shaper rates of all hierarchies 3525 * Supported only on Spectrum-1 3526 * Access: RW 3527 */ 3528 MLXSW_ITEM32(reg, qeec, ptps, 0x0C, 29, 1); 3529 3530 enum { 3531 MLXSW_REG_QEEC_BYTES_MODE, 3532 MLXSW_REG_QEEC_PACKETS_MODE, 3533 }; 3534 3535 /* reg_qeec_pb 3536 * Packets or bytes mode. 3537 * 0 - Bytes mode 3538 * 1 - Packets mode 3539 * Access: RW 3540 * 3541 * Note: Used for max shaper configuration. For Spectrum, packets mode 3542 * is supported only for traffic classes of CPU port. 3543 */ 3544 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1); 3545 3546 /* The smallest permitted min shaper rate. */ 3547 #define MLXSW_REG_QEEC_MIS_MIN 200000 /* Kbps */ 3548 3549 /* reg_qeec_min_shaper_rate 3550 * Min shaper information rate. 3551 * For CPU port, can only be configured for port hierarchy. 3552 * When in bytes mode, value is specified in units of 1000bps. 3553 * Access: RW 3554 */ 3555 MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28); 3556 3557 /* reg_qeec_mase 3558 * Max shaper configuration enable. Enables configuration of the max 3559 * shaper on this ETS element. 3560 * 0 - Disable 3561 * 1 - Enable 3562 * Access: RW 3563 */ 3564 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1); 3565 3566 /* A large max rate will disable the max shaper. */ 3567 #define MLXSW_REG_QEEC_MAS_DIS 200000000 /* Kbps */ 3568 3569 /* reg_qeec_max_shaper_rate 3570 * Max shaper information rate. 3571 * For CPU port, can only be configured for port hierarchy. 3572 * When in bytes mode, value is specified in units of 1000bps. 3573 * Access: RW 3574 */ 3575 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 28); 3576 3577 /* reg_qeec_de 3578 * DWRR configuration enable. Enables configuration of the dwrr and 3579 * dwrr_weight. 3580 * 0 - Disable 3581 * 1 - Enable 3582 * Access: RW 3583 */ 3584 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1); 3585 3586 /* reg_qeec_dwrr 3587 * Transmission selection algorithm to use on the link going down from 3588 * the ETS element. 3589 * 0 - Strict priority 3590 * 1 - DWRR 3591 * Access: RW 3592 */ 3593 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1); 3594 3595 /* reg_qeec_dwrr_weight 3596 * DWRR weight on the link going down from the ETS element. The 3597 * percentage of bandwidth guaranteed to an ETS element within 3598 * its hierarchy. The sum of all weights across all ETS elements 3599 * within one hierarchy should be equal to 100. Reserved when 3600 * transmission selection algorithm is strict priority. 3601 * Access: RW 3602 */ 3603 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8); 3604 3605 static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port, 3606 enum mlxsw_reg_qeec_hr hr, u8 index, 3607 u8 next_index) 3608 { 3609 MLXSW_REG_ZERO(qeec, payload); 3610 mlxsw_reg_qeec_local_port_set(payload, local_port); 3611 mlxsw_reg_qeec_element_hierarchy_set(payload, hr); 3612 mlxsw_reg_qeec_element_index_set(payload, index); 3613 mlxsw_reg_qeec_next_element_index_set(payload, next_index); 3614 } 3615 3616 static inline void mlxsw_reg_qeec_ptps_pack(char *payload, u8 local_port, 3617 bool ptps) 3618 { 3619 MLXSW_REG_ZERO(qeec, payload); 3620 mlxsw_reg_qeec_local_port_set(payload, local_port); 3621 mlxsw_reg_qeec_element_hierarchy_set(payload, MLXSW_REG_QEEC_HR_PORT); 3622 mlxsw_reg_qeec_ptps_set(payload, ptps); 3623 } 3624 3625 /* QRWE - QoS ReWrite Enable 3626 * ------------------------- 3627 * This register configures the rewrite enable per receive port. 3628 */ 3629 #define MLXSW_REG_QRWE_ID 0x400F 3630 #define MLXSW_REG_QRWE_LEN 0x08 3631 3632 MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN); 3633 3634 /* reg_qrwe_local_port 3635 * Local port number. 3636 * Access: Index 3637 * 3638 * Note: CPU port is supported. No support for router port. 3639 */ 3640 MLXSW_ITEM32(reg, qrwe, local_port, 0x00, 16, 8); 3641 3642 /* reg_qrwe_dscp 3643 * Whether to enable DSCP rewrite (default is 0, don't rewrite). 3644 * Access: RW 3645 */ 3646 MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1); 3647 3648 /* reg_qrwe_pcp 3649 * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite). 3650 * Access: RW 3651 */ 3652 MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1); 3653 3654 static inline void mlxsw_reg_qrwe_pack(char *payload, u8 local_port, 3655 bool rewrite_pcp, bool rewrite_dscp) 3656 { 3657 MLXSW_REG_ZERO(qrwe, payload); 3658 mlxsw_reg_qrwe_local_port_set(payload, local_port); 3659 mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp); 3660 mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp); 3661 } 3662 3663 /* QPDSM - QoS Priority to DSCP Mapping 3664 * ------------------------------------ 3665 * QoS Priority to DSCP Mapping Register 3666 */ 3667 #define MLXSW_REG_QPDSM_ID 0x4011 3668 #define MLXSW_REG_QPDSM_BASE_LEN 0x04 /* base length, without records */ 3669 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4 /* record length */ 3670 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 16 3671 #define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN + \ 3672 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN * \ 3673 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT) 3674 3675 MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN); 3676 3677 /* reg_qpdsm_local_port 3678 * Local Port. Supported for data packets from CPU port. 3679 * Access: Index 3680 */ 3681 MLXSW_ITEM32(reg, qpdsm, local_port, 0x00, 16, 8); 3682 3683 /* reg_qpdsm_prio_entry_color0_e 3684 * Enable update of the entry for color 0 and a given port. 3685 * Access: WO 3686 */ 3687 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e, 3688 MLXSW_REG_QPDSM_BASE_LEN, 31, 1, 3689 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3690 3691 /* reg_qpdsm_prio_entry_color0_dscp 3692 * DSCP field in the outer label of the packet for color 0 and a given port. 3693 * Reserved when e=0. 3694 * Access: RW 3695 */ 3696 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp, 3697 MLXSW_REG_QPDSM_BASE_LEN, 24, 6, 3698 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3699 3700 /* reg_qpdsm_prio_entry_color1_e 3701 * Enable update of the entry for color 1 and a given port. 3702 * Access: WO 3703 */ 3704 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e, 3705 MLXSW_REG_QPDSM_BASE_LEN, 23, 1, 3706 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3707 3708 /* reg_qpdsm_prio_entry_color1_dscp 3709 * DSCP field in the outer label of the packet for color 1 and a given port. 3710 * Reserved when e=0. 3711 * Access: RW 3712 */ 3713 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp, 3714 MLXSW_REG_QPDSM_BASE_LEN, 16, 6, 3715 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3716 3717 /* reg_qpdsm_prio_entry_color2_e 3718 * Enable update of the entry for color 2 and a given port. 3719 * Access: WO 3720 */ 3721 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e, 3722 MLXSW_REG_QPDSM_BASE_LEN, 15, 1, 3723 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3724 3725 /* reg_qpdsm_prio_entry_color2_dscp 3726 * DSCP field in the outer label of the packet for color 2 and a given port. 3727 * Reserved when e=0. 3728 * Access: RW 3729 */ 3730 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp, 3731 MLXSW_REG_QPDSM_BASE_LEN, 8, 6, 3732 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3733 3734 static inline void mlxsw_reg_qpdsm_pack(char *payload, u8 local_port) 3735 { 3736 MLXSW_REG_ZERO(qpdsm, payload); 3737 mlxsw_reg_qpdsm_local_port_set(payload, local_port); 3738 } 3739 3740 static inline void 3741 mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp) 3742 { 3743 mlxsw_reg_qpdsm_prio_entry_color0_e_set(payload, prio, 1); 3744 mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(payload, prio, dscp); 3745 mlxsw_reg_qpdsm_prio_entry_color1_e_set(payload, prio, 1); 3746 mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(payload, prio, dscp); 3747 mlxsw_reg_qpdsm_prio_entry_color2_e_set(payload, prio, 1); 3748 mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp); 3749 } 3750 3751 /* QPDPM - QoS Port DSCP to Priority Mapping Register 3752 * -------------------------------------------------- 3753 * This register controls the mapping from DSCP field to 3754 * Switch Priority for IP packets. 3755 */ 3756 #define MLXSW_REG_QPDPM_ID 0x4013 3757 #define MLXSW_REG_QPDPM_BASE_LEN 0x4 /* base length, without records */ 3758 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2 /* record length */ 3759 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64 3760 #define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN + \ 3761 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN * \ 3762 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT) 3763 3764 MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN); 3765 3766 /* reg_qpdpm_local_port 3767 * Local Port. Supported for data packets from CPU port. 3768 * Access: Index 3769 */ 3770 MLXSW_ITEM32(reg, qpdpm, local_port, 0x00, 16, 8); 3771 3772 /* reg_qpdpm_dscp_e 3773 * Enable update of the specific entry. When cleared, the switch_prio and color 3774 * fields are ignored and the previous switch_prio and color values are 3775 * preserved. 3776 * Access: WO 3777 */ 3778 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1, 3779 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 3780 3781 /* reg_qpdpm_dscp_prio 3782 * The new Switch Priority value for the relevant DSCP value. 3783 * Access: RW 3784 */ 3785 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio, 3786 MLXSW_REG_QPDPM_BASE_LEN, 0, 4, 3787 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 3788 3789 static inline void mlxsw_reg_qpdpm_pack(char *payload, u8 local_port) 3790 { 3791 MLXSW_REG_ZERO(qpdpm, payload); 3792 mlxsw_reg_qpdpm_local_port_set(payload, local_port); 3793 } 3794 3795 static inline void 3796 mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio) 3797 { 3798 mlxsw_reg_qpdpm_dscp_entry_e_set(payload, dscp, 1); 3799 mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio); 3800 } 3801 3802 /* QTCTM - QoS Switch Traffic Class Table is Multicast-Aware Register 3803 * ------------------------------------------------------------------ 3804 * This register configures if the Switch Priority to Traffic Class mapping is 3805 * based on Multicast packet indication. If so, then multicast packets will get 3806 * a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by 3807 * QTCT. 3808 * By default, Switch Priority to Traffic Class mapping is not based on 3809 * Multicast packet indication. 3810 */ 3811 #define MLXSW_REG_QTCTM_ID 0x401A 3812 #define MLXSW_REG_QTCTM_LEN 0x08 3813 3814 MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN); 3815 3816 /* reg_qtctm_local_port 3817 * Local port number. 3818 * No support for CPU port. 3819 * Access: Index 3820 */ 3821 MLXSW_ITEM32(reg, qtctm, local_port, 0x00, 16, 8); 3822 3823 /* reg_qtctm_mc 3824 * Multicast Mode 3825 * Whether Switch Priority to Traffic Class mapping is based on Multicast packet 3826 * indication (default is 0, not based on Multicast packet indication). 3827 */ 3828 MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1); 3829 3830 static inline void 3831 mlxsw_reg_qtctm_pack(char *payload, u8 local_port, bool mc) 3832 { 3833 MLXSW_REG_ZERO(qtctm, payload); 3834 mlxsw_reg_qtctm_local_port_set(payload, local_port); 3835 mlxsw_reg_qtctm_mc_set(payload, mc); 3836 } 3837 3838 /* QPSC - QoS PTP Shaper Configuration Register 3839 * -------------------------------------------- 3840 * The QPSC allows advanced configuration of the shapers when QEEC.ptps=1. 3841 * Supported only on Spectrum-1. 3842 */ 3843 #define MLXSW_REG_QPSC_ID 0x401B 3844 #define MLXSW_REG_QPSC_LEN 0x28 3845 3846 MLXSW_REG_DEFINE(qpsc, MLXSW_REG_QPSC_ID, MLXSW_REG_QPSC_LEN); 3847 3848 enum mlxsw_reg_qpsc_port_speed { 3849 MLXSW_REG_QPSC_PORT_SPEED_100M, 3850 MLXSW_REG_QPSC_PORT_SPEED_1G, 3851 MLXSW_REG_QPSC_PORT_SPEED_10G, 3852 MLXSW_REG_QPSC_PORT_SPEED_25G, 3853 }; 3854 3855 /* reg_qpsc_port_speed 3856 * Port speed. 3857 * Access: Index 3858 */ 3859 MLXSW_ITEM32(reg, qpsc, port_speed, 0x00, 0, 4); 3860 3861 /* reg_qpsc_shaper_time_exp 3862 * The base-time-interval for updating the shapers tokens (for all hierarchies). 3863 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec 3864 * shaper_rate = 64bit * shaper_inc / shaper_update_rate 3865 * Access: RW 3866 */ 3867 MLXSW_ITEM32(reg, qpsc, shaper_time_exp, 0x04, 16, 4); 3868 3869 /* reg_qpsc_shaper_time_mantissa 3870 * The base-time-interval for updating the shapers tokens (for all hierarchies). 3871 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec 3872 * shaper_rate = 64bit * shaper_inc / shaper_update_rate 3873 * Access: RW 3874 */ 3875 MLXSW_ITEM32(reg, qpsc, shaper_time_mantissa, 0x04, 0, 5); 3876 3877 /* reg_qpsc_shaper_inc 3878 * Number of tokens added to shaper on each update. 3879 * Units of 8B. 3880 * Access: RW 3881 */ 3882 MLXSW_ITEM32(reg, qpsc, shaper_inc, 0x08, 0, 5); 3883 3884 /* reg_qpsc_shaper_bs 3885 * Max shaper Burst size. 3886 * Burst size is 2 ^ max_shaper_bs * 512 [bits] 3887 * Range is: 5..25 (from 2KB..2GB) 3888 * Access: RW 3889 */ 3890 MLXSW_ITEM32(reg, qpsc, shaper_bs, 0x0C, 0, 6); 3891 3892 /* reg_qpsc_ptsc_we 3893 * Write enable to port_to_shaper_credits. 3894 * Access: WO 3895 */ 3896 MLXSW_ITEM32(reg, qpsc, ptsc_we, 0x10, 31, 1); 3897 3898 /* reg_qpsc_port_to_shaper_credits 3899 * For split ports: range 1..57 3900 * For non-split ports: range 1..112 3901 * Written only when ptsc_we is set. 3902 * Access: RW 3903 */ 3904 MLXSW_ITEM32(reg, qpsc, port_to_shaper_credits, 0x10, 0, 8); 3905 3906 /* reg_qpsc_ing_timestamp_inc 3907 * Ingress timestamp increment. 3908 * 2's complement. 3909 * The timestamp of MTPPTR at ingress will be incremented by this value. Global 3910 * value for all ports. 3911 * Same units as used by MTPPTR. 3912 * Access: RW 3913 */ 3914 MLXSW_ITEM32(reg, qpsc, ing_timestamp_inc, 0x20, 0, 32); 3915 3916 /* reg_qpsc_egr_timestamp_inc 3917 * Egress timestamp increment. 3918 * 2's complement. 3919 * The timestamp of MTPPTR at egress will be incremented by this value. Global 3920 * value for all ports. 3921 * Same units as used by MTPPTR. 3922 * Access: RW 3923 */ 3924 MLXSW_ITEM32(reg, qpsc, egr_timestamp_inc, 0x24, 0, 32); 3925 3926 static inline void 3927 mlxsw_reg_qpsc_pack(char *payload, enum mlxsw_reg_qpsc_port_speed port_speed, 3928 u8 shaper_time_exp, u8 shaper_time_mantissa, u8 shaper_inc, 3929 u8 shaper_bs, u8 port_to_shaper_credits, 3930 int ing_timestamp_inc, int egr_timestamp_inc) 3931 { 3932 MLXSW_REG_ZERO(qpsc, payload); 3933 mlxsw_reg_qpsc_port_speed_set(payload, port_speed); 3934 mlxsw_reg_qpsc_shaper_time_exp_set(payload, shaper_time_exp); 3935 mlxsw_reg_qpsc_shaper_time_mantissa_set(payload, shaper_time_mantissa); 3936 mlxsw_reg_qpsc_shaper_inc_set(payload, shaper_inc); 3937 mlxsw_reg_qpsc_shaper_bs_set(payload, shaper_bs); 3938 mlxsw_reg_qpsc_ptsc_we_set(payload, true); 3939 mlxsw_reg_qpsc_port_to_shaper_credits_set(payload, port_to_shaper_credits); 3940 mlxsw_reg_qpsc_ing_timestamp_inc_set(payload, ing_timestamp_inc); 3941 mlxsw_reg_qpsc_egr_timestamp_inc_set(payload, egr_timestamp_inc); 3942 } 3943 3944 /* PMLP - Ports Module to Local Port Register 3945 * ------------------------------------------ 3946 * Configures the assignment of modules to local ports. 3947 */ 3948 #define MLXSW_REG_PMLP_ID 0x5002 3949 #define MLXSW_REG_PMLP_LEN 0x40 3950 3951 MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN); 3952 3953 /* reg_pmlp_rxtx 3954 * 0 - Tx value is used for both Tx and Rx. 3955 * 1 - Rx value is taken from a separte field. 3956 * Access: RW 3957 */ 3958 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1); 3959 3960 /* reg_pmlp_local_port 3961 * Local port number. 3962 * Access: Index 3963 */ 3964 MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8); 3965 3966 /* reg_pmlp_width 3967 * 0 - Unmap local port. 3968 * 1 - Lane 0 is used. 3969 * 2 - Lanes 0 and 1 are used. 3970 * 4 - Lanes 0, 1, 2 and 3 are used. 3971 * 8 - Lanes 0-7 are used. 3972 * Access: RW 3973 */ 3974 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8); 3975 3976 /* reg_pmlp_module 3977 * Module number. 3978 * Access: RW 3979 */ 3980 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false); 3981 3982 /* reg_pmlp_tx_lane 3983 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well. 3984 * Access: RW 3985 */ 3986 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 4, 0x04, 0x00, false); 3987 3988 /* reg_pmlp_rx_lane 3989 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is 3990 * equal to Tx lane. 3991 * Access: RW 3992 */ 3993 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 4, 0x04, 0x00, false); 3994 3995 static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port) 3996 { 3997 MLXSW_REG_ZERO(pmlp, payload); 3998 mlxsw_reg_pmlp_local_port_set(payload, local_port); 3999 } 4000 4001 /* PMTU - Port MTU Register 4002 * ------------------------ 4003 * Configures and reports the port MTU. 4004 */ 4005 #define MLXSW_REG_PMTU_ID 0x5003 4006 #define MLXSW_REG_PMTU_LEN 0x10 4007 4008 MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN); 4009 4010 /* reg_pmtu_local_port 4011 * Local port number. 4012 * Access: Index 4013 */ 4014 MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8); 4015 4016 /* reg_pmtu_max_mtu 4017 * Maximum MTU. 4018 * When port type (e.g. Ethernet) is configured, the relevant MTU is 4019 * reported, otherwise the minimum between the max_mtu of the different 4020 * types is reported. 4021 * Access: RO 4022 */ 4023 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16); 4024 4025 /* reg_pmtu_admin_mtu 4026 * MTU value to set port to. Must be smaller or equal to max_mtu. 4027 * Note: If port type is Infiniband, then port must be disabled, when its 4028 * MTU is set. 4029 * Access: RW 4030 */ 4031 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16); 4032 4033 /* reg_pmtu_oper_mtu 4034 * The actual MTU configured on the port. Packets exceeding this size 4035 * will be dropped. 4036 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband 4037 * oper_mtu might be smaller than admin_mtu. 4038 * Access: RO 4039 */ 4040 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16); 4041 4042 static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port, 4043 u16 new_mtu) 4044 { 4045 MLXSW_REG_ZERO(pmtu, payload); 4046 mlxsw_reg_pmtu_local_port_set(payload, local_port); 4047 mlxsw_reg_pmtu_max_mtu_set(payload, 0); 4048 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu); 4049 mlxsw_reg_pmtu_oper_mtu_set(payload, 0); 4050 } 4051 4052 /* PTYS - Port Type and Speed Register 4053 * ----------------------------------- 4054 * Configures and reports the port speed type. 4055 * 4056 * Note: When set while the link is up, the changes will not take effect 4057 * until the port transitions from down to up state. 4058 */ 4059 #define MLXSW_REG_PTYS_ID 0x5004 4060 #define MLXSW_REG_PTYS_LEN 0x40 4061 4062 MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN); 4063 4064 /* an_disable_admin 4065 * Auto negotiation disable administrative configuration 4066 * 0 - Device doesn't support AN disable. 4067 * 1 - Device supports AN disable. 4068 * Access: RW 4069 */ 4070 MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1); 4071 4072 /* reg_ptys_local_port 4073 * Local port number. 4074 * Access: Index 4075 */ 4076 MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8); 4077 4078 #define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0) 4079 #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2) 4080 4081 /* reg_ptys_proto_mask 4082 * Protocol mask. Indicates which protocol is used. 4083 * 0 - Infiniband. 4084 * 1 - Fibre Channel. 4085 * 2 - Ethernet. 4086 * Access: Index 4087 */ 4088 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3); 4089 4090 enum { 4091 MLXSW_REG_PTYS_AN_STATUS_NA, 4092 MLXSW_REG_PTYS_AN_STATUS_OK, 4093 MLXSW_REG_PTYS_AN_STATUS_FAIL, 4094 }; 4095 4096 /* reg_ptys_an_status 4097 * Autonegotiation status. 4098 * Access: RO 4099 */ 4100 MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4); 4101 4102 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M BIT(0) 4103 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII BIT(1) 4104 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_2_5GBASE_X_2_5GMII BIT(2) 4105 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R BIT(3) 4106 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G BIT(4) 4107 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G BIT(5) 4108 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR BIT(6) 4109 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 BIT(7) 4110 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR BIT(8) 4111 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4 BIT(9) 4112 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2 BIT(10) 4113 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4 BIT(12) 4114 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_8 BIT(15) 4115 4116 /* reg_ptys_ext_eth_proto_cap 4117 * Extended Ethernet port supported speeds and protocols. 4118 * Access: RO 4119 */ 4120 MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32); 4121 4122 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0) 4123 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1) 4124 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2) 4125 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3) 4126 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4) 4127 #define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2 BIT(5) 4128 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6) 4129 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7) 4130 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12) 4131 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13) 4132 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14) 4133 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15) 4134 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16) 4135 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18) 4136 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19) 4137 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20) 4138 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21) 4139 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22) 4140 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23) 4141 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX BIT(24) 4142 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(25) 4143 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T BIT(26) 4144 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27) 4145 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28) 4146 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29) 4147 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30) 4148 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31) 4149 4150 /* reg_ptys_eth_proto_cap 4151 * Ethernet port supported speeds and protocols. 4152 * Access: RO 4153 */ 4154 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32); 4155 4156 /* reg_ptys_ib_link_width_cap 4157 * IB port supported widths. 4158 * Access: RO 4159 */ 4160 MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16); 4161 4162 #define MLXSW_REG_PTYS_IB_SPEED_SDR BIT(0) 4163 #define MLXSW_REG_PTYS_IB_SPEED_DDR BIT(1) 4164 #define MLXSW_REG_PTYS_IB_SPEED_QDR BIT(2) 4165 #define MLXSW_REG_PTYS_IB_SPEED_FDR10 BIT(3) 4166 #define MLXSW_REG_PTYS_IB_SPEED_FDR BIT(4) 4167 #define MLXSW_REG_PTYS_IB_SPEED_EDR BIT(5) 4168 4169 /* reg_ptys_ib_proto_cap 4170 * IB port supported speeds and protocols. 4171 * Access: RO 4172 */ 4173 MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16); 4174 4175 /* reg_ptys_ext_eth_proto_admin 4176 * Extended speed and protocol to set port to. 4177 * Access: RW 4178 */ 4179 MLXSW_ITEM32(reg, ptys, ext_eth_proto_admin, 0x14, 0, 32); 4180 4181 /* reg_ptys_eth_proto_admin 4182 * Speed and protocol to set port to. 4183 * Access: RW 4184 */ 4185 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32); 4186 4187 /* reg_ptys_ib_link_width_admin 4188 * IB width to set port to. 4189 * Access: RW 4190 */ 4191 MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16); 4192 4193 /* reg_ptys_ib_proto_admin 4194 * IB speeds and protocols to set port to. 4195 * Access: RW 4196 */ 4197 MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16); 4198 4199 /* reg_ptys_ext_eth_proto_oper 4200 * The extended current speed and protocol configured for the port. 4201 * Access: RO 4202 */ 4203 MLXSW_ITEM32(reg, ptys, ext_eth_proto_oper, 0x20, 0, 32); 4204 4205 /* reg_ptys_eth_proto_oper 4206 * The current speed and protocol configured for the port. 4207 * Access: RO 4208 */ 4209 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32); 4210 4211 /* reg_ptys_ib_link_width_oper 4212 * The current IB width to set port to. 4213 * Access: RO 4214 */ 4215 MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16); 4216 4217 /* reg_ptys_ib_proto_oper 4218 * The current IB speed and protocol. 4219 * Access: RO 4220 */ 4221 MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16); 4222 4223 enum mlxsw_reg_ptys_connector_type { 4224 MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR, 4225 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE, 4226 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP, 4227 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI, 4228 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC, 4229 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII, 4230 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE, 4231 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA, 4232 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER, 4233 }; 4234 4235 /* reg_ptys_connector_type 4236 * Connector type indication. 4237 * Access: RO 4238 */ 4239 MLXSW_ITEM32(reg, ptys, connector_type, 0x2C, 0, 4); 4240 4241 static inline void mlxsw_reg_ptys_eth_pack(char *payload, u8 local_port, 4242 u32 proto_admin, bool autoneg) 4243 { 4244 MLXSW_REG_ZERO(ptys, payload); 4245 mlxsw_reg_ptys_local_port_set(payload, local_port); 4246 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4247 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin); 4248 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4249 } 4250 4251 static inline void mlxsw_reg_ptys_ext_eth_pack(char *payload, u8 local_port, 4252 u32 proto_admin, bool autoneg) 4253 { 4254 MLXSW_REG_ZERO(ptys, payload); 4255 mlxsw_reg_ptys_local_port_set(payload, local_port); 4256 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4257 mlxsw_reg_ptys_ext_eth_proto_admin_set(payload, proto_admin); 4258 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4259 } 4260 4261 static inline void mlxsw_reg_ptys_eth_unpack(char *payload, 4262 u32 *p_eth_proto_cap, 4263 u32 *p_eth_proto_admin, 4264 u32 *p_eth_proto_oper) 4265 { 4266 if (p_eth_proto_cap) 4267 *p_eth_proto_cap = 4268 mlxsw_reg_ptys_eth_proto_cap_get(payload); 4269 if (p_eth_proto_admin) 4270 *p_eth_proto_admin = 4271 mlxsw_reg_ptys_eth_proto_admin_get(payload); 4272 if (p_eth_proto_oper) 4273 *p_eth_proto_oper = 4274 mlxsw_reg_ptys_eth_proto_oper_get(payload); 4275 } 4276 4277 static inline void mlxsw_reg_ptys_ext_eth_unpack(char *payload, 4278 u32 *p_eth_proto_cap, 4279 u32 *p_eth_proto_admin, 4280 u32 *p_eth_proto_oper) 4281 { 4282 if (p_eth_proto_cap) 4283 *p_eth_proto_cap = 4284 mlxsw_reg_ptys_ext_eth_proto_cap_get(payload); 4285 if (p_eth_proto_admin) 4286 *p_eth_proto_admin = 4287 mlxsw_reg_ptys_ext_eth_proto_admin_get(payload); 4288 if (p_eth_proto_oper) 4289 *p_eth_proto_oper = 4290 mlxsw_reg_ptys_ext_eth_proto_oper_get(payload); 4291 } 4292 4293 static inline void mlxsw_reg_ptys_ib_pack(char *payload, u8 local_port, 4294 u16 proto_admin, u16 link_width) 4295 { 4296 MLXSW_REG_ZERO(ptys, payload); 4297 mlxsw_reg_ptys_local_port_set(payload, local_port); 4298 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB); 4299 mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin); 4300 mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width); 4301 } 4302 4303 static inline void mlxsw_reg_ptys_ib_unpack(char *payload, u16 *p_ib_proto_cap, 4304 u16 *p_ib_link_width_cap, 4305 u16 *p_ib_proto_oper, 4306 u16 *p_ib_link_width_oper) 4307 { 4308 if (p_ib_proto_cap) 4309 *p_ib_proto_cap = mlxsw_reg_ptys_ib_proto_cap_get(payload); 4310 if (p_ib_link_width_cap) 4311 *p_ib_link_width_cap = 4312 mlxsw_reg_ptys_ib_link_width_cap_get(payload); 4313 if (p_ib_proto_oper) 4314 *p_ib_proto_oper = mlxsw_reg_ptys_ib_proto_oper_get(payload); 4315 if (p_ib_link_width_oper) 4316 *p_ib_link_width_oper = 4317 mlxsw_reg_ptys_ib_link_width_oper_get(payload); 4318 } 4319 4320 /* PPAD - Port Physical Address Register 4321 * ------------------------------------- 4322 * The PPAD register configures the per port physical MAC address. 4323 */ 4324 #define MLXSW_REG_PPAD_ID 0x5005 4325 #define MLXSW_REG_PPAD_LEN 0x10 4326 4327 MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN); 4328 4329 /* reg_ppad_single_base_mac 4330 * 0: base_mac, local port should be 0 and mac[7:0] is 4331 * reserved. HW will set incremental 4332 * 1: single_mac - mac of the local_port 4333 * Access: RW 4334 */ 4335 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1); 4336 4337 /* reg_ppad_local_port 4338 * port number, if single_base_mac = 0 then local_port is reserved 4339 * Access: RW 4340 */ 4341 MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8); 4342 4343 /* reg_ppad_mac 4344 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved. 4345 * If single_base_mac = 1 - the per port MAC address 4346 * Access: RW 4347 */ 4348 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6); 4349 4350 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac, 4351 u8 local_port) 4352 { 4353 MLXSW_REG_ZERO(ppad, payload); 4354 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac); 4355 mlxsw_reg_ppad_local_port_set(payload, local_port); 4356 } 4357 4358 /* PAOS - Ports Administrative and Operational Status Register 4359 * ----------------------------------------------------------- 4360 * Configures and retrieves per port administrative and operational status. 4361 */ 4362 #define MLXSW_REG_PAOS_ID 0x5006 4363 #define MLXSW_REG_PAOS_LEN 0x10 4364 4365 MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN); 4366 4367 /* reg_paos_swid 4368 * Switch partition ID with which to associate the port. 4369 * Note: while external ports uses unique local port numbers (and thus swid is 4370 * redundant), router ports use the same local port number where swid is the 4371 * only indication for the relevant port. 4372 * Access: Index 4373 */ 4374 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8); 4375 4376 /* reg_paos_local_port 4377 * Local port number. 4378 * Access: Index 4379 */ 4380 MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8); 4381 4382 /* reg_paos_admin_status 4383 * Port administrative state (the desired state of the port): 4384 * 1 - Up. 4385 * 2 - Down. 4386 * 3 - Up once. This means that in case of link failure, the port won't go 4387 * into polling mode, but will wait to be re-enabled by software. 4388 * 4 - Disabled by system. Can only be set by hardware. 4389 * Access: RW 4390 */ 4391 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4); 4392 4393 /* reg_paos_oper_status 4394 * Port operational state (the current state): 4395 * 1 - Up. 4396 * 2 - Down. 4397 * 3 - Down by port failure. This means that the device will not let the 4398 * port up again until explicitly specified by software. 4399 * Access: RO 4400 */ 4401 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4); 4402 4403 /* reg_paos_ase 4404 * Admin state update enabled. 4405 * Access: WO 4406 */ 4407 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1); 4408 4409 /* reg_paos_ee 4410 * Event update enable. If this bit is set, event generation will be 4411 * updated based on the e field. 4412 * Access: WO 4413 */ 4414 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1); 4415 4416 /* reg_paos_e 4417 * Event generation on operational state change: 4418 * 0 - Do not generate event. 4419 * 1 - Generate Event. 4420 * 2 - Generate Single Event. 4421 * Access: RW 4422 */ 4423 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2); 4424 4425 static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port, 4426 enum mlxsw_port_admin_status status) 4427 { 4428 MLXSW_REG_ZERO(paos, payload); 4429 mlxsw_reg_paos_swid_set(payload, 0); 4430 mlxsw_reg_paos_local_port_set(payload, local_port); 4431 mlxsw_reg_paos_admin_status_set(payload, status); 4432 mlxsw_reg_paos_oper_status_set(payload, 0); 4433 mlxsw_reg_paos_ase_set(payload, 1); 4434 mlxsw_reg_paos_ee_set(payload, 1); 4435 mlxsw_reg_paos_e_set(payload, 1); 4436 } 4437 4438 /* PFCC - Ports Flow Control Configuration Register 4439 * ------------------------------------------------ 4440 * Configures and retrieves the per port flow control configuration. 4441 */ 4442 #define MLXSW_REG_PFCC_ID 0x5007 4443 #define MLXSW_REG_PFCC_LEN 0x20 4444 4445 MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN); 4446 4447 /* reg_pfcc_local_port 4448 * Local port number. 4449 * Access: Index 4450 */ 4451 MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8); 4452 4453 /* reg_pfcc_pnat 4454 * Port number access type. Determines the way local_port is interpreted: 4455 * 0 - Local port number. 4456 * 1 - IB / label port number. 4457 * Access: Index 4458 */ 4459 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2); 4460 4461 /* reg_pfcc_shl_cap 4462 * Send to higher layers capabilities: 4463 * 0 - No capability of sending Pause and PFC frames to higher layers. 4464 * 1 - Device has capability of sending Pause and PFC frames to higher 4465 * layers. 4466 * Access: RO 4467 */ 4468 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1); 4469 4470 /* reg_pfcc_shl_opr 4471 * Send to higher layers operation: 4472 * 0 - Pause and PFC frames are handled by the port (default). 4473 * 1 - Pause and PFC frames are handled by the port and also sent to 4474 * higher layers. Only valid if shl_cap = 1. 4475 * Access: RW 4476 */ 4477 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1); 4478 4479 /* reg_pfcc_ppan 4480 * Pause policy auto negotiation. 4481 * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx. 4482 * 1 - Enabled. When auto-negotiation is performed, set the Pause policy 4483 * based on the auto-negotiation resolution. 4484 * Access: RW 4485 * 4486 * Note: The auto-negotiation advertisement is set according to pptx and 4487 * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0. 4488 */ 4489 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4); 4490 4491 /* reg_pfcc_prio_mask_tx 4492 * Bit per priority indicating if Tx flow control policy should be 4493 * updated based on bit pfctx. 4494 * Access: WO 4495 */ 4496 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8); 4497 4498 /* reg_pfcc_prio_mask_rx 4499 * Bit per priority indicating if Rx flow control policy should be 4500 * updated based on bit pfcrx. 4501 * Access: WO 4502 */ 4503 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8); 4504 4505 /* reg_pfcc_pptx 4506 * Admin Pause policy on Tx. 4507 * 0 - Never generate Pause frames (default). 4508 * 1 - Generate Pause frames according to Rx buffer threshold. 4509 * Access: RW 4510 */ 4511 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1); 4512 4513 /* reg_pfcc_aptx 4514 * Active (operational) Pause policy on Tx. 4515 * 0 - Never generate Pause frames. 4516 * 1 - Generate Pause frames according to Rx buffer threshold. 4517 * Access: RO 4518 */ 4519 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1); 4520 4521 /* reg_pfcc_pfctx 4522 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask: 4523 * 0 - Never generate priority Pause frames on the specified priority 4524 * (default). 4525 * 1 - Generate priority Pause frames according to Rx buffer threshold on 4526 * the specified priority. 4527 * Access: RW 4528 * 4529 * Note: pfctx and pptx must be mutually exclusive. 4530 */ 4531 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8); 4532 4533 /* reg_pfcc_pprx 4534 * Admin Pause policy on Rx. 4535 * 0 - Ignore received Pause frames (default). 4536 * 1 - Respect received Pause frames. 4537 * Access: RW 4538 */ 4539 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1); 4540 4541 /* reg_pfcc_aprx 4542 * Active (operational) Pause policy on Rx. 4543 * 0 - Ignore received Pause frames. 4544 * 1 - Respect received Pause frames. 4545 * Access: RO 4546 */ 4547 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1); 4548 4549 /* reg_pfcc_pfcrx 4550 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask: 4551 * 0 - Ignore incoming priority Pause frames on the specified priority 4552 * (default). 4553 * 1 - Respect incoming priority Pause frames on the specified priority. 4554 * Access: RW 4555 */ 4556 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8); 4557 4558 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF 4559 4560 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en) 4561 { 4562 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 4563 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 4564 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en); 4565 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en); 4566 } 4567 4568 static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port) 4569 { 4570 MLXSW_REG_ZERO(pfcc, payload); 4571 mlxsw_reg_pfcc_local_port_set(payload, local_port); 4572 } 4573 4574 /* PPCNT - Ports Performance Counters Register 4575 * ------------------------------------------- 4576 * The PPCNT register retrieves per port performance counters. 4577 */ 4578 #define MLXSW_REG_PPCNT_ID 0x5008 4579 #define MLXSW_REG_PPCNT_LEN 0x100 4580 #define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08 4581 4582 MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN); 4583 4584 /* reg_ppcnt_swid 4585 * For HCA: must be always 0. 4586 * Switch partition ID to associate port with. 4587 * Switch partitions are numbered from 0 to 7 inclusively. 4588 * Switch partition 254 indicates stacking ports. 4589 * Switch partition 255 indicates all switch partitions. 4590 * Only valid on Set() operation with local_port=255. 4591 * Access: Index 4592 */ 4593 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8); 4594 4595 /* reg_ppcnt_local_port 4596 * Local port number. 4597 * 255 indicates all ports on the device, and is only allowed 4598 * for Set() operation. 4599 * Access: Index 4600 */ 4601 MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8); 4602 4603 /* reg_ppcnt_pnat 4604 * Port number access type: 4605 * 0 - Local port number 4606 * 1 - IB port number 4607 * Access: Index 4608 */ 4609 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2); 4610 4611 enum mlxsw_reg_ppcnt_grp { 4612 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0, 4613 MLXSW_REG_PPCNT_RFC_2863_CNT = 0x1, 4614 MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2, 4615 MLXSW_REG_PPCNT_RFC_3635_CNT = 0x3, 4616 MLXSW_REG_PPCNT_EXT_CNT = 0x5, 4617 MLXSW_REG_PPCNT_DISCARD_CNT = 0x6, 4618 MLXSW_REG_PPCNT_PRIO_CNT = 0x10, 4619 MLXSW_REG_PPCNT_TC_CNT = 0x11, 4620 MLXSW_REG_PPCNT_TC_CONG_TC = 0x13, 4621 }; 4622 4623 /* reg_ppcnt_grp 4624 * Performance counter group. 4625 * Group 63 indicates all groups. Only valid on Set() operation with 4626 * clr bit set. 4627 * 0x0: IEEE 802.3 Counters 4628 * 0x1: RFC 2863 Counters 4629 * 0x2: RFC 2819 Counters 4630 * 0x3: RFC 3635 Counters 4631 * 0x5: Ethernet Extended Counters 4632 * 0x6: Ethernet Discard Counters 4633 * 0x8: Link Level Retransmission Counters 4634 * 0x10: Per Priority Counters 4635 * 0x11: Per Traffic Class Counters 4636 * 0x12: Physical Layer Counters 4637 * 0x13: Per Traffic Class Congestion Counters 4638 * Access: Index 4639 */ 4640 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6); 4641 4642 /* reg_ppcnt_clr 4643 * Clear counters. Setting the clr bit will reset the counter value 4644 * for all counters in the counter group. This bit can be set 4645 * for both Set() and Get() operation. 4646 * Access: OP 4647 */ 4648 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1); 4649 4650 /* reg_ppcnt_prio_tc 4651 * Priority for counter set that support per priority, valid values: 0-7. 4652 * Traffic class for counter set that support per traffic class, 4653 * valid values: 0- cap_max_tclass-1 . 4654 * For HCA: cap_max_tclass is always 8. 4655 * Otherwise must be 0. 4656 * Access: Index 4657 */ 4658 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5); 4659 4660 /* Ethernet IEEE 802.3 Counter Group */ 4661 4662 /* reg_ppcnt_a_frames_transmitted_ok 4663 * Access: RO 4664 */ 4665 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok, 4666 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4667 4668 /* reg_ppcnt_a_frames_received_ok 4669 * Access: RO 4670 */ 4671 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok, 4672 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4673 4674 /* reg_ppcnt_a_frame_check_sequence_errors 4675 * Access: RO 4676 */ 4677 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors, 4678 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 4679 4680 /* reg_ppcnt_a_alignment_errors 4681 * Access: RO 4682 */ 4683 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors, 4684 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 4685 4686 /* reg_ppcnt_a_octets_transmitted_ok 4687 * Access: RO 4688 */ 4689 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok, 4690 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 4691 4692 /* reg_ppcnt_a_octets_received_ok 4693 * Access: RO 4694 */ 4695 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok, 4696 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 4697 4698 /* reg_ppcnt_a_multicast_frames_xmitted_ok 4699 * Access: RO 4700 */ 4701 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok, 4702 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 4703 4704 /* reg_ppcnt_a_broadcast_frames_xmitted_ok 4705 * Access: RO 4706 */ 4707 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok, 4708 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 4709 4710 /* reg_ppcnt_a_multicast_frames_received_ok 4711 * Access: RO 4712 */ 4713 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok, 4714 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 4715 4716 /* reg_ppcnt_a_broadcast_frames_received_ok 4717 * Access: RO 4718 */ 4719 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok, 4720 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 4721 4722 /* reg_ppcnt_a_in_range_length_errors 4723 * Access: RO 4724 */ 4725 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors, 4726 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 4727 4728 /* reg_ppcnt_a_out_of_range_length_field 4729 * Access: RO 4730 */ 4731 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field, 4732 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 4733 4734 /* reg_ppcnt_a_frame_too_long_errors 4735 * Access: RO 4736 */ 4737 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors, 4738 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4739 4740 /* reg_ppcnt_a_symbol_error_during_carrier 4741 * Access: RO 4742 */ 4743 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier, 4744 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 4745 4746 /* reg_ppcnt_a_mac_control_frames_transmitted 4747 * Access: RO 4748 */ 4749 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted, 4750 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4751 4752 /* reg_ppcnt_a_mac_control_frames_received 4753 * Access: RO 4754 */ 4755 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received, 4756 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 4757 4758 /* reg_ppcnt_a_unsupported_opcodes_received 4759 * Access: RO 4760 */ 4761 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received, 4762 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 4763 4764 /* reg_ppcnt_a_pause_mac_ctrl_frames_received 4765 * Access: RO 4766 */ 4767 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received, 4768 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 4769 4770 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted 4771 * Access: RO 4772 */ 4773 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted, 4774 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 4775 4776 /* Ethernet RFC 2863 Counter Group */ 4777 4778 /* reg_ppcnt_if_in_discards 4779 * Access: RO 4780 */ 4781 MLXSW_ITEM64(reg, ppcnt, if_in_discards, 4782 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 4783 4784 /* reg_ppcnt_if_out_discards 4785 * Access: RO 4786 */ 4787 MLXSW_ITEM64(reg, ppcnt, if_out_discards, 4788 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 4789 4790 /* reg_ppcnt_if_out_errors 4791 * Access: RO 4792 */ 4793 MLXSW_ITEM64(reg, ppcnt, if_out_errors, 4794 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 4795 4796 /* Ethernet RFC 2819 Counter Group */ 4797 4798 /* reg_ppcnt_ether_stats_undersize_pkts 4799 * Access: RO 4800 */ 4801 MLXSW_ITEM64(reg, ppcnt, ether_stats_undersize_pkts, 4802 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 4803 4804 /* reg_ppcnt_ether_stats_oversize_pkts 4805 * Access: RO 4806 */ 4807 MLXSW_ITEM64(reg, ppcnt, ether_stats_oversize_pkts, 4808 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 4809 4810 /* reg_ppcnt_ether_stats_fragments 4811 * Access: RO 4812 */ 4813 MLXSW_ITEM64(reg, ppcnt, ether_stats_fragments, 4814 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 4815 4816 /* reg_ppcnt_ether_stats_pkts64octets 4817 * Access: RO 4818 */ 4819 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets, 4820 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 4821 4822 /* reg_ppcnt_ether_stats_pkts65to127octets 4823 * Access: RO 4824 */ 4825 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets, 4826 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4827 4828 /* reg_ppcnt_ether_stats_pkts128to255octets 4829 * Access: RO 4830 */ 4831 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets, 4832 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 4833 4834 /* reg_ppcnt_ether_stats_pkts256to511octets 4835 * Access: RO 4836 */ 4837 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets, 4838 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4839 4840 /* reg_ppcnt_ether_stats_pkts512to1023octets 4841 * Access: RO 4842 */ 4843 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets, 4844 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 4845 4846 /* reg_ppcnt_ether_stats_pkts1024to1518octets 4847 * Access: RO 4848 */ 4849 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets, 4850 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 4851 4852 /* reg_ppcnt_ether_stats_pkts1519to2047octets 4853 * Access: RO 4854 */ 4855 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets, 4856 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 4857 4858 /* reg_ppcnt_ether_stats_pkts2048to4095octets 4859 * Access: RO 4860 */ 4861 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets, 4862 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 4863 4864 /* reg_ppcnt_ether_stats_pkts4096to8191octets 4865 * Access: RO 4866 */ 4867 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets, 4868 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64); 4869 4870 /* reg_ppcnt_ether_stats_pkts8192to10239octets 4871 * Access: RO 4872 */ 4873 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets, 4874 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64); 4875 4876 /* Ethernet RFC 3635 Counter Group */ 4877 4878 /* reg_ppcnt_dot3stats_fcs_errors 4879 * Access: RO 4880 */ 4881 MLXSW_ITEM64(reg, ppcnt, dot3stats_fcs_errors, 4882 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4883 4884 /* reg_ppcnt_dot3stats_symbol_errors 4885 * Access: RO 4886 */ 4887 MLXSW_ITEM64(reg, ppcnt, dot3stats_symbol_errors, 4888 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4889 4890 /* reg_ppcnt_dot3control_in_unknown_opcodes 4891 * Access: RO 4892 */ 4893 MLXSW_ITEM64(reg, ppcnt, dot3control_in_unknown_opcodes, 4894 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 4895 4896 /* reg_ppcnt_dot3in_pause_frames 4897 * Access: RO 4898 */ 4899 MLXSW_ITEM64(reg, ppcnt, dot3in_pause_frames, 4900 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4901 4902 /* Ethernet Extended Counter Group Counters */ 4903 4904 /* reg_ppcnt_ecn_marked 4905 * Access: RO 4906 */ 4907 MLXSW_ITEM64(reg, ppcnt, ecn_marked, 4908 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4909 4910 /* Ethernet Discard Counter Group Counters */ 4911 4912 /* reg_ppcnt_ingress_general 4913 * Access: RO 4914 */ 4915 MLXSW_ITEM64(reg, ppcnt, ingress_general, 4916 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4917 4918 /* reg_ppcnt_ingress_policy_engine 4919 * Access: RO 4920 */ 4921 MLXSW_ITEM64(reg, ppcnt, ingress_policy_engine, 4922 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4923 4924 /* reg_ppcnt_ingress_vlan_membership 4925 * Access: RO 4926 */ 4927 MLXSW_ITEM64(reg, ppcnt, ingress_vlan_membership, 4928 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 4929 4930 /* reg_ppcnt_ingress_tag_frame_type 4931 * Access: RO 4932 */ 4933 MLXSW_ITEM64(reg, ppcnt, ingress_tag_frame_type, 4934 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 4935 4936 /* reg_ppcnt_egress_vlan_membership 4937 * Access: RO 4938 */ 4939 MLXSW_ITEM64(reg, ppcnt, egress_vlan_membership, 4940 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 4941 4942 /* reg_ppcnt_loopback_filter 4943 * Access: RO 4944 */ 4945 MLXSW_ITEM64(reg, ppcnt, loopback_filter, 4946 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 4947 4948 /* reg_ppcnt_egress_general 4949 * Access: RO 4950 */ 4951 MLXSW_ITEM64(reg, ppcnt, egress_general, 4952 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 4953 4954 /* reg_ppcnt_egress_hoq 4955 * Access: RO 4956 */ 4957 MLXSW_ITEM64(reg, ppcnt, egress_hoq, 4958 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 4959 4960 /* reg_ppcnt_egress_policy_engine 4961 * Access: RO 4962 */ 4963 MLXSW_ITEM64(reg, ppcnt, egress_policy_engine, 4964 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 4965 4966 /* reg_ppcnt_ingress_tx_link_down 4967 * Access: RO 4968 */ 4969 MLXSW_ITEM64(reg, ppcnt, ingress_tx_link_down, 4970 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 4971 4972 /* reg_ppcnt_egress_stp_filter 4973 * Access: RO 4974 */ 4975 MLXSW_ITEM64(reg, ppcnt, egress_stp_filter, 4976 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4977 4978 /* reg_ppcnt_egress_sll 4979 * Access: RO 4980 */ 4981 MLXSW_ITEM64(reg, ppcnt, egress_sll, 4982 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4983 4984 /* Ethernet Per Priority Group Counters */ 4985 4986 /* reg_ppcnt_rx_octets 4987 * Access: RO 4988 */ 4989 MLXSW_ITEM64(reg, ppcnt, rx_octets, 4990 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4991 4992 /* reg_ppcnt_rx_frames 4993 * Access: RO 4994 */ 4995 MLXSW_ITEM64(reg, ppcnt, rx_frames, 4996 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 4997 4998 /* reg_ppcnt_tx_octets 4999 * Access: RO 5000 */ 5001 MLXSW_ITEM64(reg, ppcnt, tx_octets, 5002 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5003 5004 /* reg_ppcnt_tx_frames 5005 * Access: RO 5006 */ 5007 MLXSW_ITEM64(reg, ppcnt, tx_frames, 5008 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 5009 5010 /* reg_ppcnt_rx_pause 5011 * Access: RO 5012 */ 5013 MLXSW_ITEM64(reg, ppcnt, rx_pause, 5014 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5015 5016 /* reg_ppcnt_rx_pause_duration 5017 * Access: RO 5018 */ 5019 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration, 5020 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5021 5022 /* reg_ppcnt_tx_pause 5023 * Access: RO 5024 */ 5025 MLXSW_ITEM64(reg, ppcnt, tx_pause, 5026 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5027 5028 /* reg_ppcnt_tx_pause_duration 5029 * Access: RO 5030 */ 5031 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration, 5032 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5033 5034 /* reg_ppcnt_rx_pause_transition 5035 * Access: RO 5036 */ 5037 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition, 5038 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5039 5040 /* Ethernet Per Traffic Group Counters */ 5041 5042 /* reg_ppcnt_tc_transmit_queue 5043 * Contains the transmit queue depth in cells of traffic class 5044 * selected by prio_tc and the port selected by local_port. 5045 * The field cannot be cleared. 5046 * Access: RO 5047 */ 5048 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue, 5049 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5050 5051 /* reg_ppcnt_tc_no_buffer_discard_uc 5052 * The number of unicast packets dropped due to lack of shared 5053 * buffer resources. 5054 * Access: RO 5055 */ 5056 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc, 5057 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5058 5059 /* Ethernet Per Traffic Class Congestion Group Counters */ 5060 5061 /* reg_ppcnt_wred_discard 5062 * Access: RO 5063 */ 5064 MLXSW_ITEM64(reg, ppcnt, wred_discard, 5065 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5066 5067 static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port, 5068 enum mlxsw_reg_ppcnt_grp grp, 5069 u8 prio_tc) 5070 { 5071 MLXSW_REG_ZERO(ppcnt, payload); 5072 mlxsw_reg_ppcnt_swid_set(payload, 0); 5073 mlxsw_reg_ppcnt_local_port_set(payload, local_port); 5074 mlxsw_reg_ppcnt_pnat_set(payload, 0); 5075 mlxsw_reg_ppcnt_grp_set(payload, grp); 5076 mlxsw_reg_ppcnt_clr_set(payload, 0); 5077 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc); 5078 } 5079 5080 /* PLIB - Port Local to InfiniBand Port 5081 * ------------------------------------ 5082 * The PLIB register performs mapping from Local Port into InfiniBand Port. 5083 */ 5084 #define MLXSW_REG_PLIB_ID 0x500A 5085 #define MLXSW_REG_PLIB_LEN 0x10 5086 5087 MLXSW_REG_DEFINE(plib, MLXSW_REG_PLIB_ID, MLXSW_REG_PLIB_LEN); 5088 5089 /* reg_plib_local_port 5090 * Local port number. 5091 * Access: Index 5092 */ 5093 MLXSW_ITEM32(reg, plib, local_port, 0x00, 16, 8); 5094 5095 /* reg_plib_ib_port 5096 * InfiniBand port remapping for local_port. 5097 * Access: RW 5098 */ 5099 MLXSW_ITEM32(reg, plib, ib_port, 0x00, 0, 8); 5100 5101 /* PPTB - Port Prio To Buffer Register 5102 * ----------------------------------- 5103 * Configures the switch priority to buffer table. 5104 */ 5105 #define MLXSW_REG_PPTB_ID 0x500B 5106 #define MLXSW_REG_PPTB_LEN 0x10 5107 5108 MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN); 5109 5110 enum { 5111 MLXSW_REG_PPTB_MM_UM, 5112 MLXSW_REG_PPTB_MM_UNICAST, 5113 MLXSW_REG_PPTB_MM_MULTICAST, 5114 }; 5115 5116 /* reg_pptb_mm 5117 * Mapping mode. 5118 * 0 - Map both unicast and multicast packets to the same buffer. 5119 * 1 - Map only unicast packets. 5120 * 2 - Map only multicast packets. 5121 * Access: Index 5122 * 5123 * Note: SwitchX-2 only supports the first option. 5124 */ 5125 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2); 5126 5127 /* reg_pptb_local_port 5128 * Local port number. 5129 * Access: Index 5130 */ 5131 MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8); 5132 5133 /* reg_pptb_um 5134 * Enables the update of the untagged_buf field. 5135 * Access: RW 5136 */ 5137 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1); 5138 5139 /* reg_pptb_pm 5140 * Enables the update of the prio_to_buff field. 5141 * Bit <i> is a flag for updating the mapping for switch priority <i>. 5142 * Access: RW 5143 */ 5144 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8); 5145 5146 /* reg_pptb_prio_to_buff 5147 * Mapping of switch priority <i> to one of the allocated receive port 5148 * buffers. 5149 * Access: RW 5150 */ 5151 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4); 5152 5153 /* reg_pptb_pm_msb 5154 * Enables the update of the prio_to_buff field. 5155 * Bit <i> is a flag for updating the mapping for switch priority <i+8>. 5156 * Access: RW 5157 */ 5158 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8); 5159 5160 /* reg_pptb_untagged_buff 5161 * Mapping of untagged frames to one of the allocated receive port buffers. 5162 * Access: RW 5163 * 5164 * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for 5165 * Spectrum, as it maps untagged packets based on the default switch priority. 5166 */ 5167 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4); 5168 5169 /* reg_pptb_prio_to_buff_msb 5170 * Mapping of switch priority <i+8> to one of the allocated receive port 5171 * buffers. 5172 * Access: RW 5173 */ 5174 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4); 5175 5176 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF 5177 5178 static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port) 5179 { 5180 MLXSW_REG_ZERO(pptb, payload); 5181 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM); 5182 mlxsw_reg_pptb_local_port_set(payload, local_port); 5183 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 5184 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 5185 } 5186 5187 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio, 5188 u8 buff) 5189 { 5190 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff); 5191 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff); 5192 } 5193 5194 /* PBMC - Port Buffer Management Control Register 5195 * ---------------------------------------------- 5196 * The PBMC register configures and retrieves the port packet buffer 5197 * allocation for different Prios, and the Pause threshold management. 5198 */ 5199 #define MLXSW_REG_PBMC_ID 0x500C 5200 #define MLXSW_REG_PBMC_LEN 0x6C 5201 5202 MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN); 5203 5204 /* reg_pbmc_local_port 5205 * Local port number. 5206 * Access: Index 5207 */ 5208 MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8); 5209 5210 /* reg_pbmc_xoff_timer_value 5211 * When device generates a pause frame, it uses this value as the pause 5212 * timer (time for the peer port to pause in quota-512 bit time). 5213 * Access: RW 5214 */ 5215 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16); 5216 5217 /* reg_pbmc_xoff_refresh 5218 * The time before a new pause frame should be sent to refresh the pause RW 5219 * state. Using the same units as xoff_timer_value above (in quota-512 bit 5220 * time). 5221 * Access: RW 5222 */ 5223 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16); 5224 5225 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11 5226 5227 /* reg_pbmc_buf_lossy 5228 * The field indicates if the buffer is lossy. 5229 * 0 - Lossless 5230 * 1 - Lossy 5231 * Access: RW 5232 */ 5233 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false); 5234 5235 /* reg_pbmc_buf_epsb 5236 * Eligible for Port Shared buffer. 5237 * If epsb is set, packets assigned to buffer are allowed to insert the port 5238 * shared buffer. 5239 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved. 5240 * Access: RW 5241 */ 5242 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false); 5243 5244 /* reg_pbmc_buf_size 5245 * The part of the packet buffer array is allocated for the specific buffer. 5246 * Units are represented in cells. 5247 * Access: RW 5248 */ 5249 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false); 5250 5251 /* reg_pbmc_buf_xoff_threshold 5252 * Once the amount of data in the buffer goes above this value, device 5253 * starts sending PFC frames for all priorities associated with the 5254 * buffer. Units are represented in cells. Reserved in case of lossy 5255 * buffer. 5256 * Access: RW 5257 * 5258 * Note: In Spectrum, reserved for buffer[9]. 5259 */ 5260 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16, 5261 0x08, 0x04, false); 5262 5263 /* reg_pbmc_buf_xon_threshold 5264 * When the amount of data in the buffer goes below this value, device 5265 * stops sending PFC frames for the priorities associated with the 5266 * buffer. Units are represented in cells. Reserved in case of lossy 5267 * buffer. 5268 * Access: RW 5269 * 5270 * Note: In Spectrum, reserved for buffer[9]. 5271 */ 5272 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16, 5273 0x08, 0x04, false); 5274 5275 static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port, 5276 u16 xoff_timer_value, u16 xoff_refresh) 5277 { 5278 MLXSW_REG_ZERO(pbmc, payload); 5279 mlxsw_reg_pbmc_local_port_set(payload, local_port); 5280 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value); 5281 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh); 5282 } 5283 5284 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload, 5285 int buf_index, 5286 u16 size) 5287 { 5288 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1); 5289 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5290 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5291 } 5292 5293 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload, 5294 int buf_index, u16 size, 5295 u16 threshold) 5296 { 5297 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0); 5298 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5299 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5300 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold); 5301 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold); 5302 } 5303 5304 /* PSPA - Port Switch Partition Allocation 5305 * --------------------------------------- 5306 * Controls the association of a port with a switch partition and enables 5307 * configuring ports as stacking ports. 5308 */ 5309 #define MLXSW_REG_PSPA_ID 0x500D 5310 #define MLXSW_REG_PSPA_LEN 0x8 5311 5312 MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN); 5313 5314 /* reg_pspa_swid 5315 * Switch partition ID. 5316 * Access: RW 5317 */ 5318 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8); 5319 5320 /* reg_pspa_local_port 5321 * Local port number. 5322 * Access: Index 5323 */ 5324 MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8); 5325 5326 /* reg_pspa_sub_port 5327 * Virtual port within the local port. Set to 0 when virtual ports are 5328 * disabled on the local port. 5329 * Access: Index 5330 */ 5331 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8); 5332 5333 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port) 5334 { 5335 MLXSW_REG_ZERO(pspa, payload); 5336 mlxsw_reg_pspa_swid_set(payload, swid); 5337 mlxsw_reg_pspa_local_port_set(payload, local_port); 5338 mlxsw_reg_pspa_sub_port_set(payload, 0); 5339 } 5340 5341 /* PPLR - Port Physical Loopback Register 5342 * -------------------------------------- 5343 * This register allows configuration of the port's loopback mode. 5344 */ 5345 #define MLXSW_REG_PPLR_ID 0x5018 5346 #define MLXSW_REG_PPLR_LEN 0x8 5347 5348 MLXSW_REG_DEFINE(pplr, MLXSW_REG_PPLR_ID, MLXSW_REG_PPLR_LEN); 5349 5350 /* reg_pplr_local_port 5351 * Local port number. 5352 * Access: Index 5353 */ 5354 MLXSW_ITEM32(reg, pplr, local_port, 0x00, 16, 8); 5355 5356 /* Phy local loopback. When set the port's egress traffic is looped back 5357 * to the receiver and the port transmitter is disabled. 5358 */ 5359 #define MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL BIT(1) 5360 5361 /* reg_pplr_lb_en 5362 * Loopback enable. 5363 * Access: RW 5364 */ 5365 MLXSW_ITEM32(reg, pplr, lb_en, 0x04, 0, 8); 5366 5367 static inline void mlxsw_reg_pplr_pack(char *payload, u8 local_port, 5368 bool phy_local) 5369 { 5370 MLXSW_REG_ZERO(pplr, payload); 5371 mlxsw_reg_pplr_local_port_set(payload, local_port); 5372 mlxsw_reg_pplr_lb_en_set(payload, 5373 phy_local ? 5374 MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL : 0); 5375 } 5376 5377 /* PMTM - Port Module Type Mapping Register 5378 * ---------------------------------------- 5379 * The PMTM allows query or configuration of module types. 5380 */ 5381 #define MLXSW_REG_PMTM_ID 0x5067 5382 #define MLXSW_REG_PMTM_LEN 0x10 5383 5384 MLXSW_REG_DEFINE(pmtm, MLXSW_REG_PMTM_ID, MLXSW_REG_PMTM_LEN); 5385 5386 /* reg_pmtm_module 5387 * Module number. 5388 * Access: Index 5389 */ 5390 MLXSW_ITEM32(reg, pmtm, module, 0x00, 16, 8); 5391 5392 enum mlxsw_reg_pmtm_module_type { 5393 /* Backplane with 4 lanes */ 5394 MLXSW_REG_PMTM_MODULE_TYPE_BP_4X, 5395 /* QSFP */ 5396 MLXSW_REG_PMTM_MODULE_TYPE_BP_QSFP, 5397 /* SFP */ 5398 MLXSW_REG_PMTM_MODULE_TYPE_BP_SFP, 5399 /* Backplane with single lane */ 5400 MLXSW_REG_PMTM_MODULE_TYPE_BP_1X = 4, 5401 /* Backplane with two lane */ 5402 MLXSW_REG_PMTM_MODULE_TYPE_BP_2X = 8, 5403 /* Chip2Chip */ 5404 MLXSW_REG_PMTM_MODULE_TYPE_C2C = 10, 5405 }; 5406 5407 /* reg_pmtm_module_type 5408 * Module type. 5409 * Access: RW 5410 */ 5411 MLXSW_ITEM32(reg, pmtm, module_type, 0x04, 0, 4); 5412 5413 static inline void mlxsw_reg_pmtm_pack(char *payload, u8 module) 5414 { 5415 MLXSW_REG_ZERO(pmtm, payload); 5416 mlxsw_reg_pmtm_module_set(payload, module); 5417 } 5418 5419 static inline void 5420 mlxsw_reg_pmtm_unpack(char *payload, 5421 enum mlxsw_reg_pmtm_module_type *module_type) 5422 { 5423 *module_type = mlxsw_reg_pmtm_module_type_get(payload); 5424 } 5425 5426 /* HTGT - Host Trap Group Table 5427 * ---------------------------- 5428 * Configures the properties for forwarding to CPU. 5429 */ 5430 #define MLXSW_REG_HTGT_ID 0x7002 5431 #define MLXSW_REG_HTGT_LEN 0x20 5432 5433 MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN); 5434 5435 /* reg_htgt_swid 5436 * Switch partition ID. 5437 * Access: Index 5438 */ 5439 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8); 5440 5441 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */ 5442 5443 /* reg_htgt_type 5444 * CPU path type. 5445 * Access: RW 5446 */ 5447 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4); 5448 5449 enum mlxsw_reg_htgt_trap_group { 5450 MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 5451 MLXSW_REG_HTGT_TRAP_GROUP_SX2_RX, 5452 MLXSW_REG_HTGT_TRAP_GROUP_SX2_CTRL, 5453 MLXSW_REG_HTGT_TRAP_GROUP_SP_STP, 5454 MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP, 5455 MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP, 5456 MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP, 5457 MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP, 5458 MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF, 5459 MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM, 5460 MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST, 5461 MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP, 5462 MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS, 5463 MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP, 5464 MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE, 5465 MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME, 5466 MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP, 5467 MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF, 5468 MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT, 5469 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD, 5470 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND, 5471 MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR, 5472 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0, 5473 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1, 5474 5475 __MLXSW_REG_HTGT_TRAP_GROUP_MAX, 5476 MLXSW_REG_HTGT_TRAP_GROUP_MAX = __MLXSW_REG_HTGT_TRAP_GROUP_MAX - 1 5477 }; 5478 5479 enum mlxsw_reg_htgt_discard_trap_group { 5480 MLXSW_REG_HTGT_DISCARD_TRAP_GROUP_BASE = MLXSW_REG_HTGT_TRAP_GROUP_MAX, 5481 MLXSW_REG_HTGT_TRAP_GROUP_SP_L2_DISCARDS, 5482 MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_DISCARDS, 5483 }; 5484 5485 /* reg_htgt_trap_group 5486 * Trap group number. User defined number specifying which trap groups 5487 * should be forwarded to the CPU. The mapping between trap IDs and trap 5488 * groups is configured using HPKT register. 5489 * Access: Index 5490 */ 5491 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8); 5492 5493 enum { 5494 MLXSW_REG_HTGT_POLICER_DISABLE, 5495 MLXSW_REG_HTGT_POLICER_ENABLE, 5496 }; 5497 5498 /* reg_htgt_pide 5499 * Enable policer ID specified using 'pid' field. 5500 * Access: RW 5501 */ 5502 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1); 5503 5504 #define MLXSW_REG_HTGT_INVALID_POLICER 0xff 5505 5506 /* reg_htgt_pid 5507 * Policer ID for the trap group. 5508 * Access: RW 5509 */ 5510 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8); 5511 5512 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0 5513 5514 /* reg_htgt_mirror_action 5515 * Mirror action to use. 5516 * 0 - Trap to CPU. 5517 * 1 - Trap to CPU and mirror to a mirroring agent. 5518 * 2 - Mirror to a mirroring agent and do not trap to CPU. 5519 * Access: RW 5520 * 5521 * Note: Mirroring to a mirroring agent is only supported in Spectrum. 5522 */ 5523 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2); 5524 5525 /* reg_htgt_mirroring_agent 5526 * Mirroring agent. 5527 * Access: RW 5528 */ 5529 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3); 5530 5531 #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0 5532 5533 /* reg_htgt_priority 5534 * Trap group priority. 5535 * In case a packet matches multiple classification rules, the packet will 5536 * only be trapped once, based on the trap ID associated with the group (via 5537 * register HPKT) with the highest priority. 5538 * Supported values are 0-7, with 7 represnting the highest priority. 5539 * Access: RW 5540 * 5541 * Note: In SwitchX-2 this field is ignored and the priority value is replaced 5542 * by the 'trap_group' field. 5543 */ 5544 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4); 5545 5546 #define MLXSW_REG_HTGT_DEFAULT_TC 7 5547 5548 /* reg_htgt_local_path_cpu_tclass 5549 * CPU ingress traffic class for the trap group. 5550 * Access: RW 5551 */ 5552 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6); 5553 5554 enum mlxsw_reg_htgt_local_path_rdq { 5555 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13, 5556 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14, 5557 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15, 5558 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15, 5559 }; 5560 /* reg_htgt_local_path_rdq 5561 * Receive descriptor queue (RDQ) to use for the trap group. 5562 * Access: RW 5563 */ 5564 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6); 5565 5566 static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id, 5567 u8 priority, u8 tc) 5568 { 5569 MLXSW_REG_ZERO(htgt, payload); 5570 5571 if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) { 5572 mlxsw_reg_htgt_pide_set(payload, 5573 MLXSW_REG_HTGT_POLICER_DISABLE); 5574 } else { 5575 mlxsw_reg_htgt_pide_set(payload, 5576 MLXSW_REG_HTGT_POLICER_ENABLE); 5577 mlxsw_reg_htgt_pid_set(payload, policer_id); 5578 } 5579 5580 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL); 5581 mlxsw_reg_htgt_trap_group_set(payload, group); 5582 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU); 5583 mlxsw_reg_htgt_mirroring_agent_set(payload, 0); 5584 mlxsw_reg_htgt_priority_set(payload, priority); 5585 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc); 5586 mlxsw_reg_htgt_local_path_rdq_set(payload, group); 5587 } 5588 5589 /* HPKT - Host Packet Trap 5590 * ----------------------- 5591 * Configures trap IDs inside trap groups. 5592 */ 5593 #define MLXSW_REG_HPKT_ID 0x7003 5594 #define MLXSW_REG_HPKT_LEN 0x10 5595 5596 MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN); 5597 5598 enum { 5599 MLXSW_REG_HPKT_ACK_NOT_REQUIRED, 5600 MLXSW_REG_HPKT_ACK_REQUIRED, 5601 }; 5602 5603 /* reg_hpkt_ack 5604 * Require acknowledgements from the host for events. 5605 * If set, then the device will wait for the event it sent to be acknowledged 5606 * by the host. This option is only relevant for event trap IDs. 5607 * Access: RW 5608 * 5609 * Note: Currently not supported by firmware. 5610 */ 5611 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1); 5612 5613 enum mlxsw_reg_hpkt_action { 5614 MLXSW_REG_HPKT_ACTION_FORWARD, 5615 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU, 5616 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU, 5617 MLXSW_REG_HPKT_ACTION_DISCARD, 5618 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD, 5619 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD, 5620 MLXSW_REG_HPKT_ACTION_TRAP_EXCEPTION_TO_CPU, 5621 MLXSW_REG_HPKT_ACTION_SET_FW_DEFAULT = 15, 5622 }; 5623 5624 /* reg_hpkt_action 5625 * Action to perform on packet when trapped. 5626 * 0 - No action. Forward to CPU based on switching rules. 5627 * 1 - Trap to CPU (CPU receives sole copy). 5628 * 2 - Mirror to CPU (CPU receives a replica of the packet). 5629 * 3 - Discard. 5630 * 4 - Soft discard (allow other traps to act on the packet). 5631 * 5 - Trap and soft discard (allow other traps to overwrite this trap). 5632 * 6 - Trap to CPU (CPU receives sole copy) and count it as error. 5633 * 15 - Restore the firmware's default action. 5634 * Access: RW 5635 * 5636 * Note: Must be set to 0 (forward) for event trap IDs, as they are already 5637 * addressed to the CPU. 5638 */ 5639 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3); 5640 5641 /* reg_hpkt_trap_group 5642 * Trap group to associate the trap with. 5643 * Access: RW 5644 */ 5645 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6); 5646 5647 /* reg_hpkt_trap_id 5648 * Trap ID. 5649 * Access: Index 5650 * 5651 * Note: A trap ID can only be associated with a single trap group. The device 5652 * will associate the trap ID with the last trap group configured. 5653 */ 5654 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9); 5655 5656 enum { 5657 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT, 5658 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER, 5659 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER, 5660 }; 5661 5662 /* reg_hpkt_ctrl 5663 * Configure dedicated buffer resources for control packets. 5664 * Ignored by SwitchX-2. 5665 * 0 - Keep factory defaults. 5666 * 1 - Do not use control buffer for this trap ID. 5667 * 2 - Use control buffer for this trap ID. 5668 * Access: RW 5669 */ 5670 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2); 5671 5672 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id, 5673 enum mlxsw_reg_htgt_trap_group trap_group, 5674 bool is_ctrl) 5675 { 5676 MLXSW_REG_ZERO(hpkt, payload); 5677 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED); 5678 mlxsw_reg_hpkt_action_set(payload, action); 5679 mlxsw_reg_hpkt_trap_group_set(payload, trap_group); 5680 mlxsw_reg_hpkt_trap_id_set(payload, trap_id); 5681 mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ? 5682 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER : 5683 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER); 5684 } 5685 5686 /* RGCR - Router General Configuration Register 5687 * -------------------------------------------- 5688 * The register is used for setting up the router configuration. 5689 */ 5690 #define MLXSW_REG_RGCR_ID 0x8001 5691 #define MLXSW_REG_RGCR_LEN 0x28 5692 5693 MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN); 5694 5695 /* reg_rgcr_ipv4_en 5696 * IPv4 router enable. 5697 * Access: RW 5698 */ 5699 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1); 5700 5701 /* reg_rgcr_ipv6_en 5702 * IPv6 router enable. 5703 * Access: RW 5704 */ 5705 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1); 5706 5707 /* reg_rgcr_max_router_interfaces 5708 * Defines the maximum number of active router interfaces for all virtual 5709 * routers. 5710 * Access: RW 5711 */ 5712 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16); 5713 5714 /* reg_rgcr_usp 5715 * Update switch priority and packet color. 5716 * 0 - Preserve the value of Switch Priority and packet color. 5717 * 1 - Recalculate the value of Switch Priority and packet color. 5718 * Access: RW 5719 * 5720 * Note: Not supported by SwitchX and SwitchX-2. 5721 */ 5722 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1); 5723 5724 /* reg_rgcr_pcp_rw 5725 * Indicates how to handle the pcp_rewrite_en value: 5726 * 0 - Preserve the value of pcp_rewrite_en. 5727 * 2 - Disable PCP rewrite. 5728 * 3 - Enable PCP rewrite. 5729 * Access: RW 5730 * 5731 * Note: Not supported by SwitchX and SwitchX-2. 5732 */ 5733 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2); 5734 5735 /* reg_rgcr_activity_dis 5736 * Activity disable: 5737 * 0 - Activity will be set when an entry is hit (default). 5738 * 1 - Activity will not be set when an entry is hit. 5739 * 5740 * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry 5741 * (RALUE). 5742 * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host 5743 * Entry (RAUHT). 5744 * Bits 2:7 are reserved. 5745 * Access: RW 5746 * 5747 * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB. 5748 */ 5749 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8); 5750 5751 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en, 5752 bool ipv6_en) 5753 { 5754 MLXSW_REG_ZERO(rgcr, payload); 5755 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en); 5756 mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en); 5757 } 5758 5759 /* RITR - Router Interface Table Register 5760 * -------------------------------------- 5761 * The register is used to configure the router interface table. 5762 */ 5763 #define MLXSW_REG_RITR_ID 0x8002 5764 #define MLXSW_REG_RITR_LEN 0x40 5765 5766 MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN); 5767 5768 /* reg_ritr_enable 5769 * Enables routing on the router interface. 5770 * Access: RW 5771 */ 5772 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1); 5773 5774 /* reg_ritr_ipv4 5775 * IPv4 routing enable. Enables routing of IPv4 traffic on the router 5776 * interface. 5777 * Access: RW 5778 */ 5779 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1); 5780 5781 /* reg_ritr_ipv6 5782 * IPv6 routing enable. Enables routing of IPv6 traffic on the router 5783 * interface. 5784 * Access: RW 5785 */ 5786 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1); 5787 5788 /* reg_ritr_ipv4_mc 5789 * IPv4 multicast routing enable. 5790 * Access: RW 5791 */ 5792 MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1); 5793 5794 /* reg_ritr_ipv6_mc 5795 * IPv6 multicast routing enable. 5796 * Access: RW 5797 */ 5798 MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1); 5799 5800 enum mlxsw_reg_ritr_if_type { 5801 /* VLAN interface. */ 5802 MLXSW_REG_RITR_VLAN_IF, 5803 /* FID interface. */ 5804 MLXSW_REG_RITR_FID_IF, 5805 /* Sub-port interface. */ 5806 MLXSW_REG_RITR_SP_IF, 5807 /* Loopback Interface. */ 5808 MLXSW_REG_RITR_LOOPBACK_IF, 5809 }; 5810 5811 /* reg_ritr_type 5812 * Router interface type as per enum mlxsw_reg_ritr_if_type. 5813 * Access: RW 5814 */ 5815 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3); 5816 5817 enum { 5818 MLXSW_REG_RITR_RIF_CREATE, 5819 MLXSW_REG_RITR_RIF_DEL, 5820 }; 5821 5822 /* reg_ritr_op 5823 * Opcode: 5824 * 0 - Create or edit RIF. 5825 * 1 - Delete RIF. 5826 * Reserved for SwitchX-2. For Spectrum, editing of interface properties 5827 * is not supported. An interface must be deleted and re-created in order 5828 * to update properties. 5829 * Access: WO 5830 */ 5831 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2); 5832 5833 /* reg_ritr_rif 5834 * Router interface index. A pointer to the Router Interface Table. 5835 * Access: Index 5836 */ 5837 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16); 5838 5839 /* reg_ritr_ipv4_fe 5840 * IPv4 Forwarding Enable. 5841 * Enables routing of IPv4 traffic on the router interface. When disabled, 5842 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 5843 * Not supported in SwitchX-2. 5844 * Access: RW 5845 */ 5846 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1); 5847 5848 /* reg_ritr_ipv6_fe 5849 * IPv6 Forwarding Enable. 5850 * Enables routing of IPv6 traffic on the router interface. When disabled, 5851 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 5852 * Not supported in SwitchX-2. 5853 * Access: RW 5854 */ 5855 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1); 5856 5857 /* reg_ritr_ipv4_mc_fe 5858 * IPv4 Multicast Forwarding Enable. 5859 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 5860 * will be enabled. 5861 * Access: RW 5862 */ 5863 MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1); 5864 5865 /* reg_ritr_ipv6_mc_fe 5866 * IPv6 Multicast Forwarding Enable. 5867 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 5868 * will be enabled. 5869 * Access: RW 5870 */ 5871 MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1); 5872 5873 /* reg_ritr_lb_en 5874 * Loop-back filter enable for unicast packets. 5875 * If the flag is set then loop-back filter for unicast packets is 5876 * implemented on the RIF. Multicast packets are always subject to 5877 * loop-back filtering. 5878 * Access: RW 5879 */ 5880 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1); 5881 5882 /* reg_ritr_virtual_router 5883 * Virtual router ID associated with the router interface. 5884 * Access: RW 5885 */ 5886 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16); 5887 5888 /* reg_ritr_mtu 5889 * Router interface MTU. 5890 * Access: RW 5891 */ 5892 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16); 5893 5894 /* reg_ritr_if_swid 5895 * Switch partition ID. 5896 * Access: RW 5897 */ 5898 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8); 5899 5900 /* reg_ritr_if_mac 5901 * Router interface MAC address. 5902 * In Spectrum, all MAC addresses must have the same 38 MSBits. 5903 * Access: RW 5904 */ 5905 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6); 5906 5907 /* reg_ritr_if_vrrp_id_ipv6 5908 * VRRP ID for IPv6 5909 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 5910 * Access: RW 5911 */ 5912 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8); 5913 5914 /* reg_ritr_if_vrrp_id_ipv4 5915 * VRRP ID for IPv4 5916 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 5917 * Access: RW 5918 */ 5919 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8); 5920 5921 /* VLAN Interface */ 5922 5923 /* reg_ritr_vlan_if_vid 5924 * VLAN ID. 5925 * Access: RW 5926 */ 5927 MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12); 5928 5929 /* FID Interface */ 5930 5931 /* reg_ritr_fid_if_fid 5932 * Filtering ID. Used to connect a bridge to the router. Only FIDs from 5933 * the vFID range are supported. 5934 * Access: RW 5935 */ 5936 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16); 5937 5938 static inline void mlxsw_reg_ritr_fid_set(char *payload, 5939 enum mlxsw_reg_ritr_if_type rif_type, 5940 u16 fid) 5941 { 5942 if (rif_type == MLXSW_REG_RITR_FID_IF) 5943 mlxsw_reg_ritr_fid_if_fid_set(payload, fid); 5944 else 5945 mlxsw_reg_ritr_vlan_if_vid_set(payload, fid); 5946 } 5947 5948 /* Sub-port Interface */ 5949 5950 /* reg_ritr_sp_if_lag 5951 * LAG indication. When this bit is set the system_port field holds the 5952 * LAG identifier. 5953 * Access: RW 5954 */ 5955 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1); 5956 5957 /* reg_ritr_sp_system_port 5958 * Port unique indentifier. When lag bit is set, this field holds the 5959 * lag_id in bits 0:9. 5960 * Access: RW 5961 */ 5962 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16); 5963 5964 /* reg_ritr_sp_if_vid 5965 * VLAN ID. 5966 * Access: RW 5967 */ 5968 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12); 5969 5970 /* Loopback Interface */ 5971 5972 enum mlxsw_reg_ritr_loopback_protocol { 5973 /* IPinIP IPv4 underlay Unicast */ 5974 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4, 5975 /* IPinIP IPv6 underlay Unicast */ 5976 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6, 5977 /* IPinIP generic - used for Spectrum-2 underlay RIF */ 5978 MLXSW_REG_RITR_LOOPBACK_GENERIC, 5979 }; 5980 5981 /* reg_ritr_loopback_protocol 5982 * Access: RW 5983 */ 5984 MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4); 5985 5986 enum mlxsw_reg_ritr_loopback_ipip_type { 5987 /* Tunnel is IPinIP. */ 5988 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP, 5989 /* Tunnel is GRE, no key. */ 5990 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP, 5991 /* Tunnel is GRE, with a key. */ 5992 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP, 5993 }; 5994 5995 /* reg_ritr_loopback_ipip_type 5996 * Encapsulation type. 5997 * Access: RW 5998 */ 5999 MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4); 6000 6001 enum mlxsw_reg_ritr_loopback_ipip_options { 6002 /* The key is defined by gre_key. */ 6003 MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET, 6004 }; 6005 6006 /* reg_ritr_loopback_ipip_options 6007 * Access: RW 6008 */ 6009 MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4); 6010 6011 /* reg_ritr_loopback_ipip_uvr 6012 * Underlay Virtual Router ID. 6013 * Range is 0..cap_max_virtual_routers-1. 6014 * Reserved for Spectrum-2. 6015 * Access: RW 6016 */ 6017 MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16); 6018 6019 /* reg_ritr_loopback_ipip_underlay_rif 6020 * Underlay ingress router interface. 6021 * Reserved for Spectrum. 6022 * Access: RW 6023 */ 6024 MLXSW_ITEM32(reg, ritr, loopback_ipip_underlay_rif, 0x14, 0, 16); 6025 6026 /* reg_ritr_loopback_ipip_usip* 6027 * Encapsulation Underlay source IP. 6028 * Access: RW 6029 */ 6030 MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16); 6031 MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32); 6032 6033 /* reg_ritr_loopback_ipip_gre_key 6034 * GRE Key. 6035 * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP. 6036 * Access: RW 6037 */ 6038 MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32); 6039 6040 /* Shared between ingress/egress */ 6041 enum mlxsw_reg_ritr_counter_set_type { 6042 /* No Count. */ 6043 MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0, 6044 /* Basic. Used for router interfaces, counting the following: 6045 * - Error and Discard counters. 6046 * - Unicast, Multicast and Broadcast counters. Sharing the 6047 * same set of counters for the different type of traffic 6048 * (IPv4, IPv6 and mpls). 6049 */ 6050 MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9, 6051 }; 6052 6053 /* reg_ritr_ingress_counter_index 6054 * Counter Index for flow counter. 6055 * Access: RW 6056 */ 6057 MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24); 6058 6059 /* reg_ritr_ingress_counter_set_type 6060 * Igress Counter Set Type for router interface counter. 6061 * Access: RW 6062 */ 6063 MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8); 6064 6065 /* reg_ritr_egress_counter_index 6066 * Counter Index for flow counter. 6067 * Access: RW 6068 */ 6069 MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24); 6070 6071 /* reg_ritr_egress_counter_set_type 6072 * Egress Counter Set Type for router interface counter. 6073 * Access: RW 6074 */ 6075 MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8); 6076 6077 static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index, 6078 bool enable, bool egress) 6079 { 6080 enum mlxsw_reg_ritr_counter_set_type set_type; 6081 6082 if (enable) 6083 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC; 6084 else 6085 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT; 6086 mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type); 6087 6088 if (egress) 6089 mlxsw_reg_ritr_egress_counter_index_set(payload, index); 6090 else 6091 mlxsw_reg_ritr_ingress_counter_index_set(payload, index); 6092 } 6093 6094 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif) 6095 { 6096 MLXSW_REG_ZERO(ritr, payload); 6097 mlxsw_reg_ritr_rif_set(payload, rif); 6098 } 6099 6100 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag, 6101 u16 system_port, u16 vid) 6102 { 6103 mlxsw_reg_ritr_sp_if_lag_set(payload, lag); 6104 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port); 6105 mlxsw_reg_ritr_sp_if_vid_set(payload, vid); 6106 } 6107 6108 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable, 6109 enum mlxsw_reg_ritr_if_type type, 6110 u16 rif, u16 vr_id, u16 mtu) 6111 { 6112 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL; 6113 6114 MLXSW_REG_ZERO(ritr, payload); 6115 mlxsw_reg_ritr_enable_set(payload, enable); 6116 mlxsw_reg_ritr_ipv4_set(payload, 1); 6117 mlxsw_reg_ritr_ipv6_set(payload, 1); 6118 mlxsw_reg_ritr_ipv4_mc_set(payload, 1); 6119 mlxsw_reg_ritr_ipv6_mc_set(payload, 1); 6120 mlxsw_reg_ritr_type_set(payload, type); 6121 mlxsw_reg_ritr_op_set(payload, op); 6122 mlxsw_reg_ritr_rif_set(payload, rif); 6123 mlxsw_reg_ritr_ipv4_fe_set(payload, 1); 6124 mlxsw_reg_ritr_ipv6_fe_set(payload, 1); 6125 mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1); 6126 mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1); 6127 mlxsw_reg_ritr_lb_en_set(payload, 1); 6128 mlxsw_reg_ritr_virtual_router_set(payload, vr_id); 6129 mlxsw_reg_ritr_mtu_set(payload, mtu); 6130 } 6131 6132 static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac) 6133 { 6134 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac); 6135 } 6136 6137 static inline void 6138 mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload, 6139 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 6140 enum mlxsw_reg_ritr_loopback_ipip_options options, 6141 u16 uvr_id, u16 underlay_rif, u32 gre_key) 6142 { 6143 mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type); 6144 mlxsw_reg_ritr_loopback_ipip_options_set(payload, options); 6145 mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id); 6146 mlxsw_reg_ritr_loopback_ipip_underlay_rif_set(payload, underlay_rif); 6147 mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key); 6148 } 6149 6150 static inline void 6151 mlxsw_reg_ritr_loopback_ipip4_pack(char *payload, 6152 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 6153 enum mlxsw_reg_ritr_loopback_ipip_options options, 6154 u16 uvr_id, u16 underlay_rif, u32 usip, u32 gre_key) 6155 { 6156 mlxsw_reg_ritr_loopback_protocol_set(payload, 6157 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4); 6158 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options, 6159 uvr_id, underlay_rif, gre_key); 6160 mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip); 6161 } 6162 6163 /* RTAR - Router TCAM Allocation Register 6164 * -------------------------------------- 6165 * This register is used for allocation of regions in the TCAM table. 6166 */ 6167 #define MLXSW_REG_RTAR_ID 0x8004 6168 #define MLXSW_REG_RTAR_LEN 0x20 6169 6170 MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN); 6171 6172 enum mlxsw_reg_rtar_op { 6173 MLXSW_REG_RTAR_OP_ALLOCATE, 6174 MLXSW_REG_RTAR_OP_RESIZE, 6175 MLXSW_REG_RTAR_OP_DEALLOCATE, 6176 }; 6177 6178 /* reg_rtar_op 6179 * Access: WO 6180 */ 6181 MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4); 6182 6183 enum mlxsw_reg_rtar_key_type { 6184 MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1, 6185 MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3 6186 }; 6187 6188 /* reg_rtar_key_type 6189 * TCAM key type for the region. 6190 * Access: WO 6191 */ 6192 MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8); 6193 6194 /* reg_rtar_region_size 6195 * TCAM region size. When allocating/resizing this is the requested 6196 * size, the response is the actual size. 6197 * Note: Actual size may be larger than requested. 6198 * Reserved for op = Deallocate 6199 * Access: WO 6200 */ 6201 MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16); 6202 6203 static inline void mlxsw_reg_rtar_pack(char *payload, 6204 enum mlxsw_reg_rtar_op op, 6205 enum mlxsw_reg_rtar_key_type key_type, 6206 u16 region_size) 6207 { 6208 MLXSW_REG_ZERO(rtar, payload); 6209 mlxsw_reg_rtar_op_set(payload, op); 6210 mlxsw_reg_rtar_key_type_set(payload, key_type); 6211 mlxsw_reg_rtar_region_size_set(payload, region_size); 6212 } 6213 6214 /* RATR - Router Adjacency Table Register 6215 * -------------------------------------- 6216 * The RATR register is used to configure the Router Adjacency (next-hop) 6217 * Table. 6218 */ 6219 #define MLXSW_REG_RATR_ID 0x8008 6220 #define MLXSW_REG_RATR_LEN 0x2C 6221 6222 MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN); 6223 6224 enum mlxsw_reg_ratr_op { 6225 /* Read */ 6226 MLXSW_REG_RATR_OP_QUERY_READ = 0, 6227 /* Read and clear activity */ 6228 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2, 6229 /* Write Adjacency entry */ 6230 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1, 6231 /* Write Adjacency entry only if the activity is cleared. 6232 * The write may not succeed if the activity is set. There is not 6233 * direct feedback if the write has succeeded or not, however 6234 * the get will reveal the actual entry (SW can compare the get 6235 * response to the set command). 6236 */ 6237 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3, 6238 }; 6239 6240 /* reg_ratr_op 6241 * Note that Write operation may also be used for updating 6242 * counter_set_type and counter_index. In this case all other 6243 * fields must not be updated. 6244 * Access: OP 6245 */ 6246 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4); 6247 6248 /* reg_ratr_v 6249 * Valid bit. Indicates if the adjacency entry is valid. 6250 * Note: the device may need some time before reusing an invalidated 6251 * entry. During this time the entry can not be reused. It is 6252 * recommended to use another entry before reusing an invalidated 6253 * entry (e.g. software can put it at the end of the list for 6254 * reusing). Trying to access an invalidated entry not yet cleared 6255 * by the device results with failure indicating "Try Again" status. 6256 * When valid is '0' then egress_router_interface,trap_action, 6257 * adjacency_parameters and counters are reserved 6258 * Access: RW 6259 */ 6260 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1); 6261 6262 /* reg_ratr_a 6263 * Activity. Set for new entries. Set if a packet lookup has hit on 6264 * the specific entry. To clear the a bit, use "clear activity". 6265 * Access: RO 6266 */ 6267 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1); 6268 6269 enum mlxsw_reg_ratr_type { 6270 /* Ethernet */ 6271 MLXSW_REG_RATR_TYPE_ETHERNET, 6272 /* IPoIB Unicast without GRH. 6273 * Reserved for Spectrum. 6274 */ 6275 MLXSW_REG_RATR_TYPE_IPOIB_UC, 6276 /* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast 6277 * adjacency). 6278 * Reserved for Spectrum. 6279 */ 6280 MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH, 6281 /* IPoIB Multicast. 6282 * Reserved for Spectrum. 6283 */ 6284 MLXSW_REG_RATR_TYPE_IPOIB_MC, 6285 /* MPLS. 6286 * Reserved for SwitchX/-2. 6287 */ 6288 MLXSW_REG_RATR_TYPE_MPLS, 6289 /* IPinIP Encap. 6290 * Reserved for SwitchX/-2. 6291 */ 6292 MLXSW_REG_RATR_TYPE_IPIP, 6293 }; 6294 6295 /* reg_ratr_type 6296 * Adjacency entry type. 6297 * Access: RW 6298 */ 6299 MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4); 6300 6301 /* reg_ratr_adjacency_index_low 6302 * Bits 15:0 of index into the adjacency table. 6303 * For SwitchX and SwitchX-2, the adjacency table is linear and 6304 * used for adjacency entries only. 6305 * For Spectrum, the index is to the KVD linear. 6306 * Access: Index 6307 */ 6308 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16); 6309 6310 /* reg_ratr_egress_router_interface 6311 * Range is 0 .. cap_max_router_interfaces - 1 6312 * Access: RW 6313 */ 6314 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16); 6315 6316 enum mlxsw_reg_ratr_trap_action { 6317 MLXSW_REG_RATR_TRAP_ACTION_NOP, 6318 MLXSW_REG_RATR_TRAP_ACTION_TRAP, 6319 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU, 6320 MLXSW_REG_RATR_TRAP_ACTION_MIRROR, 6321 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS, 6322 }; 6323 6324 /* reg_ratr_trap_action 6325 * see mlxsw_reg_ratr_trap_action 6326 * Access: RW 6327 */ 6328 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4); 6329 6330 /* reg_ratr_adjacency_index_high 6331 * Bits 23:16 of the adjacency_index. 6332 * Access: Index 6333 */ 6334 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8); 6335 6336 enum mlxsw_reg_ratr_trap_id { 6337 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0, 6338 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1, 6339 }; 6340 6341 /* reg_ratr_trap_id 6342 * Trap ID to be reported to CPU. 6343 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 6344 * For trap_action of NOP, MIRROR and DISCARD_ERROR 6345 * Access: RW 6346 */ 6347 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8); 6348 6349 /* reg_ratr_eth_destination_mac 6350 * MAC address of the destination next-hop. 6351 * Access: RW 6352 */ 6353 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6); 6354 6355 enum mlxsw_reg_ratr_ipip_type { 6356 /* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */ 6357 MLXSW_REG_RATR_IPIP_TYPE_IPV4, 6358 /* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */ 6359 MLXSW_REG_RATR_IPIP_TYPE_IPV6, 6360 }; 6361 6362 /* reg_ratr_ipip_type 6363 * Underlay destination ip type. 6364 * Note: the type field must match the protocol of the router interface. 6365 * Access: RW 6366 */ 6367 MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4); 6368 6369 /* reg_ratr_ipip_ipv4_udip 6370 * Underlay ipv4 dip. 6371 * Reserved when ipip_type is IPv6. 6372 * Access: RW 6373 */ 6374 MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32); 6375 6376 /* reg_ratr_ipip_ipv6_ptr 6377 * Pointer to IPv6 underlay destination ip address. 6378 * For Spectrum: Pointer to KVD linear space. 6379 * Access: RW 6380 */ 6381 MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24); 6382 6383 enum mlxsw_reg_flow_counter_set_type { 6384 /* No count */ 6385 MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00, 6386 /* Count packets and bytes */ 6387 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03, 6388 /* Count only packets */ 6389 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05, 6390 }; 6391 6392 /* reg_ratr_counter_set_type 6393 * Counter set type for flow counters 6394 * Access: RW 6395 */ 6396 MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8); 6397 6398 /* reg_ratr_counter_index 6399 * Counter index for flow counters 6400 * Access: RW 6401 */ 6402 MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24); 6403 6404 static inline void 6405 mlxsw_reg_ratr_pack(char *payload, 6406 enum mlxsw_reg_ratr_op op, bool valid, 6407 enum mlxsw_reg_ratr_type type, 6408 u32 adjacency_index, u16 egress_rif) 6409 { 6410 MLXSW_REG_ZERO(ratr, payload); 6411 mlxsw_reg_ratr_op_set(payload, op); 6412 mlxsw_reg_ratr_v_set(payload, valid); 6413 mlxsw_reg_ratr_type_set(payload, type); 6414 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index); 6415 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16); 6416 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif); 6417 } 6418 6419 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload, 6420 const char *dest_mac) 6421 { 6422 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac); 6423 } 6424 6425 static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip) 6426 { 6427 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4); 6428 mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip); 6429 } 6430 6431 static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index, 6432 bool counter_enable) 6433 { 6434 enum mlxsw_reg_flow_counter_set_type set_type; 6435 6436 if (counter_enable) 6437 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES; 6438 else 6439 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT; 6440 6441 mlxsw_reg_ratr_counter_index_set(payload, counter_index); 6442 mlxsw_reg_ratr_counter_set_type_set(payload, set_type); 6443 } 6444 6445 /* RDPM - Router DSCP to Priority Mapping 6446 * -------------------------------------- 6447 * Controls the mapping from DSCP field to switch priority on routed packets 6448 */ 6449 #define MLXSW_REG_RDPM_ID 0x8009 6450 #define MLXSW_REG_RDPM_BASE_LEN 0x00 6451 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01 6452 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64 6453 #define MLXSW_REG_RDPM_LEN 0x40 6454 #define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \ 6455 MLXSW_REG_RDPM_LEN - \ 6456 MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN) 6457 6458 MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN); 6459 6460 /* reg_dscp_entry_e 6461 * Enable update of the specific entry 6462 * Access: Index 6463 */ 6464 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1, 6465 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 6466 6467 /* reg_dscp_entry_prio 6468 * Switch Priority 6469 * Access: RW 6470 */ 6471 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4, 6472 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 6473 6474 static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index, 6475 u8 prio) 6476 { 6477 mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1); 6478 mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio); 6479 } 6480 6481 /* RICNT - Router Interface Counter Register 6482 * ----------------------------------------- 6483 * The RICNT register retrieves per port performance counters 6484 */ 6485 #define MLXSW_REG_RICNT_ID 0x800B 6486 #define MLXSW_REG_RICNT_LEN 0x100 6487 6488 MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN); 6489 6490 /* reg_ricnt_counter_index 6491 * Counter index 6492 * Access: RW 6493 */ 6494 MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24); 6495 6496 enum mlxsw_reg_ricnt_counter_set_type { 6497 /* No Count. */ 6498 MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00, 6499 /* Basic. Used for router interfaces, counting the following: 6500 * - Error and Discard counters. 6501 * - Unicast, Multicast and Broadcast counters. Sharing the 6502 * same set of counters for the different type of traffic 6503 * (IPv4, IPv6 and mpls). 6504 */ 6505 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09, 6506 }; 6507 6508 /* reg_ricnt_counter_set_type 6509 * Counter Set Type for router interface counter 6510 * Access: RW 6511 */ 6512 MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8); 6513 6514 enum mlxsw_reg_ricnt_opcode { 6515 /* Nop. Supported only for read access*/ 6516 MLXSW_REG_RICNT_OPCODE_NOP = 0x00, 6517 /* Clear. Setting the clr bit will reset the counter value for 6518 * all counters of the specified Router Interface. 6519 */ 6520 MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08, 6521 }; 6522 6523 /* reg_ricnt_opcode 6524 * Opcode 6525 * Access: RW 6526 */ 6527 MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4); 6528 6529 /* reg_ricnt_good_unicast_packets 6530 * good unicast packets. 6531 * Access: RW 6532 */ 6533 MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64); 6534 6535 /* reg_ricnt_good_multicast_packets 6536 * good multicast packets. 6537 * Access: RW 6538 */ 6539 MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64); 6540 6541 /* reg_ricnt_good_broadcast_packets 6542 * good broadcast packets 6543 * Access: RW 6544 */ 6545 MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64); 6546 6547 /* reg_ricnt_good_unicast_bytes 6548 * A count of L3 data and padding octets not including L2 headers 6549 * for good unicast frames. 6550 * Access: RW 6551 */ 6552 MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64); 6553 6554 /* reg_ricnt_good_multicast_bytes 6555 * A count of L3 data and padding octets not including L2 headers 6556 * for good multicast frames. 6557 * Access: RW 6558 */ 6559 MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64); 6560 6561 /* reg_ritr_good_broadcast_bytes 6562 * A count of L3 data and padding octets not including L2 headers 6563 * for good broadcast frames. 6564 * Access: RW 6565 */ 6566 MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64); 6567 6568 /* reg_ricnt_error_packets 6569 * A count of errored frames that do not pass the router checks. 6570 * Access: RW 6571 */ 6572 MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64); 6573 6574 /* reg_ricnt_discrad_packets 6575 * A count of non-errored frames that do not pass the router checks. 6576 * Access: RW 6577 */ 6578 MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64); 6579 6580 /* reg_ricnt_error_bytes 6581 * A count of L3 data and padding octets not including L2 headers 6582 * for errored frames. 6583 * Access: RW 6584 */ 6585 MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64); 6586 6587 /* reg_ricnt_discard_bytes 6588 * A count of L3 data and padding octets not including L2 headers 6589 * for non-errored frames that do not pass the router checks. 6590 * Access: RW 6591 */ 6592 MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64); 6593 6594 static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index, 6595 enum mlxsw_reg_ricnt_opcode op) 6596 { 6597 MLXSW_REG_ZERO(ricnt, payload); 6598 mlxsw_reg_ricnt_op_set(payload, op); 6599 mlxsw_reg_ricnt_counter_index_set(payload, index); 6600 mlxsw_reg_ricnt_counter_set_type_set(payload, 6601 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC); 6602 } 6603 6604 /* RRCR - Router Rules Copy Register Layout 6605 * ---------------------------------------- 6606 * This register is used for moving and copying route entry rules. 6607 */ 6608 #define MLXSW_REG_RRCR_ID 0x800F 6609 #define MLXSW_REG_RRCR_LEN 0x24 6610 6611 MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN); 6612 6613 enum mlxsw_reg_rrcr_op { 6614 /* Move rules */ 6615 MLXSW_REG_RRCR_OP_MOVE, 6616 /* Copy rules */ 6617 MLXSW_REG_RRCR_OP_COPY, 6618 }; 6619 6620 /* reg_rrcr_op 6621 * Access: WO 6622 */ 6623 MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4); 6624 6625 /* reg_rrcr_offset 6626 * Offset within the region from which to copy/move. 6627 * Access: Index 6628 */ 6629 MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16); 6630 6631 /* reg_rrcr_size 6632 * The number of rules to copy/move. 6633 * Access: WO 6634 */ 6635 MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16); 6636 6637 /* reg_rrcr_table_id 6638 * Identifier of the table on which to perform the operation. Encoding is the 6639 * same as in RTAR.key_type 6640 * Access: Index 6641 */ 6642 MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4); 6643 6644 /* reg_rrcr_dest_offset 6645 * Offset within the region to which to copy/move 6646 * Access: Index 6647 */ 6648 MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16); 6649 6650 static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op, 6651 u16 offset, u16 size, 6652 enum mlxsw_reg_rtar_key_type table_id, 6653 u16 dest_offset) 6654 { 6655 MLXSW_REG_ZERO(rrcr, payload); 6656 mlxsw_reg_rrcr_op_set(payload, op); 6657 mlxsw_reg_rrcr_offset_set(payload, offset); 6658 mlxsw_reg_rrcr_size_set(payload, size); 6659 mlxsw_reg_rrcr_table_id_set(payload, table_id); 6660 mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset); 6661 } 6662 6663 /* RALTA - Router Algorithmic LPM Tree Allocation Register 6664 * ------------------------------------------------------- 6665 * RALTA is used to allocate the LPM trees of the SHSPM method. 6666 */ 6667 #define MLXSW_REG_RALTA_ID 0x8010 6668 #define MLXSW_REG_RALTA_LEN 0x04 6669 6670 MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN); 6671 6672 /* reg_ralta_op 6673 * opcode (valid for Write, must be 0 on Read) 6674 * 0 - allocate a tree 6675 * 1 - deallocate a tree 6676 * Access: OP 6677 */ 6678 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2); 6679 6680 enum mlxsw_reg_ralxx_protocol { 6681 MLXSW_REG_RALXX_PROTOCOL_IPV4, 6682 MLXSW_REG_RALXX_PROTOCOL_IPV6, 6683 }; 6684 6685 /* reg_ralta_protocol 6686 * Protocol. 6687 * Deallocation opcode: Reserved. 6688 * Access: RW 6689 */ 6690 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4); 6691 6692 /* reg_ralta_tree_id 6693 * An identifier (numbered from 1..cap_shspm_max_trees-1) representing 6694 * the tree identifier (managed by software). 6695 * Note that tree_id 0 is allocated for a default-route tree. 6696 * Access: Index 6697 */ 6698 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8); 6699 6700 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc, 6701 enum mlxsw_reg_ralxx_protocol protocol, 6702 u8 tree_id) 6703 { 6704 MLXSW_REG_ZERO(ralta, payload); 6705 mlxsw_reg_ralta_op_set(payload, !alloc); 6706 mlxsw_reg_ralta_protocol_set(payload, protocol); 6707 mlxsw_reg_ralta_tree_id_set(payload, tree_id); 6708 } 6709 6710 /* RALST - Router Algorithmic LPM Structure Tree Register 6711 * ------------------------------------------------------ 6712 * RALST is used to set and query the structure of an LPM tree. 6713 * The structure of the tree must be sorted as a sorted binary tree, while 6714 * each node is a bin that is tagged as the length of the prefixes the lookup 6715 * will refer to. Therefore, bin X refers to a set of entries with prefixes 6716 * of X bits to match with the destination address. The bin 0 indicates 6717 * the default action, when there is no match of any prefix. 6718 */ 6719 #define MLXSW_REG_RALST_ID 0x8011 6720 #define MLXSW_REG_RALST_LEN 0x104 6721 6722 MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN); 6723 6724 /* reg_ralst_root_bin 6725 * The bin number of the root bin. 6726 * 0<root_bin=<(length of IP address) 6727 * For a default-route tree configure 0xff 6728 * Access: RW 6729 */ 6730 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8); 6731 6732 /* reg_ralst_tree_id 6733 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 6734 * Access: Index 6735 */ 6736 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8); 6737 6738 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff 6739 #define MLXSW_REG_RALST_BIN_OFFSET 0x04 6740 #define MLXSW_REG_RALST_BIN_COUNT 128 6741 6742 /* reg_ralst_left_child_bin 6743 * Holding the children of the bin according to the stored tree's structure. 6744 * For trees composed of less than 4 blocks, the bins in excess are reserved. 6745 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 6746 * Access: RW 6747 */ 6748 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false); 6749 6750 /* reg_ralst_right_child_bin 6751 * Holding the children of the bin according to the stored tree's structure. 6752 * For trees composed of less than 4 blocks, the bins in excess are reserved. 6753 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 6754 * Access: RW 6755 */ 6756 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00, 6757 false); 6758 6759 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id) 6760 { 6761 MLXSW_REG_ZERO(ralst, payload); 6762 6763 /* Initialize all bins to have no left or right child */ 6764 memset(payload + MLXSW_REG_RALST_BIN_OFFSET, 6765 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2); 6766 6767 mlxsw_reg_ralst_root_bin_set(payload, root_bin); 6768 mlxsw_reg_ralst_tree_id_set(payload, tree_id); 6769 } 6770 6771 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number, 6772 u8 left_child_bin, 6773 u8 right_child_bin) 6774 { 6775 int bin_index = bin_number - 1; 6776 6777 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin); 6778 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index, 6779 right_child_bin); 6780 } 6781 6782 /* RALTB - Router Algorithmic LPM Tree Binding Register 6783 * ---------------------------------------------------- 6784 * RALTB is used to bind virtual router and protocol to an allocated LPM tree. 6785 */ 6786 #define MLXSW_REG_RALTB_ID 0x8012 6787 #define MLXSW_REG_RALTB_LEN 0x04 6788 6789 MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN); 6790 6791 /* reg_raltb_virtual_router 6792 * Virtual Router ID 6793 * Range is 0..cap_max_virtual_routers-1 6794 * Access: Index 6795 */ 6796 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16); 6797 6798 /* reg_raltb_protocol 6799 * Protocol. 6800 * Access: Index 6801 */ 6802 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4); 6803 6804 /* reg_raltb_tree_id 6805 * Tree to be used for the {virtual_router, protocol} 6806 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 6807 * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0. 6808 * Access: RW 6809 */ 6810 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8); 6811 6812 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router, 6813 enum mlxsw_reg_ralxx_protocol protocol, 6814 u8 tree_id) 6815 { 6816 MLXSW_REG_ZERO(raltb, payload); 6817 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router); 6818 mlxsw_reg_raltb_protocol_set(payload, protocol); 6819 mlxsw_reg_raltb_tree_id_set(payload, tree_id); 6820 } 6821 6822 /* RALUE - Router Algorithmic LPM Unicast Entry Register 6823 * ----------------------------------------------------- 6824 * RALUE is used to configure and query LPM entries that serve 6825 * the Unicast protocols. 6826 */ 6827 #define MLXSW_REG_RALUE_ID 0x8013 6828 #define MLXSW_REG_RALUE_LEN 0x38 6829 6830 MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN); 6831 6832 /* reg_ralue_protocol 6833 * Protocol. 6834 * Access: Index 6835 */ 6836 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4); 6837 6838 enum mlxsw_reg_ralue_op { 6839 /* Read operation. If entry doesn't exist, the operation fails. */ 6840 MLXSW_REG_RALUE_OP_QUERY_READ = 0, 6841 /* Clear on read operation. Used to read entry and 6842 * clear Activity bit. 6843 */ 6844 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1, 6845 /* Write operation. Used to write a new entry to the table. All RW 6846 * fields are written for new entry. Activity bit is set 6847 * for new entries. 6848 */ 6849 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0, 6850 /* Update operation. Used to update an existing route entry and 6851 * only update the RW fields that are detailed in the field 6852 * op_u_mask. If entry doesn't exist, the operation fails. 6853 */ 6854 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1, 6855 /* Clear activity. The Activity bit (the field a) is cleared 6856 * for the entry. 6857 */ 6858 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2, 6859 /* Delete operation. Used to delete an existing entry. If entry 6860 * doesn't exist, the operation fails. 6861 */ 6862 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3, 6863 }; 6864 6865 /* reg_ralue_op 6866 * Operation. 6867 * Access: OP 6868 */ 6869 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3); 6870 6871 /* reg_ralue_a 6872 * Activity. Set for new entries. Set if a packet lookup has hit on the 6873 * specific entry, only if the entry is a route. To clear the a bit, use 6874 * "clear activity" op. 6875 * Enabled by activity_dis in RGCR 6876 * Access: RO 6877 */ 6878 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1); 6879 6880 /* reg_ralue_virtual_router 6881 * Virtual Router ID 6882 * Range is 0..cap_max_virtual_routers-1 6883 * Access: Index 6884 */ 6885 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16); 6886 6887 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0) 6888 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1) 6889 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2) 6890 6891 /* reg_ralue_op_u_mask 6892 * opcode update mask. 6893 * On read operation, this field is reserved. 6894 * This field is valid for update opcode, otherwise - reserved. 6895 * This field is a bitmask of the fields that should be updated. 6896 * Access: WO 6897 */ 6898 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3); 6899 6900 /* reg_ralue_prefix_len 6901 * Number of bits in the prefix of the LPM route. 6902 * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes 6903 * two entries in the physical HW table. 6904 * Access: Index 6905 */ 6906 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8); 6907 6908 /* reg_ralue_dip* 6909 * The prefix of the route or of the marker that the object of the LPM 6910 * is compared with. The most significant bits of the dip are the prefix. 6911 * The least significant bits must be '0' if the prefix_len is smaller 6912 * than 128 for IPv6 or smaller than 32 for IPv4. 6913 * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved. 6914 * Access: Index 6915 */ 6916 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32); 6917 MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16); 6918 6919 enum mlxsw_reg_ralue_entry_type { 6920 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1, 6921 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2, 6922 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3, 6923 }; 6924 6925 /* reg_ralue_entry_type 6926 * Entry type. 6927 * Note - for Marker entries, the action_type and action fields are reserved. 6928 * Access: RW 6929 */ 6930 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2); 6931 6932 /* reg_ralue_bmp_len 6933 * The best match prefix length in the case that there is no match for 6934 * longer prefixes. 6935 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len 6936 * Note for any update operation with entry_type modification this 6937 * field must be set. 6938 * Access: RW 6939 */ 6940 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8); 6941 6942 enum mlxsw_reg_ralue_action_type { 6943 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE, 6944 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL, 6945 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME, 6946 }; 6947 6948 /* reg_ralue_action_type 6949 * Action Type 6950 * Indicates how the IP address is connected. 6951 * It can be connected to a local subnet through local_erif or can be 6952 * on a remote subnet connected through a next-hop router, 6953 * or transmitted to the CPU. 6954 * Reserved when entry_type = MARKER_ENTRY 6955 * Access: RW 6956 */ 6957 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2); 6958 6959 enum mlxsw_reg_ralue_trap_action { 6960 MLXSW_REG_RALUE_TRAP_ACTION_NOP, 6961 MLXSW_REG_RALUE_TRAP_ACTION_TRAP, 6962 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU, 6963 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR, 6964 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR, 6965 }; 6966 6967 /* reg_ralue_trap_action 6968 * Trap action. 6969 * For IP2ME action, only NOP and MIRROR are possible. 6970 * Access: RW 6971 */ 6972 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4); 6973 6974 /* reg_ralue_trap_id 6975 * Trap ID to be reported to CPU. 6976 * Trap ID is RTR_INGRESS0 or RTR_INGRESS1. 6977 * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved. 6978 * Access: RW 6979 */ 6980 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9); 6981 6982 /* reg_ralue_adjacency_index 6983 * Points to the first entry of the group-based ECMP. 6984 * Only relevant in case of REMOTE action. 6985 * Access: RW 6986 */ 6987 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24); 6988 6989 /* reg_ralue_ecmp_size 6990 * Amount of sequential entries starting 6991 * from the adjacency_index (the number of ECMPs). 6992 * The valid range is 1-64, 512, 1024, 2048 and 4096. 6993 * Reserved when trap_action is TRAP or DISCARD_ERROR. 6994 * Only relevant in case of REMOTE action. 6995 * Access: RW 6996 */ 6997 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13); 6998 6999 /* reg_ralue_local_erif 7000 * Egress Router Interface. 7001 * Only relevant in case of LOCAL action. 7002 * Access: RW 7003 */ 7004 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16); 7005 7006 /* reg_ralue_ip2me_v 7007 * Valid bit for the tunnel_ptr field. 7008 * If valid = 0 then trap to CPU as IP2ME trap ID. 7009 * If valid = 1 and the packet format allows NVE or IPinIP tunnel 7010 * decapsulation then tunnel decapsulation is done. 7011 * If valid = 1 and packet format does not allow NVE or IPinIP tunnel 7012 * decapsulation then trap as IP2ME trap ID. 7013 * Only relevant in case of IP2ME action. 7014 * Access: RW 7015 */ 7016 MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1); 7017 7018 /* reg_ralue_ip2me_tunnel_ptr 7019 * Tunnel Pointer for NVE or IPinIP tunnel decapsulation. 7020 * For Spectrum, pointer to KVD Linear. 7021 * Only relevant in case of IP2ME action. 7022 * Access: RW 7023 */ 7024 MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24); 7025 7026 static inline void mlxsw_reg_ralue_pack(char *payload, 7027 enum mlxsw_reg_ralxx_protocol protocol, 7028 enum mlxsw_reg_ralue_op op, 7029 u16 virtual_router, u8 prefix_len) 7030 { 7031 MLXSW_REG_ZERO(ralue, payload); 7032 mlxsw_reg_ralue_protocol_set(payload, protocol); 7033 mlxsw_reg_ralue_op_set(payload, op); 7034 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router); 7035 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len); 7036 mlxsw_reg_ralue_entry_type_set(payload, 7037 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY); 7038 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len); 7039 } 7040 7041 static inline void mlxsw_reg_ralue_pack4(char *payload, 7042 enum mlxsw_reg_ralxx_protocol protocol, 7043 enum mlxsw_reg_ralue_op op, 7044 u16 virtual_router, u8 prefix_len, 7045 u32 dip) 7046 { 7047 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 7048 mlxsw_reg_ralue_dip4_set(payload, dip); 7049 } 7050 7051 static inline void mlxsw_reg_ralue_pack6(char *payload, 7052 enum mlxsw_reg_ralxx_protocol protocol, 7053 enum mlxsw_reg_ralue_op op, 7054 u16 virtual_router, u8 prefix_len, 7055 const void *dip) 7056 { 7057 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 7058 mlxsw_reg_ralue_dip6_memcpy_to(payload, dip); 7059 } 7060 7061 static inline void 7062 mlxsw_reg_ralue_act_remote_pack(char *payload, 7063 enum mlxsw_reg_ralue_trap_action trap_action, 7064 u16 trap_id, u32 adjacency_index, u16 ecmp_size) 7065 { 7066 mlxsw_reg_ralue_action_type_set(payload, 7067 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE); 7068 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 7069 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 7070 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index); 7071 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size); 7072 } 7073 7074 static inline void 7075 mlxsw_reg_ralue_act_local_pack(char *payload, 7076 enum mlxsw_reg_ralue_trap_action trap_action, 7077 u16 trap_id, u16 local_erif) 7078 { 7079 mlxsw_reg_ralue_action_type_set(payload, 7080 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL); 7081 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 7082 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 7083 mlxsw_reg_ralue_local_erif_set(payload, local_erif); 7084 } 7085 7086 static inline void 7087 mlxsw_reg_ralue_act_ip2me_pack(char *payload) 7088 { 7089 mlxsw_reg_ralue_action_type_set(payload, 7090 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 7091 } 7092 7093 static inline void 7094 mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr) 7095 { 7096 mlxsw_reg_ralue_action_type_set(payload, 7097 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 7098 mlxsw_reg_ralue_ip2me_v_set(payload, 1); 7099 mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr); 7100 } 7101 7102 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register 7103 * ---------------------------------------------------------- 7104 * The RAUHT register is used to configure and query the Unicast Host table in 7105 * devices that implement the Algorithmic LPM. 7106 */ 7107 #define MLXSW_REG_RAUHT_ID 0x8014 7108 #define MLXSW_REG_RAUHT_LEN 0x74 7109 7110 MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN); 7111 7112 enum mlxsw_reg_rauht_type { 7113 MLXSW_REG_RAUHT_TYPE_IPV4, 7114 MLXSW_REG_RAUHT_TYPE_IPV6, 7115 }; 7116 7117 /* reg_rauht_type 7118 * Access: Index 7119 */ 7120 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2); 7121 7122 enum mlxsw_reg_rauht_op { 7123 MLXSW_REG_RAUHT_OP_QUERY_READ = 0, 7124 /* Read operation */ 7125 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1, 7126 /* Clear on read operation. Used to read entry and clear 7127 * activity bit. 7128 */ 7129 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0, 7130 /* Add. Used to write a new entry to the table. All R/W fields are 7131 * relevant for new entry. Activity bit is set for new entries. 7132 */ 7133 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1, 7134 /* Update action. Used to update an existing route entry and 7135 * only update the following fields: 7136 * trap_action, trap_id, mac, counter_set_type, counter_index 7137 */ 7138 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2, 7139 /* Clear activity. A bit is cleared for the entry. */ 7140 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3, 7141 /* Delete entry */ 7142 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4, 7143 /* Delete all host entries on a RIF. In this command, dip 7144 * field is reserved. 7145 */ 7146 }; 7147 7148 /* reg_rauht_op 7149 * Access: OP 7150 */ 7151 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3); 7152 7153 /* reg_rauht_a 7154 * Activity. Set for new entries. Set if a packet lookup has hit on 7155 * the specific entry. 7156 * To clear the a bit, use "clear activity" op. 7157 * Enabled by activity_dis in RGCR 7158 * Access: RO 7159 */ 7160 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1); 7161 7162 /* reg_rauht_rif 7163 * Router Interface 7164 * Access: Index 7165 */ 7166 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16); 7167 7168 /* reg_rauht_dip* 7169 * Destination address. 7170 * Access: Index 7171 */ 7172 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32); 7173 MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16); 7174 7175 enum mlxsw_reg_rauht_trap_action { 7176 MLXSW_REG_RAUHT_TRAP_ACTION_NOP, 7177 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP, 7178 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU, 7179 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR, 7180 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS, 7181 }; 7182 7183 /* reg_rauht_trap_action 7184 * Access: RW 7185 */ 7186 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4); 7187 7188 enum mlxsw_reg_rauht_trap_id { 7189 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0, 7190 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1, 7191 }; 7192 7193 /* reg_rauht_trap_id 7194 * Trap ID to be reported to CPU. 7195 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 7196 * For trap_action of NOP, MIRROR and DISCARD_ERROR, 7197 * trap_id is reserved. 7198 * Access: RW 7199 */ 7200 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9); 7201 7202 /* reg_rauht_counter_set_type 7203 * Counter set type for flow counters 7204 * Access: RW 7205 */ 7206 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8); 7207 7208 /* reg_rauht_counter_index 7209 * Counter index for flow counters 7210 * Access: RW 7211 */ 7212 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24); 7213 7214 /* reg_rauht_mac 7215 * MAC address. 7216 * Access: RW 7217 */ 7218 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6); 7219 7220 static inline void mlxsw_reg_rauht_pack(char *payload, 7221 enum mlxsw_reg_rauht_op op, u16 rif, 7222 const char *mac) 7223 { 7224 MLXSW_REG_ZERO(rauht, payload); 7225 mlxsw_reg_rauht_op_set(payload, op); 7226 mlxsw_reg_rauht_rif_set(payload, rif); 7227 mlxsw_reg_rauht_mac_memcpy_to(payload, mac); 7228 } 7229 7230 static inline void mlxsw_reg_rauht_pack4(char *payload, 7231 enum mlxsw_reg_rauht_op op, u16 rif, 7232 const char *mac, u32 dip) 7233 { 7234 mlxsw_reg_rauht_pack(payload, op, rif, mac); 7235 mlxsw_reg_rauht_dip4_set(payload, dip); 7236 } 7237 7238 static inline void mlxsw_reg_rauht_pack6(char *payload, 7239 enum mlxsw_reg_rauht_op op, u16 rif, 7240 const char *mac, const char *dip) 7241 { 7242 mlxsw_reg_rauht_pack(payload, op, rif, mac); 7243 mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6); 7244 mlxsw_reg_rauht_dip6_memcpy_to(payload, dip); 7245 } 7246 7247 static inline void mlxsw_reg_rauht_pack_counter(char *payload, 7248 u64 counter_index) 7249 { 7250 mlxsw_reg_rauht_counter_index_set(payload, counter_index); 7251 mlxsw_reg_rauht_counter_set_type_set(payload, 7252 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 7253 } 7254 7255 /* RALEU - Router Algorithmic LPM ECMP Update Register 7256 * --------------------------------------------------- 7257 * The register enables updating the ECMP section in the action for multiple 7258 * LPM Unicast entries in a single operation. The update is executed to 7259 * all entries of a {virtual router, protocol} tuple using the same ECMP group. 7260 */ 7261 #define MLXSW_REG_RALEU_ID 0x8015 7262 #define MLXSW_REG_RALEU_LEN 0x28 7263 7264 MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN); 7265 7266 /* reg_raleu_protocol 7267 * Protocol. 7268 * Access: Index 7269 */ 7270 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4); 7271 7272 /* reg_raleu_virtual_router 7273 * Virtual Router ID 7274 * Range is 0..cap_max_virtual_routers-1 7275 * Access: Index 7276 */ 7277 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16); 7278 7279 /* reg_raleu_adjacency_index 7280 * Adjacency Index used for matching on the existing entries. 7281 * Access: Index 7282 */ 7283 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24); 7284 7285 /* reg_raleu_ecmp_size 7286 * ECMP Size used for matching on the existing entries. 7287 * Access: Index 7288 */ 7289 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13); 7290 7291 /* reg_raleu_new_adjacency_index 7292 * New Adjacency Index. 7293 * Access: WO 7294 */ 7295 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24); 7296 7297 /* reg_raleu_new_ecmp_size 7298 * New ECMP Size. 7299 * Access: WO 7300 */ 7301 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13); 7302 7303 static inline void mlxsw_reg_raleu_pack(char *payload, 7304 enum mlxsw_reg_ralxx_protocol protocol, 7305 u16 virtual_router, 7306 u32 adjacency_index, u16 ecmp_size, 7307 u32 new_adjacency_index, 7308 u16 new_ecmp_size) 7309 { 7310 MLXSW_REG_ZERO(raleu, payload); 7311 mlxsw_reg_raleu_protocol_set(payload, protocol); 7312 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router); 7313 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index); 7314 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size); 7315 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index); 7316 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size); 7317 } 7318 7319 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register 7320 * ---------------------------------------------------------------- 7321 * The RAUHTD register allows dumping entries from the Router Unicast Host 7322 * Table. For a given session an entry is dumped no more than one time. The 7323 * first RAUHTD access after reset is a new session. A session ends when the 7324 * num_rec response is smaller than num_rec request or for IPv4 when the 7325 * num_entries is smaller than 4. The clear activity affect the current session 7326 * or the last session if a new session has not started. 7327 */ 7328 #define MLXSW_REG_RAUHTD_ID 0x8018 7329 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20 7330 #define MLXSW_REG_RAUHTD_REC_LEN 0x20 7331 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32 7332 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \ 7333 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN) 7334 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4 7335 7336 MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN); 7337 7338 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0) 7339 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3) 7340 7341 /* reg_rauhtd_filter_fields 7342 * if a bit is '0' then the relevant field is ignored and dump is done 7343 * regardless of the field value 7344 * Bit0 - filter by activity: entry_a 7345 * Bit3 - filter by entry rip: entry_rif 7346 * Access: Index 7347 */ 7348 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8); 7349 7350 enum mlxsw_reg_rauhtd_op { 7351 MLXSW_REG_RAUHTD_OP_DUMP, 7352 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR, 7353 }; 7354 7355 /* reg_rauhtd_op 7356 * Access: OP 7357 */ 7358 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2); 7359 7360 /* reg_rauhtd_num_rec 7361 * At request: number of records requested 7362 * At response: number of records dumped 7363 * For IPv4, each record has 4 entries at request and up to 4 entries 7364 * at response 7365 * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM 7366 * Access: Index 7367 */ 7368 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8); 7369 7370 /* reg_rauhtd_entry_a 7371 * Dump only if activity has value of entry_a 7372 * Reserved if filter_fields bit0 is '0' 7373 * Access: Index 7374 */ 7375 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1); 7376 7377 enum mlxsw_reg_rauhtd_type { 7378 MLXSW_REG_RAUHTD_TYPE_IPV4, 7379 MLXSW_REG_RAUHTD_TYPE_IPV6, 7380 }; 7381 7382 /* reg_rauhtd_type 7383 * Dump only if record type is: 7384 * 0 - IPv4 7385 * 1 - IPv6 7386 * Access: Index 7387 */ 7388 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4); 7389 7390 /* reg_rauhtd_entry_rif 7391 * Dump only if RIF has value of entry_rif 7392 * Reserved if filter_fields bit3 is '0' 7393 * Access: Index 7394 */ 7395 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16); 7396 7397 static inline void mlxsw_reg_rauhtd_pack(char *payload, 7398 enum mlxsw_reg_rauhtd_type type) 7399 { 7400 MLXSW_REG_ZERO(rauhtd, payload); 7401 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A); 7402 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR); 7403 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM); 7404 mlxsw_reg_rauhtd_entry_a_set(payload, 1); 7405 mlxsw_reg_rauhtd_type_set(payload, type); 7406 } 7407 7408 /* reg_rauhtd_ipv4_rec_num_entries 7409 * Number of valid entries in this record: 7410 * 0 - 1 valid entry 7411 * 1 - 2 valid entries 7412 * 2 - 3 valid entries 7413 * 3 - 4 valid entries 7414 * Access: RO 7415 */ 7416 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries, 7417 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2, 7418 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 7419 7420 /* reg_rauhtd_rec_type 7421 * Record type. 7422 * 0 - IPv4 7423 * 1 - IPv6 7424 * Access: RO 7425 */ 7426 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2, 7427 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 7428 7429 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8 7430 7431 /* reg_rauhtd_ipv4_ent_a 7432 * Activity. Set for new entries. Set if a packet lookup has hit on the 7433 * specific entry. 7434 * Access: RO 7435 */ 7436 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 7437 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 7438 7439 /* reg_rauhtd_ipv4_ent_rif 7440 * Router interface. 7441 * Access: RO 7442 */ 7443 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 7444 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 7445 7446 /* reg_rauhtd_ipv4_ent_dip 7447 * Destination IPv4 address. 7448 * Access: RO 7449 */ 7450 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0, 7451 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false); 7452 7453 #define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20 7454 7455 /* reg_rauhtd_ipv6_ent_a 7456 * Activity. Set for new entries. Set if a packet lookup has hit on the 7457 * specific entry. 7458 * Access: RO 7459 */ 7460 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 7461 MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 7462 7463 /* reg_rauhtd_ipv6_ent_rif 7464 * Router interface. 7465 * Access: RO 7466 */ 7467 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 7468 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 7469 7470 /* reg_rauhtd_ipv6_ent_dip 7471 * Destination IPv6 address. 7472 * Access: RO 7473 */ 7474 MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 7475 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10); 7476 7477 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload, 7478 int ent_index, u16 *p_rif, 7479 u32 *p_dip) 7480 { 7481 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index); 7482 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index); 7483 } 7484 7485 static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload, 7486 int rec_index, u16 *p_rif, 7487 char *p_dip) 7488 { 7489 *p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index); 7490 mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip); 7491 } 7492 7493 /* RTDP - Routing Tunnel Decap Properties Register 7494 * ----------------------------------------------- 7495 * The RTDP register is used for configuring the tunnel decap properties of NVE 7496 * and IPinIP. 7497 */ 7498 #define MLXSW_REG_RTDP_ID 0x8020 7499 #define MLXSW_REG_RTDP_LEN 0x44 7500 7501 MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN); 7502 7503 enum mlxsw_reg_rtdp_type { 7504 MLXSW_REG_RTDP_TYPE_NVE, 7505 MLXSW_REG_RTDP_TYPE_IPIP, 7506 }; 7507 7508 /* reg_rtdp_type 7509 * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type. 7510 * Access: RW 7511 */ 7512 MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4); 7513 7514 /* reg_rtdp_tunnel_index 7515 * Index to the Decap entry. 7516 * For Spectrum, Index to KVD Linear. 7517 * Access: Index 7518 */ 7519 MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24); 7520 7521 /* reg_rtdp_egress_router_interface 7522 * Underlay egress router interface. 7523 * Valid range is from 0 to cap_max_router_interfaces - 1 7524 * Access: RW 7525 */ 7526 MLXSW_ITEM32(reg, rtdp, egress_router_interface, 0x40, 0, 16); 7527 7528 /* IPinIP */ 7529 7530 /* reg_rtdp_ipip_irif 7531 * Ingress Router Interface for the overlay router 7532 * Access: RW 7533 */ 7534 MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16); 7535 7536 enum mlxsw_reg_rtdp_ipip_sip_check { 7537 /* No sip checks. */ 7538 MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO, 7539 /* Filter packet if underlay is not IPv4 or if underlay SIP does not 7540 * equal ipv4_usip. 7541 */ 7542 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4, 7543 /* Filter packet if underlay is not IPv6 or if underlay SIP does not 7544 * equal ipv6_usip. 7545 */ 7546 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3, 7547 }; 7548 7549 /* reg_rtdp_ipip_sip_check 7550 * SIP check to perform. If decapsulation failed due to these configurations 7551 * then trap_id is IPIP_DECAP_ERROR. 7552 * Access: RW 7553 */ 7554 MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3); 7555 7556 /* If set, allow decapsulation of IPinIP (without GRE). */ 7557 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP BIT(0) 7558 /* If set, allow decapsulation of IPinGREinIP without a key. */ 7559 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE BIT(1) 7560 /* If set, allow decapsulation of IPinGREinIP with a key. */ 7561 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY BIT(2) 7562 7563 /* reg_rtdp_ipip_type_check 7564 * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to 7565 * these configurations then trap_id is IPIP_DECAP_ERROR. 7566 * Access: RW 7567 */ 7568 MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3); 7569 7570 /* reg_rtdp_ipip_gre_key_check 7571 * Whether GRE key should be checked. When check is enabled: 7572 * - A packet received as IPinIP (without GRE) will always pass. 7573 * - A packet received as IPinGREinIP without a key will not pass the check. 7574 * - A packet received as IPinGREinIP with a key will pass the check only if the 7575 * key in the packet is equal to expected_gre_key. 7576 * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR. 7577 * Access: RW 7578 */ 7579 MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1); 7580 7581 /* reg_rtdp_ipip_ipv4_usip 7582 * Underlay IPv4 address for ipv4 source address check. 7583 * Reserved when sip_check is not '1'. 7584 * Access: RW 7585 */ 7586 MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32); 7587 7588 /* reg_rtdp_ipip_ipv6_usip_ptr 7589 * This field is valid when sip_check is "sipv6 check explicitly". This is a 7590 * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index 7591 * is to the KVD linear. 7592 * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6. 7593 * Access: RW 7594 */ 7595 MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24); 7596 7597 /* reg_rtdp_ipip_expected_gre_key 7598 * GRE key for checking. 7599 * Reserved when gre_key_check is '0'. 7600 * Access: RW 7601 */ 7602 MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32); 7603 7604 static inline void mlxsw_reg_rtdp_pack(char *payload, 7605 enum mlxsw_reg_rtdp_type type, 7606 u32 tunnel_index) 7607 { 7608 MLXSW_REG_ZERO(rtdp, payload); 7609 mlxsw_reg_rtdp_type_set(payload, type); 7610 mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index); 7611 } 7612 7613 static inline void 7614 mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif, 7615 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 7616 unsigned int type_check, bool gre_key_check, 7617 u32 ipv4_usip, u32 expected_gre_key) 7618 { 7619 mlxsw_reg_rtdp_ipip_irif_set(payload, irif); 7620 mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check); 7621 mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check); 7622 mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check); 7623 mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip); 7624 mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key); 7625 } 7626 7627 /* RIGR-V2 - Router Interface Group Register Version 2 7628 * --------------------------------------------------- 7629 * The RIGR_V2 register is used to add, remove and query egress interface list 7630 * of a multicast forwarding entry. 7631 */ 7632 #define MLXSW_REG_RIGR2_ID 0x8023 7633 #define MLXSW_REG_RIGR2_LEN 0xB0 7634 7635 #define MLXSW_REG_RIGR2_MAX_ERIFS 32 7636 7637 MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN); 7638 7639 /* reg_rigr2_rigr_index 7640 * KVD Linear index. 7641 * Access: Index 7642 */ 7643 MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24); 7644 7645 /* reg_rigr2_vnext 7646 * Next RIGR Index is valid. 7647 * Access: RW 7648 */ 7649 MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1); 7650 7651 /* reg_rigr2_next_rigr_index 7652 * Next RIGR Index. The index is to the KVD linear. 7653 * Reserved when vnxet = '0'. 7654 * Access: RW 7655 */ 7656 MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24); 7657 7658 /* reg_rigr2_vrmid 7659 * RMID Index is valid. 7660 * Access: RW 7661 */ 7662 MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1); 7663 7664 /* reg_rigr2_rmid_index 7665 * RMID Index. 7666 * Range 0 .. max_mid - 1 7667 * Reserved when vrmid = '0'. 7668 * The index is to the Port Group Table (PGT) 7669 * Access: RW 7670 */ 7671 MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16); 7672 7673 /* reg_rigr2_erif_entry_v 7674 * Egress Router Interface is valid. 7675 * Note that low-entries must be set if high-entries are set. For 7676 * example: if erif_entry[2].v is set then erif_entry[1].v and 7677 * erif_entry[0].v must be set. 7678 * Index can be from 0 to cap_mc_erif_list_entries-1 7679 * Access: RW 7680 */ 7681 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false); 7682 7683 /* reg_rigr2_erif_entry_erif 7684 * Egress Router Interface. 7685 * Valid range is from 0 to cap_max_router_interfaces - 1 7686 * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1 7687 * Access: RW 7688 */ 7689 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false); 7690 7691 static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index, 7692 bool vnext, u32 next_rigr_index) 7693 { 7694 MLXSW_REG_ZERO(rigr2, payload); 7695 mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index); 7696 mlxsw_reg_rigr2_vnext_set(payload, vnext); 7697 mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index); 7698 mlxsw_reg_rigr2_vrmid_set(payload, 0); 7699 mlxsw_reg_rigr2_rmid_index_set(payload, 0); 7700 } 7701 7702 static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index, 7703 bool v, u16 erif) 7704 { 7705 mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v); 7706 mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif); 7707 } 7708 7709 /* RECR-V2 - Router ECMP Configuration Version 2 Register 7710 * ------------------------------------------------------ 7711 */ 7712 #define MLXSW_REG_RECR2_ID 0x8025 7713 #define MLXSW_REG_RECR2_LEN 0x38 7714 7715 MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN); 7716 7717 /* reg_recr2_pp 7718 * Per-port configuration 7719 * Access: Index 7720 */ 7721 MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1); 7722 7723 /* reg_recr2_sh 7724 * Symmetric hash 7725 * Access: RW 7726 */ 7727 MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1); 7728 7729 /* reg_recr2_seed 7730 * Seed 7731 * Access: RW 7732 */ 7733 MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32); 7734 7735 enum { 7736 /* Enable IPv4 fields if packet is not TCP and not UDP */ 7737 MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP = 3, 7738 /* Enable IPv4 fields if packet is TCP or UDP */ 7739 MLXSW_REG_RECR2_IPV4_EN_TCP_UDP = 4, 7740 /* Enable IPv6 fields if packet is not TCP and not UDP */ 7741 MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP = 5, 7742 /* Enable IPv6 fields if packet is TCP or UDP */ 7743 MLXSW_REG_RECR2_IPV6_EN_TCP_UDP = 6, 7744 /* Enable TCP/UDP header fields if packet is IPv4 */ 7745 MLXSW_REG_RECR2_TCP_UDP_EN_IPV4 = 7, 7746 /* Enable TCP/UDP header fields if packet is IPv6 */ 7747 MLXSW_REG_RECR2_TCP_UDP_EN_IPV6 = 8, 7748 }; 7749 7750 /* reg_recr2_outer_header_enables 7751 * Bit mask where each bit enables a specific layer to be included in 7752 * the hash calculation. 7753 * Access: RW 7754 */ 7755 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1); 7756 7757 enum { 7758 /* IPv4 Source IP */ 7759 MLXSW_REG_RECR2_IPV4_SIP0 = 9, 7760 MLXSW_REG_RECR2_IPV4_SIP3 = 12, 7761 /* IPv4 Destination IP */ 7762 MLXSW_REG_RECR2_IPV4_DIP0 = 13, 7763 MLXSW_REG_RECR2_IPV4_DIP3 = 16, 7764 /* IP Protocol */ 7765 MLXSW_REG_RECR2_IPV4_PROTOCOL = 17, 7766 /* IPv6 Source IP */ 7767 MLXSW_REG_RECR2_IPV6_SIP0_7 = 21, 7768 MLXSW_REG_RECR2_IPV6_SIP8 = 29, 7769 MLXSW_REG_RECR2_IPV6_SIP15 = 36, 7770 /* IPv6 Destination IP */ 7771 MLXSW_REG_RECR2_IPV6_DIP0_7 = 37, 7772 MLXSW_REG_RECR2_IPV6_DIP8 = 45, 7773 MLXSW_REG_RECR2_IPV6_DIP15 = 52, 7774 /* IPv6 Next Header */ 7775 MLXSW_REG_RECR2_IPV6_NEXT_HEADER = 53, 7776 /* IPv6 Flow Label */ 7777 MLXSW_REG_RECR2_IPV6_FLOW_LABEL = 57, 7778 /* TCP/UDP Source Port */ 7779 MLXSW_REG_RECR2_TCP_UDP_SPORT = 74, 7780 /* TCP/UDP Destination Port */ 7781 MLXSW_REG_RECR2_TCP_UDP_DPORT = 75, 7782 }; 7783 7784 /* reg_recr2_outer_header_fields_enable 7785 * Packet fields to enable for ECMP hash subject to outer_header_enable. 7786 * Access: RW 7787 */ 7788 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1); 7789 7790 static inline void mlxsw_reg_recr2_ipv4_sip_enable(char *payload) 7791 { 7792 int i; 7793 7794 for (i = MLXSW_REG_RECR2_IPV4_SIP0; i <= MLXSW_REG_RECR2_IPV4_SIP3; i++) 7795 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7796 true); 7797 } 7798 7799 static inline void mlxsw_reg_recr2_ipv4_dip_enable(char *payload) 7800 { 7801 int i; 7802 7803 for (i = MLXSW_REG_RECR2_IPV4_DIP0; i <= MLXSW_REG_RECR2_IPV4_DIP3; i++) 7804 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7805 true); 7806 } 7807 7808 static inline void mlxsw_reg_recr2_ipv6_sip_enable(char *payload) 7809 { 7810 int i = MLXSW_REG_RECR2_IPV6_SIP0_7; 7811 7812 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true); 7813 7814 i = MLXSW_REG_RECR2_IPV6_SIP8; 7815 for (; i <= MLXSW_REG_RECR2_IPV6_SIP15; i++) 7816 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7817 true); 7818 } 7819 7820 static inline void mlxsw_reg_recr2_ipv6_dip_enable(char *payload) 7821 { 7822 int i = MLXSW_REG_RECR2_IPV6_DIP0_7; 7823 7824 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true); 7825 7826 i = MLXSW_REG_RECR2_IPV6_DIP8; 7827 for (; i <= MLXSW_REG_RECR2_IPV6_DIP15; i++) 7828 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7829 true); 7830 } 7831 7832 static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed) 7833 { 7834 MLXSW_REG_ZERO(recr2, payload); 7835 mlxsw_reg_recr2_pp_set(payload, false); 7836 mlxsw_reg_recr2_sh_set(payload, true); 7837 mlxsw_reg_recr2_seed_set(payload, seed); 7838 } 7839 7840 /* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register 7841 * -------------------------------------------------------------- 7842 * The RMFT_V2 register is used to configure and query the multicast table. 7843 */ 7844 #define MLXSW_REG_RMFT2_ID 0x8027 7845 #define MLXSW_REG_RMFT2_LEN 0x174 7846 7847 MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN); 7848 7849 /* reg_rmft2_v 7850 * Valid 7851 * Access: RW 7852 */ 7853 MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1); 7854 7855 enum mlxsw_reg_rmft2_type { 7856 MLXSW_REG_RMFT2_TYPE_IPV4, 7857 MLXSW_REG_RMFT2_TYPE_IPV6 7858 }; 7859 7860 /* reg_rmft2_type 7861 * Access: Index 7862 */ 7863 MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2); 7864 7865 enum mlxsw_sp_reg_rmft2_op { 7866 /* For Write: 7867 * Write operation. Used to write a new entry to the table. All RW 7868 * fields are relevant for new entry. Activity bit is set for new 7869 * entries - Note write with v (Valid) 0 will delete the entry. 7870 * For Query: 7871 * Read operation 7872 */ 7873 MLXSW_REG_RMFT2_OP_READ_WRITE, 7874 }; 7875 7876 /* reg_rmft2_op 7877 * Operation. 7878 * Access: OP 7879 */ 7880 MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2); 7881 7882 /* reg_rmft2_a 7883 * Activity. Set for new entries. Set if a packet lookup has hit on the specific 7884 * entry. 7885 * Access: RO 7886 */ 7887 MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1); 7888 7889 /* reg_rmft2_offset 7890 * Offset within the multicast forwarding table to write to. 7891 * Access: Index 7892 */ 7893 MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16); 7894 7895 /* reg_rmft2_virtual_router 7896 * Virtual Router ID. Range from 0..cap_max_virtual_routers-1 7897 * Access: RW 7898 */ 7899 MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16); 7900 7901 enum mlxsw_reg_rmft2_irif_mask { 7902 MLXSW_REG_RMFT2_IRIF_MASK_IGNORE, 7903 MLXSW_REG_RMFT2_IRIF_MASK_COMPARE 7904 }; 7905 7906 /* reg_rmft2_irif_mask 7907 * Ingress RIF mask. 7908 * Access: RW 7909 */ 7910 MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1); 7911 7912 /* reg_rmft2_irif 7913 * Ingress RIF index. 7914 * Access: RW 7915 */ 7916 MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16); 7917 7918 /* reg_rmft2_dip{4,6} 7919 * Destination IPv4/6 address 7920 * Access: RW 7921 */ 7922 MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16); 7923 MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32); 7924 7925 /* reg_rmft2_dip{4,6}_mask 7926 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 7927 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 7928 * Access: RW 7929 */ 7930 MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16); 7931 MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32); 7932 7933 /* reg_rmft2_sip{4,6} 7934 * Source IPv4/6 address 7935 * Access: RW 7936 */ 7937 MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16); 7938 MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32); 7939 7940 /* reg_rmft2_sip{4,6}_mask 7941 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 7942 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 7943 * Access: RW 7944 */ 7945 MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16); 7946 MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32); 7947 7948 /* reg_rmft2_flexible_action_set 7949 * ACL action set. The only supported action types in this field and in any 7950 * action-set pointed from here are as follows: 7951 * 00h: ACTION_NULL 7952 * 01h: ACTION_MAC_TTL, only TTL configuration is supported. 7953 * 03h: ACTION_TRAP 7954 * 06h: ACTION_QOS 7955 * 08h: ACTION_POLICING_MONITORING 7956 * 10h: ACTION_ROUTER_MC 7957 * Access: RW 7958 */ 7959 MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80, 7960 MLXSW_REG_FLEX_ACTION_SET_LEN); 7961 7962 static inline void 7963 mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset, 7964 u16 virtual_router, 7965 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 7966 const char *flex_action_set) 7967 { 7968 MLXSW_REG_ZERO(rmft2, payload); 7969 mlxsw_reg_rmft2_v_set(payload, v); 7970 mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE); 7971 mlxsw_reg_rmft2_offset_set(payload, offset); 7972 mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router); 7973 mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask); 7974 mlxsw_reg_rmft2_irif_set(payload, irif); 7975 if (flex_action_set) 7976 mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload, 7977 flex_action_set); 7978 } 7979 7980 static inline void 7981 mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router, 7982 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 7983 u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask, 7984 const char *flexible_action_set) 7985 { 7986 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 7987 irif_mask, irif, flexible_action_set); 7988 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4); 7989 mlxsw_reg_rmft2_dip4_set(payload, dip4); 7990 mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask); 7991 mlxsw_reg_rmft2_sip4_set(payload, sip4); 7992 mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask); 7993 } 7994 7995 static inline void 7996 mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router, 7997 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 7998 struct in6_addr dip6, struct in6_addr dip6_mask, 7999 struct in6_addr sip6, struct in6_addr sip6_mask, 8000 const char *flexible_action_set) 8001 { 8002 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 8003 irif_mask, irif, flexible_action_set); 8004 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6); 8005 mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6); 8006 mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask); 8007 mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6); 8008 mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask); 8009 } 8010 8011 /* MFCR - Management Fan Control Register 8012 * -------------------------------------- 8013 * This register controls the settings of the Fan Speed PWM mechanism. 8014 */ 8015 #define MLXSW_REG_MFCR_ID 0x9001 8016 #define MLXSW_REG_MFCR_LEN 0x08 8017 8018 MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN); 8019 8020 enum mlxsw_reg_mfcr_pwm_frequency { 8021 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00, 8022 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01, 8023 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02, 8024 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40, 8025 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41, 8026 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42, 8027 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43, 8028 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44, 8029 }; 8030 8031 /* reg_mfcr_pwm_frequency 8032 * Controls the frequency of the PWM signal. 8033 * Access: RW 8034 */ 8035 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7); 8036 8037 #define MLXSW_MFCR_TACHOS_MAX 10 8038 8039 /* reg_mfcr_tacho_active 8040 * Indicates which of the tachometer is active (bit per tachometer). 8041 * Access: RO 8042 */ 8043 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX); 8044 8045 #define MLXSW_MFCR_PWMS_MAX 5 8046 8047 /* reg_mfcr_pwm_active 8048 * Indicates which of the PWM control is active (bit per PWM). 8049 * Access: RO 8050 */ 8051 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX); 8052 8053 static inline void 8054 mlxsw_reg_mfcr_pack(char *payload, 8055 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency) 8056 { 8057 MLXSW_REG_ZERO(mfcr, payload); 8058 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency); 8059 } 8060 8061 static inline void 8062 mlxsw_reg_mfcr_unpack(char *payload, 8063 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency, 8064 u16 *p_tacho_active, u8 *p_pwm_active) 8065 { 8066 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload); 8067 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload); 8068 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload); 8069 } 8070 8071 /* MFSC - Management Fan Speed Control Register 8072 * -------------------------------------------- 8073 * This register controls the settings of the Fan Speed PWM mechanism. 8074 */ 8075 #define MLXSW_REG_MFSC_ID 0x9002 8076 #define MLXSW_REG_MFSC_LEN 0x08 8077 8078 MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN); 8079 8080 /* reg_mfsc_pwm 8081 * Fan pwm to control / monitor. 8082 * Access: Index 8083 */ 8084 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3); 8085 8086 /* reg_mfsc_pwm_duty_cycle 8087 * Controls the duty cycle of the PWM. Value range from 0..255 to 8088 * represent duty cycle of 0%...100%. 8089 * Access: RW 8090 */ 8091 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8); 8092 8093 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm, 8094 u8 pwm_duty_cycle) 8095 { 8096 MLXSW_REG_ZERO(mfsc, payload); 8097 mlxsw_reg_mfsc_pwm_set(payload, pwm); 8098 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle); 8099 } 8100 8101 /* MFSM - Management Fan Speed Measurement 8102 * --------------------------------------- 8103 * This register controls the settings of the Tacho measurements and 8104 * enables reading the Tachometer measurements. 8105 */ 8106 #define MLXSW_REG_MFSM_ID 0x9003 8107 #define MLXSW_REG_MFSM_LEN 0x08 8108 8109 MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN); 8110 8111 /* reg_mfsm_tacho 8112 * Fan tachometer index. 8113 * Access: Index 8114 */ 8115 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4); 8116 8117 /* reg_mfsm_rpm 8118 * Fan speed (round per minute). 8119 * Access: RO 8120 */ 8121 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16); 8122 8123 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho) 8124 { 8125 MLXSW_REG_ZERO(mfsm, payload); 8126 mlxsw_reg_mfsm_tacho_set(payload, tacho); 8127 } 8128 8129 /* MFSL - Management Fan Speed Limit Register 8130 * ------------------------------------------ 8131 * The Fan Speed Limit register is used to configure the fan speed 8132 * event / interrupt notification mechanism. Fan speed threshold are 8133 * defined for both under-speed and over-speed. 8134 */ 8135 #define MLXSW_REG_MFSL_ID 0x9004 8136 #define MLXSW_REG_MFSL_LEN 0x0C 8137 8138 MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN); 8139 8140 /* reg_mfsl_tacho 8141 * Fan tachometer index. 8142 * Access: Index 8143 */ 8144 MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4); 8145 8146 /* reg_mfsl_tach_min 8147 * Tachometer minimum value (minimum RPM). 8148 * Access: RW 8149 */ 8150 MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16); 8151 8152 /* reg_mfsl_tach_max 8153 * Tachometer maximum value (maximum RPM). 8154 * Access: RW 8155 */ 8156 MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16); 8157 8158 static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho, 8159 u16 tach_min, u16 tach_max) 8160 { 8161 MLXSW_REG_ZERO(mfsl, payload); 8162 mlxsw_reg_mfsl_tacho_set(payload, tacho); 8163 mlxsw_reg_mfsl_tach_min_set(payload, tach_min); 8164 mlxsw_reg_mfsl_tach_max_set(payload, tach_max); 8165 } 8166 8167 static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho, 8168 u16 *p_tach_min, u16 *p_tach_max) 8169 { 8170 if (p_tach_min) 8171 *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload); 8172 8173 if (p_tach_max) 8174 *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload); 8175 } 8176 8177 /* FORE - Fan Out of Range Event Register 8178 * -------------------------------------- 8179 * This register reports the status of the controlled fans compared to the 8180 * range defined by the MFSL register. 8181 */ 8182 #define MLXSW_REG_FORE_ID 0x9007 8183 #define MLXSW_REG_FORE_LEN 0x0C 8184 8185 MLXSW_REG_DEFINE(fore, MLXSW_REG_FORE_ID, MLXSW_REG_FORE_LEN); 8186 8187 /* fan_under_limit 8188 * Fan speed is below the low limit defined in MFSL register. Each bit relates 8189 * to a single tachometer and indicates the specific tachometer reading is 8190 * below the threshold. 8191 * Access: RO 8192 */ 8193 MLXSW_ITEM32(reg, fore, fan_under_limit, 0x00, 16, 10); 8194 8195 static inline void mlxsw_reg_fore_unpack(char *payload, u8 tacho, 8196 bool *fault) 8197 { 8198 u16 limit; 8199 8200 if (fault) { 8201 limit = mlxsw_reg_fore_fan_under_limit_get(payload); 8202 *fault = limit & BIT(tacho); 8203 } 8204 } 8205 8206 /* MTCAP - Management Temperature Capabilities 8207 * ------------------------------------------- 8208 * This register exposes the capabilities of the device and 8209 * system temperature sensing. 8210 */ 8211 #define MLXSW_REG_MTCAP_ID 0x9009 8212 #define MLXSW_REG_MTCAP_LEN 0x08 8213 8214 MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN); 8215 8216 /* reg_mtcap_sensor_count 8217 * Number of sensors supported by the device. 8218 * This includes the QSFP module sensors (if exists in the QSFP module). 8219 * Access: RO 8220 */ 8221 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7); 8222 8223 /* MTMP - Management Temperature 8224 * ----------------------------- 8225 * This register controls the settings of the temperature measurements 8226 * and enables reading the temperature measurements. Note that temperature 8227 * is in 0.125 degrees Celsius. 8228 */ 8229 #define MLXSW_REG_MTMP_ID 0x900A 8230 #define MLXSW_REG_MTMP_LEN 0x20 8231 8232 MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN); 8233 8234 #define MLXSW_REG_MTMP_MODULE_INDEX_MIN 64 8235 #define MLXSW_REG_MTMP_GBOX_INDEX_MIN 256 8236 /* reg_mtmp_sensor_index 8237 * Sensors index to access. 8238 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially 8239 * (module 0 is mapped to sensor_index 64). 8240 * Access: Index 8241 */ 8242 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 12); 8243 8244 /* Convert to milli degrees Celsius */ 8245 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) ({ typeof(val) v_ = (val); \ 8246 ((v_) >= 0) ? ((v_) * 125) : \ 8247 ((s16)((GENMASK(15, 0) + (v_) + 1) \ 8248 * 125)); }) 8249 8250 /* reg_mtmp_temperature 8251 * Temperature reading from the sensor. Reading is in 0.125 Celsius 8252 * degrees units. 8253 * Access: RO 8254 */ 8255 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16); 8256 8257 /* reg_mtmp_mte 8258 * Max Temperature Enable - enables measuring the max temperature on a sensor. 8259 * Access: RW 8260 */ 8261 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1); 8262 8263 /* reg_mtmp_mtr 8264 * Max Temperature Reset - clears the value of the max temperature register. 8265 * Access: WO 8266 */ 8267 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1); 8268 8269 /* reg_mtmp_max_temperature 8270 * The highest measured temperature from the sensor. 8271 * When the bit mte is cleared, the field max_temperature is reserved. 8272 * Access: RO 8273 */ 8274 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16); 8275 8276 /* reg_mtmp_tee 8277 * Temperature Event Enable. 8278 * 0 - Do not generate event 8279 * 1 - Generate event 8280 * 2 - Generate single event 8281 * Access: RW 8282 */ 8283 MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2); 8284 8285 #define MLXSW_REG_MTMP_THRESH_HI 0x348 /* 105 Celsius */ 8286 8287 /* reg_mtmp_temperature_threshold_hi 8288 * High threshold for Temperature Warning Event. In 0.125 Celsius. 8289 * Access: RW 8290 */ 8291 MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16); 8292 8293 /* reg_mtmp_temperature_threshold_lo 8294 * Low threshold for Temperature Warning Event. In 0.125 Celsius. 8295 * Access: RW 8296 */ 8297 MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16); 8298 8299 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8 8300 8301 /* reg_mtmp_sensor_name 8302 * Sensor Name 8303 * Access: RO 8304 */ 8305 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE); 8306 8307 static inline void mlxsw_reg_mtmp_pack(char *payload, u16 sensor_index, 8308 bool max_temp_enable, 8309 bool max_temp_reset) 8310 { 8311 MLXSW_REG_ZERO(mtmp, payload); 8312 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index); 8313 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable); 8314 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset); 8315 mlxsw_reg_mtmp_temperature_threshold_hi_set(payload, 8316 MLXSW_REG_MTMP_THRESH_HI); 8317 } 8318 8319 static inline void mlxsw_reg_mtmp_unpack(char *payload, int *p_temp, 8320 int *p_max_temp, char *sensor_name) 8321 { 8322 s16 temp; 8323 8324 if (p_temp) { 8325 temp = mlxsw_reg_mtmp_temperature_get(payload); 8326 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 8327 } 8328 if (p_max_temp) { 8329 temp = mlxsw_reg_mtmp_max_temperature_get(payload); 8330 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 8331 } 8332 if (sensor_name) 8333 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name); 8334 } 8335 8336 /* MTBR - Management Temperature Bulk Register 8337 * ------------------------------------------- 8338 * This register is used for bulk temperature reading. 8339 */ 8340 #define MLXSW_REG_MTBR_ID 0x900F 8341 #define MLXSW_REG_MTBR_BASE_LEN 0x10 /* base length, without records */ 8342 #define MLXSW_REG_MTBR_REC_LEN 0x04 /* record length */ 8343 #define MLXSW_REG_MTBR_REC_MAX_COUNT 47 /* firmware limitation */ 8344 #define MLXSW_REG_MTBR_LEN (MLXSW_REG_MTBR_BASE_LEN + \ 8345 MLXSW_REG_MTBR_REC_LEN * \ 8346 MLXSW_REG_MTBR_REC_MAX_COUNT) 8347 8348 MLXSW_REG_DEFINE(mtbr, MLXSW_REG_MTBR_ID, MLXSW_REG_MTBR_LEN); 8349 8350 /* reg_mtbr_base_sensor_index 8351 * Base sensors index to access (0 - ASIC sensor, 1-63 - ambient sensors, 8352 * 64-127 are mapped to the SFP+/QSFP modules sequentially). 8353 * Access: Index 8354 */ 8355 MLXSW_ITEM32(reg, mtbr, base_sensor_index, 0x00, 0, 12); 8356 8357 /* reg_mtbr_num_rec 8358 * Request: Number of records to read 8359 * Response: Number of records read 8360 * See above description for more details. 8361 * Range 1..255 8362 * Access: RW 8363 */ 8364 MLXSW_ITEM32(reg, mtbr, num_rec, 0x04, 0, 8); 8365 8366 /* reg_mtbr_rec_max_temp 8367 * The highest measured temperature from the sensor. 8368 * When the bit mte is cleared, the field max_temperature is reserved. 8369 * Access: RO 8370 */ 8371 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_max_temp, MLXSW_REG_MTBR_BASE_LEN, 16, 8372 16, MLXSW_REG_MTBR_REC_LEN, 0x00, false); 8373 8374 /* reg_mtbr_rec_temp 8375 * Temperature reading from the sensor. Reading is in 0..125 Celsius 8376 * degrees units. 8377 * Access: RO 8378 */ 8379 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_temp, MLXSW_REG_MTBR_BASE_LEN, 0, 16, 8380 MLXSW_REG_MTBR_REC_LEN, 0x00, false); 8381 8382 static inline void mlxsw_reg_mtbr_pack(char *payload, u16 base_sensor_index, 8383 u8 num_rec) 8384 { 8385 MLXSW_REG_ZERO(mtbr, payload); 8386 mlxsw_reg_mtbr_base_sensor_index_set(payload, base_sensor_index); 8387 mlxsw_reg_mtbr_num_rec_set(payload, num_rec); 8388 } 8389 8390 /* Error codes from temperatute reading */ 8391 enum mlxsw_reg_mtbr_temp_status { 8392 MLXSW_REG_MTBR_NO_CONN = 0x8000, 8393 MLXSW_REG_MTBR_NO_TEMP_SENS = 0x8001, 8394 MLXSW_REG_MTBR_INDEX_NA = 0x8002, 8395 MLXSW_REG_MTBR_BAD_SENS_INFO = 0x8003, 8396 }; 8397 8398 /* Base index for reading modules temperature */ 8399 #define MLXSW_REG_MTBR_BASE_MODULE_INDEX 64 8400 8401 static inline void mlxsw_reg_mtbr_temp_unpack(char *payload, int rec_ind, 8402 u16 *p_temp, u16 *p_max_temp) 8403 { 8404 if (p_temp) 8405 *p_temp = mlxsw_reg_mtbr_rec_temp_get(payload, rec_ind); 8406 if (p_max_temp) 8407 *p_max_temp = mlxsw_reg_mtbr_rec_max_temp_get(payload, rec_ind); 8408 } 8409 8410 /* MCIA - Management Cable Info Access 8411 * ----------------------------------- 8412 * MCIA register is used to access the SFP+ and QSFP connector's EPROM. 8413 */ 8414 8415 #define MLXSW_REG_MCIA_ID 0x9014 8416 #define MLXSW_REG_MCIA_LEN 0x40 8417 8418 MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN); 8419 8420 /* reg_mcia_l 8421 * Lock bit. Setting this bit will lock the access to the specific 8422 * cable. Used for updating a full page in a cable EPROM. Any access 8423 * other then subsequence writes will fail while the port is locked. 8424 * Access: RW 8425 */ 8426 MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1); 8427 8428 /* reg_mcia_module 8429 * Module number. 8430 * Access: Index 8431 */ 8432 MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8); 8433 8434 /* reg_mcia_status 8435 * Module status. 8436 * Access: RO 8437 */ 8438 MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8); 8439 8440 /* reg_mcia_i2c_device_address 8441 * I2C device address. 8442 * Access: RW 8443 */ 8444 MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8); 8445 8446 /* reg_mcia_page_number 8447 * Page number. 8448 * Access: RW 8449 */ 8450 MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8); 8451 8452 /* reg_mcia_device_address 8453 * Device address. 8454 * Access: RW 8455 */ 8456 MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16); 8457 8458 /* reg_mcia_size 8459 * Number of bytes to read/write (up to 48 bytes). 8460 * Access: RW 8461 */ 8462 MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16); 8463 8464 #define MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH 256 8465 #define MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH 128 8466 #define MLXSW_REG_MCIA_EEPROM_SIZE 48 8467 #define MLXSW_REG_MCIA_I2C_ADDR_LOW 0x50 8468 #define MLXSW_REG_MCIA_I2C_ADDR_HIGH 0x51 8469 #define MLXSW_REG_MCIA_PAGE0_LO_OFF 0xa0 8470 #define MLXSW_REG_MCIA_TH_ITEM_SIZE 2 8471 #define MLXSW_REG_MCIA_TH_PAGE_NUM 3 8472 #define MLXSW_REG_MCIA_PAGE0_LO 0 8473 #define MLXSW_REG_MCIA_TH_PAGE_OFF 0x80 8474 8475 enum mlxsw_reg_mcia_eeprom_module_info_rev_id { 8476 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00, 8477 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01, 8478 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03, 8479 }; 8480 8481 enum mlxsw_reg_mcia_eeprom_module_info_id { 8482 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_SFP = 0x03, 8483 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP = 0x0C, 8484 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D, 8485 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11, 8486 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_DD = 0x18, 8487 }; 8488 8489 enum mlxsw_reg_mcia_eeprom_module_info { 8490 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID, 8491 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID, 8492 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_SIZE, 8493 }; 8494 8495 /* reg_mcia_eeprom 8496 * Bytes to read/write. 8497 * Access: RW 8498 */ 8499 MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_REG_MCIA_EEPROM_SIZE); 8500 8501 /* This is used to access the optional upper pages (1-3) in the QSFP+ 8502 * memory map. Page 1 is available on offset 256 through 383, page 2 - 8503 * on offset 384 through 511, page 3 - on offset 512 through 639. 8504 */ 8505 #define MLXSW_REG_MCIA_PAGE_GET(off) (((off) - \ 8506 MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH) / \ 8507 MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH + 1) 8508 8509 static inline void mlxsw_reg_mcia_pack(char *payload, u8 module, u8 lock, 8510 u8 page_number, u16 device_addr, 8511 u8 size, u8 i2c_device_addr) 8512 { 8513 MLXSW_REG_ZERO(mcia, payload); 8514 mlxsw_reg_mcia_module_set(payload, module); 8515 mlxsw_reg_mcia_l_set(payload, lock); 8516 mlxsw_reg_mcia_page_number_set(payload, page_number); 8517 mlxsw_reg_mcia_device_address_set(payload, device_addr); 8518 mlxsw_reg_mcia_size_set(payload, size); 8519 mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr); 8520 } 8521 8522 /* MPAT - Monitoring Port Analyzer Table 8523 * ------------------------------------- 8524 * MPAT Register is used to query and configure the Switch PortAnalyzer Table. 8525 * For an enabled analyzer, all fields except e (enable) cannot be modified. 8526 */ 8527 #define MLXSW_REG_MPAT_ID 0x901A 8528 #define MLXSW_REG_MPAT_LEN 0x78 8529 8530 MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN); 8531 8532 /* reg_mpat_pa_id 8533 * Port Analyzer ID. 8534 * Access: Index 8535 */ 8536 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4); 8537 8538 /* reg_mpat_system_port 8539 * A unique port identifier for the final destination of the packet. 8540 * Access: RW 8541 */ 8542 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16); 8543 8544 /* reg_mpat_e 8545 * Enable. Indicating the Port Analyzer is enabled. 8546 * Access: RW 8547 */ 8548 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1); 8549 8550 /* reg_mpat_qos 8551 * Quality Of Service Mode. 8552 * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation 8553 * PCP, DEI, DSCP or VL) are configured. 8554 * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the 8555 * same as in the original packet that has triggered the mirroring. For 8556 * SPAN also the pcp,dei are maintained. 8557 * Access: RW 8558 */ 8559 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1); 8560 8561 /* reg_mpat_be 8562 * Best effort mode. Indicates mirroring traffic should not cause packet 8563 * drop or back pressure, but will discard the mirrored packets. Mirrored 8564 * packets will be forwarded on a best effort manner. 8565 * 0: Do not discard mirrored packets 8566 * 1: Discard mirrored packets if causing congestion 8567 * Access: RW 8568 */ 8569 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1); 8570 8571 enum mlxsw_reg_mpat_span_type { 8572 /* Local SPAN Ethernet. 8573 * The original packet is not encapsulated. 8574 */ 8575 MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0, 8576 8577 /* Remote SPAN Ethernet VLAN. 8578 * The packet is forwarded to the monitoring port on the monitoring 8579 * VLAN. 8580 */ 8581 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1, 8582 8583 /* Encapsulated Remote SPAN Ethernet L3 GRE. 8584 * The packet is encapsulated with GRE header. 8585 */ 8586 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3, 8587 }; 8588 8589 /* reg_mpat_span_type 8590 * SPAN type. 8591 * Access: RW 8592 */ 8593 MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4); 8594 8595 /* Remote SPAN - Ethernet VLAN 8596 * - - - - - - - - - - - - - - 8597 */ 8598 8599 /* reg_mpat_eth_rspan_vid 8600 * Encapsulation header VLAN ID. 8601 * Access: RW 8602 */ 8603 MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12); 8604 8605 /* Encapsulated Remote SPAN - Ethernet L2 8606 * - - - - - - - - - - - - - - - - - - - 8607 */ 8608 8609 enum mlxsw_reg_mpat_eth_rspan_version { 8610 MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15, 8611 }; 8612 8613 /* reg_mpat_eth_rspan_version 8614 * RSPAN mirror header version. 8615 * Access: RW 8616 */ 8617 MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4); 8618 8619 /* reg_mpat_eth_rspan_mac 8620 * Destination MAC address. 8621 * Access: RW 8622 */ 8623 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6); 8624 8625 /* reg_mpat_eth_rspan_tp 8626 * Tag Packet. Indicates whether the mirroring header should be VLAN tagged. 8627 * Access: RW 8628 */ 8629 MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1); 8630 8631 /* Encapsulated Remote SPAN - Ethernet L3 8632 * - - - - - - - - - - - - - - - - - - - 8633 */ 8634 8635 enum mlxsw_reg_mpat_eth_rspan_protocol { 8636 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4, 8637 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6, 8638 }; 8639 8640 /* reg_mpat_eth_rspan_protocol 8641 * SPAN encapsulation protocol. 8642 * Access: RW 8643 */ 8644 MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4); 8645 8646 /* reg_mpat_eth_rspan_ttl 8647 * Encapsulation header Time-to-Live/HopLimit. 8648 * Access: RW 8649 */ 8650 MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8); 8651 8652 /* reg_mpat_eth_rspan_smac 8653 * Source MAC address 8654 * Access: RW 8655 */ 8656 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6); 8657 8658 /* reg_mpat_eth_rspan_dip* 8659 * Destination IP address. The IP version is configured by protocol. 8660 * Access: RW 8661 */ 8662 MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32); 8663 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16); 8664 8665 /* reg_mpat_eth_rspan_sip* 8666 * Source IP address. The IP version is configured by protocol. 8667 * Access: RW 8668 */ 8669 MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32); 8670 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16); 8671 8672 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id, 8673 u16 system_port, bool e, 8674 enum mlxsw_reg_mpat_span_type span_type) 8675 { 8676 MLXSW_REG_ZERO(mpat, payload); 8677 mlxsw_reg_mpat_pa_id_set(payload, pa_id); 8678 mlxsw_reg_mpat_system_port_set(payload, system_port); 8679 mlxsw_reg_mpat_e_set(payload, e); 8680 mlxsw_reg_mpat_qos_set(payload, 1); 8681 mlxsw_reg_mpat_be_set(payload, 1); 8682 mlxsw_reg_mpat_span_type_set(payload, span_type); 8683 } 8684 8685 static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid) 8686 { 8687 mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid); 8688 } 8689 8690 static inline void 8691 mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload, 8692 enum mlxsw_reg_mpat_eth_rspan_version version, 8693 const char *mac, 8694 bool tp) 8695 { 8696 mlxsw_reg_mpat_eth_rspan_version_set(payload, version); 8697 mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac); 8698 mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp); 8699 } 8700 8701 static inline void 8702 mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl, 8703 const char *smac, 8704 u32 sip, u32 dip) 8705 { 8706 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 8707 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 8708 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 8709 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4); 8710 mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip); 8711 mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip); 8712 } 8713 8714 static inline void 8715 mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl, 8716 const char *smac, 8717 struct in6_addr sip, struct in6_addr dip) 8718 { 8719 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 8720 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 8721 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 8722 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6); 8723 mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip); 8724 mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip); 8725 } 8726 8727 /* MPAR - Monitoring Port Analyzer Register 8728 * ---------------------------------------- 8729 * MPAR register is used to query and configure the port analyzer port mirroring 8730 * properties. 8731 */ 8732 #define MLXSW_REG_MPAR_ID 0x901B 8733 #define MLXSW_REG_MPAR_LEN 0x0C 8734 8735 MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN); 8736 8737 /* reg_mpar_local_port 8738 * The local port to mirror the packets from. 8739 * Access: Index 8740 */ 8741 MLXSW_ITEM32(reg, mpar, local_port, 0x00, 16, 8); 8742 8743 enum mlxsw_reg_mpar_i_e { 8744 MLXSW_REG_MPAR_TYPE_EGRESS, 8745 MLXSW_REG_MPAR_TYPE_INGRESS, 8746 }; 8747 8748 /* reg_mpar_i_e 8749 * Ingress/Egress 8750 * Access: Index 8751 */ 8752 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4); 8753 8754 /* reg_mpar_enable 8755 * Enable mirroring 8756 * By default, port mirroring is disabled for all ports. 8757 * Access: RW 8758 */ 8759 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1); 8760 8761 /* reg_mpar_pa_id 8762 * Port Analyzer ID. 8763 * Access: RW 8764 */ 8765 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4); 8766 8767 static inline void mlxsw_reg_mpar_pack(char *payload, u8 local_port, 8768 enum mlxsw_reg_mpar_i_e i_e, 8769 bool enable, u8 pa_id) 8770 { 8771 MLXSW_REG_ZERO(mpar, payload); 8772 mlxsw_reg_mpar_local_port_set(payload, local_port); 8773 mlxsw_reg_mpar_enable_set(payload, enable); 8774 mlxsw_reg_mpar_i_e_set(payload, i_e); 8775 mlxsw_reg_mpar_pa_id_set(payload, pa_id); 8776 } 8777 8778 /* MGIR - Management General Information Register 8779 * ---------------------------------------------- 8780 * MGIR register allows software to query the hardware and firmware general 8781 * information. 8782 */ 8783 #define MLXSW_REG_MGIR_ID 0x9020 8784 #define MLXSW_REG_MGIR_LEN 0x9C 8785 8786 MLXSW_REG_DEFINE(mgir, MLXSW_REG_MGIR_ID, MLXSW_REG_MGIR_LEN); 8787 8788 /* reg_mgir_hw_info_device_hw_revision 8789 * Access: RO 8790 */ 8791 MLXSW_ITEM32(reg, mgir, hw_info_device_hw_revision, 0x0, 16, 16); 8792 8793 #define MLXSW_REG_MGIR_FW_INFO_PSID_SIZE 16 8794 8795 /* reg_mgir_fw_info_psid 8796 * PSID (ASCII string). 8797 * Access: RO 8798 */ 8799 MLXSW_ITEM_BUF(reg, mgir, fw_info_psid, 0x30, MLXSW_REG_MGIR_FW_INFO_PSID_SIZE); 8800 8801 /* reg_mgir_fw_info_extended_major 8802 * Access: RO 8803 */ 8804 MLXSW_ITEM32(reg, mgir, fw_info_extended_major, 0x44, 0, 32); 8805 8806 /* reg_mgir_fw_info_extended_minor 8807 * Access: RO 8808 */ 8809 MLXSW_ITEM32(reg, mgir, fw_info_extended_minor, 0x48, 0, 32); 8810 8811 /* reg_mgir_fw_info_extended_sub_minor 8812 * Access: RO 8813 */ 8814 MLXSW_ITEM32(reg, mgir, fw_info_extended_sub_minor, 0x4C, 0, 32); 8815 8816 static inline void mlxsw_reg_mgir_pack(char *payload) 8817 { 8818 MLXSW_REG_ZERO(mgir, payload); 8819 } 8820 8821 static inline void 8822 mlxsw_reg_mgir_unpack(char *payload, u32 *hw_rev, char *fw_info_psid, 8823 u32 *fw_major, u32 *fw_minor, u32 *fw_sub_minor) 8824 { 8825 *hw_rev = mlxsw_reg_mgir_hw_info_device_hw_revision_get(payload); 8826 mlxsw_reg_mgir_fw_info_psid_memcpy_from(payload, fw_info_psid); 8827 *fw_major = mlxsw_reg_mgir_fw_info_extended_major_get(payload); 8828 *fw_minor = mlxsw_reg_mgir_fw_info_extended_minor_get(payload); 8829 *fw_sub_minor = mlxsw_reg_mgir_fw_info_extended_sub_minor_get(payload); 8830 } 8831 8832 /* MRSR - Management Reset and Shutdown Register 8833 * --------------------------------------------- 8834 * MRSR register is used to reset or shutdown the switch or 8835 * the entire system (when applicable). 8836 */ 8837 #define MLXSW_REG_MRSR_ID 0x9023 8838 #define MLXSW_REG_MRSR_LEN 0x08 8839 8840 MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN); 8841 8842 /* reg_mrsr_command 8843 * Reset/shutdown command 8844 * 0 - do nothing 8845 * 1 - software reset 8846 * Access: WO 8847 */ 8848 MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4); 8849 8850 static inline void mlxsw_reg_mrsr_pack(char *payload) 8851 { 8852 MLXSW_REG_ZERO(mrsr, payload); 8853 mlxsw_reg_mrsr_command_set(payload, 1); 8854 } 8855 8856 /* MLCR - Management LED Control Register 8857 * -------------------------------------- 8858 * Controls the system LEDs. 8859 */ 8860 #define MLXSW_REG_MLCR_ID 0x902B 8861 #define MLXSW_REG_MLCR_LEN 0x0C 8862 8863 MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN); 8864 8865 /* reg_mlcr_local_port 8866 * Local port number. 8867 * Access: RW 8868 */ 8869 MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8); 8870 8871 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF 8872 8873 /* reg_mlcr_beacon_duration 8874 * Duration of the beacon to be active, in seconds. 8875 * 0x0 - Will turn off the beacon. 8876 * 0xFFFF - Will turn on the beacon until explicitly turned off. 8877 * Access: RW 8878 */ 8879 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16); 8880 8881 /* reg_mlcr_beacon_remain 8882 * Remaining duration of the beacon, in seconds. 8883 * 0xFFFF indicates an infinite amount of time. 8884 * Access: RO 8885 */ 8886 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16); 8887 8888 static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port, 8889 bool active) 8890 { 8891 MLXSW_REG_ZERO(mlcr, payload); 8892 mlxsw_reg_mlcr_local_port_set(payload, local_port); 8893 mlxsw_reg_mlcr_beacon_duration_set(payload, active ? 8894 MLXSW_REG_MLCR_DURATION_MAX : 0); 8895 } 8896 8897 /* MTPPS - Management Pulse Per Second Register 8898 * -------------------------------------------- 8899 * This register provides the device PPS capabilities, configure the PPS in and 8900 * out modules and holds the PPS in time stamp. 8901 */ 8902 #define MLXSW_REG_MTPPS_ID 0x9053 8903 #define MLXSW_REG_MTPPS_LEN 0x3C 8904 8905 MLXSW_REG_DEFINE(mtpps, MLXSW_REG_MTPPS_ID, MLXSW_REG_MTPPS_LEN); 8906 8907 /* reg_mtpps_enable 8908 * Enables the PPS functionality the specific pin. 8909 * A boolean variable. 8910 * Access: RW 8911 */ 8912 MLXSW_ITEM32(reg, mtpps, enable, 0x20, 31, 1); 8913 8914 enum mlxsw_reg_mtpps_pin_mode { 8915 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN = 0x2, 8916 }; 8917 8918 /* reg_mtpps_pin_mode 8919 * Pin mode to be used. The mode must comply with the supported modes of the 8920 * requested pin. 8921 * Access: RW 8922 */ 8923 MLXSW_ITEM32(reg, mtpps, pin_mode, 0x20, 8, 4); 8924 8925 #define MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN 7 8926 8927 /* reg_mtpps_pin 8928 * Pin to be configured or queried out of the supported pins. 8929 * Access: Index 8930 */ 8931 MLXSW_ITEM32(reg, mtpps, pin, 0x20, 0, 8); 8932 8933 /* reg_mtpps_time_stamp 8934 * When pin_mode = pps_in, the latched device time when it was triggered from 8935 * the external GPIO pin. 8936 * When pin_mode = pps_out or virtual_pin or pps_out_and_virtual_pin, the target 8937 * time to generate next output signal. 8938 * Time is in units of device clock. 8939 * Access: RW 8940 */ 8941 MLXSW_ITEM64(reg, mtpps, time_stamp, 0x28, 0, 64); 8942 8943 static inline void 8944 mlxsw_reg_mtpps_vpin_pack(char *payload, u64 time_stamp) 8945 { 8946 MLXSW_REG_ZERO(mtpps, payload); 8947 mlxsw_reg_mtpps_pin_set(payload, MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN); 8948 mlxsw_reg_mtpps_pin_mode_set(payload, 8949 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN); 8950 mlxsw_reg_mtpps_enable_set(payload, true); 8951 mlxsw_reg_mtpps_time_stamp_set(payload, time_stamp); 8952 } 8953 8954 /* MTUTC - Management UTC Register 8955 * ------------------------------- 8956 * Configures the HW UTC counter. 8957 */ 8958 #define MLXSW_REG_MTUTC_ID 0x9055 8959 #define MLXSW_REG_MTUTC_LEN 0x1C 8960 8961 MLXSW_REG_DEFINE(mtutc, MLXSW_REG_MTUTC_ID, MLXSW_REG_MTUTC_LEN); 8962 8963 enum mlxsw_reg_mtutc_operation { 8964 MLXSW_REG_MTUTC_OPERATION_SET_TIME_AT_NEXT_SEC = 0, 8965 MLXSW_REG_MTUTC_OPERATION_ADJUST_FREQ = 3, 8966 }; 8967 8968 /* reg_mtutc_operation 8969 * Operation. 8970 * Access: OP 8971 */ 8972 MLXSW_ITEM32(reg, mtutc, operation, 0x00, 0, 4); 8973 8974 /* reg_mtutc_freq_adjustment 8975 * Frequency adjustment: Every PPS the HW frequency will be 8976 * adjusted by this value. Units of HW clock, where HW counts 8977 * 10^9 HW clocks for 1 HW second. 8978 * Access: RW 8979 */ 8980 MLXSW_ITEM32(reg, mtutc, freq_adjustment, 0x04, 0, 32); 8981 8982 /* reg_mtutc_utc_sec 8983 * UTC seconds. 8984 * Access: WO 8985 */ 8986 MLXSW_ITEM32(reg, mtutc, utc_sec, 0x10, 0, 32); 8987 8988 static inline void 8989 mlxsw_reg_mtutc_pack(char *payload, enum mlxsw_reg_mtutc_operation oper, 8990 u32 freq_adj, u32 utc_sec) 8991 { 8992 MLXSW_REG_ZERO(mtutc, payload); 8993 mlxsw_reg_mtutc_operation_set(payload, oper); 8994 mlxsw_reg_mtutc_freq_adjustment_set(payload, freq_adj); 8995 mlxsw_reg_mtutc_utc_sec_set(payload, utc_sec); 8996 } 8997 8998 /* MCQI - Management Component Query Information 8999 * --------------------------------------------- 9000 * This register allows querying information about firmware components. 9001 */ 9002 #define MLXSW_REG_MCQI_ID 0x9061 9003 #define MLXSW_REG_MCQI_BASE_LEN 0x18 9004 #define MLXSW_REG_MCQI_CAP_LEN 0x14 9005 #define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN) 9006 9007 MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN); 9008 9009 /* reg_mcqi_component_index 9010 * Index of the accessed component. 9011 * Access: Index 9012 */ 9013 MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16); 9014 9015 enum mlxfw_reg_mcqi_info_type { 9016 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES, 9017 }; 9018 9019 /* reg_mcqi_info_type 9020 * Component properties set. 9021 * Access: RW 9022 */ 9023 MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5); 9024 9025 /* reg_mcqi_offset 9026 * The requested/returned data offset from the section start, given in bytes. 9027 * Must be DWORD aligned. 9028 * Access: RW 9029 */ 9030 MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32); 9031 9032 /* reg_mcqi_data_size 9033 * The requested/returned data size, given in bytes. If data_size is not DWORD 9034 * aligned, the last bytes are zero padded. 9035 * Access: RW 9036 */ 9037 MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16); 9038 9039 /* reg_mcqi_cap_max_component_size 9040 * Maximum size for this component, given in bytes. 9041 * Access: RO 9042 */ 9043 MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32); 9044 9045 /* reg_mcqi_cap_log_mcda_word_size 9046 * Log 2 of the access word size in bytes. Read and write access must be aligned 9047 * to the word size. Write access must be done for an integer number of words. 9048 * Access: RO 9049 */ 9050 MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4); 9051 9052 /* reg_mcqi_cap_mcda_max_write_size 9053 * Maximal write size for MCDA register 9054 * Access: RO 9055 */ 9056 MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16); 9057 9058 static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index) 9059 { 9060 MLXSW_REG_ZERO(mcqi, payload); 9061 mlxsw_reg_mcqi_component_index_set(payload, component_index); 9062 mlxsw_reg_mcqi_info_type_set(payload, 9063 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES); 9064 mlxsw_reg_mcqi_offset_set(payload, 0); 9065 mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN); 9066 } 9067 9068 static inline void mlxsw_reg_mcqi_unpack(char *payload, 9069 u32 *p_cap_max_component_size, 9070 u8 *p_cap_log_mcda_word_size, 9071 u16 *p_cap_mcda_max_write_size) 9072 { 9073 *p_cap_max_component_size = 9074 mlxsw_reg_mcqi_cap_max_component_size_get(payload); 9075 *p_cap_log_mcda_word_size = 9076 mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload); 9077 *p_cap_mcda_max_write_size = 9078 mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload); 9079 } 9080 9081 /* MCC - Management Component Control 9082 * ---------------------------------- 9083 * Controls the firmware component and updates the FSM. 9084 */ 9085 #define MLXSW_REG_MCC_ID 0x9062 9086 #define MLXSW_REG_MCC_LEN 0x1C 9087 9088 MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN); 9089 9090 enum mlxsw_reg_mcc_instruction { 9091 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01, 9092 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02, 9093 MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03, 9094 MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04, 9095 MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06, 9096 MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08, 9097 }; 9098 9099 /* reg_mcc_instruction 9100 * Command to be executed by the FSM. 9101 * Applicable for write operation only. 9102 * Access: RW 9103 */ 9104 MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8); 9105 9106 /* reg_mcc_component_index 9107 * Index of the accessed component. Applicable only for commands that 9108 * refer to components. Otherwise, this field is reserved. 9109 * Access: Index 9110 */ 9111 MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16); 9112 9113 /* reg_mcc_update_handle 9114 * Token representing the current flow executed by the FSM. 9115 * Access: WO 9116 */ 9117 MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24); 9118 9119 /* reg_mcc_error_code 9120 * Indicates the successful completion of the instruction, or the reason it 9121 * failed 9122 * Access: RO 9123 */ 9124 MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8); 9125 9126 /* reg_mcc_control_state 9127 * Current FSM state 9128 * Access: RO 9129 */ 9130 MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4); 9131 9132 /* reg_mcc_component_size 9133 * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying 9134 * the size may shorten the update time. Value 0x0 means that size is 9135 * unspecified. 9136 * Access: WO 9137 */ 9138 MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32); 9139 9140 static inline void mlxsw_reg_mcc_pack(char *payload, 9141 enum mlxsw_reg_mcc_instruction instr, 9142 u16 component_index, u32 update_handle, 9143 u32 component_size) 9144 { 9145 MLXSW_REG_ZERO(mcc, payload); 9146 mlxsw_reg_mcc_instruction_set(payload, instr); 9147 mlxsw_reg_mcc_component_index_set(payload, component_index); 9148 mlxsw_reg_mcc_update_handle_set(payload, update_handle); 9149 mlxsw_reg_mcc_component_size_set(payload, component_size); 9150 } 9151 9152 static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle, 9153 u8 *p_error_code, u8 *p_control_state) 9154 { 9155 if (p_update_handle) 9156 *p_update_handle = mlxsw_reg_mcc_update_handle_get(payload); 9157 if (p_error_code) 9158 *p_error_code = mlxsw_reg_mcc_error_code_get(payload); 9159 if (p_control_state) 9160 *p_control_state = mlxsw_reg_mcc_control_state_get(payload); 9161 } 9162 9163 /* MCDA - Management Component Data Access 9164 * --------------------------------------- 9165 * This register allows reading and writing a firmware component. 9166 */ 9167 #define MLXSW_REG_MCDA_ID 0x9063 9168 #define MLXSW_REG_MCDA_BASE_LEN 0x10 9169 #define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80 9170 #define MLXSW_REG_MCDA_LEN \ 9171 (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN) 9172 9173 MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN); 9174 9175 /* reg_mcda_update_handle 9176 * Token representing the current flow executed by the FSM. 9177 * Access: RW 9178 */ 9179 MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24); 9180 9181 /* reg_mcda_offset 9182 * Offset of accessed address relative to component start. Accesses must be in 9183 * accordance to log_mcda_word_size in MCQI reg. 9184 * Access: RW 9185 */ 9186 MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32); 9187 9188 /* reg_mcda_size 9189 * Size of the data accessed, given in bytes. 9190 * Access: RW 9191 */ 9192 MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16); 9193 9194 /* reg_mcda_data 9195 * Data block accessed. 9196 * Access: RW 9197 */ 9198 MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false); 9199 9200 static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle, 9201 u32 offset, u16 size, u8 *data) 9202 { 9203 int i; 9204 9205 MLXSW_REG_ZERO(mcda, payload); 9206 mlxsw_reg_mcda_update_handle_set(payload, update_handle); 9207 mlxsw_reg_mcda_offset_set(payload, offset); 9208 mlxsw_reg_mcda_size_set(payload, size); 9209 9210 for (i = 0; i < size / 4; i++) 9211 mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]); 9212 } 9213 9214 /* MPSC - Monitoring Packet Sampling Configuration Register 9215 * -------------------------------------------------------- 9216 * MPSC Register is used to configure the Packet Sampling mechanism. 9217 */ 9218 #define MLXSW_REG_MPSC_ID 0x9080 9219 #define MLXSW_REG_MPSC_LEN 0x1C 9220 9221 MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN); 9222 9223 /* reg_mpsc_local_port 9224 * Local port number 9225 * Not supported for CPU port 9226 * Access: Index 9227 */ 9228 MLXSW_ITEM32(reg, mpsc, local_port, 0x00, 16, 8); 9229 9230 /* reg_mpsc_e 9231 * Enable sampling on port local_port 9232 * Access: RW 9233 */ 9234 MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1); 9235 9236 #define MLXSW_REG_MPSC_RATE_MAX 3500000000UL 9237 9238 /* reg_mpsc_rate 9239 * Sampling rate = 1 out of rate packets (with randomization around 9240 * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX 9241 * Access: RW 9242 */ 9243 MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32); 9244 9245 static inline void mlxsw_reg_mpsc_pack(char *payload, u8 local_port, bool e, 9246 u32 rate) 9247 { 9248 MLXSW_REG_ZERO(mpsc, payload); 9249 mlxsw_reg_mpsc_local_port_set(payload, local_port); 9250 mlxsw_reg_mpsc_e_set(payload, e); 9251 mlxsw_reg_mpsc_rate_set(payload, rate); 9252 } 9253 9254 /* MGPC - Monitoring General Purpose Counter Set Register 9255 * The MGPC register retrieves and sets the General Purpose Counter Set. 9256 */ 9257 #define MLXSW_REG_MGPC_ID 0x9081 9258 #define MLXSW_REG_MGPC_LEN 0x18 9259 9260 MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN); 9261 9262 /* reg_mgpc_counter_set_type 9263 * Counter set type. 9264 * Access: OP 9265 */ 9266 MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8); 9267 9268 /* reg_mgpc_counter_index 9269 * Counter index. 9270 * Access: Index 9271 */ 9272 MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24); 9273 9274 enum mlxsw_reg_mgpc_opcode { 9275 /* Nop */ 9276 MLXSW_REG_MGPC_OPCODE_NOP = 0x00, 9277 /* Clear counters */ 9278 MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08, 9279 }; 9280 9281 /* reg_mgpc_opcode 9282 * Opcode. 9283 * Access: OP 9284 */ 9285 MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4); 9286 9287 /* reg_mgpc_byte_counter 9288 * Byte counter value. 9289 * Access: RW 9290 */ 9291 MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64); 9292 9293 /* reg_mgpc_packet_counter 9294 * Packet counter value. 9295 * Access: RW 9296 */ 9297 MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64); 9298 9299 static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index, 9300 enum mlxsw_reg_mgpc_opcode opcode, 9301 enum mlxsw_reg_flow_counter_set_type set_type) 9302 { 9303 MLXSW_REG_ZERO(mgpc, payload); 9304 mlxsw_reg_mgpc_counter_index_set(payload, counter_index); 9305 mlxsw_reg_mgpc_counter_set_type_set(payload, set_type); 9306 mlxsw_reg_mgpc_opcode_set(payload, opcode); 9307 } 9308 9309 /* MPRS - Monitoring Parsing State Register 9310 * ---------------------------------------- 9311 * The MPRS register is used for setting up the parsing for hash, 9312 * policy-engine and routing. 9313 */ 9314 #define MLXSW_REG_MPRS_ID 0x9083 9315 #define MLXSW_REG_MPRS_LEN 0x14 9316 9317 MLXSW_REG_DEFINE(mprs, MLXSW_REG_MPRS_ID, MLXSW_REG_MPRS_LEN); 9318 9319 /* reg_mprs_parsing_depth 9320 * Minimum parsing depth. 9321 * Need to enlarge parsing depth according to L3, MPLS, tunnels, ACL 9322 * rules, traps, hash, etc. Default is 96 bytes. Reserved when SwitchX-2. 9323 * Access: RW 9324 */ 9325 MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16); 9326 9327 /* reg_mprs_parsing_en 9328 * Parsing enable. 9329 * Bit 0 - Enable parsing of NVE of types VxLAN, VxLAN-GPE, GENEVE and 9330 * NVGRE. Default is enabled. Reserved when SwitchX-2. 9331 * Access: RW 9332 */ 9333 MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16); 9334 9335 /* reg_mprs_vxlan_udp_dport 9336 * VxLAN UDP destination port. 9337 * Used for identifying VxLAN packets and for dport field in 9338 * encapsulation. Default is 4789. 9339 * Access: RW 9340 */ 9341 MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16); 9342 9343 static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth, 9344 u16 vxlan_udp_dport) 9345 { 9346 MLXSW_REG_ZERO(mprs, payload); 9347 mlxsw_reg_mprs_parsing_depth_set(payload, parsing_depth); 9348 mlxsw_reg_mprs_parsing_en_set(payload, true); 9349 mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport); 9350 } 9351 9352 /* MOGCR - Monitoring Global Configuration Register 9353 * ------------------------------------------------ 9354 */ 9355 #define MLXSW_REG_MOGCR_ID 0x9086 9356 #define MLXSW_REG_MOGCR_LEN 0x20 9357 9358 MLXSW_REG_DEFINE(mogcr, MLXSW_REG_MOGCR_ID, MLXSW_REG_MOGCR_LEN); 9359 9360 /* reg_mogcr_ptp_iftc 9361 * PTP Ingress FIFO Trap Clear 9362 * The PTP_ING_FIFO trap provides MTPPTR with clr according 9363 * to this value. Default 0. 9364 * Reserved when IB switches and when SwitchX/-2, Spectrum-2 9365 * Access: RW 9366 */ 9367 MLXSW_ITEM32(reg, mogcr, ptp_iftc, 0x00, 1, 1); 9368 9369 /* reg_mogcr_ptp_eftc 9370 * PTP Egress FIFO Trap Clear 9371 * The PTP_EGR_FIFO trap provides MTPPTR with clr according 9372 * to this value. Default 0. 9373 * Reserved when IB switches and when SwitchX/-2, Spectrum-2 9374 * Access: RW 9375 */ 9376 MLXSW_ITEM32(reg, mogcr, ptp_eftc, 0x00, 0, 1); 9377 9378 /* MTPPPC - Time Precision Packet Port Configuration 9379 * ------------------------------------------------- 9380 * This register serves for configuration of which PTP messages should be 9381 * timestamped. This is a global configuration, despite the register name. 9382 * 9383 * Reserved when Spectrum-2. 9384 */ 9385 #define MLXSW_REG_MTPPPC_ID 0x9090 9386 #define MLXSW_REG_MTPPPC_LEN 0x28 9387 9388 MLXSW_REG_DEFINE(mtpppc, MLXSW_REG_MTPPPC_ID, MLXSW_REG_MTPPPC_LEN); 9389 9390 /* reg_mtpppc_ing_timestamp_message_type 9391 * Bitwise vector of PTP message types to timestamp at ingress. 9392 * MessageType field as defined by IEEE 1588 9393 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req) 9394 * Default all 0 9395 * Access: RW 9396 */ 9397 MLXSW_ITEM32(reg, mtpppc, ing_timestamp_message_type, 0x08, 0, 16); 9398 9399 /* reg_mtpppc_egr_timestamp_message_type 9400 * Bitwise vector of PTP message types to timestamp at egress. 9401 * MessageType field as defined by IEEE 1588 9402 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req) 9403 * Default all 0 9404 * Access: RW 9405 */ 9406 MLXSW_ITEM32(reg, mtpppc, egr_timestamp_message_type, 0x0C, 0, 16); 9407 9408 static inline void mlxsw_reg_mtpppc_pack(char *payload, u16 ing, u16 egr) 9409 { 9410 MLXSW_REG_ZERO(mtpppc, payload); 9411 mlxsw_reg_mtpppc_ing_timestamp_message_type_set(payload, ing); 9412 mlxsw_reg_mtpppc_egr_timestamp_message_type_set(payload, egr); 9413 } 9414 9415 /* MTPPTR - Time Precision Packet Timestamping Reading 9416 * --------------------------------------------------- 9417 * The MTPPTR is used for reading the per port PTP timestamp FIFO. 9418 * There is a trap for packets which are latched to the timestamp FIFO, thus the 9419 * SW knows which FIFO to read. Note that packets enter the FIFO before been 9420 * trapped. The sequence number is used to synchronize the timestamp FIFO 9421 * entries and the trapped packets. 9422 * Reserved when Spectrum-2. 9423 */ 9424 9425 #define MLXSW_REG_MTPPTR_ID 0x9091 9426 #define MLXSW_REG_MTPPTR_BASE_LEN 0x10 /* base length, without records */ 9427 #define MLXSW_REG_MTPPTR_REC_LEN 0x10 /* record length */ 9428 #define MLXSW_REG_MTPPTR_REC_MAX_COUNT 4 9429 #define MLXSW_REG_MTPPTR_LEN (MLXSW_REG_MTPPTR_BASE_LEN + \ 9430 MLXSW_REG_MTPPTR_REC_LEN * MLXSW_REG_MTPPTR_REC_MAX_COUNT) 9431 9432 MLXSW_REG_DEFINE(mtpptr, MLXSW_REG_MTPPTR_ID, MLXSW_REG_MTPPTR_LEN); 9433 9434 /* reg_mtpptr_local_port 9435 * Not supported for CPU port. 9436 * Access: Index 9437 */ 9438 MLXSW_ITEM32(reg, mtpptr, local_port, 0x00, 16, 8); 9439 9440 enum mlxsw_reg_mtpptr_dir { 9441 MLXSW_REG_MTPPTR_DIR_INGRESS, 9442 MLXSW_REG_MTPPTR_DIR_EGRESS, 9443 }; 9444 9445 /* reg_mtpptr_dir 9446 * Direction. 9447 * Access: Index 9448 */ 9449 MLXSW_ITEM32(reg, mtpptr, dir, 0x00, 0, 1); 9450 9451 /* reg_mtpptr_clr 9452 * Clear the records. 9453 * Access: OP 9454 */ 9455 MLXSW_ITEM32(reg, mtpptr, clr, 0x04, 31, 1); 9456 9457 /* reg_mtpptr_num_rec 9458 * Number of valid records in the response 9459 * Range 0.. cap_ptp_timestamp_fifo 9460 * Access: RO 9461 */ 9462 MLXSW_ITEM32(reg, mtpptr, num_rec, 0x08, 0, 4); 9463 9464 /* reg_mtpptr_rec_message_type 9465 * MessageType field as defined by IEEE 1588 Each bit corresponds to a value 9466 * (e.g. Bit0: Sync, Bit1: Delay_Req) 9467 * Access: RO 9468 */ 9469 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_message_type, 9470 MLXSW_REG_MTPPTR_BASE_LEN, 8, 4, 9471 MLXSW_REG_MTPPTR_REC_LEN, 0, false); 9472 9473 /* reg_mtpptr_rec_domain_number 9474 * DomainNumber field as defined by IEEE 1588 9475 * Access: RO 9476 */ 9477 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_domain_number, 9478 MLXSW_REG_MTPPTR_BASE_LEN, 0, 8, 9479 MLXSW_REG_MTPPTR_REC_LEN, 0, false); 9480 9481 /* reg_mtpptr_rec_sequence_id 9482 * SequenceId field as defined by IEEE 1588 9483 * Access: RO 9484 */ 9485 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_sequence_id, 9486 MLXSW_REG_MTPPTR_BASE_LEN, 0, 16, 9487 MLXSW_REG_MTPPTR_REC_LEN, 0x4, false); 9488 9489 /* reg_mtpptr_rec_timestamp_high 9490 * Timestamp of when the PTP packet has passed through the port Units of PLL 9491 * clock time. 9492 * For Spectrum-1 the PLL clock is 156.25Mhz and PLL clock time is 6.4nSec. 9493 * Access: RO 9494 */ 9495 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_high, 9496 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32, 9497 MLXSW_REG_MTPPTR_REC_LEN, 0x8, false); 9498 9499 /* reg_mtpptr_rec_timestamp_low 9500 * See rec_timestamp_high. 9501 * Access: RO 9502 */ 9503 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_low, 9504 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32, 9505 MLXSW_REG_MTPPTR_REC_LEN, 0xC, false); 9506 9507 static inline void mlxsw_reg_mtpptr_unpack(const char *payload, 9508 unsigned int rec, 9509 u8 *p_message_type, 9510 u8 *p_domain_number, 9511 u16 *p_sequence_id, 9512 u64 *p_timestamp) 9513 { 9514 u32 timestamp_high, timestamp_low; 9515 9516 *p_message_type = mlxsw_reg_mtpptr_rec_message_type_get(payload, rec); 9517 *p_domain_number = mlxsw_reg_mtpptr_rec_domain_number_get(payload, rec); 9518 *p_sequence_id = mlxsw_reg_mtpptr_rec_sequence_id_get(payload, rec); 9519 timestamp_high = mlxsw_reg_mtpptr_rec_timestamp_high_get(payload, rec); 9520 timestamp_low = mlxsw_reg_mtpptr_rec_timestamp_low_get(payload, rec); 9521 *p_timestamp = (u64)timestamp_high << 32 | timestamp_low; 9522 } 9523 9524 /* MTPTPT - Monitoring Precision Time Protocol Trap Register 9525 * --------------------------------------------------------- 9526 * This register is used for configuring under which trap to deliver PTP 9527 * packets depending on type of the packet. 9528 */ 9529 #define MLXSW_REG_MTPTPT_ID 0x9092 9530 #define MLXSW_REG_MTPTPT_LEN 0x08 9531 9532 MLXSW_REG_DEFINE(mtptpt, MLXSW_REG_MTPTPT_ID, MLXSW_REG_MTPTPT_LEN); 9533 9534 enum mlxsw_reg_mtptpt_trap_id { 9535 MLXSW_REG_MTPTPT_TRAP_ID_PTP0, 9536 MLXSW_REG_MTPTPT_TRAP_ID_PTP1, 9537 }; 9538 9539 /* reg_mtptpt_trap_id 9540 * Trap id. 9541 * Access: Index 9542 */ 9543 MLXSW_ITEM32(reg, mtptpt, trap_id, 0x00, 0, 4); 9544 9545 /* reg_mtptpt_message_type 9546 * Bitwise vector of PTP message types to trap. This is a necessary but 9547 * non-sufficient condition since need to enable also per port. See MTPPPC. 9548 * Message types are defined by IEEE 1588 Each bit corresponds to a value (e.g. 9549 * Bit0: Sync, Bit1: Delay_Req) 9550 */ 9551 MLXSW_ITEM32(reg, mtptpt, message_type, 0x04, 0, 16); 9552 9553 static inline void mlxsw_reg_mtptptp_pack(char *payload, 9554 enum mlxsw_reg_mtptpt_trap_id trap_id, 9555 u16 message_type) 9556 { 9557 MLXSW_REG_ZERO(mtptpt, payload); 9558 mlxsw_reg_mtptpt_trap_id_set(payload, trap_id); 9559 mlxsw_reg_mtptpt_message_type_set(payload, message_type); 9560 } 9561 9562 /* MGPIR - Management General Peripheral Information Register 9563 * ---------------------------------------------------------- 9564 * MGPIR register allows software to query the hardware and 9565 * firmware general information of peripheral entities. 9566 */ 9567 #define MLXSW_REG_MGPIR_ID 0x9100 9568 #define MLXSW_REG_MGPIR_LEN 0xA0 9569 9570 MLXSW_REG_DEFINE(mgpir, MLXSW_REG_MGPIR_ID, MLXSW_REG_MGPIR_LEN); 9571 9572 enum mlxsw_reg_mgpir_device_type { 9573 MLXSW_REG_MGPIR_DEVICE_TYPE_NONE, 9574 MLXSW_REG_MGPIR_DEVICE_TYPE_GEARBOX_DIE, 9575 }; 9576 9577 /* device_type 9578 * Access: RO 9579 */ 9580 MLXSW_ITEM32(reg, mgpir, device_type, 0x00, 24, 4); 9581 9582 /* devices_per_flash 9583 * Number of devices of device_type per flash (can be shared by few devices). 9584 * Access: RO 9585 */ 9586 MLXSW_ITEM32(reg, mgpir, devices_per_flash, 0x00, 16, 8); 9587 9588 /* num_of_devices 9589 * Number of devices of device_type. 9590 * Access: RO 9591 */ 9592 MLXSW_ITEM32(reg, mgpir, num_of_devices, 0x00, 0, 8); 9593 9594 /* num_of_modules 9595 * Number of modules. 9596 * Access: RO 9597 */ 9598 MLXSW_ITEM32(reg, mgpir, num_of_modules, 0x04, 0, 8); 9599 9600 static inline void mlxsw_reg_mgpir_pack(char *payload) 9601 { 9602 MLXSW_REG_ZERO(mgpir, payload); 9603 } 9604 9605 static inline void 9606 mlxsw_reg_mgpir_unpack(char *payload, u8 *num_of_devices, 9607 enum mlxsw_reg_mgpir_device_type *device_type, 9608 u8 *devices_per_flash, u8 *num_of_modules) 9609 { 9610 if (num_of_devices) 9611 *num_of_devices = mlxsw_reg_mgpir_num_of_devices_get(payload); 9612 if (device_type) 9613 *device_type = mlxsw_reg_mgpir_device_type_get(payload); 9614 if (devices_per_flash) 9615 *devices_per_flash = 9616 mlxsw_reg_mgpir_devices_per_flash_get(payload); 9617 if (num_of_modules) 9618 *num_of_modules = mlxsw_reg_mgpir_num_of_modules_get(payload); 9619 } 9620 9621 /* TNGCR - Tunneling NVE General Configuration Register 9622 * ---------------------------------------------------- 9623 * The TNGCR register is used for setting up the NVE Tunneling configuration. 9624 */ 9625 #define MLXSW_REG_TNGCR_ID 0xA001 9626 #define MLXSW_REG_TNGCR_LEN 0x44 9627 9628 MLXSW_REG_DEFINE(tngcr, MLXSW_REG_TNGCR_ID, MLXSW_REG_TNGCR_LEN); 9629 9630 enum mlxsw_reg_tngcr_type { 9631 MLXSW_REG_TNGCR_TYPE_VXLAN, 9632 MLXSW_REG_TNGCR_TYPE_VXLAN_GPE, 9633 MLXSW_REG_TNGCR_TYPE_GENEVE, 9634 MLXSW_REG_TNGCR_TYPE_NVGRE, 9635 }; 9636 9637 /* reg_tngcr_type 9638 * Tunnel type for encapsulation and decapsulation. The types are mutually 9639 * exclusive. 9640 * Note: For Spectrum the NVE parsing must be enabled in MPRS. 9641 * Access: RW 9642 */ 9643 MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4); 9644 9645 /* reg_tngcr_nve_valid 9646 * The VTEP is valid. Allows adding FDB entries for tunnel encapsulation. 9647 * Access: RW 9648 */ 9649 MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1); 9650 9651 /* reg_tngcr_nve_ttl_uc 9652 * The TTL for NVE tunnel encapsulation underlay unicast packets. 9653 * Access: RW 9654 */ 9655 MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8); 9656 9657 /* reg_tngcr_nve_ttl_mc 9658 * The TTL for NVE tunnel encapsulation underlay multicast packets. 9659 * Access: RW 9660 */ 9661 MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8); 9662 9663 enum { 9664 /* Do not copy flow label. Calculate flow label using nve_flh. */ 9665 MLXSW_REG_TNGCR_FL_NO_COPY, 9666 /* Copy flow label from inner packet if packet is IPv6 and 9667 * encapsulation is by IPv6. Otherwise, calculate flow label using 9668 * nve_flh. 9669 */ 9670 MLXSW_REG_TNGCR_FL_COPY, 9671 }; 9672 9673 /* reg_tngcr_nve_flc 9674 * For NVE tunnel encapsulation: Flow label copy from inner packet. 9675 * Access: RW 9676 */ 9677 MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1); 9678 9679 enum { 9680 /* Flow label is static. In Spectrum this means '0'. Spectrum-2 9681 * uses {nve_fl_prefix, nve_fl_suffix}. 9682 */ 9683 MLXSW_REG_TNGCR_FL_NO_HASH, 9684 /* 8 LSBs of the flow label are calculated from ECMP hash of the 9685 * inner packet. 12 MSBs are configured by nve_fl_prefix. 9686 */ 9687 MLXSW_REG_TNGCR_FL_HASH, 9688 }; 9689 9690 /* reg_tngcr_nve_flh 9691 * NVE flow label hash. 9692 * Access: RW 9693 */ 9694 MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1); 9695 9696 /* reg_tngcr_nve_fl_prefix 9697 * NVE flow label prefix. Constant 12 MSBs of the flow label. 9698 * Access: RW 9699 */ 9700 MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12); 9701 9702 /* reg_tngcr_nve_fl_suffix 9703 * NVE flow label suffix. Constant 8 LSBs of the flow label. 9704 * Reserved when nve_flh=1 and for Spectrum. 9705 * Access: RW 9706 */ 9707 MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8); 9708 9709 enum { 9710 /* Source UDP port is fixed (default '0') */ 9711 MLXSW_REG_TNGCR_UDP_SPORT_NO_HASH, 9712 /* Source UDP port is calculated based on hash */ 9713 MLXSW_REG_TNGCR_UDP_SPORT_HASH, 9714 }; 9715 9716 /* reg_tngcr_nve_udp_sport_type 9717 * NVE UDP source port type. 9718 * Spectrum uses LAG hash (SLCRv2). Spectrum-2 uses ECMP hash (RECRv2). 9719 * When the source UDP port is calculated based on hash, then the 8 LSBs 9720 * are calculated from hash the 8 MSBs are configured by 9721 * nve_udp_sport_prefix. 9722 * Access: RW 9723 */ 9724 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1); 9725 9726 /* reg_tngcr_nve_udp_sport_prefix 9727 * NVE UDP source port prefix. Constant 8 MSBs of the UDP source port. 9728 * Reserved when NVE type is NVGRE. 9729 * Access: RW 9730 */ 9731 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8); 9732 9733 /* reg_tngcr_nve_group_size_mc 9734 * The amount of sequential linked lists of MC entries. The first linked 9735 * list is configured by SFD.underlay_mc_ptr. 9736 * Valid values: 1, 2, 4, 8, 16, 32, 64 9737 * The linked list are configured by TNUMT. 9738 * The hash is set by LAG hash. 9739 * Access: RW 9740 */ 9741 MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8); 9742 9743 /* reg_tngcr_nve_group_size_flood 9744 * The amount of sequential linked lists of flooding entries. The first 9745 * linked list is configured by SFMR.nve_tunnel_flood_ptr 9746 * Valid values: 1, 2, 4, 8, 16, 32, 64 9747 * The linked list are configured by TNUMT. 9748 * The hash is set by LAG hash. 9749 * Access: RW 9750 */ 9751 MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8); 9752 9753 /* reg_tngcr_learn_enable 9754 * During decapsulation, whether to learn from NVE port. 9755 * Reserved when Spectrum-2. See TNPC. 9756 * Access: RW 9757 */ 9758 MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1); 9759 9760 /* reg_tngcr_underlay_virtual_router 9761 * Underlay virtual router. 9762 * Reserved when Spectrum-2. 9763 * Access: RW 9764 */ 9765 MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16); 9766 9767 /* reg_tngcr_underlay_rif 9768 * Underlay ingress router interface. RIF type should be loopback generic. 9769 * Reserved when Spectrum. 9770 * Access: RW 9771 */ 9772 MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16); 9773 9774 /* reg_tngcr_usipv4 9775 * Underlay source IPv4 address of the NVE. 9776 * Access: RW 9777 */ 9778 MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32); 9779 9780 /* reg_tngcr_usipv6 9781 * Underlay source IPv6 address of the NVE. For Spectrum, must not be 9782 * modified under traffic of NVE tunneling encapsulation. 9783 * Access: RW 9784 */ 9785 MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16); 9786 9787 static inline void mlxsw_reg_tngcr_pack(char *payload, 9788 enum mlxsw_reg_tngcr_type type, 9789 bool valid, u8 ttl) 9790 { 9791 MLXSW_REG_ZERO(tngcr, payload); 9792 mlxsw_reg_tngcr_type_set(payload, type); 9793 mlxsw_reg_tngcr_nve_valid_set(payload, valid); 9794 mlxsw_reg_tngcr_nve_ttl_uc_set(payload, ttl); 9795 mlxsw_reg_tngcr_nve_ttl_mc_set(payload, ttl); 9796 mlxsw_reg_tngcr_nve_flc_set(payload, MLXSW_REG_TNGCR_FL_NO_COPY); 9797 mlxsw_reg_tngcr_nve_flh_set(payload, 0); 9798 mlxsw_reg_tngcr_nve_udp_sport_type_set(payload, 9799 MLXSW_REG_TNGCR_UDP_SPORT_HASH); 9800 mlxsw_reg_tngcr_nve_udp_sport_prefix_set(payload, 0); 9801 mlxsw_reg_tngcr_nve_group_size_mc_set(payload, 1); 9802 mlxsw_reg_tngcr_nve_group_size_flood_set(payload, 1); 9803 } 9804 9805 /* TNUMT - Tunneling NVE Underlay Multicast Table Register 9806 * ------------------------------------------------------- 9807 * The TNUMT register is for building the underlay MC table. It is used 9808 * for MC, flooding and BC traffic into the NVE tunnel. 9809 */ 9810 #define MLXSW_REG_TNUMT_ID 0xA003 9811 #define MLXSW_REG_TNUMT_LEN 0x20 9812 9813 MLXSW_REG_DEFINE(tnumt, MLXSW_REG_TNUMT_ID, MLXSW_REG_TNUMT_LEN); 9814 9815 enum mlxsw_reg_tnumt_record_type { 9816 MLXSW_REG_TNUMT_RECORD_TYPE_IPV4, 9817 MLXSW_REG_TNUMT_RECORD_TYPE_IPV6, 9818 MLXSW_REG_TNUMT_RECORD_TYPE_LABEL, 9819 }; 9820 9821 /* reg_tnumt_record_type 9822 * Record type. 9823 * Access: RW 9824 */ 9825 MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4); 9826 9827 enum mlxsw_reg_tnumt_tunnel_port { 9828 MLXSW_REG_TNUMT_TUNNEL_PORT_NVE, 9829 MLXSW_REG_TNUMT_TUNNEL_PORT_VPLS, 9830 MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL0, 9831 MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL1, 9832 }; 9833 9834 /* reg_tnumt_tunnel_port 9835 * Tunnel port. 9836 * Access: RW 9837 */ 9838 MLXSW_ITEM32(reg, tnumt, tunnel_port, 0x00, 24, 4); 9839 9840 /* reg_tnumt_underlay_mc_ptr 9841 * Index to the underlay multicast table. 9842 * For Spectrum the index is to the KVD linear. 9843 * Access: Index 9844 */ 9845 MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24); 9846 9847 /* reg_tnumt_vnext 9848 * The next_underlay_mc_ptr is valid. 9849 * Access: RW 9850 */ 9851 MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1); 9852 9853 /* reg_tnumt_next_underlay_mc_ptr 9854 * The next index to the underlay multicast table. 9855 * Access: RW 9856 */ 9857 MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24); 9858 9859 /* reg_tnumt_record_size 9860 * Number of IP addresses in the record. 9861 * Range is 1..cap_max_nve_mc_entries_ipv{4,6} 9862 * Access: RW 9863 */ 9864 MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3); 9865 9866 /* reg_tnumt_udip 9867 * The underlay IPv4 addresses. udip[i] is reserved if i >= size 9868 * Access: RW 9869 */ 9870 MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false); 9871 9872 /* reg_tnumt_udip_ptr 9873 * The pointer to the underlay IPv6 addresses. udip_ptr[i] is reserved if 9874 * i >= size. The IPv6 addresses are configured by RIPS. 9875 * Access: RW 9876 */ 9877 MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false); 9878 9879 static inline void mlxsw_reg_tnumt_pack(char *payload, 9880 enum mlxsw_reg_tnumt_record_type type, 9881 enum mlxsw_reg_tnumt_tunnel_port tport, 9882 u32 underlay_mc_ptr, bool vnext, 9883 u32 next_underlay_mc_ptr, 9884 u8 record_size) 9885 { 9886 MLXSW_REG_ZERO(tnumt, payload); 9887 mlxsw_reg_tnumt_record_type_set(payload, type); 9888 mlxsw_reg_tnumt_tunnel_port_set(payload, tport); 9889 mlxsw_reg_tnumt_underlay_mc_ptr_set(payload, underlay_mc_ptr); 9890 mlxsw_reg_tnumt_vnext_set(payload, vnext); 9891 mlxsw_reg_tnumt_next_underlay_mc_ptr_set(payload, next_underlay_mc_ptr); 9892 mlxsw_reg_tnumt_record_size_set(payload, record_size); 9893 } 9894 9895 /* TNQCR - Tunneling NVE QoS Configuration Register 9896 * ------------------------------------------------ 9897 * The TNQCR register configures how QoS is set in encapsulation into the 9898 * underlay network. 9899 */ 9900 #define MLXSW_REG_TNQCR_ID 0xA010 9901 #define MLXSW_REG_TNQCR_LEN 0x0C 9902 9903 MLXSW_REG_DEFINE(tnqcr, MLXSW_REG_TNQCR_ID, MLXSW_REG_TNQCR_LEN); 9904 9905 /* reg_tnqcr_enc_set_dscp 9906 * For encapsulation: How to set DSCP field: 9907 * 0 - Copy the DSCP from the overlay (inner) IP header to the underlay 9908 * (outer) IP header. If there is no IP header, use TNQDR.dscp 9909 * 1 - Set the DSCP field as TNQDR.dscp 9910 * Access: RW 9911 */ 9912 MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1); 9913 9914 static inline void mlxsw_reg_tnqcr_pack(char *payload) 9915 { 9916 MLXSW_REG_ZERO(tnqcr, payload); 9917 mlxsw_reg_tnqcr_enc_set_dscp_set(payload, 0); 9918 } 9919 9920 /* TNQDR - Tunneling NVE QoS Default Register 9921 * ------------------------------------------ 9922 * The TNQDR register configures the default QoS settings for NVE 9923 * encapsulation. 9924 */ 9925 #define MLXSW_REG_TNQDR_ID 0xA011 9926 #define MLXSW_REG_TNQDR_LEN 0x08 9927 9928 MLXSW_REG_DEFINE(tnqdr, MLXSW_REG_TNQDR_ID, MLXSW_REG_TNQDR_LEN); 9929 9930 /* reg_tnqdr_local_port 9931 * Local port number (receive port). CPU port is supported. 9932 * Access: Index 9933 */ 9934 MLXSW_ITEM32(reg, tnqdr, local_port, 0x00, 16, 8); 9935 9936 /* reg_tnqdr_dscp 9937 * For encapsulation, the default DSCP. 9938 * Access: RW 9939 */ 9940 MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6); 9941 9942 static inline void mlxsw_reg_tnqdr_pack(char *payload, u8 local_port) 9943 { 9944 MLXSW_REG_ZERO(tnqdr, payload); 9945 mlxsw_reg_tnqdr_local_port_set(payload, local_port); 9946 mlxsw_reg_tnqdr_dscp_set(payload, 0); 9947 } 9948 9949 /* TNEEM - Tunneling NVE Encapsulation ECN Mapping Register 9950 * -------------------------------------------------------- 9951 * The TNEEM register maps ECN of the IP header at the ingress to the 9952 * encapsulation to the ECN of the underlay network. 9953 */ 9954 #define MLXSW_REG_TNEEM_ID 0xA012 9955 #define MLXSW_REG_TNEEM_LEN 0x0C 9956 9957 MLXSW_REG_DEFINE(tneem, MLXSW_REG_TNEEM_ID, MLXSW_REG_TNEEM_LEN); 9958 9959 /* reg_tneem_overlay_ecn 9960 * ECN of the IP header in the overlay network. 9961 * Access: Index 9962 */ 9963 MLXSW_ITEM32(reg, tneem, overlay_ecn, 0x04, 24, 2); 9964 9965 /* reg_tneem_underlay_ecn 9966 * ECN of the IP header in the underlay network. 9967 * Access: RW 9968 */ 9969 MLXSW_ITEM32(reg, tneem, underlay_ecn, 0x04, 16, 2); 9970 9971 static inline void mlxsw_reg_tneem_pack(char *payload, u8 overlay_ecn, 9972 u8 underlay_ecn) 9973 { 9974 MLXSW_REG_ZERO(tneem, payload); 9975 mlxsw_reg_tneem_overlay_ecn_set(payload, overlay_ecn); 9976 mlxsw_reg_tneem_underlay_ecn_set(payload, underlay_ecn); 9977 } 9978 9979 /* TNDEM - Tunneling NVE Decapsulation ECN Mapping Register 9980 * -------------------------------------------------------- 9981 * The TNDEM register configures the actions that are done in the 9982 * decapsulation. 9983 */ 9984 #define MLXSW_REG_TNDEM_ID 0xA013 9985 #define MLXSW_REG_TNDEM_LEN 0x0C 9986 9987 MLXSW_REG_DEFINE(tndem, MLXSW_REG_TNDEM_ID, MLXSW_REG_TNDEM_LEN); 9988 9989 /* reg_tndem_underlay_ecn 9990 * ECN field of the IP header in the underlay network. 9991 * Access: Index 9992 */ 9993 MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2); 9994 9995 /* reg_tndem_overlay_ecn 9996 * ECN field of the IP header in the overlay network. 9997 * Access: Index 9998 */ 9999 MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2); 10000 10001 /* reg_tndem_eip_ecn 10002 * Egress IP ECN. ECN field of the IP header of the packet which goes out 10003 * from the decapsulation. 10004 * Access: RW 10005 */ 10006 MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2); 10007 10008 /* reg_tndem_trap_en 10009 * Trap enable: 10010 * 0 - No trap due to decap ECN 10011 * 1 - Trap enable with trap_id 10012 * Access: RW 10013 */ 10014 MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4); 10015 10016 /* reg_tndem_trap_id 10017 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 10018 * Reserved when trap_en is '0'. 10019 * Access: RW 10020 */ 10021 MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9); 10022 10023 static inline void mlxsw_reg_tndem_pack(char *payload, u8 underlay_ecn, 10024 u8 overlay_ecn, u8 ecn, bool trap_en, 10025 u16 trap_id) 10026 { 10027 MLXSW_REG_ZERO(tndem, payload); 10028 mlxsw_reg_tndem_underlay_ecn_set(payload, underlay_ecn); 10029 mlxsw_reg_tndem_overlay_ecn_set(payload, overlay_ecn); 10030 mlxsw_reg_tndem_eip_ecn_set(payload, ecn); 10031 mlxsw_reg_tndem_trap_en_set(payload, trap_en); 10032 mlxsw_reg_tndem_trap_id_set(payload, trap_id); 10033 } 10034 10035 /* TNPC - Tunnel Port Configuration Register 10036 * ----------------------------------------- 10037 * The TNPC register is used for tunnel port configuration. 10038 * Reserved when Spectrum. 10039 */ 10040 #define MLXSW_REG_TNPC_ID 0xA020 10041 #define MLXSW_REG_TNPC_LEN 0x18 10042 10043 MLXSW_REG_DEFINE(tnpc, MLXSW_REG_TNPC_ID, MLXSW_REG_TNPC_LEN); 10044 10045 enum mlxsw_reg_tnpc_tunnel_port { 10046 MLXSW_REG_TNPC_TUNNEL_PORT_NVE, 10047 MLXSW_REG_TNPC_TUNNEL_PORT_VPLS, 10048 MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL0, 10049 MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL1, 10050 }; 10051 10052 /* reg_tnpc_tunnel_port 10053 * Tunnel port. 10054 * Access: Index 10055 */ 10056 MLXSW_ITEM32(reg, tnpc, tunnel_port, 0x00, 0, 4); 10057 10058 /* reg_tnpc_learn_enable_v6 10059 * During IPv6 underlay decapsulation, whether to learn from tunnel port. 10060 * Access: RW 10061 */ 10062 MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1); 10063 10064 /* reg_tnpc_learn_enable_v4 10065 * During IPv4 underlay decapsulation, whether to learn from tunnel port. 10066 * Access: RW 10067 */ 10068 MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1); 10069 10070 static inline void mlxsw_reg_tnpc_pack(char *payload, 10071 enum mlxsw_reg_tnpc_tunnel_port tport, 10072 bool learn_enable) 10073 { 10074 MLXSW_REG_ZERO(tnpc, payload); 10075 mlxsw_reg_tnpc_tunnel_port_set(payload, tport); 10076 mlxsw_reg_tnpc_learn_enable_v4_set(payload, learn_enable); 10077 mlxsw_reg_tnpc_learn_enable_v6_set(payload, learn_enable); 10078 } 10079 10080 /* TIGCR - Tunneling IPinIP General Configuration Register 10081 * ------------------------------------------------------- 10082 * The TIGCR register is used for setting up the IPinIP Tunnel configuration. 10083 */ 10084 #define MLXSW_REG_TIGCR_ID 0xA801 10085 #define MLXSW_REG_TIGCR_LEN 0x10 10086 10087 MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN); 10088 10089 /* reg_tigcr_ipip_ttlc 10090 * For IPinIP Tunnel encapsulation: whether to copy the ttl from the packet 10091 * header. 10092 * Access: RW 10093 */ 10094 MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1); 10095 10096 /* reg_tigcr_ipip_ttl_uc 10097 * The TTL for IPinIP Tunnel encapsulation of unicast packets if 10098 * reg_tigcr_ipip_ttlc is unset. 10099 * Access: RW 10100 */ 10101 MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8); 10102 10103 static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc) 10104 { 10105 MLXSW_REG_ZERO(tigcr, payload); 10106 mlxsw_reg_tigcr_ttlc_set(payload, ttlc); 10107 mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc); 10108 } 10109 10110 /* SBPR - Shared Buffer Pools Register 10111 * ----------------------------------- 10112 * The SBPR configures and retrieves the shared buffer pools and configuration. 10113 */ 10114 #define MLXSW_REG_SBPR_ID 0xB001 10115 #define MLXSW_REG_SBPR_LEN 0x14 10116 10117 MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN); 10118 10119 /* shared direstion enum for SBPR, SBCM, SBPM */ 10120 enum mlxsw_reg_sbxx_dir { 10121 MLXSW_REG_SBXX_DIR_INGRESS, 10122 MLXSW_REG_SBXX_DIR_EGRESS, 10123 }; 10124 10125 /* reg_sbpr_dir 10126 * Direction. 10127 * Access: Index 10128 */ 10129 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2); 10130 10131 /* reg_sbpr_pool 10132 * Pool index. 10133 * Access: Index 10134 */ 10135 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4); 10136 10137 /* reg_sbpr_infi_size 10138 * Size is infinite. 10139 * Access: RW 10140 */ 10141 MLXSW_ITEM32(reg, sbpr, infi_size, 0x04, 31, 1); 10142 10143 /* reg_sbpr_size 10144 * Pool size in buffer cells. 10145 * Reserved when infi_size = 1. 10146 * Access: RW 10147 */ 10148 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24); 10149 10150 enum mlxsw_reg_sbpr_mode { 10151 MLXSW_REG_SBPR_MODE_STATIC, 10152 MLXSW_REG_SBPR_MODE_DYNAMIC, 10153 }; 10154 10155 /* reg_sbpr_mode 10156 * Pool quota calculation mode. 10157 * Access: RW 10158 */ 10159 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4); 10160 10161 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool, 10162 enum mlxsw_reg_sbxx_dir dir, 10163 enum mlxsw_reg_sbpr_mode mode, u32 size, 10164 bool infi_size) 10165 { 10166 MLXSW_REG_ZERO(sbpr, payload); 10167 mlxsw_reg_sbpr_pool_set(payload, pool); 10168 mlxsw_reg_sbpr_dir_set(payload, dir); 10169 mlxsw_reg_sbpr_mode_set(payload, mode); 10170 mlxsw_reg_sbpr_size_set(payload, size); 10171 mlxsw_reg_sbpr_infi_size_set(payload, infi_size); 10172 } 10173 10174 /* SBCM - Shared Buffer Class Management Register 10175 * ---------------------------------------------- 10176 * The SBCM register configures and retrieves the shared buffer allocation 10177 * and configuration according to Port-PG, including the binding to pool 10178 * and definition of the associated quota. 10179 */ 10180 #define MLXSW_REG_SBCM_ID 0xB002 10181 #define MLXSW_REG_SBCM_LEN 0x28 10182 10183 MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN); 10184 10185 /* reg_sbcm_local_port 10186 * Local port number. 10187 * For Ingress: excludes CPU port and Router port 10188 * For Egress: excludes IP Router 10189 * Access: Index 10190 */ 10191 MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8); 10192 10193 /* reg_sbcm_pg_buff 10194 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress) 10195 * For PG buffer: range is 0..cap_max_pg_buffers - 1 10196 * For traffic class: range is 0..cap_max_tclass - 1 10197 * Note that when traffic class is in MC aware mode then the traffic 10198 * classes which are MC aware cannot be configured. 10199 * Access: Index 10200 */ 10201 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6); 10202 10203 /* reg_sbcm_dir 10204 * Direction. 10205 * Access: Index 10206 */ 10207 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2); 10208 10209 /* reg_sbcm_min_buff 10210 * Minimum buffer size for the limiter, in cells. 10211 * Access: RW 10212 */ 10213 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24); 10214 10215 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */ 10216 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1 10217 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14 10218 10219 /* reg_sbcm_infi_max 10220 * Max buffer is infinite. 10221 * Access: RW 10222 */ 10223 MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1); 10224 10225 /* reg_sbcm_max_buff 10226 * When the pool associated to the port-pg/tclass is configured to 10227 * static, Maximum buffer size for the limiter configured in cells. 10228 * When the pool associated to the port-pg/tclass is configured to 10229 * dynamic, the max_buff holds the "alpha" parameter, supporting 10230 * the following values: 10231 * 0: 0 10232 * i: (1/128)*2^(i-1), for i=1..14 10233 * 0xFF: Infinity 10234 * Reserved when infi_max = 1. 10235 * Access: RW 10236 */ 10237 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24); 10238 10239 /* reg_sbcm_pool 10240 * Association of the port-priority to a pool. 10241 * Access: RW 10242 */ 10243 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4); 10244 10245 static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff, 10246 enum mlxsw_reg_sbxx_dir dir, 10247 u32 min_buff, u32 max_buff, 10248 bool infi_max, u8 pool) 10249 { 10250 MLXSW_REG_ZERO(sbcm, payload); 10251 mlxsw_reg_sbcm_local_port_set(payload, local_port); 10252 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff); 10253 mlxsw_reg_sbcm_dir_set(payload, dir); 10254 mlxsw_reg_sbcm_min_buff_set(payload, min_buff); 10255 mlxsw_reg_sbcm_max_buff_set(payload, max_buff); 10256 mlxsw_reg_sbcm_infi_max_set(payload, infi_max); 10257 mlxsw_reg_sbcm_pool_set(payload, pool); 10258 } 10259 10260 /* SBPM - Shared Buffer Port Management Register 10261 * --------------------------------------------- 10262 * The SBPM register configures and retrieves the shared buffer allocation 10263 * and configuration according to Port-Pool, including the definition 10264 * of the associated quota. 10265 */ 10266 #define MLXSW_REG_SBPM_ID 0xB003 10267 #define MLXSW_REG_SBPM_LEN 0x28 10268 10269 MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN); 10270 10271 /* reg_sbpm_local_port 10272 * Local port number. 10273 * For Ingress: excludes CPU port and Router port 10274 * For Egress: excludes IP Router 10275 * Access: Index 10276 */ 10277 MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8); 10278 10279 /* reg_sbpm_pool 10280 * The pool associated to quota counting on the local_port. 10281 * Access: Index 10282 */ 10283 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4); 10284 10285 /* reg_sbpm_dir 10286 * Direction. 10287 * Access: Index 10288 */ 10289 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2); 10290 10291 /* reg_sbpm_buff_occupancy 10292 * Current buffer occupancy in cells. 10293 * Access: RO 10294 */ 10295 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24); 10296 10297 /* reg_sbpm_clr 10298 * Clear Max Buffer Occupancy 10299 * When this bit is set, max_buff_occupancy field is cleared (and a 10300 * new max value is tracked from the time the clear was performed). 10301 * Access: OP 10302 */ 10303 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1); 10304 10305 /* reg_sbpm_max_buff_occupancy 10306 * Maximum value of buffer occupancy in cells monitored. Cleared by 10307 * writing to the clr field. 10308 * Access: RO 10309 */ 10310 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24); 10311 10312 /* reg_sbpm_min_buff 10313 * Minimum buffer size for the limiter, in cells. 10314 * Access: RW 10315 */ 10316 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24); 10317 10318 /* reg_sbpm_max_buff 10319 * When the pool associated to the port-pg/tclass is configured to 10320 * static, Maximum buffer size for the limiter configured in cells. 10321 * When the pool associated to the port-pg/tclass is configured to 10322 * dynamic, the max_buff holds the "alpha" parameter, supporting 10323 * the following values: 10324 * 0: 0 10325 * i: (1/128)*2^(i-1), for i=1..14 10326 * 0xFF: Infinity 10327 * Access: RW 10328 */ 10329 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24); 10330 10331 static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool, 10332 enum mlxsw_reg_sbxx_dir dir, bool clr, 10333 u32 min_buff, u32 max_buff) 10334 { 10335 MLXSW_REG_ZERO(sbpm, payload); 10336 mlxsw_reg_sbpm_local_port_set(payload, local_port); 10337 mlxsw_reg_sbpm_pool_set(payload, pool); 10338 mlxsw_reg_sbpm_dir_set(payload, dir); 10339 mlxsw_reg_sbpm_clr_set(payload, clr); 10340 mlxsw_reg_sbpm_min_buff_set(payload, min_buff); 10341 mlxsw_reg_sbpm_max_buff_set(payload, max_buff); 10342 } 10343 10344 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy, 10345 u32 *p_max_buff_occupancy) 10346 { 10347 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload); 10348 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload); 10349 } 10350 10351 /* SBMM - Shared Buffer Multicast Management Register 10352 * -------------------------------------------------- 10353 * The SBMM register configures and retrieves the shared buffer allocation 10354 * and configuration for MC packets according to Switch-Priority, including 10355 * the binding to pool and definition of the associated quota. 10356 */ 10357 #define MLXSW_REG_SBMM_ID 0xB004 10358 #define MLXSW_REG_SBMM_LEN 0x28 10359 10360 MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN); 10361 10362 /* reg_sbmm_prio 10363 * Switch Priority. 10364 * Access: Index 10365 */ 10366 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4); 10367 10368 /* reg_sbmm_min_buff 10369 * Minimum buffer size for the limiter, in cells. 10370 * Access: RW 10371 */ 10372 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24); 10373 10374 /* reg_sbmm_max_buff 10375 * When the pool associated to the port-pg/tclass is configured to 10376 * static, Maximum buffer size for the limiter configured in cells. 10377 * When the pool associated to the port-pg/tclass is configured to 10378 * dynamic, the max_buff holds the "alpha" parameter, supporting 10379 * the following values: 10380 * 0: 0 10381 * i: (1/128)*2^(i-1), for i=1..14 10382 * 0xFF: Infinity 10383 * Access: RW 10384 */ 10385 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24); 10386 10387 /* reg_sbmm_pool 10388 * Association of the port-priority to a pool. 10389 * Access: RW 10390 */ 10391 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4); 10392 10393 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff, 10394 u32 max_buff, u8 pool) 10395 { 10396 MLXSW_REG_ZERO(sbmm, payload); 10397 mlxsw_reg_sbmm_prio_set(payload, prio); 10398 mlxsw_reg_sbmm_min_buff_set(payload, min_buff); 10399 mlxsw_reg_sbmm_max_buff_set(payload, max_buff); 10400 mlxsw_reg_sbmm_pool_set(payload, pool); 10401 } 10402 10403 /* SBSR - Shared Buffer Status Register 10404 * ------------------------------------ 10405 * The SBSR register retrieves the shared buffer occupancy according to 10406 * Port-Pool. Note that this register enables reading a large amount of data. 10407 * It is the user's responsibility to limit the amount of data to ensure the 10408 * response can match the maximum transfer unit. In case the response exceeds 10409 * the maximum transport unit, it will be truncated with no special notice. 10410 */ 10411 #define MLXSW_REG_SBSR_ID 0xB005 10412 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */ 10413 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */ 10414 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120 10415 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \ 10416 MLXSW_REG_SBSR_REC_LEN * \ 10417 MLXSW_REG_SBSR_REC_MAX_COUNT) 10418 10419 MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN); 10420 10421 /* reg_sbsr_clr 10422 * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy 10423 * field is cleared (and a new max value is tracked from the time the clear 10424 * was performed). 10425 * Access: OP 10426 */ 10427 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1); 10428 10429 /* reg_sbsr_ingress_port_mask 10430 * Bit vector for all ingress network ports. 10431 * Indicates which of the ports (for which the relevant bit is set) 10432 * are affected by the set operation. Configuration of any other port 10433 * does not change. 10434 * Access: Index 10435 */ 10436 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1); 10437 10438 /* reg_sbsr_pg_buff_mask 10439 * Bit vector for all switch priority groups. 10440 * Indicates which of the priorities (for which the relevant bit is set) 10441 * are affected by the set operation. Configuration of any other priority 10442 * does not change. 10443 * Range is 0..cap_max_pg_buffers - 1 10444 * Access: Index 10445 */ 10446 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1); 10447 10448 /* reg_sbsr_egress_port_mask 10449 * Bit vector for all egress network ports. 10450 * Indicates which of the ports (for which the relevant bit is set) 10451 * are affected by the set operation. Configuration of any other port 10452 * does not change. 10453 * Access: Index 10454 */ 10455 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1); 10456 10457 /* reg_sbsr_tclass_mask 10458 * Bit vector for all traffic classes. 10459 * Indicates which of the traffic classes (for which the relevant bit is 10460 * set) are affected by the set operation. Configuration of any other 10461 * traffic class does not change. 10462 * Range is 0..cap_max_tclass - 1 10463 * Access: Index 10464 */ 10465 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1); 10466 10467 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr) 10468 { 10469 MLXSW_REG_ZERO(sbsr, payload); 10470 mlxsw_reg_sbsr_clr_set(payload, clr); 10471 } 10472 10473 /* reg_sbsr_rec_buff_occupancy 10474 * Current buffer occupancy in cells. 10475 * Access: RO 10476 */ 10477 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 10478 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false); 10479 10480 /* reg_sbsr_rec_max_buff_occupancy 10481 * Maximum value of buffer occupancy in cells monitored. Cleared by 10482 * writing to the clr field. 10483 * Access: RO 10484 */ 10485 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 10486 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false); 10487 10488 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index, 10489 u32 *p_buff_occupancy, 10490 u32 *p_max_buff_occupancy) 10491 { 10492 *p_buff_occupancy = 10493 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index); 10494 *p_max_buff_occupancy = 10495 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index); 10496 } 10497 10498 /* SBIB - Shared Buffer Internal Buffer Register 10499 * --------------------------------------------- 10500 * The SBIB register configures per port buffers for internal use. The internal 10501 * buffers consume memory on the port buffers (note that the port buffers are 10502 * used also by PBMC). 10503 * 10504 * For Spectrum this is used for egress mirroring. 10505 */ 10506 #define MLXSW_REG_SBIB_ID 0xB006 10507 #define MLXSW_REG_SBIB_LEN 0x10 10508 10509 MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN); 10510 10511 /* reg_sbib_local_port 10512 * Local port number 10513 * Not supported for CPU port and router port 10514 * Access: Index 10515 */ 10516 MLXSW_ITEM32(reg, sbib, local_port, 0x00, 16, 8); 10517 10518 /* reg_sbib_buff_size 10519 * Units represented in cells 10520 * Allowed range is 0 to (cap_max_headroom_size - 1) 10521 * Default is 0 10522 * Access: RW 10523 */ 10524 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24); 10525 10526 static inline void mlxsw_reg_sbib_pack(char *payload, u8 local_port, 10527 u32 buff_size) 10528 { 10529 MLXSW_REG_ZERO(sbib, payload); 10530 mlxsw_reg_sbib_local_port_set(payload, local_port); 10531 mlxsw_reg_sbib_buff_size_set(payload, buff_size); 10532 } 10533 10534 static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { 10535 MLXSW_REG(sgcr), 10536 MLXSW_REG(spad), 10537 MLXSW_REG(smid), 10538 MLXSW_REG(sspr), 10539 MLXSW_REG(sfdat), 10540 MLXSW_REG(sfd), 10541 MLXSW_REG(sfn), 10542 MLXSW_REG(spms), 10543 MLXSW_REG(spvid), 10544 MLXSW_REG(spvm), 10545 MLXSW_REG(spaft), 10546 MLXSW_REG(sfgc), 10547 MLXSW_REG(sftr), 10548 MLXSW_REG(sfdf), 10549 MLXSW_REG(sldr), 10550 MLXSW_REG(slcr), 10551 MLXSW_REG(slcor), 10552 MLXSW_REG(spmlr), 10553 MLXSW_REG(svfa), 10554 MLXSW_REG(svpe), 10555 MLXSW_REG(sfmr), 10556 MLXSW_REG(spvmlr), 10557 MLXSW_REG(cwtp), 10558 MLXSW_REG(cwtpm), 10559 MLXSW_REG(pgcr), 10560 MLXSW_REG(ppbt), 10561 MLXSW_REG(pacl), 10562 MLXSW_REG(pagt), 10563 MLXSW_REG(ptar), 10564 MLXSW_REG(ppbs), 10565 MLXSW_REG(prcr), 10566 MLXSW_REG(pefa), 10567 MLXSW_REG(pemrbt), 10568 MLXSW_REG(ptce2), 10569 MLXSW_REG(perpt), 10570 MLXSW_REG(peabfe), 10571 MLXSW_REG(perar), 10572 MLXSW_REG(ptce3), 10573 MLXSW_REG(percr), 10574 MLXSW_REG(pererp), 10575 MLXSW_REG(iedr), 10576 MLXSW_REG(qpts), 10577 MLXSW_REG(qpcr), 10578 MLXSW_REG(qtct), 10579 MLXSW_REG(qeec), 10580 MLXSW_REG(qrwe), 10581 MLXSW_REG(qpdsm), 10582 MLXSW_REG(qpdpm), 10583 MLXSW_REG(qtctm), 10584 MLXSW_REG(qpsc), 10585 MLXSW_REG(pmlp), 10586 MLXSW_REG(pmtu), 10587 MLXSW_REG(ptys), 10588 MLXSW_REG(ppad), 10589 MLXSW_REG(paos), 10590 MLXSW_REG(pfcc), 10591 MLXSW_REG(ppcnt), 10592 MLXSW_REG(plib), 10593 MLXSW_REG(pptb), 10594 MLXSW_REG(pbmc), 10595 MLXSW_REG(pspa), 10596 MLXSW_REG(pplr), 10597 MLXSW_REG(pmtm), 10598 MLXSW_REG(htgt), 10599 MLXSW_REG(hpkt), 10600 MLXSW_REG(rgcr), 10601 MLXSW_REG(ritr), 10602 MLXSW_REG(rtar), 10603 MLXSW_REG(ratr), 10604 MLXSW_REG(rtdp), 10605 MLXSW_REG(rdpm), 10606 MLXSW_REG(ricnt), 10607 MLXSW_REG(rrcr), 10608 MLXSW_REG(ralta), 10609 MLXSW_REG(ralst), 10610 MLXSW_REG(raltb), 10611 MLXSW_REG(ralue), 10612 MLXSW_REG(rauht), 10613 MLXSW_REG(raleu), 10614 MLXSW_REG(rauhtd), 10615 MLXSW_REG(rigr2), 10616 MLXSW_REG(recr2), 10617 MLXSW_REG(rmft2), 10618 MLXSW_REG(mfcr), 10619 MLXSW_REG(mfsc), 10620 MLXSW_REG(mfsm), 10621 MLXSW_REG(mfsl), 10622 MLXSW_REG(fore), 10623 MLXSW_REG(mtcap), 10624 MLXSW_REG(mtmp), 10625 MLXSW_REG(mtbr), 10626 MLXSW_REG(mcia), 10627 MLXSW_REG(mpat), 10628 MLXSW_REG(mpar), 10629 MLXSW_REG(mgir), 10630 MLXSW_REG(mrsr), 10631 MLXSW_REG(mlcr), 10632 MLXSW_REG(mtpps), 10633 MLXSW_REG(mtutc), 10634 MLXSW_REG(mpsc), 10635 MLXSW_REG(mcqi), 10636 MLXSW_REG(mcc), 10637 MLXSW_REG(mcda), 10638 MLXSW_REG(mgpc), 10639 MLXSW_REG(mprs), 10640 MLXSW_REG(mogcr), 10641 MLXSW_REG(mtpppc), 10642 MLXSW_REG(mtpptr), 10643 MLXSW_REG(mtptpt), 10644 MLXSW_REG(mgpir), 10645 MLXSW_REG(tngcr), 10646 MLXSW_REG(tnumt), 10647 MLXSW_REG(tnqcr), 10648 MLXSW_REG(tnqdr), 10649 MLXSW_REG(tneem), 10650 MLXSW_REG(tndem), 10651 MLXSW_REG(tnpc), 10652 MLXSW_REG(tigcr), 10653 MLXSW_REG(sbpr), 10654 MLXSW_REG(sbcm), 10655 MLXSW_REG(sbpm), 10656 MLXSW_REG(sbmm), 10657 MLXSW_REG(sbsr), 10658 MLXSW_REG(sbib), 10659 }; 10660 10661 static inline const char *mlxsw_reg_id_str(u16 reg_id) 10662 { 10663 const struct mlxsw_reg_info *reg_info; 10664 int i; 10665 10666 for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) { 10667 reg_info = mlxsw_reg_infos[i]; 10668 if (reg_info->id == reg_id) 10669 return reg_info->name; 10670 } 10671 return "*UNKNOWN*"; 10672 } 10673 10674 /* PUDE - Port Up / Down Event 10675 * --------------------------- 10676 * Reports the operational state change of a port. 10677 */ 10678 #define MLXSW_REG_PUDE_LEN 0x10 10679 10680 /* reg_pude_swid 10681 * Switch partition ID with which to associate the port. 10682 * Access: Index 10683 */ 10684 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8); 10685 10686 /* reg_pude_local_port 10687 * Local port number. 10688 * Access: Index 10689 */ 10690 MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8); 10691 10692 /* reg_pude_admin_status 10693 * Port administrative state (the desired state). 10694 * 1 - Up. 10695 * 2 - Down. 10696 * 3 - Up once. This means that in case of link failure, the port won't go 10697 * into polling mode, but will wait to be re-enabled by software. 10698 * 4 - Disabled by system. Can only be set by hardware. 10699 * Access: RO 10700 */ 10701 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4); 10702 10703 /* reg_pude_oper_status 10704 * Port operatioanl state. 10705 * 1 - Up. 10706 * 2 - Down. 10707 * 3 - Down by port failure. This means that the device will not let the 10708 * port up again until explicitly specified by software. 10709 * Access: RO 10710 */ 10711 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4); 10712 10713 #endif 10714