1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #ifndef _MLXSW_REG_H 5 #define _MLXSW_REG_H 6 7 #include <linux/kernel.h> 8 #include <linux/string.h> 9 #include <linux/bitops.h> 10 #include <linux/if_vlan.h> 11 12 #include "item.h" 13 #include "port.h" 14 15 struct mlxsw_reg_info { 16 u16 id; 17 u16 len; /* In u8 */ 18 const char *name; 19 }; 20 21 #define MLXSW_REG_DEFINE(_name, _id, _len) \ 22 static const struct mlxsw_reg_info mlxsw_reg_##_name = { \ 23 .id = _id, \ 24 .len = _len, \ 25 .name = #_name, \ 26 } 27 28 #define MLXSW_REG(type) (&mlxsw_reg_##type) 29 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len 30 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len) 31 32 /* SGCR - Switch General Configuration Register 33 * -------------------------------------------- 34 * This register is used for configuration of the switch capabilities. 35 */ 36 #define MLXSW_REG_SGCR_ID 0x2000 37 #define MLXSW_REG_SGCR_LEN 0x10 38 39 MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN); 40 41 /* reg_sgcr_llb 42 * Link Local Broadcast (Default=0) 43 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast 44 * packets and ignore the IGMP snooping entries. 45 * Access: RW 46 */ 47 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1); 48 49 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb) 50 { 51 MLXSW_REG_ZERO(sgcr, payload); 52 mlxsw_reg_sgcr_llb_set(payload, !!llb); 53 } 54 55 /* SPAD - Switch Physical Address Register 56 * --------------------------------------- 57 * The SPAD register configures the switch physical MAC address. 58 */ 59 #define MLXSW_REG_SPAD_ID 0x2002 60 #define MLXSW_REG_SPAD_LEN 0x10 61 62 MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN); 63 64 /* reg_spad_base_mac 65 * Base MAC address for the switch partitions. 66 * Per switch partition MAC address is equal to: 67 * base_mac + swid 68 * Access: RW 69 */ 70 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6); 71 72 /* SSPR - Switch System Port Record Register 73 * ----------------------------------------- 74 * Configures the system port to local port mapping. 75 */ 76 #define MLXSW_REG_SSPR_ID 0x2008 77 #define MLXSW_REG_SSPR_LEN 0x8 78 79 MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN); 80 81 /* reg_sspr_m 82 * Master - if set, then the record describes the master system port. 83 * This is needed in case a local port is mapped into several system ports 84 * (for multipathing). That number will be reported as the source system 85 * port when packets are forwarded to the CPU. Only one master port is allowed 86 * per local port. 87 * 88 * Note: Must be set for Spectrum. 89 * Access: RW 90 */ 91 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1); 92 93 /* reg_sspr_local_port 94 * Local port number. 95 * 96 * Access: RW 97 */ 98 MLXSW_ITEM32_LP(reg, sspr, 0x00, 16, 0x00, 12); 99 100 /* reg_sspr_sub_port 101 * Virtual port within the physical port. 102 * Should be set to 0 when virtual ports are not enabled on the port. 103 * 104 * Access: RW 105 */ 106 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8); 107 108 /* reg_sspr_system_port 109 * Unique identifier within the stacking domain that represents all the ports 110 * that are available in the system (external ports). 111 * 112 * Currently, only single-ASIC configurations are supported, so we default to 113 * 1:1 mapping between system ports and local ports. 114 * Access: Index 115 */ 116 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16); 117 118 static inline void mlxsw_reg_sspr_pack(char *payload, u16 local_port) 119 { 120 MLXSW_REG_ZERO(sspr, payload); 121 mlxsw_reg_sspr_m_set(payload, 1); 122 mlxsw_reg_sspr_local_port_set(payload, local_port); 123 mlxsw_reg_sspr_sub_port_set(payload, 0); 124 mlxsw_reg_sspr_system_port_set(payload, local_port); 125 } 126 127 /* SFDAT - Switch Filtering Database Aging Time 128 * -------------------------------------------- 129 * Controls the Switch aging time. Aging time is able to be set per Switch 130 * Partition. 131 */ 132 #define MLXSW_REG_SFDAT_ID 0x2009 133 #define MLXSW_REG_SFDAT_LEN 0x8 134 135 MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN); 136 137 /* reg_sfdat_swid 138 * Switch partition ID. 139 * Access: Index 140 */ 141 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8); 142 143 /* reg_sfdat_age_time 144 * Aging time in seconds 145 * Min - 10 seconds 146 * Max - 1,000,000 seconds 147 * Default is 300 seconds. 148 * Access: RW 149 */ 150 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20); 151 152 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time) 153 { 154 MLXSW_REG_ZERO(sfdat, payload); 155 mlxsw_reg_sfdat_swid_set(payload, 0); 156 mlxsw_reg_sfdat_age_time_set(payload, age_time); 157 } 158 159 /* SFD - Switch Filtering Database 160 * ------------------------------- 161 * The following register defines the access to the filtering database. 162 * The register supports querying, adding, removing and modifying the database. 163 * The access is optimized for bulk updates in which case more than one 164 * FDB record is present in the same command. 165 */ 166 #define MLXSW_REG_SFD_ID 0x200A 167 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */ 168 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */ 169 #define MLXSW_REG_SFD_REC_MAX_COUNT 64 170 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \ 171 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT) 172 173 MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN); 174 175 /* reg_sfd_swid 176 * Switch partition ID for queries. Reserved on Write. 177 * Access: Index 178 */ 179 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8); 180 181 enum mlxsw_reg_sfd_op { 182 /* Dump entire FDB a (process according to record_locator) */ 183 MLXSW_REG_SFD_OP_QUERY_DUMP = 0, 184 /* Query records by {MAC, VID/FID} value */ 185 MLXSW_REG_SFD_OP_QUERY_QUERY = 1, 186 /* Query and clear activity. Query records by {MAC, VID/FID} value */ 187 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2, 188 /* Test. Response indicates if each of the records could be 189 * added to the FDB. 190 */ 191 MLXSW_REG_SFD_OP_WRITE_TEST = 0, 192 /* Add/modify. Aged-out records cannot be added. This command removes 193 * the learning notification of the {MAC, VID/FID}. Response includes 194 * the entries that were added to the FDB. 195 */ 196 MLXSW_REG_SFD_OP_WRITE_EDIT = 1, 197 /* Remove record by {MAC, VID/FID}. This command also removes 198 * the learning notification and aged-out notifications 199 * of the {MAC, VID/FID}. The response provides current (pre-removal) 200 * entries as non-aged-out. 201 */ 202 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2, 203 /* Remove learned notification by {MAC, VID/FID}. The response provides 204 * the removed learning notification. 205 */ 206 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2, 207 }; 208 209 /* reg_sfd_op 210 * Operation. 211 * Access: OP 212 */ 213 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2); 214 215 /* reg_sfd_record_locator 216 * Used for querying the FDB. Use record_locator=0 to initiate the 217 * query. When a record is returned, a new record_locator is 218 * returned to be used in the subsequent query. 219 * Reserved for database update. 220 * Access: Index 221 */ 222 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30); 223 224 /* reg_sfd_num_rec 225 * Request: Number of records to read/add/modify/remove 226 * Response: Number of records read/added/replaced/removed 227 * See above description for more details. 228 * Ranges 0..64 229 * Access: RW 230 */ 231 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8); 232 233 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op, 234 u32 record_locator) 235 { 236 MLXSW_REG_ZERO(sfd, payload); 237 mlxsw_reg_sfd_op_set(payload, op); 238 mlxsw_reg_sfd_record_locator_set(payload, record_locator); 239 } 240 241 /* reg_sfd_rec_swid 242 * Switch partition ID. 243 * Access: Index 244 */ 245 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8, 246 MLXSW_REG_SFD_REC_LEN, 0x00, false); 247 248 enum mlxsw_reg_sfd_rec_type { 249 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0, 250 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1, 251 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2, 252 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL = 0xC, 253 }; 254 255 /* reg_sfd_rec_type 256 * FDB record type. 257 * Access: RW 258 */ 259 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4, 260 MLXSW_REG_SFD_REC_LEN, 0x00, false); 261 262 enum mlxsw_reg_sfd_rec_policy { 263 /* Replacement disabled, aging disabled. */ 264 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0, 265 /* (mlag remote): Replacement enabled, aging disabled, 266 * learning notification enabled on this port. 267 */ 268 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1, 269 /* (ingress device): Replacement enabled, aging enabled. */ 270 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3, 271 }; 272 273 /* reg_sfd_rec_policy 274 * Policy. 275 * Access: RW 276 */ 277 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2, 278 MLXSW_REG_SFD_REC_LEN, 0x00, false); 279 280 /* reg_sfd_rec_a 281 * Activity. Set for new static entries. Set for static entries if a frame SMAC 282 * lookup hits on the entry. 283 * To clear the a bit, use "query and clear activity" op. 284 * Access: RO 285 */ 286 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1, 287 MLXSW_REG_SFD_REC_LEN, 0x00, false); 288 289 /* reg_sfd_rec_mac 290 * MAC address. 291 * Access: Index 292 */ 293 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6, 294 MLXSW_REG_SFD_REC_LEN, 0x02); 295 296 enum mlxsw_reg_sfd_rec_action { 297 /* forward */ 298 MLXSW_REG_SFD_REC_ACTION_NOP = 0, 299 /* forward and trap, trap_id is FDB_TRAP */ 300 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1, 301 /* trap and do not forward, trap_id is FDB_TRAP */ 302 MLXSW_REG_SFD_REC_ACTION_TRAP = 2, 303 /* forward to IP router */ 304 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3, 305 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15, 306 }; 307 308 /* reg_sfd_rec_action 309 * Action to apply on the packet. 310 * Note: Dynamic entries can only be configured with NOP action. 311 * Access: RW 312 */ 313 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4, 314 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 315 316 /* reg_sfd_uc_sub_port 317 * VEPA channel on local port. 318 * Valid only if local port is a non-stacking port. Must be 0 if multichannel 319 * VEPA is not enabled. 320 * Access: RW 321 */ 322 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 323 MLXSW_REG_SFD_REC_LEN, 0x08, false); 324 325 /* reg_sfd_uc_set_vid 326 * Set VID. 327 * 0 - Do not update VID. 328 * 1 - Set VID. 329 * For Spectrum-2 when set_vid=0 and smpe_valid=1, the smpe will modify the vid. 330 * Access: RW 331 * 332 * Note: Reserved when legacy bridge model is used. 333 */ 334 MLXSW_ITEM32_INDEXED(reg, sfd, uc_set_vid, MLXSW_REG_SFD_BASE_LEN, 31, 1, 335 MLXSW_REG_SFD_REC_LEN, 0x08, false); 336 337 /* reg_sfd_uc_fid_vid 338 * Filtering ID or VLAN ID 339 * For SwitchX and SwitchX-2: 340 * - Dynamic entries (policy 2,3) use FID 341 * - Static entries (policy 0) use VID 342 * - When independent learning is configured, VID=FID 343 * For Spectrum: use FID for both Dynamic and Static entries. 344 * VID should not be used. 345 * Access: Index 346 */ 347 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 348 MLXSW_REG_SFD_REC_LEN, 0x08, false); 349 350 /* reg_sfd_uc_vid 351 * New VID when set_vid=1. 352 * Access: RW 353 * 354 * Note: Reserved when legacy bridge model is used and when set_vid=0. 355 */ 356 MLXSW_ITEM32_INDEXED(reg, sfd, uc_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, 357 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 358 359 /* reg_sfd_uc_system_port 360 * Unique port identifier for the final destination of the packet. 361 * Access: RW 362 */ 363 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16, 364 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 365 366 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index, 367 enum mlxsw_reg_sfd_rec_type rec_type, 368 const char *mac, 369 enum mlxsw_reg_sfd_rec_action action) 370 { 371 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload); 372 373 if (rec_index >= num_rec) 374 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1); 375 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0); 376 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type); 377 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac); 378 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action); 379 } 380 381 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index, 382 enum mlxsw_reg_sfd_rec_policy policy, 383 const char *mac, u16 fid_vid, 384 enum mlxsw_reg_sfd_rec_action action, 385 u16 local_port) 386 { 387 mlxsw_reg_sfd_rec_pack(payload, rec_index, 388 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action); 389 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 390 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0); 391 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid); 392 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port); 393 } 394 395 /* reg_sfd_uc_lag_sub_port 396 * LAG sub port. 397 * Must be 0 if multichannel VEPA is not enabled. 398 * Access: RW 399 */ 400 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 401 MLXSW_REG_SFD_REC_LEN, 0x08, false); 402 403 /* reg_sfd_uc_lag_set_vid 404 * Set VID. 405 * 0 - Do not update VID. 406 * 1 - Set VID. 407 * For Spectrum-2 when set_vid=0 and smpe_valid=1, the smpe will modify the vid. 408 * Access: RW 409 * 410 * Note: Reserved when legacy bridge model is used. 411 */ 412 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_set_vid, MLXSW_REG_SFD_BASE_LEN, 31, 1, 413 MLXSW_REG_SFD_REC_LEN, 0x08, false); 414 415 /* reg_sfd_uc_lag_fid_vid 416 * Filtering ID or VLAN ID 417 * For SwitchX and SwitchX-2: 418 * - Dynamic entries (policy 2,3) use FID 419 * - Static entries (policy 0) use VID 420 * - When independent learning is configured, VID=FID 421 * For Spectrum: use FID for both Dynamic and Static entries. 422 * VID should not be used. 423 * Access: Index 424 */ 425 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 426 MLXSW_REG_SFD_REC_LEN, 0x08, false); 427 428 /* reg_sfd_uc_lag_lag_vid 429 * New vlan ID. 430 * Access: RW 431 * 432 * Note: Reserved when legacy bridge model is used and set_vid=0. 433 */ 434 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, 435 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 436 437 /* reg_sfd_uc_lag_lag_id 438 * LAG Identifier - pointer into the LAG descriptor table. 439 * Access: RW 440 */ 441 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10, 442 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 443 444 static inline void 445 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index, 446 enum mlxsw_reg_sfd_rec_policy policy, 447 const char *mac, u16 fid_vid, 448 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid, 449 u16 lag_id) 450 { 451 mlxsw_reg_sfd_rec_pack(payload, rec_index, 452 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG, 453 mac, action); 454 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 455 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0); 456 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid); 457 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid); 458 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id); 459 } 460 461 /* reg_sfd_mc_pgi 462 * 463 * Multicast port group index - index into the port group table. 464 * Value 0x1FFF indicates the pgi should point to the MID entry. 465 * For Spectrum this value must be set to 0x1FFF 466 * Access: RW 467 */ 468 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13, 469 MLXSW_REG_SFD_REC_LEN, 0x08, false); 470 471 /* reg_sfd_mc_fid_vid 472 * 473 * Filtering ID or VLAN ID 474 * Access: Index 475 */ 476 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 477 MLXSW_REG_SFD_REC_LEN, 0x08, false); 478 479 /* reg_sfd_mc_mid 480 * 481 * Multicast identifier - global identifier that represents the multicast 482 * group across all devices. 483 * Access: RW 484 */ 485 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 486 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 487 488 static inline void 489 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index, 490 const char *mac, u16 fid_vid, 491 enum mlxsw_reg_sfd_rec_action action, u16 mid) 492 { 493 mlxsw_reg_sfd_rec_pack(payload, rec_index, 494 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action); 495 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF); 496 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid); 497 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid); 498 } 499 500 /* reg_sfd_uc_tunnel_uip_msb 501 * When protocol is IPv4, the most significant byte of the underlay IPv4 502 * destination IP. 503 * When protocol is IPv6, reserved. 504 * Access: RW 505 */ 506 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24, 507 8, MLXSW_REG_SFD_REC_LEN, 0x08, false); 508 509 /* reg_sfd_uc_tunnel_fid 510 * Filtering ID. 511 * Access: Index 512 */ 513 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 514 MLXSW_REG_SFD_REC_LEN, 0x08, false); 515 516 enum mlxsw_reg_sfd_uc_tunnel_protocol { 517 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4, 518 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6, 519 }; 520 521 /* reg_sfd_uc_tunnel_protocol 522 * IP protocol. 523 * Access: RW 524 */ 525 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27, 526 1, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 527 528 /* reg_sfd_uc_tunnel_uip_lsb 529 * When protocol is IPv4, the least significant bytes of the underlay 530 * IPv4 destination IP. 531 * When protocol is IPv6, pointer to the underlay IPv6 destination IP 532 * which is configured by RIPS. 533 * Access: RW 534 */ 535 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0, 536 24, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 537 538 static inline void 539 mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index, 540 enum mlxsw_reg_sfd_rec_policy policy, 541 const char *mac, u16 fid, 542 enum mlxsw_reg_sfd_rec_action action, 543 enum mlxsw_reg_sfd_uc_tunnel_protocol proto) 544 { 545 mlxsw_reg_sfd_rec_pack(payload, rec_index, 546 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL, mac, 547 action); 548 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 549 mlxsw_reg_sfd_uc_tunnel_fid_set(payload, rec_index, fid); 550 mlxsw_reg_sfd_uc_tunnel_protocol_set(payload, rec_index, proto); 551 } 552 553 static inline void 554 mlxsw_reg_sfd_uc_tunnel_pack4(char *payload, int rec_index, 555 enum mlxsw_reg_sfd_rec_policy policy, 556 const char *mac, u16 fid, 557 enum mlxsw_reg_sfd_rec_action action, u32 uip) 558 { 559 mlxsw_reg_sfd_uc_tunnel_uip_msb_set(payload, rec_index, uip >> 24); 560 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip); 561 mlxsw_reg_sfd_uc_tunnel_pack(payload, rec_index, policy, mac, fid, 562 action, 563 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4); 564 } 565 566 static inline void 567 mlxsw_reg_sfd_uc_tunnel_pack6(char *payload, int rec_index, const char *mac, 568 u16 fid, enum mlxsw_reg_sfd_rec_action action, 569 u32 uip_ptr) 570 { 571 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip_ptr); 572 /* Only static policy is supported for IPv6 unicast tunnel entry. */ 573 mlxsw_reg_sfd_uc_tunnel_pack(payload, rec_index, 574 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY, 575 mac, fid, action, 576 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6); 577 } 578 579 enum mlxsw_reg_tunnel_port { 580 MLXSW_REG_TUNNEL_PORT_NVE, 581 MLXSW_REG_TUNNEL_PORT_VPLS, 582 MLXSW_REG_TUNNEL_PORT_FLEX_TUNNEL0, 583 MLXSW_REG_TUNNEL_PORT_FLEX_TUNNEL1, 584 }; 585 586 /* SFN - Switch FDB Notification Register 587 * ------------------------------------------- 588 * The switch provides notifications on newly learned FDB entries and 589 * aged out entries. The notifications can be polled by software. 590 */ 591 #define MLXSW_REG_SFN_ID 0x200B 592 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */ 593 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */ 594 #define MLXSW_REG_SFN_REC_MAX_COUNT 64 595 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \ 596 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT) 597 598 MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN); 599 600 /* reg_sfn_swid 601 * Switch partition ID. 602 * Access: Index 603 */ 604 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8); 605 606 /* reg_sfn_end 607 * Forces the current session to end. 608 * Access: OP 609 */ 610 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1); 611 612 /* reg_sfn_num_rec 613 * Request: Number of learned notifications and aged-out notification 614 * records requested. 615 * Response: Number of notification records returned (must be smaller 616 * than or equal to the value requested) 617 * Ranges 0..64 618 * Access: OP 619 */ 620 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8); 621 622 static inline void mlxsw_reg_sfn_pack(char *payload) 623 { 624 MLXSW_REG_ZERO(sfn, payload); 625 mlxsw_reg_sfn_swid_set(payload, 0); 626 mlxsw_reg_sfn_end_set(payload, 0); 627 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT); 628 } 629 630 /* reg_sfn_rec_swid 631 * Switch partition ID. 632 * Access: RO 633 */ 634 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8, 635 MLXSW_REG_SFN_REC_LEN, 0x00, false); 636 637 enum mlxsw_reg_sfn_rec_type { 638 /* MAC addresses learned on a regular port. */ 639 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5, 640 /* MAC addresses learned on a LAG port. */ 641 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6, 642 /* Aged-out MAC address on a regular port. */ 643 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7, 644 /* Aged-out MAC address on a LAG port. */ 645 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8, 646 /* Learned unicast tunnel record. */ 647 MLXSW_REG_SFN_REC_TYPE_LEARNED_UNICAST_TUNNEL = 0xD, 648 /* Aged-out unicast tunnel record. */ 649 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_UNICAST_TUNNEL = 0xE, 650 }; 651 652 /* reg_sfn_rec_type 653 * Notification record type. 654 * Access: RO 655 */ 656 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4, 657 MLXSW_REG_SFN_REC_LEN, 0x00, false); 658 659 /* reg_sfn_rec_mac 660 * MAC address. 661 * Access: RO 662 */ 663 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6, 664 MLXSW_REG_SFN_REC_LEN, 0x02); 665 666 /* reg_sfn_mac_sub_port 667 * VEPA channel on the local port. 668 * 0 if multichannel VEPA is not enabled. 669 * Access: RO 670 */ 671 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8, 672 MLXSW_REG_SFN_REC_LEN, 0x08, false); 673 674 /* reg_sfn_mac_fid 675 * Filtering identifier. 676 * Access: RO 677 */ 678 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16, 679 MLXSW_REG_SFN_REC_LEN, 0x08, false); 680 681 /* reg_sfn_mac_system_port 682 * Unique port identifier for the final destination of the packet. 683 * Access: RO 684 */ 685 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16, 686 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 687 688 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index, 689 char *mac, u16 *p_vid, 690 u16 *p_local_port) 691 { 692 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 693 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 694 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index); 695 } 696 697 /* reg_sfn_mac_lag_lag_id 698 * LAG ID (pointer into the LAG descriptor table). 699 * Access: RO 700 */ 701 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10, 702 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 703 704 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index, 705 char *mac, u16 *p_vid, 706 u16 *p_lag_id) 707 { 708 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 709 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 710 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index); 711 } 712 713 /* reg_sfn_uc_tunnel_uip_msb 714 * When protocol is IPv4, the most significant byte of the underlay IPv4 715 * address of the remote VTEP. 716 * When protocol is IPv6, reserved. 717 * Access: RO 718 */ 719 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_msb, MLXSW_REG_SFN_BASE_LEN, 24, 720 8, MLXSW_REG_SFN_REC_LEN, 0x08, false); 721 722 enum mlxsw_reg_sfn_uc_tunnel_protocol { 723 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV4, 724 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV6, 725 }; 726 727 /* reg_sfn_uc_tunnel_protocol 728 * IP protocol. 729 * Access: RO 730 */ 731 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_protocol, MLXSW_REG_SFN_BASE_LEN, 27, 732 1, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 733 734 /* reg_sfn_uc_tunnel_uip_lsb 735 * When protocol is IPv4, the least significant bytes of the underlay 736 * IPv4 address of the remote VTEP. 737 * When protocol is IPv6, ipv6_id to be queried from TNIPSD. 738 * Access: RO 739 */ 740 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0, 741 24, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 742 743 /* reg_sfn_uc_tunnel_port 744 * Tunnel port. 745 * Reserved on Spectrum. 746 * Access: RO 747 */ 748 MLXSW_ITEM32_INDEXED(reg, sfn, tunnel_port, MLXSW_REG_SFN_BASE_LEN, 0, 4, 749 MLXSW_REG_SFN_REC_LEN, 0x10, false); 750 751 static inline void 752 mlxsw_reg_sfn_uc_tunnel_unpack(char *payload, int rec_index, char *mac, 753 u16 *p_fid, u32 *p_uip, 754 enum mlxsw_reg_sfn_uc_tunnel_protocol *p_proto) 755 { 756 u32 uip_msb, uip_lsb; 757 758 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 759 *p_fid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 760 uip_msb = mlxsw_reg_sfn_uc_tunnel_uip_msb_get(payload, rec_index); 761 uip_lsb = mlxsw_reg_sfn_uc_tunnel_uip_lsb_get(payload, rec_index); 762 *p_uip = uip_msb << 24 | uip_lsb; 763 *p_proto = mlxsw_reg_sfn_uc_tunnel_protocol_get(payload, rec_index); 764 } 765 766 /* SPMS - Switch Port MSTP/RSTP State Register 767 * ------------------------------------------- 768 * Configures the spanning tree state of a physical port. 769 */ 770 #define MLXSW_REG_SPMS_ID 0x200D 771 #define MLXSW_REG_SPMS_LEN 0x404 772 773 MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN); 774 775 /* reg_spms_local_port 776 * Local port number. 777 * Access: Index 778 */ 779 MLXSW_ITEM32_LP(reg, spms, 0x00, 16, 0x00, 12); 780 781 enum mlxsw_reg_spms_state { 782 MLXSW_REG_SPMS_STATE_NO_CHANGE, 783 MLXSW_REG_SPMS_STATE_DISCARDING, 784 MLXSW_REG_SPMS_STATE_LEARNING, 785 MLXSW_REG_SPMS_STATE_FORWARDING, 786 }; 787 788 /* reg_spms_state 789 * Spanning tree state of each VLAN ID (VID) of the local port. 790 * 0 - Do not change spanning tree state (used only when writing). 791 * 1 - Discarding. No learning or forwarding to/from this port (default). 792 * 2 - Learning. Port is learning, but not forwarding. 793 * 3 - Forwarding. Port is learning and forwarding. 794 * Access: RW 795 */ 796 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2); 797 798 static inline void mlxsw_reg_spms_pack(char *payload, u16 local_port) 799 { 800 MLXSW_REG_ZERO(spms, payload); 801 mlxsw_reg_spms_local_port_set(payload, local_port); 802 } 803 804 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid, 805 enum mlxsw_reg_spms_state state) 806 { 807 mlxsw_reg_spms_state_set(payload, vid, state); 808 } 809 810 /* SPVID - Switch Port VID 811 * ----------------------- 812 * The switch port VID configures the default VID for a port. 813 */ 814 #define MLXSW_REG_SPVID_ID 0x200E 815 #define MLXSW_REG_SPVID_LEN 0x08 816 817 MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN); 818 819 /* reg_spvid_tport 820 * Port is tunnel port. 821 * Reserved when SwitchX/-2 or Spectrum-1. 822 * Access: Index 823 */ 824 MLXSW_ITEM32(reg, spvid, tport, 0x00, 24, 1); 825 826 /* reg_spvid_local_port 827 * When tport = 0: Local port number. Not supported for CPU port. 828 * When tport = 1: Tunnel port. 829 * Access: Index 830 */ 831 MLXSW_ITEM32_LP(reg, spvid, 0x00, 16, 0x00, 12); 832 833 /* reg_spvid_sub_port 834 * Virtual port within the physical port. 835 * Should be set to 0 when virtual ports are not enabled on the port. 836 * Access: Index 837 */ 838 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8); 839 840 /* reg_spvid_egr_et_set 841 * When VLAN is pushed at ingress (for untagged packets or for 842 * QinQ push mode) then the EtherType is decided at the egress port. 843 * Reserved when Spectrum-1. 844 * Access: RW 845 */ 846 MLXSW_ITEM32(reg, spvid, egr_et_set, 0x04, 24, 1); 847 848 /* reg_spvid_et_vlan 849 * EtherType used for when VLAN is pushed at ingress (for untagged 850 * packets or for QinQ push mode). 851 * 0: ether_type0 - (default) 852 * 1: ether_type1 853 * 2: ether_type2 - Reserved when Spectrum-1, supported by Spectrum-2 854 * Ethertype IDs are configured by SVER. 855 * Reserved when egr_et_set = 1. 856 * Access: RW 857 */ 858 MLXSW_ITEM32(reg, spvid, et_vlan, 0x04, 16, 2); 859 860 /* reg_spvid_pvid 861 * Port default VID 862 * Access: RW 863 */ 864 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12); 865 866 static inline void mlxsw_reg_spvid_pack(char *payload, u16 local_port, u16 pvid, 867 u8 et_vlan) 868 { 869 MLXSW_REG_ZERO(spvid, payload); 870 mlxsw_reg_spvid_local_port_set(payload, local_port); 871 mlxsw_reg_spvid_pvid_set(payload, pvid); 872 mlxsw_reg_spvid_et_vlan_set(payload, et_vlan); 873 } 874 875 /* SPVM - Switch Port VLAN Membership 876 * ---------------------------------- 877 * The Switch Port VLAN Membership register configures the VLAN membership 878 * of a port in a VLAN denoted by VID. VLAN membership is managed per 879 * virtual port. The register can be used to add and remove VID(s) from a port. 880 */ 881 #define MLXSW_REG_SPVM_ID 0x200F 882 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */ 883 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */ 884 #define MLXSW_REG_SPVM_REC_MAX_COUNT 255 885 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \ 886 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT) 887 888 MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN); 889 890 /* reg_spvm_pt 891 * Priority tagged. If this bit is set, packets forwarded to the port with 892 * untagged VLAN membership (u bit is set) will be tagged with priority tag 893 * (VID=0) 894 * Access: RW 895 */ 896 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1); 897 898 /* reg_spvm_pte 899 * Priority Tagged Update Enable. On Write operations, if this bit is cleared, 900 * the pt bit will NOT be updated. To update the pt bit, pte must be set. 901 * Access: WO 902 */ 903 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1); 904 905 /* reg_spvm_local_port 906 * Local port number. 907 * Access: Index 908 */ 909 MLXSW_ITEM32_LP(reg, spvm, 0x00, 16, 0x00, 12); 910 911 /* reg_spvm_sub_port 912 * Virtual port within the physical port. 913 * Should be set to 0 when virtual ports are not enabled on the port. 914 * Access: Index 915 */ 916 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8); 917 918 /* reg_spvm_num_rec 919 * Number of records to update. Each record contains: i, e, u, vid. 920 * Access: OP 921 */ 922 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8); 923 924 /* reg_spvm_rec_i 925 * Ingress membership in VLAN ID. 926 * Access: Index 927 */ 928 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i, 929 MLXSW_REG_SPVM_BASE_LEN, 14, 1, 930 MLXSW_REG_SPVM_REC_LEN, 0, false); 931 932 /* reg_spvm_rec_e 933 * Egress membership in VLAN ID. 934 * Access: Index 935 */ 936 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e, 937 MLXSW_REG_SPVM_BASE_LEN, 13, 1, 938 MLXSW_REG_SPVM_REC_LEN, 0, false); 939 940 /* reg_spvm_rec_u 941 * Untagged - port is an untagged member - egress transmission uses untagged 942 * frames on VID<n> 943 * Access: Index 944 */ 945 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u, 946 MLXSW_REG_SPVM_BASE_LEN, 12, 1, 947 MLXSW_REG_SPVM_REC_LEN, 0, false); 948 949 /* reg_spvm_rec_vid 950 * Egress membership in VLAN ID. 951 * Access: Index 952 */ 953 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid, 954 MLXSW_REG_SPVM_BASE_LEN, 0, 12, 955 MLXSW_REG_SPVM_REC_LEN, 0, false); 956 957 static inline void mlxsw_reg_spvm_pack(char *payload, u16 local_port, 958 u16 vid_begin, u16 vid_end, 959 bool is_member, bool untagged) 960 { 961 int size = vid_end - vid_begin + 1; 962 int i; 963 964 MLXSW_REG_ZERO(spvm, payload); 965 mlxsw_reg_spvm_local_port_set(payload, local_port); 966 mlxsw_reg_spvm_num_rec_set(payload, size); 967 968 for (i = 0; i < size; i++) { 969 mlxsw_reg_spvm_rec_i_set(payload, i, is_member); 970 mlxsw_reg_spvm_rec_e_set(payload, i, is_member); 971 mlxsw_reg_spvm_rec_u_set(payload, i, untagged); 972 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i); 973 } 974 } 975 976 /* SPAFT - Switch Port Acceptable Frame Types 977 * ------------------------------------------ 978 * The Switch Port Acceptable Frame Types register configures the frame 979 * admittance of the port. 980 */ 981 #define MLXSW_REG_SPAFT_ID 0x2010 982 #define MLXSW_REG_SPAFT_LEN 0x08 983 984 MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN); 985 986 /* reg_spaft_local_port 987 * Local port number. 988 * Access: Index 989 * 990 * Note: CPU port is not supported (all tag types are allowed). 991 */ 992 MLXSW_ITEM32_LP(reg, spaft, 0x00, 16, 0x00, 12); 993 994 /* reg_spaft_sub_port 995 * Virtual port within the physical port. 996 * Should be set to 0 when virtual ports are not enabled on the port. 997 * Access: RW 998 */ 999 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8); 1000 1001 /* reg_spaft_allow_untagged 1002 * When set, untagged frames on the ingress are allowed (default). 1003 * Access: RW 1004 */ 1005 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1); 1006 1007 /* reg_spaft_allow_prio_tagged 1008 * When set, priority tagged frames on the ingress are allowed (default). 1009 * Access: RW 1010 */ 1011 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1); 1012 1013 /* reg_spaft_allow_tagged 1014 * When set, tagged frames on the ingress are allowed (default). 1015 * Access: RW 1016 */ 1017 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1); 1018 1019 static inline void mlxsw_reg_spaft_pack(char *payload, u16 local_port, 1020 bool allow_untagged) 1021 { 1022 MLXSW_REG_ZERO(spaft, payload); 1023 mlxsw_reg_spaft_local_port_set(payload, local_port); 1024 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged); 1025 mlxsw_reg_spaft_allow_prio_tagged_set(payload, allow_untagged); 1026 mlxsw_reg_spaft_allow_tagged_set(payload, true); 1027 } 1028 1029 /* SFGC - Switch Flooding Group Configuration 1030 * ------------------------------------------ 1031 * The following register controls the association of flooding tables and MIDs 1032 * to packet types used for flooding. 1033 */ 1034 #define MLXSW_REG_SFGC_ID 0x2011 1035 #define MLXSW_REG_SFGC_LEN 0x14 1036 1037 MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN); 1038 1039 enum mlxsw_reg_sfgc_type { 1040 MLXSW_REG_SFGC_TYPE_BROADCAST, 1041 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST, 1042 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4, 1043 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6, 1044 MLXSW_REG_SFGC_TYPE_RESERVED, 1045 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP, 1046 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL, 1047 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST, 1048 MLXSW_REG_SFGC_TYPE_MAX, 1049 }; 1050 1051 /* reg_sfgc_type 1052 * The traffic type to reach the flooding table. 1053 * Access: Index 1054 */ 1055 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4); 1056 1057 enum mlxsw_reg_sfgc_bridge_type { 1058 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0, 1059 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1, 1060 }; 1061 1062 /* reg_sfgc_bridge_type 1063 * Access: Index 1064 * 1065 * Note: SwitchX-2 only supports 802.1Q mode. 1066 */ 1067 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3); 1068 1069 enum mlxsw_flood_table_type { 1070 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1, 1071 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2, 1072 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0, 1073 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3, 1074 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4, 1075 }; 1076 1077 /* reg_sfgc_table_type 1078 * See mlxsw_flood_table_type 1079 * Access: RW 1080 * 1081 * Note: FID offset and FID types are not supported in SwitchX-2. 1082 */ 1083 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3); 1084 1085 /* reg_sfgc_flood_table 1086 * Flooding table index to associate with the specific type on the specific 1087 * switch partition. 1088 * Access: RW 1089 */ 1090 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6); 1091 1092 /* reg_sfgc_counter_set_type 1093 * Counter Set Type for flow counters. 1094 * Access: RW 1095 */ 1096 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8); 1097 1098 /* reg_sfgc_counter_index 1099 * Counter Index for flow counters. 1100 * Access: RW 1101 */ 1102 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24); 1103 1104 /* reg_sfgc_mid_base 1105 * MID Base. 1106 * Access: RW 1107 * 1108 * Note: Reserved when legacy bridge model is used. 1109 */ 1110 MLXSW_ITEM32(reg, sfgc, mid_base, 0x10, 0, 16); 1111 1112 static inline void 1113 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type, 1114 enum mlxsw_reg_sfgc_bridge_type bridge_type, 1115 enum mlxsw_flood_table_type table_type, 1116 unsigned int flood_table) 1117 { 1118 MLXSW_REG_ZERO(sfgc, payload); 1119 mlxsw_reg_sfgc_type_set(payload, type); 1120 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type); 1121 mlxsw_reg_sfgc_table_type_set(payload, table_type); 1122 mlxsw_reg_sfgc_flood_table_set(payload, flood_table); 1123 } 1124 1125 /* SFDF - Switch Filtering DB Flush 1126 * -------------------------------- 1127 * The switch filtering DB flush register is used to flush the FDB. 1128 * Note that FDB notifications are flushed as well. 1129 */ 1130 #define MLXSW_REG_SFDF_ID 0x2013 1131 #define MLXSW_REG_SFDF_LEN 0x14 1132 1133 MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN); 1134 1135 /* reg_sfdf_swid 1136 * Switch partition ID. 1137 * Access: Index 1138 */ 1139 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8); 1140 1141 enum mlxsw_reg_sfdf_flush_type { 1142 MLXSW_REG_SFDF_FLUSH_PER_SWID, 1143 MLXSW_REG_SFDF_FLUSH_PER_FID, 1144 MLXSW_REG_SFDF_FLUSH_PER_PORT, 1145 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID, 1146 MLXSW_REG_SFDF_FLUSH_PER_LAG, 1147 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID, 1148 MLXSW_REG_SFDF_FLUSH_PER_NVE, 1149 MLXSW_REG_SFDF_FLUSH_PER_NVE_AND_FID, 1150 }; 1151 1152 /* reg_sfdf_flush_type 1153 * Flush type. 1154 * 0 - All SWID dynamic entries are flushed. 1155 * 1 - All FID dynamic entries are flushed. 1156 * 2 - All dynamic entries pointing to port are flushed. 1157 * 3 - All FID dynamic entries pointing to port are flushed. 1158 * 4 - All dynamic entries pointing to LAG are flushed. 1159 * 5 - All FID dynamic entries pointing to LAG are flushed. 1160 * 6 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1161 * flushed. 1162 * 7 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1163 * flushed, per FID. 1164 * Access: RW 1165 */ 1166 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4); 1167 1168 /* reg_sfdf_flush_static 1169 * Static. 1170 * 0 - Flush only dynamic entries. 1171 * 1 - Flush both dynamic and static entries. 1172 * Access: RW 1173 */ 1174 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1); 1175 1176 static inline void mlxsw_reg_sfdf_pack(char *payload, 1177 enum mlxsw_reg_sfdf_flush_type type) 1178 { 1179 MLXSW_REG_ZERO(sfdf, payload); 1180 mlxsw_reg_sfdf_flush_type_set(payload, type); 1181 mlxsw_reg_sfdf_flush_static_set(payload, true); 1182 } 1183 1184 /* reg_sfdf_fid 1185 * FID to flush. 1186 * Access: RW 1187 */ 1188 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16); 1189 1190 /* reg_sfdf_system_port 1191 * Port to flush. 1192 * Access: RW 1193 */ 1194 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16); 1195 1196 /* reg_sfdf_port_fid_system_port 1197 * Port to flush, pointed to by FID. 1198 * Access: RW 1199 */ 1200 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16); 1201 1202 /* reg_sfdf_lag_id 1203 * LAG ID to flush. 1204 * Access: RW 1205 */ 1206 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10); 1207 1208 /* reg_sfdf_lag_fid_lag_id 1209 * LAG ID to flush, pointed to by FID. 1210 * Access: RW 1211 */ 1212 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10); 1213 1214 /* SLDR - Switch LAG Descriptor Register 1215 * ----------------------------------------- 1216 * The switch LAG descriptor register is populated by LAG descriptors. 1217 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to 1218 * max_lag-1. 1219 */ 1220 #define MLXSW_REG_SLDR_ID 0x2014 1221 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */ 1222 1223 MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN); 1224 1225 enum mlxsw_reg_sldr_op { 1226 /* Indicates a creation of a new LAG-ID, lag_id must be valid */ 1227 MLXSW_REG_SLDR_OP_LAG_CREATE, 1228 MLXSW_REG_SLDR_OP_LAG_DESTROY, 1229 /* Ports that appear in the list have the Distributor enabled */ 1230 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST, 1231 /* Removes ports from the disributor list */ 1232 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST, 1233 }; 1234 1235 /* reg_sldr_op 1236 * Operation. 1237 * Access: RW 1238 */ 1239 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3); 1240 1241 /* reg_sldr_lag_id 1242 * LAG identifier. The lag_id is the index into the LAG descriptor table. 1243 * Access: Index 1244 */ 1245 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10); 1246 1247 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id) 1248 { 1249 MLXSW_REG_ZERO(sldr, payload); 1250 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE); 1251 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1252 } 1253 1254 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id) 1255 { 1256 MLXSW_REG_ZERO(sldr, payload); 1257 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY); 1258 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1259 } 1260 1261 /* reg_sldr_num_ports 1262 * The number of member ports of the LAG. 1263 * Reserved for Create / Destroy operations 1264 * For Add / Remove operations - indicates the number of ports in the list. 1265 * Access: RW 1266 */ 1267 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8); 1268 1269 /* reg_sldr_system_port 1270 * System port. 1271 * Access: RW 1272 */ 1273 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false); 1274 1275 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id, 1276 u16 local_port) 1277 { 1278 MLXSW_REG_ZERO(sldr, payload); 1279 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST); 1280 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1281 mlxsw_reg_sldr_num_ports_set(payload, 1); 1282 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1283 } 1284 1285 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id, 1286 u16 local_port) 1287 { 1288 MLXSW_REG_ZERO(sldr, payload); 1289 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST); 1290 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1291 mlxsw_reg_sldr_num_ports_set(payload, 1); 1292 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1293 } 1294 1295 /* SLCR - Switch LAG Configuration 2 Register 1296 * ------------------------------------------- 1297 * The Switch LAG Configuration register is used for configuring the 1298 * LAG properties of the switch. 1299 */ 1300 #define MLXSW_REG_SLCR_ID 0x2015 1301 #define MLXSW_REG_SLCR_LEN 0x10 1302 1303 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN); 1304 1305 enum mlxsw_reg_slcr_pp { 1306 /* Global Configuration (for all ports) */ 1307 MLXSW_REG_SLCR_PP_GLOBAL, 1308 /* Per port configuration, based on local_port field */ 1309 MLXSW_REG_SLCR_PP_PER_PORT, 1310 }; 1311 1312 /* reg_slcr_pp 1313 * Per Port Configuration 1314 * Note: Reading at Global mode results in reading port 1 configuration. 1315 * Access: Index 1316 */ 1317 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1); 1318 1319 /* reg_slcr_local_port 1320 * Local port number 1321 * Supported from CPU port 1322 * Not supported from router port 1323 * Reserved when pp = Global Configuration 1324 * Access: Index 1325 */ 1326 MLXSW_ITEM32_LP(reg, slcr, 0x00, 16, 0x00, 12); 1327 1328 enum mlxsw_reg_slcr_type { 1329 MLXSW_REG_SLCR_TYPE_CRC, /* default */ 1330 MLXSW_REG_SLCR_TYPE_XOR, 1331 MLXSW_REG_SLCR_TYPE_RANDOM, 1332 }; 1333 1334 /* reg_slcr_type 1335 * Hash type 1336 * Access: RW 1337 */ 1338 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4); 1339 1340 /* Ingress port */ 1341 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0) 1342 /* SMAC - for IPv4 and IPv6 packets */ 1343 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1) 1344 /* SMAC - for non-IP packets */ 1345 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2) 1346 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \ 1347 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \ 1348 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP) 1349 /* DMAC - for IPv4 and IPv6 packets */ 1350 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3) 1351 /* DMAC - for non-IP packets */ 1352 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4) 1353 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \ 1354 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \ 1355 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP) 1356 /* Ethertype - for IPv4 and IPv6 packets */ 1357 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5) 1358 /* Ethertype - for non-IP packets */ 1359 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6) 1360 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \ 1361 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \ 1362 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP) 1363 /* VLAN ID - for IPv4 and IPv6 packets */ 1364 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7) 1365 /* VLAN ID - for non-IP packets */ 1366 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8) 1367 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \ 1368 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \ 1369 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP) 1370 /* Source IP address (can be IPv4 or IPv6) */ 1371 #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9) 1372 /* Destination IP address (can be IPv4 or IPv6) */ 1373 #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10) 1374 /* TCP/UDP source port */ 1375 #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11) 1376 /* TCP/UDP destination port*/ 1377 #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12) 1378 /* IPv4 Protocol/IPv6 Next Header */ 1379 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13) 1380 /* IPv6 Flow label */ 1381 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14) 1382 /* SID - FCoE source ID */ 1383 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15) 1384 /* DID - FCoE destination ID */ 1385 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16) 1386 /* OXID - FCoE originator exchange ID */ 1387 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17) 1388 /* Destination QP number - for RoCE packets */ 1389 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19) 1390 1391 /* reg_slcr_lag_hash 1392 * LAG hashing configuration. This is a bitmask, in which each set 1393 * bit includes the corresponding item in the LAG hash calculation. 1394 * The default lag_hash contains SMAC, DMAC, VLANID and 1395 * Ethertype (for all packet types). 1396 * Access: RW 1397 */ 1398 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20); 1399 1400 /* reg_slcr_seed 1401 * LAG seed value. The seed is the same for all ports. 1402 * Access: RW 1403 */ 1404 MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32); 1405 1406 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed) 1407 { 1408 MLXSW_REG_ZERO(slcr, payload); 1409 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL); 1410 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC); 1411 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash); 1412 mlxsw_reg_slcr_seed_set(payload, seed); 1413 } 1414 1415 /* SLCOR - Switch LAG Collector Register 1416 * ------------------------------------- 1417 * The Switch LAG Collector register controls the Local Port membership 1418 * in a LAG and enablement of the collector. 1419 */ 1420 #define MLXSW_REG_SLCOR_ID 0x2016 1421 #define MLXSW_REG_SLCOR_LEN 0x10 1422 1423 MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN); 1424 1425 enum mlxsw_reg_slcor_col { 1426 /* Port is added with collector disabled */ 1427 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT, 1428 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED, 1429 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED, 1430 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT, 1431 }; 1432 1433 /* reg_slcor_col 1434 * Collector configuration 1435 * Access: RW 1436 */ 1437 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2); 1438 1439 /* reg_slcor_local_port 1440 * Local port number 1441 * Not supported for CPU port 1442 * Access: Index 1443 */ 1444 MLXSW_ITEM32_LP(reg, slcor, 0x00, 16, 0x00, 12); 1445 1446 /* reg_slcor_lag_id 1447 * LAG Identifier. Index into the LAG descriptor table. 1448 * Access: Index 1449 */ 1450 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10); 1451 1452 /* reg_slcor_port_index 1453 * Port index in the LAG list. Only valid on Add Port to LAG col. 1454 * Valid range is from 0 to cap_max_lag_members-1 1455 * Access: RW 1456 */ 1457 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10); 1458 1459 static inline void mlxsw_reg_slcor_pack(char *payload, 1460 u16 local_port, u16 lag_id, 1461 enum mlxsw_reg_slcor_col col) 1462 { 1463 MLXSW_REG_ZERO(slcor, payload); 1464 mlxsw_reg_slcor_col_set(payload, col); 1465 mlxsw_reg_slcor_local_port_set(payload, local_port); 1466 mlxsw_reg_slcor_lag_id_set(payload, lag_id); 1467 } 1468 1469 static inline void mlxsw_reg_slcor_port_add_pack(char *payload, 1470 u16 local_port, u16 lag_id, 1471 u8 port_index) 1472 { 1473 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1474 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT); 1475 mlxsw_reg_slcor_port_index_set(payload, port_index); 1476 } 1477 1478 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload, 1479 u16 local_port, u16 lag_id) 1480 { 1481 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1482 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT); 1483 } 1484 1485 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload, 1486 u16 local_port, u16 lag_id) 1487 { 1488 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1489 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1490 } 1491 1492 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload, 1493 u16 local_port, u16 lag_id) 1494 { 1495 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1496 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1497 } 1498 1499 /* SPMLR - Switch Port MAC Learning Register 1500 * ----------------------------------------- 1501 * Controls the Switch MAC learning policy per port. 1502 */ 1503 #define MLXSW_REG_SPMLR_ID 0x2018 1504 #define MLXSW_REG_SPMLR_LEN 0x8 1505 1506 MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN); 1507 1508 /* reg_spmlr_local_port 1509 * Local port number. 1510 * Access: Index 1511 */ 1512 MLXSW_ITEM32_LP(reg, spmlr, 0x00, 16, 0x00, 12); 1513 1514 /* reg_spmlr_sub_port 1515 * Virtual port within the physical port. 1516 * Should be set to 0 when virtual ports are not enabled on the port. 1517 * Access: Index 1518 */ 1519 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8); 1520 1521 enum mlxsw_reg_spmlr_learn_mode { 1522 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0, 1523 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2, 1524 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3, 1525 }; 1526 1527 /* reg_spmlr_learn_mode 1528 * Learning mode on the port. 1529 * 0 - Learning disabled. 1530 * 2 - Learning enabled. 1531 * 3 - Security mode. 1532 * 1533 * In security mode the switch does not learn MACs on the port, but uses the 1534 * SMAC to see if it exists on another ingress port. If so, the packet is 1535 * classified as a bad packet and is discarded unless the software registers 1536 * to receive port security error packets usign HPKT. 1537 */ 1538 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2); 1539 1540 static inline void mlxsw_reg_spmlr_pack(char *payload, u16 local_port, 1541 enum mlxsw_reg_spmlr_learn_mode mode) 1542 { 1543 MLXSW_REG_ZERO(spmlr, payload); 1544 mlxsw_reg_spmlr_local_port_set(payload, local_port); 1545 mlxsw_reg_spmlr_sub_port_set(payload, 0); 1546 mlxsw_reg_spmlr_learn_mode_set(payload, mode); 1547 } 1548 1549 /* SVFA - Switch VID to FID Allocation Register 1550 * -------------------------------------------- 1551 * Controls the VID to FID mapping and {Port, VID} to FID mapping for 1552 * virtualized ports. 1553 */ 1554 #define MLXSW_REG_SVFA_ID 0x201C 1555 #define MLXSW_REG_SVFA_LEN 0x18 1556 1557 MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN); 1558 1559 /* reg_svfa_swid 1560 * Switch partition ID. 1561 * Access: Index 1562 */ 1563 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8); 1564 1565 /* reg_svfa_local_port 1566 * Local port number. 1567 * Access: Index 1568 * 1569 * Note: Reserved for 802.1Q FIDs. 1570 */ 1571 MLXSW_ITEM32_LP(reg, svfa, 0x00, 16, 0x00, 12); 1572 1573 enum mlxsw_reg_svfa_mt { 1574 MLXSW_REG_SVFA_MT_VID_TO_FID, 1575 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, 1576 MLXSW_REG_SVFA_MT_VNI_TO_FID, 1577 }; 1578 1579 /* reg_svfa_mapping_table 1580 * Mapping table: 1581 * 0 - VID to FID 1582 * 1 - {Port, VID} to FID 1583 * Access: Index 1584 * 1585 * Note: Reserved for SwitchX-2. 1586 */ 1587 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3); 1588 1589 /* reg_svfa_v 1590 * Valid. 1591 * Valid if set. 1592 * Access: RW 1593 * 1594 * Note: Reserved for SwitchX-2. 1595 */ 1596 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1); 1597 1598 /* reg_svfa_fid 1599 * Filtering ID. 1600 * Access: RW 1601 */ 1602 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16); 1603 1604 /* reg_svfa_vid 1605 * VLAN ID. 1606 * Access: Index 1607 */ 1608 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12); 1609 1610 /* reg_svfa_counter_set_type 1611 * Counter set type for flow counters. 1612 * Access: RW 1613 * 1614 * Note: Reserved for SwitchX-2. 1615 */ 1616 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8); 1617 1618 /* reg_svfa_counter_index 1619 * Counter index for flow counters. 1620 * Access: RW 1621 * 1622 * Note: Reserved for SwitchX-2. 1623 */ 1624 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24); 1625 1626 /* reg_svfa_vni 1627 * Virtual Network Identifier. 1628 * Access: Index 1629 * 1630 * Note: Reserved when mapping_table is not 2 (VNI mapping table). 1631 */ 1632 MLXSW_ITEM32(reg, svfa, vni, 0x10, 0, 24); 1633 1634 /* reg_svfa_irif_v 1635 * Ingress RIF valid. 1636 * 0 - Ingress RIF is not valid, no ingress RIF assigned. 1637 * 1 - Ingress RIF valid. 1638 * Must not be set for a non enabled RIF. 1639 * Access: RW 1640 * 1641 * Note: Reserved when legacy bridge model is used. 1642 */ 1643 MLXSW_ITEM32(reg, svfa, irif_v, 0x14, 24, 1); 1644 1645 /* reg_svfa_irif 1646 * Ingress RIF (Router Interface). 1647 * Range is 0..cap_max_router_interfaces-1. 1648 * Access: RW 1649 * 1650 * Note: Reserved when legacy bridge model is used and when irif_v=0. 1651 */ 1652 MLXSW_ITEM32(reg, svfa, irif, 0x14, 0, 16); 1653 1654 static inline void __mlxsw_reg_svfa_pack(char *payload, 1655 enum mlxsw_reg_svfa_mt mt, bool valid, 1656 u16 fid) 1657 { 1658 MLXSW_REG_ZERO(svfa, payload); 1659 mlxsw_reg_svfa_swid_set(payload, 0); 1660 mlxsw_reg_svfa_mapping_table_set(payload, mt); 1661 mlxsw_reg_svfa_v_set(payload, valid); 1662 mlxsw_reg_svfa_fid_set(payload, fid); 1663 } 1664 1665 static inline void mlxsw_reg_svfa_port_vid_pack(char *payload, u16 local_port, 1666 bool valid, u16 fid, u16 vid) 1667 { 1668 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID; 1669 1670 __mlxsw_reg_svfa_pack(payload, mt, valid, fid); 1671 mlxsw_reg_svfa_local_port_set(payload, local_port); 1672 mlxsw_reg_svfa_vid_set(payload, vid); 1673 } 1674 1675 static inline void mlxsw_reg_svfa_vid_pack(char *payload, bool valid, u16 fid, 1676 u16 vid) 1677 { 1678 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_VID_TO_FID; 1679 1680 __mlxsw_reg_svfa_pack(payload, mt, valid, fid); 1681 mlxsw_reg_svfa_vid_set(payload, vid); 1682 } 1683 1684 static inline void mlxsw_reg_svfa_vni_pack(char *payload, bool valid, u16 fid, 1685 u32 vni) 1686 { 1687 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_VNI_TO_FID; 1688 1689 __mlxsw_reg_svfa_pack(payload, mt, valid, fid); 1690 mlxsw_reg_svfa_vni_set(payload, vni); 1691 } 1692 1693 /* SPVTR - Switch Port VLAN Stacking Register 1694 * ------------------------------------------ 1695 * The Switch Port VLAN Stacking register configures the VLAN mode of the port 1696 * to enable VLAN stacking. 1697 */ 1698 #define MLXSW_REG_SPVTR_ID 0x201D 1699 #define MLXSW_REG_SPVTR_LEN 0x10 1700 1701 MLXSW_REG_DEFINE(spvtr, MLXSW_REG_SPVTR_ID, MLXSW_REG_SPVTR_LEN); 1702 1703 /* reg_spvtr_tport 1704 * Port is tunnel port. 1705 * Access: Index 1706 * 1707 * Note: Reserved when SwitchX/-2 or Spectrum-1. 1708 */ 1709 MLXSW_ITEM32(reg, spvtr, tport, 0x00, 24, 1); 1710 1711 /* reg_spvtr_local_port 1712 * When tport = 0: local port number (Not supported from/to CPU). 1713 * When tport = 1: tunnel port. 1714 * Access: Index 1715 */ 1716 MLXSW_ITEM32_LP(reg, spvtr, 0x00, 16, 0x00, 12); 1717 1718 /* reg_spvtr_ippe 1719 * Ingress Port Prio Mode Update Enable. 1720 * When set, the Port Prio Mode is updated with the provided ipprio_mode field. 1721 * Reserved on Get operations. 1722 * Access: OP 1723 */ 1724 MLXSW_ITEM32(reg, spvtr, ippe, 0x04, 31, 1); 1725 1726 /* reg_spvtr_ipve 1727 * Ingress Port VID Mode Update Enable. 1728 * When set, the Ingress Port VID Mode is updated with the provided ipvid_mode 1729 * field. 1730 * Reserved on Get operations. 1731 * Access: OP 1732 */ 1733 MLXSW_ITEM32(reg, spvtr, ipve, 0x04, 30, 1); 1734 1735 /* reg_spvtr_epve 1736 * Egress Port VID Mode Update Enable. 1737 * When set, the Egress Port VID Mode is updated with the provided epvid_mode 1738 * field. 1739 * Access: OP 1740 */ 1741 MLXSW_ITEM32(reg, spvtr, epve, 0x04, 29, 1); 1742 1743 /* reg_spvtr_ipprio_mode 1744 * Ingress Port Priority Mode. 1745 * This controls the PCP and DEI of the new outer VLAN 1746 * Note: for SwitchX/-2 the DEI is not affected. 1747 * 0: use port default PCP and DEI (configured by QPDPC). 1748 * 1: use C-VLAN PCP and DEI. 1749 * Has no effect when ipvid_mode = 0. 1750 * Reserved when tport = 1. 1751 * Access: RW 1752 */ 1753 MLXSW_ITEM32(reg, spvtr, ipprio_mode, 0x04, 20, 4); 1754 1755 enum mlxsw_reg_spvtr_ipvid_mode { 1756 /* IEEE Compliant PVID (default) */ 1757 MLXSW_REG_SPVTR_IPVID_MODE_IEEE_COMPLIANT_PVID, 1758 /* Push VLAN (for VLAN stacking, except prio tagged packets) */ 1759 MLXSW_REG_SPVTR_IPVID_MODE_PUSH_VLAN_FOR_UNTAGGED_PACKET, 1760 /* Always push VLAN (also for prio tagged packets) */ 1761 MLXSW_REG_SPVTR_IPVID_MODE_ALWAYS_PUSH_VLAN, 1762 }; 1763 1764 /* reg_spvtr_ipvid_mode 1765 * Ingress Port VLAN-ID Mode. 1766 * For Spectrum family, this affects the values of SPVM.i 1767 * Access: RW 1768 */ 1769 MLXSW_ITEM32(reg, spvtr, ipvid_mode, 0x04, 16, 4); 1770 1771 enum mlxsw_reg_spvtr_epvid_mode { 1772 /* IEEE Compliant VLAN membership */ 1773 MLXSW_REG_SPVTR_EPVID_MODE_IEEE_COMPLIANT_VLAN_MEMBERSHIP, 1774 /* Pop VLAN (for VLAN stacking) */ 1775 MLXSW_REG_SPVTR_EPVID_MODE_POP_VLAN, 1776 }; 1777 1778 /* reg_spvtr_epvid_mode 1779 * Egress Port VLAN-ID Mode. 1780 * For Spectrum family, this affects the values of SPVM.e,u,pt. 1781 * Access: WO 1782 */ 1783 MLXSW_ITEM32(reg, spvtr, epvid_mode, 0x04, 0, 4); 1784 1785 static inline void mlxsw_reg_spvtr_pack(char *payload, bool tport, 1786 u16 local_port, 1787 enum mlxsw_reg_spvtr_ipvid_mode ipvid_mode) 1788 { 1789 MLXSW_REG_ZERO(spvtr, payload); 1790 mlxsw_reg_spvtr_tport_set(payload, tport); 1791 mlxsw_reg_spvtr_local_port_set(payload, local_port); 1792 mlxsw_reg_spvtr_ipvid_mode_set(payload, ipvid_mode); 1793 mlxsw_reg_spvtr_ipve_set(payload, true); 1794 } 1795 1796 /* SVPE - Switch Virtual-Port Enabling Register 1797 * -------------------------------------------- 1798 * Enables port virtualization. 1799 */ 1800 #define MLXSW_REG_SVPE_ID 0x201E 1801 #define MLXSW_REG_SVPE_LEN 0x4 1802 1803 MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN); 1804 1805 /* reg_svpe_local_port 1806 * Local port number 1807 * Access: Index 1808 * 1809 * Note: CPU port is not supported (uses VLAN mode only). 1810 */ 1811 MLXSW_ITEM32_LP(reg, svpe, 0x00, 16, 0x00, 12); 1812 1813 /* reg_svpe_vp_en 1814 * Virtual port enable. 1815 * 0 - Disable, VLAN mode (VID to FID). 1816 * 1 - Enable, Virtual port mode ({Port, VID} to FID). 1817 * Access: RW 1818 */ 1819 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1); 1820 1821 static inline void mlxsw_reg_svpe_pack(char *payload, u16 local_port, 1822 bool enable) 1823 { 1824 MLXSW_REG_ZERO(svpe, payload); 1825 mlxsw_reg_svpe_local_port_set(payload, local_port); 1826 mlxsw_reg_svpe_vp_en_set(payload, enable); 1827 } 1828 1829 /* SFMR - Switch FID Management Register 1830 * ------------------------------------- 1831 * Creates and configures FIDs. 1832 */ 1833 #define MLXSW_REG_SFMR_ID 0x201F 1834 #define MLXSW_REG_SFMR_LEN 0x30 1835 1836 MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN); 1837 1838 enum mlxsw_reg_sfmr_op { 1839 MLXSW_REG_SFMR_OP_CREATE_FID, 1840 MLXSW_REG_SFMR_OP_DESTROY_FID, 1841 }; 1842 1843 /* reg_sfmr_op 1844 * Operation. 1845 * 0 - Create or edit FID. 1846 * 1 - Destroy FID. 1847 * Access: WO 1848 */ 1849 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4); 1850 1851 /* reg_sfmr_fid 1852 * Filtering ID. 1853 * Access: Index 1854 */ 1855 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16); 1856 1857 /* reg_sfmr_flood_rsp 1858 * Router sub-port flooding table. 1859 * 0 - Regular flooding table. 1860 * 1 - Router sub-port flooding table. For this FID the flooding is per 1861 * router-sub-port local_port. Must not be set for a FID which is not a 1862 * router-sub-port and must be set prior to enabling the relevant RIF. 1863 * Access: RW 1864 * 1865 * Note: Reserved when legacy bridge model is used. 1866 */ 1867 MLXSW_ITEM32(reg, sfmr, flood_rsp, 0x08, 31, 1); 1868 1869 /* reg_sfmr_flood_bridge_type 1870 * Flood bridge type (see SFGC.bridge_type). 1871 * 0 - type_0. 1872 * 1 - type_1. 1873 * Access: RW 1874 * 1875 * Note: Reserved when legacy bridge model is used and when flood_rsp=1. 1876 */ 1877 MLXSW_ITEM32(reg, sfmr, flood_bridge_type, 0x08, 28, 1); 1878 1879 /* reg_sfmr_fid_offset 1880 * FID offset. 1881 * Used to point into the flooding table selected by SFGC register if 1882 * the table is of type FID-Offset. Otherwise, this field is reserved. 1883 * Access: RW 1884 */ 1885 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16); 1886 1887 /* reg_sfmr_vtfp 1888 * Valid Tunnel Flood Pointer. 1889 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL. 1890 * Access: RW 1891 * 1892 * Note: Reserved for 802.1Q FIDs. 1893 */ 1894 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1); 1895 1896 /* reg_sfmr_nve_tunnel_flood_ptr 1897 * Underlay Flooding and BC Pointer. 1898 * Used as a pointer to the first entry of the group based link lists of 1899 * flooding or BC entries (for NVE tunnels). 1900 * Access: RW 1901 */ 1902 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24); 1903 1904 /* reg_sfmr_vv 1905 * VNI Valid. 1906 * If not set, then vni is reserved. 1907 * Access: RW 1908 * 1909 * Note: Reserved for 802.1Q FIDs. 1910 */ 1911 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1); 1912 1913 /* reg_sfmr_vni 1914 * Virtual Network Identifier. 1915 * When legacy bridge model is used, a given VNI can only be assigned to one 1916 * FID. When unified bridge model is used, it configures only the FID->VNI, 1917 * the VNI->FID is done by SVFA. 1918 * Access: RW 1919 */ 1920 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24); 1921 1922 /* reg_sfmr_irif_v 1923 * Ingress RIF valid. 1924 * 0 - Ingress RIF is not valid, no ingress RIF assigned. 1925 * 1 - Ingress RIF valid. 1926 * Must not be set for a non valid RIF. 1927 * Access: RW 1928 * 1929 * Note: Reserved when legacy bridge model is used. 1930 */ 1931 MLXSW_ITEM32(reg, sfmr, irif_v, 0x14, 24, 1); 1932 1933 /* reg_sfmr_irif 1934 * Ingress RIF (Router Interface). 1935 * Range is 0..cap_max_router_interfaces-1. 1936 * Access: RW 1937 * 1938 * Note: Reserved when legacy bridge model is used and when irif_v=0. 1939 */ 1940 MLXSW_ITEM32(reg, sfmr, irif, 0x14, 0, 16); 1941 1942 /* reg_sfmr_smpe_valid 1943 * SMPE is valid. 1944 * Access: RW 1945 * 1946 * Note: Reserved when legacy bridge model is used, when flood_rsp=1 and on 1947 * Spectrum-1. 1948 */ 1949 MLXSW_ITEM32(reg, sfmr, smpe_valid, 0x28, 20, 1); 1950 1951 /* reg_sfmr_smpe 1952 * Switch multicast port to egress VID. 1953 * Range is 0..cap_max_rmpe-1 1954 * Access: RW 1955 * 1956 * Note: Reserved when legacy bridge model is used, when flood_rsp=1 and on 1957 * Spectrum-1. 1958 */ 1959 MLXSW_ITEM32(reg, sfmr, smpe, 0x28, 0, 16); 1960 1961 static inline void mlxsw_reg_sfmr_pack(char *payload, 1962 enum mlxsw_reg_sfmr_op op, u16 fid, 1963 u16 fid_offset) 1964 { 1965 MLXSW_REG_ZERO(sfmr, payload); 1966 mlxsw_reg_sfmr_op_set(payload, op); 1967 mlxsw_reg_sfmr_fid_set(payload, fid); 1968 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset); 1969 mlxsw_reg_sfmr_vtfp_set(payload, false); 1970 mlxsw_reg_sfmr_vv_set(payload, false); 1971 } 1972 1973 /* SPVMLR - Switch Port VLAN MAC Learning Register 1974 * ----------------------------------------------- 1975 * Controls the switch MAC learning policy per {Port, VID}. 1976 */ 1977 #define MLXSW_REG_SPVMLR_ID 0x2020 1978 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */ 1979 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */ 1980 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255 1981 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \ 1982 MLXSW_REG_SPVMLR_REC_LEN * \ 1983 MLXSW_REG_SPVMLR_REC_MAX_COUNT) 1984 1985 MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN); 1986 1987 /* reg_spvmlr_local_port 1988 * Local ingress port. 1989 * Access: Index 1990 * 1991 * Note: CPU port is not supported. 1992 */ 1993 MLXSW_ITEM32_LP(reg, spvmlr, 0x00, 16, 0x00, 12); 1994 1995 /* reg_spvmlr_num_rec 1996 * Number of records to update. 1997 * Access: OP 1998 */ 1999 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8); 2000 2001 /* reg_spvmlr_rec_learn_enable 2002 * 0 - Disable learning for {Port, VID}. 2003 * 1 - Enable learning for {Port, VID}. 2004 * Access: RW 2005 */ 2006 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN, 2007 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 2008 2009 /* reg_spvmlr_rec_vid 2010 * VLAN ID to be added/removed from port or for querying. 2011 * Access: Index 2012 */ 2013 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12, 2014 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 2015 2016 static inline void mlxsw_reg_spvmlr_pack(char *payload, u16 local_port, 2017 u16 vid_begin, u16 vid_end, 2018 bool learn_enable) 2019 { 2020 int num_rec = vid_end - vid_begin + 1; 2021 int i; 2022 2023 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT); 2024 2025 MLXSW_REG_ZERO(spvmlr, payload); 2026 mlxsw_reg_spvmlr_local_port_set(payload, local_port); 2027 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec); 2028 2029 for (i = 0; i < num_rec; i++) { 2030 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable); 2031 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i); 2032 } 2033 } 2034 2035 /* SPVC - Switch Port VLAN Classification Register 2036 * ----------------------------------------------- 2037 * Configures the port to identify packets as untagged / single tagged / 2038 * double packets based on the packet EtherTypes. 2039 * Ethertype IDs are configured by SVER. 2040 */ 2041 #define MLXSW_REG_SPVC_ID 0x2026 2042 #define MLXSW_REG_SPVC_LEN 0x0C 2043 2044 MLXSW_REG_DEFINE(spvc, MLXSW_REG_SPVC_ID, MLXSW_REG_SPVC_LEN); 2045 2046 /* reg_spvc_local_port 2047 * Local port. 2048 * Access: Index 2049 * 2050 * Note: applies both to Rx port and Tx port, so if a packet traverses 2051 * through Rx port i and a Tx port j then port i and port j must have the 2052 * same configuration. 2053 */ 2054 MLXSW_ITEM32_LP(reg, spvc, 0x00, 16, 0x00, 12); 2055 2056 /* reg_spvc_inner_et2 2057 * Vlan Tag1 EtherType2 enable. 2058 * Packet is initially classified as double VLAN Tag if in addition to 2059 * being classified with a tag0 VLAN Tag its tag1 EtherType value is 2060 * equal to ether_type2. 2061 * 0: disable (default) 2062 * 1: enable 2063 * Access: RW 2064 */ 2065 MLXSW_ITEM32(reg, spvc, inner_et2, 0x08, 17, 1); 2066 2067 /* reg_spvc_et2 2068 * Vlan Tag0 EtherType2 enable. 2069 * Packet is initially classified as VLAN Tag if its tag0 EtherType is 2070 * equal to ether_type2. 2071 * 0: disable (default) 2072 * 1: enable 2073 * Access: RW 2074 */ 2075 MLXSW_ITEM32(reg, spvc, et2, 0x08, 16, 1); 2076 2077 /* reg_spvc_inner_et1 2078 * Vlan Tag1 EtherType1 enable. 2079 * Packet is initially classified as double VLAN Tag if in addition to 2080 * being classified with a tag0 VLAN Tag its tag1 EtherType value is 2081 * equal to ether_type1. 2082 * 0: disable 2083 * 1: enable (default) 2084 * Access: RW 2085 */ 2086 MLXSW_ITEM32(reg, spvc, inner_et1, 0x08, 9, 1); 2087 2088 /* reg_spvc_et1 2089 * Vlan Tag0 EtherType1 enable. 2090 * Packet is initially classified as VLAN Tag if its tag0 EtherType is 2091 * equal to ether_type1. 2092 * 0: disable 2093 * 1: enable (default) 2094 * Access: RW 2095 */ 2096 MLXSW_ITEM32(reg, spvc, et1, 0x08, 8, 1); 2097 2098 /* reg_inner_et0 2099 * Vlan Tag1 EtherType0 enable. 2100 * Packet is initially classified as double VLAN Tag if in addition to 2101 * being classified with a tag0 VLAN Tag its tag1 EtherType value is 2102 * equal to ether_type0. 2103 * 0: disable 2104 * 1: enable (default) 2105 * Access: RW 2106 */ 2107 MLXSW_ITEM32(reg, spvc, inner_et0, 0x08, 1, 1); 2108 2109 /* reg_et0 2110 * Vlan Tag0 EtherType0 enable. 2111 * Packet is initially classified as VLAN Tag if its tag0 EtherType is 2112 * equal to ether_type0. 2113 * 0: disable 2114 * 1: enable (default) 2115 * Access: RW 2116 */ 2117 MLXSW_ITEM32(reg, spvc, et0, 0x08, 0, 1); 2118 2119 static inline void mlxsw_reg_spvc_pack(char *payload, u16 local_port, bool et1, 2120 bool et0) 2121 { 2122 MLXSW_REG_ZERO(spvc, payload); 2123 mlxsw_reg_spvc_local_port_set(payload, local_port); 2124 /* Enable inner_et1 and inner_et0 to enable identification of double 2125 * tagged packets. 2126 */ 2127 mlxsw_reg_spvc_inner_et1_set(payload, 1); 2128 mlxsw_reg_spvc_inner_et0_set(payload, 1); 2129 mlxsw_reg_spvc_et1_set(payload, et1); 2130 mlxsw_reg_spvc_et0_set(payload, et0); 2131 } 2132 2133 /* SPEVET - Switch Port Egress VLAN EtherType 2134 * ------------------------------------------ 2135 * The switch port egress VLAN EtherType configures which EtherType to push at 2136 * egress for packets incoming through a local port for which 'SPVID.egr_et_set' 2137 * is set. 2138 */ 2139 #define MLXSW_REG_SPEVET_ID 0x202A 2140 #define MLXSW_REG_SPEVET_LEN 0x08 2141 2142 MLXSW_REG_DEFINE(spevet, MLXSW_REG_SPEVET_ID, MLXSW_REG_SPEVET_LEN); 2143 2144 /* reg_spevet_local_port 2145 * Egress Local port number. 2146 * Not supported to CPU port. 2147 * Access: Index 2148 */ 2149 MLXSW_ITEM32_LP(reg, spevet, 0x00, 16, 0x00, 12); 2150 2151 /* reg_spevet_et_vlan 2152 * Egress EtherType VLAN to push when SPVID.egr_et_set field set for the packet: 2153 * 0: ether_type0 - (default) 2154 * 1: ether_type1 2155 * 2: ether_type2 2156 * Access: RW 2157 */ 2158 MLXSW_ITEM32(reg, spevet, et_vlan, 0x04, 16, 2); 2159 2160 static inline void mlxsw_reg_spevet_pack(char *payload, u16 local_port, 2161 u8 et_vlan) 2162 { 2163 MLXSW_REG_ZERO(spevet, payload); 2164 mlxsw_reg_spevet_local_port_set(payload, local_port); 2165 mlxsw_reg_spevet_et_vlan_set(payload, et_vlan); 2166 } 2167 2168 /* SMPE - Switch Multicast Port to Egress VID 2169 * ------------------------------------------ 2170 * The switch multicast port to egress VID maps 2171 * {egress_port, SMPE index} -> {VID}. 2172 */ 2173 #define MLXSW_REG_SMPE_ID 0x202B 2174 #define MLXSW_REG_SMPE_LEN 0x0C 2175 2176 MLXSW_REG_DEFINE(smpe, MLXSW_REG_SMPE_ID, MLXSW_REG_SMPE_LEN); 2177 2178 /* reg_smpe_local_port 2179 * Local port number. 2180 * CPU port is not supported. 2181 * Access: Index 2182 */ 2183 MLXSW_ITEM32_LP(reg, smpe, 0x00, 16, 0x00, 12); 2184 2185 /* reg_smpe_smpe_index 2186 * Switch multicast port to egress VID. 2187 * Range is 0..cap_max_rmpe-1. 2188 * Access: Index 2189 */ 2190 MLXSW_ITEM32(reg, smpe, smpe_index, 0x04, 0, 16); 2191 2192 /* reg_smpe_evid 2193 * Egress VID. 2194 * Access: RW 2195 */ 2196 MLXSW_ITEM32(reg, smpe, evid, 0x08, 0, 12); 2197 2198 static inline void mlxsw_reg_smpe_pack(char *payload, u16 local_port, 2199 u16 smpe_index, u16 evid) 2200 { 2201 MLXSW_REG_ZERO(smpe, payload); 2202 mlxsw_reg_smpe_local_port_set(payload, local_port); 2203 mlxsw_reg_smpe_smpe_index_set(payload, smpe_index); 2204 mlxsw_reg_smpe_evid_set(payload, evid); 2205 } 2206 2207 /* SFTR-V2 - Switch Flooding Table Version 2 Register 2208 * -------------------------------------------------- 2209 * The switch flooding table is used for flooding packet replication. The table 2210 * defines a bit mask of ports for packet replication. 2211 */ 2212 #define MLXSW_REG_SFTR2_ID 0x202F 2213 #define MLXSW_REG_SFTR2_LEN 0x120 2214 2215 MLXSW_REG_DEFINE(sftr2, MLXSW_REG_SFTR2_ID, MLXSW_REG_SFTR2_LEN); 2216 2217 /* reg_sftr2_swid 2218 * Switch partition ID with which to associate the port. 2219 * Access: Index 2220 */ 2221 MLXSW_ITEM32(reg, sftr2, swid, 0x00, 24, 8); 2222 2223 /* reg_sftr2_flood_table 2224 * Flooding table index to associate with the specific type on the specific 2225 * switch partition. 2226 * Access: Index 2227 */ 2228 MLXSW_ITEM32(reg, sftr2, flood_table, 0x00, 16, 6); 2229 2230 /* reg_sftr2_index 2231 * Index. Used as an index into the Flooding Table in case the table is 2232 * configured to use VID / FID or FID Offset. 2233 * Access: Index 2234 */ 2235 MLXSW_ITEM32(reg, sftr2, index, 0x00, 0, 16); 2236 2237 /* reg_sftr2_table_type 2238 * See mlxsw_flood_table_type 2239 * Access: RW 2240 */ 2241 MLXSW_ITEM32(reg, sftr2, table_type, 0x04, 16, 3); 2242 2243 /* reg_sftr2_range 2244 * Range of entries to update 2245 * Access: Index 2246 */ 2247 MLXSW_ITEM32(reg, sftr2, range, 0x04, 0, 16); 2248 2249 /* reg_sftr2_port 2250 * Local port membership (1 bit per port). 2251 * Access: RW 2252 */ 2253 MLXSW_ITEM_BIT_ARRAY(reg, sftr2, port, 0x20, 0x80, 1); 2254 2255 /* reg_sftr2_port_mask 2256 * Local port mask (1 bit per port). 2257 * Access: WO 2258 */ 2259 MLXSW_ITEM_BIT_ARRAY(reg, sftr2, port_mask, 0xA0, 0x80, 1); 2260 2261 static inline void mlxsw_reg_sftr2_pack(char *payload, 2262 unsigned int flood_table, 2263 unsigned int index, 2264 enum mlxsw_flood_table_type table_type, 2265 unsigned int range, u16 port, bool set) 2266 { 2267 MLXSW_REG_ZERO(sftr2, payload); 2268 mlxsw_reg_sftr2_swid_set(payload, 0); 2269 mlxsw_reg_sftr2_flood_table_set(payload, flood_table); 2270 mlxsw_reg_sftr2_index_set(payload, index); 2271 mlxsw_reg_sftr2_table_type_set(payload, table_type); 2272 mlxsw_reg_sftr2_range_set(payload, range); 2273 mlxsw_reg_sftr2_port_set(payload, port, set); 2274 mlxsw_reg_sftr2_port_mask_set(payload, port, 1); 2275 } 2276 2277 /* SMID-V2 - Switch Multicast ID Version 2 Register 2278 * ------------------------------------------------ 2279 * The MID record maps from a MID (Multicast ID), which is a unique identifier 2280 * of the multicast group within the stacking domain, into a list of local 2281 * ports into which the packet is replicated. 2282 */ 2283 #define MLXSW_REG_SMID2_ID 0x2034 2284 #define MLXSW_REG_SMID2_LEN 0x120 2285 2286 MLXSW_REG_DEFINE(smid2, MLXSW_REG_SMID2_ID, MLXSW_REG_SMID2_LEN); 2287 2288 /* reg_smid2_swid 2289 * Switch partition ID. 2290 * Access: Index 2291 */ 2292 MLXSW_ITEM32(reg, smid2, swid, 0x00, 24, 8); 2293 2294 /* reg_smid2_mid 2295 * Multicast identifier - global identifier that represents the multicast group 2296 * across all devices. 2297 * Access: Index 2298 */ 2299 MLXSW_ITEM32(reg, smid2, mid, 0x00, 0, 16); 2300 2301 /* reg_smid2_smpe_valid 2302 * SMPE is valid. 2303 * When not valid, the egress VID will not be modified by the SMPE table. 2304 * Access: RW 2305 * 2306 * Note: Reserved when legacy bridge model is used and on Spectrum-2. 2307 */ 2308 MLXSW_ITEM32(reg, smid2, smpe_valid, 0x08, 20, 1); 2309 2310 /* reg_smid2_smpe 2311 * Switch multicast port to egress VID. 2312 * Access: RW 2313 * 2314 * Note: Reserved when legacy bridge model is used and on Spectrum-2. 2315 */ 2316 MLXSW_ITEM32(reg, smid2, smpe, 0x08, 0, 16); 2317 2318 /* reg_smid2_port 2319 * Local port memebership (1 bit per port). 2320 * Access: RW 2321 */ 2322 MLXSW_ITEM_BIT_ARRAY(reg, smid2, port, 0x20, 0x80, 1); 2323 2324 /* reg_smid2_port_mask 2325 * Local port mask (1 bit per port). 2326 * Access: WO 2327 */ 2328 MLXSW_ITEM_BIT_ARRAY(reg, smid2, port_mask, 0xA0, 0x80, 1); 2329 2330 static inline void mlxsw_reg_smid2_pack(char *payload, u16 mid, u16 port, 2331 bool set, bool smpe_valid, u16 smpe) 2332 { 2333 MLXSW_REG_ZERO(smid2, payload); 2334 mlxsw_reg_smid2_swid_set(payload, 0); 2335 mlxsw_reg_smid2_mid_set(payload, mid); 2336 mlxsw_reg_smid2_port_set(payload, port, set); 2337 mlxsw_reg_smid2_port_mask_set(payload, port, 1); 2338 mlxsw_reg_smid2_smpe_valid_set(payload, smpe_valid); 2339 mlxsw_reg_smid2_smpe_set(payload, smpe_valid ? smpe : 0); 2340 } 2341 2342 /* CWTP - Congetion WRED ECN TClass Profile 2343 * ---------------------------------------- 2344 * Configures the profiles for queues of egress port and traffic class 2345 */ 2346 #define MLXSW_REG_CWTP_ID 0x2802 2347 #define MLXSW_REG_CWTP_BASE_LEN 0x28 2348 #define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08 2349 #define MLXSW_REG_CWTP_LEN 0x40 2350 2351 MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN); 2352 2353 /* reg_cwtp_local_port 2354 * Local port number 2355 * Not supported for CPU port 2356 * Access: Index 2357 */ 2358 MLXSW_ITEM32_LP(reg, cwtp, 0x00, 16, 0x00, 12); 2359 2360 /* reg_cwtp_traffic_class 2361 * Traffic Class to configure 2362 * Access: Index 2363 */ 2364 MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8); 2365 2366 /* reg_cwtp_profile_min 2367 * Minimum Average Queue Size of the profile in cells. 2368 * Access: RW 2369 */ 2370 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN, 2371 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false); 2372 2373 /* reg_cwtp_profile_percent 2374 * Percentage of WRED and ECN marking for maximum Average Queue size 2375 * Range is 0 to 100, units of integer percentage 2376 * Access: RW 2377 */ 2378 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN, 2379 24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 2380 2381 /* reg_cwtp_profile_max 2382 * Maximum Average Queue size of the profile in cells 2383 * Access: RW 2384 */ 2385 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN, 2386 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 2387 2388 #define MLXSW_REG_CWTP_MIN_VALUE 64 2389 #define MLXSW_REG_CWTP_MAX_PROFILE 2 2390 #define MLXSW_REG_CWTP_DEFAULT_PROFILE 1 2391 2392 static inline void mlxsw_reg_cwtp_pack(char *payload, u16 local_port, 2393 u8 traffic_class) 2394 { 2395 int i; 2396 2397 MLXSW_REG_ZERO(cwtp, payload); 2398 mlxsw_reg_cwtp_local_port_set(payload, local_port); 2399 mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class); 2400 2401 for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) { 2402 mlxsw_reg_cwtp_profile_min_set(payload, i, 2403 MLXSW_REG_CWTP_MIN_VALUE); 2404 mlxsw_reg_cwtp_profile_max_set(payload, i, 2405 MLXSW_REG_CWTP_MIN_VALUE); 2406 } 2407 } 2408 2409 #define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1) 2410 2411 static inline void 2412 mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max, 2413 u32 probability) 2414 { 2415 u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile); 2416 2417 mlxsw_reg_cwtp_profile_min_set(payload, index, min); 2418 mlxsw_reg_cwtp_profile_max_set(payload, index, max); 2419 mlxsw_reg_cwtp_profile_percent_set(payload, index, probability); 2420 } 2421 2422 /* CWTPM - Congestion WRED ECN TClass and Pool Mapping 2423 * --------------------------------------------------- 2424 * The CWTPM register maps each egress port and traffic class to profile num. 2425 */ 2426 #define MLXSW_REG_CWTPM_ID 0x2803 2427 #define MLXSW_REG_CWTPM_LEN 0x44 2428 2429 MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN); 2430 2431 /* reg_cwtpm_local_port 2432 * Local port number 2433 * Not supported for CPU port 2434 * Access: Index 2435 */ 2436 MLXSW_ITEM32_LP(reg, cwtpm, 0x00, 16, 0x00, 12); 2437 2438 /* reg_cwtpm_traffic_class 2439 * Traffic Class to configure 2440 * Access: Index 2441 */ 2442 MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8); 2443 2444 /* reg_cwtpm_ew 2445 * Control enablement of WRED for traffic class: 2446 * 0 - Disable 2447 * 1 - Enable 2448 * Access: RW 2449 */ 2450 MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1); 2451 2452 /* reg_cwtpm_ee 2453 * Control enablement of ECN for traffic class: 2454 * 0 - Disable 2455 * 1 - Enable 2456 * Access: RW 2457 */ 2458 MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1); 2459 2460 /* reg_cwtpm_tcp_g 2461 * TCP Green Profile. 2462 * Index of the profile within {port, traffic class} to use. 2463 * 0 for disabling both WRED and ECN for this type of traffic. 2464 * Access: RW 2465 */ 2466 MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2); 2467 2468 /* reg_cwtpm_tcp_y 2469 * TCP Yellow Profile. 2470 * Index of the profile within {port, traffic class} to use. 2471 * 0 for disabling both WRED and ECN for this type of traffic. 2472 * Access: RW 2473 */ 2474 MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2); 2475 2476 /* reg_cwtpm_tcp_r 2477 * TCP Red Profile. 2478 * Index of the profile within {port, traffic class} to use. 2479 * 0 for disabling both WRED and ECN for this type of traffic. 2480 * Access: RW 2481 */ 2482 MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2); 2483 2484 /* reg_cwtpm_ntcp_g 2485 * Non-TCP Green Profile. 2486 * Index of the profile within {port, traffic class} to use. 2487 * 0 for disabling both WRED and ECN for this type of traffic. 2488 * Access: RW 2489 */ 2490 MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2); 2491 2492 /* reg_cwtpm_ntcp_y 2493 * Non-TCP Yellow Profile. 2494 * Index of the profile within {port, traffic class} to use. 2495 * 0 for disabling both WRED and ECN for this type of traffic. 2496 * Access: RW 2497 */ 2498 MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2); 2499 2500 /* reg_cwtpm_ntcp_r 2501 * Non-TCP Red Profile. 2502 * Index of the profile within {port, traffic class} to use. 2503 * 0 for disabling both WRED and ECN for this type of traffic. 2504 * Access: RW 2505 */ 2506 MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2); 2507 2508 #define MLXSW_REG_CWTPM_RESET_PROFILE 0 2509 2510 static inline void mlxsw_reg_cwtpm_pack(char *payload, u16 local_port, 2511 u8 traffic_class, u8 profile, 2512 bool wred, bool ecn) 2513 { 2514 MLXSW_REG_ZERO(cwtpm, payload); 2515 mlxsw_reg_cwtpm_local_port_set(payload, local_port); 2516 mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class); 2517 mlxsw_reg_cwtpm_ew_set(payload, wred); 2518 mlxsw_reg_cwtpm_ee_set(payload, ecn); 2519 mlxsw_reg_cwtpm_tcp_g_set(payload, profile); 2520 mlxsw_reg_cwtpm_tcp_y_set(payload, profile); 2521 mlxsw_reg_cwtpm_tcp_r_set(payload, profile); 2522 mlxsw_reg_cwtpm_ntcp_g_set(payload, profile); 2523 mlxsw_reg_cwtpm_ntcp_y_set(payload, profile); 2524 mlxsw_reg_cwtpm_ntcp_r_set(payload, profile); 2525 } 2526 2527 /* PGCR - Policy-Engine General Configuration Register 2528 * --------------------------------------------------- 2529 * This register configures general Policy-Engine settings. 2530 */ 2531 #define MLXSW_REG_PGCR_ID 0x3001 2532 #define MLXSW_REG_PGCR_LEN 0x20 2533 2534 MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN); 2535 2536 /* reg_pgcr_default_action_pointer_base 2537 * Default action pointer base. Each region has a default action pointer 2538 * which is equal to default_action_pointer_base + region_id. 2539 * Access: RW 2540 */ 2541 MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24); 2542 2543 static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base) 2544 { 2545 MLXSW_REG_ZERO(pgcr, payload); 2546 mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base); 2547 } 2548 2549 /* PPBT - Policy-Engine Port Binding Table 2550 * --------------------------------------- 2551 * This register is used for configuration of the Port Binding Table. 2552 */ 2553 #define MLXSW_REG_PPBT_ID 0x3002 2554 #define MLXSW_REG_PPBT_LEN 0x14 2555 2556 MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN); 2557 2558 enum mlxsw_reg_pxbt_e { 2559 MLXSW_REG_PXBT_E_IACL, 2560 MLXSW_REG_PXBT_E_EACL, 2561 }; 2562 2563 /* reg_ppbt_e 2564 * Access: Index 2565 */ 2566 MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1); 2567 2568 enum mlxsw_reg_pxbt_op { 2569 MLXSW_REG_PXBT_OP_BIND, 2570 MLXSW_REG_PXBT_OP_UNBIND, 2571 }; 2572 2573 /* reg_ppbt_op 2574 * Access: RW 2575 */ 2576 MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3); 2577 2578 /* reg_ppbt_local_port 2579 * Local port. Not including CPU port. 2580 * Access: Index 2581 */ 2582 MLXSW_ITEM32_LP(reg, ppbt, 0x00, 16, 0x00, 12); 2583 2584 /* reg_ppbt_g 2585 * group - When set, the binding is of an ACL group. When cleared, 2586 * the binding is of an ACL. 2587 * Must be set to 1 for Spectrum. 2588 * Access: RW 2589 */ 2590 MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1); 2591 2592 /* reg_ppbt_acl_info 2593 * ACL/ACL group identifier. If the g bit is set, this field should hold 2594 * the acl_group_id, else it should hold the acl_id. 2595 * Access: RW 2596 */ 2597 MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16); 2598 2599 static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e, 2600 enum mlxsw_reg_pxbt_op op, 2601 u16 local_port, u16 acl_info) 2602 { 2603 MLXSW_REG_ZERO(ppbt, payload); 2604 mlxsw_reg_ppbt_e_set(payload, e); 2605 mlxsw_reg_ppbt_op_set(payload, op); 2606 mlxsw_reg_ppbt_local_port_set(payload, local_port); 2607 mlxsw_reg_ppbt_g_set(payload, true); 2608 mlxsw_reg_ppbt_acl_info_set(payload, acl_info); 2609 } 2610 2611 /* PACL - Policy-Engine ACL Register 2612 * --------------------------------- 2613 * This register is used for configuration of the ACL. 2614 */ 2615 #define MLXSW_REG_PACL_ID 0x3004 2616 #define MLXSW_REG_PACL_LEN 0x70 2617 2618 MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN); 2619 2620 /* reg_pacl_v 2621 * Valid. Setting the v bit makes the ACL valid. It should not be cleared 2622 * while the ACL is bounded to either a port, VLAN or ACL rule. 2623 * Access: RW 2624 */ 2625 MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1); 2626 2627 /* reg_pacl_acl_id 2628 * An identifier representing the ACL (managed by software) 2629 * Range 0 .. cap_max_acl_regions - 1 2630 * Access: Index 2631 */ 2632 MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16); 2633 2634 #define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16 2635 2636 /* reg_pacl_tcam_region_info 2637 * Opaque object that represents a TCAM region. 2638 * Obtained through PTAR register. 2639 * Access: RW 2640 */ 2641 MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30, 2642 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2643 2644 static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id, 2645 bool valid, const char *tcam_region_info) 2646 { 2647 MLXSW_REG_ZERO(pacl, payload); 2648 mlxsw_reg_pacl_acl_id_set(payload, acl_id); 2649 mlxsw_reg_pacl_v_set(payload, valid); 2650 mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info); 2651 } 2652 2653 /* PAGT - Policy-Engine ACL Group Table 2654 * ------------------------------------ 2655 * This register is used for configuration of the ACL Group Table. 2656 */ 2657 #define MLXSW_REG_PAGT_ID 0x3005 2658 #define MLXSW_REG_PAGT_BASE_LEN 0x30 2659 #define MLXSW_REG_PAGT_ACL_LEN 4 2660 #define MLXSW_REG_PAGT_ACL_MAX_NUM 16 2661 #define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \ 2662 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN) 2663 2664 MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN); 2665 2666 /* reg_pagt_size 2667 * Number of ACLs in the group. 2668 * Size 0 invalidates a group. 2669 * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now) 2670 * Total number of ACLs in all groups must be lower or equal 2671 * to cap_max_acl_tot_groups 2672 * Note: a group which is binded must not be invalidated 2673 * Access: Index 2674 */ 2675 MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8); 2676 2677 /* reg_pagt_acl_group_id 2678 * An identifier (numbered from 0..cap_max_acl_groups-1) representing 2679 * the ACL Group identifier (managed by software). 2680 * Access: Index 2681 */ 2682 MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16); 2683 2684 /* reg_pagt_multi 2685 * Multi-ACL 2686 * 0 - This ACL is the last ACL in the multi-ACL 2687 * 1 - This ACL is part of a multi-ACL 2688 * Access: RW 2689 */ 2690 MLXSW_ITEM32_INDEXED(reg, pagt, multi, 0x30, 31, 1, 0x04, 0x00, false); 2691 2692 /* reg_pagt_acl_id 2693 * ACL identifier 2694 * Access: RW 2695 */ 2696 MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false); 2697 2698 static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id) 2699 { 2700 MLXSW_REG_ZERO(pagt, payload); 2701 mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id); 2702 } 2703 2704 static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index, 2705 u16 acl_id, bool multi) 2706 { 2707 u8 size = mlxsw_reg_pagt_size_get(payload); 2708 2709 if (index >= size) 2710 mlxsw_reg_pagt_size_set(payload, index + 1); 2711 mlxsw_reg_pagt_multi_set(payload, index, multi); 2712 mlxsw_reg_pagt_acl_id_set(payload, index, acl_id); 2713 } 2714 2715 /* PTAR - Policy-Engine TCAM Allocation Register 2716 * --------------------------------------------- 2717 * This register is used for allocation of regions in the TCAM. 2718 * Note: Query method is not supported on this register. 2719 */ 2720 #define MLXSW_REG_PTAR_ID 0x3006 2721 #define MLXSW_REG_PTAR_BASE_LEN 0x20 2722 #define MLXSW_REG_PTAR_KEY_ID_LEN 1 2723 #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16 2724 #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \ 2725 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN) 2726 2727 MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN); 2728 2729 enum mlxsw_reg_ptar_op { 2730 /* allocate a TCAM region */ 2731 MLXSW_REG_PTAR_OP_ALLOC, 2732 /* resize a TCAM region */ 2733 MLXSW_REG_PTAR_OP_RESIZE, 2734 /* deallocate TCAM region */ 2735 MLXSW_REG_PTAR_OP_FREE, 2736 /* test allocation */ 2737 MLXSW_REG_PTAR_OP_TEST, 2738 }; 2739 2740 /* reg_ptar_op 2741 * Access: OP 2742 */ 2743 MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4); 2744 2745 /* reg_ptar_action_set_type 2746 * Type of action set to be used on this region. 2747 * For Spectrum and Spectrum-2, this is always type 2 - "flexible" 2748 * Access: WO 2749 */ 2750 MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8); 2751 2752 enum mlxsw_reg_ptar_key_type { 2753 MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50, /* Spetrum */ 2754 MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51, /* Spectrum-2 */ 2755 }; 2756 2757 /* reg_ptar_key_type 2758 * TCAM key type for the region. 2759 * Access: WO 2760 */ 2761 MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8); 2762 2763 /* reg_ptar_region_size 2764 * TCAM region size. When allocating/resizing this is the requested size, 2765 * the response is the actual size. Note that actual size may be 2766 * larger than requested. 2767 * Allowed range 1 .. cap_max_rules-1 2768 * Reserved during op deallocate. 2769 * Access: WO 2770 */ 2771 MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16); 2772 2773 /* reg_ptar_region_id 2774 * Region identifier 2775 * Range 0 .. cap_max_regions-1 2776 * Access: Index 2777 */ 2778 MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16); 2779 2780 /* reg_ptar_tcam_region_info 2781 * Opaque object that represents the TCAM region. 2782 * Returned when allocating a region. 2783 * Provided by software for ACL generation and region deallocation and resize. 2784 * Access: RW 2785 */ 2786 MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10, 2787 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2788 2789 /* reg_ptar_flexible_key_id 2790 * Identifier of the Flexible Key. 2791 * Only valid if key_type == "FLEX_KEY" 2792 * The key size will be rounded up to one of the following values: 2793 * 9B, 18B, 36B, 54B. 2794 * This field is reserved for in resize operation. 2795 * Access: WO 2796 */ 2797 MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8, 2798 MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false); 2799 2800 static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op, 2801 enum mlxsw_reg_ptar_key_type key_type, 2802 u16 region_size, u16 region_id, 2803 const char *tcam_region_info) 2804 { 2805 MLXSW_REG_ZERO(ptar, payload); 2806 mlxsw_reg_ptar_op_set(payload, op); 2807 mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */ 2808 mlxsw_reg_ptar_key_type_set(payload, key_type); 2809 mlxsw_reg_ptar_region_size_set(payload, region_size); 2810 mlxsw_reg_ptar_region_id_set(payload, region_id); 2811 mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info); 2812 } 2813 2814 static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index, 2815 u16 key_id) 2816 { 2817 mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id); 2818 } 2819 2820 static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info) 2821 { 2822 mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info); 2823 } 2824 2825 /* PPBS - Policy-Engine Policy Based Switching Register 2826 * ---------------------------------------------------- 2827 * This register retrieves and sets Policy Based Switching Table entries. 2828 */ 2829 #define MLXSW_REG_PPBS_ID 0x300C 2830 #define MLXSW_REG_PPBS_LEN 0x14 2831 2832 MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN); 2833 2834 /* reg_ppbs_pbs_ptr 2835 * Index into the PBS table. 2836 * For Spectrum, the index points to the KVD Linear. 2837 * Access: Index 2838 */ 2839 MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24); 2840 2841 /* reg_ppbs_system_port 2842 * Unique port identifier for the final destination of the packet. 2843 * Access: RW 2844 */ 2845 MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16); 2846 2847 static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr, 2848 u16 system_port) 2849 { 2850 MLXSW_REG_ZERO(ppbs, payload); 2851 mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr); 2852 mlxsw_reg_ppbs_system_port_set(payload, system_port); 2853 } 2854 2855 /* PRCR - Policy-Engine Rules Copy Register 2856 * ---------------------------------------- 2857 * This register is used for accessing rules within a TCAM region. 2858 */ 2859 #define MLXSW_REG_PRCR_ID 0x300D 2860 #define MLXSW_REG_PRCR_LEN 0x40 2861 2862 MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN); 2863 2864 enum mlxsw_reg_prcr_op { 2865 /* Move rules. Moves the rules from "tcam_region_info" starting 2866 * at offset "offset" to "dest_tcam_region_info" 2867 * at offset "dest_offset." 2868 */ 2869 MLXSW_REG_PRCR_OP_MOVE, 2870 /* Copy rules. Copies the rules from "tcam_region_info" starting 2871 * at offset "offset" to "dest_tcam_region_info" 2872 * at offset "dest_offset." 2873 */ 2874 MLXSW_REG_PRCR_OP_COPY, 2875 }; 2876 2877 /* reg_prcr_op 2878 * Access: OP 2879 */ 2880 MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4); 2881 2882 /* reg_prcr_offset 2883 * Offset within the source region to copy/move from. 2884 * Access: Index 2885 */ 2886 MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16); 2887 2888 /* reg_prcr_size 2889 * The number of rules to copy/move. 2890 * Access: WO 2891 */ 2892 MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16); 2893 2894 /* reg_prcr_tcam_region_info 2895 * Opaque object that represents the source TCAM region. 2896 * Access: Index 2897 */ 2898 MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10, 2899 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2900 2901 /* reg_prcr_dest_offset 2902 * Offset within the source region to copy/move to. 2903 * Access: Index 2904 */ 2905 MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16); 2906 2907 /* reg_prcr_dest_tcam_region_info 2908 * Opaque object that represents the destination TCAM region. 2909 * Access: Index 2910 */ 2911 MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30, 2912 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2913 2914 static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op, 2915 const char *src_tcam_region_info, 2916 u16 src_offset, 2917 const char *dest_tcam_region_info, 2918 u16 dest_offset, u16 size) 2919 { 2920 MLXSW_REG_ZERO(prcr, payload); 2921 mlxsw_reg_prcr_op_set(payload, op); 2922 mlxsw_reg_prcr_offset_set(payload, src_offset); 2923 mlxsw_reg_prcr_size_set(payload, size); 2924 mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload, 2925 src_tcam_region_info); 2926 mlxsw_reg_prcr_dest_offset_set(payload, dest_offset); 2927 mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload, 2928 dest_tcam_region_info); 2929 } 2930 2931 /* PEFA - Policy-Engine Extended Flexible Action Register 2932 * ------------------------------------------------------ 2933 * This register is used for accessing an extended flexible action entry 2934 * in the central KVD Linear Database. 2935 */ 2936 #define MLXSW_REG_PEFA_ID 0x300F 2937 #define MLXSW_REG_PEFA_LEN 0xB0 2938 2939 MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN); 2940 2941 /* reg_pefa_index 2942 * Index in the KVD Linear Centralized Database. 2943 * Access: Index 2944 */ 2945 MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24); 2946 2947 /* reg_pefa_a 2948 * Index in the KVD Linear Centralized Database. 2949 * Activity 2950 * For a new entry: set if ca=0, clear if ca=1 2951 * Set if a packet lookup has hit on the specific entry 2952 * Access: RO 2953 */ 2954 MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1); 2955 2956 /* reg_pefa_ca 2957 * Clear activity 2958 * When write: activity is according to this field 2959 * When read: after reading the activity is cleared according to ca 2960 * Access: OP 2961 */ 2962 MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1); 2963 2964 #define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8 2965 2966 /* reg_pefa_flex_action_set 2967 * Action-set to perform when rule is matched. 2968 * Must be zero padded if action set is shorter. 2969 * Access: RW 2970 */ 2971 MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN); 2972 2973 static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca, 2974 const char *flex_action_set) 2975 { 2976 MLXSW_REG_ZERO(pefa, payload); 2977 mlxsw_reg_pefa_index_set(payload, index); 2978 mlxsw_reg_pefa_ca_set(payload, ca); 2979 if (flex_action_set) 2980 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload, 2981 flex_action_set); 2982 } 2983 2984 static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a) 2985 { 2986 *p_a = mlxsw_reg_pefa_a_get(payload); 2987 } 2988 2989 /* PEMRBT - Policy-Engine Multicast Router Binding Table Register 2990 * -------------------------------------------------------------- 2991 * This register is used for binding Multicast router to an ACL group 2992 * that serves the MC router. 2993 * This register is not supported by SwitchX/-2 and Spectrum. 2994 */ 2995 #define MLXSW_REG_PEMRBT_ID 0x3014 2996 #define MLXSW_REG_PEMRBT_LEN 0x14 2997 2998 MLXSW_REG_DEFINE(pemrbt, MLXSW_REG_PEMRBT_ID, MLXSW_REG_PEMRBT_LEN); 2999 3000 enum mlxsw_reg_pemrbt_protocol { 3001 MLXSW_REG_PEMRBT_PROTO_IPV4, 3002 MLXSW_REG_PEMRBT_PROTO_IPV6, 3003 }; 3004 3005 /* reg_pemrbt_protocol 3006 * Access: Index 3007 */ 3008 MLXSW_ITEM32(reg, pemrbt, protocol, 0x00, 0, 1); 3009 3010 /* reg_pemrbt_group_id 3011 * ACL group identifier. 3012 * Range 0..cap_max_acl_groups-1 3013 * Access: RW 3014 */ 3015 MLXSW_ITEM32(reg, pemrbt, group_id, 0x10, 0, 16); 3016 3017 static inline void 3018 mlxsw_reg_pemrbt_pack(char *payload, enum mlxsw_reg_pemrbt_protocol protocol, 3019 u16 group_id) 3020 { 3021 MLXSW_REG_ZERO(pemrbt, payload); 3022 mlxsw_reg_pemrbt_protocol_set(payload, protocol); 3023 mlxsw_reg_pemrbt_group_id_set(payload, group_id); 3024 } 3025 3026 /* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2 3027 * ----------------------------------------------------- 3028 * This register is used for accessing rules within a TCAM region. 3029 * It is a new version of PTCE in order to support wider key, 3030 * mask and action within a TCAM region. This register is not supported 3031 * by SwitchX and SwitchX-2. 3032 */ 3033 #define MLXSW_REG_PTCE2_ID 0x3017 3034 #define MLXSW_REG_PTCE2_LEN 0x1D8 3035 3036 MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN); 3037 3038 /* reg_ptce2_v 3039 * Valid. 3040 * Access: RW 3041 */ 3042 MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1); 3043 3044 /* reg_ptce2_a 3045 * Activity. Set if a packet lookup has hit on the specific entry. 3046 * To clear the "a" bit, use "clear activity" op or "clear on read" op. 3047 * Access: RO 3048 */ 3049 MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1); 3050 3051 enum mlxsw_reg_ptce2_op { 3052 /* Read operation. */ 3053 MLXSW_REG_PTCE2_OP_QUERY_READ = 0, 3054 /* clear on read operation. Used to read entry 3055 * and clear Activity bit. 3056 */ 3057 MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1, 3058 /* Write operation. Used to write a new entry to the table. 3059 * All R/W fields are relevant for new entry. Activity bit is set 3060 * for new entries - Note write with v = 0 will delete the entry. 3061 */ 3062 MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0, 3063 /* Update action. Only action set will be updated. */ 3064 MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1, 3065 /* Clear activity. A bit is cleared for the entry. */ 3066 MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2, 3067 }; 3068 3069 /* reg_ptce2_op 3070 * Access: OP 3071 */ 3072 MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3); 3073 3074 /* reg_ptce2_offset 3075 * Access: Index 3076 */ 3077 MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16); 3078 3079 /* reg_ptce2_priority 3080 * Priority of the rule, higher values win. The range is 1..cap_kvd_size-1. 3081 * Note: priority does not have to be unique per rule. 3082 * Within a region, higher priority should have lower offset (no limitation 3083 * between regions in a multi-region). 3084 * Access: RW 3085 */ 3086 MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24); 3087 3088 /* reg_ptce2_tcam_region_info 3089 * Opaque object that represents the TCAM region. 3090 * Access: Index 3091 */ 3092 MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10, 3093 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 3094 3095 #define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 96 3096 3097 /* reg_ptce2_flex_key_blocks 3098 * ACL Key. 3099 * Access: RW 3100 */ 3101 MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20, 3102 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 3103 3104 /* reg_ptce2_mask 3105 * mask- in the same size as key. A bit that is set directs the TCAM 3106 * to compare the corresponding bit in key. A bit that is clear directs 3107 * the TCAM to ignore the corresponding bit in key. 3108 * Access: RW 3109 */ 3110 MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80, 3111 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 3112 3113 /* reg_ptce2_flex_action_set 3114 * ACL action set. 3115 * Access: RW 3116 */ 3117 MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0, 3118 MLXSW_REG_FLEX_ACTION_SET_LEN); 3119 3120 static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid, 3121 enum mlxsw_reg_ptce2_op op, 3122 const char *tcam_region_info, 3123 u16 offset, u32 priority) 3124 { 3125 MLXSW_REG_ZERO(ptce2, payload); 3126 mlxsw_reg_ptce2_v_set(payload, valid); 3127 mlxsw_reg_ptce2_op_set(payload, op); 3128 mlxsw_reg_ptce2_offset_set(payload, offset); 3129 mlxsw_reg_ptce2_priority_set(payload, priority); 3130 mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info); 3131 } 3132 3133 /* PERPT - Policy-Engine ERP Table Register 3134 * ---------------------------------------- 3135 * This register adds and removes eRPs from the eRP table. 3136 */ 3137 #define MLXSW_REG_PERPT_ID 0x3021 3138 #define MLXSW_REG_PERPT_LEN 0x80 3139 3140 MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN); 3141 3142 /* reg_perpt_erpt_bank 3143 * eRP table bank. 3144 * Range 0 .. cap_max_erp_table_banks - 1 3145 * Access: Index 3146 */ 3147 MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4); 3148 3149 /* reg_perpt_erpt_index 3150 * Index to eRP table within the eRP bank. 3151 * Range is 0 .. cap_max_erp_table_bank_size - 1 3152 * Access: Index 3153 */ 3154 MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8); 3155 3156 enum mlxsw_reg_perpt_key_size { 3157 MLXSW_REG_PERPT_KEY_SIZE_2KB, 3158 MLXSW_REG_PERPT_KEY_SIZE_4KB, 3159 MLXSW_REG_PERPT_KEY_SIZE_8KB, 3160 MLXSW_REG_PERPT_KEY_SIZE_12KB, 3161 }; 3162 3163 /* reg_perpt_key_size 3164 * Access: OP 3165 */ 3166 MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4); 3167 3168 /* reg_perpt_bf_bypass 3169 * 0 - The eRP is used only if bloom filter state is set for the given 3170 * rule. 3171 * 1 - The eRP is used regardless of bloom filter state. 3172 * The bypass is an OR condition of region_id or eRP. See PERCR.bf_bypass 3173 * Access: RW 3174 */ 3175 MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1); 3176 3177 /* reg_perpt_erp_id 3178 * eRP ID for use by the rules. 3179 * Access: RW 3180 */ 3181 MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4); 3182 3183 /* reg_perpt_erpt_base_bank 3184 * Base eRP table bank, points to head of erp_vector 3185 * Range is 0 .. cap_max_erp_table_banks - 1 3186 * Access: OP 3187 */ 3188 MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4); 3189 3190 /* reg_perpt_erpt_base_index 3191 * Base index to eRP table within the eRP bank 3192 * Range is 0 .. cap_max_erp_table_bank_size - 1 3193 * Access: OP 3194 */ 3195 MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8); 3196 3197 /* reg_perpt_erp_index_in_vector 3198 * eRP index in the vector. 3199 * Access: OP 3200 */ 3201 MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4); 3202 3203 /* reg_perpt_erp_vector 3204 * eRP vector. 3205 * Access: OP 3206 */ 3207 MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1); 3208 3209 /* reg_perpt_mask 3210 * Mask 3211 * 0 - A-TCAM will ignore the bit in key 3212 * 1 - A-TCAM will compare the bit in key 3213 * Access: RW 3214 */ 3215 MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 3216 3217 static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload, 3218 unsigned long *erp_vector, 3219 unsigned long size) 3220 { 3221 unsigned long bit; 3222 3223 for_each_set_bit(bit, erp_vector, size) 3224 mlxsw_reg_perpt_erp_vector_set(payload, bit, true); 3225 } 3226 3227 static inline void 3228 mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index, 3229 enum mlxsw_reg_perpt_key_size key_size, u8 erp_id, 3230 u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index, 3231 char *mask) 3232 { 3233 MLXSW_REG_ZERO(perpt, payload); 3234 mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank); 3235 mlxsw_reg_perpt_erpt_index_set(payload, erpt_index); 3236 mlxsw_reg_perpt_key_size_set(payload, key_size); 3237 mlxsw_reg_perpt_bf_bypass_set(payload, false); 3238 mlxsw_reg_perpt_erp_id_set(payload, erp_id); 3239 mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank); 3240 mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index); 3241 mlxsw_reg_perpt_erp_index_in_vector_set(payload, erp_index); 3242 mlxsw_reg_perpt_mask_memcpy_to(payload, mask); 3243 } 3244 3245 /* PERAR - Policy-Engine Region Association Register 3246 * ------------------------------------------------- 3247 * This register associates a hw region for region_id's. Changing on the fly 3248 * is supported by the device. 3249 */ 3250 #define MLXSW_REG_PERAR_ID 0x3026 3251 #define MLXSW_REG_PERAR_LEN 0x08 3252 3253 MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN); 3254 3255 /* reg_perar_region_id 3256 * Region identifier 3257 * Range 0 .. cap_max_regions-1 3258 * Access: Index 3259 */ 3260 MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16); 3261 3262 static inline unsigned int 3263 mlxsw_reg_perar_hw_regions_needed(unsigned int block_num) 3264 { 3265 return DIV_ROUND_UP(block_num, 4); 3266 } 3267 3268 /* reg_perar_hw_region 3269 * HW Region 3270 * Range 0 .. cap_max_regions-1 3271 * Default: hw_region = region_id 3272 * For a 8 key block region, 2 consecutive regions are used 3273 * For a 12 key block region, 3 consecutive regions are used 3274 * Access: RW 3275 */ 3276 MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16); 3277 3278 static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id, 3279 u16 hw_region) 3280 { 3281 MLXSW_REG_ZERO(perar, payload); 3282 mlxsw_reg_perar_region_id_set(payload, region_id); 3283 mlxsw_reg_perar_hw_region_set(payload, hw_region); 3284 } 3285 3286 /* PTCE-V3 - Policy-Engine TCAM Entry Register Version 3 3287 * ----------------------------------------------------- 3288 * This register is a new version of PTCE-V2 in order to support the 3289 * A-TCAM. This register is not supported by SwitchX/-2 and Spectrum. 3290 */ 3291 #define MLXSW_REG_PTCE3_ID 0x3027 3292 #define MLXSW_REG_PTCE3_LEN 0xF0 3293 3294 MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN); 3295 3296 /* reg_ptce3_v 3297 * Valid. 3298 * Access: RW 3299 */ 3300 MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1); 3301 3302 enum mlxsw_reg_ptce3_op { 3303 /* Write operation. Used to write a new entry to the table. 3304 * All R/W fields are relevant for new entry. Activity bit is set 3305 * for new entries. Write with v = 0 will delete the entry. Must 3306 * not be used if an entry exists. 3307 */ 3308 MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0, 3309 /* Update operation */ 3310 MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1, 3311 /* Read operation */ 3312 MLXSW_REG_PTCE3_OP_QUERY_READ = 0, 3313 }; 3314 3315 /* reg_ptce3_op 3316 * Access: OP 3317 */ 3318 MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3); 3319 3320 /* reg_ptce3_priority 3321 * Priority of the rule. Higher values win. 3322 * For Spectrum-2 range is 1..cap_kvd_size - 1 3323 * Note: Priority does not have to be unique per rule. 3324 * Access: RW 3325 */ 3326 MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24); 3327 3328 /* reg_ptce3_tcam_region_info 3329 * Opaque object that represents the TCAM region. 3330 * Access: Index 3331 */ 3332 MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10, 3333 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 3334 3335 /* reg_ptce3_flex2_key_blocks 3336 * ACL key. The key must be masked according to eRP (if exists) or 3337 * according to master mask. 3338 * Access: Index 3339 */ 3340 MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20, 3341 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 3342 3343 /* reg_ptce3_erp_id 3344 * eRP ID. 3345 * Access: Index 3346 */ 3347 MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4); 3348 3349 /* reg_ptce3_delta_start 3350 * Start point of delta_value and delta_mask, in bits. Must not exceed 3351 * num_key_blocks * 36 - 8. Reserved when delta_mask = 0. 3352 * Access: Index 3353 */ 3354 MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10); 3355 3356 /* reg_ptce3_delta_mask 3357 * Delta mask. 3358 * 0 - Ignore relevant bit in delta_value 3359 * 1 - Compare relevant bit in delta_value 3360 * Delta mask must not be set for reserved fields in the key blocks. 3361 * Note: No delta when no eRPs. Thus, for regions with 3362 * PERERP.erpt_pointer_valid = 0 the delta mask must be 0. 3363 * Access: Index 3364 */ 3365 MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8); 3366 3367 /* reg_ptce3_delta_value 3368 * Delta value. 3369 * Bits which are masked by delta_mask must be 0. 3370 * Access: Index 3371 */ 3372 MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8); 3373 3374 /* reg_ptce3_prune_vector 3375 * Pruning vector relative to the PERPT.erp_id. 3376 * Used for reducing lookups. 3377 * 0 - NEED: Do a lookup using the eRP. 3378 * 1 - PRUNE: Do not perform a lookup using the eRP. 3379 * Maybe be modified by PEAPBL and PEAPBM. 3380 * Note: In Spectrum-2, a region of 8 key blocks must be set to either 3381 * all 1's or all 0's. 3382 * Access: RW 3383 */ 3384 MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1); 3385 3386 /* reg_ptce3_prune_ctcam 3387 * Pruning on C-TCAM. Used for reducing lookups. 3388 * 0 - NEED: Do a lookup in the C-TCAM. 3389 * 1 - PRUNE: Do not perform a lookup in the C-TCAM. 3390 * Access: RW 3391 */ 3392 MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1); 3393 3394 /* reg_ptce3_large_exists 3395 * Large entry key ID exists. 3396 * Within the region: 3397 * 0 - SINGLE: The large_entry_key_id is not currently in use. 3398 * For rule insert: The MSB of the key (blocks 6..11) will be added. 3399 * For rule delete: The MSB of the key will be removed. 3400 * 1 - NON_SINGLE: The large_entry_key_id is currently in use. 3401 * For rule insert: The MSB of the key (blocks 6..11) will not be added. 3402 * For rule delete: The MSB of the key will not be removed. 3403 * Access: WO 3404 */ 3405 MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1); 3406 3407 /* reg_ptce3_large_entry_key_id 3408 * Large entry key ID. 3409 * A key for 12 key blocks rules. Reserved when region has less than 12 key 3410 * blocks. Must be different for different keys which have the same common 3411 * 6 key blocks (MSB, blocks 6..11) key within a region. 3412 * Range is 0..cap_max_pe_large_key_id - 1 3413 * Access: RW 3414 */ 3415 MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24); 3416 3417 /* reg_ptce3_action_pointer 3418 * Pointer to action. 3419 * Range is 0..cap_max_kvd_action_sets - 1 3420 * Access: RW 3421 */ 3422 MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24); 3423 3424 static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid, 3425 enum mlxsw_reg_ptce3_op op, 3426 u32 priority, 3427 const char *tcam_region_info, 3428 const char *key, u8 erp_id, 3429 u16 delta_start, u8 delta_mask, 3430 u8 delta_value, bool large_exists, 3431 u32 lkey_id, u32 action_pointer) 3432 { 3433 MLXSW_REG_ZERO(ptce3, payload); 3434 mlxsw_reg_ptce3_v_set(payload, valid); 3435 mlxsw_reg_ptce3_op_set(payload, op); 3436 mlxsw_reg_ptce3_priority_set(payload, priority); 3437 mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info); 3438 mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key); 3439 mlxsw_reg_ptce3_erp_id_set(payload, erp_id); 3440 mlxsw_reg_ptce3_delta_start_set(payload, delta_start); 3441 mlxsw_reg_ptce3_delta_mask_set(payload, delta_mask); 3442 mlxsw_reg_ptce3_delta_value_set(payload, delta_value); 3443 mlxsw_reg_ptce3_large_exists_set(payload, large_exists); 3444 mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id); 3445 mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer); 3446 } 3447 3448 /* PERCR - Policy-Engine Region Configuration Register 3449 * --------------------------------------------------- 3450 * This register configures the region parameters. The region_id must be 3451 * allocated. 3452 */ 3453 #define MLXSW_REG_PERCR_ID 0x302A 3454 #define MLXSW_REG_PERCR_LEN 0x80 3455 3456 MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN); 3457 3458 /* reg_percr_region_id 3459 * Region identifier. 3460 * Range 0..cap_max_regions-1 3461 * Access: Index 3462 */ 3463 MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16); 3464 3465 /* reg_percr_atcam_ignore_prune 3466 * Ignore prune_vector by other A-TCAM rules. Used e.g., for a new rule. 3467 * Access: RW 3468 */ 3469 MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1); 3470 3471 /* reg_percr_ctcam_ignore_prune 3472 * Ignore prune_ctcam by other A-TCAM rules. Used e.g., for a new rule. 3473 * Access: RW 3474 */ 3475 MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1); 3476 3477 /* reg_percr_bf_bypass 3478 * Bloom filter bypass. 3479 * 0 - Bloom filter is used (default) 3480 * 1 - Bloom filter is bypassed. The bypass is an OR condition of 3481 * region_id or eRP. See PERPT.bf_bypass 3482 * Access: RW 3483 */ 3484 MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1); 3485 3486 /* reg_percr_master_mask 3487 * Master mask. Logical OR mask of all masks of all rules of a region 3488 * (both A-TCAM and C-TCAM). When there are no eRPs 3489 * (erpt_pointer_valid = 0), then this provides the mask. 3490 * Access: RW 3491 */ 3492 MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96); 3493 3494 static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id) 3495 { 3496 MLXSW_REG_ZERO(percr, payload); 3497 mlxsw_reg_percr_region_id_set(payload, region_id); 3498 mlxsw_reg_percr_atcam_ignore_prune_set(payload, false); 3499 mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false); 3500 mlxsw_reg_percr_bf_bypass_set(payload, false); 3501 } 3502 3503 /* PERERP - Policy-Engine Region eRP Register 3504 * ------------------------------------------ 3505 * This register configures the region eRP. The region_id must be 3506 * allocated. 3507 */ 3508 #define MLXSW_REG_PERERP_ID 0x302B 3509 #define MLXSW_REG_PERERP_LEN 0x1C 3510 3511 MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN); 3512 3513 /* reg_pererp_region_id 3514 * Region identifier. 3515 * Range 0..cap_max_regions-1 3516 * Access: Index 3517 */ 3518 MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16); 3519 3520 /* reg_pererp_ctcam_le 3521 * C-TCAM lookup enable. Reserved when erpt_pointer_valid = 0. 3522 * Access: RW 3523 */ 3524 MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1); 3525 3526 /* reg_pererp_erpt_pointer_valid 3527 * erpt_pointer is valid. 3528 * Access: RW 3529 */ 3530 MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1); 3531 3532 /* reg_pererp_erpt_bank_pointer 3533 * Pointer to eRP table bank. May be modified at any time. 3534 * Range 0..cap_max_erp_table_banks-1 3535 * Reserved when erpt_pointer_valid = 0 3536 */ 3537 MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4); 3538 3539 /* reg_pererp_erpt_pointer 3540 * Pointer to eRP table within the eRP bank. Can be changed for an 3541 * existing region. 3542 * Range 0..cap_max_erp_table_size-1 3543 * Reserved when erpt_pointer_valid = 0 3544 * Access: RW 3545 */ 3546 MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8); 3547 3548 /* reg_pererp_erpt_vector 3549 * Vector of allowed eRP indexes starting from erpt_pointer within the 3550 * erpt_bank_pointer. Next entries will be in next bank. 3551 * Note that eRP index is used and not eRP ID. 3552 * Reserved when erpt_pointer_valid = 0 3553 * Access: RW 3554 */ 3555 MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1); 3556 3557 /* reg_pererp_master_rp_id 3558 * Master RP ID. When there are no eRPs, then this provides the eRP ID 3559 * for the lookup. Can be changed for an existing region. 3560 * Reserved when erpt_pointer_valid = 1 3561 * Access: RW 3562 */ 3563 MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4); 3564 3565 static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload, 3566 unsigned long *erp_vector, 3567 unsigned long size) 3568 { 3569 unsigned long bit; 3570 3571 for_each_set_bit(bit, erp_vector, size) 3572 mlxsw_reg_pererp_erpt_vector_set(payload, bit, true); 3573 } 3574 3575 static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id, 3576 bool ctcam_le, bool erpt_pointer_valid, 3577 u8 erpt_bank_pointer, u8 erpt_pointer, 3578 u8 master_rp_id) 3579 { 3580 MLXSW_REG_ZERO(pererp, payload); 3581 mlxsw_reg_pererp_region_id_set(payload, region_id); 3582 mlxsw_reg_pererp_ctcam_le_set(payload, ctcam_le); 3583 mlxsw_reg_pererp_erpt_pointer_valid_set(payload, erpt_pointer_valid); 3584 mlxsw_reg_pererp_erpt_bank_pointer_set(payload, erpt_bank_pointer); 3585 mlxsw_reg_pererp_erpt_pointer_set(payload, erpt_pointer); 3586 mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id); 3587 } 3588 3589 /* PEABFE - Policy-Engine Algorithmic Bloom Filter Entries Register 3590 * ---------------------------------------------------------------- 3591 * This register configures the Bloom filter entries. 3592 */ 3593 #define MLXSW_REG_PEABFE_ID 0x3022 3594 #define MLXSW_REG_PEABFE_BASE_LEN 0x10 3595 #define MLXSW_REG_PEABFE_BF_REC_LEN 0x4 3596 #define MLXSW_REG_PEABFE_BF_REC_MAX_COUNT 256 3597 #define MLXSW_REG_PEABFE_LEN (MLXSW_REG_PEABFE_BASE_LEN + \ 3598 MLXSW_REG_PEABFE_BF_REC_LEN * \ 3599 MLXSW_REG_PEABFE_BF_REC_MAX_COUNT) 3600 3601 MLXSW_REG_DEFINE(peabfe, MLXSW_REG_PEABFE_ID, MLXSW_REG_PEABFE_LEN); 3602 3603 /* reg_peabfe_size 3604 * Number of BF entries to be updated. 3605 * Range 1..256 3606 * Access: Op 3607 */ 3608 MLXSW_ITEM32(reg, peabfe, size, 0x00, 0, 9); 3609 3610 /* reg_peabfe_bf_entry_state 3611 * Bloom filter state 3612 * 0 - Clear 3613 * 1 - Set 3614 * Access: RW 3615 */ 3616 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_state, 3617 MLXSW_REG_PEABFE_BASE_LEN, 31, 1, 3618 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3619 3620 /* reg_peabfe_bf_entry_bank 3621 * Bloom filter bank ID 3622 * Range 0..cap_max_erp_table_banks-1 3623 * Access: Index 3624 */ 3625 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_bank, 3626 MLXSW_REG_PEABFE_BASE_LEN, 24, 4, 3627 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3628 3629 /* reg_peabfe_bf_entry_index 3630 * Bloom filter entry index 3631 * Range 0..2^cap_max_bf_log-1 3632 * Access: Index 3633 */ 3634 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_index, 3635 MLXSW_REG_PEABFE_BASE_LEN, 0, 24, 3636 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3637 3638 static inline void mlxsw_reg_peabfe_pack(char *payload) 3639 { 3640 MLXSW_REG_ZERO(peabfe, payload); 3641 } 3642 3643 static inline void mlxsw_reg_peabfe_rec_pack(char *payload, int rec_index, 3644 u8 state, u8 bank, u32 bf_index) 3645 { 3646 u8 num_rec = mlxsw_reg_peabfe_size_get(payload); 3647 3648 if (rec_index >= num_rec) 3649 mlxsw_reg_peabfe_size_set(payload, rec_index + 1); 3650 mlxsw_reg_peabfe_bf_entry_state_set(payload, rec_index, state); 3651 mlxsw_reg_peabfe_bf_entry_bank_set(payload, rec_index, bank); 3652 mlxsw_reg_peabfe_bf_entry_index_set(payload, rec_index, bf_index); 3653 } 3654 3655 /* IEDR - Infrastructure Entry Delete Register 3656 * ---------------------------------------------------- 3657 * This register is used for deleting entries from the entry tables. 3658 * It is legitimate to attempt to delete a nonexisting entry (the device will 3659 * respond as a good flow). 3660 */ 3661 #define MLXSW_REG_IEDR_ID 0x3804 3662 #define MLXSW_REG_IEDR_BASE_LEN 0x10 /* base length, without records */ 3663 #define MLXSW_REG_IEDR_REC_LEN 0x8 /* record length */ 3664 #define MLXSW_REG_IEDR_REC_MAX_COUNT 64 3665 #define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN + \ 3666 MLXSW_REG_IEDR_REC_LEN * \ 3667 MLXSW_REG_IEDR_REC_MAX_COUNT) 3668 3669 MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN); 3670 3671 /* reg_iedr_num_rec 3672 * Number of records. 3673 * Access: OP 3674 */ 3675 MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8); 3676 3677 /* reg_iedr_rec_type 3678 * Resource type. 3679 * Access: OP 3680 */ 3681 MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8, 3682 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3683 3684 /* reg_iedr_rec_size 3685 * Size of entries do be deleted. The unit is 1 entry, regardless of entry type. 3686 * Access: OP 3687 */ 3688 MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 13, 3689 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3690 3691 /* reg_iedr_rec_index_start 3692 * Resource index start. 3693 * Access: OP 3694 */ 3695 MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24, 3696 MLXSW_REG_IEDR_REC_LEN, 0x04, false); 3697 3698 static inline void mlxsw_reg_iedr_pack(char *payload) 3699 { 3700 MLXSW_REG_ZERO(iedr, payload); 3701 } 3702 3703 static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index, 3704 u8 rec_type, u16 rec_size, 3705 u32 rec_index_start) 3706 { 3707 u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload); 3708 3709 if (rec_index >= num_rec) 3710 mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1); 3711 mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type); 3712 mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size); 3713 mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start); 3714 } 3715 3716 /* QPTS - QoS Priority Trust State Register 3717 * ---------------------------------------- 3718 * This register controls the port policy to calculate the switch priority and 3719 * packet color based on incoming packet fields. 3720 */ 3721 #define MLXSW_REG_QPTS_ID 0x4002 3722 #define MLXSW_REG_QPTS_LEN 0x8 3723 3724 MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN); 3725 3726 /* reg_qpts_local_port 3727 * Local port number. 3728 * Access: Index 3729 * 3730 * Note: CPU port is supported. 3731 */ 3732 MLXSW_ITEM32_LP(reg, qpts, 0x00, 16, 0x00, 12); 3733 3734 enum mlxsw_reg_qpts_trust_state { 3735 MLXSW_REG_QPTS_TRUST_STATE_PCP = 1, 3736 MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2, /* For MPLS, trust EXP. */ 3737 }; 3738 3739 /* reg_qpts_trust_state 3740 * Trust state for a given port. 3741 * Access: RW 3742 */ 3743 MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3); 3744 3745 static inline void mlxsw_reg_qpts_pack(char *payload, u16 local_port, 3746 enum mlxsw_reg_qpts_trust_state ts) 3747 { 3748 MLXSW_REG_ZERO(qpts, payload); 3749 3750 mlxsw_reg_qpts_local_port_set(payload, local_port); 3751 mlxsw_reg_qpts_trust_state_set(payload, ts); 3752 } 3753 3754 /* QPCR - QoS Policer Configuration Register 3755 * ----------------------------------------- 3756 * The QPCR register is used to create policers - that limit 3757 * the rate of bytes or packets via some trap group. 3758 */ 3759 #define MLXSW_REG_QPCR_ID 0x4004 3760 #define MLXSW_REG_QPCR_LEN 0x28 3761 3762 MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN); 3763 3764 enum mlxsw_reg_qpcr_g { 3765 MLXSW_REG_QPCR_G_GLOBAL = 2, 3766 MLXSW_REG_QPCR_G_STORM_CONTROL = 3, 3767 }; 3768 3769 /* reg_qpcr_g 3770 * The policer type. 3771 * Access: Index 3772 */ 3773 MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2); 3774 3775 /* reg_qpcr_pid 3776 * Policer ID. 3777 * Access: Index 3778 */ 3779 MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14); 3780 3781 /* reg_qpcr_clear_counter 3782 * Clear counters. 3783 * Access: OP 3784 */ 3785 MLXSW_ITEM32(reg, qpcr, clear_counter, 0x04, 31, 1); 3786 3787 /* reg_qpcr_color_aware 3788 * Is the policer aware of colors. 3789 * Must be 0 (unaware) for cpu port. 3790 * Access: RW for unbounded policer. RO for bounded policer. 3791 */ 3792 MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1); 3793 3794 /* reg_qpcr_bytes 3795 * Is policer limit is for bytes per sec or packets per sec. 3796 * 0 - packets 3797 * 1 - bytes 3798 * Access: RW for unbounded policer. RO for bounded policer. 3799 */ 3800 MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1); 3801 3802 enum mlxsw_reg_qpcr_ir_units { 3803 MLXSW_REG_QPCR_IR_UNITS_M, 3804 MLXSW_REG_QPCR_IR_UNITS_K, 3805 }; 3806 3807 /* reg_qpcr_ir_units 3808 * Policer's units for cir and eir fields (for bytes limits only) 3809 * 1 - 10^3 3810 * 0 - 10^6 3811 * Access: OP 3812 */ 3813 MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1); 3814 3815 enum mlxsw_reg_qpcr_rate_type { 3816 MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1, 3817 MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2, 3818 }; 3819 3820 /* reg_qpcr_rate_type 3821 * Policer can have one limit (single rate) or 2 limits with specific operation 3822 * for packets that exceed the lower rate but not the upper one. 3823 * (For cpu port must be single rate) 3824 * Access: RW for unbounded policer. RO for bounded policer. 3825 */ 3826 MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2); 3827 3828 /* reg_qpc_cbs 3829 * Policer's committed burst size. 3830 * The policer is working with time slices of 50 nano sec. By default every 3831 * slice is granted the proportionate share of the committed rate. If we want to 3832 * allow a slice to exceed that share (while still keeping the rate per sec) we 3833 * can allow burst. The burst size is between the default proportionate share 3834 * (and no lower than 8) to 32Gb. (Even though giving a number higher than the 3835 * committed rate will result in exceeding the rate). The burst size must be a 3836 * log of 2 and will be determined by 2^cbs. 3837 * Access: RW 3838 */ 3839 MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6); 3840 3841 /* reg_qpcr_cir 3842 * Policer's committed rate. 3843 * The rate used for sungle rate, the lower rate for double rate. 3844 * For bytes limits, the rate will be this value * the unit from ir_units. 3845 * (Resolution error is up to 1%). 3846 * Access: RW 3847 */ 3848 MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32); 3849 3850 /* reg_qpcr_eir 3851 * Policer's exceed rate. 3852 * The higher rate for double rate, reserved for single rate. 3853 * Lower rate for double rate policer. 3854 * For bytes limits, the rate will be this value * the unit from ir_units. 3855 * (Resolution error is up to 1%). 3856 * Access: RW 3857 */ 3858 MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32); 3859 3860 #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2 3861 3862 /* reg_qpcr_exceed_action. 3863 * What to do with packets between the 2 limits for double rate. 3864 * Access: RW for unbounded policer. RO for bounded policer. 3865 */ 3866 MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4); 3867 3868 enum mlxsw_reg_qpcr_action { 3869 /* Discard */ 3870 MLXSW_REG_QPCR_ACTION_DISCARD = 1, 3871 /* Forward and set color to red. 3872 * If the packet is intended to cpu port, it will be dropped. 3873 */ 3874 MLXSW_REG_QPCR_ACTION_FORWARD = 2, 3875 }; 3876 3877 /* reg_qpcr_violate_action 3878 * What to do with packets that cross the cir limit (for single rate) or the eir 3879 * limit (for double rate). 3880 * Access: RW for unbounded policer. RO for bounded policer. 3881 */ 3882 MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4); 3883 3884 /* reg_qpcr_violate_count 3885 * Counts the number of times violate_action happened on this PID. 3886 * Access: RW 3887 */ 3888 MLXSW_ITEM64(reg, qpcr, violate_count, 0x20, 0, 64); 3889 3890 /* Packets */ 3891 #define MLXSW_REG_QPCR_LOWEST_CIR 1 3892 #define MLXSW_REG_QPCR_HIGHEST_CIR (2 * 1000 * 1000 * 1000) /* 2Gpps */ 3893 #define MLXSW_REG_QPCR_LOWEST_CBS 4 3894 #define MLXSW_REG_QPCR_HIGHEST_CBS 24 3895 3896 /* Bandwidth */ 3897 #define MLXSW_REG_QPCR_LOWEST_CIR_BITS 1024 /* bps */ 3898 #define MLXSW_REG_QPCR_HIGHEST_CIR_BITS 2000000000000ULL /* 2Tbps */ 3899 #define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP1 4 3900 #define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP2 4 3901 #define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP1 25 3902 #define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP2 31 3903 3904 static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid, 3905 enum mlxsw_reg_qpcr_ir_units ir_units, 3906 bool bytes, u32 cir, u16 cbs) 3907 { 3908 MLXSW_REG_ZERO(qpcr, payload); 3909 mlxsw_reg_qpcr_pid_set(payload, pid); 3910 mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL); 3911 mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE); 3912 mlxsw_reg_qpcr_violate_action_set(payload, 3913 MLXSW_REG_QPCR_ACTION_DISCARD); 3914 mlxsw_reg_qpcr_cir_set(payload, cir); 3915 mlxsw_reg_qpcr_ir_units_set(payload, ir_units); 3916 mlxsw_reg_qpcr_bytes_set(payload, bytes); 3917 mlxsw_reg_qpcr_cbs_set(payload, cbs); 3918 } 3919 3920 /* QTCT - QoS Switch Traffic Class Table 3921 * ------------------------------------- 3922 * Configures the mapping between the packet switch priority and the 3923 * traffic class on the transmit port. 3924 */ 3925 #define MLXSW_REG_QTCT_ID 0x400A 3926 #define MLXSW_REG_QTCT_LEN 0x08 3927 3928 MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN); 3929 3930 /* reg_qtct_local_port 3931 * Local port number. 3932 * Access: Index 3933 * 3934 * Note: CPU port is not supported. 3935 */ 3936 MLXSW_ITEM32_LP(reg, qtct, 0x00, 16, 0x00, 12); 3937 3938 /* reg_qtct_sub_port 3939 * Virtual port within the physical port. 3940 * Should be set to 0 when virtual ports are not enabled on the port. 3941 * Access: Index 3942 */ 3943 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8); 3944 3945 /* reg_qtct_switch_prio 3946 * Switch priority. 3947 * Access: Index 3948 */ 3949 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4); 3950 3951 /* reg_qtct_tclass 3952 * Traffic class. 3953 * Default values: 3954 * switch_prio 0 : tclass 1 3955 * switch_prio 1 : tclass 0 3956 * switch_prio i : tclass i, for i > 1 3957 * Access: RW 3958 */ 3959 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4); 3960 3961 static inline void mlxsw_reg_qtct_pack(char *payload, u16 local_port, 3962 u8 switch_prio, u8 tclass) 3963 { 3964 MLXSW_REG_ZERO(qtct, payload); 3965 mlxsw_reg_qtct_local_port_set(payload, local_port); 3966 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio); 3967 mlxsw_reg_qtct_tclass_set(payload, tclass); 3968 } 3969 3970 /* QEEC - QoS ETS Element Configuration Register 3971 * --------------------------------------------- 3972 * Configures the ETS elements. 3973 */ 3974 #define MLXSW_REG_QEEC_ID 0x400D 3975 #define MLXSW_REG_QEEC_LEN 0x20 3976 3977 MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN); 3978 3979 /* reg_qeec_local_port 3980 * Local port number. 3981 * Access: Index 3982 * 3983 * Note: CPU port is supported. 3984 */ 3985 MLXSW_ITEM32_LP(reg, qeec, 0x00, 16, 0x00, 12); 3986 3987 enum mlxsw_reg_qeec_hr { 3988 MLXSW_REG_QEEC_HR_PORT, 3989 MLXSW_REG_QEEC_HR_GROUP, 3990 MLXSW_REG_QEEC_HR_SUBGROUP, 3991 MLXSW_REG_QEEC_HR_TC, 3992 }; 3993 3994 /* reg_qeec_element_hierarchy 3995 * 0 - Port 3996 * 1 - Group 3997 * 2 - Subgroup 3998 * 3 - Traffic Class 3999 * Access: Index 4000 */ 4001 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4); 4002 4003 /* reg_qeec_element_index 4004 * The index of the element in the hierarchy. 4005 * Access: Index 4006 */ 4007 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8); 4008 4009 /* reg_qeec_next_element_index 4010 * The index of the next (lower) element in the hierarchy. 4011 * Access: RW 4012 * 4013 * Note: Reserved for element_hierarchy 0. 4014 */ 4015 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8); 4016 4017 /* reg_qeec_mise 4018 * Min shaper configuration enable. Enables configuration of the min 4019 * shaper on this ETS element 4020 * 0 - Disable 4021 * 1 - Enable 4022 * Access: RW 4023 */ 4024 MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1); 4025 4026 /* reg_qeec_ptps 4027 * PTP shaper 4028 * 0: regular shaper mode 4029 * 1: PTP oriented shaper 4030 * Allowed only for hierarchy 0 4031 * Not supported for CPU port 4032 * Note that ptps mode may affect the shaper rates of all hierarchies 4033 * Supported only on Spectrum-1 4034 * Access: RW 4035 */ 4036 MLXSW_ITEM32(reg, qeec, ptps, 0x0C, 29, 1); 4037 4038 enum { 4039 MLXSW_REG_QEEC_BYTES_MODE, 4040 MLXSW_REG_QEEC_PACKETS_MODE, 4041 }; 4042 4043 /* reg_qeec_pb 4044 * Packets or bytes mode. 4045 * 0 - Bytes mode 4046 * 1 - Packets mode 4047 * Access: RW 4048 * 4049 * Note: Used for max shaper configuration. For Spectrum, packets mode 4050 * is supported only for traffic classes of CPU port. 4051 */ 4052 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1); 4053 4054 /* The smallest permitted min shaper rate. */ 4055 #define MLXSW_REG_QEEC_MIS_MIN 200000 /* Kbps */ 4056 4057 /* reg_qeec_min_shaper_rate 4058 * Min shaper information rate. 4059 * For CPU port, can only be configured for port hierarchy. 4060 * When in bytes mode, value is specified in units of 1000bps. 4061 * Access: RW 4062 */ 4063 MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28); 4064 4065 /* reg_qeec_mase 4066 * Max shaper configuration enable. Enables configuration of the max 4067 * shaper on this ETS element. 4068 * 0 - Disable 4069 * 1 - Enable 4070 * Access: RW 4071 */ 4072 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1); 4073 4074 /* The largest max shaper value possible to disable the shaper. */ 4075 #define MLXSW_REG_QEEC_MAS_DIS ((1u << 31) - 1) /* Kbps */ 4076 4077 /* reg_qeec_max_shaper_rate 4078 * Max shaper information rate. 4079 * For CPU port, can only be configured for port hierarchy. 4080 * When in bytes mode, value is specified in units of 1000bps. 4081 * Access: RW 4082 */ 4083 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 31); 4084 4085 /* reg_qeec_de 4086 * DWRR configuration enable. Enables configuration of the dwrr and 4087 * dwrr_weight. 4088 * 0 - Disable 4089 * 1 - Enable 4090 * Access: RW 4091 */ 4092 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1); 4093 4094 /* reg_qeec_dwrr 4095 * Transmission selection algorithm to use on the link going down from 4096 * the ETS element. 4097 * 0 - Strict priority 4098 * 1 - DWRR 4099 * Access: RW 4100 */ 4101 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1); 4102 4103 /* reg_qeec_dwrr_weight 4104 * DWRR weight on the link going down from the ETS element. The 4105 * percentage of bandwidth guaranteed to an ETS element within 4106 * its hierarchy. The sum of all weights across all ETS elements 4107 * within one hierarchy should be equal to 100. Reserved when 4108 * transmission selection algorithm is strict priority. 4109 * Access: RW 4110 */ 4111 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8); 4112 4113 /* reg_qeec_max_shaper_bs 4114 * Max shaper burst size 4115 * Burst size is 2^max_shaper_bs * 512 bits 4116 * For Spectrum-1: Range is: 5..25 4117 * For Spectrum-2: Range is: 11..25 4118 * Reserved when ptps = 1 4119 * Access: RW 4120 */ 4121 MLXSW_ITEM32(reg, qeec, max_shaper_bs, 0x1C, 0, 6); 4122 4123 #define MLXSW_REG_QEEC_HIGHEST_SHAPER_BS 25 4124 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1 5 4125 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2 11 4126 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3 11 4127 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP4 11 4128 4129 static inline void mlxsw_reg_qeec_pack(char *payload, u16 local_port, 4130 enum mlxsw_reg_qeec_hr hr, u8 index, 4131 u8 next_index) 4132 { 4133 MLXSW_REG_ZERO(qeec, payload); 4134 mlxsw_reg_qeec_local_port_set(payload, local_port); 4135 mlxsw_reg_qeec_element_hierarchy_set(payload, hr); 4136 mlxsw_reg_qeec_element_index_set(payload, index); 4137 mlxsw_reg_qeec_next_element_index_set(payload, next_index); 4138 } 4139 4140 static inline void mlxsw_reg_qeec_ptps_pack(char *payload, u16 local_port, 4141 bool ptps) 4142 { 4143 MLXSW_REG_ZERO(qeec, payload); 4144 mlxsw_reg_qeec_local_port_set(payload, local_port); 4145 mlxsw_reg_qeec_element_hierarchy_set(payload, MLXSW_REG_QEEC_HR_PORT); 4146 mlxsw_reg_qeec_ptps_set(payload, ptps); 4147 } 4148 4149 /* QRWE - QoS ReWrite Enable 4150 * ------------------------- 4151 * This register configures the rewrite enable per receive port. 4152 */ 4153 #define MLXSW_REG_QRWE_ID 0x400F 4154 #define MLXSW_REG_QRWE_LEN 0x08 4155 4156 MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN); 4157 4158 /* reg_qrwe_local_port 4159 * Local port number. 4160 * Access: Index 4161 * 4162 * Note: CPU port is supported. No support for router port. 4163 */ 4164 MLXSW_ITEM32_LP(reg, qrwe, 0x00, 16, 0x00, 12); 4165 4166 /* reg_qrwe_dscp 4167 * Whether to enable DSCP rewrite (default is 0, don't rewrite). 4168 * Access: RW 4169 */ 4170 MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1); 4171 4172 /* reg_qrwe_pcp 4173 * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite). 4174 * Access: RW 4175 */ 4176 MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1); 4177 4178 static inline void mlxsw_reg_qrwe_pack(char *payload, u16 local_port, 4179 bool rewrite_pcp, bool rewrite_dscp) 4180 { 4181 MLXSW_REG_ZERO(qrwe, payload); 4182 mlxsw_reg_qrwe_local_port_set(payload, local_port); 4183 mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp); 4184 mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp); 4185 } 4186 4187 /* QPDSM - QoS Priority to DSCP Mapping 4188 * ------------------------------------ 4189 * QoS Priority to DSCP Mapping Register 4190 */ 4191 #define MLXSW_REG_QPDSM_ID 0x4011 4192 #define MLXSW_REG_QPDSM_BASE_LEN 0x04 /* base length, without records */ 4193 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4 /* record length */ 4194 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 16 4195 #define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN + \ 4196 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN * \ 4197 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT) 4198 4199 MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN); 4200 4201 /* reg_qpdsm_local_port 4202 * Local Port. Supported for data packets from CPU port. 4203 * Access: Index 4204 */ 4205 MLXSW_ITEM32_LP(reg, qpdsm, 0x00, 16, 0x00, 12); 4206 4207 /* reg_qpdsm_prio_entry_color0_e 4208 * Enable update of the entry for color 0 and a given port. 4209 * Access: WO 4210 */ 4211 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e, 4212 MLXSW_REG_QPDSM_BASE_LEN, 31, 1, 4213 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4214 4215 /* reg_qpdsm_prio_entry_color0_dscp 4216 * DSCP field in the outer label of the packet for color 0 and a given port. 4217 * Reserved when e=0. 4218 * Access: RW 4219 */ 4220 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp, 4221 MLXSW_REG_QPDSM_BASE_LEN, 24, 6, 4222 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4223 4224 /* reg_qpdsm_prio_entry_color1_e 4225 * Enable update of the entry for color 1 and a given port. 4226 * Access: WO 4227 */ 4228 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e, 4229 MLXSW_REG_QPDSM_BASE_LEN, 23, 1, 4230 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4231 4232 /* reg_qpdsm_prio_entry_color1_dscp 4233 * DSCP field in the outer label of the packet for color 1 and a given port. 4234 * Reserved when e=0. 4235 * Access: RW 4236 */ 4237 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp, 4238 MLXSW_REG_QPDSM_BASE_LEN, 16, 6, 4239 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4240 4241 /* reg_qpdsm_prio_entry_color2_e 4242 * Enable update of the entry for color 2 and a given port. 4243 * Access: WO 4244 */ 4245 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e, 4246 MLXSW_REG_QPDSM_BASE_LEN, 15, 1, 4247 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4248 4249 /* reg_qpdsm_prio_entry_color2_dscp 4250 * DSCP field in the outer label of the packet for color 2 and a given port. 4251 * Reserved when e=0. 4252 * Access: RW 4253 */ 4254 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp, 4255 MLXSW_REG_QPDSM_BASE_LEN, 8, 6, 4256 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4257 4258 static inline void mlxsw_reg_qpdsm_pack(char *payload, u16 local_port) 4259 { 4260 MLXSW_REG_ZERO(qpdsm, payload); 4261 mlxsw_reg_qpdsm_local_port_set(payload, local_port); 4262 } 4263 4264 static inline void 4265 mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp) 4266 { 4267 mlxsw_reg_qpdsm_prio_entry_color0_e_set(payload, prio, 1); 4268 mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(payload, prio, dscp); 4269 mlxsw_reg_qpdsm_prio_entry_color1_e_set(payload, prio, 1); 4270 mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(payload, prio, dscp); 4271 mlxsw_reg_qpdsm_prio_entry_color2_e_set(payload, prio, 1); 4272 mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp); 4273 } 4274 4275 /* QPDP - QoS Port DSCP to Priority Mapping Register 4276 * ------------------------------------------------- 4277 * This register controls the port default Switch Priority and Color. The 4278 * default Switch Priority and Color are used for frames where the trust state 4279 * uses default values. All member ports of a LAG should be configured with the 4280 * same default values. 4281 */ 4282 #define MLXSW_REG_QPDP_ID 0x4007 4283 #define MLXSW_REG_QPDP_LEN 0x8 4284 4285 MLXSW_REG_DEFINE(qpdp, MLXSW_REG_QPDP_ID, MLXSW_REG_QPDP_LEN); 4286 4287 /* reg_qpdp_local_port 4288 * Local Port. Supported for data packets from CPU port. 4289 * Access: Index 4290 */ 4291 MLXSW_ITEM32_LP(reg, qpdp, 0x00, 16, 0x00, 12); 4292 4293 /* reg_qpdp_switch_prio 4294 * Default port Switch Priority (default 0) 4295 * Access: RW 4296 */ 4297 MLXSW_ITEM32(reg, qpdp, switch_prio, 0x04, 0, 4); 4298 4299 static inline void mlxsw_reg_qpdp_pack(char *payload, u16 local_port, 4300 u8 switch_prio) 4301 { 4302 MLXSW_REG_ZERO(qpdp, payload); 4303 mlxsw_reg_qpdp_local_port_set(payload, local_port); 4304 mlxsw_reg_qpdp_switch_prio_set(payload, switch_prio); 4305 } 4306 4307 /* QPDPM - QoS Port DSCP to Priority Mapping Register 4308 * -------------------------------------------------- 4309 * This register controls the mapping from DSCP field to 4310 * Switch Priority for IP packets. 4311 */ 4312 #define MLXSW_REG_QPDPM_ID 0x4013 4313 #define MLXSW_REG_QPDPM_BASE_LEN 0x4 /* base length, without records */ 4314 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2 /* record length */ 4315 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64 4316 #define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN + \ 4317 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN * \ 4318 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT) 4319 4320 MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN); 4321 4322 /* reg_qpdpm_local_port 4323 * Local Port. Supported for data packets from CPU port. 4324 * Access: Index 4325 */ 4326 MLXSW_ITEM32_LP(reg, qpdpm, 0x00, 16, 0x00, 12); 4327 4328 /* reg_qpdpm_dscp_e 4329 * Enable update of the specific entry. When cleared, the switch_prio and color 4330 * fields are ignored and the previous switch_prio and color values are 4331 * preserved. 4332 * Access: WO 4333 */ 4334 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1, 4335 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 4336 4337 /* reg_qpdpm_dscp_prio 4338 * The new Switch Priority value for the relevant DSCP value. 4339 * Access: RW 4340 */ 4341 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio, 4342 MLXSW_REG_QPDPM_BASE_LEN, 0, 4, 4343 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 4344 4345 static inline void mlxsw_reg_qpdpm_pack(char *payload, u16 local_port) 4346 { 4347 MLXSW_REG_ZERO(qpdpm, payload); 4348 mlxsw_reg_qpdpm_local_port_set(payload, local_port); 4349 } 4350 4351 static inline void 4352 mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio) 4353 { 4354 mlxsw_reg_qpdpm_dscp_entry_e_set(payload, dscp, 1); 4355 mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio); 4356 } 4357 4358 /* QTCTM - QoS Switch Traffic Class Table is Multicast-Aware Register 4359 * ------------------------------------------------------------------ 4360 * This register configures if the Switch Priority to Traffic Class mapping is 4361 * based on Multicast packet indication. If so, then multicast packets will get 4362 * a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by 4363 * QTCT. 4364 * By default, Switch Priority to Traffic Class mapping is not based on 4365 * Multicast packet indication. 4366 */ 4367 #define MLXSW_REG_QTCTM_ID 0x401A 4368 #define MLXSW_REG_QTCTM_LEN 0x08 4369 4370 MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN); 4371 4372 /* reg_qtctm_local_port 4373 * Local port number. 4374 * No support for CPU port. 4375 * Access: Index 4376 */ 4377 MLXSW_ITEM32_LP(reg, qtctm, 0x00, 16, 0x00, 12); 4378 4379 /* reg_qtctm_mc 4380 * Multicast Mode 4381 * Whether Switch Priority to Traffic Class mapping is based on Multicast packet 4382 * indication (default is 0, not based on Multicast packet indication). 4383 */ 4384 MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1); 4385 4386 static inline void 4387 mlxsw_reg_qtctm_pack(char *payload, u16 local_port, bool mc) 4388 { 4389 MLXSW_REG_ZERO(qtctm, payload); 4390 mlxsw_reg_qtctm_local_port_set(payload, local_port); 4391 mlxsw_reg_qtctm_mc_set(payload, mc); 4392 } 4393 4394 /* QPSC - QoS PTP Shaper Configuration Register 4395 * -------------------------------------------- 4396 * The QPSC allows advanced configuration of the shapers when QEEC.ptps=1. 4397 * Supported only on Spectrum-1. 4398 */ 4399 #define MLXSW_REG_QPSC_ID 0x401B 4400 #define MLXSW_REG_QPSC_LEN 0x28 4401 4402 MLXSW_REG_DEFINE(qpsc, MLXSW_REG_QPSC_ID, MLXSW_REG_QPSC_LEN); 4403 4404 enum mlxsw_reg_qpsc_port_speed { 4405 MLXSW_REG_QPSC_PORT_SPEED_100M, 4406 MLXSW_REG_QPSC_PORT_SPEED_1G, 4407 MLXSW_REG_QPSC_PORT_SPEED_10G, 4408 MLXSW_REG_QPSC_PORT_SPEED_25G, 4409 }; 4410 4411 /* reg_qpsc_port_speed 4412 * Port speed. 4413 * Access: Index 4414 */ 4415 MLXSW_ITEM32(reg, qpsc, port_speed, 0x00, 0, 4); 4416 4417 /* reg_qpsc_shaper_time_exp 4418 * The base-time-interval for updating the shapers tokens (for all hierarchies). 4419 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec 4420 * shaper_rate = 64bit * shaper_inc / shaper_update_rate 4421 * Access: RW 4422 */ 4423 MLXSW_ITEM32(reg, qpsc, shaper_time_exp, 0x04, 16, 4); 4424 4425 /* reg_qpsc_shaper_time_mantissa 4426 * The base-time-interval for updating the shapers tokens (for all hierarchies). 4427 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec 4428 * shaper_rate = 64bit * shaper_inc / shaper_update_rate 4429 * Access: RW 4430 */ 4431 MLXSW_ITEM32(reg, qpsc, shaper_time_mantissa, 0x04, 0, 5); 4432 4433 /* reg_qpsc_shaper_inc 4434 * Number of tokens added to shaper on each update. 4435 * Units of 8B. 4436 * Access: RW 4437 */ 4438 MLXSW_ITEM32(reg, qpsc, shaper_inc, 0x08, 0, 5); 4439 4440 /* reg_qpsc_shaper_bs 4441 * Max shaper Burst size. 4442 * Burst size is 2 ^ max_shaper_bs * 512 [bits] 4443 * Range is: 5..25 (from 2KB..2GB) 4444 * Access: RW 4445 */ 4446 MLXSW_ITEM32(reg, qpsc, shaper_bs, 0x0C, 0, 6); 4447 4448 /* reg_qpsc_ptsc_we 4449 * Write enable to port_to_shaper_credits. 4450 * Access: WO 4451 */ 4452 MLXSW_ITEM32(reg, qpsc, ptsc_we, 0x10, 31, 1); 4453 4454 /* reg_qpsc_port_to_shaper_credits 4455 * For split ports: range 1..57 4456 * For non-split ports: range 1..112 4457 * Written only when ptsc_we is set. 4458 * Access: RW 4459 */ 4460 MLXSW_ITEM32(reg, qpsc, port_to_shaper_credits, 0x10, 0, 8); 4461 4462 /* reg_qpsc_ing_timestamp_inc 4463 * Ingress timestamp increment. 4464 * 2's complement. 4465 * The timestamp of MTPPTR at ingress will be incremented by this value. Global 4466 * value for all ports. 4467 * Same units as used by MTPPTR. 4468 * Access: RW 4469 */ 4470 MLXSW_ITEM32(reg, qpsc, ing_timestamp_inc, 0x20, 0, 32); 4471 4472 /* reg_qpsc_egr_timestamp_inc 4473 * Egress timestamp increment. 4474 * 2's complement. 4475 * The timestamp of MTPPTR at egress will be incremented by this value. Global 4476 * value for all ports. 4477 * Same units as used by MTPPTR. 4478 * Access: RW 4479 */ 4480 MLXSW_ITEM32(reg, qpsc, egr_timestamp_inc, 0x24, 0, 32); 4481 4482 static inline void 4483 mlxsw_reg_qpsc_pack(char *payload, enum mlxsw_reg_qpsc_port_speed port_speed, 4484 u8 shaper_time_exp, u8 shaper_time_mantissa, u8 shaper_inc, 4485 u8 shaper_bs, u8 port_to_shaper_credits, 4486 int ing_timestamp_inc, int egr_timestamp_inc) 4487 { 4488 MLXSW_REG_ZERO(qpsc, payload); 4489 mlxsw_reg_qpsc_port_speed_set(payload, port_speed); 4490 mlxsw_reg_qpsc_shaper_time_exp_set(payload, shaper_time_exp); 4491 mlxsw_reg_qpsc_shaper_time_mantissa_set(payload, shaper_time_mantissa); 4492 mlxsw_reg_qpsc_shaper_inc_set(payload, shaper_inc); 4493 mlxsw_reg_qpsc_shaper_bs_set(payload, shaper_bs); 4494 mlxsw_reg_qpsc_ptsc_we_set(payload, true); 4495 mlxsw_reg_qpsc_port_to_shaper_credits_set(payload, port_to_shaper_credits); 4496 mlxsw_reg_qpsc_ing_timestamp_inc_set(payload, ing_timestamp_inc); 4497 mlxsw_reg_qpsc_egr_timestamp_inc_set(payload, egr_timestamp_inc); 4498 } 4499 4500 /* PMLP - Ports Module to Local Port Register 4501 * ------------------------------------------ 4502 * Configures the assignment of modules to local ports. 4503 */ 4504 #define MLXSW_REG_PMLP_ID 0x5002 4505 #define MLXSW_REG_PMLP_LEN 0x40 4506 4507 MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN); 4508 4509 /* reg_pmlp_rxtx 4510 * 0 - Tx value is used for both Tx and Rx. 4511 * 1 - Rx value is taken from a separte field. 4512 * Access: RW 4513 */ 4514 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1); 4515 4516 /* reg_pmlp_local_port 4517 * Local port number. 4518 * Access: Index 4519 */ 4520 MLXSW_ITEM32_LP(reg, pmlp, 0x00, 16, 0x00, 12); 4521 4522 /* reg_pmlp_width 4523 * 0 - Unmap local port. 4524 * 1 - Lane 0 is used. 4525 * 2 - Lanes 0 and 1 are used. 4526 * 4 - Lanes 0, 1, 2 and 3 are used. 4527 * 8 - Lanes 0-7 are used. 4528 * Access: RW 4529 */ 4530 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8); 4531 4532 /* reg_pmlp_module 4533 * Module number. 4534 * Access: RW 4535 */ 4536 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false); 4537 4538 /* reg_pmlp_slot_index 4539 * Module number. 4540 * Slot_index 4541 * Slot_index = 0 represent the onboard (motherboard). 4542 * In case of non-modular system only slot_index = 0 is available. 4543 * Access: RW 4544 */ 4545 MLXSW_ITEM32_INDEXED(reg, pmlp, slot_index, 0x04, 8, 4, 0x04, 0x00, false); 4546 4547 /* reg_pmlp_tx_lane 4548 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well. 4549 * Access: RW 4550 */ 4551 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 4, 0x04, 0x00, false); 4552 4553 /* reg_pmlp_rx_lane 4554 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is 4555 * equal to Tx lane. 4556 * Access: RW 4557 */ 4558 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 4, 0x04, 0x00, false); 4559 4560 static inline void mlxsw_reg_pmlp_pack(char *payload, u16 local_port) 4561 { 4562 MLXSW_REG_ZERO(pmlp, payload); 4563 mlxsw_reg_pmlp_local_port_set(payload, local_port); 4564 } 4565 4566 /* PMTU - Port MTU Register 4567 * ------------------------ 4568 * Configures and reports the port MTU. 4569 */ 4570 #define MLXSW_REG_PMTU_ID 0x5003 4571 #define MLXSW_REG_PMTU_LEN 0x10 4572 4573 MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN); 4574 4575 /* reg_pmtu_local_port 4576 * Local port number. 4577 * Access: Index 4578 */ 4579 MLXSW_ITEM32_LP(reg, pmtu, 0x00, 16, 0x00, 12); 4580 4581 /* reg_pmtu_max_mtu 4582 * Maximum MTU. 4583 * When port type (e.g. Ethernet) is configured, the relevant MTU is 4584 * reported, otherwise the minimum between the max_mtu of the different 4585 * types is reported. 4586 * Access: RO 4587 */ 4588 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16); 4589 4590 /* reg_pmtu_admin_mtu 4591 * MTU value to set port to. Must be smaller or equal to max_mtu. 4592 * Note: If port type is Infiniband, then port must be disabled, when its 4593 * MTU is set. 4594 * Access: RW 4595 */ 4596 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16); 4597 4598 /* reg_pmtu_oper_mtu 4599 * The actual MTU configured on the port. Packets exceeding this size 4600 * will be dropped. 4601 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband 4602 * oper_mtu might be smaller than admin_mtu. 4603 * Access: RO 4604 */ 4605 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16); 4606 4607 static inline void mlxsw_reg_pmtu_pack(char *payload, u16 local_port, 4608 u16 new_mtu) 4609 { 4610 MLXSW_REG_ZERO(pmtu, payload); 4611 mlxsw_reg_pmtu_local_port_set(payload, local_port); 4612 mlxsw_reg_pmtu_max_mtu_set(payload, 0); 4613 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu); 4614 mlxsw_reg_pmtu_oper_mtu_set(payload, 0); 4615 } 4616 4617 /* PTYS - Port Type and Speed Register 4618 * ----------------------------------- 4619 * Configures and reports the port speed type. 4620 * 4621 * Note: When set while the link is up, the changes will not take effect 4622 * until the port transitions from down to up state. 4623 */ 4624 #define MLXSW_REG_PTYS_ID 0x5004 4625 #define MLXSW_REG_PTYS_LEN 0x40 4626 4627 MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN); 4628 4629 /* an_disable_admin 4630 * Auto negotiation disable administrative configuration 4631 * 0 - Device doesn't support AN disable. 4632 * 1 - Device supports AN disable. 4633 * Access: RW 4634 */ 4635 MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1); 4636 4637 /* reg_ptys_local_port 4638 * Local port number. 4639 * Access: Index 4640 */ 4641 MLXSW_ITEM32_LP(reg, ptys, 0x00, 16, 0x00, 12); 4642 4643 #define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0) 4644 #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2) 4645 4646 /* reg_ptys_proto_mask 4647 * Protocol mask. Indicates which protocol is used. 4648 * 0 - Infiniband. 4649 * 1 - Fibre Channel. 4650 * 2 - Ethernet. 4651 * Access: Index 4652 */ 4653 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3); 4654 4655 enum { 4656 MLXSW_REG_PTYS_AN_STATUS_NA, 4657 MLXSW_REG_PTYS_AN_STATUS_OK, 4658 MLXSW_REG_PTYS_AN_STATUS_FAIL, 4659 }; 4660 4661 /* reg_ptys_an_status 4662 * Autonegotiation status. 4663 * Access: RO 4664 */ 4665 MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4); 4666 4667 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M BIT(0) 4668 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII BIT(1) 4669 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R BIT(3) 4670 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G BIT(4) 4671 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G BIT(5) 4672 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR BIT(6) 4673 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 BIT(7) 4674 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR BIT(8) 4675 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4 BIT(9) 4676 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2 BIT(10) 4677 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4 BIT(12) 4678 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_8 BIT(15) 4679 4680 /* reg_ptys_ext_eth_proto_cap 4681 * Extended Ethernet port supported speeds and protocols. 4682 * Access: RO 4683 */ 4684 MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32); 4685 4686 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0) 4687 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1) 4688 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2) 4689 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3) 4690 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4) 4691 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6) 4692 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7) 4693 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12) 4694 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13) 4695 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14) 4696 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15) 4697 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16) 4698 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18) 4699 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19) 4700 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20) 4701 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21) 4702 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22) 4703 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23) 4704 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(24) 4705 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_T BIT(25) 4706 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27) 4707 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28) 4708 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29) 4709 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30) 4710 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31) 4711 4712 /* reg_ptys_eth_proto_cap 4713 * Ethernet port supported speeds and protocols. 4714 * Access: RO 4715 */ 4716 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32); 4717 4718 /* reg_ptys_ib_link_width_cap 4719 * IB port supported widths. 4720 * Access: RO 4721 */ 4722 MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16); 4723 4724 #define MLXSW_REG_PTYS_IB_SPEED_SDR BIT(0) 4725 #define MLXSW_REG_PTYS_IB_SPEED_DDR BIT(1) 4726 #define MLXSW_REG_PTYS_IB_SPEED_QDR BIT(2) 4727 #define MLXSW_REG_PTYS_IB_SPEED_FDR10 BIT(3) 4728 #define MLXSW_REG_PTYS_IB_SPEED_FDR BIT(4) 4729 #define MLXSW_REG_PTYS_IB_SPEED_EDR BIT(5) 4730 4731 /* reg_ptys_ib_proto_cap 4732 * IB port supported speeds and protocols. 4733 * Access: RO 4734 */ 4735 MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16); 4736 4737 /* reg_ptys_ext_eth_proto_admin 4738 * Extended speed and protocol to set port to. 4739 * Access: RW 4740 */ 4741 MLXSW_ITEM32(reg, ptys, ext_eth_proto_admin, 0x14, 0, 32); 4742 4743 /* reg_ptys_eth_proto_admin 4744 * Speed and protocol to set port to. 4745 * Access: RW 4746 */ 4747 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32); 4748 4749 /* reg_ptys_ib_link_width_admin 4750 * IB width to set port to. 4751 * Access: RW 4752 */ 4753 MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16); 4754 4755 /* reg_ptys_ib_proto_admin 4756 * IB speeds and protocols to set port to. 4757 * Access: RW 4758 */ 4759 MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16); 4760 4761 /* reg_ptys_ext_eth_proto_oper 4762 * The extended current speed and protocol configured for the port. 4763 * Access: RO 4764 */ 4765 MLXSW_ITEM32(reg, ptys, ext_eth_proto_oper, 0x20, 0, 32); 4766 4767 /* reg_ptys_eth_proto_oper 4768 * The current speed and protocol configured for the port. 4769 * Access: RO 4770 */ 4771 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32); 4772 4773 /* reg_ptys_ib_link_width_oper 4774 * The current IB width to set port to. 4775 * Access: RO 4776 */ 4777 MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16); 4778 4779 /* reg_ptys_ib_proto_oper 4780 * The current IB speed and protocol. 4781 * Access: RO 4782 */ 4783 MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16); 4784 4785 enum mlxsw_reg_ptys_connector_type { 4786 MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR, 4787 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE, 4788 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP, 4789 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI, 4790 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC, 4791 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII, 4792 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE, 4793 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA, 4794 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER, 4795 }; 4796 4797 /* reg_ptys_connector_type 4798 * Connector type indication. 4799 * Access: RO 4800 */ 4801 MLXSW_ITEM32(reg, ptys, connector_type, 0x2C, 0, 4); 4802 4803 static inline void mlxsw_reg_ptys_eth_pack(char *payload, u16 local_port, 4804 u32 proto_admin, bool autoneg) 4805 { 4806 MLXSW_REG_ZERO(ptys, payload); 4807 mlxsw_reg_ptys_local_port_set(payload, local_port); 4808 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4809 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin); 4810 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4811 } 4812 4813 static inline void mlxsw_reg_ptys_ext_eth_pack(char *payload, u16 local_port, 4814 u32 proto_admin, bool autoneg) 4815 { 4816 MLXSW_REG_ZERO(ptys, payload); 4817 mlxsw_reg_ptys_local_port_set(payload, local_port); 4818 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4819 mlxsw_reg_ptys_ext_eth_proto_admin_set(payload, proto_admin); 4820 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4821 } 4822 4823 static inline void mlxsw_reg_ptys_eth_unpack(char *payload, 4824 u32 *p_eth_proto_cap, 4825 u32 *p_eth_proto_admin, 4826 u32 *p_eth_proto_oper) 4827 { 4828 if (p_eth_proto_cap) 4829 *p_eth_proto_cap = 4830 mlxsw_reg_ptys_eth_proto_cap_get(payload); 4831 if (p_eth_proto_admin) 4832 *p_eth_proto_admin = 4833 mlxsw_reg_ptys_eth_proto_admin_get(payload); 4834 if (p_eth_proto_oper) 4835 *p_eth_proto_oper = 4836 mlxsw_reg_ptys_eth_proto_oper_get(payload); 4837 } 4838 4839 static inline void mlxsw_reg_ptys_ext_eth_unpack(char *payload, 4840 u32 *p_eth_proto_cap, 4841 u32 *p_eth_proto_admin, 4842 u32 *p_eth_proto_oper) 4843 { 4844 if (p_eth_proto_cap) 4845 *p_eth_proto_cap = 4846 mlxsw_reg_ptys_ext_eth_proto_cap_get(payload); 4847 if (p_eth_proto_admin) 4848 *p_eth_proto_admin = 4849 mlxsw_reg_ptys_ext_eth_proto_admin_get(payload); 4850 if (p_eth_proto_oper) 4851 *p_eth_proto_oper = 4852 mlxsw_reg_ptys_ext_eth_proto_oper_get(payload); 4853 } 4854 4855 static inline void mlxsw_reg_ptys_ib_pack(char *payload, u16 local_port, 4856 u16 proto_admin, u16 link_width) 4857 { 4858 MLXSW_REG_ZERO(ptys, payload); 4859 mlxsw_reg_ptys_local_port_set(payload, local_port); 4860 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB); 4861 mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin); 4862 mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width); 4863 } 4864 4865 static inline void mlxsw_reg_ptys_ib_unpack(char *payload, u16 *p_ib_proto_cap, 4866 u16 *p_ib_link_width_cap, 4867 u16 *p_ib_proto_oper, 4868 u16 *p_ib_link_width_oper) 4869 { 4870 if (p_ib_proto_cap) 4871 *p_ib_proto_cap = mlxsw_reg_ptys_ib_proto_cap_get(payload); 4872 if (p_ib_link_width_cap) 4873 *p_ib_link_width_cap = 4874 mlxsw_reg_ptys_ib_link_width_cap_get(payload); 4875 if (p_ib_proto_oper) 4876 *p_ib_proto_oper = mlxsw_reg_ptys_ib_proto_oper_get(payload); 4877 if (p_ib_link_width_oper) 4878 *p_ib_link_width_oper = 4879 mlxsw_reg_ptys_ib_link_width_oper_get(payload); 4880 } 4881 4882 /* PPAD - Port Physical Address Register 4883 * ------------------------------------- 4884 * The PPAD register configures the per port physical MAC address. 4885 */ 4886 #define MLXSW_REG_PPAD_ID 0x5005 4887 #define MLXSW_REG_PPAD_LEN 0x10 4888 4889 MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN); 4890 4891 /* reg_ppad_single_base_mac 4892 * 0: base_mac, local port should be 0 and mac[7:0] is 4893 * reserved. HW will set incremental 4894 * 1: single_mac - mac of the local_port 4895 * Access: RW 4896 */ 4897 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1); 4898 4899 /* reg_ppad_local_port 4900 * port number, if single_base_mac = 0 then local_port is reserved 4901 * Access: RW 4902 */ 4903 MLXSW_ITEM32_LP(reg, ppad, 0x00, 16, 0x00, 24); 4904 4905 /* reg_ppad_mac 4906 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved. 4907 * If single_base_mac = 1 - the per port MAC address 4908 * Access: RW 4909 */ 4910 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6); 4911 4912 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac, 4913 u16 local_port) 4914 { 4915 MLXSW_REG_ZERO(ppad, payload); 4916 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac); 4917 mlxsw_reg_ppad_local_port_set(payload, local_port); 4918 } 4919 4920 /* PAOS - Ports Administrative and Operational Status Register 4921 * ----------------------------------------------------------- 4922 * Configures and retrieves per port administrative and operational status. 4923 */ 4924 #define MLXSW_REG_PAOS_ID 0x5006 4925 #define MLXSW_REG_PAOS_LEN 0x10 4926 4927 MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN); 4928 4929 /* reg_paos_swid 4930 * Switch partition ID with which to associate the port. 4931 * Note: while external ports uses unique local port numbers (and thus swid is 4932 * redundant), router ports use the same local port number where swid is the 4933 * only indication for the relevant port. 4934 * Access: Index 4935 */ 4936 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8); 4937 4938 /* reg_paos_local_port 4939 * Local port number. 4940 * Access: Index 4941 */ 4942 MLXSW_ITEM32_LP(reg, paos, 0x00, 16, 0x00, 12); 4943 4944 /* reg_paos_admin_status 4945 * Port administrative state (the desired state of the port): 4946 * 1 - Up. 4947 * 2 - Down. 4948 * 3 - Up once. This means that in case of link failure, the port won't go 4949 * into polling mode, but will wait to be re-enabled by software. 4950 * 4 - Disabled by system. Can only be set by hardware. 4951 * Access: RW 4952 */ 4953 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4); 4954 4955 /* reg_paos_oper_status 4956 * Port operational state (the current state): 4957 * 1 - Up. 4958 * 2 - Down. 4959 * 3 - Down by port failure. This means that the device will not let the 4960 * port up again until explicitly specified by software. 4961 * Access: RO 4962 */ 4963 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4); 4964 4965 /* reg_paos_ase 4966 * Admin state update enabled. 4967 * Access: WO 4968 */ 4969 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1); 4970 4971 /* reg_paos_ee 4972 * Event update enable. If this bit is set, event generation will be 4973 * updated based on the e field. 4974 * Access: WO 4975 */ 4976 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1); 4977 4978 /* reg_paos_e 4979 * Event generation on operational state change: 4980 * 0 - Do not generate event. 4981 * 1 - Generate Event. 4982 * 2 - Generate Single Event. 4983 * Access: RW 4984 */ 4985 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2); 4986 4987 static inline void mlxsw_reg_paos_pack(char *payload, u16 local_port, 4988 enum mlxsw_port_admin_status status) 4989 { 4990 MLXSW_REG_ZERO(paos, payload); 4991 mlxsw_reg_paos_swid_set(payload, 0); 4992 mlxsw_reg_paos_local_port_set(payload, local_port); 4993 mlxsw_reg_paos_admin_status_set(payload, status); 4994 mlxsw_reg_paos_oper_status_set(payload, 0); 4995 mlxsw_reg_paos_ase_set(payload, 1); 4996 mlxsw_reg_paos_ee_set(payload, 1); 4997 mlxsw_reg_paos_e_set(payload, 1); 4998 } 4999 5000 /* PFCC - Ports Flow Control Configuration Register 5001 * ------------------------------------------------ 5002 * Configures and retrieves the per port flow control configuration. 5003 */ 5004 #define MLXSW_REG_PFCC_ID 0x5007 5005 #define MLXSW_REG_PFCC_LEN 0x20 5006 5007 MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN); 5008 5009 /* reg_pfcc_local_port 5010 * Local port number. 5011 * Access: Index 5012 */ 5013 MLXSW_ITEM32_LP(reg, pfcc, 0x00, 16, 0x00, 12); 5014 5015 /* reg_pfcc_pnat 5016 * Port number access type. Determines the way local_port is interpreted: 5017 * 0 - Local port number. 5018 * 1 - IB / label port number. 5019 * Access: Index 5020 */ 5021 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2); 5022 5023 /* reg_pfcc_shl_cap 5024 * Send to higher layers capabilities: 5025 * 0 - No capability of sending Pause and PFC frames to higher layers. 5026 * 1 - Device has capability of sending Pause and PFC frames to higher 5027 * layers. 5028 * Access: RO 5029 */ 5030 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1); 5031 5032 /* reg_pfcc_shl_opr 5033 * Send to higher layers operation: 5034 * 0 - Pause and PFC frames are handled by the port (default). 5035 * 1 - Pause and PFC frames are handled by the port and also sent to 5036 * higher layers. Only valid if shl_cap = 1. 5037 * Access: RW 5038 */ 5039 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1); 5040 5041 /* reg_pfcc_ppan 5042 * Pause policy auto negotiation. 5043 * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx. 5044 * 1 - Enabled. When auto-negotiation is performed, set the Pause policy 5045 * based on the auto-negotiation resolution. 5046 * Access: RW 5047 * 5048 * Note: The auto-negotiation advertisement is set according to pptx and 5049 * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0. 5050 */ 5051 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4); 5052 5053 /* reg_pfcc_prio_mask_tx 5054 * Bit per priority indicating if Tx flow control policy should be 5055 * updated based on bit pfctx. 5056 * Access: WO 5057 */ 5058 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8); 5059 5060 /* reg_pfcc_prio_mask_rx 5061 * Bit per priority indicating if Rx flow control policy should be 5062 * updated based on bit pfcrx. 5063 * Access: WO 5064 */ 5065 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8); 5066 5067 /* reg_pfcc_pptx 5068 * Admin Pause policy on Tx. 5069 * 0 - Never generate Pause frames (default). 5070 * 1 - Generate Pause frames according to Rx buffer threshold. 5071 * Access: RW 5072 */ 5073 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1); 5074 5075 /* reg_pfcc_aptx 5076 * Active (operational) Pause policy on Tx. 5077 * 0 - Never generate Pause frames. 5078 * 1 - Generate Pause frames according to Rx buffer threshold. 5079 * Access: RO 5080 */ 5081 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1); 5082 5083 /* reg_pfcc_pfctx 5084 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask: 5085 * 0 - Never generate priority Pause frames on the specified priority 5086 * (default). 5087 * 1 - Generate priority Pause frames according to Rx buffer threshold on 5088 * the specified priority. 5089 * Access: RW 5090 * 5091 * Note: pfctx and pptx must be mutually exclusive. 5092 */ 5093 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8); 5094 5095 /* reg_pfcc_pprx 5096 * Admin Pause policy on Rx. 5097 * 0 - Ignore received Pause frames (default). 5098 * 1 - Respect received Pause frames. 5099 * Access: RW 5100 */ 5101 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1); 5102 5103 /* reg_pfcc_aprx 5104 * Active (operational) Pause policy on Rx. 5105 * 0 - Ignore received Pause frames. 5106 * 1 - Respect received Pause frames. 5107 * Access: RO 5108 */ 5109 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1); 5110 5111 /* reg_pfcc_pfcrx 5112 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask: 5113 * 0 - Ignore incoming priority Pause frames on the specified priority 5114 * (default). 5115 * 1 - Respect incoming priority Pause frames on the specified priority. 5116 * Access: RW 5117 */ 5118 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8); 5119 5120 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF 5121 5122 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en) 5123 { 5124 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 5125 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 5126 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en); 5127 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en); 5128 } 5129 5130 static inline void mlxsw_reg_pfcc_pack(char *payload, u16 local_port) 5131 { 5132 MLXSW_REG_ZERO(pfcc, payload); 5133 mlxsw_reg_pfcc_local_port_set(payload, local_port); 5134 } 5135 5136 /* PPCNT - Ports Performance Counters Register 5137 * ------------------------------------------- 5138 * The PPCNT register retrieves per port performance counters. 5139 */ 5140 #define MLXSW_REG_PPCNT_ID 0x5008 5141 #define MLXSW_REG_PPCNT_LEN 0x100 5142 #define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08 5143 5144 MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN); 5145 5146 /* reg_ppcnt_swid 5147 * For HCA: must be always 0. 5148 * Switch partition ID to associate port with. 5149 * Switch partitions are numbered from 0 to 7 inclusively. 5150 * Switch partition 254 indicates stacking ports. 5151 * Switch partition 255 indicates all switch partitions. 5152 * Only valid on Set() operation with local_port=255. 5153 * Access: Index 5154 */ 5155 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8); 5156 5157 /* reg_ppcnt_local_port 5158 * Local port number. 5159 * Access: Index 5160 */ 5161 MLXSW_ITEM32_LP(reg, ppcnt, 0x00, 16, 0x00, 12); 5162 5163 /* reg_ppcnt_pnat 5164 * Port number access type: 5165 * 0 - Local port number 5166 * 1 - IB port number 5167 * Access: Index 5168 */ 5169 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2); 5170 5171 enum mlxsw_reg_ppcnt_grp { 5172 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0, 5173 MLXSW_REG_PPCNT_RFC_2863_CNT = 0x1, 5174 MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2, 5175 MLXSW_REG_PPCNT_RFC_3635_CNT = 0x3, 5176 MLXSW_REG_PPCNT_EXT_CNT = 0x5, 5177 MLXSW_REG_PPCNT_DISCARD_CNT = 0x6, 5178 MLXSW_REG_PPCNT_PRIO_CNT = 0x10, 5179 MLXSW_REG_PPCNT_TC_CNT = 0x11, 5180 MLXSW_REG_PPCNT_TC_CONG_CNT = 0x13, 5181 }; 5182 5183 /* reg_ppcnt_grp 5184 * Performance counter group. 5185 * Group 63 indicates all groups. Only valid on Set() operation with 5186 * clr bit set. 5187 * 0x0: IEEE 802.3 Counters 5188 * 0x1: RFC 2863 Counters 5189 * 0x2: RFC 2819 Counters 5190 * 0x3: RFC 3635 Counters 5191 * 0x5: Ethernet Extended Counters 5192 * 0x6: Ethernet Discard Counters 5193 * 0x8: Link Level Retransmission Counters 5194 * 0x10: Per Priority Counters 5195 * 0x11: Per Traffic Class Counters 5196 * 0x12: Physical Layer Counters 5197 * 0x13: Per Traffic Class Congestion Counters 5198 * Access: Index 5199 */ 5200 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6); 5201 5202 /* reg_ppcnt_clr 5203 * Clear counters. Setting the clr bit will reset the counter value 5204 * for all counters in the counter group. This bit can be set 5205 * for both Set() and Get() operation. 5206 * Access: OP 5207 */ 5208 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1); 5209 5210 /* reg_ppcnt_lp_gl 5211 * Local port global variable. 5212 * 0: local_port 255 = all ports of the device. 5213 * 1: local_port indicates local port number for all ports. 5214 * Access: OP 5215 */ 5216 MLXSW_ITEM32(reg, ppcnt, lp_gl, 0x04, 30, 1); 5217 5218 /* reg_ppcnt_prio_tc 5219 * Priority for counter set that support per priority, valid values: 0-7. 5220 * Traffic class for counter set that support per traffic class, 5221 * valid values: 0- cap_max_tclass-1 . 5222 * For HCA: cap_max_tclass is always 8. 5223 * Otherwise must be 0. 5224 * Access: Index 5225 */ 5226 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5); 5227 5228 /* Ethernet IEEE 802.3 Counter Group */ 5229 5230 /* reg_ppcnt_a_frames_transmitted_ok 5231 * Access: RO 5232 */ 5233 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok, 5234 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5235 5236 /* reg_ppcnt_a_frames_received_ok 5237 * Access: RO 5238 */ 5239 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok, 5240 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5241 5242 /* reg_ppcnt_a_frame_check_sequence_errors 5243 * Access: RO 5244 */ 5245 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors, 5246 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 5247 5248 /* reg_ppcnt_a_alignment_errors 5249 * Access: RO 5250 */ 5251 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors, 5252 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 5253 5254 /* reg_ppcnt_a_octets_transmitted_ok 5255 * Access: RO 5256 */ 5257 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok, 5258 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5259 5260 /* reg_ppcnt_a_octets_received_ok 5261 * Access: RO 5262 */ 5263 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok, 5264 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5265 5266 /* reg_ppcnt_a_multicast_frames_xmitted_ok 5267 * Access: RO 5268 */ 5269 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok, 5270 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 5271 5272 /* reg_ppcnt_a_broadcast_frames_xmitted_ok 5273 * Access: RO 5274 */ 5275 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok, 5276 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 5277 5278 /* reg_ppcnt_a_multicast_frames_received_ok 5279 * Access: RO 5280 */ 5281 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok, 5282 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5283 5284 /* reg_ppcnt_a_broadcast_frames_received_ok 5285 * Access: RO 5286 */ 5287 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok, 5288 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 5289 5290 /* reg_ppcnt_a_in_range_length_errors 5291 * Access: RO 5292 */ 5293 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors, 5294 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5295 5296 /* reg_ppcnt_a_out_of_range_length_field 5297 * Access: RO 5298 */ 5299 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field, 5300 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5301 5302 /* reg_ppcnt_a_frame_too_long_errors 5303 * Access: RO 5304 */ 5305 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors, 5306 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5307 5308 /* reg_ppcnt_a_symbol_error_during_carrier 5309 * Access: RO 5310 */ 5311 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier, 5312 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5313 5314 /* reg_ppcnt_a_mac_control_frames_transmitted 5315 * Access: RO 5316 */ 5317 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted, 5318 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5319 5320 /* reg_ppcnt_a_mac_control_frames_received 5321 * Access: RO 5322 */ 5323 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received, 5324 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 5325 5326 /* reg_ppcnt_a_unsupported_opcodes_received 5327 * Access: RO 5328 */ 5329 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received, 5330 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 5331 5332 /* reg_ppcnt_a_pause_mac_ctrl_frames_received 5333 * Access: RO 5334 */ 5335 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received, 5336 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 5337 5338 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted 5339 * Access: RO 5340 */ 5341 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted, 5342 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 5343 5344 /* Ethernet RFC 2863 Counter Group */ 5345 5346 /* reg_ppcnt_if_in_discards 5347 * Access: RO 5348 */ 5349 MLXSW_ITEM64(reg, ppcnt, if_in_discards, 5350 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 5351 5352 /* reg_ppcnt_if_out_discards 5353 * Access: RO 5354 */ 5355 MLXSW_ITEM64(reg, ppcnt, if_out_discards, 5356 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 5357 5358 /* reg_ppcnt_if_out_errors 5359 * Access: RO 5360 */ 5361 MLXSW_ITEM64(reg, ppcnt, if_out_errors, 5362 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5363 5364 /* Ethernet RFC 2819 Counter Group */ 5365 5366 /* reg_ppcnt_ether_stats_undersize_pkts 5367 * Access: RO 5368 */ 5369 MLXSW_ITEM64(reg, ppcnt, ether_stats_undersize_pkts, 5370 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 5371 5372 /* reg_ppcnt_ether_stats_oversize_pkts 5373 * Access: RO 5374 */ 5375 MLXSW_ITEM64(reg, ppcnt, ether_stats_oversize_pkts, 5376 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 5377 5378 /* reg_ppcnt_ether_stats_fragments 5379 * Access: RO 5380 */ 5381 MLXSW_ITEM64(reg, ppcnt, ether_stats_fragments, 5382 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5383 5384 /* reg_ppcnt_ether_stats_pkts64octets 5385 * Access: RO 5386 */ 5387 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets, 5388 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5389 5390 /* reg_ppcnt_ether_stats_pkts65to127octets 5391 * Access: RO 5392 */ 5393 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets, 5394 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5395 5396 /* reg_ppcnt_ether_stats_pkts128to255octets 5397 * Access: RO 5398 */ 5399 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets, 5400 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5401 5402 /* reg_ppcnt_ether_stats_pkts256to511octets 5403 * Access: RO 5404 */ 5405 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets, 5406 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5407 5408 /* reg_ppcnt_ether_stats_pkts512to1023octets 5409 * Access: RO 5410 */ 5411 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets, 5412 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 5413 5414 /* reg_ppcnt_ether_stats_pkts1024to1518octets 5415 * Access: RO 5416 */ 5417 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets, 5418 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 5419 5420 /* reg_ppcnt_ether_stats_pkts1519to2047octets 5421 * Access: RO 5422 */ 5423 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets, 5424 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 5425 5426 /* reg_ppcnt_ether_stats_pkts2048to4095octets 5427 * Access: RO 5428 */ 5429 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets, 5430 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 5431 5432 /* reg_ppcnt_ether_stats_pkts4096to8191octets 5433 * Access: RO 5434 */ 5435 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets, 5436 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64); 5437 5438 /* reg_ppcnt_ether_stats_pkts8192to10239octets 5439 * Access: RO 5440 */ 5441 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets, 5442 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64); 5443 5444 /* Ethernet RFC 3635 Counter Group */ 5445 5446 /* reg_ppcnt_dot3stats_fcs_errors 5447 * Access: RO 5448 */ 5449 MLXSW_ITEM64(reg, ppcnt, dot3stats_fcs_errors, 5450 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5451 5452 /* reg_ppcnt_dot3stats_symbol_errors 5453 * Access: RO 5454 */ 5455 MLXSW_ITEM64(reg, ppcnt, dot3stats_symbol_errors, 5456 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5457 5458 /* reg_ppcnt_dot3control_in_unknown_opcodes 5459 * Access: RO 5460 */ 5461 MLXSW_ITEM64(reg, ppcnt, dot3control_in_unknown_opcodes, 5462 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5463 5464 /* reg_ppcnt_dot3in_pause_frames 5465 * Access: RO 5466 */ 5467 MLXSW_ITEM64(reg, ppcnt, dot3in_pause_frames, 5468 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5469 5470 /* Ethernet Extended Counter Group Counters */ 5471 5472 /* reg_ppcnt_ecn_marked 5473 * Access: RO 5474 */ 5475 MLXSW_ITEM64(reg, ppcnt, ecn_marked, 5476 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5477 5478 /* Ethernet Discard Counter Group Counters */ 5479 5480 /* reg_ppcnt_ingress_general 5481 * Access: RO 5482 */ 5483 MLXSW_ITEM64(reg, ppcnt, ingress_general, 5484 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5485 5486 /* reg_ppcnt_ingress_policy_engine 5487 * Access: RO 5488 */ 5489 MLXSW_ITEM64(reg, ppcnt, ingress_policy_engine, 5490 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5491 5492 /* reg_ppcnt_ingress_vlan_membership 5493 * Access: RO 5494 */ 5495 MLXSW_ITEM64(reg, ppcnt, ingress_vlan_membership, 5496 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 5497 5498 /* reg_ppcnt_ingress_tag_frame_type 5499 * Access: RO 5500 */ 5501 MLXSW_ITEM64(reg, ppcnt, ingress_tag_frame_type, 5502 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 5503 5504 /* reg_ppcnt_egress_vlan_membership 5505 * Access: RO 5506 */ 5507 MLXSW_ITEM64(reg, ppcnt, egress_vlan_membership, 5508 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5509 5510 /* reg_ppcnt_loopback_filter 5511 * Access: RO 5512 */ 5513 MLXSW_ITEM64(reg, ppcnt, loopback_filter, 5514 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5515 5516 /* reg_ppcnt_egress_general 5517 * Access: RO 5518 */ 5519 MLXSW_ITEM64(reg, ppcnt, egress_general, 5520 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 5521 5522 /* reg_ppcnt_egress_hoq 5523 * Access: RO 5524 */ 5525 MLXSW_ITEM64(reg, ppcnt, egress_hoq, 5526 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5527 5528 /* reg_ppcnt_egress_policy_engine 5529 * Access: RO 5530 */ 5531 MLXSW_ITEM64(reg, ppcnt, egress_policy_engine, 5532 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5533 5534 /* reg_ppcnt_ingress_tx_link_down 5535 * Access: RO 5536 */ 5537 MLXSW_ITEM64(reg, ppcnt, ingress_tx_link_down, 5538 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5539 5540 /* reg_ppcnt_egress_stp_filter 5541 * Access: RO 5542 */ 5543 MLXSW_ITEM64(reg, ppcnt, egress_stp_filter, 5544 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5545 5546 /* reg_ppcnt_egress_sll 5547 * Access: RO 5548 */ 5549 MLXSW_ITEM64(reg, ppcnt, egress_sll, 5550 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5551 5552 /* Ethernet Per Priority Group Counters */ 5553 5554 /* reg_ppcnt_rx_octets 5555 * Access: RO 5556 */ 5557 MLXSW_ITEM64(reg, ppcnt, rx_octets, 5558 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5559 5560 /* reg_ppcnt_rx_frames 5561 * Access: RO 5562 */ 5563 MLXSW_ITEM64(reg, ppcnt, rx_frames, 5564 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5565 5566 /* reg_ppcnt_tx_octets 5567 * Access: RO 5568 */ 5569 MLXSW_ITEM64(reg, ppcnt, tx_octets, 5570 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5571 5572 /* reg_ppcnt_tx_frames 5573 * Access: RO 5574 */ 5575 MLXSW_ITEM64(reg, ppcnt, tx_frames, 5576 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 5577 5578 /* reg_ppcnt_rx_pause 5579 * Access: RO 5580 */ 5581 MLXSW_ITEM64(reg, ppcnt, rx_pause, 5582 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5583 5584 /* reg_ppcnt_rx_pause_duration 5585 * Access: RO 5586 */ 5587 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration, 5588 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5589 5590 /* reg_ppcnt_tx_pause 5591 * Access: RO 5592 */ 5593 MLXSW_ITEM64(reg, ppcnt, tx_pause, 5594 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5595 5596 /* reg_ppcnt_tx_pause_duration 5597 * Access: RO 5598 */ 5599 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration, 5600 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5601 5602 /* reg_ppcnt_rx_pause_transition 5603 * Access: RO 5604 */ 5605 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition, 5606 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5607 5608 /* Ethernet Per Traffic Class Counters */ 5609 5610 /* reg_ppcnt_tc_transmit_queue 5611 * Contains the transmit queue depth in cells of traffic class 5612 * selected by prio_tc and the port selected by local_port. 5613 * The field cannot be cleared. 5614 * Access: RO 5615 */ 5616 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue, 5617 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5618 5619 /* reg_ppcnt_tc_no_buffer_discard_uc 5620 * The number of unicast packets dropped due to lack of shared 5621 * buffer resources. 5622 * Access: RO 5623 */ 5624 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc, 5625 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5626 5627 /* Ethernet Per Traffic Class Congestion Group Counters */ 5628 5629 /* reg_ppcnt_wred_discard 5630 * Access: RO 5631 */ 5632 MLXSW_ITEM64(reg, ppcnt, wred_discard, 5633 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5634 5635 /* reg_ppcnt_ecn_marked_tc 5636 * Access: RO 5637 */ 5638 MLXSW_ITEM64(reg, ppcnt, ecn_marked_tc, 5639 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5640 5641 static inline void mlxsw_reg_ppcnt_pack(char *payload, u16 local_port, 5642 enum mlxsw_reg_ppcnt_grp grp, 5643 u8 prio_tc) 5644 { 5645 MLXSW_REG_ZERO(ppcnt, payload); 5646 mlxsw_reg_ppcnt_swid_set(payload, 0); 5647 mlxsw_reg_ppcnt_local_port_set(payload, local_port); 5648 mlxsw_reg_ppcnt_pnat_set(payload, 0); 5649 mlxsw_reg_ppcnt_grp_set(payload, grp); 5650 mlxsw_reg_ppcnt_clr_set(payload, 0); 5651 mlxsw_reg_ppcnt_lp_gl_set(payload, 1); 5652 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc); 5653 } 5654 5655 /* PLIB - Port Local to InfiniBand Port 5656 * ------------------------------------ 5657 * The PLIB register performs mapping from Local Port into InfiniBand Port. 5658 */ 5659 #define MLXSW_REG_PLIB_ID 0x500A 5660 #define MLXSW_REG_PLIB_LEN 0x10 5661 5662 MLXSW_REG_DEFINE(plib, MLXSW_REG_PLIB_ID, MLXSW_REG_PLIB_LEN); 5663 5664 /* reg_plib_local_port 5665 * Local port number. 5666 * Access: Index 5667 */ 5668 MLXSW_ITEM32_LP(reg, plib, 0x00, 16, 0x00, 12); 5669 5670 /* reg_plib_ib_port 5671 * InfiniBand port remapping for local_port. 5672 * Access: RW 5673 */ 5674 MLXSW_ITEM32(reg, plib, ib_port, 0x00, 0, 8); 5675 5676 /* PPTB - Port Prio To Buffer Register 5677 * ----------------------------------- 5678 * Configures the switch priority to buffer table. 5679 */ 5680 #define MLXSW_REG_PPTB_ID 0x500B 5681 #define MLXSW_REG_PPTB_LEN 0x10 5682 5683 MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN); 5684 5685 enum { 5686 MLXSW_REG_PPTB_MM_UM, 5687 MLXSW_REG_PPTB_MM_UNICAST, 5688 MLXSW_REG_PPTB_MM_MULTICAST, 5689 }; 5690 5691 /* reg_pptb_mm 5692 * Mapping mode. 5693 * 0 - Map both unicast and multicast packets to the same buffer. 5694 * 1 - Map only unicast packets. 5695 * 2 - Map only multicast packets. 5696 * Access: Index 5697 * 5698 * Note: SwitchX-2 only supports the first option. 5699 */ 5700 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2); 5701 5702 /* reg_pptb_local_port 5703 * Local port number. 5704 * Access: Index 5705 */ 5706 MLXSW_ITEM32_LP(reg, pptb, 0x00, 16, 0x00, 12); 5707 5708 /* reg_pptb_um 5709 * Enables the update of the untagged_buf field. 5710 * Access: RW 5711 */ 5712 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1); 5713 5714 /* reg_pptb_pm 5715 * Enables the update of the prio_to_buff field. 5716 * Bit <i> is a flag for updating the mapping for switch priority <i>. 5717 * Access: RW 5718 */ 5719 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8); 5720 5721 /* reg_pptb_prio_to_buff 5722 * Mapping of switch priority <i> to one of the allocated receive port 5723 * buffers. 5724 * Access: RW 5725 */ 5726 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4); 5727 5728 /* reg_pptb_pm_msb 5729 * Enables the update of the prio_to_buff field. 5730 * Bit <i> is a flag for updating the mapping for switch priority <i+8>. 5731 * Access: RW 5732 */ 5733 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8); 5734 5735 /* reg_pptb_untagged_buff 5736 * Mapping of untagged frames to one of the allocated receive port buffers. 5737 * Access: RW 5738 * 5739 * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for 5740 * Spectrum, as it maps untagged packets based on the default switch priority. 5741 */ 5742 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4); 5743 5744 /* reg_pptb_prio_to_buff_msb 5745 * Mapping of switch priority <i+8> to one of the allocated receive port 5746 * buffers. 5747 * Access: RW 5748 */ 5749 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4); 5750 5751 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF 5752 5753 static inline void mlxsw_reg_pptb_pack(char *payload, u16 local_port) 5754 { 5755 MLXSW_REG_ZERO(pptb, payload); 5756 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM); 5757 mlxsw_reg_pptb_local_port_set(payload, local_port); 5758 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 5759 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 5760 } 5761 5762 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio, 5763 u8 buff) 5764 { 5765 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff); 5766 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff); 5767 } 5768 5769 /* PBMC - Port Buffer Management Control Register 5770 * ---------------------------------------------- 5771 * The PBMC register configures and retrieves the port packet buffer 5772 * allocation for different Prios, and the Pause threshold management. 5773 */ 5774 #define MLXSW_REG_PBMC_ID 0x500C 5775 #define MLXSW_REG_PBMC_LEN 0x6C 5776 5777 MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN); 5778 5779 /* reg_pbmc_local_port 5780 * Local port number. 5781 * Access: Index 5782 */ 5783 MLXSW_ITEM32_LP(reg, pbmc, 0x00, 16, 0x00, 12); 5784 5785 /* reg_pbmc_xoff_timer_value 5786 * When device generates a pause frame, it uses this value as the pause 5787 * timer (time for the peer port to pause in quota-512 bit time). 5788 * Access: RW 5789 */ 5790 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16); 5791 5792 /* reg_pbmc_xoff_refresh 5793 * The time before a new pause frame should be sent to refresh the pause RW 5794 * state. Using the same units as xoff_timer_value above (in quota-512 bit 5795 * time). 5796 * Access: RW 5797 */ 5798 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16); 5799 5800 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11 5801 5802 /* reg_pbmc_buf_lossy 5803 * The field indicates if the buffer is lossy. 5804 * 0 - Lossless 5805 * 1 - Lossy 5806 * Access: RW 5807 */ 5808 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false); 5809 5810 /* reg_pbmc_buf_epsb 5811 * Eligible for Port Shared buffer. 5812 * If epsb is set, packets assigned to buffer are allowed to insert the port 5813 * shared buffer. 5814 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved. 5815 * Access: RW 5816 */ 5817 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false); 5818 5819 /* reg_pbmc_buf_size 5820 * The part of the packet buffer array is allocated for the specific buffer. 5821 * Units are represented in cells. 5822 * Access: RW 5823 */ 5824 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false); 5825 5826 /* reg_pbmc_buf_xoff_threshold 5827 * Once the amount of data in the buffer goes above this value, device 5828 * starts sending PFC frames for all priorities associated with the 5829 * buffer. Units are represented in cells. Reserved in case of lossy 5830 * buffer. 5831 * Access: RW 5832 * 5833 * Note: In Spectrum, reserved for buffer[9]. 5834 */ 5835 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16, 5836 0x08, 0x04, false); 5837 5838 /* reg_pbmc_buf_xon_threshold 5839 * When the amount of data in the buffer goes below this value, device 5840 * stops sending PFC frames for the priorities associated with the 5841 * buffer. Units are represented in cells. Reserved in case of lossy 5842 * buffer. 5843 * Access: RW 5844 * 5845 * Note: In Spectrum, reserved for buffer[9]. 5846 */ 5847 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16, 5848 0x08, 0x04, false); 5849 5850 static inline void mlxsw_reg_pbmc_pack(char *payload, u16 local_port, 5851 u16 xoff_timer_value, u16 xoff_refresh) 5852 { 5853 MLXSW_REG_ZERO(pbmc, payload); 5854 mlxsw_reg_pbmc_local_port_set(payload, local_port); 5855 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value); 5856 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh); 5857 } 5858 5859 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload, 5860 int buf_index, 5861 u16 size) 5862 { 5863 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1); 5864 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5865 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5866 } 5867 5868 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload, 5869 int buf_index, u16 size, 5870 u16 threshold) 5871 { 5872 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0); 5873 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5874 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5875 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold); 5876 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold); 5877 } 5878 5879 /* PSPA - Port Switch Partition Allocation 5880 * --------------------------------------- 5881 * Controls the association of a port with a switch partition and enables 5882 * configuring ports as stacking ports. 5883 */ 5884 #define MLXSW_REG_PSPA_ID 0x500D 5885 #define MLXSW_REG_PSPA_LEN 0x8 5886 5887 MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN); 5888 5889 /* reg_pspa_swid 5890 * Switch partition ID. 5891 * Access: RW 5892 */ 5893 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8); 5894 5895 /* reg_pspa_local_port 5896 * Local port number. 5897 * Access: Index 5898 */ 5899 MLXSW_ITEM32_LP(reg, pspa, 0x00, 16, 0x00, 0); 5900 5901 /* reg_pspa_sub_port 5902 * Virtual port within the local port. Set to 0 when virtual ports are 5903 * disabled on the local port. 5904 * Access: Index 5905 */ 5906 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8); 5907 5908 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u16 local_port) 5909 { 5910 MLXSW_REG_ZERO(pspa, payload); 5911 mlxsw_reg_pspa_swid_set(payload, swid); 5912 mlxsw_reg_pspa_local_port_set(payload, local_port); 5913 mlxsw_reg_pspa_sub_port_set(payload, 0); 5914 } 5915 5916 /* PMAOS - Ports Module Administrative and Operational Status 5917 * ---------------------------------------------------------- 5918 * This register configures and retrieves the per module status. 5919 */ 5920 #define MLXSW_REG_PMAOS_ID 0x5012 5921 #define MLXSW_REG_PMAOS_LEN 0x10 5922 5923 MLXSW_REG_DEFINE(pmaos, MLXSW_REG_PMAOS_ID, MLXSW_REG_PMAOS_LEN); 5924 5925 /* reg_pmaos_rst 5926 * Module reset toggle. 5927 * Note: Setting reset while module is plugged-in will result in transition to 5928 * "initializing" operational state. 5929 * Access: OP 5930 */ 5931 MLXSW_ITEM32(reg, pmaos, rst, 0x00, 31, 1); 5932 5933 /* reg_pmaos_slot_index 5934 * Slot index. 5935 * Access: Index 5936 */ 5937 MLXSW_ITEM32(reg, pmaos, slot_index, 0x00, 24, 4); 5938 5939 /* reg_pmaos_module 5940 * Module number. 5941 * Access: Index 5942 */ 5943 MLXSW_ITEM32(reg, pmaos, module, 0x00, 16, 8); 5944 5945 enum mlxsw_reg_pmaos_admin_status { 5946 MLXSW_REG_PMAOS_ADMIN_STATUS_ENABLED = 1, 5947 MLXSW_REG_PMAOS_ADMIN_STATUS_DISABLED = 2, 5948 /* If the module is active and then unplugged, or experienced an error 5949 * event, the operational status should go to "disabled" and can only 5950 * be enabled upon explicit enable command. 5951 */ 5952 MLXSW_REG_PMAOS_ADMIN_STATUS_ENABLED_ONCE = 3, 5953 }; 5954 5955 /* reg_pmaos_admin_status 5956 * Module administrative state (the desired state of the module). 5957 * Note: To disable a module, all ports associated with the port must be 5958 * administatively down first. 5959 * Access: RW 5960 */ 5961 MLXSW_ITEM32(reg, pmaos, admin_status, 0x00, 8, 4); 5962 5963 /* reg_pmaos_ase 5964 * Admin state update enable. 5965 * If this bit is set, admin state will be updated based on admin_state field. 5966 * Only relevant on Set() operations. 5967 * Access: WO 5968 */ 5969 MLXSW_ITEM32(reg, pmaos, ase, 0x04, 31, 1); 5970 5971 /* reg_pmaos_ee 5972 * Event update enable. 5973 * If this bit is set, event generation will be updated based on the e field. 5974 * Only relevant on Set operations. 5975 * Access: WO 5976 */ 5977 MLXSW_ITEM32(reg, pmaos, ee, 0x04, 30, 1); 5978 5979 enum mlxsw_reg_pmaos_e { 5980 MLXSW_REG_PMAOS_E_DO_NOT_GENERATE_EVENT, 5981 MLXSW_REG_PMAOS_E_GENERATE_EVENT, 5982 MLXSW_REG_PMAOS_E_GENERATE_SINGLE_EVENT, 5983 }; 5984 5985 /* reg_pmaos_e 5986 * Event Generation on operational state change. 5987 * Access: RW 5988 */ 5989 MLXSW_ITEM32(reg, pmaos, e, 0x04, 0, 2); 5990 5991 static inline void mlxsw_reg_pmaos_pack(char *payload, u8 slot_index, u8 module) 5992 { 5993 MLXSW_REG_ZERO(pmaos, payload); 5994 mlxsw_reg_pmaos_slot_index_set(payload, slot_index); 5995 mlxsw_reg_pmaos_module_set(payload, module); 5996 } 5997 5998 /* PPLR - Port Physical Loopback Register 5999 * -------------------------------------- 6000 * This register allows configuration of the port's loopback mode. 6001 */ 6002 #define MLXSW_REG_PPLR_ID 0x5018 6003 #define MLXSW_REG_PPLR_LEN 0x8 6004 6005 MLXSW_REG_DEFINE(pplr, MLXSW_REG_PPLR_ID, MLXSW_REG_PPLR_LEN); 6006 6007 /* reg_pplr_local_port 6008 * Local port number. 6009 * Access: Index 6010 */ 6011 MLXSW_ITEM32_LP(reg, pplr, 0x00, 16, 0x00, 12); 6012 6013 /* Phy local loopback. When set the port's egress traffic is looped back 6014 * to the receiver and the port transmitter is disabled. 6015 */ 6016 #define MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL BIT(1) 6017 6018 /* reg_pplr_lb_en 6019 * Loopback enable. 6020 * Access: RW 6021 */ 6022 MLXSW_ITEM32(reg, pplr, lb_en, 0x04, 0, 8); 6023 6024 static inline void mlxsw_reg_pplr_pack(char *payload, u16 local_port, 6025 bool phy_local) 6026 { 6027 MLXSW_REG_ZERO(pplr, payload); 6028 mlxsw_reg_pplr_local_port_set(payload, local_port); 6029 mlxsw_reg_pplr_lb_en_set(payload, 6030 phy_local ? 6031 MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL : 0); 6032 } 6033 6034 /* PMTDB - Port Module To local DataBase Register 6035 * ---------------------------------------------- 6036 * The PMTDB register allows to query the possible module<->local port 6037 * mapping than can be used in PMLP. It does not represent the actual/current 6038 * mapping of the local to module. Actual mapping is only defined by PMLP. 6039 */ 6040 #define MLXSW_REG_PMTDB_ID 0x501A 6041 #define MLXSW_REG_PMTDB_LEN 0x40 6042 6043 MLXSW_REG_DEFINE(pmtdb, MLXSW_REG_PMTDB_ID, MLXSW_REG_PMTDB_LEN); 6044 6045 /* reg_pmtdb_slot_index 6046 * Slot index (0: Main board). 6047 * Access: Index 6048 */ 6049 MLXSW_ITEM32(reg, pmtdb, slot_index, 0x00, 24, 4); 6050 6051 /* reg_pmtdb_module 6052 * Module number. 6053 * Access: Index 6054 */ 6055 MLXSW_ITEM32(reg, pmtdb, module, 0x00, 16, 8); 6056 6057 /* reg_pmtdb_ports_width 6058 * Port's width 6059 * Access: Index 6060 */ 6061 MLXSW_ITEM32(reg, pmtdb, ports_width, 0x00, 12, 4); 6062 6063 /* reg_pmtdb_num_ports 6064 * Number of ports in a single module (split/breakout) 6065 * Access: Index 6066 */ 6067 MLXSW_ITEM32(reg, pmtdb, num_ports, 0x00, 8, 4); 6068 6069 enum mlxsw_reg_pmtdb_status { 6070 MLXSW_REG_PMTDB_STATUS_SUCCESS, 6071 }; 6072 6073 /* reg_pmtdb_status 6074 * Status 6075 * Access: RO 6076 */ 6077 MLXSW_ITEM32(reg, pmtdb, status, 0x00, 0, 4); 6078 6079 /* reg_pmtdb_port_num 6080 * The local_port value which can be assigned to the module. 6081 * In case of more than one port, port<x> represent the /<x> port of 6082 * the module. 6083 * Access: RO 6084 */ 6085 MLXSW_ITEM16_INDEXED(reg, pmtdb, port_num, 0x04, 0, 10, 0x02, 0x00, false); 6086 6087 static inline void mlxsw_reg_pmtdb_pack(char *payload, u8 slot_index, u8 module, 6088 u8 ports_width, u8 num_ports) 6089 { 6090 MLXSW_REG_ZERO(pmtdb, payload); 6091 mlxsw_reg_pmtdb_slot_index_set(payload, slot_index); 6092 mlxsw_reg_pmtdb_module_set(payload, module); 6093 mlxsw_reg_pmtdb_ports_width_set(payload, ports_width); 6094 mlxsw_reg_pmtdb_num_ports_set(payload, num_ports); 6095 } 6096 6097 /* PMECR - Ports Mapping Event Configuration Register 6098 * -------------------------------------------------- 6099 * The PMECR register is used to enable/disable event triggering 6100 * in case of local port mapping change. 6101 */ 6102 #define MLXSW_REG_PMECR_ID 0x501B 6103 #define MLXSW_REG_PMECR_LEN 0x20 6104 6105 MLXSW_REG_DEFINE(pmecr, MLXSW_REG_PMECR_ID, MLXSW_REG_PMECR_LEN); 6106 6107 /* reg_pmecr_local_port 6108 * Local port number. 6109 * Access: Index 6110 */ 6111 MLXSW_ITEM32_LP(reg, pmecr, 0x00, 16, 0x00, 12); 6112 6113 /* reg_pmecr_ee 6114 * Event update enable. If this bit is set, event generation will be updated 6115 * based on the e field. Only relevant on Set operations. 6116 * Access: WO 6117 */ 6118 MLXSW_ITEM32(reg, pmecr, ee, 0x04, 30, 1); 6119 6120 /* reg_pmecr_eswi 6121 * Software ignore enable bit. If this bit is set, the value of swi is used. 6122 * If this bit is clear, the value of swi is ignored. 6123 * Only relevant on Set operations. 6124 * Access: WO 6125 */ 6126 MLXSW_ITEM32(reg, pmecr, eswi, 0x04, 24, 1); 6127 6128 /* reg_pmecr_swi 6129 * Software ignore. If this bit is set, the device shouldn't generate events 6130 * in case of PMLP SET operation but only upon self local port mapping change 6131 * (if applicable according to e configuration). This is supplementary 6132 * configuration on top of e value. 6133 * Access: RW 6134 */ 6135 MLXSW_ITEM32(reg, pmecr, swi, 0x04, 8, 1); 6136 6137 enum mlxsw_reg_pmecr_e { 6138 MLXSW_REG_PMECR_E_DO_NOT_GENERATE_EVENT, 6139 MLXSW_REG_PMECR_E_GENERATE_EVENT, 6140 MLXSW_REG_PMECR_E_GENERATE_SINGLE_EVENT, 6141 }; 6142 6143 /* reg_pmecr_e 6144 * Event generation on local port mapping change. 6145 * Access: RW 6146 */ 6147 MLXSW_ITEM32(reg, pmecr, e, 0x04, 0, 2); 6148 6149 static inline void mlxsw_reg_pmecr_pack(char *payload, u16 local_port, 6150 enum mlxsw_reg_pmecr_e e) 6151 { 6152 MLXSW_REG_ZERO(pmecr, payload); 6153 mlxsw_reg_pmecr_local_port_set(payload, local_port); 6154 mlxsw_reg_pmecr_e_set(payload, e); 6155 mlxsw_reg_pmecr_ee_set(payload, true); 6156 mlxsw_reg_pmecr_swi_set(payload, true); 6157 mlxsw_reg_pmecr_eswi_set(payload, true); 6158 } 6159 6160 /* PMPE - Port Module Plug/Unplug Event Register 6161 * --------------------------------------------- 6162 * This register reports any operational status change of a module. 6163 * A change in the module’s state will generate an event only if the change 6164 * happens after arming the event mechanism. Any changes to the module state 6165 * while the event mechanism is not armed will not be reported. Software can 6166 * query the PMPE register for module status. 6167 */ 6168 #define MLXSW_REG_PMPE_ID 0x5024 6169 #define MLXSW_REG_PMPE_LEN 0x10 6170 6171 MLXSW_REG_DEFINE(pmpe, MLXSW_REG_PMPE_ID, MLXSW_REG_PMPE_LEN); 6172 6173 /* reg_pmpe_slot_index 6174 * Slot index. 6175 * Access: Index 6176 */ 6177 MLXSW_ITEM32(reg, pmpe, slot_index, 0x00, 24, 4); 6178 6179 /* reg_pmpe_module 6180 * Module number. 6181 * Access: Index 6182 */ 6183 MLXSW_ITEM32(reg, pmpe, module, 0x00, 16, 8); 6184 6185 enum mlxsw_reg_pmpe_module_status { 6186 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_ENABLED = 1, 6187 MLXSW_REG_PMPE_MODULE_STATUS_UNPLUGGED, 6188 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_ERROR, 6189 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_DISABLED, 6190 }; 6191 6192 /* reg_pmpe_module_status 6193 * Module status. 6194 * Access: RO 6195 */ 6196 MLXSW_ITEM32(reg, pmpe, module_status, 0x00, 0, 4); 6197 6198 /* reg_pmpe_error_type 6199 * Module error details. 6200 * Access: RO 6201 */ 6202 MLXSW_ITEM32(reg, pmpe, error_type, 0x04, 8, 4); 6203 6204 /* PDDR - Port Diagnostics Database Register 6205 * ----------------------------------------- 6206 * The PDDR enables to read the Phy debug database 6207 */ 6208 #define MLXSW_REG_PDDR_ID 0x5031 6209 #define MLXSW_REG_PDDR_LEN 0x100 6210 6211 MLXSW_REG_DEFINE(pddr, MLXSW_REG_PDDR_ID, MLXSW_REG_PDDR_LEN); 6212 6213 /* reg_pddr_local_port 6214 * Local port number. 6215 * Access: Index 6216 */ 6217 MLXSW_ITEM32_LP(reg, pddr, 0x00, 16, 0x00, 12); 6218 6219 enum mlxsw_reg_pddr_page_select { 6220 MLXSW_REG_PDDR_PAGE_SELECT_TROUBLESHOOTING_INFO = 1, 6221 }; 6222 6223 /* reg_pddr_page_select 6224 * Page select index. 6225 * Access: Index 6226 */ 6227 MLXSW_ITEM32(reg, pddr, page_select, 0x04, 0, 8); 6228 6229 enum mlxsw_reg_pddr_trblsh_group_opcode { 6230 /* Monitor opcodes */ 6231 MLXSW_REG_PDDR_TRBLSH_GROUP_OPCODE_MONITOR, 6232 }; 6233 6234 /* reg_pddr_group_opcode 6235 * Group selector. 6236 * Access: Index 6237 */ 6238 MLXSW_ITEM32(reg, pddr, trblsh_group_opcode, 0x08, 0, 16); 6239 6240 /* reg_pddr_status_opcode 6241 * Group selector. 6242 * Access: RO 6243 */ 6244 MLXSW_ITEM32(reg, pddr, trblsh_status_opcode, 0x0C, 0, 16); 6245 6246 static inline void mlxsw_reg_pddr_pack(char *payload, u16 local_port, 6247 u8 page_select) 6248 { 6249 MLXSW_REG_ZERO(pddr, payload); 6250 mlxsw_reg_pddr_local_port_set(payload, local_port); 6251 mlxsw_reg_pddr_page_select_set(payload, page_select); 6252 } 6253 6254 /* PMMP - Port Module Memory Map Properties Register 6255 * ------------------------------------------------- 6256 * The PMMP register allows to override the module memory map advertisement. 6257 * The register can only be set when the module is disabled by PMAOS register. 6258 */ 6259 #define MLXSW_REG_PMMP_ID 0x5044 6260 #define MLXSW_REG_PMMP_LEN 0x2C 6261 6262 MLXSW_REG_DEFINE(pmmp, MLXSW_REG_PMMP_ID, MLXSW_REG_PMMP_LEN); 6263 6264 /* reg_pmmp_module 6265 * Module number. 6266 * Access: Index 6267 */ 6268 MLXSW_ITEM32(reg, pmmp, module, 0x00, 16, 8); 6269 6270 /* reg_pmmp_slot_index 6271 * Slot index. 6272 * Access: Index 6273 */ 6274 MLXSW_ITEM32(reg, pmmp, slot_index, 0x00, 24, 4); 6275 6276 /* reg_pmmp_sticky 6277 * When set, will keep eeprom_override values after plug-out event. 6278 * Access: OP 6279 */ 6280 MLXSW_ITEM32(reg, pmmp, sticky, 0x00, 0, 1); 6281 6282 /* reg_pmmp_eeprom_override_mask 6283 * Write mask bit (negative polarity). 6284 * 0 - Allow write 6285 * 1 - Ignore write 6286 * On write, indicates which of the bits from eeprom_override field are 6287 * updated. 6288 * Access: WO 6289 */ 6290 MLXSW_ITEM32(reg, pmmp, eeprom_override_mask, 0x04, 16, 16); 6291 6292 enum { 6293 /* Set module to low power mode */ 6294 MLXSW_REG_PMMP_EEPROM_OVERRIDE_LOW_POWER_MASK = BIT(8), 6295 }; 6296 6297 /* reg_pmmp_eeprom_override 6298 * Override / ignore EEPROM advertisement properties bitmask 6299 * Access: RW 6300 */ 6301 MLXSW_ITEM32(reg, pmmp, eeprom_override, 0x04, 0, 16); 6302 6303 static inline void mlxsw_reg_pmmp_pack(char *payload, u8 slot_index, u8 module) 6304 { 6305 MLXSW_REG_ZERO(pmmp, payload); 6306 mlxsw_reg_pmmp_slot_index_set(payload, slot_index); 6307 mlxsw_reg_pmmp_module_set(payload, module); 6308 } 6309 6310 /* PLLP - Port Local port to Label Port mapping Register 6311 * ----------------------------------------------------- 6312 * The PLLP register returns the mapping from Local Port into Label Port. 6313 */ 6314 #define MLXSW_REG_PLLP_ID 0x504A 6315 #define MLXSW_REG_PLLP_LEN 0x10 6316 6317 MLXSW_REG_DEFINE(pllp, MLXSW_REG_PLLP_ID, MLXSW_REG_PLLP_LEN); 6318 6319 /* reg_pllp_local_port 6320 * Local port number. 6321 * Access: Index 6322 */ 6323 MLXSW_ITEM32_LP(reg, pllp, 0x00, 16, 0x00, 12); 6324 6325 /* reg_pllp_label_port 6326 * Front panel label of the port. 6327 * Access: RO 6328 */ 6329 MLXSW_ITEM32(reg, pllp, label_port, 0x00, 0, 8); 6330 6331 /* reg_pllp_split_num 6332 * Label split mapping for local_port. 6333 * Access: RO 6334 */ 6335 MLXSW_ITEM32(reg, pllp, split_num, 0x04, 0, 4); 6336 6337 /* reg_pllp_slot_index 6338 * Slot index (0: Main board). 6339 * Access: RO 6340 */ 6341 MLXSW_ITEM32(reg, pllp, slot_index, 0x08, 0, 4); 6342 6343 static inline void mlxsw_reg_pllp_pack(char *payload, u16 local_port) 6344 { 6345 MLXSW_REG_ZERO(pllp, payload); 6346 mlxsw_reg_pllp_local_port_set(payload, local_port); 6347 } 6348 6349 static inline void mlxsw_reg_pllp_unpack(char *payload, u8 *label_port, 6350 u8 *split_num, u8 *slot_index) 6351 { 6352 *label_port = mlxsw_reg_pllp_label_port_get(payload); 6353 *split_num = mlxsw_reg_pllp_split_num_get(payload); 6354 *slot_index = mlxsw_reg_pllp_slot_index_get(payload); 6355 } 6356 6357 /* PMTM - Port Module Type Mapping Register 6358 * ---------------------------------------- 6359 * The PMTM register allows query or configuration of module types. 6360 * The register can only be set when the module is disabled by PMAOS register 6361 */ 6362 #define MLXSW_REG_PMTM_ID 0x5067 6363 #define MLXSW_REG_PMTM_LEN 0x10 6364 6365 MLXSW_REG_DEFINE(pmtm, MLXSW_REG_PMTM_ID, MLXSW_REG_PMTM_LEN); 6366 6367 /* reg_pmtm_slot_index 6368 * Slot index. 6369 * Access: Index 6370 */ 6371 MLXSW_ITEM32(reg, pmtm, slot_index, 0x00, 24, 4); 6372 6373 /* reg_pmtm_module 6374 * Module number. 6375 * Access: Index 6376 */ 6377 MLXSW_ITEM32(reg, pmtm, module, 0x00, 16, 8); 6378 6379 enum mlxsw_reg_pmtm_module_type { 6380 MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_4_LANES = 0, 6381 MLXSW_REG_PMTM_MODULE_TYPE_QSFP = 1, 6382 MLXSW_REG_PMTM_MODULE_TYPE_SFP = 2, 6383 MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_SINGLE_LANE = 4, 6384 MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_2_LANES = 8, 6385 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP4X = 10, 6386 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP2X = 11, 6387 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP1X = 12, 6388 MLXSW_REG_PMTM_MODULE_TYPE_QSFP_DD = 14, 6389 MLXSW_REG_PMTM_MODULE_TYPE_OSFP = 15, 6390 MLXSW_REG_PMTM_MODULE_TYPE_SFP_DD = 16, 6391 MLXSW_REG_PMTM_MODULE_TYPE_DSFP = 17, 6392 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP8X = 18, 6393 MLXSW_REG_PMTM_MODULE_TYPE_TWISTED_PAIR = 19, 6394 }; 6395 6396 /* reg_pmtm_module_type 6397 * Module type. 6398 * Access: RW 6399 */ 6400 MLXSW_ITEM32(reg, pmtm, module_type, 0x04, 0, 5); 6401 6402 static inline void mlxsw_reg_pmtm_pack(char *payload, u8 slot_index, u8 module) 6403 { 6404 MLXSW_REG_ZERO(pmtm, payload); 6405 mlxsw_reg_pmtm_slot_index_set(payload, slot_index); 6406 mlxsw_reg_pmtm_module_set(payload, module); 6407 } 6408 6409 /* HTGT - Host Trap Group Table 6410 * ---------------------------- 6411 * Configures the properties for forwarding to CPU. 6412 */ 6413 #define MLXSW_REG_HTGT_ID 0x7002 6414 #define MLXSW_REG_HTGT_LEN 0x20 6415 6416 MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN); 6417 6418 /* reg_htgt_swid 6419 * Switch partition ID. 6420 * Access: Index 6421 */ 6422 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8); 6423 6424 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */ 6425 6426 /* reg_htgt_type 6427 * CPU path type. 6428 * Access: RW 6429 */ 6430 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4); 6431 6432 enum mlxsw_reg_htgt_trap_group { 6433 MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 6434 MLXSW_REG_HTGT_TRAP_GROUP_CORE_EVENT, 6435 MLXSW_REG_HTGT_TRAP_GROUP_SP_STP, 6436 MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP, 6437 MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP, 6438 MLXSW_REG_HTGT_TRAP_GROUP_SP_MC_SNOOPING, 6439 MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP, 6440 MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF, 6441 MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM, 6442 MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST, 6443 MLXSW_REG_HTGT_TRAP_GROUP_SP_NEIGH_DISCOVERY, 6444 MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP, 6445 MLXSW_REG_HTGT_TRAP_GROUP_SP_EXTERNAL_ROUTE, 6446 MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME, 6447 MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP, 6448 MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT, 6449 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6, 6450 MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR, 6451 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0, 6452 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1, 6453 MLXSW_REG_HTGT_TRAP_GROUP_SP_VRRP, 6454 MLXSW_REG_HTGT_TRAP_GROUP_SP_PKT_SAMPLE, 6455 MLXSW_REG_HTGT_TRAP_GROUP_SP_FLOW_LOGGING, 6456 MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS, 6457 MLXSW_REG_HTGT_TRAP_GROUP_SP_BFD, 6458 MLXSW_REG_HTGT_TRAP_GROUP_SP_DUMMY, 6459 MLXSW_REG_HTGT_TRAP_GROUP_SP_L2_DISCARDS, 6460 MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_DISCARDS, 6461 MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_EXCEPTIONS, 6462 MLXSW_REG_HTGT_TRAP_GROUP_SP_TUNNEL_DISCARDS, 6463 MLXSW_REG_HTGT_TRAP_GROUP_SP_ACL_DISCARDS, 6464 MLXSW_REG_HTGT_TRAP_GROUP_SP_BUFFER_DISCARDS, 6465 6466 __MLXSW_REG_HTGT_TRAP_GROUP_MAX, 6467 MLXSW_REG_HTGT_TRAP_GROUP_MAX = __MLXSW_REG_HTGT_TRAP_GROUP_MAX - 1 6468 }; 6469 6470 /* reg_htgt_trap_group 6471 * Trap group number. User defined number specifying which trap groups 6472 * should be forwarded to the CPU. The mapping between trap IDs and trap 6473 * groups is configured using HPKT register. 6474 * Access: Index 6475 */ 6476 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8); 6477 6478 enum { 6479 MLXSW_REG_HTGT_POLICER_DISABLE, 6480 MLXSW_REG_HTGT_POLICER_ENABLE, 6481 }; 6482 6483 /* reg_htgt_pide 6484 * Enable policer ID specified using 'pid' field. 6485 * Access: RW 6486 */ 6487 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1); 6488 6489 #define MLXSW_REG_HTGT_INVALID_POLICER 0xff 6490 6491 /* reg_htgt_pid 6492 * Policer ID for the trap group. 6493 * Access: RW 6494 */ 6495 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8); 6496 6497 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0 6498 6499 /* reg_htgt_mirror_action 6500 * Mirror action to use. 6501 * 0 - Trap to CPU. 6502 * 1 - Trap to CPU and mirror to a mirroring agent. 6503 * 2 - Mirror to a mirroring agent and do not trap to CPU. 6504 * Access: RW 6505 * 6506 * Note: Mirroring to a mirroring agent is only supported in Spectrum. 6507 */ 6508 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2); 6509 6510 /* reg_htgt_mirroring_agent 6511 * Mirroring agent. 6512 * Access: RW 6513 */ 6514 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3); 6515 6516 #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0 6517 6518 /* reg_htgt_priority 6519 * Trap group priority. 6520 * In case a packet matches multiple classification rules, the packet will 6521 * only be trapped once, based on the trap ID associated with the group (via 6522 * register HPKT) with the highest priority. 6523 * Supported values are 0-7, with 7 represnting the highest priority. 6524 * Access: RW 6525 * 6526 * Note: In SwitchX-2 this field is ignored and the priority value is replaced 6527 * by the 'trap_group' field. 6528 */ 6529 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4); 6530 6531 #define MLXSW_REG_HTGT_DEFAULT_TC 7 6532 6533 /* reg_htgt_local_path_cpu_tclass 6534 * CPU ingress traffic class for the trap group. 6535 * Access: RW 6536 */ 6537 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6); 6538 6539 enum mlxsw_reg_htgt_local_path_rdq { 6540 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13, 6541 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14, 6542 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15, 6543 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15, 6544 }; 6545 /* reg_htgt_local_path_rdq 6546 * Receive descriptor queue (RDQ) to use for the trap group. 6547 * Access: RW 6548 */ 6549 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6); 6550 6551 static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id, 6552 u8 priority, u8 tc) 6553 { 6554 MLXSW_REG_ZERO(htgt, payload); 6555 6556 if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) { 6557 mlxsw_reg_htgt_pide_set(payload, 6558 MLXSW_REG_HTGT_POLICER_DISABLE); 6559 } else { 6560 mlxsw_reg_htgt_pide_set(payload, 6561 MLXSW_REG_HTGT_POLICER_ENABLE); 6562 mlxsw_reg_htgt_pid_set(payload, policer_id); 6563 } 6564 6565 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL); 6566 mlxsw_reg_htgt_trap_group_set(payload, group); 6567 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU); 6568 mlxsw_reg_htgt_mirroring_agent_set(payload, 0); 6569 mlxsw_reg_htgt_priority_set(payload, priority); 6570 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc); 6571 mlxsw_reg_htgt_local_path_rdq_set(payload, group); 6572 } 6573 6574 /* HPKT - Host Packet Trap 6575 * ----------------------- 6576 * Configures trap IDs inside trap groups. 6577 */ 6578 #define MLXSW_REG_HPKT_ID 0x7003 6579 #define MLXSW_REG_HPKT_LEN 0x10 6580 6581 MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN); 6582 6583 enum { 6584 MLXSW_REG_HPKT_ACK_NOT_REQUIRED, 6585 MLXSW_REG_HPKT_ACK_REQUIRED, 6586 }; 6587 6588 /* reg_hpkt_ack 6589 * Require acknowledgements from the host for events. 6590 * If set, then the device will wait for the event it sent to be acknowledged 6591 * by the host. This option is only relevant for event trap IDs. 6592 * Access: RW 6593 * 6594 * Note: Currently not supported by firmware. 6595 */ 6596 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1); 6597 6598 enum mlxsw_reg_hpkt_action { 6599 MLXSW_REG_HPKT_ACTION_FORWARD, 6600 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU, 6601 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU, 6602 MLXSW_REG_HPKT_ACTION_DISCARD, 6603 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD, 6604 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD, 6605 MLXSW_REG_HPKT_ACTION_TRAP_EXCEPTION_TO_CPU, 6606 MLXSW_REG_HPKT_ACTION_SET_FW_DEFAULT = 15, 6607 }; 6608 6609 /* reg_hpkt_action 6610 * Action to perform on packet when trapped. 6611 * 0 - No action. Forward to CPU based on switching rules. 6612 * 1 - Trap to CPU (CPU receives sole copy). 6613 * 2 - Mirror to CPU (CPU receives a replica of the packet). 6614 * 3 - Discard. 6615 * 4 - Soft discard (allow other traps to act on the packet). 6616 * 5 - Trap and soft discard (allow other traps to overwrite this trap). 6617 * 6 - Trap to CPU (CPU receives sole copy) and count it as error. 6618 * 15 - Restore the firmware's default action. 6619 * Access: RW 6620 * 6621 * Note: Must be set to 0 (forward) for event trap IDs, as they are already 6622 * addressed to the CPU. 6623 */ 6624 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3); 6625 6626 /* reg_hpkt_trap_group 6627 * Trap group to associate the trap with. 6628 * Access: RW 6629 */ 6630 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6); 6631 6632 /* reg_hpkt_trap_id 6633 * Trap ID. 6634 * Access: Index 6635 * 6636 * Note: A trap ID can only be associated with a single trap group. The device 6637 * will associate the trap ID with the last trap group configured. 6638 */ 6639 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 10); 6640 6641 enum { 6642 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT, 6643 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER, 6644 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER, 6645 }; 6646 6647 /* reg_hpkt_ctrl 6648 * Configure dedicated buffer resources for control packets. 6649 * Ignored by SwitchX-2. 6650 * 0 - Keep factory defaults. 6651 * 1 - Do not use control buffer for this trap ID. 6652 * 2 - Use control buffer for this trap ID. 6653 * Access: RW 6654 */ 6655 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2); 6656 6657 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id, 6658 enum mlxsw_reg_htgt_trap_group trap_group, 6659 bool is_ctrl) 6660 { 6661 MLXSW_REG_ZERO(hpkt, payload); 6662 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED); 6663 mlxsw_reg_hpkt_action_set(payload, action); 6664 mlxsw_reg_hpkt_trap_group_set(payload, trap_group); 6665 mlxsw_reg_hpkt_trap_id_set(payload, trap_id); 6666 mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ? 6667 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER : 6668 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER); 6669 } 6670 6671 /* RGCR - Router General Configuration Register 6672 * -------------------------------------------- 6673 * The register is used for setting up the router configuration. 6674 */ 6675 #define MLXSW_REG_RGCR_ID 0x8001 6676 #define MLXSW_REG_RGCR_LEN 0x28 6677 6678 MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN); 6679 6680 /* reg_rgcr_ipv4_en 6681 * IPv4 router enable. 6682 * Access: RW 6683 */ 6684 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1); 6685 6686 /* reg_rgcr_ipv6_en 6687 * IPv6 router enable. 6688 * Access: RW 6689 */ 6690 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1); 6691 6692 /* reg_rgcr_max_router_interfaces 6693 * Defines the maximum number of active router interfaces for all virtual 6694 * routers. 6695 * Access: RW 6696 */ 6697 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16); 6698 6699 /* reg_rgcr_usp 6700 * Update switch priority and packet color. 6701 * 0 - Preserve the value of Switch Priority and packet color. 6702 * 1 - Recalculate the value of Switch Priority and packet color. 6703 * Access: RW 6704 * 6705 * Note: Not supported by SwitchX and SwitchX-2. 6706 */ 6707 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1); 6708 6709 /* reg_rgcr_pcp_rw 6710 * Indicates how to handle the pcp_rewrite_en value: 6711 * 0 - Preserve the value of pcp_rewrite_en. 6712 * 2 - Disable PCP rewrite. 6713 * 3 - Enable PCP rewrite. 6714 * Access: RW 6715 * 6716 * Note: Not supported by SwitchX and SwitchX-2. 6717 */ 6718 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2); 6719 6720 /* reg_rgcr_activity_dis 6721 * Activity disable: 6722 * 0 - Activity will be set when an entry is hit (default). 6723 * 1 - Activity will not be set when an entry is hit. 6724 * 6725 * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry 6726 * (RALUE). 6727 * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host 6728 * Entry (RAUHT). 6729 * Bits 2:7 are reserved. 6730 * Access: RW 6731 * 6732 * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB. 6733 */ 6734 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8); 6735 6736 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en, 6737 bool ipv6_en) 6738 { 6739 MLXSW_REG_ZERO(rgcr, payload); 6740 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en); 6741 mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en); 6742 } 6743 6744 /* RITR - Router Interface Table Register 6745 * -------------------------------------- 6746 * The register is used to configure the router interface table. 6747 */ 6748 #define MLXSW_REG_RITR_ID 0x8002 6749 #define MLXSW_REG_RITR_LEN 0x40 6750 6751 MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN); 6752 6753 /* reg_ritr_enable 6754 * Enables routing on the router interface. 6755 * Access: RW 6756 */ 6757 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1); 6758 6759 /* reg_ritr_ipv4 6760 * IPv4 routing enable. Enables routing of IPv4 traffic on the router 6761 * interface. 6762 * Access: RW 6763 */ 6764 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1); 6765 6766 /* reg_ritr_ipv6 6767 * IPv6 routing enable. Enables routing of IPv6 traffic on the router 6768 * interface. 6769 * Access: RW 6770 */ 6771 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1); 6772 6773 /* reg_ritr_ipv4_mc 6774 * IPv4 multicast routing enable. 6775 * Access: RW 6776 */ 6777 MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1); 6778 6779 /* reg_ritr_ipv6_mc 6780 * IPv6 multicast routing enable. 6781 * Access: RW 6782 */ 6783 MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1); 6784 6785 enum mlxsw_reg_ritr_if_type { 6786 /* VLAN interface. */ 6787 MLXSW_REG_RITR_VLAN_IF, 6788 /* FID interface. */ 6789 MLXSW_REG_RITR_FID_IF, 6790 /* Sub-port interface. */ 6791 MLXSW_REG_RITR_SP_IF, 6792 /* Loopback Interface. */ 6793 MLXSW_REG_RITR_LOOPBACK_IF, 6794 }; 6795 6796 /* reg_ritr_type 6797 * Router interface type as per enum mlxsw_reg_ritr_if_type. 6798 * Access: RW 6799 */ 6800 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3); 6801 6802 enum { 6803 MLXSW_REG_RITR_RIF_CREATE, 6804 MLXSW_REG_RITR_RIF_DEL, 6805 }; 6806 6807 /* reg_ritr_op 6808 * Opcode: 6809 * 0 - Create or edit RIF. 6810 * 1 - Delete RIF. 6811 * Reserved for SwitchX-2. For Spectrum, editing of interface properties 6812 * is not supported. An interface must be deleted and re-created in order 6813 * to update properties. 6814 * Access: WO 6815 */ 6816 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2); 6817 6818 /* reg_ritr_rif 6819 * Router interface index. A pointer to the Router Interface Table. 6820 * Access: Index 6821 */ 6822 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16); 6823 6824 /* reg_ritr_ipv4_fe 6825 * IPv4 Forwarding Enable. 6826 * Enables routing of IPv4 traffic on the router interface. When disabled, 6827 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 6828 * Not supported in SwitchX-2. 6829 * Access: RW 6830 */ 6831 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1); 6832 6833 /* reg_ritr_ipv6_fe 6834 * IPv6 Forwarding Enable. 6835 * Enables routing of IPv6 traffic on the router interface. When disabled, 6836 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 6837 * Not supported in SwitchX-2. 6838 * Access: RW 6839 */ 6840 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1); 6841 6842 /* reg_ritr_ipv4_mc_fe 6843 * IPv4 Multicast Forwarding Enable. 6844 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 6845 * will be enabled. 6846 * Access: RW 6847 */ 6848 MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1); 6849 6850 /* reg_ritr_ipv6_mc_fe 6851 * IPv6 Multicast Forwarding Enable. 6852 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 6853 * will be enabled. 6854 * Access: RW 6855 */ 6856 MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1); 6857 6858 /* reg_ritr_lb_en 6859 * Loop-back filter enable for unicast packets. 6860 * If the flag is set then loop-back filter for unicast packets is 6861 * implemented on the RIF. Multicast packets are always subject to 6862 * loop-back filtering. 6863 * Access: RW 6864 */ 6865 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1); 6866 6867 /* reg_ritr_virtual_router 6868 * Virtual router ID associated with the router interface. 6869 * Access: RW 6870 */ 6871 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16); 6872 6873 /* reg_ritr_mtu 6874 * Router interface MTU. 6875 * Access: RW 6876 */ 6877 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16); 6878 6879 /* reg_ritr_if_swid 6880 * Switch partition ID. 6881 * Access: RW 6882 */ 6883 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8); 6884 6885 /* reg_ritr_if_mac_profile_id 6886 * MAC msb profile ID. 6887 * Access: RW 6888 */ 6889 MLXSW_ITEM32(reg, ritr, if_mac_profile_id, 0x10, 16, 4); 6890 6891 /* reg_ritr_if_mac 6892 * Router interface MAC address. 6893 * In Spectrum, all MAC addresses must have the same 38 MSBits. 6894 * Access: RW 6895 */ 6896 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6); 6897 6898 /* reg_ritr_if_vrrp_id_ipv6 6899 * VRRP ID for IPv6 6900 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 6901 * Access: RW 6902 */ 6903 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8); 6904 6905 /* reg_ritr_if_vrrp_id_ipv4 6906 * VRRP ID for IPv4 6907 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 6908 * Access: RW 6909 */ 6910 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8); 6911 6912 /* VLAN Interface */ 6913 6914 /* reg_ritr_vlan_if_vlan_id 6915 * VLAN ID. 6916 * Access: RW 6917 */ 6918 MLXSW_ITEM32(reg, ritr, vlan_if_vlan_id, 0x08, 0, 12); 6919 6920 /* reg_ritr_vlan_if_efid 6921 * Egress FID. 6922 * Used to connect the RIF to a bridge. 6923 * Access: RW 6924 * 6925 * Note: Reserved when legacy bridge model is used and on Spectrum-1. 6926 */ 6927 MLXSW_ITEM32(reg, ritr, vlan_if_efid, 0x0C, 0, 16); 6928 6929 /* FID Interface */ 6930 6931 /* reg_ritr_fid_if_fid 6932 * Filtering ID. Used to connect a bridge to the router. 6933 * When legacy bridge model is used, only FIDs from the vFID range are 6934 * supported. When unified bridge model is used, this is the egress FID for 6935 * router to bridge. 6936 * Access: RW 6937 */ 6938 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16); 6939 6940 /* Sub-port Interface */ 6941 6942 /* reg_ritr_sp_if_lag 6943 * LAG indication. When this bit is set the system_port field holds the 6944 * LAG identifier. 6945 * Access: RW 6946 */ 6947 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1); 6948 6949 /* reg_ritr_sp_system_port 6950 * Port unique indentifier. When lag bit is set, this field holds the 6951 * lag_id in bits 0:9. 6952 * Access: RW 6953 */ 6954 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16); 6955 6956 /* reg_ritr_sp_if_efid 6957 * Egress filtering ID. 6958 * Used to connect the eRIF to a bridge if eRIF-ACL has modified the DMAC or 6959 * the VID. 6960 * Access: RW 6961 * 6962 * Note: Reserved when legacy bridge model is used. 6963 */ 6964 MLXSW_ITEM32(reg, ritr, sp_if_efid, 0x0C, 0, 16); 6965 6966 /* reg_ritr_sp_if_vid 6967 * VLAN ID. 6968 * Access: RW 6969 */ 6970 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12); 6971 6972 /* Loopback Interface */ 6973 6974 enum mlxsw_reg_ritr_loopback_protocol { 6975 /* IPinIP IPv4 underlay Unicast */ 6976 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4, 6977 /* IPinIP IPv6 underlay Unicast */ 6978 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6, 6979 /* IPinIP generic - used for Spectrum-2 underlay RIF */ 6980 MLXSW_REG_RITR_LOOPBACK_GENERIC, 6981 }; 6982 6983 /* reg_ritr_loopback_protocol 6984 * Access: RW 6985 */ 6986 MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4); 6987 6988 enum mlxsw_reg_ritr_loopback_ipip_type { 6989 /* Tunnel is IPinIP. */ 6990 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP, 6991 /* Tunnel is GRE, no key. */ 6992 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP, 6993 /* Tunnel is GRE, with a key. */ 6994 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP, 6995 }; 6996 6997 /* reg_ritr_loopback_ipip_type 6998 * Encapsulation type. 6999 * Access: RW 7000 */ 7001 MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4); 7002 7003 enum mlxsw_reg_ritr_loopback_ipip_options { 7004 /* The key is defined by gre_key. */ 7005 MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET, 7006 }; 7007 7008 /* reg_ritr_loopback_ipip_options 7009 * Access: RW 7010 */ 7011 MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4); 7012 7013 /* reg_ritr_loopback_ipip_uvr 7014 * Underlay Virtual Router ID. 7015 * Range is 0..cap_max_virtual_routers-1. 7016 * Reserved for Spectrum-2. 7017 * Access: RW 7018 */ 7019 MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16); 7020 7021 /* reg_ritr_loopback_ipip_underlay_rif 7022 * Underlay ingress router interface. 7023 * Reserved for Spectrum. 7024 * Access: RW 7025 */ 7026 MLXSW_ITEM32(reg, ritr, loopback_ipip_underlay_rif, 0x14, 0, 16); 7027 7028 /* reg_ritr_loopback_ipip_usip* 7029 * Encapsulation Underlay source IP. 7030 * Access: RW 7031 */ 7032 MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16); 7033 MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32); 7034 7035 /* reg_ritr_loopback_ipip_gre_key 7036 * GRE Key. 7037 * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP. 7038 * Access: RW 7039 */ 7040 MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32); 7041 7042 /* Shared between ingress/egress */ 7043 enum mlxsw_reg_ritr_counter_set_type { 7044 /* No Count. */ 7045 MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0, 7046 /* Basic. Used for router interfaces, counting the following: 7047 * - Error and Discard counters. 7048 * - Unicast, Multicast and Broadcast counters. Sharing the 7049 * same set of counters for the different type of traffic 7050 * (IPv4, IPv6 and mpls). 7051 */ 7052 MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9, 7053 }; 7054 7055 /* reg_ritr_ingress_counter_index 7056 * Counter Index for flow counter. 7057 * Access: RW 7058 */ 7059 MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24); 7060 7061 /* reg_ritr_ingress_counter_set_type 7062 * Igress Counter Set Type for router interface counter. 7063 * Access: RW 7064 */ 7065 MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8); 7066 7067 /* reg_ritr_egress_counter_index 7068 * Counter Index for flow counter. 7069 * Access: RW 7070 */ 7071 MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24); 7072 7073 /* reg_ritr_egress_counter_set_type 7074 * Egress Counter Set Type for router interface counter. 7075 * Access: RW 7076 */ 7077 MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8); 7078 7079 static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index, 7080 bool enable, bool egress) 7081 { 7082 enum mlxsw_reg_ritr_counter_set_type set_type; 7083 7084 if (enable) 7085 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC; 7086 else 7087 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT; 7088 7089 if (egress) { 7090 mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type); 7091 mlxsw_reg_ritr_egress_counter_index_set(payload, index); 7092 } else { 7093 mlxsw_reg_ritr_ingress_counter_set_type_set(payload, set_type); 7094 mlxsw_reg_ritr_ingress_counter_index_set(payload, index); 7095 } 7096 } 7097 7098 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif) 7099 { 7100 MLXSW_REG_ZERO(ritr, payload); 7101 mlxsw_reg_ritr_rif_set(payload, rif); 7102 } 7103 7104 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag, 7105 u16 system_port, u16 vid) 7106 { 7107 mlxsw_reg_ritr_sp_if_lag_set(payload, lag); 7108 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port); 7109 mlxsw_reg_ritr_sp_if_vid_set(payload, vid); 7110 } 7111 7112 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable, 7113 enum mlxsw_reg_ritr_if_type type, 7114 u16 rif, u16 vr_id, u16 mtu) 7115 { 7116 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL; 7117 7118 MLXSW_REG_ZERO(ritr, payload); 7119 mlxsw_reg_ritr_enable_set(payload, enable); 7120 mlxsw_reg_ritr_ipv4_set(payload, 1); 7121 mlxsw_reg_ritr_ipv6_set(payload, 1); 7122 mlxsw_reg_ritr_ipv4_mc_set(payload, 1); 7123 mlxsw_reg_ritr_ipv6_mc_set(payload, 1); 7124 mlxsw_reg_ritr_type_set(payload, type); 7125 mlxsw_reg_ritr_op_set(payload, op); 7126 mlxsw_reg_ritr_rif_set(payload, rif); 7127 mlxsw_reg_ritr_ipv4_fe_set(payload, 1); 7128 mlxsw_reg_ritr_ipv6_fe_set(payload, 1); 7129 mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1); 7130 mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1); 7131 mlxsw_reg_ritr_lb_en_set(payload, 1); 7132 mlxsw_reg_ritr_virtual_router_set(payload, vr_id); 7133 mlxsw_reg_ritr_mtu_set(payload, mtu); 7134 } 7135 7136 static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac) 7137 { 7138 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac); 7139 } 7140 7141 static inline void 7142 mlxsw_reg_ritr_vlan_if_pack(char *payload, bool enable, u16 rif, u16 vr_id, 7143 u16 mtu, const char *mac, u8 mac_profile_id, 7144 u16 vlan_id, u16 efid) 7145 { 7146 enum mlxsw_reg_ritr_if_type type = MLXSW_REG_RITR_VLAN_IF; 7147 7148 mlxsw_reg_ritr_pack(payload, enable, type, rif, vr_id, mtu); 7149 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac); 7150 mlxsw_reg_ritr_if_mac_profile_id_set(payload, mac_profile_id); 7151 mlxsw_reg_ritr_vlan_if_vlan_id_set(payload, vlan_id); 7152 mlxsw_reg_ritr_vlan_if_efid_set(payload, efid); 7153 } 7154 7155 static inline void 7156 mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload, 7157 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 7158 enum mlxsw_reg_ritr_loopback_ipip_options options, 7159 u16 uvr_id, u16 underlay_rif, u32 gre_key) 7160 { 7161 mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type); 7162 mlxsw_reg_ritr_loopback_ipip_options_set(payload, options); 7163 mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id); 7164 mlxsw_reg_ritr_loopback_ipip_underlay_rif_set(payload, underlay_rif); 7165 mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key); 7166 } 7167 7168 static inline void 7169 mlxsw_reg_ritr_loopback_ipip4_pack(char *payload, 7170 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 7171 enum mlxsw_reg_ritr_loopback_ipip_options options, 7172 u16 uvr_id, u16 underlay_rif, u32 usip, u32 gre_key) 7173 { 7174 mlxsw_reg_ritr_loopback_protocol_set(payload, 7175 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4); 7176 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options, 7177 uvr_id, underlay_rif, gre_key); 7178 mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip); 7179 } 7180 7181 static inline void 7182 mlxsw_reg_ritr_loopback_ipip6_pack(char *payload, 7183 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 7184 enum mlxsw_reg_ritr_loopback_ipip_options options, 7185 u16 uvr_id, u16 underlay_rif, 7186 const struct in6_addr *usip, u32 gre_key) 7187 { 7188 enum mlxsw_reg_ritr_loopback_protocol protocol = 7189 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6; 7190 7191 mlxsw_reg_ritr_loopback_protocol_set(payload, protocol); 7192 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options, 7193 uvr_id, underlay_rif, gre_key); 7194 mlxsw_reg_ritr_loopback_ipip_usip6_memcpy_to(payload, 7195 (const char *)usip); 7196 } 7197 7198 /* RTAR - Router TCAM Allocation Register 7199 * -------------------------------------- 7200 * This register is used for allocation of regions in the TCAM table. 7201 */ 7202 #define MLXSW_REG_RTAR_ID 0x8004 7203 #define MLXSW_REG_RTAR_LEN 0x20 7204 7205 MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN); 7206 7207 enum mlxsw_reg_rtar_op { 7208 MLXSW_REG_RTAR_OP_ALLOCATE, 7209 MLXSW_REG_RTAR_OP_RESIZE, 7210 MLXSW_REG_RTAR_OP_DEALLOCATE, 7211 }; 7212 7213 /* reg_rtar_op 7214 * Access: WO 7215 */ 7216 MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4); 7217 7218 enum mlxsw_reg_rtar_key_type { 7219 MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1, 7220 MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3 7221 }; 7222 7223 /* reg_rtar_key_type 7224 * TCAM key type for the region. 7225 * Access: WO 7226 */ 7227 MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8); 7228 7229 /* reg_rtar_region_size 7230 * TCAM region size. When allocating/resizing this is the requested 7231 * size, the response is the actual size. 7232 * Note: Actual size may be larger than requested. 7233 * Reserved for op = Deallocate 7234 * Access: WO 7235 */ 7236 MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16); 7237 7238 static inline void mlxsw_reg_rtar_pack(char *payload, 7239 enum mlxsw_reg_rtar_op op, 7240 enum mlxsw_reg_rtar_key_type key_type, 7241 u16 region_size) 7242 { 7243 MLXSW_REG_ZERO(rtar, payload); 7244 mlxsw_reg_rtar_op_set(payload, op); 7245 mlxsw_reg_rtar_key_type_set(payload, key_type); 7246 mlxsw_reg_rtar_region_size_set(payload, region_size); 7247 } 7248 7249 /* RATR - Router Adjacency Table Register 7250 * -------------------------------------- 7251 * The RATR register is used to configure the Router Adjacency (next-hop) 7252 * Table. 7253 */ 7254 #define MLXSW_REG_RATR_ID 0x8008 7255 #define MLXSW_REG_RATR_LEN 0x2C 7256 7257 MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN); 7258 7259 enum mlxsw_reg_ratr_op { 7260 /* Read */ 7261 MLXSW_REG_RATR_OP_QUERY_READ = 0, 7262 /* Read and clear activity */ 7263 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2, 7264 /* Write Adjacency entry */ 7265 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1, 7266 /* Write Adjacency entry only if the activity is cleared. 7267 * The write may not succeed if the activity is set. There is not 7268 * direct feedback if the write has succeeded or not, however 7269 * the get will reveal the actual entry (SW can compare the get 7270 * response to the set command). 7271 */ 7272 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3, 7273 }; 7274 7275 /* reg_ratr_op 7276 * Note that Write operation may also be used for updating 7277 * counter_set_type and counter_index. In this case all other 7278 * fields must not be updated. 7279 * Access: OP 7280 */ 7281 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4); 7282 7283 /* reg_ratr_v 7284 * Valid bit. Indicates if the adjacency entry is valid. 7285 * Note: the device may need some time before reusing an invalidated 7286 * entry. During this time the entry can not be reused. It is 7287 * recommended to use another entry before reusing an invalidated 7288 * entry (e.g. software can put it at the end of the list for 7289 * reusing). Trying to access an invalidated entry not yet cleared 7290 * by the device results with failure indicating "Try Again" status. 7291 * When valid is '0' then egress_router_interface,trap_action, 7292 * adjacency_parameters and counters are reserved 7293 * Access: RW 7294 */ 7295 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1); 7296 7297 /* reg_ratr_a 7298 * Activity. Set for new entries. Set if a packet lookup has hit on 7299 * the specific entry. To clear the a bit, use "clear activity". 7300 * Access: RO 7301 */ 7302 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1); 7303 7304 enum mlxsw_reg_ratr_type { 7305 /* Ethernet */ 7306 MLXSW_REG_RATR_TYPE_ETHERNET, 7307 /* IPoIB Unicast without GRH. 7308 * Reserved for Spectrum. 7309 */ 7310 MLXSW_REG_RATR_TYPE_IPOIB_UC, 7311 /* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast 7312 * adjacency). 7313 * Reserved for Spectrum. 7314 */ 7315 MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH, 7316 /* IPoIB Multicast. 7317 * Reserved for Spectrum. 7318 */ 7319 MLXSW_REG_RATR_TYPE_IPOIB_MC, 7320 /* MPLS. 7321 * Reserved for SwitchX/-2. 7322 */ 7323 MLXSW_REG_RATR_TYPE_MPLS, 7324 /* IPinIP Encap. 7325 * Reserved for SwitchX/-2. 7326 */ 7327 MLXSW_REG_RATR_TYPE_IPIP, 7328 }; 7329 7330 /* reg_ratr_type 7331 * Adjacency entry type. 7332 * Access: RW 7333 */ 7334 MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4); 7335 7336 /* reg_ratr_adjacency_index_low 7337 * Bits 15:0 of index into the adjacency table. 7338 * For SwitchX and SwitchX-2, the adjacency table is linear and 7339 * used for adjacency entries only. 7340 * For Spectrum, the index is to the KVD linear. 7341 * Access: Index 7342 */ 7343 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16); 7344 7345 /* reg_ratr_egress_router_interface 7346 * Range is 0 .. cap_max_router_interfaces - 1 7347 * Access: RW 7348 */ 7349 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16); 7350 7351 enum mlxsw_reg_ratr_trap_action { 7352 MLXSW_REG_RATR_TRAP_ACTION_NOP, 7353 MLXSW_REG_RATR_TRAP_ACTION_TRAP, 7354 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU, 7355 MLXSW_REG_RATR_TRAP_ACTION_MIRROR, 7356 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS, 7357 }; 7358 7359 /* reg_ratr_trap_action 7360 * see mlxsw_reg_ratr_trap_action 7361 * Access: RW 7362 */ 7363 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4); 7364 7365 /* reg_ratr_adjacency_index_high 7366 * Bits 23:16 of the adjacency_index. 7367 * Access: Index 7368 */ 7369 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8); 7370 7371 enum mlxsw_reg_ratr_trap_id { 7372 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0, 7373 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1, 7374 }; 7375 7376 /* reg_ratr_trap_id 7377 * Trap ID to be reported to CPU. 7378 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 7379 * For trap_action of NOP, MIRROR and DISCARD_ERROR 7380 * Access: RW 7381 */ 7382 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8); 7383 7384 /* reg_ratr_eth_destination_mac 7385 * MAC address of the destination next-hop. 7386 * Access: RW 7387 */ 7388 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6); 7389 7390 enum mlxsw_reg_ratr_ipip_type { 7391 /* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */ 7392 MLXSW_REG_RATR_IPIP_TYPE_IPV4, 7393 /* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */ 7394 MLXSW_REG_RATR_IPIP_TYPE_IPV6, 7395 }; 7396 7397 /* reg_ratr_ipip_type 7398 * Underlay destination ip type. 7399 * Note: the type field must match the protocol of the router interface. 7400 * Access: RW 7401 */ 7402 MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4); 7403 7404 /* reg_ratr_ipip_ipv4_udip 7405 * Underlay ipv4 dip. 7406 * Reserved when ipip_type is IPv6. 7407 * Access: RW 7408 */ 7409 MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32); 7410 7411 /* reg_ratr_ipip_ipv6_ptr 7412 * Pointer to IPv6 underlay destination ip address. 7413 * For Spectrum: Pointer to KVD linear space. 7414 * Access: RW 7415 */ 7416 MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24); 7417 7418 enum mlxsw_reg_flow_counter_set_type { 7419 /* No count */ 7420 MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00, 7421 /* Count packets and bytes */ 7422 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03, 7423 /* Count only packets */ 7424 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05, 7425 }; 7426 7427 /* reg_ratr_counter_set_type 7428 * Counter set type for flow counters 7429 * Access: RW 7430 */ 7431 MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8); 7432 7433 /* reg_ratr_counter_index 7434 * Counter index for flow counters 7435 * Access: RW 7436 */ 7437 MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24); 7438 7439 static inline void 7440 mlxsw_reg_ratr_pack(char *payload, 7441 enum mlxsw_reg_ratr_op op, bool valid, 7442 enum mlxsw_reg_ratr_type type, 7443 u32 adjacency_index, u16 egress_rif) 7444 { 7445 MLXSW_REG_ZERO(ratr, payload); 7446 mlxsw_reg_ratr_op_set(payload, op); 7447 mlxsw_reg_ratr_v_set(payload, valid); 7448 mlxsw_reg_ratr_type_set(payload, type); 7449 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index); 7450 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16); 7451 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif); 7452 } 7453 7454 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload, 7455 const char *dest_mac) 7456 { 7457 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac); 7458 } 7459 7460 static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip) 7461 { 7462 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4); 7463 mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip); 7464 } 7465 7466 static inline void mlxsw_reg_ratr_ipip6_entry_pack(char *payload, u32 ipv6_ptr) 7467 { 7468 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV6); 7469 mlxsw_reg_ratr_ipip_ipv6_ptr_set(payload, ipv6_ptr); 7470 } 7471 7472 static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index, 7473 bool counter_enable) 7474 { 7475 enum mlxsw_reg_flow_counter_set_type set_type; 7476 7477 if (counter_enable) 7478 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES; 7479 else 7480 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT; 7481 7482 mlxsw_reg_ratr_counter_index_set(payload, counter_index); 7483 mlxsw_reg_ratr_counter_set_type_set(payload, set_type); 7484 } 7485 7486 /* RDPM - Router DSCP to Priority Mapping 7487 * -------------------------------------- 7488 * Controls the mapping from DSCP field to switch priority on routed packets 7489 */ 7490 #define MLXSW_REG_RDPM_ID 0x8009 7491 #define MLXSW_REG_RDPM_BASE_LEN 0x00 7492 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01 7493 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64 7494 #define MLXSW_REG_RDPM_LEN 0x40 7495 #define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \ 7496 MLXSW_REG_RDPM_LEN - \ 7497 MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN) 7498 7499 MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN); 7500 7501 /* reg_dscp_entry_e 7502 * Enable update of the specific entry 7503 * Access: Index 7504 */ 7505 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1, 7506 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 7507 7508 /* reg_dscp_entry_prio 7509 * Switch Priority 7510 * Access: RW 7511 */ 7512 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4, 7513 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 7514 7515 static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index, 7516 u8 prio) 7517 { 7518 mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1); 7519 mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio); 7520 } 7521 7522 /* RICNT - Router Interface Counter Register 7523 * ----------------------------------------- 7524 * The RICNT register retrieves per port performance counters 7525 */ 7526 #define MLXSW_REG_RICNT_ID 0x800B 7527 #define MLXSW_REG_RICNT_LEN 0x100 7528 7529 MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN); 7530 7531 /* reg_ricnt_counter_index 7532 * Counter index 7533 * Access: RW 7534 */ 7535 MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24); 7536 7537 enum mlxsw_reg_ricnt_counter_set_type { 7538 /* No Count. */ 7539 MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00, 7540 /* Basic. Used for router interfaces, counting the following: 7541 * - Error and Discard counters. 7542 * - Unicast, Multicast and Broadcast counters. Sharing the 7543 * same set of counters for the different type of traffic 7544 * (IPv4, IPv6 and mpls). 7545 */ 7546 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09, 7547 }; 7548 7549 /* reg_ricnt_counter_set_type 7550 * Counter Set Type for router interface counter 7551 * Access: RW 7552 */ 7553 MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8); 7554 7555 enum mlxsw_reg_ricnt_opcode { 7556 /* Nop. Supported only for read access*/ 7557 MLXSW_REG_RICNT_OPCODE_NOP = 0x00, 7558 /* Clear. Setting the clr bit will reset the counter value for 7559 * all counters of the specified Router Interface. 7560 */ 7561 MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08, 7562 }; 7563 7564 /* reg_ricnt_opcode 7565 * Opcode 7566 * Access: RW 7567 */ 7568 MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4); 7569 7570 /* reg_ricnt_good_unicast_packets 7571 * good unicast packets. 7572 * Access: RW 7573 */ 7574 MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64); 7575 7576 /* reg_ricnt_good_multicast_packets 7577 * good multicast packets. 7578 * Access: RW 7579 */ 7580 MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64); 7581 7582 /* reg_ricnt_good_broadcast_packets 7583 * good broadcast packets 7584 * Access: RW 7585 */ 7586 MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64); 7587 7588 /* reg_ricnt_good_unicast_bytes 7589 * A count of L3 data and padding octets not including L2 headers 7590 * for good unicast frames. 7591 * Access: RW 7592 */ 7593 MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64); 7594 7595 /* reg_ricnt_good_multicast_bytes 7596 * A count of L3 data and padding octets not including L2 headers 7597 * for good multicast frames. 7598 * Access: RW 7599 */ 7600 MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64); 7601 7602 /* reg_ritr_good_broadcast_bytes 7603 * A count of L3 data and padding octets not including L2 headers 7604 * for good broadcast frames. 7605 * Access: RW 7606 */ 7607 MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64); 7608 7609 /* reg_ricnt_error_packets 7610 * A count of errored frames that do not pass the router checks. 7611 * Access: RW 7612 */ 7613 MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64); 7614 7615 /* reg_ricnt_discrad_packets 7616 * A count of non-errored frames that do not pass the router checks. 7617 * Access: RW 7618 */ 7619 MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64); 7620 7621 /* reg_ricnt_error_bytes 7622 * A count of L3 data and padding octets not including L2 headers 7623 * for errored frames. 7624 * Access: RW 7625 */ 7626 MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64); 7627 7628 /* reg_ricnt_discard_bytes 7629 * A count of L3 data and padding octets not including L2 headers 7630 * for non-errored frames that do not pass the router checks. 7631 * Access: RW 7632 */ 7633 MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64); 7634 7635 static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index, 7636 enum mlxsw_reg_ricnt_opcode op) 7637 { 7638 MLXSW_REG_ZERO(ricnt, payload); 7639 mlxsw_reg_ricnt_op_set(payload, op); 7640 mlxsw_reg_ricnt_counter_index_set(payload, index); 7641 mlxsw_reg_ricnt_counter_set_type_set(payload, 7642 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC); 7643 } 7644 7645 /* RRCR - Router Rules Copy Register Layout 7646 * ---------------------------------------- 7647 * This register is used for moving and copying route entry rules. 7648 */ 7649 #define MLXSW_REG_RRCR_ID 0x800F 7650 #define MLXSW_REG_RRCR_LEN 0x24 7651 7652 MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN); 7653 7654 enum mlxsw_reg_rrcr_op { 7655 /* Move rules */ 7656 MLXSW_REG_RRCR_OP_MOVE, 7657 /* Copy rules */ 7658 MLXSW_REG_RRCR_OP_COPY, 7659 }; 7660 7661 /* reg_rrcr_op 7662 * Access: WO 7663 */ 7664 MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4); 7665 7666 /* reg_rrcr_offset 7667 * Offset within the region from which to copy/move. 7668 * Access: Index 7669 */ 7670 MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16); 7671 7672 /* reg_rrcr_size 7673 * The number of rules to copy/move. 7674 * Access: WO 7675 */ 7676 MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16); 7677 7678 /* reg_rrcr_table_id 7679 * Identifier of the table on which to perform the operation. Encoding is the 7680 * same as in RTAR.key_type 7681 * Access: Index 7682 */ 7683 MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4); 7684 7685 /* reg_rrcr_dest_offset 7686 * Offset within the region to which to copy/move 7687 * Access: Index 7688 */ 7689 MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16); 7690 7691 static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op, 7692 u16 offset, u16 size, 7693 enum mlxsw_reg_rtar_key_type table_id, 7694 u16 dest_offset) 7695 { 7696 MLXSW_REG_ZERO(rrcr, payload); 7697 mlxsw_reg_rrcr_op_set(payload, op); 7698 mlxsw_reg_rrcr_offset_set(payload, offset); 7699 mlxsw_reg_rrcr_size_set(payload, size); 7700 mlxsw_reg_rrcr_table_id_set(payload, table_id); 7701 mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset); 7702 } 7703 7704 /* RALTA - Router Algorithmic LPM Tree Allocation Register 7705 * ------------------------------------------------------- 7706 * RALTA is used to allocate the LPM trees of the SHSPM method. 7707 */ 7708 #define MLXSW_REG_RALTA_ID 0x8010 7709 #define MLXSW_REG_RALTA_LEN 0x04 7710 7711 MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN); 7712 7713 /* reg_ralta_op 7714 * opcode (valid for Write, must be 0 on Read) 7715 * 0 - allocate a tree 7716 * 1 - deallocate a tree 7717 * Access: OP 7718 */ 7719 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2); 7720 7721 enum mlxsw_reg_ralxx_protocol { 7722 MLXSW_REG_RALXX_PROTOCOL_IPV4, 7723 MLXSW_REG_RALXX_PROTOCOL_IPV6, 7724 }; 7725 7726 /* reg_ralta_protocol 7727 * Protocol. 7728 * Deallocation opcode: Reserved. 7729 * Access: RW 7730 */ 7731 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4); 7732 7733 /* reg_ralta_tree_id 7734 * An identifier (numbered from 1..cap_shspm_max_trees-1) representing 7735 * the tree identifier (managed by software). 7736 * Note that tree_id 0 is allocated for a default-route tree. 7737 * Access: Index 7738 */ 7739 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8); 7740 7741 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc, 7742 enum mlxsw_reg_ralxx_protocol protocol, 7743 u8 tree_id) 7744 { 7745 MLXSW_REG_ZERO(ralta, payload); 7746 mlxsw_reg_ralta_op_set(payload, !alloc); 7747 mlxsw_reg_ralta_protocol_set(payload, protocol); 7748 mlxsw_reg_ralta_tree_id_set(payload, tree_id); 7749 } 7750 7751 /* RALST - Router Algorithmic LPM Structure Tree Register 7752 * ------------------------------------------------------ 7753 * RALST is used to set and query the structure of an LPM tree. 7754 * The structure of the tree must be sorted as a sorted binary tree, while 7755 * each node is a bin that is tagged as the length of the prefixes the lookup 7756 * will refer to. Therefore, bin X refers to a set of entries with prefixes 7757 * of X bits to match with the destination address. The bin 0 indicates 7758 * the default action, when there is no match of any prefix. 7759 */ 7760 #define MLXSW_REG_RALST_ID 0x8011 7761 #define MLXSW_REG_RALST_LEN 0x104 7762 7763 MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN); 7764 7765 /* reg_ralst_root_bin 7766 * The bin number of the root bin. 7767 * 0<root_bin=<(length of IP address) 7768 * For a default-route tree configure 0xff 7769 * Access: RW 7770 */ 7771 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8); 7772 7773 /* reg_ralst_tree_id 7774 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 7775 * Access: Index 7776 */ 7777 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8); 7778 7779 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff 7780 #define MLXSW_REG_RALST_BIN_OFFSET 0x04 7781 #define MLXSW_REG_RALST_BIN_COUNT 128 7782 7783 /* reg_ralst_left_child_bin 7784 * Holding the children of the bin according to the stored tree's structure. 7785 * For trees composed of less than 4 blocks, the bins in excess are reserved. 7786 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 7787 * Access: RW 7788 */ 7789 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false); 7790 7791 /* reg_ralst_right_child_bin 7792 * Holding the children of the bin according to the stored tree's structure. 7793 * For trees composed of less than 4 blocks, the bins in excess are reserved. 7794 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 7795 * Access: RW 7796 */ 7797 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00, 7798 false); 7799 7800 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id) 7801 { 7802 MLXSW_REG_ZERO(ralst, payload); 7803 7804 /* Initialize all bins to have no left or right child */ 7805 memset(payload + MLXSW_REG_RALST_BIN_OFFSET, 7806 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2); 7807 7808 mlxsw_reg_ralst_root_bin_set(payload, root_bin); 7809 mlxsw_reg_ralst_tree_id_set(payload, tree_id); 7810 } 7811 7812 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number, 7813 u8 left_child_bin, 7814 u8 right_child_bin) 7815 { 7816 int bin_index = bin_number - 1; 7817 7818 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin); 7819 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index, 7820 right_child_bin); 7821 } 7822 7823 /* RALTB - Router Algorithmic LPM Tree Binding Register 7824 * ---------------------------------------------------- 7825 * RALTB is used to bind virtual router and protocol to an allocated LPM tree. 7826 */ 7827 #define MLXSW_REG_RALTB_ID 0x8012 7828 #define MLXSW_REG_RALTB_LEN 0x04 7829 7830 MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN); 7831 7832 /* reg_raltb_virtual_router 7833 * Virtual Router ID 7834 * Range is 0..cap_max_virtual_routers-1 7835 * Access: Index 7836 */ 7837 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16); 7838 7839 /* reg_raltb_protocol 7840 * Protocol. 7841 * Access: Index 7842 */ 7843 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4); 7844 7845 /* reg_raltb_tree_id 7846 * Tree to be used for the {virtual_router, protocol} 7847 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 7848 * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0. 7849 * Access: RW 7850 */ 7851 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8); 7852 7853 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router, 7854 enum mlxsw_reg_ralxx_protocol protocol, 7855 u8 tree_id) 7856 { 7857 MLXSW_REG_ZERO(raltb, payload); 7858 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router); 7859 mlxsw_reg_raltb_protocol_set(payload, protocol); 7860 mlxsw_reg_raltb_tree_id_set(payload, tree_id); 7861 } 7862 7863 /* RALUE - Router Algorithmic LPM Unicast Entry Register 7864 * ----------------------------------------------------- 7865 * RALUE is used to configure and query LPM entries that serve 7866 * the Unicast protocols. 7867 */ 7868 #define MLXSW_REG_RALUE_ID 0x8013 7869 #define MLXSW_REG_RALUE_LEN 0x38 7870 7871 MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN); 7872 7873 /* reg_ralue_protocol 7874 * Protocol. 7875 * Access: Index 7876 */ 7877 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4); 7878 7879 enum mlxsw_reg_ralue_op { 7880 /* Read operation. If entry doesn't exist, the operation fails. */ 7881 MLXSW_REG_RALUE_OP_QUERY_READ = 0, 7882 /* Clear on read operation. Used to read entry and 7883 * clear Activity bit. 7884 */ 7885 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1, 7886 /* Write operation. Used to write a new entry to the table. All RW 7887 * fields are written for new entry. Activity bit is set 7888 * for new entries. 7889 */ 7890 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0, 7891 /* Update operation. Used to update an existing route entry and 7892 * only update the RW fields that are detailed in the field 7893 * op_u_mask. If entry doesn't exist, the operation fails. 7894 */ 7895 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1, 7896 /* Clear activity. The Activity bit (the field a) is cleared 7897 * for the entry. 7898 */ 7899 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2, 7900 /* Delete operation. Used to delete an existing entry. If entry 7901 * doesn't exist, the operation fails. 7902 */ 7903 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3, 7904 }; 7905 7906 /* reg_ralue_op 7907 * Operation. 7908 * Access: OP 7909 */ 7910 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3); 7911 7912 /* reg_ralue_a 7913 * Activity. Set for new entries. Set if a packet lookup has hit on the 7914 * specific entry, only if the entry is a route. To clear the a bit, use 7915 * "clear activity" op. 7916 * Enabled by activity_dis in RGCR 7917 * Access: RO 7918 */ 7919 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1); 7920 7921 /* reg_ralue_virtual_router 7922 * Virtual Router ID 7923 * Range is 0..cap_max_virtual_routers-1 7924 * Access: Index 7925 */ 7926 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16); 7927 7928 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0) 7929 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1) 7930 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2) 7931 7932 /* reg_ralue_op_u_mask 7933 * opcode update mask. 7934 * On read operation, this field is reserved. 7935 * This field is valid for update opcode, otherwise - reserved. 7936 * This field is a bitmask of the fields that should be updated. 7937 * Access: WO 7938 */ 7939 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3); 7940 7941 /* reg_ralue_prefix_len 7942 * Number of bits in the prefix of the LPM route. 7943 * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes 7944 * two entries in the physical HW table. 7945 * Access: Index 7946 */ 7947 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8); 7948 7949 /* reg_ralue_dip* 7950 * The prefix of the route or of the marker that the object of the LPM 7951 * is compared with. The most significant bits of the dip are the prefix. 7952 * The least significant bits must be '0' if the prefix_len is smaller 7953 * than 128 for IPv6 or smaller than 32 for IPv4. 7954 * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved. 7955 * Access: Index 7956 */ 7957 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32); 7958 MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16); 7959 7960 enum mlxsw_reg_ralue_entry_type { 7961 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1, 7962 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2, 7963 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3, 7964 }; 7965 7966 /* reg_ralue_entry_type 7967 * Entry type. 7968 * Note - for Marker entries, the action_type and action fields are reserved. 7969 * Access: RW 7970 */ 7971 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2); 7972 7973 /* reg_ralue_bmp_len 7974 * The best match prefix length in the case that there is no match for 7975 * longer prefixes. 7976 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len 7977 * Note for any update operation with entry_type modification this 7978 * field must be set. 7979 * Access: RW 7980 */ 7981 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8); 7982 7983 enum mlxsw_reg_ralue_action_type { 7984 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE, 7985 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL, 7986 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME, 7987 }; 7988 7989 /* reg_ralue_action_type 7990 * Action Type 7991 * Indicates how the IP address is connected. 7992 * It can be connected to a local subnet through local_erif or can be 7993 * on a remote subnet connected through a next-hop router, 7994 * or transmitted to the CPU. 7995 * Reserved when entry_type = MARKER_ENTRY 7996 * Access: RW 7997 */ 7998 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2); 7999 8000 enum mlxsw_reg_ralue_trap_action { 8001 MLXSW_REG_RALUE_TRAP_ACTION_NOP, 8002 MLXSW_REG_RALUE_TRAP_ACTION_TRAP, 8003 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU, 8004 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR, 8005 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR, 8006 }; 8007 8008 /* reg_ralue_trap_action 8009 * Trap action. 8010 * For IP2ME action, only NOP and MIRROR are possible. 8011 * Access: RW 8012 */ 8013 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4); 8014 8015 /* reg_ralue_trap_id 8016 * Trap ID to be reported to CPU. 8017 * Trap ID is RTR_INGRESS0 or RTR_INGRESS1. 8018 * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved. 8019 * Access: RW 8020 */ 8021 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9); 8022 8023 /* reg_ralue_adjacency_index 8024 * Points to the first entry of the group-based ECMP. 8025 * Only relevant in case of REMOTE action. 8026 * Access: RW 8027 */ 8028 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24); 8029 8030 /* reg_ralue_ecmp_size 8031 * Amount of sequential entries starting 8032 * from the adjacency_index (the number of ECMPs). 8033 * The valid range is 1-64, 512, 1024, 2048 and 4096. 8034 * Reserved when trap_action is TRAP or DISCARD_ERROR. 8035 * Only relevant in case of REMOTE action. 8036 * Access: RW 8037 */ 8038 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13); 8039 8040 /* reg_ralue_local_erif 8041 * Egress Router Interface. 8042 * Only relevant in case of LOCAL action. 8043 * Access: RW 8044 */ 8045 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16); 8046 8047 /* reg_ralue_ip2me_v 8048 * Valid bit for the tunnel_ptr field. 8049 * If valid = 0 then trap to CPU as IP2ME trap ID. 8050 * If valid = 1 and the packet format allows NVE or IPinIP tunnel 8051 * decapsulation then tunnel decapsulation is done. 8052 * If valid = 1 and packet format does not allow NVE or IPinIP tunnel 8053 * decapsulation then trap as IP2ME trap ID. 8054 * Only relevant in case of IP2ME action. 8055 * Access: RW 8056 */ 8057 MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1); 8058 8059 /* reg_ralue_ip2me_tunnel_ptr 8060 * Tunnel Pointer for NVE or IPinIP tunnel decapsulation. 8061 * For Spectrum, pointer to KVD Linear. 8062 * Only relevant in case of IP2ME action. 8063 * Access: RW 8064 */ 8065 MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24); 8066 8067 static inline void mlxsw_reg_ralue_pack(char *payload, 8068 enum mlxsw_reg_ralxx_protocol protocol, 8069 enum mlxsw_reg_ralue_op op, 8070 u16 virtual_router, u8 prefix_len) 8071 { 8072 MLXSW_REG_ZERO(ralue, payload); 8073 mlxsw_reg_ralue_protocol_set(payload, protocol); 8074 mlxsw_reg_ralue_op_set(payload, op); 8075 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router); 8076 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len); 8077 mlxsw_reg_ralue_entry_type_set(payload, 8078 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY); 8079 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len); 8080 } 8081 8082 static inline void mlxsw_reg_ralue_pack4(char *payload, 8083 enum mlxsw_reg_ralxx_protocol protocol, 8084 enum mlxsw_reg_ralue_op op, 8085 u16 virtual_router, u8 prefix_len, 8086 u32 dip) 8087 { 8088 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 8089 mlxsw_reg_ralue_dip4_set(payload, dip); 8090 } 8091 8092 static inline void mlxsw_reg_ralue_pack6(char *payload, 8093 enum mlxsw_reg_ralxx_protocol protocol, 8094 enum mlxsw_reg_ralue_op op, 8095 u16 virtual_router, u8 prefix_len, 8096 const void *dip) 8097 { 8098 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 8099 mlxsw_reg_ralue_dip6_memcpy_to(payload, dip); 8100 } 8101 8102 static inline void 8103 mlxsw_reg_ralue_act_remote_pack(char *payload, 8104 enum mlxsw_reg_ralue_trap_action trap_action, 8105 u16 trap_id, u32 adjacency_index, u16 ecmp_size) 8106 { 8107 mlxsw_reg_ralue_action_type_set(payload, 8108 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE); 8109 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 8110 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 8111 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index); 8112 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size); 8113 } 8114 8115 static inline void 8116 mlxsw_reg_ralue_act_local_pack(char *payload, 8117 enum mlxsw_reg_ralue_trap_action trap_action, 8118 u16 trap_id, u16 local_erif) 8119 { 8120 mlxsw_reg_ralue_action_type_set(payload, 8121 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL); 8122 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 8123 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 8124 mlxsw_reg_ralue_local_erif_set(payload, local_erif); 8125 } 8126 8127 static inline void 8128 mlxsw_reg_ralue_act_ip2me_pack(char *payload) 8129 { 8130 mlxsw_reg_ralue_action_type_set(payload, 8131 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 8132 } 8133 8134 static inline void 8135 mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr) 8136 { 8137 mlxsw_reg_ralue_action_type_set(payload, 8138 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 8139 mlxsw_reg_ralue_ip2me_v_set(payload, 1); 8140 mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr); 8141 } 8142 8143 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register 8144 * ---------------------------------------------------------- 8145 * The RAUHT register is used to configure and query the Unicast Host table in 8146 * devices that implement the Algorithmic LPM. 8147 */ 8148 #define MLXSW_REG_RAUHT_ID 0x8014 8149 #define MLXSW_REG_RAUHT_LEN 0x74 8150 8151 MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN); 8152 8153 enum mlxsw_reg_rauht_type { 8154 MLXSW_REG_RAUHT_TYPE_IPV4, 8155 MLXSW_REG_RAUHT_TYPE_IPV6, 8156 }; 8157 8158 /* reg_rauht_type 8159 * Access: Index 8160 */ 8161 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2); 8162 8163 enum mlxsw_reg_rauht_op { 8164 MLXSW_REG_RAUHT_OP_QUERY_READ = 0, 8165 /* Read operation */ 8166 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1, 8167 /* Clear on read operation. Used to read entry and clear 8168 * activity bit. 8169 */ 8170 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0, 8171 /* Add. Used to write a new entry to the table. All R/W fields are 8172 * relevant for new entry. Activity bit is set for new entries. 8173 */ 8174 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1, 8175 /* Update action. Used to update an existing route entry and 8176 * only update the following fields: 8177 * trap_action, trap_id, mac, counter_set_type, counter_index 8178 */ 8179 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2, 8180 /* Clear activity. A bit is cleared for the entry. */ 8181 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3, 8182 /* Delete entry */ 8183 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4, 8184 /* Delete all host entries on a RIF. In this command, dip 8185 * field is reserved. 8186 */ 8187 }; 8188 8189 /* reg_rauht_op 8190 * Access: OP 8191 */ 8192 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3); 8193 8194 /* reg_rauht_a 8195 * Activity. Set for new entries. Set if a packet lookup has hit on 8196 * the specific entry. 8197 * To clear the a bit, use "clear activity" op. 8198 * Enabled by activity_dis in RGCR 8199 * Access: RO 8200 */ 8201 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1); 8202 8203 /* reg_rauht_rif 8204 * Router Interface 8205 * Access: Index 8206 */ 8207 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16); 8208 8209 /* reg_rauht_dip* 8210 * Destination address. 8211 * Access: Index 8212 */ 8213 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32); 8214 MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16); 8215 8216 enum mlxsw_reg_rauht_trap_action { 8217 MLXSW_REG_RAUHT_TRAP_ACTION_NOP, 8218 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP, 8219 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU, 8220 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR, 8221 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS, 8222 }; 8223 8224 /* reg_rauht_trap_action 8225 * Access: RW 8226 */ 8227 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4); 8228 8229 enum mlxsw_reg_rauht_trap_id { 8230 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0, 8231 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1, 8232 }; 8233 8234 /* reg_rauht_trap_id 8235 * Trap ID to be reported to CPU. 8236 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 8237 * For trap_action of NOP, MIRROR and DISCARD_ERROR, 8238 * trap_id is reserved. 8239 * Access: RW 8240 */ 8241 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9); 8242 8243 /* reg_rauht_counter_set_type 8244 * Counter set type for flow counters 8245 * Access: RW 8246 */ 8247 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8); 8248 8249 /* reg_rauht_counter_index 8250 * Counter index for flow counters 8251 * Access: RW 8252 */ 8253 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24); 8254 8255 /* reg_rauht_mac 8256 * MAC address. 8257 * Access: RW 8258 */ 8259 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6); 8260 8261 static inline void mlxsw_reg_rauht_pack(char *payload, 8262 enum mlxsw_reg_rauht_op op, u16 rif, 8263 const char *mac) 8264 { 8265 MLXSW_REG_ZERO(rauht, payload); 8266 mlxsw_reg_rauht_op_set(payload, op); 8267 mlxsw_reg_rauht_rif_set(payload, rif); 8268 mlxsw_reg_rauht_mac_memcpy_to(payload, mac); 8269 } 8270 8271 static inline void mlxsw_reg_rauht_pack4(char *payload, 8272 enum mlxsw_reg_rauht_op op, u16 rif, 8273 const char *mac, u32 dip) 8274 { 8275 mlxsw_reg_rauht_pack(payload, op, rif, mac); 8276 mlxsw_reg_rauht_dip4_set(payload, dip); 8277 } 8278 8279 static inline void mlxsw_reg_rauht_pack6(char *payload, 8280 enum mlxsw_reg_rauht_op op, u16 rif, 8281 const char *mac, const char *dip) 8282 { 8283 mlxsw_reg_rauht_pack(payload, op, rif, mac); 8284 mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6); 8285 mlxsw_reg_rauht_dip6_memcpy_to(payload, dip); 8286 } 8287 8288 static inline void mlxsw_reg_rauht_pack_counter(char *payload, 8289 u64 counter_index) 8290 { 8291 mlxsw_reg_rauht_counter_index_set(payload, counter_index); 8292 mlxsw_reg_rauht_counter_set_type_set(payload, 8293 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 8294 } 8295 8296 /* RALEU - Router Algorithmic LPM ECMP Update Register 8297 * --------------------------------------------------- 8298 * The register enables updating the ECMP section in the action for multiple 8299 * LPM Unicast entries in a single operation. The update is executed to 8300 * all entries of a {virtual router, protocol} tuple using the same ECMP group. 8301 */ 8302 #define MLXSW_REG_RALEU_ID 0x8015 8303 #define MLXSW_REG_RALEU_LEN 0x28 8304 8305 MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN); 8306 8307 /* reg_raleu_protocol 8308 * Protocol. 8309 * Access: Index 8310 */ 8311 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4); 8312 8313 /* reg_raleu_virtual_router 8314 * Virtual Router ID 8315 * Range is 0..cap_max_virtual_routers-1 8316 * Access: Index 8317 */ 8318 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16); 8319 8320 /* reg_raleu_adjacency_index 8321 * Adjacency Index used for matching on the existing entries. 8322 * Access: Index 8323 */ 8324 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24); 8325 8326 /* reg_raleu_ecmp_size 8327 * ECMP Size used for matching on the existing entries. 8328 * Access: Index 8329 */ 8330 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13); 8331 8332 /* reg_raleu_new_adjacency_index 8333 * New Adjacency Index. 8334 * Access: WO 8335 */ 8336 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24); 8337 8338 /* reg_raleu_new_ecmp_size 8339 * New ECMP Size. 8340 * Access: WO 8341 */ 8342 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13); 8343 8344 static inline void mlxsw_reg_raleu_pack(char *payload, 8345 enum mlxsw_reg_ralxx_protocol protocol, 8346 u16 virtual_router, 8347 u32 adjacency_index, u16 ecmp_size, 8348 u32 new_adjacency_index, 8349 u16 new_ecmp_size) 8350 { 8351 MLXSW_REG_ZERO(raleu, payload); 8352 mlxsw_reg_raleu_protocol_set(payload, protocol); 8353 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router); 8354 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index); 8355 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size); 8356 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index); 8357 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size); 8358 } 8359 8360 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register 8361 * ---------------------------------------------------------------- 8362 * The RAUHTD register allows dumping entries from the Router Unicast Host 8363 * Table. For a given session an entry is dumped no more than one time. The 8364 * first RAUHTD access after reset is a new session. A session ends when the 8365 * num_rec response is smaller than num_rec request or for IPv4 when the 8366 * num_entries is smaller than 4. The clear activity affect the current session 8367 * or the last session if a new session has not started. 8368 */ 8369 #define MLXSW_REG_RAUHTD_ID 0x8018 8370 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20 8371 #define MLXSW_REG_RAUHTD_REC_LEN 0x20 8372 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32 8373 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \ 8374 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN) 8375 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4 8376 8377 MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN); 8378 8379 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0) 8380 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3) 8381 8382 /* reg_rauhtd_filter_fields 8383 * if a bit is '0' then the relevant field is ignored and dump is done 8384 * regardless of the field value 8385 * Bit0 - filter by activity: entry_a 8386 * Bit3 - filter by entry rip: entry_rif 8387 * Access: Index 8388 */ 8389 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8); 8390 8391 enum mlxsw_reg_rauhtd_op { 8392 MLXSW_REG_RAUHTD_OP_DUMP, 8393 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR, 8394 }; 8395 8396 /* reg_rauhtd_op 8397 * Access: OP 8398 */ 8399 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2); 8400 8401 /* reg_rauhtd_num_rec 8402 * At request: number of records requested 8403 * At response: number of records dumped 8404 * For IPv4, each record has 4 entries at request and up to 4 entries 8405 * at response 8406 * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM 8407 * Access: Index 8408 */ 8409 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8); 8410 8411 /* reg_rauhtd_entry_a 8412 * Dump only if activity has value of entry_a 8413 * Reserved if filter_fields bit0 is '0' 8414 * Access: Index 8415 */ 8416 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1); 8417 8418 enum mlxsw_reg_rauhtd_type { 8419 MLXSW_REG_RAUHTD_TYPE_IPV4, 8420 MLXSW_REG_RAUHTD_TYPE_IPV6, 8421 }; 8422 8423 /* reg_rauhtd_type 8424 * Dump only if record type is: 8425 * 0 - IPv4 8426 * 1 - IPv6 8427 * Access: Index 8428 */ 8429 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4); 8430 8431 /* reg_rauhtd_entry_rif 8432 * Dump only if RIF has value of entry_rif 8433 * Reserved if filter_fields bit3 is '0' 8434 * Access: Index 8435 */ 8436 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16); 8437 8438 static inline void mlxsw_reg_rauhtd_pack(char *payload, 8439 enum mlxsw_reg_rauhtd_type type) 8440 { 8441 MLXSW_REG_ZERO(rauhtd, payload); 8442 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A); 8443 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR); 8444 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM); 8445 mlxsw_reg_rauhtd_entry_a_set(payload, 1); 8446 mlxsw_reg_rauhtd_type_set(payload, type); 8447 } 8448 8449 /* reg_rauhtd_ipv4_rec_num_entries 8450 * Number of valid entries in this record: 8451 * 0 - 1 valid entry 8452 * 1 - 2 valid entries 8453 * 2 - 3 valid entries 8454 * 3 - 4 valid entries 8455 * Access: RO 8456 */ 8457 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries, 8458 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2, 8459 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 8460 8461 /* reg_rauhtd_rec_type 8462 * Record type. 8463 * 0 - IPv4 8464 * 1 - IPv6 8465 * Access: RO 8466 */ 8467 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2, 8468 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 8469 8470 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8 8471 8472 /* reg_rauhtd_ipv4_ent_a 8473 * Activity. Set for new entries. Set if a packet lookup has hit on the 8474 * specific entry. 8475 * Access: RO 8476 */ 8477 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 8478 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 8479 8480 /* reg_rauhtd_ipv4_ent_rif 8481 * Router interface. 8482 * Access: RO 8483 */ 8484 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 8485 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 8486 8487 /* reg_rauhtd_ipv4_ent_dip 8488 * Destination IPv4 address. 8489 * Access: RO 8490 */ 8491 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0, 8492 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false); 8493 8494 #define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20 8495 8496 /* reg_rauhtd_ipv6_ent_a 8497 * Activity. Set for new entries. Set if a packet lookup has hit on the 8498 * specific entry. 8499 * Access: RO 8500 */ 8501 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 8502 MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 8503 8504 /* reg_rauhtd_ipv6_ent_rif 8505 * Router interface. 8506 * Access: RO 8507 */ 8508 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 8509 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 8510 8511 /* reg_rauhtd_ipv6_ent_dip 8512 * Destination IPv6 address. 8513 * Access: RO 8514 */ 8515 MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 8516 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10); 8517 8518 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload, 8519 int ent_index, u16 *p_rif, 8520 u32 *p_dip) 8521 { 8522 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index); 8523 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index); 8524 } 8525 8526 static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload, 8527 int rec_index, u16 *p_rif, 8528 char *p_dip) 8529 { 8530 *p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index); 8531 mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip); 8532 } 8533 8534 /* RTDP - Routing Tunnel Decap Properties Register 8535 * ----------------------------------------------- 8536 * The RTDP register is used for configuring the tunnel decap properties of NVE 8537 * and IPinIP. 8538 */ 8539 #define MLXSW_REG_RTDP_ID 0x8020 8540 #define MLXSW_REG_RTDP_LEN 0x44 8541 8542 MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN); 8543 8544 enum mlxsw_reg_rtdp_type { 8545 MLXSW_REG_RTDP_TYPE_NVE, 8546 MLXSW_REG_RTDP_TYPE_IPIP, 8547 }; 8548 8549 /* reg_rtdp_type 8550 * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type. 8551 * Access: RW 8552 */ 8553 MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4); 8554 8555 /* reg_rtdp_tunnel_index 8556 * Index to the Decap entry. 8557 * For Spectrum, Index to KVD Linear. 8558 * Access: Index 8559 */ 8560 MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24); 8561 8562 /* reg_rtdp_egress_router_interface 8563 * Underlay egress router interface. 8564 * Valid range is from 0 to cap_max_router_interfaces - 1 8565 * Access: RW 8566 */ 8567 MLXSW_ITEM32(reg, rtdp, egress_router_interface, 0x40, 0, 16); 8568 8569 /* IPinIP */ 8570 8571 /* reg_rtdp_ipip_irif 8572 * Ingress Router Interface for the overlay router 8573 * Access: RW 8574 */ 8575 MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16); 8576 8577 enum mlxsw_reg_rtdp_ipip_sip_check { 8578 /* No sip checks. */ 8579 MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO, 8580 /* Filter packet if underlay is not IPv4 or if underlay SIP does not 8581 * equal ipv4_usip. 8582 */ 8583 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4, 8584 /* Filter packet if underlay is not IPv6 or if underlay SIP does not 8585 * equal ipv6_usip. 8586 */ 8587 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3, 8588 }; 8589 8590 /* reg_rtdp_ipip_sip_check 8591 * SIP check to perform. If decapsulation failed due to these configurations 8592 * then trap_id is IPIP_DECAP_ERROR. 8593 * Access: RW 8594 */ 8595 MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3); 8596 8597 /* If set, allow decapsulation of IPinIP (without GRE). */ 8598 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP BIT(0) 8599 /* If set, allow decapsulation of IPinGREinIP without a key. */ 8600 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE BIT(1) 8601 /* If set, allow decapsulation of IPinGREinIP with a key. */ 8602 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY BIT(2) 8603 8604 /* reg_rtdp_ipip_type_check 8605 * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to 8606 * these configurations then trap_id is IPIP_DECAP_ERROR. 8607 * Access: RW 8608 */ 8609 MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3); 8610 8611 /* reg_rtdp_ipip_gre_key_check 8612 * Whether GRE key should be checked. When check is enabled: 8613 * - A packet received as IPinIP (without GRE) will always pass. 8614 * - A packet received as IPinGREinIP without a key will not pass the check. 8615 * - A packet received as IPinGREinIP with a key will pass the check only if the 8616 * key in the packet is equal to expected_gre_key. 8617 * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR. 8618 * Access: RW 8619 */ 8620 MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1); 8621 8622 /* reg_rtdp_ipip_ipv4_usip 8623 * Underlay IPv4 address for ipv4 source address check. 8624 * Reserved when sip_check is not '1'. 8625 * Access: RW 8626 */ 8627 MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32); 8628 8629 /* reg_rtdp_ipip_ipv6_usip_ptr 8630 * This field is valid when sip_check is "sipv6 check explicitly". This is a 8631 * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index 8632 * is to the KVD linear. 8633 * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6. 8634 * Access: RW 8635 */ 8636 MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24); 8637 8638 /* reg_rtdp_ipip_expected_gre_key 8639 * GRE key for checking. 8640 * Reserved when gre_key_check is '0'. 8641 * Access: RW 8642 */ 8643 MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32); 8644 8645 static inline void mlxsw_reg_rtdp_pack(char *payload, 8646 enum mlxsw_reg_rtdp_type type, 8647 u32 tunnel_index) 8648 { 8649 MLXSW_REG_ZERO(rtdp, payload); 8650 mlxsw_reg_rtdp_type_set(payload, type); 8651 mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index); 8652 } 8653 8654 static inline void 8655 mlxsw_reg_rtdp_ipip_pack(char *payload, u16 irif, 8656 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 8657 unsigned int type_check, bool gre_key_check, 8658 u32 expected_gre_key) 8659 { 8660 mlxsw_reg_rtdp_ipip_irif_set(payload, irif); 8661 mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check); 8662 mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check); 8663 mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check); 8664 mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key); 8665 } 8666 8667 static inline void 8668 mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif, 8669 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 8670 unsigned int type_check, bool gre_key_check, 8671 u32 ipv4_usip, u32 expected_gre_key) 8672 { 8673 mlxsw_reg_rtdp_ipip_pack(payload, irif, sip_check, type_check, 8674 gre_key_check, expected_gre_key); 8675 mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip); 8676 } 8677 8678 static inline void 8679 mlxsw_reg_rtdp_ipip6_pack(char *payload, u16 irif, 8680 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 8681 unsigned int type_check, bool gre_key_check, 8682 u32 ipv6_usip_ptr, u32 expected_gre_key) 8683 { 8684 mlxsw_reg_rtdp_ipip_pack(payload, irif, sip_check, type_check, 8685 gre_key_check, expected_gre_key); 8686 mlxsw_reg_rtdp_ipip_ipv6_usip_ptr_set(payload, ipv6_usip_ptr); 8687 } 8688 8689 /* RIPS - Router IP version Six Register 8690 * ------------------------------------- 8691 * The RIPS register is used to store IPv6 addresses for use by the NVE and 8692 * IPinIP 8693 */ 8694 #define MLXSW_REG_RIPS_ID 0x8021 8695 #define MLXSW_REG_RIPS_LEN 0x14 8696 8697 MLXSW_REG_DEFINE(rips, MLXSW_REG_RIPS_ID, MLXSW_REG_RIPS_LEN); 8698 8699 /* reg_rips_index 8700 * Index to IPv6 address. 8701 * For Spectrum, the index is to the KVD linear. 8702 * Access: Index 8703 */ 8704 MLXSW_ITEM32(reg, rips, index, 0x00, 0, 24); 8705 8706 /* reg_rips_ipv6 8707 * IPv6 address 8708 * Access: RW 8709 */ 8710 MLXSW_ITEM_BUF(reg, rips, ipv6, 0x04, 16); 8711 8712 static inline void mlxsw_reg_rips_pack(char *payload, u32 index, 8713 const struct in6_addr *ipv6) 8714 { 8715 MLXSW_REG_ZERO(rips, payload); 8716 mlxsw_reg_rips_index_set(payload, index); 8717 mlxsw_reg_rips_ipv6_memcpy_to(payload, (const char *)ipv6); 8718 } 8719 8720 /* RATRAD - Router Adjacency Table Activity Dump Register 8721 * ------------------------------------------------------ 8722 * The RATRAD register is used to dump and optionally clear activity bits of 8723 * router adjacency table entries. 8724 */ 8725 #define MLXSW_REG_RATRAD_ID 0x8022 8726 #define MLXSW_REG_RATRAD_LEN 0x210 8727 8728 MLXSW_REG_DEFINE(ratrad, MLXSW_REG_RATRAD_ID, MLXSW_REG_RATRAD_LEN); 8729 8730 enum { 8731 /* Read activity */ 8732 MLXSW_REG_RATRAD_OP_READ_ACTIVITY, 8733 /* Read and clear activity */ 8734 MLXSW_REG_RATRAD_OP_READ_CLEAR_ACTIVITY, 8735 }; 8736 8737 /* reg_ratrad_op 8738 * Access: Operation 8739 */ 8740 MLXSW_ITEM32(reg, ratrad, op, 0x00, 30, 2); 8741 8742 /* reg_ratrad_ecmp_size 8743 * ecmp_size is the amount of sequential entries from adjacency_index. Valid 8744 * ranges: 8745 * Spectrum-1: 32-64, 512, 1024, 2048, 4096 8746 * Spectrum-2/3: 32-128, 256, 512, 1024, 2048, 4096 8747 * Access: Index 8748 */ 8749 MLXSW_ITEM32(reg, ratrad, ecmp_size, 0x00, 0, 13); 8750 8751 /* reg_ratrad_adjacency_index 8752 * Index into the adjacency table. 8753 * Access: Index 8754 */ 8755 MLXSW_ITEM32(reg, ratrad, adjacency_index, 0x04, 0, 24); 8756 8757 /* reg_ratrad_activity_vector 8758 * Activity bit per adjacency index. 8759 * Bits higher than ecmp_size are reserved. 8760 * Access: RO 8761 */ 8762 MLXSW_ITEM_BIT_ARRAY(reg, ratrad, activity_vector, 0x10, 0x200, 1); 8763 8764 static inline void mlxsw_reg_ratrad_pack(char *payload, u32 adjacency_index, 8765 u16 ecmp_size) 8766 { 8767 MLXSW_REG_ZERO(ratrad, payload); 8768 mlxsw_reg_ratrad_op_set(payload, 8769 MLXSW_REG_RATRAD_OP_READ_CLEAR_ACTIVITY); 8770 mlxsw_reg_ratrad_ecmp_size_set(payload, ecmp_size); 8771 mlxsw_reg_ratrad_adjacency_index_set(payload, adjacency_index); 8772 } 8773 8774 /* RIGR-V2 - Router Interface Group Register Version 2 8775 * --------------------------------------------------- 8776 * The RIGR_V2 register is used to add, remove and query egress interface list 8777 * of a multicast forwarding entry. 8778 */ 8779 #define MLXSW_REG_RIGR2_ID 0x8023 8780 #define MLXSW_REG_RIGR2_LEN 0xB0 8781 8782 #define MLXSW_REG_RIGR2_MAX_ERIFS 32 8783 8784 MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN); 8785 8786 /* reg_rigr2_rigr_index 8787 * KVD Linear index. 8788 * Access: Index 8789 */ 8790 MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24); 8791 8792 /* reg_rigr2_vnext 8793 * Next RIGR Index is valid. 8794 * Access: RW 8795 */ 8796 MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1); 8797 8798 /* reg_rigr2_next_rigr_index 8799 * Next RIGR Index. The index is to the KVD linear. 8800 * Reserved when vnxet = '0'. 8801 * Access: RW 8802 */ 8803 MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24); 8804 8805 /* reg_rigr2_vrmid 8806 * RMID Index is valid. 8807 * Access: RW 8808 */ 8809 MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1); 8810 8811 /* reg_rigr2_rmid_index 8812 * RMID Index. 8813 * Range 0 .. max_mid - 1 8814 * Reserved when vrmid = '0'. 8815 * The index is to the Port Group Table (PGT) 8816 * Access: RW 8817 */ 8818 MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16); 8819 8820 /* reg_rigr2_erif_entry_v 8821 * Egress Router Interface is valid. 8822 * Note that low-entries must be set if high-entries are set. For 8823 * example: if erif_entry[2].v is set then erif_entry[1].v and 8824 * erif_entry[0].v must be set. 8825 * Index can be from 0 to cap_mc_erif_list_entries-1 8826 * Access: RW 8827 */ 8828 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false); 8829 8830 /* reg_rigr2_erif_entry_erif 8831 * Egress Router Interface. 8832 * Valid range is from 0 to cap_max_router_interfaces - 1 8833 * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1 8834 * Access: RW 8835 */ 8836 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false); 8837 8838 static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index, 8839 bool vnext, u32 next_rigr_index) 8840 { 8841 MLXSW_REG_ZERO(rigr2, payload); 8842 mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index); 8843 mlxsw_reg_rigr2_vnext_set(payload, vnext); 8844 mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index); 8845 mlxsw_reg_rigr2_vrmid_set(payload, 0); 8846 mlxsw_reg_rigr2_rmid_index_set(payload, 0); 8847 } 8848 8849 static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index, 8850 bool v, u16 erif) 8851 { 8852 mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v); 8853 mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif); 8854 } 8855 8856 /* RECR-V2 - Router ECMP Configuration Version 2 Register 8857 * ------------------------------------------------------ 8858 */ 8859 #define MLXSW_REG_RECR2_ID 0x8025 8860 #define MLXSW_REG_RECR2_LEN 0x38 8861 8862 MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN); 8863 8864 /* reg_recr2_pp 8865 * Per-port configuration 8866 * Access: Index 8867 */ 8868 MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1); 8869 8870 /* reg_recr2_sh 8871 * Symmetric hash 8872 * Access: RW 8873 */ 8874 MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1); 8875 8876 /* reg_recr2_seed 8877 * Seed 8878 * Access: RW 8879 */ 8880 MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32); 8881 8882 enum { 8883 /* Enable IPv4 fields if packet is not TCP and not UDP */ 8884 MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP = 3, 8885 /* Enable IPv4 fields if packet is TCP or UDP */ 8886 MLXSW_REG_RECR2_IPV4_EN_TCP_UDP = 4, 8887 /* Enable IPv6 fields if packet is not TCP and not UDP */ 8888 MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP = 5, 8889 /* Enable IPv6 fields if packet is TCP or UDP */ 8890 MLXSW_REG_RECR2_IPV6_EN_TCP_UDP = 6, 8891 /* Enable TCP/UDP header fields if packet is IPv4 */ 8892 MLXSW_REG_RECR2_TCP_UDP_EN_IPV4 = 7, 8893 /* Enable TCP/UDP header fields if packet is IPv6 */ 8894 MLXSW_REG_RECR2_TCP_UDP_EN_IPV6 = 8, 8895 8896 __MLXSW_REG_RECR2_HEADER_CNT, 8897 }; 8898 8899 /* reg_recr2_outer_header_enables 8900 * Bit mask where each bit enables a specific layer to be included in 8901 * the hash calculation. 8902 * Access: RW 8903 */ 8904 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1); 8905 8906 enum { 8907 /* IPv4 Source IP */ 8908 MLXSW_REG_RECR2_IPV4_SIP0 = 9, 8909 MLXSW_REG_RECR2_IPV4_SIP3 = 12, 8910 /* IPv4 Destination IP */ 8911 MLXSW_REG_RECR2_IPV4_DIP0 = 13, 8912 MLXSW_REG_RECR2_IPV4_DIP3 = 16, 8913 /* IP Protocol */ 8914 MLXSW_REG_RECR2_IPV4_PROTOCOL = 17, 8915 /* IPv6 Source IP */ 8916 MLXSW_REG_RECR2_IPV6_SIP0_7 = 21, 8917 MLXSW_REG_RECR2_IPV6_SIP8 = 29, 8918 MLXSW_REG_RECR2_IPV6_SIP15 = 36, 8919 /* IPv6 Destination IP */ 8920 MLXSW_REG_RECR2_IPV6_DIP0_7 = 37, 8921 MLXSW_REG_RECR2_IPV6_DIP8 = 45, 8922 MLXSW_REG_RECR2_IPV6_DIP15 = 52, 8923 /* IPv6 Next Header */ 8924 MLXSW_REG_RECR2_IPV6_NEXT_HEADER = 53, 8925 /* IPv6 Flow Label */ 8926 MLXSW_REG_RECR2_IPV6_FLOW_LABEL = 57, 8927 /* TCP/UDP Source Port */ 8928 MLXSW_REG_RECR2_TCP_UDP_SPORT = 74, 8929 /* TCP/UDP Destination Port */ 8930 MLXSW_REG_RECR2_TCP_UDP_DPORT = 75, 8931 8932 __MLXSW_REG_RECR2_FIELD_CNT, 8933 }; 8934 8935 /* reg_recr2_outer_header_fields_enable 8936 * Packet fields to enable for ECMP hash subject to outer_header_enable. 8937 * Access: RW 8938 */ 8939 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1); 8940 8941 /* reg_recr2_inner_header_enables 8942 * Bit mask where each bit enables a specific inner layer to be included in the 8943 * hash calculation. Same values as reg_recr2_outer_header_enables. 8944 * Access: RW 8945 */ 8946 MLXSW_ITEM_BIT_ARRAY(reg, recr2, inner_header_enables, 0x2C, 0x04, 1); 8947 8948 enum { 8949 /* Inner IPv4 Source IP */ 8950 MLXSW_REG_RECR2_INNER_IPV4_SIP0 = 3, 8951 MLXSW_REG_RECR2_INNER_IPV4_SIP3 = 6, 8952 /* Inner IPv4 Destination IP */ 8953 MLXSW_REG_RECR2_INNER_IPV4_DIP0 = 7, 8954 MLXSW_REG_RECR2_INNER_IPV4_DIP3 = 10, 8955 /* Inner IP Protocol */ 8956 MLXSW_REG_RECR2_INNER_IPV4_PROTOCOL = 11, 8957 /* Inner IPv6 Source IP */ 8958 MLXSW_REG_RECR2_INNER_IPV6_SIP0_7 = 12, 8959 MLXSW_REG_RECR2_INNER_IPV6_SIP8 = 20, 8960 MLXSW_REG_RECR2_INNER_IPV6_SIP15 = 27, 8961 /* Inner IPv6 Destination IP */ 8962 MLXSW_REG_RECR2_INNER_IPV6_DIP0_7 = 28, 8963 MLXSW_REG_RECR2_INNER_IPV6_DIP8 = 36, 8964 MLXSW_REG_RECR2_INNER_IPV6_DIP15 = 43, 8965 /* Inner IPv6 Next Header */ 8966 MLXSW_REG_RECR2_INNER_IPV6_NEXT_HEADER = 44, 8967 /* Inner IPv6 Flow Label */ 8968 MLXSW_REG_RECR2_INNER_IPV6_FLOW_LABEL = 45, 8969 /* Inner TCP/UDP Source Port */ 8970 MLXSW_REG_RECR2_INNER_TCP_UDP_SPORT = 46, 8971 /* Inner TCP/UDP Destination Port */ 8972 MLXSW_REG_RECR2_INNER_TCP_UDP_DPORT = 47, 8973 8974 __MLXSW_REG_RECR2_INNER_FIELD_CNT, 8975 }; 8976 8977 /* reg_recr2_inner_header_fields_enable 8978 * Inner packet fields to enable for ECMP hash subject to inner_header_enables. 8979 * Access: RW 8980 */ 8981 MLXSW_ITEM_BIT_ARRAY(reg, recr2, inner_header_fields_enable, 0x30, 0x08, 1); 8982 8983 static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed) 8984 { 8985 MLXSW_REG_ZERO(recr2, payload); 8986 mlxsw_reg_recr2_pp_set(payload, false); 8987 mlxsw_reg_recr2_sh_set(payload, true); 8988 mlxsw_reg_recr2_seed_set(payload, seed); 8989 } 8990 8991 /* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register 8992 * -------------------------------------------------------------- 8993 * The RMFT_V2 register is used to configure and query the multicast table. 8994 */ 8995 #define MLXSW_REG_RMFT2_ID 0x8027 8996 #define MLXSW_REG_RMFT2_LEN 0x174 8997 8998 MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN); 8999 9000 /* reg_rmft2_v 9001 * Valid 9002 * Access: RW 9003 */ 9004 MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1); 9005 9006 enum mlxsw_reg_rmft2_type { 9007 MLXSW_REG_RMFT2_TYPE_IPV4, 9008 MLXSW_REG_RMFT2_TYPE_IPV6 9009 }; 9010 9011 /* reg_rmft2_type 9012 * Access: Index 9013 */ 9014 MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2); 9015 9016 enum mlxsw_sp_reg_rmft2_op { 9017 /* For Write: 9018 * Write operation. Used to write a new entry to the table. All RW 9019 * fields are relevant for new entry. Activity bit is set for new 9020 * entries - Note write with v (Valid) 0 will delete the entry. 9021 * For Query: 9022 * Read operation 9023 */ 9024 MLXSW_REG_RMFT2_OP_READ_WRITE, 9025 }; 9026 9027 /* reg_rmft2_op 9028 * Operation. 9029 * Access: OP 9030 */ 9031 MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2); 9032 9033 /* reg_rmft2_a 9034 * Activity. Set for new entries. Set if a packet lookup has hit on the specific 9035 * entry. 9036 * Access: RO 9037 */ 9038 MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1); 9039 9040 /* reg_rmft2_offset 9041 * Offset within the multicast forwarding table to write to. 9042 * Access: Index 9043 */ 9044 MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16); 9045 9046 /* reg_rmft2_virtual_router 9047 * Virtual Router ID. Range from 0..cap_max_virtual_routers-1 9048 * Access: RW 9049 */ 9050 MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16); 9051 9052 enum mlxsw_reg_rmft2_irif_mask { 9053 MLXSW_REG_RMFT2_IRIF_MASK_IGNORE, 9054 MLXSW_REG_RMFT2_IRIF_MASK_COMPARE 9055 }; 9056 9057 /* reg_rmft2_irif_mask 9058 * Ingress RIF mask. 9059 * Access: RW 9060 */ 9061 MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1); 9062 9063 /* reg_rmft2_irif 9064 * Ingress RIF index. 9065 * Access: RW 9066 */ 9067 MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16); 9068 9069 /* reg_rmft2_dip{4,6} 9070 * Destination IPv4/6 address 9071 * Access: RW 9072 */ 9073 MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16); 9074 MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32); 9075 9076 /* reg_rmft2_dip{4,6}_mask 9077 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 9078 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 9079 * Access: RW 9080 */ 9081 MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16); 9082 MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32); 9083 9084 /* reg_rmft2_sip{4,6} 9085 * Source IPv4/6 address 9086 * Access: RW 9087 */ 9088 MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16); 9089 MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32); 9090 9091 /* reg_rmft2_sip{4,6}_mask 9092 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 9093 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 9094 * Access: RW 9095 */ 9096 MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16); 9097 MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32); 9098 9099 /* reg_rmft2_flexible_action_set 9100 * ACL action set. The only supported action types in this field and in any 9101 * action-set pointed from here are as follows: 9102 * 00h: ACTION_NULL 9103 * 01h: ACTION_MAC_TTL, only TTL configuration is supported. 9104 * 03h: ACTION_TRAP 9105 * 06h: ACTION_QOS 9106 * 08h: ACTION_POLICING_MONITORING 9107 * 10h: ACTION_ROUTER_MC 9108 * Access: RW 9109 */ 9110 MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80, 9111 MLXSW_REG_FLEX_ACTION_SET_LEN); 9112 9113 static inline void 9114 mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset, 9115 u16 virtual_router, 9116 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 9117 const char *flex_action_set) 9118 { 9119 MLXSW_REG_ZERO(rmft2, payload); 9120 mlxsw_reg_rmft2_v_set(payload, v); 9121 mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE); 9122 mlxsw_reg_rmft2_offset_set(payload, offset); 9123 mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router); 9124 mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask); 9125 mlxsw_reg_rmft2_irif_set(payload, irif); 9126 if (flex_action_set) 9127 mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload, 9128 flex_action_set); 9129 } 9130 9131 static inline void 9132 mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router, 9133 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 9134 u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask, 9135 const char *flexible_action_set) 9136 { 9137 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 9138 irif_mask, irif, flexible_action_set); 9139 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4); 9140 mlxsw_reg_rmft2_dip4_set(payload, dip4); 9141 mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask); 9142 mlxsw_reg_rmft2_sip4_set(payload, sip4); 9143 mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask); 9144 } 9145 9146 static inline void 9147 mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router, 9148 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 9149 struct in6_addr dip6, struct in6_addr dip6_mask, 9150 struct in6_addr sip6, struct in6_addr sip6_mask, 9151 const char *flexible_action_set) 9152 { 9153 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 9154 irif_mask, irif, flexible_action_set); 9155 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6); 9156 mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6); 9157 mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask); 9158 mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6); 9159 mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask); 9160 } 9161 9162 /* REIV - Router Egress Interface to VID Register 9163 * ---------------------------------------------- 9164 * The REIV register maps {eRIF, egress_port} -> VID. 9165 * This mapping is done at the egress, after the ACLs. 9166 * This mapping always takes effect after router, regardless of cast 9167 * (for unicast/multicast/port-base multicast), regardless of eRIF type and 9168 * regardless of bridge decisions (e.g. SFD for unicast or SMPE). 9169 * Reserved when the RIF is a loopback RIF. 9170 * 9171 * Note: Reserved when legacy bridge model is used. 9172 */ 9173 #define MLXSW_REG_REIV_ID 0x8034 9174 #define MLXSW_REG_REIV_BASE_LEN 0x20 /* base length, without records */ 9175 #define MLXSW_REG_REIV_REC_LEN 0x04 /* record length */ 9176 #define MLXSW_REG_REIV_REC_MAX_COUNT 256 /* firmware limitation */ 9177 #define MLXSW_REG_REIV_LEN (MLXSW_REG_REIV_BASE_LEN + \ 9178 MLXSW_REG_REIV_REC_LEN * \ 9179 MLXSW_REG_REIV_REC_MAX_COUNT) 9180 9181 MLXSW_REG_DEFINE(reiv, MLXSW_REG_REIV_ID, MLXSW_REG_REIV_LEN); 9182 9183 /* reg_reiv_port_page 9184 * Port page - elport_record[0] is 256*port_page. 9185 * Access: Index 9186 */ 9187 MLXSW_ITEM32(reg, reiv, port_page, 0x00, 0, 4); 9188 9189 /* reg_reiv_erif 9190 * Egress RIF. 9191 * Range is 0..cap_max_router_interfaces-1. 9192 * Access: Index 9193 */ 9194 MLXSW_ITEM32(reg, reiv, erif, 0x04, 0, 16); 9195 9196 /* reg_reiv_rec_update 9197 * Update enable (when write): 9198 * 0 - Do not update the entry. 9199 * 1 - Update the entry. 9200 * Access: OP 9201 */ 9202 MLXSW_ITEM32_INDEXED(reg, reiv, rec_update, MLXSW_REG_REIV_BASE_LEN, 31, 1, 9203 MLXSW_REG_REIV_REC_LEN, 0x00, false); 9204 9205 /* reg_reiv_rec_evid 9206 * Egress VID. 9207 * Range is 0..4095. 9208 * Access: RW 9209 */ 9210 MLXSW_ITEM32_INDEXED(reg, reiv, rec_evid, MLXSW_REG_REIV_BASE_LEN, 0, 12, 9211 MLXSW_REG_REIV_REC_LEN, 0x00, false); 9212 9213 static inline void mlxsw_reg_reiv_pack(char *payload, u8 port_page, u16 erif) 9214 { 9215 MLXSW_REG_ZERO(reiv, payload); 9216 mlxsw_reg_reiv_port_page_set(payload, port_page); 9217 mlxsw_reg_reiv_erif_set(payload, erif); 9218 } 9219 9220 /* MFCR - Management Fan Control Register 9221 * -------------------------------------- 9222 * This register controls the settings of the Fan Speed PWM mechanism. 9223 */ 9224 #define MLXSW_REG_MFCR_ID 0x9001 9225 #define MLXSW_REG_MFCR_LEN 0x08 9226 9227 MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN); 9228 9229 enum mlxsw_reg_mfcr_pwm_frequency { 9230 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00, 9231 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01, 9232 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02, 9233 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40, 9234 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41, 9235 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42, 9236 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43, 9237 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44, 9238 }; 9239 9240 /* reg_mfcr_pwm_frequency 9241 * Controls the frequency of the PWM signal. 9242 * Access: RW 9243 */ 9244 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7); 9245 9246 #define MLXSW_MFCR_TACHOS_MAX 10 9247 9248 /* reg_mfcr_tacho_active 9249 * Indicates which of the tachometer is active (bit per tachometer). 9250 * Access: RO 9251 */ 9252 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX); 9253 9254 #define MLXSW_MFCR_PWMS_MAX 5 9255 9256 /* reg_mfcr_pwm_active 9257 * Indicates which of the PWM control is active (bit per PWM). 9258 * Access: RO 9259 */ 9260 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX); 9261 9262 static inline void 9263 mlxsw_reg_mfcr_pack(char *payload, 9264 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency) 9265 { 9266 MLXSW_REG_ZERO(mfcr, payload); 9267 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency); 9268 } 9269 9270 static inline void 9271 mlxsw_reg_mfcr_unpack(char *payload, 9272 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency, 9273 u16 *p_tacho_active, u8 *p_pwm_active) 9274 { 9275 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload); 9276 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload); 9277 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload); 9278 } 9279 9280 /* MFSC - Management Fan Speed Control Register 9281 * -------------------------------------------- 9282 * This register controls the settings of the Fan Speed PWM mechanism. 9283 */ 9284 #define MLXSW_REG_MFSC_ID 0x9002 9285 #define MLXSW_REG_MFSC_LEN 0x08 9286 9287 MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN); 9288 9289 /* reg_mfsc_pwm 9290 * Fan pwm to control / monitor. 9291 * Access: Index 9292 */ 9293 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3); 9294 9295 /* reg_mfsc_pwm_duty_cycle 9296 * Controls the duty cycle of the PWM. Value range from 0..255 to 9297 * represent duty cycle of 0%...100%. 9298 * Access: RW 9299 */ 9300 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8); 9301 9302 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm, 9303 u8 pwm_duty_cycle) 9304 { 9305 MLXSW_REG_ZERO(mfsc, payload); 9306 mlxsw_reg_mfsc_pwm_set(payload, pwm); 9307 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle); 9308 } 9309 9310 /* MFSM - Management Fan Speed Measurement 9311 * --------------------------------------- 9312 * This register controls the settings of the Tacho measurements and 9313 * enables reading the Tachometer measurements. 9314 */ 9315 #define MLXSW_REG_MFSM_ID 0x9003 9316 #define MLXSW_REG_MFSM_LEN 0x08 9317 9318 MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN); 9319 9320 /* reg_mfsm_tacho 9321 * Fan tachometer index. 9322 * Access: Index 9323 */ 9324 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4); 9325 9326 /* reg_mfsm_rpm 9327 * Fan speed (round per minute). 9328 * Access: RO 9329 */ 9330 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16); 9331 9332 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho) 9333 { 9334 MLXSW_REG_ZERO(mfsm, payload); 9335 mlxsw_reg_mfsm_tacho_set(payload, tacho); 9336 } 9337 9338 /* MFSL - Management Fan Speed Limit Register 9339 * ------------------------------------------ 9340 * The Fan Speed Limit register is used to configure the fan speed 9341 * event / interrupt notification mechanism. Fan speed threshold are 9342 * defined for both under-speed and over-speed. 9343 */ 9344 #define MLXSW_REG_MFSL_ID 0x9004 9345 #define MLXSW_REG_MFSL_LEN 0x0C 9346 9347 MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN); 9348 9349 /* reg_mfsl_tacho 9350 * Fan tachometer index. 9351 * Access: Index 9352 */ 9353 MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4); 9354 9355 /* reg_mfsl_tach_min 9356 * Tachometer minimum value (minimum RPM). 9357 * Access: RW 9358 */ 9359 MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16); 9360 9361 /* reg_mfsl_tach_max 9362 * Tachometer maximum value (maximum RPM). 9363 * Access: RW 9364 */ 9365 MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16); 9366 9367 static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho, 9368 u16 tach_min, u16 tach_max) 9369 { 9370 MLXSW_REG_ZERO(mfsl, payload); 9371 mlxsw_reg_mfsl_tacho_set(payload, tacho); 9372 mlxsw_reg_mfsl_tach_min_set(payload, tach_min); 9373 mlxsw_reg_mfsl_tach_max_set(payload, tach_max); 9374 } 9375 9376 static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho, 9377 u16 *p_tach_min, u16 *p_tach_max) 9378 { 9379 if (p_tach_min) 9380 *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload); 9381 9382 if (p_tach_max) 9383 *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload); 9384 } 9385 9386 /* FORE - Fan Out of Range Event Register 9387 * -------------------------------------- 9388 * This register reports the status of the controlled fans compared to the 9389 * range defined by the MFSL register. 9390 */ 9391 #define MLXSW_REG_FORE_ID 0x9007 9392 #define MLXSW_REG_FORE_LEN 0x0C 9393 9394 MLXSW_REG_DEFINE(fore, MLXSW_REG_FORE_ID, MLXSW_REG_FORE_LEN); 9395 9396 /* fan_under_limit 9397 * Fan speed is below the low limit defined in MFSL register. Each bit relates 9398 * to a single tachometer and indicates the specific tachometer reading is 9399 * below the threshold. 9400 * Access: RO 9401 */ 9402 MLXSW_ITEM32(reg, fore, fan_under_limit, 0x00, 16, 10); 9403 9404 static inline void mlxsw_reg_fore_unpack(char *payload, u8 tacho, 9405 bool *fault) 9406 { 9407 u16 limit; 9408 9409 if (fault) { 9410 limit = mlxsw_reg_fore_fan_under_limit_get(payload); 9411 *fault = limit & BIT(tacho); 9412 } 9413 } 9414 9415 /* MTCAP - Management Temperature Capabilities 9416 * ------------------------------------------- 9417 * This register exposes the capabilities of the device and 9418 * system temperature sensing. 9419 */ 9420 #define MLXSW_REG_MTCAP_ID 0x9009 9421 #define MLXSW_REG_MTCAP_LEN 0x08 9422 9423 MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN); 9424 9425 /* reg_mtcap_sensor_count 9426 * Number of sensors supported by the device. 9427 * This includes the QSFP module sensors (if exists in the QSFP module). 9428 * Access: RO 9429 */ 9430 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7); 9431 9432 /* MTMP - Management Temperature 9433 * ----------------------------- 9434 * This register controls the settings of the temperature measurements 9435 * and enables reading the temperature measurements. Note that temperature 9436 * is in 0.125 degrees Celsius. 9437 */ 9438 #define MLXSW_REG_MTMP_ID 0x900A 9439 #define MLXSW_REG_MTMP_LEN 0x20 9440 9441 MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN); 9442 9443 /* reg_mtmp_slot_index 9444 * Slot index (0: Main board). 9445 * Access: Index 9446 */ 9447 MLXSW_ITEM32(reg, mtmp, slot_index, 0x00, 16, 4); 9448 9449 #define MLXSW_REG_MTMP_MODULE_INDEX_MIN 64 9450 #define MLXSW_REG_MTMP_GBOX_INDEX_MIN 256 9451 /* reg_mtmp_sensor_index 9452 * Sensors index to access. 9453 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially 9454 * (module 0 is mapped to sensor_index 64). 9455 * Access: Index 9456 */ 9457 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 12); 9458 9459 /* Convert to milli degrees Celsius */ 9460 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) ({ typeof(val) v_ = (val); \ 9461 ((v_) >= 0) ? ((v_) * 125) : \ 9462 ((s16)((GENMASK(15, 0) + (v_) + 1) \ 9463 * 125)); }) 9464 9465 /* reg_mtmp_max_operational_temperature 9466 * The highest temperature in the nominal operational range. Reading is in 9467 * 0.125 Celsius degrees units. 9468 * In case of module this is SFF critical temperature threshold. 9469 * Access: RO 9470 */ 9471 MLXSW_ITEM32(reg, mtmp, max_operational_temperature, 0x04, 16, 16); 9472 9473 /* reg_mtmp_temperature 9474 * Temperature reading from the sensor. Reading is in 0.125 Celsius 9475 * degrees units. 9476 * Access: RO 9477 */ 9478 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16); 9479 9480 /* reg_mtmp_mte 9481 * Max Temperature Enable - enables measuring the max temperature on a sensor. 9482 * Access: RW 9483 */ 9484 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1); 9485 9486 /* reg_mtmp_mtr 9487 * Max Temperature Reset - clears the value of the max temperature register. 9488 * Access: WO 9489 */ 9490 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1); 9491 9492 /* reg_mtmp_max_temperature 9493 * The highest measured temperature from the sensor. 9494 * When the bit mte is cleared, the field max_temperature is reserved. 9495 * Access: RO 9496 */ 9497 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16); 9498 9499 /* reg_mtmp_tee 9500 * Temperature Event Enable. 9501 * 0 - Do not generate event 9502 * 1 - Generate event 9503 * 2 - Generate single event 9504 * Access: RW 9505 */ 9506 9507 enum mlxsw_reg_mtmp_tee { 9508 MLXSW_REG_MTMP_TEE_NO_EVENT, 9509 MLXSW_REG_MTMP_TEE_GENERATE_EVENT, 9510 MLXSW_REG_MTMP_TEE_GENERATE_SINGLE_EVENT, 9511 }; 9512 9513 MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2); 9514 9515 #define MLXSW_REG_MTMP_THRESH_HI 0x348 /* 105 Celsius */ 9516 9517 /* reg_mtmp_temperature_threshold_hi 9518 * High threshold for Temperature Warning Event. In 0.125 Celsius. 9519 * Access: RW 9520 */ 9521 MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16); 9522 9523 #define MLXSW_REG_MTMP_HYSTERESIS_TEMP 0x28 /* 5 Celsius */ 9524 /* reg_mtmp_temperature_threshold_lo 9525 * Low threshold for Temperature Warning Event. In 0.125 Celsius. 9526 * Access: RW 9527 */ 9528 MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16); 9529 9530 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8 9531 9532 /* reg_mtmp_sensor_name 9533 * Sensor Name 9534 * Access: RO 9535 */ 9536 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE); 9537 9538 static inline void mlxsw_reg_mtmp_pack(char *payload, u8 slot_index, 9539 u16 sensor_index, bool max_temp_enable, 9540 bool max_temp_reset) 9541 { 9542 MLXSW_REG_ZERO(mtmp, payload); 9543 mlxsw_reg_mtmp_slot_index_set(payload, slot_index); 9544 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index); 9545 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable); 9546 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset); 9547 mlxsw_reg_mtmp_temperature_threshold_hi_set(payload, 9548 MLXSW_REG_MTMP_THRESH_HI); 9549 } 9550 9551 static inline void mlxsw_reg_mtmp_unpack(char *payload, int *p_temp, 9552 int *p_max_temp, int *p_temp_hi, 9553 int *p_max_oper_temp, 9554 char *sensor_name) 9555 { 9556 s16 temp; 9557 9558 if (p_temp) { 9559 temp = mlxsw_reg_mtmp_temperature_get(payload); 9560 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9561 } 9562 if (p_max_temp) { 9563 temp = mlxsw_reg_mtmp_max_temperature_get(payload); 9564 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9565 } 9566 if (p_temp_hi) { 9567 temp = mlxsw_reg_mtmp_temperature_threshold_hi_get(payload); 9568 *p_temp_hi = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9569 } 9570 if (p_max_oper_temp) { 9571 temp = mlxsw_reg_mtmp_max_operational_temperature_get(payload); 9572 *p_max_oper_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9573 } 9574 if (sensor_name) 9575 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name); 9576 } 9577 9578 /* MTWE - Management Temperature Warning Event 9579 * ------------------------------------------- 9580 * This register is used for over temperature warning. 9581 */ 9582 #define MLXSW_REG_MTWE_ID 0x900B 9583 #define MLXSW_REG_MTWE_LEN 0x10 9584 9585 MLXSW_REG_DEFINE(mtwe, MLXSW_REG_MTWE_ID, MLXSW_REG_MTWE_LEN); 9586 9587 /* reg_mtwe_sensor_warning 9588 * Bit vector indicating which of the sensor reading is above threshold. 9589 * Address 00h bit31 is sensor_warning[127]. 9590 * Address 0Ch bit0 is sensor_warning[0]. 9591 * Access: RO 9592 */ 9593 MLXSW_ITEM_BIT_ARRAY(reg, mtwe, sensor_warning, 0x0, 0x10, 1); 9594 9595 /* MTBR - Management Temperature Bulk Register 9596 * ------------------------------------------- 9597 * This register is used for bulk temperature reading. 9598 */ 9599 #define MLXSW_REG_MTBR_ID 0x900F 9600 #define MLXSW_REG_MTBR_BASE_LEN 0x10 /* base length, without records */ 9601 #define MLXSW_REG_MTBR_REC_LEN 0x04 /* record length */ 9602 #define MLXSW_REG_MTBR_REC_MAX_COUNT 47 /* firmware limitation */ 9603 #define MLXSW_REG_MTBR_LEN (MLXSW_REG_MTBR_BASE_LEN + \ 9604 MLXSW_REG_MTBR_REC_LEN * \ 9605 MLXSW_REG_MTBR_REC_MAX_COUNT) 9606 9607 MLXSW_REG_DEFINE(mtbr, MLXSW_REG_MTBR_ID, MLXSW_REG_MTBR_LEN); 9608 9609 /* reg_mtbr_slot_index 9610 * Slot index (0: Main board). 9611 * Access: Index 9612 */ 9613 MLXSW_ITEM32(reg, mtbr, slot_index, 0x00, 16, 4); 9614 9615 /* reg_mtbr_base_sensor_index 9616 * Base sensors index to access (0 - ASIC sensor, 1-63 - ambient sensors, 9617 * 64-127 are mapped to the SFP+/QSFP modules sequentially). 9618 * Access: Index 9619 */ 9620 MLXSW_ITEM32(reg, mtbr, base_sensor_index, 0x00, 0, 12); 9621 9622 /* reg_mtbr_num_rec 9623 * Request: Number of records to read 9624 * Response: Number of records read 9625 * See above description for more details. 9626 * Range 1..255 9627 * Access: RW 9628 */ 9629 MLXSW_ITEM32(reg, mtbr, num_rec, 0x04, 0, 8); 9630 9631 /* reg_mtbr_rec_max_temp 9632 * The highest measured temperature from the sensor. 9633 * When the bit mte is cleared, the field max_temperature is reserved. 9634 * Access: RO 9635 */ 9636 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_max_temp, MLXSW_REG_MTBR_BASE_LEN, 16, 9637 16, MLXSW_REG_MTBR_REC_LEN, 0x00, false); 9638 9639 /* reg_mtbr_rec_temp 9640 * Temperature reading from the sensor. Reading is in 0..125 Celsius 9641 * degrees units. 9642 * Access: RO 9643 */ 9644 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_temp, MLXSW_REG_MTBR_BASE_LEN, 0, 16, 9645 MLXSW_REG_MTBR_REC_LEN, 0x00, false); 9646 9647 static inline void mlxsw_reg_mtbr_pack(char *payload, u8 slot_index, 9648 u16 base_sensor_index, u8 num_rec) 9649 { 9650 MLXSW_REG_ZERO(mtbr, payload); 9651 mlxsw_reg_mtbr_slot_index_set(payload, slot_index); 9652 mlxsw_reg_mtbr_base_sensor_index_set(payload, base_sensor_index); 9653 mlxsw_reg_mtbr_num_rec_set(payload, num_rec); 9654 } 9655 9656 /* Error codes from temperatute reading */ 9657 enum mlxsw_reg_mtbr_temp_status { 9658 MLXSW_REG_MTBR_NO_CONN = 0x8000, 9659 MLXSW_REG_MTBR_NO_TEMP_SENS = 0x8001, 9660 MLXSW_REG_MTBR_INDEX_NA = 0x8002, 9661 MLXSW_REG_MTBR_BAD_SENS_INFO = 0x8003, 9662 }; 9663 9664 /* Base index for reading modules temperature */ 9665 #define MLXSW_REG_MTBR_BASE_MODULE_INDEX 64 9666 9667 static inline void mlxsw_reg_mtbr_temp_unpack(char *payload, int rec_ind, 9668 u16 *p_temp, u16 *p_max_temp) 9669 { 9670 if (p_temp) 9671 *p_temp = mlxsw_reg_mtbr_rec_temp_get(payload, rec_ind); 9672 if (p_max_temp) 9673 *p_max_temp = mlxsw_reg_mtbr_rec_max_temp_get(payload, rec_ind); 9674 } 9675 9676 /* MCIA - Management Cable Info Access 9677 * ----------------------------------- 9678 * MCIA register is used to access the SFP+ and QSFP connector's EPROM. 9679 */ 9680 9681 #define MLXSW_REG_MCIA_ID 0x9014 9682 #define MLXSW_REG_MCIA_LEN 0x40 9683 9684 MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN); 9685 9686 /* reg_mcia_l 9687 * Lock bit. Setting this bit will lock the access to the specific 9688 * cable. Used for updating a full page in a cable EPROM. Any access 9689 * other then subsequence writes will fail while the port is locked. 9690 * Access: RW 9691 */ 9692 MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1); 9693 9694 /* reg_mcia_module 9695 * Module number. 9696 * Access: Index 9697 */ 9698 MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8); 9699 9700 /* reg_mcia_slot_index 9701 * Slot index (0: Main board) 9702 * Access: Index 9703 */ 9704 MLXSW_ITEM32(reg, mcia, slot, 0x00, 12, 4); 9705 9706 enum { 9707 MLXSW_REG_MCIA_STATUS_GOOD = 0, 9708 /* No response from module's EEPROM. */ 9709 MLXSW_REG_MCIA_STATUS_NO_EEPROM_MODULE = 1, 9710 /* Module type not supported by the device. */ 9711 MLXSW_REG_MCIA_STATUS_MODULE_NOT_SUPPORTED = 2, 9712 /* No module present indication. */ 9713 MLXSW_REG_MCIA_STATUS_MODULE_NOT_CONNECTED = 3, 9714 /* Error occurred while trying to access module's EEPROM using I2C. */ 9715 MLXSW_REG_MCIA_STATUS_I2C_ERROR = 9, 9716 /* Module is disabled. */ 9717 MLXSW_REG_MCIA_STATUS_MODULE_DISABLED = 16, 9718 }; 9719 9720 /* reg_mcia_status 9721 * Module status. 9722 * Access: RO 9723 */ 9724 MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8); 9725 9726 /* reg_mcia_i2c_device_address 9727 * I2C device address. 9728 * Access: RW 9729 */ 9730 MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8); 9731 9732 /* reg_mcia_page_number 9733 * Page number. 9734 * Access: RW 9735 */ 9736 MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8); 9737 9738 /* reg_mcia_device_address 9739 * Device address. 9740 * Access: RW 9741 */ 9742 MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16); 9743 9744 /* reg_mcia_bank_number 9745 * Bank number. 9746 * Access: Index 9747 */ 9748 MLXSW_ITEM32(reg, mcia, bank_number, 0x08, 16, 8); 9749 9750 /* reg_mcia_size 9751 * Number of bytes to read/write (up to 48 bytes). 9752 * Access: RW 9753 */ 9754 MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16); 9755 9756 #define MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH 256 9757 #define MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH 128 9758 #define MLXSW_REG_MCIA_EEPROM_SIZE 48 9759 #define MLXSW_REG_MCIA_I2C_ADDR_LOW 0x50 9760 #define MLXSW_REG_MCIA_I2C_ADDR_HIGH 0x51 9761 #define MLXSW_REG_MCIA_PAGE0_LO_OFF 0xa0 9762 #define MLXSW_REG_MCIA_TH_ITEM_SIZE 2 9763 #define MLXSW_REG_MCIA_TH_PAGE_NUM 3 9764 #define MLXSW_REG_MCIA_TH_PAGE_CMIS_NUM 2 9765 #define MLXSW_REG_MCIA_PAGE0_LO 0 9766 #define MLXSW_REG_MCIA_TH_PAGE_OFF 0x80 9767 #define MLXSW_REG_MCIA_EEPROM_CMIS_FLAT_MEMORY BIT(7) 9768 9769 enum mlxsw_reg_mcia_eeprom_module_info_rev_id { 9770 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00, 9771 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01, 9772 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03, 9773 }; 9774 9775 enum mlxsw_reg_mcia_eeprom_module_info_id { 9776 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_SFP = 0x03, 9777 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP = 0x0C, 9778 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D, 9779 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11, 9780 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_DD = 0x18, 9781 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_OSFP = 0x19, 9782 }; 9783 9784 enum mlxsw_reg_mcia_eeprom_module_info { 9785 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID, 9786 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID, 9787 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_TYPE_ID, 9788 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_SIZE, 9789 }; 9790 9791 /* reg_mcia_eeprom 9792 * Bytes to read/write. 9793 * Access: RW 9794 */ 9795 MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_REG_MCIA_EEPROM_SIZE); 9796 9797 /* This is used to access the optional upper pages (1-3) in the QSFP+ 9798 * memory map. Page 1 is available on offset 256 through 383, page 2 - 9799 * on offset 384 through 511, page 3 - on offset 512 through 639. 9800 */ 9801 #define MLXSW_REG_MCIA_PAGE_GET(off) (((off) - \ 9802 MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH) / \ 9803 MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH + 1) 9804 9805 static inline void mlxsw_reg_mcia_pack(char *payload, u8 slot_index, u8 module, 9806 u8 lock, u8 page_number, 9807 u16 device_addr, u8 size, 9808 u8 i2c_device_addr) 9809 { 9810 MLXSW_REG_ZERO(mcia, payload); 9811 mlxsw_reg_mcia_slot_set(payload, slot_index); 9812 mlxsw_reg_mcia_module_set(payload, module); 9813 mlxsw_reg_mcia_l_set(payload, lock); 9814 mlxsw_reg_mcia_page_number_set(payload, page_number); 9815 mlxsw_reg_mcia_device_address_set(payload, device_addr); 9816 mlxsw_reg_mcia_size_set(payload, size); 9817 mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr); 9818 } 9819 9820 /* MPAT - Monitoring Port Analyzer Table 9821 * ------------------------------------- 9822 * MPAT Register is used to query and configure the Switch PortAnalyzer Table. 9823 * For an enabled analyzer, all fields except e (enable) cannot be modified. 9824 */ 9825 #define MLXSW_REG_MPAT_ID 0x901A 9826 #define MLXSW_REG_MPAT_LEN 0x78 9827 9828 MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN); 9829 9830 /* reg_mpat_pa_id 9831 * Port Analyzer ID. 9832 * Access: Index 9833 */ 9834 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4); 9835 9836 /* reg_mpat_session_id 9837 * Mirror Session ID. 9838 * Used for MIRROR_SESSION<i> trap. 9839 * Access: RW 9840 */ 9841 MLXSW_ITEM32(reg, mpat, session_id, 0x00, 24, 4); 9842 9843 /* reg_mpat_system_port 9844 * A unique port identifier for the final destination of the packet. 9845 * Access: RW 9846 */ 9847 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16); 9848 9849 /* reg_mpat_e 9850 * Enable. Indicating the Port Analyzer is enabled. 9851 * Access: RW 9852 */ 9853 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1); 9854 9855 /* reg_mpat_qos 9856 * Quality Of Service Mode. 9857 * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation 9858 * PCP, DEI, DSCP or VL) are configured. 9859 * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the 9860 * same as in the original packet that has triggered the mirroring. For 9861 * SPAN also the pcp,dei are maintained. 9862 * Access: RW 9863 */ 9864 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1); 9865 9866 /* reg_mpat_be 9867 * Best effort mode. Indicates mirroring traffic should not cause packet 9868 * drop or back pressure, but will discard the mirrored packets. Mirrored 9869 * packets will be forwarded on a best effort manner. 9870 * 0: Do not discard mirrored packets 9871 * 1: Discard mirrored packets if causing congestion 9872 * Access: RW 9873 */ 9874 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1); 9875 9876 enum mlxsw_reg_mpat_span_type { 9877 /* Local SPAN Ethernet. 9878 * The original packet is not encapsulated. 9879 */ 9880 MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0, 9881 9882 /* Remote SPAN Ethernet VLAN. 9883 * The packet is forwarded to the monitoring port on the monitoring 9884 * VLAN. 9885 */ 9886 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1, 9887 9888 /* Encapsulated Remote SPAN Ethernet L3 GRE. 9889 * The packet is encapsulated with GRE header. 9890 */ 9891 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3, 9892 }; 9893 9894 /* reg_mpat_span_type 9895 * SPAN type. 9896 * Access: RW 9897 */ 9898 MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4); 9899 9900 /* reg_mpat_pide 9901 * Policer enable. 9902 * Access: RW 9903 */ 9904 MLXSW_ITEM32(reg, mpat, pide, 0x0C, 15, 1); 9905 9906 /* reg_mpat_pid 9907 * Policer ID. 9908 * Access: RW 9909 */ 9910 MLXSW_ITEM32(reg, mpat, pid, 0x0C, 0, 14); 9911 9912 /* Remote SPAN - Ethernet VLAN 9913 * - - - - - - - - - - - - - - 9914 */ 9915 9916 /* reg_mpat_eth_rspan_vid 9917 * Encapsulation header VLAN ID. 9918 * Access: RW 9919 */ 9920 MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12); 9921 9922 /* Encapsulated Remote SPAN - Ethernet L2 9923 * - - - - - - - - - - - - - - - - - - - 9924 */ 9925 9926 enum mlxsw_reg_mpat_eth_rspan_version { 9927 MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15, 9928 }; 9929 9930 /* reg_mpat_eth_rspan_version 9931 * RSPAN mirror header version. 9932 * Access: RW 9933 */ 9934 MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4); 9935 9936 /* reg_mpat_eth_rspan_mac 9937 * Destination MAC address. 9938 * Access: RW 9939 */ 9940 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6); 9941 9942 /* reg_mpat_eth_rspan_tp 9943 * Tag Packet. Indicates whether the mirroring header should be VLAN tagged. 9944 * Access: RW 9945 */ 9946 MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1); 9947 9948 /* Encapsulated Remote SPAN - Ethernet L3 9949 * - - - - - - - - - - - - - - - - - - - 9950 */ 9951 9952 enum mlxsw_reg_mpat_eth_rspan_protocol { 9953 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4, 9954 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6, 9955 }; 9956 9957 /* reg_mpat_eth_rspan_protocol 9958 * SPAN encapsulation protocol. 9959 * Access: RW 9960 */ 9961 MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4); 9962 9963 /* reg_mpat_eth_rspan_ttl 9964 * Encapsulation header Time-to-Live/HopLimit. 9965 * Access: RW 9966 */ 9967 MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8); 9968 9969 /* reg_mpat_eth_rspan_smac 9970 * Source MAC address 9971 * Access: RW 9972 */ 9973 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6); 9974 9975 /* reg_mpat_eth_rspan_dip* 9976 * Destination IP address. The IP version is configured by protocol. 9977 * Access: RW 9978 */ 9979 MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32); 9980 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16); 9981 9982 /* reg_mpat_eth_rspan_sip* 9983 * Source IP address. The IP version is configured by protocol. 9984 * Access: RW 9985 */ 9986 MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32); 9987 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16); 9988 9989 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id, 9990 u16 system_port, bool e, 9991 enum mlxsw_reg_mpat_span_type span_type) 9992 { 9993 MLXSW_REG_ZERO(mpat, payload); 9994 mlxsw_reg_mpat_pa_id_set(payload, pa_id); 9995 mlxsw_reg_mpat_system_port_set(payload, system_port); 9996 mlxsw_reg_mpat_e_set(payload, e); 9997 mlxsw_reg_mpat_qos_set(payload, 1); 9998 mlxsw_reg_mpat_be_set(payload, 1); 9999 mlxsw_reg_mpat_span_type_set(payload, span_type); 10000 } 10001 10002 static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid) 10003 { 10004 mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid); 10005 } 10006 10007 static inline void 10008 mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload, 10009 enum mlxsw_reg_mpat_eth_rspan_version version, 10010 const char *mac, 10011 bool tp) 10012 { 10013 mlxsw_reg_mpat_eth_rspan_version_set(payload, version); 10014 mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac); 10015 mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp); 10016 } 10017 10018 static inline void 10019 mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl, 10020 const char *smac, 10021 u32 sip, u32 dip) 10022 { 10023 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 10024 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 10025 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 10026 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4); 10027 mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip); 10028 mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip); 10029 } 10030 10031 static inline void 10032 mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl, 10033 const char *smac, 10034 struct in6_addr sip, struct in6_addr dip) 10035 { 10036 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 10037 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 10038 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 10039 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6); 10040 mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip); 10041 mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip); 10042 } 10043 10044 /* MPAR - Monitoring Port Analyzer Register 10045 * ---------------------------------------- 10046 * MPAR register is used to query and configure the port analyzer port mirroring 10047 * properties. 10048 */ 10049 #define MLXSW_REG_MPAR_ID 0x901B 10050 #define MLXSW_REG_MPAR_LEN 0x0C 10051 10052 MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN); 10053 10054 /* reg_mpar_local_port 10055 * The local port to mirror the packets from. 10056 * Access: Index 10057 */ 10058 MLXSW_ITEM32_LP(reg, mpar, 0x00, 16, 0x00, 4); 10059 10060 enum mlxsw_reg_mpar_i_e { 10061 MLXSW_REG_MPAR_TYPE_EGRESS, 10062 MLXSW_REG_MPAR_TYPE_INGRESS, 10063 }; 10064 10065 /* reg_mpar_i_e 10066 * Ingress/Egress 10067 * Access: Index 10068 */ 10069 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4); 10070 10071 /* reg_mpar_enable 10072 * Enable mirroring 10073 * By default, port mirroring is disabled for all ports. 10074 * Access: RW 10075 */ 10076 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1); 10077 10078 /* reg_mpar_pa_id 10079 * Port Analyzer ID. 10080 * Access: RW 10081 */ 10082 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4); 10083 10084 #define MLXSW_REG_MPAR_RATE_MAX 3500000000UL 10085 10086 /* reg_mpar_probability_rate 10087 * Sampling rate. 10088 * Valid values are: 1 to 3.5*10^9 10089 * Value of 1 means "sample all". Default is 1. 10090 * Reserved when Spectrum-1. 10091 * Access: RW 10092 */ 10093 MLXSW_ITEM32(reg, mpar, probability_rate, 0x08, 0, 32); 10094 10095 static inline void mlxsw_reg_mpar_pack(char *payload, u16 local_port, 10096 enum mlxsw_reg_mpar_i_e i_e, 10097 bool enable, u8 pa_id, 10098 u32 probability_rate) 10099 { 10100 MLXSW_REG_ZERO(mpar, payload); 10101 mlxsw_reg_mpar_local_port_set(payload, local_port); 10102 mlxsw_reg_mpar_enable_set(payload, enable); 10103 mlxsw_reg_mpar_i_e_set(payload, i_e); 10104 mlxsw_reg_mpar_pa_id_set(payload, pa_id); 10105 mlxsw_reg_mpar_probability_rate_set(payload, probability_rate); 10106 } 10107 10108 /* MGIR - Management General Information Register 10109 * ---------------------------------------------- 10110 * MGIR register allows software to query the hardware and firmware general 10111 * information. 10112 */ 10113 #define MLXSW_REG_MGIR_ID 0x9020 10114 #define MLXSW_REG_MGIR_LEN 0x9C 10115 10116 MLXSW_REG_DEFINE(mgir, MLXSW_REG_MGIR_ID, MLXSW_REG_MGIR_LEN); 10117 10118 /* reg_mgir_hw_info_device_hw_revision 10119 * Access: RO 10120 */ 10121 MLXSW_ITEM32(reg, mgir, hw_info_device_hw_revision, 0x0, 16, 16); 10122 10123 #define MLXSW_REG_MGIR_FW_INFO_PSID_SIZE 16 10124 10125 /* reg_mgir_fw_info_psid 10126 * PSID (ASCII string). 10127 * Access: RO 10128 */ 10129 MLXSW_ITEM_BUF(reg, mgir, fw_info_psid, 0x30, MLXSW_REG_MGIR_FW_INFO_PSID_SIZE); 10130 10131 /* reg_mgir_fw_info_extended_major 10132 * Access: RO 10133 */ 10134 MLXSW_ITEM32(reg, mgir, fw_info_extended_major, 0x44, 0, 32); 10135 10136 /* reg_mgir_fw_info_extended_minor 10137 * Access: RO 10138 */ 10139 MLXSW_ITEM32(reg, mgir, fw_info_extended_minor, 0x48, 0, 32); 10140 10141 /* reg_mgir_fw_info_extended_sub_minor 10142 * Access: RO 10143 */ 10144 MLXSW_ITEM32(reg, mgir, fw_info_extended_sub_minor, 0x4C, 0, 32); 10145 10146 static inline void mlxsw_reg_mgir_pack(char *payload) 10147 { 10148 MLXSW_REG_ZERO(mgir, payload); 10149 } 10150 10151 static inline void 10152 mlxsw_reg_mgir_unpack(char *payload, u32 *hw_rev, char *fw_info_psid, 10153 u32 *fw_major, u32 *fw_minor, u32 *fw_sub_minor) 10154 { 10155 *hw_rev = mlxsw_reg_mgir_hw_info_device_hw_revision_get(payload); 10156 mlxsw_reg_mgir_fw_info_psid_memcpy_from(payload, fw_info_psid); 10157 *fw_major = mlxsw_reg_mgir_fw_info_extended_major_get(payload); 10158 *fw_minor = mlxsw_reg_mgir_fw_info_extended_minor_get(payload); 10159 *fw_sub_minor = mlxsw_reg_mgir_fw_info_extended_sub_minor_get(payload); 10160 } 10161 10162 /* MRSR - Management Reset and Shutdown Register 10163 * --------------------------------------------- 10164 * MRSR register is used to reset or shutdown the switch or 10165 * the entire system (when applicable). 10166 */ 10167 #define MLXSW_REG_MRSR_ID 0x9023 10168 #define MLXSW_REG_MRSR_LEN 0x08 10169 10170 MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN); 10171 10172 /* reg_mrsr_command 10173 * Reset/shutdown command 10174 * 0 - do nothing 10175 * 1 - software reset 10176 * Access: WO 10177 */ 10178 MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4); 10179 10180 static inline void mlxsw_reg_mrsr_pack(char *payload) 10181 { 10182 MLXSW_REG_ZERO(mrsr, payload); 10183 mlxsw_reg_mrsr_command_set(payload, 1); 10184 } 10185 10186 /* MLCR - Management LED Control Register 10187 * -------------------------------------- 10188 * Controls the system LEDs. 10189 */ 10190 #define MLXSW_REG_MLCR_ID 0x902B 10191 #define MLXSW_REG_MLCR_LEN 0x0C 10192 10193 MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN); 10194 10195 /* reg_mlcr_local_port 10196 * Local port number. 10197 * Access: RW 10198 */ 10199 MLXSW_ITEM32_LP(reg, mlcr, 0x00, 16, 0x00, 24); 10200 10201 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF 10202 10203 /* reg_mlcr_beacon_duration 10204 * Duration of the beacon to be active, in seconds. 10205 * 0x0 - Will turn off the beacon. 10206 * 0xFFFF - Will turn on the beacon until explicitly turned off. 10207 * Access: RW 10208 */ 10209 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16); 10210 10211 /* reg_mlcr_beacon_remain 10212 * Remaining duration of the beacon, in seconds. 10213 * 0xFFFF indicates an infinite amount of time. 10214 * Access: RO 10215 */ 10216 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16); 10217 10218 static inline void mlxsw_reg_mlcr_pack(char *payload, u16 local_port, 10219 bool active) 10220 { 10221 MLXSW_REG_ZERO(mlcr, payload); 10222 mlxsw_reg_mlcr_local_port_set(payload, local_port); 10223 mlxsw_reg_mlcr_beacon_duration_set(payload, active ? 10224 MLXSW_REG_MLCR_DURATION_MAX : 0); 10225 } 10226 10227 /* MCION - Management Cable IO and Notifications Register 10228 * ------------------------------------------------------ 10229 * The MCION register is used to query transceiver modules' IO pins and other 10230 * notifications. 10231 */ 10232 #define MLXSW_REG_MCION_ID 0x9052 10233 #define MLXSW_REG_MCION_LEN 0x18 10234 10235 MLXSW_REG_DEFINE(mcion, MLXSW_REG_MCION_ID, MLXSW_REG_MCION_LEN); 10236 10237 /* reg_mcion_module 10238 * Module number. 10239 * Access: Index 10240 */ 10241 MLXSW_ITEM32(reg, mcion, module, 0x00, 16, 8); 10242 10243 /* reg_mcion_slot_index 10244 * Slot index. 10245 * Access: Index 10246 */ 10247 MLXSW_ITEM32(reg, mcion, slot_index, 0x00, 12, 4); 10248 10249 enum { 10250 MLXSW_REG_MCION_MODULE_STATUS_BITS_PRESENT_MASK = BIT(0), 10251 MLXSW_REG_MCION_MODULE_STATUS_BITS_LOW_POWER_MASK = BIT(8), 10252 }; 10253 10254 /* reg_mcion_module_status_bits 10255 * Module IO status as defined by SFF. 10256 * Access: RO 10257 */ 10258 MLXSW_ITEM32(reg, mcion, module_status_bits, 0x04, 0, 16); 10259 10260 static inline void mlxsw_reg_mcion_pack(char *payload, u8 slot_index, u8 module) 10261 { 10262 MLXSW_REG_ZERO(mcion, payload); 10263 mlxsw_reg_mcion_slot_index_set(payload, slot_index); 10264 mlxsw_reg_mcion_module_set(payload, module); 10265 } 10266 10267 /* MTPPS - Management Pulse Per Second Register 10268 * -------------------------------------------- 10269 * This register provides the device PPS capabilities, configure the PPS in and 10270 * out modules and holds the PPS in time stamp. 10271 */ 10272 #define MLXSW_REG_MTPPS_ID 0x9053 10273 #define MLXSW_REG_MTPPS_LEN 0x3C 10274 10275 MLXSW_REG_DEFINE(mtpps, MLXSW_REG_MTPPS_ID, MLXSW_REG_MTPPS_LEN); 10276 10277 /* reg_mtpps_enable 10278 * Enables the PPS functionality the specific pin. 10279 * A boolean variable. 10280 * Access: RW 10281 */ 10282 MLXSW_ITEM32(reg, mtpps, enable, 0x20, 31, 1); 10283 10284 enum mlxsw_reg_mtpps_pin_mode { 10285 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN = 0x2, 10286 }; 10287 10288 /* reg_mtpps_pin_mode 10289 * Pin mode to be used. The mode must comply with the supported modes of the 10290 * requested pin. 10291 * Access: RW 10292 */ 10293 MLXSW_ITEM32(reg, mtpps, pin_mode, 0x20, 8, 4); 10294 10295 #define MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN 7 10296 10297 /* reg_mtpps_pin 10298 * Pin to be configured or queried out of the supported pins. 10299 * Access: Index 10300 */ 10301 MLXSW_ITEM32(reg, mtpps, pin, 0x20, 0, 8); 10302 10303 /* reg_mtpps_time_stamp 10304 * When pin_mode = pps_in, the latched device time when it was triggered from 10305 * the external GPIO pin. 10306 * When pin_mode = pps_out or virtual_pin or pps_out_and_virtual_pin, the target 10307 * time to generate next output signal. 10308 * Time is in units of device clock. 10309 * Access: RW 10310 */ 10311 MLXSW_ITEM64(reg, mtpps, time_stamp, 0x28, 0, 64); 10312 10313 static inline void 10314 mlxsw_reg_mtpps_vpin_pack(char *payload, u64 time_stamp) 10315 { 10316 MLXSW_REG_ZERO(mtpps, payload); 10317 mlxsw_reg_mtpps_pin_set(payload, MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN); 10318 mlxsw_reg_mtpps_pin_mode_set(payload, 10319 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN); 10320 mlxsw_reg_mtpps_enable_set(payload, true); 10321 mlxsw_reg_mtpps_time_stamp_set(payload, time_stamp); 10322 } 10323 10324 /* MTUTC - Management UTC Register 10325 * ------------------------------- 10326 * Configures the HW UTC counter. 10327 */ 10328 #define MLXSW_REG_MTUTC_ID 0x9055 10329 #define MLXSW_REG_MTUTC_LEN 0x1C 10330 10331 MLXSW_REG_DEFINE(mtutc, MLXSW_REG_MTUTC_ID, MLXSW_REG_MTUTC_LEN); 10332 10333 enum mlxsw_reg_mtutc_operation { 10334 MLXSW_REG_MTUTC_OPERATION_SET_TIME_AT_NEXT_SEC = 0, 10335 MLXSW_REG_MTUTC_OPERATION_ADJUST_FREQ = 3, 10336 }; 10337 10338 /* reg_mtutc_operation 10339 * Operation. 10340 * Access: OP 10341 */ 10342 MLXSW_ITEM32(reg, mtutc, operation, 0x00, 0, 4); 10343 10344 /* reg_mtutc_freq_adjustment 10345 * Frequency adjustment: Every PPS the HW frequency will be 10346 * adjusted by this value. Units of HW clock, where HW counts 10347 * 10^9 HW clocks for 1 HW second. 10348 * Access: RW 10349 */ 10350 MLXSW_ITEM32(reg, mtutc, freq_adjustment, 0x04, 0, 32); 10351 10352 /* reg_mtutc_utc_sec 10353 * UTC seconds. 10354 * Access: WO 10355 */ 10356 MLXSW_ITEM32(reg, mtutc, utc_sec, 0x10, 0, 32); 10357 10358 static inline void 10359 mlxsw_reg_mtutc_pack(char *payload, enum mlxsw_reg_mtutc_operation oper, 10360 u32 freq_adj, u32 utc_sec) 10361 { 10362 MLXSW_REG_ZERO(mtutc, payload); 10363 mlxsw_reg_mtutc_operation_set(payload, oper); 10364 mlxsw_reg_mtutc_freq_adjustment_set(payload, freq_adj); 10365 mlxsw_reg_mtutc_utc_sec_set(payload, utc_sec); 10366 } 10367 10368 /* MCQI - Management Component Query Information 10369 * --------------------------------------------- 10370 * This register allows querying information about firmware components. 10371 */ 10372 #define MLXSW_REG_MCQI_ID 0x9061 10373 #define MLXSW_REG_MCQI_BASE_LEN 0x18 10374 #define MLXSW_REG_MCQI_CAP_LEN 0x14 10375 #define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN) 10376 10377 MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN); 10378 10379 /* reg_mcqi_component_index 10380 * Index of the accessed component. 10381 * Access: Index 10382 */ 10383 MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16); 10384 10385 enum mlxfw_reg_mcqi_info_type { 10386 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES, 10387 }; 10388 10389 /* reg_mcqi_info_type 10390 * Component properties set. 10391 * Access: RW 10392 */ 10393 MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5); 10394 10395 /* reg_mcqi_offset 10396 * The requested/returned data offset from the section start, given in bytes. 10397 * Must be DWORD aligned. 10398 * Access: RW 10399 */ 10400 MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32); 10401 10402 /* reg_mcqi_data_size 10403 * The requested/returned data size, given in bytes. If data_size is not DWORD 10404 * aligned, the last bytes are zero padded. 10405 * Access: RW 10406 */ 10407 MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16); 10408 10409 /* reg_mcqi_cap_max_component_size 10410 * Maximum size for this component, given in bytes. 10411 * Access: RO 10412 */ 10413 MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32); 10414 10415 /* reg_mcqi_cap_log_mcda_word_size 10416 * Log 2 of the access word size in bytes. Read and write access must be aligned 10417 * to the word size. Write access must be done for an integer number of words. 10418 * Access: RO 10419 */ 10420 MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4); 10421 10422 /* reg_mcqi_cap_mcda_max_write_size 10423 * Maximal write size for MCDA register 10424 * Access: RO 10425 */ 10426 MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16); 10427 10428 static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index) 10429 { 10430 MLXSW_REG_ZERO(mcqi, payload); 10431 mlxsw_reg_mcqi_component_index_set(payload, component_index); 10432 mlxsw_reg_mcqi_info_type_set(payload, 10433 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES); 10434 mlxsw_reg_mcqi_offset_set(payload, 0); 10435 mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN); 10436 } 10437 10438 static inline void mlxsw_reg_mcqi_unpack(char *payload, 10439 u32 *p_cap_max_component_size, 10440 u8 *p_cap_log_mcda_word_size, 10441 u16 *p_cap_mcda_max_write_size) 10442 { 10443 *p_cap_max_component_size = 10444 mlxsw_reg_mcqi_cap_max_component_size_get(payload); 10445 *p_cap_log_mcda_word_size = 10446 mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload); 10447 *p_cap_mcda_max_write_size = 10448 mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload); 10449 } 10450 10451 /* MCC - Management Component Control 10452 * ---------------------------------- 10453 * Controls the firmware component and updates the FSM. 10454 */ 10455 #define MLXSW_REG_MCC_ID 0x9062 10456 #define MLXSW_REG_MCC_LEN 0x1C 10457 10458 MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN); 10459 10460 enum mlxsw_reg_mcc_instruction { 10461 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01, 10462 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02, 10463 MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03, 10464 MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04, 10465 MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06, 10466 MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08, 10467 }; 10468 10469 /* reg_mcc_instruction 10470 * Command to be executed by the FSM. 10471 * Applicable for write operation only. 10472 * Access: RW 10473 */ 10474 MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8); 10475 10476 /* reg_mcc_component_index 10477 * Index of the accessed component. Applicable only for commands that 10478 * refer to components. Otherwise, this field is reserved. 10479 * Access: Index 10480 */ 10481 MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16); 10482 10483 /* reg_mcc_update_handle 10484 * Token representing the current flow executed by the FSM. 10485 * Access: WO 10486 */ 10487 MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24); 10488 10489 /* reg_mcc_error_code 10490 * Indicates the successful completion of the instruction, or the reason it 10491 * failed 10492 * Access: RO 10493 */ 10494 MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8); 10495 10496 /* reg_mcc_control_state 10497 * Current FSM state 10498 * Access: RO 10499 */ 10500 MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4); 10501 10502 /* reg_mcc_component_size 10503 * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying 10504 * the size may shorten the update time. Value 0x0 means that size is 10505 * unspecified. 10506 * Access: WO 10507 */ 10508 MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32); 10509 10510 static inline void mlxsw_reg_mcc_pack(char *payload, 10511 enum mlxsw_reg_mcc_instruction instr, 10512 u16 component_index, u32 update_handle, 10513 u32 component_size) 10514 { 10515 MLXSW_REG_ZERO(mcc, payload); 10516 mlxsw_reg_mcc_instruction_set(payload, instr); 10517 mlxsw_reg_mcc_component_index_set(payload, component_index); 10518 mlxsw_reg_mcc_update_handle_set(payload, update_handle); 10519 mlxsw_reg_mcc_component_size_set(payload, component_size); 10520 } 10521 10522 static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle, 10523 u8 *p_error_code, u8 *p_control_state) 10524 { 10525 if (p_update_handle) 10526 *p_update_handle = mlxsw_reg_mcc_update_handle_get(payload); 10527 if (p_error_code) 10528 *p_error_code = mlxsw_reg_mcc_error_code_get(payload); 10529 if (p_control_state) 10530 *p_control_state = mlxsw_reg_mcc_control_state_get(payload); 10531 } 10532 10533 /* MCDA - Management Component Data Access 10534 * --------------------------------------- 10535 * This register allows reading and writing a firmware component. 10536 */ 10537 #define MLXSW_REG_MCDA_ID 0x9063 10538 #define MLXSW_REG_MCDA_BASE_LEN 0x10 10539 #define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80 10540 #define MLXSW_REG_MCDA_LEN \ 10541 (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN) 10542 10543 MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN); 10544 10545 /* reg_mcda_update_handle 10546 * Token representing the current flow executed by the FSM. 10547 * Access: RW 10548 */ 10549 MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24); 10550 10551 /* reg_mcda_offset 10552 * Offset of accessed address relative to component start. Accesses must be in 10553 * accordance to log_mcda_word_size in MCQI reg. 10554 * Access: RW 10555 */ 10556 MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32); 10557 10558 /* reg_mcda_size 10559 * Size of the data accessed, given in bytes. 10560 * Access: RW 10561 */ 10562 MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16); 10563 10564 /* reg_mcda_data 10565 * Data block accessed. 10566 * Access: RW 10567 */ 10568 MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false); 10569 10570 static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle, 10571 u32 offset, u16 size, u8 *data) 10572 { 10573 int i; 10574 10575 MLXSW_REG_ZERO(mcda, payload); 10576 mlxsw_reg_mcda_update_handle_set(payload, update_handle); 10577 mlxsw_reg_mcda_offset_set(payload, offset); 10578 mlxsw_reg_mcda_size_set(payload, size); 10579 10580 for (i = 0; i < size / 4; i++) 10581 mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]); 10582 } 10583 10584 /* MPSC - Monitoring Packet Sampling Configuration Register 10585 * -------------------------------------------------------- 10586 * MPSC Register is used to configure the Packet Sampling mechanism. 10587 */ 10588 #define MLXSW_REG_MPSC_ID 0x9080 10589 #define MLXSW_REG_MPSC_LEN 0x1C 10590 10591 MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN); 10592 10593 /* reg_mpsc_local_port 10594 * Local port number 10595 * Not supported for CPU port 10596 * Access: Index 10597 */ 10598 MLXSW_ITEM32_LP(reg, mpsc, 0x00, 16, 0x00, 12); 10599 10600 /* reg_mpsc_e 10601 * Enable sampling on port local_port 10602 * Access: RW 10603 */ 10604 MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1); 10605 10606 #define MLXSW_REG_MPSC_RATE_MAX 3500000000UL 10607 10608 /* reg_mpsc_rate 10609 * Sampling rate = 1 out of rate packets (with randomization around 10610 * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX 10611 * Access: RW 10612 */ 10613 MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32); 10614 10615 static inline void mlxsw_reg_mpsc_pack(char *payload, u16 local_port, bool e, 10616 u32 rate) 10617 { 10618 MLXSW_REG_ZERO(mpsc, payload); 10619 mlxsw_reg_mpsc_local_port_set(payload, local_port); 10620 mlxsw_reg_mpsc_e_set(payload, e); 10621 mlxsw_reg_mpsc_rate_set(payload, rate); 10622 } 10623 10624 /* MGPC - Monitoring General Purpose Counter Set Register 10625 * The MGPC register retrieves and sets the General Purpose Counter Set. 10626 */ 10627 #define MLXSW_REG_MGPC_ID 0x9081 10628 #define MLXSW_REG_MGPC_LEN 0x18 10629 10630 MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN); 10631 10632 /* reg_mgpc_counter_set_type 10633 * Counter set type. 10634 * Access: OP 10635 */ 10636 MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8); 10637 10638 /* reg_mgpc_counter_index 10639 * Counter index. 10640 * Access: Index 10641 */ 10642 MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24); 10643 10644 enum mlxsw_reg_mgpc_opcode { 10645 /* Nop */ 10646 MLXSW_REG_MGPC_OPCODE_NOP = 0x00, 10647 /* Clear counters */ 10648 MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08, 10649 }; 10650 10651 /* reg_mgpc_opcode 10652 * Opcode. 10653 * Access: OP 10654 */ 10655 MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4); 10656 10657 /* reg_mgpc_byte_counter 10658 * Byte counter value. 10659 * Access: RW 10660 */ 10661 MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64); 10662 10663 /* reg_mgpc_packet_counter 10664 * Packet counter value. 10665 * Access: RW 10666 */ 10667 MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64); 10668 10669 static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index, 10670 enum mlxsw_reg_mgpc_opcode opcode, 10671 enum mlxsw_reg_flow_counter_set_type set_type) 10672 { 10673 MLXSW_REG_ZERO(mgpc, payload); 10674 mlxsw_reg_mgpc_counter_index_set(payload, counter_index); 10675 mlxsw_reg_mgpc_counter_set_type_set(payload, set_type); 10676 mlxsw_reg_mgpc_opcode_set(payload, opcode); 10677 } 10678 10679 /* MPRS - Monitoring Parsing State Register 10680 * ---------------------------------------- 10681 * The MPRS register is used for setting up the parsing for hash, 10682 * policy-engine and routing. 10683 */ 10684 #define MLXSW_REG_MPRS_ID 0x9083 10685 #define MLXSW_REG_MPRS_LEN 0x14 10686 10687 MLXSW_REG_DEFINE(mprs, MLXSW_REG_MPRS_ID, MLXSW_REG_MPRS_LEN); 10688 10689 /* reg_mprs_parsing_depth 10690 * Minimum parsing depth. 10691 * Need to enlarge parsing depth according to L3, MPLS, tunnels, ACL 10692 * rules, traps, hash, etc. Default is 96 bytes. Reserved when SwitchX-2. 10693 * Access: RW 10694 */ 10695 MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16); 10696 10697 /* reg_mprs_parsing_en 10698 * Parsing enable. 10699 * Bit 0 - Enable parsing of NVE of types VxLAN, VxLAN-GPE, GENEVE and 10700 * NVGRE. Default is enabled. Reserved when SwitchX-2. 10701 * Access: RW 10702 */ 10703 MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16); 10704 10705 /* reg_mprs_vxlan_udp_dport 10706 * VxLAN UDP destination port. 10707 * Used for identifying VxLAN packets and for dport field in 10708 * encapsulation. Default is 4789. 10709 * Access: RW 10710 */ 10711 MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16); 10712 10713 static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth, 10714 u16 vxlan_udp_dport) 10715 { 10716 MLXSW_REG_ZERO(mprs, payload); 10717 mlxsw_reg_mprs_parsing_depth_set(payload, parsing_depth); 10718 mlxsw_reg_mprs_parsing_en_set(payload, true); 10719 mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport); 10720 } 10721 10722 /* MOGCR - Monitoring Global Configuration Register 10723 * ------------------------------------------------ 10724 */ 10725 #define MLXSW_REG_MOGCR_ID 0x9086 10726 #define MLXSW_REG_MOGCR_LEN 0x20 10727 10728 MLXSW_REG_DEFINE(mogcr, MLXSW_REG_MOGCR_ID, MLXSW_REG_MOGCR_LEN); 10729 10730 /* reg_mogcr_ptp_iftc 10731 * PTP Ingress FIFO Trap Clear 10732 * The PTP_ING_FIFO trap provides MTPPTR with clr according 10733 * to this value. Default 0. 10734 * Reserved when IB switches and when SwitchX/-2, Spectrum-2 10735 * Access: RW 10736 */ 10737 MLXSW_ITEM32(reg, mogcr, ptp_iftc, 0x00, 1, 1); 10738 10739 /* reg_mogcr_ptp_eftc 10740 * PTP Egress FIFO Trap Clear 10741 * The PTP_EGR_FIFO trap provides MTPPTR with clr according 10742 * to this value. Default 0. 10743 * Reserved when IB switches and when SwitchX/-2, Spectrum-2 10744 * Access: RW 10745 */ 10746 MLXSW_ITEM32(reg, mogcr, ptp_eftc, 0x00, 0, 1); 10747 10748 /* reg_mogcr_mirroring_pid_base 10749 * Base policer id for mirroring policers. 10750 * Must have an even value (e.g. 1000, not 1001). 10751 * Reserved when SwitchX/-2, Switch-IB/2, Spectrum-1 and Quantum. 10752 * Access: RW 10753 */ 10754 MLXSW_ITEM32(reg, mogcr, mirroring_pid_base, 0x0C, 0, 14); 10755 10756 /* MPAGR - Monitoring Port Analyzer Global Register 10757 * ------------------------------------------------ 10758 * This register is used for global port analyzer configurations. 10759 * Note: This register is not supported by current FW versions for Spectrum-1. 10760 */ 10761 #define MLXSW_REG_MPAGR_ID 0x9089 10762 #define MLXSW_REG_MPAGR_LEN 0x0C 10763 10764 MLXSW_REG_DEFINE(mpagr, MLXSW_REG_MPAGR_ID, MLXSW_REG_MPAGR_LEN); 10765 10766 enum mlxsw_reg_mpagr_trigger { 10767 MLXSW_REG_MPAGR_TRIGGER_EGRESS, 10768 MLXSW_REG_MPAGR_TRIGGER_INGRESS, 10769 MLXSW_REG_MPAGR_TRIGGER_INGRESS_WRED, 10770 MLXSW_REG_MPAGR_TRIGGER_INGRESS_SHARED_BUFFER, 10771 MLXSW_REG_MPAGR_TRIGGER_INGRESS_ING_CONG, 10772 MLXSW_REG_MPAGR_TRIGGER_INGRESS_EGR_CONG, 10773 MLXSW_REG_MPAGR_TRIGGER_EGRESS_ECN, 10774 MLXSW_REG_MPAGR_TRIGGER_EGRESS_HIGH_LATENCY, 10775 }; 10776 10777 /* reg_mpagr_trigger 10778 * Mirror trigger. 10779 * Access: Index 10780 */ 10781 MLXSW_ITEM32(reg, mpagr, trigger, 0x00, 0, 4); 10782 10783 /* reg_mpagr_pa_id 10784 * Port analyzer ID. 10785 * Access: RW 10786 */ 10787 MLXSW_ITEM32(reg, mpagr, pa_id, 0x04, 0, 4); 10788 10789 #define MLXSW_REG_MPAGR_RATE_MAX 3500000000UL 10790 10791 /* reg_mpagr_probability_rate 10792 * Sampling rate. 10793 * Valid values are: 1 to 3.5*10^9 10794 * Value of 1 means "sample all". Default is 1. 10795 * Access: RW 10796 */ 10797 MLXSW_ITEM32(reg, mpagr, probability_rate, 0x08, 0, 32); 10798 10799 static inline void mlxsw_reg_mpagr_pack(char *payload, 10800 enum mlxsw_reg_mpagr_trigger trigger, 10801 u8 pa_id, u32 probability_rate) 10802 { 10803 MLXSW_REG_ZERO(mpagr, payload); 10804 mlxsw_reg_mpagr_trigger_set(payload, trigger); 10805 mlxsw_reg_mpagr_pa_id_set(payload, pa_id); 10806 mlxsw_reg_mpagr_probability_rate_set(payload, probability_rate); 10807 } 10808 10809 /* MOMTE - Monitoring Mirror Trigger Enable Register 10810 * ------------------------------------------------- 10811 * This register is used to configure the mirror enable for different mirror 10812 * reasons. 10813 */ 10814 #define MLXSW_REG_MOMTE_ID 0x908D 10815 #define MLXSW_REG_MOMTE_LEN 0x10 10816 10817 MLXSW_REG_DEFINE(momte, MLXSW_REG_MOMTE_ID, MLXSW_REG_MOMTE_LEN); 10818 10819 /* reg_momte_local_port 10820 * Local port number. 10821 * Access: Index 10822 */ 10823 MLXSW_ITEM32_LP(reg, momte, 0x00, 16, 0x00, 12); 10824 10825 enum mlxsw_reg_momte_type { 10826 MLXSW_REG_MOMTE_TYPE_WRED = 0x20, 10827 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS = 0x31, 10828 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS_DESCRIPTORS = 0x32, 10829 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_EGRESS_PORT = 0x33, 10830 MLXSW_REG_MOMTE_TYPE_ING_CONG = 0x40, 10831 MLXSW_REG_MOMTE_TYPE_EGR_CONG = 0x50, 10832 MLXSW_REG_MOMTE_TYPE_ECN = 0x60, 10833 MLXSW_REG_MOMTE_TYPE_HIGH_LATENCY = 0x70, 10834 }; 10835 10836 /* reg_momte_type 10837 * Type of mirroring. 10838 * Access: Index 10839 */ 10840 MLXSW_ITEM32(reg, momte, type, 0x04, 0, 8); 10841 10842 /* reg_momte_tclass_en 10843 * TClass/PG mirror enable. Each bit represents corresponding tclass. 10844 * 0: disable (default) 10845 * 1: enable 10846 * Access: RW 10847 */ 10848 MLXSW_ITEM_BIT_ARRAY(reg, momte, tclass_en, 0x08, 0x08, 1); 10849 10850 static inline void mlxsw_reg_momte_pack(char *payload, u16 local_port, 10851 enum mlxsw_reg_momte_type type) 10852 { 10853 MLXSW_REG_ZERO(momte, payload); 10854 mlxsw_reg_momte_local_port_set(payload, local_port); 10855 mlxsw_reg_momte_type_set(payload, type); 10856 } 10857 10858 /* MTPPPC - Time Precision Packet Port Configuration 10859 * ------------------------------------------------- 10860 * This register serves for configuration of which PTP messages should be 10861 * timestamped. This is a global configuration, despite the register name. 10862 * 10863 * Reserved when Spectrum-2. 10864 */ 10865 #define MLXSW_REG_MTPPPC_ID 0x9090 10866 #define MLXSW_REG_MTPPPC_LEN 0x28 10867 10868 MLXSW_REG_DEFINE(mtpppc, MLXSW_REG_MTPPPC_ID, MLXSW_REG_MTPPPC_LEN); 10869 10870 /* reg_mtpppc_ing_timestamp_message_type 10871 * Bitwise vector of PTP message types to timestamp at ingress. 10872 * MessageType field as defined by IEEE 1588 10873 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req) 10874 * Default all 0 10875 * Access: RW 10876 */ 10877 MLXSW_ITEM32(reg, mtpppc, ing_timestamp_message_type, 0x08, 0, 16); 10878 10879 /* reg_mtpppc_egr_timestamp_message_type 10880 * Bitwise vector of PTP message types to timestamp at egress. 10881 * MessageType field as defined by IEEE 1588 10882 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req) 10883 * Default all 0 10884 * Access: RW 10885 */ 10886 MLXSW_ITEM32(reg, mtpppc, egr_timestamp_message_type, 0x0C, 0, 16); 10887 10888 static inline void mlxsw_reg_mtpppc_pack(char *payload, u16 ing, u16 egr) 10889 { 10890 MLXSW_REG_ZERO(mtpppc, payload); 10891 mlxsw_reg_mtpppc_ing_timestamp_message_type_set(payload, ing); 10892 mlxsw_reg_mtpppc_egr_timestamp_message_type_set(payload, egr); 10893 } 10894 10895 /* MTPPTR - Time Precision Packet Timestamping Reading 10896 * --------------------------------------------------- 10897 * The MTPPTR is used for reading the per port PTP timestamp FIFO. 10898 * There is a trap for packets which are latched to the timestamp FIFO, thus the 10899 * SW knows which FIFO to read. Note that packets enter the FIFO before been 10900 * trapped. The sequence number is used to synchronize the timestamp FIFO 10901 * entries and the trapped packets. 10902 * Reserved when Spectrum-2. 10903 */ 10904 10905 #define MLXSW_REG_MTPPTR_ID 0x9091 10906 #define MLXSW_REG_MTPPTR_BASE_LEN 0x10 /* base length, without records */ 10907 #define MLXSW_REG_MTPPTR_REC_LEN 0x10 /* record length */ 10908 #define MLXSW_REG_MTPPTR_REC_MAX_COUNT 4 10909 #define MLXSW_REG_MTPPTR_LEN (MLXSW_REG_MTPPTR_BASE_LEN + \ 10910 MLXSW_REG_MTPPTR_REC_LEN * MLXSW_REG_MTPPTR_REC_MAX_COUNT) 10911 10912 MLXSW_REG_DEFINE(mtpptr, MLXSW_REG_MTPPTR_ID, MLXSW_REG_MTPPTR_LEN); 10913 10914 /* reg_mtpptr_local_port 10915 * Not supported for CPU port. 10916 * Access: Index 10917 */ 10918 MLXSW_ITEM32_LP(reg, mtpptr, 0x00, 16, 0x00, 12); 10919 10920 enum mlxsw_reg_mtpptr_dir { 10921 MLXSW_REG_MTPPTR_DIR_INGRESS, 10922 MLXSW_REG_MTPPTR_DIR_EGRESS, 10923 }; 10924 10925 /* reg_mtpptr_dir 10926 * Direction. 10927 * Access: Index 10928 */ 10929 MLXSW_ITEM32(reg, mtpptr, dir, 0x00, 0, 1); 10930 10931 /* reg_mtpptr_clr 10932 * Clear the records. 10933 * Access: OP 10934 */ 10935 MLXSW_ITEM32(reg, mtpptr, clr, 0x04, 31, 1); 10936 10937 /* reg_mtpptr_num_rec 10938 * Number of valid records in the response 10939 * Range 0.. cap_ptp_timestamp_fifo 10940 * Access: RO 10941 */ 10942 MLXSW_ITEM32(reg, mtpptr, num_rec, 0x08, 0, 4); 10943 10944 /* reg_mtpptr_rec_message_type 10945 * MessageType field as defined by IEEE 1588 Each bit corresponds to a value 10946 * (e.g. Bit0: Sync, Bit1: Delay_Req) 10947 * Access: RO 10948 */ 10949 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_message_type, 10950 MLXSW_REG_MTPPTR_BASE_LEN, 8, 4, 10951 MLXSW_REG_MTPPTR_REC_LEN, 0, false); 10952 10953 /* reg_mtpptr_rec_domain_number 10954 * DomainNumber field as defined by IEEE 1588 10955 * Access: RO 10956 */ 10957 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_domain_number, 10958 MLXSW_REG_MTPPTR_BASE_LEN, 0, 8, 10959 MLXSW_REG_MTPPTR_REC_LEN, 0, false); 10960 10961 /* reg_mtpptr_rec_sequence_id 10962 * SequenceId field as defined by IEEE 1588 10963 * Access: RO 10964 */ 10965 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_sequence_id, 10966 MLXSW_REG_MTPPTR_BASE_LEN, 0, 16, 10967 MLXSW_REG_MTPPTR_REC_LEN, 0x4, false); 10968 10969 /* reg_mtpptr_rec_timestamp_high 10970 * Timestamp of when the PTP packet has passed through the port Units of PLL 10971 * clock time. 10972 * For Spectrum-1 the PLL clock is 156.25Mhz and PLL clock time is 6.4nSec. 10973 * Access: RO 10974 */ 10975 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_high, 10976 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32, 10977 MLXSW_REG_MTPPTR_REC_LEN, 0x8, false); 10978 10979 /* reg_mtpptr_rec_timestamp_low 10980 * See rec_timestamp_high. 10981 * Access: RO 10982 */ 10983 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_low, 10984 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32, 10985 MLXSW_REG_MTPPTR_REC_LEN, 0xC, false); 10986 10987 static inline void mlxsw_reg_mtpptr_unpack(const char *payload, 10988 unsigned int rec, 10989 u8 *p_message_type, 10990 u8 *p_domain_number, 10991 u16 *p_sequence_id, 10992 u64 *p_timestamp) 10993 { 10994 u32 timestamp_high, timestamp_low; 10995 10996 *p_message_type = mlxsw_reg_mtpptr_rec_message_type_get(payload, rec); 10997 *p_domain_number = mlxsw_reg_mtpptr_rec_domain_number_get(payload, rec); 10998 *p_sequence_id = mlxsw_reg_mtpptr_rec_sequence_id_get(payload, rec); 10999 timestamp_high = mlxsw_reg_mtpptr_rec_timestamp_high_get(payload, rec); 11000 timestamp_low = mlxsw_reg_mtpptr_rec_timestamp_low_get(payload, rec); 11001 *p_timestamp = (u64)timestamp_high << 32 | timestamp_low; 11002 } 11003 11004 /* MTPTPT - Monitoring Precision Time Protocol Trap Register 11005 * --------------------------------------------------------- 11006 * This register is used for configuring under which trap to deliver PTP 11007 * packets depending on type of the packet. 11008 */ 11009 #define MLXSW_REG_MTPTPT_ID 0x9092 11010 #define MLXSW_REG_MTPTPT_LEN 0x08 11011 11012 MLXSW_REG_DEFINE(mtptpt, MLXSW_REG_MTPTPT_ID, MLXSW_REG_MTPTPT_LEN); 11013 11014 enum mlxsw_reg_mtptpt_trap_id { 11015 MLXSW_REG_MTPTPT_TRAP_ID_PTP0, 11016 MLXSW_REG_MTPTPT_TRAP_ID_PTP1, 11017 }; 11018 11019 /* reg_mtptpt_trap_id 11020 * Trap id. 11021 * Access: Index 11022 */ 11023 MLXSW_ITEM32(reg, mtptpt, trap_id, 0x00, 0, 4); 11024 11025 /* reg_mtptpt_message_type 11026 * Bitwise vector of PTP message types to trap. This is a necessary but 11027 * non-sufficient condition since need to enable also per port. See MTPPPC. 11028 * Message types are defined by IEEE 1588 Each bit corresponds to a value (e.g. 11029 * Bit0: Sync, Bit1: Delay_Req) 11030 */ 11031 MLXSW_ITEM32(reg, mtptpt, message_type, 0x04, 0, 16); 11032 11033 static inline void mlxsw_reg_mtptptp_pack(char *payload, 11034 enum mlxsw_reg_mtptpt_trap_id trap_id, 11035 u16 message_type) 11036 { 11037 MLXSW_REG_ZERO(mtptpt, payload); 11038 mlxsw_reg_mtptpt_trap_id_set(payload, trap_id); 11039 mlxsw_reg_mtptpt_message_type_set(payload, message_type); 11040 } 11041 11042 /* MFGD - Monitoring FW General Debug Register 11043 * ------------------------------------------- 11044 */ 11045 #define MLXSW_REG_MFGD_ID 0x90F0 11046 #define MLXSW_REG_MFGD_LEN 0x0C 11047 11048 MLXSW_REG_DEFINE(mfgd, MLXSW_REG_MFGD_ID, MLXSW_REG_MFGD_LEN); 11049 11050 /* reg_mfgd_fw_fatal_event_mode 11051 * 0 - don't check FW fatal (default) 11052 * 1 - check FW fatal - enable MFDE trap 11053 * Access: RW 11054 */ 11055 MLXSW_ITEM32(reg, mfgd, fatal_event_mode, 0x00, 9, 2); 11056 11057 /* reg_mfgd_trigger_test 11058 * Access: WO 11059 */ 11060 MLXSW_ITEM32(reg, mfgd, trigger_test, 0x00, 11, 1); 11061 11062 /* MGPIR - Management General Peripheral Information Register 11063 * ---------------------------------------------------------- 11064 * MGPIR register allows software to query the hardware and 11065 * firmware general information of peripheral entities. 11066 */ 11067 #define MLXSW_REG_MGPIR_ID 0x9100 11068 #define MLXSW_REG_MGPIR_LEN 0xA0 11069 11070 MLXSW_REG_DEFINE(mgpir, MLXSW_REG_MGPIR_ID, MLXSW_REG_MGPIR_LEN); 11071 11072 enum mlxsw_reg_mgpir_device_type { 11073 MLXSW_REG_MGPIR_DEVICE_TYPE_NONE, 11074 MLXSW_REG_MGPIR_DEVICE_TYPE_GEARBOX_DIE, 11075 }; 11076 11077 /* mgpir_slot_index 11078 * Slot index (0: Main board). 11079 * Access: Index 11080 */ 11081 MLXSW_ITEM32(reg, mgpir, slot_index, 0x00, 28, 4); 11082 11083 /* mgpir_device_type 11084 * Access: RO 11085 */ 11086 MLXSW_ITEM32(reg, mgpir, device_type, 0x00, 24, 4); 11087 11088 /* mgpir_devices_per_flash 11089 * Number of devices of device_type per flash (can be shared by few devices). 11090 * Access: RO 11091 */ 11092 MLXSW_ITEM32(reg, mgpir, devices_per_flash, 0x00, 16, 8); 11093 11094 /* mgpir_num_of_devices 11095 * Number of devices of device_type. 11096 * Access: RO 11097 */ 11098 MLXSW_ITEM32(reg, mgpir, num_of_devices, 0x00, 0, 8); 11099 11100 /* max_modules_per_slot 11101 * Maximum number of modules that can be connected per slot. 11102 * Access: RO 11103 */ 11104 MLXSW_ITEM32(reg, mgpir, max_modules_per_slot, 0x04, 16, 8); 11105 11106 /* mgpir_num_of_slots 11107 * Number of slots in the system. 11108 * Access: RO 11109 */ 11110 MLXSW_ITEM32(reg, mgpir, num_of_slots, 0x04, 8, 8); 11111 11112 /* mgpir_num_of_modules 11113 * Number of modules. 11114 * Access: RO 11115 */ 11116 MLXSW_ITEM32(reg, mgpir, num_of_modules, 0x04, 0, 8); 11117 11118 static inline void mlxsw_reg_mgpir_pack(char *payload, u8 slot_index) 11119 { 11120 MLXSW_REG_ZERO(mgpir, payload); 11121 mlxsw_reg_mgpir_slot_index_set(payload, slot_index); 11122 } 11123 11124 static inline void 11125 mlxsw_reg_mgpir_unpack(char *payload, u8 *num_of_devices, 11126 enum mlxsw_reg_mgpir_device_type *device_type, 11127 u8 *devices_per_flash, u8 *num_of_modules, 11128 u8 *num_of_slots) 11129 { 11130 if (num_of_devices) 11131 *num_of_devices = mlxsw_reg_mgpir_num_of_devices_get(payload); 11132 if (device_type) 11133 *device_type = mlxsw_reg_mgpir_device_type_get(payload); 11134 if (devices_per_flash) 11135 *devices_per_flash = 11136 mlxsw_reg_mgpir_devices_per_flash_get(payload); 11137 if (num_of_modules) 11138 *num_of_modules = mlxsw_reg_mgpir_num_of_modules_get(payload); 11139 if (num_of_slots) 11140 *num_of_slots = mlxsw_reg_mgpir_num_of_slots_get(payload); 11141 } 11142 11143 /* MBCT - Management Binary Code Transfer Register 11144 * ----------------------------------------------- 11145 * This register allows to transfer binary codes from the host to 11146 * the management FW by transferring it by chunks of maximum 1KB. 11147 */ 11148 #define MLXSW_REG_MBCT_ID 0x9120 11149 #define MLXSW_REG_MBCT_LEN 0x420 11150 11151 MLXSW_REG_DEFINE(mbct, MLXSW_REG_MBCT_ID, MLXSW_REG_MBCT_LEN); 11152 11153 /* reg_mbct_slot_index 11154 * Slot index. 0 is reserved. 11155 * Access: Index 11156 */ 11157 MLXSW_ITEM32(reg, mbct, slot_index, 0x00, 0, 4); 11158 11159 /* reg_mbct_data_size 11160 * Actual data field size in bytes for the current data transfer. 11161 * Access: WO 11162 */ 11163 MLXSW_ITEM32(reg, mbct, data_size, 0x04, 0, 11); 11164 11165 enum mlxsw_reg_mbct_op { 11166 MLXSW_REG_MBCT_OP_ERASE_INI_IMAGE = 1, 11167 MLXSW_REG_MBCT_OP_DATA_TRANSFER, /* Download */ 11168 MLXSW_REG_MBCT_OP_ACTIVATE, 11169 MLXSW_REG_MBCT_OP_CLEAR_ERRORS = 6, 11170 MLXSW_REG_MBCT_OP_QUERY_STATUS, 11171 }; 11172 11173 /* reg_mbct_op 11174 * Access: WO 11175 */ 11176 MLXSW_ITEM32(reg, mbct, op, 0x08, 28, 4); 11177 11178 /* reg_mbct_last 11179 * Indicates that the current data field is the last chunk of the INI. 11180 * Access: WO 11181 */ 11182 MLXSW_ITEM32(reg, mbct, last, 0x08, 26, 1); 11183 11184 /* reg_mbct_oee 11185 * Opcode Event Enable. When set a BCTOE event will be sent once the opcode 11186 * was executed and the fsm_state has changed. 11187 * Access: WO 11188 */ 11189 MLXSW_ITEM32(reg, mbct, oee, 0x08, 25, 1); 11190 11191 enum mlxsw_reg_mbct_status { 11192 /* Partial data transfer completed successfully and ready for next 11193 * data transfer. 11194 */ 11195 MLXSW_REG_MBCT_STATUS_PART_DATA = 2, 11196 MLXSW_REG_MBCT_STATUS_LAST_DATA, 11197 MLXSW_REG_MBCT_STATUS_ERASE_COMPLETE, 11198 /* Error - trying to erase INI while it being used. */ 11199 MLXSW_REG_MBCT_STATUS_ERROR_INI_IN_USE, 11200 /* Last data transfer completed, applying magic pattern. */ 11201 MLXSW_REG_MBCT_STATUS_ERASE_FAILED = 7, 11202 MLXSW_REG_MBCT_STATUS_INI_ERROR, 11203 MLXSW_REG_MBCT_STATUS_ACTIVATION_FAILED, 11204 MLXSW_REG_MBCT_STATUS_ILLEGAL_OPERATION = 11, 11205 }; 11206 11207 /* reg_mbct_status 11208 * Status. 11209 * Access: RO 11210 */ 11211 MLXSW_ITEM32(reg, mbct, status, 0x0C, 24, 5); 11212 11213 enum mlxsw_reg_mbct_fsm_state { 11214 MLXSW_REG_MBCT_FSM_STATE_INI_IN_USE = 5, 11215 MLXSW_REG_MBCT_FSM_STATE_ERROR, 11216 }; 11217 11218 /* reg_mbct_fsm_state 11219 * FSM state. 11220 * Access: RO 11221 */ 11222 MLXSW_ITEM32(reg, mbct, fsm_state, 0x0C, 16, 4); 11223 11224 #define MLXSW_REG_MBCT_DATA_LEN 1024 11225 11226 /* reg_mbct_data 11227 * Up to 1KB of data. 11228 * Access: WO 11229 */ 11230 MLXSW_ITEM_BUF(reg, mbct, data, 0x20, MLXSW_REG_MBCT_DATA_LEN); 11231 11232 static inline void mlxsw_reg_mbct_pack(char *payload, u8 slot_index, 11233 enum mlxsw_reg_mbct_op op, bool oee) 11234 { 11235 MLXSW_REG_ZERO(mbct, payload); 11236 mlxsw_reg_mbct_slot_index_set(payload, slot_index); 11237 mlxsw_reg_mbct_op_set(payload, op); 11238 mlxsw_reg_mbct_oee_set(payload, oee); 11239 } 11240 11241 static inline void mlxsw_reg_mbct_dt_pack(char *payload, 11242 u16 data_size, bool last, 11243 const char *data) 11244 { 11245 if (WARN_ON(data_size > MLXSW_REG_MBCT_DATA_LEN)) 11246 return; 11247 mlxsw_reg_mbct_data_size_set(payload, data_size); 11248 mlxsw_reg_mbct_last_set(payload, last); 11249 mlxsw_reg_mbct_data_memcpy_to(payload, data); 11250 } 11251 11252 static inline void 11253 mlxsw_reg_mbct_unpack(const char *payload, u8 *p_slot_index, 11254 enum mlxsw_reg_mbct_status *p_status, 11255 enum mlxsw_reg_mbct_fsm_state *p_fsm_state) 11256 { 11257 if (p_slot_index) 11258 *p_slot_index = mlxsw_reg_mbct_slot_index_get(payload); 11259 *p_status = mlxsw_reg_mbct_status_get(payload); 11260 if (p_fsm_state) 11261 *p_fsm_state = mlxsw_reg_mbct_fsm_state_get(payload); 11262 } 11263 11264 /* MDDQ - Management DownStream Device Query Register 11265 * -------------------------------------------------- 11266 * This register allows to query the DownStream device properties. The desired 11267 * information is chosen upon the query_type field and is delivered by 32B 11268 * of data blocks. 11269 */ 11270 #define MLXSW_REG_MDDQ_ID 0x9161 11271 #define MLXSW_REG_MDDQ_LEN 0x30 11272 11273 MLXSW_REG_DEFINE(mddq, MLXSW_REG_MDDQ_ID, MLXSW_REG_MDDQ_LEN); 11274 11275 /* reg_mddq_sie 11276 * Slot info event enable. 11277 * When set to '1', each change in the slot_info.provisioned / sr_valid / 11278 * active / ready will generate a DSDSC event. 11279 * Access: RW 11280 */ 11281 MLXSW_ITEM32(reg, mddq, sie, 0x00, 31, 1); 11282 11283 enum mlxsw_reg_mddq_query_type { 11284 MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_INFO = 1, 11285 MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_NAME = 3, 11286 }; 11287 11288 /* reg_mddq_query_type 11289 * Access: Index 11290 */ 11291 MLXSW_ITEM32(reg, mddq, query_type, 0x00, 16, 8); 11292 11293 /* reg_mddq_slot_index 11294 * Slot index. 0 is reserved. 11295 * Access: Index 11296 */ 11297 MLXSW_ITEM32(reg, mddq, slot_index, 0x00, 0, 4); 11298 11299 /* reg_mddq_slot_info_provisioned 11300 * If set, the INI file is applied and the card is provisioned. 11301 * Access: RO 11302 */ 11303 MLXSW_ITEM32(reg, mddq, slot_info_provisioned, 0x10, 31, 1); 11304 11305 /* reg_mddq_slot_info_sr_valid 11306 * If set, Shift Register is valid (after being provisioned) and data 11307 * can be sent from the switch ASIC to the line-card CPLD over Shift-Register. 11308 * Access: RO 11309 */ 11310 MLXSW_ITEM32(reg, mddq, slot_info_sr_valid, 0x10, 30, 1); 11311 11312 enum mlxsw_reg_mddq_slot_info_ready { 11313 MLXSW_REG_MDDQ_SLOT_INFO_READY_NOT_READY, 11314 MLXSW_REG_MDDQ_SLOT_INFO_READY_READY, 11315 MLXSW_REG_MDDQ_SLOT_INFO_READY_ERROR, 11316 }; 11317 11318 /* reg_mddq_slot_info_lc_ready 11319 * If set, the LC is powered on, matching the INI version and a new FW 11320 * version can be burnt (if necessary). 11321 * Access: RO 11322 */ 11323 MLXSW_ITEM32(reg, mddq, slot_info_lc_ready, 0x10, 28, 2); 11324 11325 /* reg_mddq_slot_info_active 11326 * If set, the FW has completed the MDDC.device_enable command. 11327 * Access: RO 11328 */ 11329 MLXSW_ITEM32(reg, mddq, slot_info_active, 0x10, 27, 1); 11330 11331 /* reg_mddq_slot_info_hw_revision 11332 * Major user-configured version number of the current INI file. 11333 * Valid only when active or ready are '1'. 11334 * Access: RO 11335 */ 11336 MLXSW_ITEM32(reg, mddq, slot_info_hw_revision, 0x14, 16, 16); 11337 11338 /* reg_mddq_slot_info_ini_file_version 11339 * User-configured version number of the current INI file. 11340 * Valid only when active or lc_ready are '1'. 11341 * Access: RO 11342 */ 11343 MLXSW_ITEM32(reg, mddq, slot_info_ini_file_version, 0x14, 0, 16); 11344 11345 /* reg_mddq_slot_info_card_type 11346 * Access: RO 11347 */ 11348 MLXSW_ITEM32(reg, mddq, slot_info_card_type, 0x18, 0, 8); 11349 11350 static inline void 11351 __mlxsw_reg_mddq_pack(char *payload, u8 slot_index, 11352 enum mlxsw_reg_mddq_query_type query_type) 11353 { 11354 MLXSW_REG_ZERO(mddq, payload); 11355 mlxsw_reg_mddq_slot_index_set(payload, slot_index); 11356 mlxsw_reg_mddq_query_type_set(payload, query_type); 11357 } 11358 11359 static inline void 11360 mlxsw_reg_mddq_slot_info_pack(char *payload, u8 slot_index, bool sie) 11361 { 11362 __mlxsw_reg_mddq_pack(payload, slot_index, 11363 MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_INFO); 11364 mlxsw_reg_mddq_sie_set(payload, sie); 11365 } 11366 11367 static inline void 11368 mlxsw_reg_mddq_slot_info_unpack(const char *payload, u8 *p_slot_index, 11369 bool *p_provisioned, bool *p_sr_valid, 11370 enum mlxsw_reg_mddq_slot_info_ready *p_lc_ready, 11371 bool *p_active, u16 *p_hw_revision, 11372 u16 *p_ini_file_version, 11373 u8 *p_card_type) 11374 { 11375 *p_slot_index = mlxsw_reg_mddq_slot_index_get(payload); 11376 *p_provisioned = mlxsw_reg_mddq_slot_info_provisioned_get(payload); 11377 *p_sr_valid = mlxsw_reg_mddq_slot_info_sr_valid_get(payload); 11378 *p_lc_ready = mlxsw_reg_mddq_slot_info_lc_ready_get(payload); 11379 *p_active = mlxsw_reg_mddq_slot_info_active_get(payload); 11380 *p_hw_revision = mlxsw_reg_mddq_slot_info_hw_revision_get(payload); 11381 *p_ini_file_version = mlxsw_reg_mddq_slot_info_ini_file_version_get(payload); 11382 *p_card_type = mlxsw_reg_mddq_slot_info_card_type_get(payload); 11383 } 11384 11385 #define MLXSW_REG_MDDQ_SLOT_ASCII_NAME_LEN 20 11386 11387 /* reg_mddq_slot_ascii_name 11388 * Slot's ASCII name. 11389 * Access: RO 11390 */ 11391 MLXSW_ITEM_BUF(reg, mddq, slot_ascii_name, 0x10, 11392 MLXSW_REG_MDDQ_SLOT_ASCII_NAME_LEN); 11393 11394 static inline void 11395 mlxsw_reg_mddq_slot_name_pack(char *payload, u8 slot_index) 11396 { 11397 __mlxsw_reg_mddq_pack(payload, slot_index, 11398 MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_NAME); 11399 } 11400 11401 static inline void 11402 mlxsw_reg_mddq_slot_name_unpack(const char *payload, char *slot_ascii_name) 11403 { 11404 mlxsw_reg_mddq_slot_ascii_name_memcpy_from(payload, slot_ascii_name); 11405 } 11406 11407 /* MDDC - Management DownStream Device Control Register 11408 * ---------------------------------------------------- 11409 * This register allows to control downstream devices and line cards. 11410 */ 11411 #define MLXSW_REG_MDDC_ID 0x9163 11412 #define MLXSW_REG_MDDC_LEN 0x30 11413 11414 MLXSW_REG_DEFINE(mddc, MLXSW_REG_MDDC_ID, MLXSW_REG_MDDC_LEN); 11415 11416 /* reg_mddc_slot_index 11417 * Slot index. 0 is reserved. 11418 * Access: Index 11419 */ 11420 MLXSW_ITEM32(reg, mddc, slot_index, 0x00, 0, 4); 11421 11422 /* reg_mddc_rst 11423 * Reset request. 11424 * Access: OP 11425 */ 11426 MLXSW_ITEM32(reg, mddc, rst, 0x04, 29, 1); 11427 11428 /* reg_mddc_device_enable 11429 * When set, FW is the manager and allowed to program the downstream device. 11430 * Access: RW 11431 */ 11432 MLXSW_ITEM32(reg, mddc, device_enable, 0x04, 28, 1); 11433 11434 static inline void mlxsw_reg_mddc_pack(char *payload, u8 slot_index, bool rst, 11435 bool device_enable) 11436 { 11437 MLXSW_REG_ZERO(mddc, payload); 11438 mlxsw_reg_mddc_slot_index_set(payload, slot_index); 11439 mlxsw_reg_mddc_rst_set(payload, rst); 11440 mlxsw_reg_mddc_device_enable_set(payload, device_enable); 11441 } 11442 11443 /* MFDE - Monitoring FW Debug Register 11444 * ----------------------------------- 11445 */ 11446 #define MLXSW_REG_MFDE_ID 0x9200 11447 #define MLXSW_REG_MFDE_LEN 0x30 11448 11449 MLXSW_REG_DEFINE(mfde, MLXSW_REG_MFDE_ID, MLXSW_REG_MFDE_LEN); 11450 11451 /* reg_mfde_irisc_id 11452 * Which irisc triggered the event 11453 * Access: RO 11454 */ 11455 MLXSW_ITEM32(reg, mfde, irisc_id, 0x00, 24, 8); 11456 11457 enum mlxsw_reg_mfde_severity { 11458 /* Unrecoverable switch behavior */ 11459 MLXSW_REG_MFDE_SEVERITY_FATL = 2, 11460 /* Unexpected state with possible systemic failure */ 11461 MLXSW_REG_MFDE_SEVERITY_NRML = 3, 11462 /* Unexpected state without systemic failure */ 11463 MLXSW_REG_MFDE_SEVERITY_INTR = 5, 11464 }; 11465 11466 /* reg_mfde_severity 11467 * The severity of the event. 11468 * Access: RO 11469 */ 11470 MLXSW_ITEM32(reg, mfde, severity, 0x00, 16, 8); 11471 11472 enum mlxsw_reg_mfde_event_id { 11473 /* CRspace timeout */ 11474 MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO = 1, 11475 /* KVD insertion machine stopped */ 11476 MLXSW_REG_MFDE_EVENT_ID_KVD_IM_STOP, 11477 /* Triggered by MFGD.trigger_test */ 11478 MLXSW_REG_MFDE_EVENT_ID_TEST, 11479 /* Triggered when firmware hits an assert */ 11480 MLXSW_REG_MFDE_EVENT_ID_FW_ASSERT, 11481 /* Fatal error interrupt from hardware */ 11482 MLXSW_REG_MFDE_EVENT_ID_FATAL_CAUSE, 11483 }; 11484 11485 /* reg_mfde_event_id 11486 * Access: RO 11487 */ 11488 MLXSW_ITEM32(reg, mfde, event_id, 0x00, 0, 16); 11489 11490 enum mlxsw_reg_mfde_method { 11491 MLXSW_REG_MFDE_METHOD_QUERY, 11492 MLXSW_REG_MFDE_METHOD_WRITE, 11493 }; 11494 11495 /* reg_mfde_method 11496 * Access: RO 11497 */ 11498 MLXSW_ITEM32(reg, mfde, method, 0x04, 29, 1); 11499 11500 /* reg_mfde_long_process 11501 * Indicates if the command is in long_process mode. 11502 * Access: RO 11503 */ 11504 MLXSW_ITEM32(reg, mfde, long_process, 0x04, 28, 1); 11505 11506 enum mlxsw_reg_mfde_command_type { 11507 MLXSW_REG_MFDE_COMMAND_TYPE_MAD, 11508 MLXSW_REG_MFDE_COMMAND_TYPE_EMAD, 11509 MLXSW_REG_MFDE_COMMAND_TYPE_CMDIF, 11510 }; 11511 11512 /* reg_mfde_command_type 11513 * Access: RO 11514 */ 11515 MLXSW_ITEM32(reg, mfde, command_type, 0x04, 24, 2); 11516 11517 /* reg_mfde_reg_attr_id 11518 * EMAD - register id, MAD - attibute id 11519 * Access: RO 11520 */ 11521 MLXSW_ITEM32(reg, mfde, reg_attr_id, 0x04, 0, 16); 11522 11523 /* reg_mfde_crspace_to_log_address 11524 * crspace address accessed, which resulted in timeout. 11525 * Access: RO 11526 */ 11527 MLXSW_ITEM32(reg, mfde, crspace_to_log_address, 0x10, 0, 32); 11528 11529 /* reg_mfde_crspace_to_oe 11530 * 0 - New event 11531 * 1 - Old event, occurred before MFGD activation. 11532 * Access: RO 11533 */ 11534 MLXSW_ITEM32(reg, mfde, crspace_to_oe, 0x14, 24, 1); 11535 11536 /* reg_mfde_crspace_to_log_id 11537 * Which irisc triggered the timeout. 11538 * Access: RO 11539 */ 11540 MLXSW_ITEM32(reg, mfde, crspace_to_log_id, 0x14, 0, 4); 11541 11542 /* reg_mfde_crspace_to_log_ip 11543 * IP (instruction pointer) that triggered the timeout. 11544 * Access: RO 11545 */ 11546 MLXSW_ITEM64(reg, mfde, crspace_to_log_ip, 0x18, 0, 64); 11547 11548 /* reg_mfde_kvd_im_stop_oe 11549 * 0 - New event 11550 * 1 - Old event, occurred before MFGD activation. 11551 * Access: RO 11552 */ 11553 MLXSW_ITEM32(reg, mfde, kvd_im_stop_oe, 0x10, 24, 1); 11554 11555 /* reg_mfde_kvd_im_stop_pipes_mask 11556 * Bit per kvh pipe. 11557 * Access: RO 11558 */ 11559 MLXSW_ITEM32(reg, mfde, kvd_im_stop_pipes_mask, 0x10, 0, 16); 11560 11561 /* reg_mfde_fw_assert_var0-4 11562 * Variables passed to assert. 11563 * Access: RO 11564 */ 11565 MLXSW_ITEM32(reg, mfde, fw_assert_var0, 0x10, 0, 32); 11566 MLXSW_ITEM32(reg, mfde, fw_assert_var1, 0x14, 0, 32); 11567 MLXSW_ITEM32(reg, mfde, fw_assert_var2, 0x18, 0, 32); 11568 MLXSW_ITEM32(reg, mfde, fw_assert_var3, 0x1C, 0, 32); 11569 MLXSW_ITEM32(reg, mfde, fw_assert_var4, 0x20, 0, 32); 11570 11571 /* reg_mfde_fw_assert_existptr 11572 * The instruction pointer when assert was triggered. 11573 * Access: RO 11574 */ 11575 MLXSW_ITEM32(reg, mfde, fw_assert_existptr, 0x24, 0, 32); 11576 11577 /* reg_mfde_fw_assert_callra 11578 * The return address after triggering assert. 11579 * Access: RO 11580 */ 11581 MLXSW_ITEM32(reg, mfde, fw_assert_callra, 0x28, 0, 32); 11582 11583 /* reg_mfde_fw_assert_oe 11584 * 0 - New event 11585 * 1 - Old event, occurred before MFGD activation. 11586 * Access: RO 11587 */ 11588 MLXSW_ITEM32(reg, mfde, fw_assert_oe, 0x2C, 24, 1); 11589 11590 /* reg_mfde_fw_assert_tile_v 11591 * 0: The assert was from main 11592 * 1: The assert was from a tile 11593 * Access: RO 11594 */ 11595 MLXSW_ITEM32(reg, mfde, fw_assert_tile_v, 0x2C, 23, 1); 11596 11597 /* reg_mfde_fw_assert_tile_index 11598 * When tile_v=1, the tile_index that caused the assert. 11599 * Access: RO 11600 */ 11601 MLXSW_ITEM32(reg, mfde, fw_assert_tile_index, 0x2C, 16, 6); 11602 11603 /* reg_mfde_fw_assert_ext_synd 11604 * A generated one-to-one identifier which is specific per-assert. 11605 * Access: RO 11606 */ 11607 MLXSW_ITEM32(reg, mfde, fw_assert_ext_synd, 0x2C, 0, 16); 11608 11609 /* reg_mfde_fatal_cause_id 11610 * HW interrupt cause id. 11611 * Access: RO 11612 */ 11613 MLXSW_ITEM32(reg, mfde, fatal_cause_id, 0x10, 0, 18); 11614 11615 /* reg_mfde_fatal_cause_tile_v 11616 * 0: The assert was from main 11617 * 1: The assert was from a tile 11618 * Access: RO 11619 */ 11620 MLXSW_ITEM32(reg, mfde, fatal_cause_tile_v, 0x14, 23, 1); 11621 11622 /* reg_mfde_fatal_cause_tile_index 11623 * When tile_v=1, the tile_index that caused the assert. 11624 * Access: RO 11625 */ 11626 MLXSW_ITEM32(reg, mfde, fatal_cause_tile_index, 0x14, 16, 6); 11627 11628 /* TNGCR - Tunneling NVE General Configuration Register 11629 * ---------------------------------------------------- 11630 * The TNGCR register is used for setting up the NVE Tunneling configuration. 11631 */ 11632 #define MLXSW_REG_TNGCR_ID 0xA001 11633 #define MLXSW_REG_TNGCR_LEN 0x44 11634 11635 MLXSW_REG_DEFINE(tngcr, MLXSW_REG_TNGCR_ID, MLXSW_REG_TNGCR_LEN); 11636 11637 enum mlxsw_reg_tngcr_type { 11638 MLXSW_REG_TNGCR_TYPE_VXLAN, 11639 MLXSW_REG_TNGCR_TYPE_VXLAN_GPE, 11640 MLXSW_REG_TNGCR_TYPE_GENEVE, 11641 MLXSW_REG_TNGCR_TYPE_NVGRE, 11642 }; 11643 11644 /* reg_tngcr_type 11645 * Tunnel type for encapsulation and decapsulation. The types are mutually 11646 * exclusive. 11647 * Note: For Spectrum the NVE parsing must be enabled in MPRS. 11648 * Access: RW 11649 */ 11650 MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4); 11651 11652 /* reg_tngcr_nve_valid 11653 * The VTEP is valid. Allows adding FDB entries for tunnel encapsulation. 11654 * Access: RW 11655 */ 11656 MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1); 11657 11658 /* reg_tngcr_nve_ttl_uc 11659 * The TTL for NVE tunnel encapsulation underlay unicast packets. 11660 * Access: RW 11661 */ 11662 MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8); 11663 11664 /* reg_tngcr_nve_ttl_mc 11665 * The TTL for NVE tunnel encapsulation underlay multicast packets. 11666 * Access: RW 11667 */ 11668 MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8); 11669 11670 enum { 11671 /* Do not copy flow label. Calculate flow label using nve_flh. */ 11672 MLXSW_REG_TNGCR_FL_NO_COPY, 11673 /* Copy flow label from inner packet if packet is IPv6 and 11674 * encapsulation is by IPv6. Otherwise, calculate flow label using 11675 * nve_flh. 11676 */ 11677 MLXSW_REG_TNGCR_FL_COPY, 11678 }; 11679 11680 /* reg_tngcr_nve_flc 11681 * For NVE tunnel encapsulation: Flow label copy from inner packet. 11682 * Access: RW 11683 */ 11684 MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1); 11685 11686 enum { 11687 /* Flow label is static. In Spectrum this means '0'. Spectrum-2 11688 * uses {nve_fl_prefix, nve_fl_suffix}. 11689 */ 11690 MLXSW_REG_TNGCR_FL_NO_HASH, 11691 /* 8 LSBs of the flow label are calculated from ECMP hash of the 11692 * inner packet. 12 MSBs are configured by nve_fl_prefix. 11693 */ 11694 MLXSW_REG_TNGCR_FL_HASH, 11695 }; 11696 11697 /* reg_tngcr_nve_flh 11698 * NVE flow label hash. 11699 * Access: RW 11700 */ 11701 MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1); 11702 11703 /* reg_tngcr_nve_fl_prefix 11704 * NVE flow label prefix. Constant 12 MSBs of the flow label. 11705 * Access: RW 11706 */ 11707 MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12); 11708 11709 /* reg_tngcr_nve_fl_suffix 11710 * NVE flow label suffix. Constant 8 LSBs of the flow label. 11711 * Reserved when nve_flh=1 and for Spectrum. 11712 * Access: RW 11713 */ 11714 MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8); 11715 11716 enum { 11717 /* Source UDP port is fixed (default '0') */ 11718 MLXSW_REG_TNGCR_UDP_SPORT_NO_HASH, 11719 /* Source UDP port is calculated based on hash */ 11720 MLXSW_REG_TNGCR_UDP_SPORT_HASH, 11721 }; 11722 11723 /* reg_tngcr_nve_udp_sport_type 11724 * NVE UDP source port type. 11725 * Spectrum uses LAG hash (SLCRv2). Spectrum-2 uses ECMP hash (RECRv2). 11726 * When the source UDP port is calculated based on hash, then the 8 LSBs 11727 * are calculated from hash the 8 MSBs are configured by 11728 * nve_udp_sport_prefix. 11729 * Access: RW 11730 */ 11731 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1); 11732 11733 /* reg_tngcr_nve_udp_sport_prefix 11734 * NVE UDP source port prefix. Constant 8 MSBs of the UDP source port. 11735 * Reserved when NVE type is NVGRE. 11736 * Access: RW 11737 */ 11738 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8); 11739 11740 /* reg_tngcr_nve_group_size_mc 11741 * The amount of sequential linked lists of MC entries. The first linked 11742 * list is configured by SFD.underlay_mc_ptr. 11743 * Valid values: 1, 2, 4, 8, 16, 32, 64 11744 * The linked list are configured by TNUMT. 11745 * The hash is set by LAG hash. 11746 * Access: RW 11747 */ 11748 MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8); 11749 11750 /* reg_tngcr_nve_group_size_flood 11751 * The amount of sequential linked lists of flooding entries. The first 11752 * linked list is configured by SFMR.nve_tunnel_flood_ptr 11753 * Valid values: 1, 2, 4, 8, 16, 32, 64 11754 * The linked list are configured by TNUMT. 11755 * The hash is set by LAG hash. 11756 * Access: RW 11757 */ 11758 MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8); 11759 11760 /* reg_tngcr_learn_enable 11761 * During decapsulation, whether to learn from NVE port. 11762 * Reserved when Spectrum-2. See TNPC. 11763 * Access: RW 11764 */ 11765 MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1); 11766 11767 /* reg_tngcr_underlay_virtual_router 11768 * Underlay virtual router. 11769 * Reserved when Spectrum-2. 11770 * Access: RW 11771 */ 11772 MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16); 11773 11774 /* reg_tngcr_underlay_rif 11775 * Underlay ingress router interface. RIF type should be loopback generic. 11776 * Reserved when Spectrum. 11777 * Access: RW 11778 */ 11779 MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16); 11780 11781 /* reg_tngcr_usipv4 11782 * Underlay source IPv4 address of the NVE. 11783 * Access: RW 11784 */ 11785 MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32); 11786 11787 /* reg_tngcr_usipv6 11788 * Underlay source IPv6 address of the NVE. For Spectrum, must not be 11789 * modified under traffic of NVE tunneling encapsulation. 11790 * Access: RW 11791 */ 11792 MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16); 11793 11794 static inline void mlxsw_reg_tngcr_pack(char *payload, 11795 enum mlxsw_reg_tngcr_type type, 11796 bool valid, u8 ttl) 11797 { 11798 MLXSW_REG_ZERO(tngcr, payload); 11799 mlxsw_reg_tngcr_type_set(payload, type); 11800 mlxsw_reg_tngcr_nve_valid_set(payload, valid); 11801 mlxsw_reg_tngcr_nve_ttl_uc_set(payload, ttl); 11802 mlxsw_reg_tngcr_nve_ttl_mc_set(payload, ttl); 11803 mlxsw_reg_tngcr_nve_flc_set(payload, MLXSW_REG_TNGCR_FL_NO_COPY); 11804 mlxsw_reg_tngcr_nve_flh_set(payload, 0); 11805 mlxsw_reg_tngcr_nve_udp_sport_type_set(payload, 11806 MLXSW_REG_TNGCR_UDP_SPORT_HASH); 11807 mlxsw_reg_tngcr_nve_udp_sport_prefix_set(payload, 0); 11808 mlxsw_reg_tngcr_nve_group_size_mc_set(payload, 1); 11809 mlxsw_reg_tngcr_nve_group_size_flood_set(payload, 1); 11810 } 11811 11812 /* TNUMT - Tunneling NVE Underlay Multicast Table Register 11813 * ------------------------------------------------------- 11814 * The TNUMT register is for building the underlay MC table. It is used 11815 * for MC, flooding and BC traffic into the NVE tunnel. 11816 */ 11817 #define MLXSW_REG_TNUMT_ID 0xA003 11818 #define MLXSW_REG_TNUMT_LEN 0x20 11819 11820 MLXSW_REG_DEFINE(tnumt, MLXSW_REG_TNUMT_ID, MLXSW_REG_TNUMT_LEN); 11821 11822 enum mlxsw_reg_tnumt_record_type { 11823 MLXSW_REG_TNUMT_RECORD_TYPE_IPV4, 11824 MLXSW_REG_TNUMT_RECORD_TYPE_IPV6, 11825 MLXSW_REG_TNUMT_RECORD_TYPE_LABEL, 11826 }; 11827 11828 /* reg_tnumt_record_type 11829 * Record type. 11830 * Access: RW 11831 */ 11832 MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4); 11833 11834 /* reg_tnumt_tunnel_port 11835 * Tunnel port. 11836 * Access: RW 11837 */ 11838 MLXSW_ITEM32(reg, tnumt, tunnel_port, 0x00, 24, 4); 11839 11840 /* reg_tnumt_underlay_mc_ptr 11841 * Index to the underlay multicast table. 11842 * For Spectrum the index is to the KVD linear. 11843 * Access: Index 11844 */ 11845 MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24); 11846 11847 /* reg_tnumt_vnext 11848 * The next_underlay_mc_ptr is valid. 11849 * Access: RW 11850 */ 11851 MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1); 11852 11853 /* reg_tnumt_next_underlay_mc_ptr 11854 * The next index to the underlay multicast table. 11855 * Access: RW 11856 */ 11857 MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24); 11858 11859 /* reg_tnumt_record_size 11860 * Number of IP addresses in the record. 11861 * Range is 1..cap_max_nve_mc_entries_ipv{4,6} 11862 * Access: RW 11863 */ 11864 MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3); 11865 11866 /* reg_tnumt_udip 11867 * The underlay IPv4 addresses. udip[i] is reserved if i >= size 11868 * Access: RW 11869 */ 11870 MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false); 11871 11872 /* reg_tnumt_udip_ptr 11873 * The pointer to the underlay IPv6 addresses. udip_ptr[i] is reserved if 11874 * i >= size. The IPv6 addresses are configured by RIPS. 11875 * Access: RW 11876 */ 11877 MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false); 11878 11879 static inline void mlxsw_reg_tnumt_pack(char *payload, 11880 enum mlxsw_reg_tnumt_record_type type, 11881 enum mlxsw_reg_tunnel_port tport, 11882 u32 underlay_mc_ptr, bool vnext, 11883 u32 next_underlay_mc_ptr, 11884 u8 record_size) 11885 { 11886 MLXSW_REG_ZERO(tnumt, payload); 11887 mlxsw_reg_tnumt_record_type_set(payload, type); 11888 mlxsw_reg_tnumt_tunnel_port_set(payload, tport); 11889 mlxsw_reg_tnumt_underlay_mc_ptr_set(payload, underlay_mc_ptr); 11890 mlxsw_reg_tnumt_vnext_set(payload, vnext); 11891 mlxsw_reg_tnumt_next_underlay_mc_ptr_set(payload, next_underlay_mc_ptr); 11892 mlxsw_reg_tnumt_record_size_set(payload, record_size); 11893 } 11894 11895 /* TNQCR - Tunneling NVE QoS Configuration Register 11896 * ------------------------------------------------ 11897 * The TNQCR register configures how QoS is set in encapsulation into the 11898 * underlay network. 11899 */ 11900 #define MLXSW_REG_TNQCR_ID 0xA010 11901 #define MLXSW_REG_TNQCR_LEN 0x0C 11902 11903 MLXSW_REG_DEFINE(tnqcr, MLXSW_REG_TNQCR_ID, MLXSW_REG_TNQCR_LEN); 11904 11905 /* reg_tnqcr_enc_set_dscp 11906 * For encapsulation: How to set DSCP field: 11907 * 0 - Copy the DSCP from the overlay (inner) IP header to the underlay 11908 * (outer) IP header. If there is no IP header, use TNQDR.dscp 11909 * 1 - Set the DSCP field as TNQDR.dscp 11910 * Access: RW 11911 */ 11912 MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1); 11913 11914 static inline void mlxsw_reg_tnqcr_pack(char *payload) 11915 { 11916 MLXSW_REG_ZERO(tnqcr, payload); 11917 mlxsw_reg_tnqcr_enc_set_dscp_set(payload, 0); 11918 } 11919 11920 /* TNQDR - Tunneling NVE QoS Default Register 11921 * ------------------------------------------ 11922 * The TNQDR register configures the default QoS settings for NVE 11923 * encapsulation. 11924 */ 11925 #define MLXSW_REG_TNQDR_ID 0xA011 11926 #define MLXSW_REG_TNQDR_LEN 0x08 11927 11928 MLXSW_REG_DEFINE(tnqdr, MLXSW_REG_TNQDR_ID, MLXSW_REG_TNQDR_LEN); 11929 11930 /* reg_tnqdr_local_port 11931 * Local port number (receive port). CPU port is supported. 11932 * Access: Index 11933 */ 11934 MLXSW_ITEM32_LP(reg, tnqdr, 0x00, 16, 0x00, 12); 11935 11936 /* reg_tnqdr_dscp 11937 * For encapsulation, the default DSCP. 11938 * Access: RW 11939 */ 11940 MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6); 11941 11942 static inline void mlxsw_reg_tnqdr_pack(char *payload, u16 local_port) 11943 { 11944 MLXSW_REG_ZERO(tnqdr, payload); 11945 mlxsw_reg_tnqdr_local_port_set(payload, local_port); 11946 mlxsw_reg_tnqdr_dscp_set(payload, 0); 11947 } 11948 11949 /* TNEEM - Tunneling NVE Encapsulation ECN Mapping Register 11950 * -------------------------------------------------------- 11951 * The TNEEM register maps ECN of the IP header at the ingress to the 11952 * encapsulation to the ECN of the underlay network. 11953 */ 11954 #define MLXSW_REG_TNEEM_ID 0xA012 11955 #define MLXSW_REG_TNEEM_LEN 0x0C 11956 11957 MLXSW_REG_DEFINE(tneem, MLXSW_REG_TNEEM_ID, MLXSW_REG_TNEEM_LEN); 11958 11959 /* reg_tneem_overlay_ecn 11960 * ECN of the IP header in the overlay network. 11961 * Access: Index 11962 */ 11963 MLXSW_ITEM32(reg, tneem, overlay_ecn, 0x04, 24, 2); 11964 11965 /* reg_tneem_underlay_ecn 11966 * ECN of the IP header in the underlay network. 11967 * Access: RW 11968 */ 11969 MLXSW_ITEM32(reg, tneem, underlay_ecn, 0x04, 16, 2); 11970 11971 static inline void mlxsw_reg_tneem_pack(char *payload, u8 overlay_ecn, 11972 u8 underlay_ecn) 11973 { 11974 MLXSW_REG_ZERO(tneem, payload); 11975 mlxsw_reg_tneem_overlay_ecn_set(payload, overlay_ecn); 11976 mlxsw_reg_tneem_underlay_ecn_set(payload, underlay_ecn); 11977 } 11978 11979 /* TNDEM - Tunneling NVE Decapsulation ECN Mapping Register 11980 * -------------------------------------------------------- 11981 * The TNDEM register configures the actions that are done in the 11982 * decapsulation. 11983 */ 11984 #define MLXSW_REG_TNDEM_ID 0xA013 11985 #define MLXSW_REG_TNDEM_LEN 0x0C 11986 11987 MLXSW_REG_DEFINE(tndem, MLXSW_REG_TNDEM_ID, MLXSW_REG_TNDEM_LEN); 11988 11989 /* reg_tndem_underlay_ecn 11990 * ECN field of the IP header in the underlay network. 11991 * Access: Index 11992 */ 11993 MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2); 11994 11995 /* reg_tndem_overlay_ecn 11996 * ECN field of the IP header in the overlay network. 11997 * Access: Index 11998 */ 11999 MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2); 12000 12001 /* reg_tndem_eip_ecn 12002 * Egress IP ECN. ECN field of the IP header of the packet which goes out 12003 * from the decapsulation. 12004 * Access: RW 12005 */ 12006 MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2); 12007 12008 /* reg_tndem_trap_en 12009 * Trap enable: 12010 * 0 - No trap due to decap ECN 12011 * 1 - Trap enable with trap_id 12012 * Access: RW 12013 */ 12014 MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4); 12015 12016 /* reg_tndem_trap_id 12017 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 12018 * Reserved when trap_en is '0'. 12019 * Access: RW 12020 */ 12021 MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9); 12022 12023 static inline void mlxsw_reg_tndem_pack(char *payload, u8 underlay_ecn, 12024 u8 overlay_ecn, u8 ecn, bool trap_en, 12025 u16 trap_id) 12026 { 12027 MLXSW_REG_ZERO(tndem, payload); 12028 mlxsw_reg_tndem_underlay_ecn_set(payload, underlay_ecn); 12029 mlxsw_reg_tndem_overlay_ecn_set(payload, overlay_ecn); 12030 mlxsw_reg_tndem_eip_ecn_set(payload, ecn); 12031 mlxsw_reg_tndem_trap_en_set(payload, trap_en); 12032 mlxsw_reg_tndem_trap_id_set(payload, trap_id); 12033 } 12034 12035 /* TNPC - Tunnel Port Configuration Register 12036 * ----------------------------------------- 12037 * The TNPC register is used for tunnel port configuration. 12038 * Reserved when Spectrum. 12039 */ 12040 #define MLXSW_REG_TNPC_ID 0xA020 12041 #define MLXSW_REG_TNPC_LEN 0x18 12042 12043 MLXSW_REG_DEFINE(tnpc, MLXSW_REG_TNPC_ID, MLXSW_REG_TNPC_LEN); 12044 12045 /* reg_tnpc_tunnel_port 12046 * Tunnel port. 12047 * Access: Index 12048 */ 12049 MLXSW_ITEM32(reg, tnpc, tunnel_port, 0x00, 0, 4); 12050 12051 /* reg_tnpc_learn_enable_v6 12052 * During IPv6 underlay decapsulation, whether to learn from tunnel port. 12053 * Access: RW 12054 */ 12055 MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1); 12056 12057 /* reg_tnpc_learn_enable_v4 12058 * During IPv4 underlay decapsulation, whether to learn from tunnel port. 12059 * Access: RW 12060 */ 12061 MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1); 12062 12063 static inline void mlxsw_reg_tnpc_pack(char *payload, 12064 enum mlxsw_reg_tunnel_port tport, 12065 bool learn_enable) 12066 { 12067 MLXSW_REG_ZERO(tnpc, payload); 12068 mlxsw_reg_tnpc_tunnel_port_set(payload, tport); 12069 mlxsw_reg_tnpc_learn_enable_v4_set(payload, learn_enable); 12070 mlxsw_reg_tnpc_learn_enable_v6_set(payload, learn_enable); 12071 } 12072 12073 /* TIGCR - Tunneling IPinIP General Configuration Register 12074 * ------------------------------------------------------- 12075 * The TIGCR register is used for setting up the IPinIP Tunnel configuration. 12076 */ 12077 #define MLXSW_REG_TIGCR_ID 0xA801 12078 #define MLXSW_REG_TIGCR_LEN 0x10 12079 12080 MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN); 12081 12082 /* reg_tigcr_ipip_ttlc 12083 * For IPinIP Tunnel encapsulation: whether to copy the ttl from the packet 12084 * header. 12085 * Access: RW 12086 */ 12087 MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1); 12088 12089 /* reg_tigcr_ipip_ttl_uc 12090 * The TTL for IPinIP Tunnel encapsulation of unicast packets if 12091 * reg_tigcr_ipip_ttlc is unset. 12092 * Access: RW 12093 */ 12094 MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8); 12095 12096 static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc) 12097 { 12098 MLXSW_REG_ZERO(tigcr, payload); 12099 mlxsw_reg_tigcr_ttlc_set(payload, ttlc); 12100 mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc); 12101 } 12102 12103 /* TIEEM - Tunneling IPinIP Encapsulation ECN Mapping Register 12104 * ----------------------------------------------------------- 12105 * The TIEEM register maps ECN of the IP header at the ingress to the 12106 * encapsulation to the ECN of the underlay network. 12107 */ 12108 #define MLXSW_REG_TIEEM_ID 0xA812 12109 #define MLXSW_REG_TIEEM_LEN 0x0C 12110 12111 MLXSW_REG_DEFINE(tieem, MLXSW_REG_TIEEM_ID, MLXSW_REG_TIEEM_LEN); 12112 12113 /* reg_tieem_overlay_ecn 12114 * ECN of the IP header in the overlay network. 12115 * Access: Index 12116 */ 12117 MLXSW_ITEM32(reg, tieem, overlay_ecn, 0x04, 24, 2); 12118 12119 /* reg_tineem_underlay_ecn 12120 * ECN of the IP header in the underlay network. 12121 * Access: RW 12122 */ 12123 MLXSW_ITEM32(reg, tieem, underlay_ecn, 0x04, 16, 2); 12124 12125 static inline void mlxsw_reg_tieem_pack(char *payload, u8 overlay_ecn, 12126 u8 underlay_ecn) 12127 { 12128 MLXSW_REG_ZERO(tieem, payload); 12129 mlxsw_reg_tieem_overlay_ecn_set(payload, overlay_ecn); 12130 mlxsw_reg_tieem_underlay_ecn_set(payload, underlay_ecn); 12131 } 12132 12133 /* TIDEM - Tunneling IPinIP Decapsulation ECN Mapping Register 12134 * ----------------------------------------------------------- 12135 * The TIDEM register configures the actions that are done in the 12136 * decapsulation. 12137 */ 12138 #define MLXSW_REG_TIDEM_ID 0xA813 12139 #define MLXSW_REG_TIDEM_LEN 0x0C 12140 12141 MLXSW_REG_DEFINE(tidem, MLXSW_REG_TIDEM_ID, MLXSW_REG_TIDEM_LEN); 12142 12143 /* reg_tidem_underlay_ecn 12144 * ECN field of the IP header in the underlay network. 12145 * Access: Index 12146 */ 12147 MLXSW_ITEM32(reg, tidem, underlay_ecn, 0x04, 24, 2); 12148 12149 /* reg_tidem_overlay_ecn 12150 * ECN field of the IP header in the overlay network. 12151 * Access: Index 12152 */ 12153 MLXSW_ITEM32(reg, tidem, overlay_ecn, 0x04, 16, 2); 12154 12155 /* reg_tidem_eip_ecn 12156 * Egress IP ECN. ECN field of the IP header of the packet which goes out 12157 * from the decapsulation. 12158 * Access: RW 12159 */ 12160 MLXSW_ITEM32(reg, tidem, eip_ecn, 0x04, 8, 2); 12161 12162 /* reg_tidem_trap_en 12163 * Trap enable: 12164 * 0 - No trap due to decap ECN 12165 * 1 - Trap enable with trap_id 12166 * Access: RW 12167 */ 12168 MLXSW_ITEM32(reg, tidem, trap_en, 0x08, 28, 4); 12169 12170 /* reg_tidem_trap_id 12171 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 12172 * Reserved when trap_en is '0'. 12173 * Access: RW 12174 */ 12175 MLXSW_ITEM32(reg, tidem, trap_id, 0x08, 0, 9); 12176 12177 static inline void mlxsw_reg_tidem_pack(char *payload, u8 underlay_ecn, 12178 u8 overlay_ecn, u8 eip_ecn, 12179 bool trap_en, u16 trap_id) 12180 { 12181 MLXSW_REG_ZERO(tidem, payload); 12182 mlxsw_reg_tidem_underlay_ecn_set(payload, underlay_ecn); 12183 mlxsw_reg_tidem_overlay_ecn_set(payload, overlay_ecn); 12184 mlxsw_reg_tidem_eip_ecn_set(payload, eip_ecn); 12185 mlxsw_reg_tidem_trap_en_set(payload, trap_en); 12186 mlxsw_reg_tidem_trap_id_set(payload, trap_id); 12187 } 12188 12189 /* SBPR - Shared Buffer Pools Register 12190 * ----------------------------------- 12191 * The SBPR configures and retrieves the shared buffer pools and configuration. 12192 */ 12193 #define MLXSW_REG_SBPR_ID 0xB001 12194 #define MLXSW_REG_SBPR_LEN 0x14 12195 12196 MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN); 12197 12198 /* reg_sbpr_desc 12199 * When set, configures descriptor buffer. 12200 * Access: Index 12201 */ 12202 MLXSW_ITEM32(reg, sbpr, desc, 0x00, 31, 1); 12203 12204 /* shared direstion enum for SBPR, SBCM, SBPM */ 12205 enum mlxsw_reg_sbxx_dir { 12206 MLXSW_REG_SBXX_DIR_INGRESS, 12207 MLXSW_REG_SBXX_DIR_EGRESS, 12208 }; 12209 12210 /* reg_sbpr_dir 12211 * Direction. 12212 * Access: Index 12213 */ 12214 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2); 12215 12216 /* reg_sbpr_pool 12217 * Pool index. 12218 * Access: Index 12219 */ 12220 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4); 12221 12222 /* reg_sbpr_infi_size 12223 * Size is infinite. 12224 * Access: RW 12225 */ 12226 MLXSW_ITEM32(reg, sbpr, infi_size, 0x04, 31, 1); 12227 12228 /* reg_sbpr_size 12229 * Pool size in buffer cells. 12230 * Reserved when infi_size = 1. 12231 * Access: RW 12232 */ 12233 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24); 12234 12235 enum mlxsw_reg_sbpr_mode { 12236 MLXSW_REG_SBPR_MODE_STATIC, 12237 MLXSW_REG_SBPR_MODE_DYNAMIC, 12238 }; 12239 12240 /* reg_sbpr_mode 12241 * Pool quota calculation mode. 12242 * Access: RW 12243 */ 12244 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4); 12245 12246 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool, 12247 enum mlxsw_reg_sbxx_dir dir, 12248 enum mlxsw_reg_sbpr_mode mode, u32 size, 12249 bool infi_size) 12250 { 12251 MLXSW_REG_ZERO(sbpr, payload); 12252 mlxsw_reg_sbpr_pool_set(payload, pool); 12253 mlxsw_reg_sbpr_dir_set(payload, dir); 12254 mlxsw_reg_sbpr_mode_set(payload, mode); 12255 mlxsw_reg_sbpr_size_set(payload, size); 12256 mlxsw_reg_sbpr_infi_size_set(payload, infi_size); 12257 } 12258 12259 /* SBCM - Shared Buffer Class Management Register 12260 * ---------------------------------------------- 12261 * The SBCM register configures and retrieves the shared buffer allocation 12262 * and configuration according to Port-PG, including the binding to pool 12263 * and definition of the associated quota. 12264 */ 12265 #define MLXSW_REG_SBCM_ID 0xB002 12266 #define MLXSW_REG_SBCM_LEN 0x28 12267 12268 MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN); 12269 12270 /* reg_sbcm_local_port 12271 * Local port number. 12272 * For Ingress: excludes CPU port and Router port 12273 * For Egress: excludes IP Router 12274 * Access: Index 12275 */ 12276 MLXSW_ITEM32_LP(reg, sbcm, 0x00, 16, 0x00, 4); 12277 12278 /* reg_sbcm_pg_buff 12279 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress) 12280 * For PG buffer: range is 0..cap_max_pg_buffers - 1 12281 * For traffic class: range is 0..cap_max_tclass - 1 12282 * Note that when traffic class is in MC aware mode then the traffic 12283 * classes which are MC aware cannot be configured. 12284 * Access: Index 12285 */ 12286 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6); 12287 12288 /* reg_sbcm_dir 12289 * Direction. 12290 * Access: Index 12291 */ 12292 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2); 12293 12294 /* reg_sbcm_min_buff 12295 * Minimum buffer size for the limiter, in cells. 12296 * Access: RW 12297 */ 12298 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24); 12299 12300 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */ 12301 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1 12302 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14 12303 12304 /* reg_sbcm_infi_max 12305 * Max buffer is infinite. 12306 * Access: RW 12307 */ 12308 MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1); 12309 12310 /* reg_sbcm_max_buff 12311 * When the pool associated to the port-pg/tclass is configured to 12312 * static, Maximum buffer size for the limiter configured in cells. 12313 * When the pool associated to the port-pg/tclass is configured to 12314 * dynamic, the max_buff holds the "alpha" parameter, supporting 12315 * the following values: 12316 * 0: 0 12317 * i: (1/128)*2^(i-1), for i=1..14 12318 * 0xFF: Infinity 12319 * Reserved when infi_max = 1. 12320 * Access: RW 12321 */ 12322 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24); 12323 12324 /* reg_sbcm_pool 12325 * Association of the port-priority to a pool. 12326 * Access: RW 12327 */ 12328 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4); 12329 12330 static inline void mlxsw_reg_sbcm_pack(char *payload, u16 local_port, u8 pg_buff, 12331 enum mlxsw_reg_sbxx_dir dir, 12332 u32 min_buff, u32 max_buff, 12333 bool infi_max, u8 pool) 12334 { 12335 MLXSW_REG_ZERO(sbcm, payload); 12336 mlxsw_reg_sbcm_local_port_set(payload, local_port); 12337 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff); 12338 mlxsw_reg_sbcm_dir_set(payload, dir); 12339 mlxsw_reg_sbcm_min_buff_set(payload, min_buff); 12340 mlxsw_reg_sbcm_max_buff_set(payload, max_buff); 12341 mlxsw_reg_sbcm_infi_max_set(payload, infi_max); 12342 mlxsw_reg_sbcm_pool_set(payload, pool); 12343 } 12344 12345 /* SBPM - Shared Buffer Port Management Register 12346 * --------------------------------------------- 12347 * The SBPM register configures and retrieves the shared buffer allocation 12348 * and configuration according to Port-Pool, including the definition 12349 * of the associated quota. 12350 */ 12351 #define MLXSW_REG_SBPM_ID 0xB003 12352 #define MLXSW_REG_SBPM_LEN 0x28 12353 12354 MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN); 12355 12356 /* reg_sbpm_local_port 12357 * Local port number. 12358 * For Ingress: excludes CPU port and Router port 12359 * For Egress: excludes IP Router 12360 * Access: Index 12361 */ 12362 MLXSW_ITEM32_LP(reg, sbpm, 0x00, 16, 0x00, 12); 12363 12364 /* reg_sbpm_pool 12365 * The pool associated to quota counting on the local_port. 12366 * Access: Index 12367 */ 12368 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4); 12369 12370 /* reg_sbpm_dir 12371 * Direction. 12372 * Access: Index 12373 */ 12374 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2); 12375 12376 /* reg_sbpm_buff_occupancy 12377 * Current buffer occupancy in cells. 12378 * Access: RO 12379 */ 12380 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24); 12381 12382 /* reg_sbpm_clr 12383 * Clear Max Buffer Occupancy 12384 * When this bit is set, max_buff_occupancy field is cleared (and a 12385 * new max value is tracked from the time the clear was performed). 12386 * Access: OP 12387 */ 12388 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1); 12389 12390 /* reg_sbpm_max_buff_occupancy 12391 * Maximum value of buffer occupancy in cells monitored. Cleared by 12392 * writing to the clr field. 12393 * Access: RO 12394 */ 12395 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24); 12396 12397 /* reg_sbpm_min_buff 12398 * Minimum buffer size for the limiter, in cells. 12399 * Access: RW 12400 */ 12401 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24); 12402 12403 /* reg_sbpm_max_buff 12404 * When the pool associated to the port-pg/tclass is configured to 12405 * static, Maximum buffer size for the limiter configured in cells. 12406 * When the pool associated to the port-pg/tclass is configured to 12407 * dynamic, the max_buff holds the "alpha" parameter, supporting 12408 * the following values: 12409 * 0: 0 12410 * i: (1/128)*2^(i-1), for i=1..14 12411 * 0xFF: Infinity 12412 * Access: RW 12413 */ 12414 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24); 12415 12416 static inline void mlxsw_reg_sbpm_pack(char *payload, u16 local_port, u8 pool, 12417 enum mlxsw_reg_sbxx_dir dir, bool clr, 12418 u32 min_buff, u32 max_buff) 12419 { 12420 MLXSW_REG_ZERO(sbpm, payload); 12421 mlxsw_reg_sbpm_local_port_set(payload, local_port); 12422 mlxsw_reg_sbpm_pool_set(payload, pool); 12423 mlxsw_reg_sbpm_dir_set(payload, dir); 12424 mlxsw_reg_sbpm_clr_set(payload, clr); 12425 mlxsw_reg_sbpm_min_buff_set(payload, min_buff); 12426 mlxsw_reg_sbpm_max_buff_set(payload, max_buff); 12427 } 12428 12429 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy, 12430 u32 *p_max_buff_occupancy) 12431 { 12432 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload); 12433 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload); 12434 } 12435 12436 /* SBMM - Shared Buffer Multicast Management Register 12437 * -------------------------------------------------- 12438 * The SBMM register configures and retrieves the shared buffer allocation 12439 * and configuration for MC packets according to Switch-Priority, including 12440 * the binding to pool and definition of the associated quota. 12441 */ 12442 #define MLXSW_REG_SBMM_ID 0xB004 12443 #define MLXSW_REG_SBMM_LEN 0x28 12444 12445 MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN); 12446 12447 /* reg_sbmm_prio 12448 * Switch Priority. 12449 * Access: Index 12450 */ 12451 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4); 12452 12453 /* reg_sbmm_min_buff 12454 * Minimum buffer size for the limiter, in cells. 12455 * Access: RW 12456 */ 12457 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24); 12458 12459 /* reg_sbmm_max_buff 12460 * When the pool associated to the port-pg/tclass is configured to 12461 * static, Maximum buffer size for the limiter configured in cells. 12462 * When the pool associated to the port-pg/tclass is configured to 12463 * dynamic, the max_buff holds the "alpha" parameter, supporting 12464 * the following values: 12465 * 0: 0 12466 * i: (1/128)*2^(i-1), for i=1..14 12467 * 0xFF: Infinity 12468 * Access: RW 12469 */ 12470 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24); 12471 12472 /* reg_sbmm_pool 12473 * Association of the port-priority to a pool. 12474 * Access: RW 12475 */ 12476 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4); 12477 12478 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff, 12479 u32 max_buff, u8 pool) 12480 { 12481 MLXSW_REG_ZERO(sbmm, payload); 12482 mlxsw_reg_sbmm_prio_set(payload, prio); 12483 mlxsw_reg_sbmm_min_buff_set(payload, min_buff); 12484 mlxsw_reg_sbmm_max_buff_set(payload, max_buff); 12485 mlxsw_reg_sbmm_pool_set(payload, pool); 12486 } 12487 12488 /* SBSR - Shared Buffer Status Register 12489 * ------------------------------------ 12490 * The SBSR register retrieves the shared buffer occupancy according to 12491 * Port-Pool. Note that this register enables reading a large amount of data. 12492 * It is the user's responsibility to limit the amount of data to ensure the 12493 * response can match the maximum transfer unit. In case the response exceeds 12494 * the maximum transport unit, it will be truncated with no special notice. 12495 */ 12496 #define MLXSW_REG_SBSR_ID 0xB005 12497 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */ 12498 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */ 12499 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120 12500 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \ 12501 MLXSW_REG_SBSR_REC_LEN * \ 12502 MLXSW_REG_SBSR_REC_MAX_COUNT) 12503 12504 MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN); 12505 12506 /* reg_sbsr_clr 12507 * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy 12508 * field is cleared (and a new max value is tracked from the time the clear 12509 * was performed). 12510 * Access: OP 12511 */ 12512 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1); 12513 12514 #define MLXSW_REG_SBSR_NUM_PORTS_IN_PAGE 256 12515 12516 /* reg_sbsr_port_page 12517 * Determines the range of the ports specified in the 'ingress_port_mask' 12518 * and 'egress_port_mask' bit masks. 12519 * {ingress,egress}_port_mask[x] is (256 * port_page) + x 12520 * Access: Index 12521 */ 12522 MLXSW_ITEM32(reg, sbsr, port_page, 0x04, 0, 4); 12523 12524 /* reg_sbsr_ingress_port_mask 12525 * Bit vector for all ingress network ports. 12526 * Indicates which of the ports (for which the relevant bit is set) 12527 * are affected by the set operation. Configuration of any other port 12528 * does not change. 12529 * Access: Index 12530 */ 12531 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1); 12532 12533 /* reg_sbsr_pg_buff_mask 12534 * Bit vector for all switch priority groups. 12535 * Indicates which of the priorities (for which the relevant bit is set) 12536 * are affected by the set operation. Configuration of any other priority 12537 * does not change. 12538 * Range is 0..cap_max_pg_buffers - 1 12539 * Access: Index 12540 */ 12541 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1); 12542 12543 /* reg_sbsr_egress_port_mask 12544 * Bit vector for all egress network ports. 12545 * Indicates which of the ports (for which the relevant bit is set) 12546 * are affected by the set operation. Configuration of any other port 12547 * does not change. 12548 * Access: Index 12549 */ 12550 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1); 12551 12552 /* reg_sbsr_tclass_mask 12553 * Bit vector for all traffic classes. 12554 * Indicates which of the traffic classes (for which the relevant bit is 12555 * set) are affected by the set operation. Configuration of any other 12556 * traffic class does not change. 12557 * Range is 0..cap_max_tclass - 1 12558 * Access: Index 12559 */ 12560 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1); 12561 12562 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr) 12563 { 12564 MLXSW_REG_ZERO(sbsr, payload); 12565 mlxsw_reg_sbsr_clr_set(payload, clr); 12566 } 12567 12568 /* reg_sbsr_rec_buff_occupancy 12569 * Current buffer occupancy in cells. 12570 * Access: RO 12571 */ 12572 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 12573 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false); 12574 12575 /* reg_sbsr_rec_max_buff_occupancy 12576 * Maximum value of buffer occupancy in cells monitored. Cleared by 12577 * writing to the clr field. 12578 * Access: RO 12579 */ 12580 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 12581 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false); 12582 12583 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index, 12584 u32 *p_buff_occupancy, 12585 u32 *p_max_buff_occupancy) 12586 { 12587 *p_buff_occupancy = 12588 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index); 12589 *p_max_buff_occupancy = 12590 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index); 12591 } 12592 12593 /* SBIB - Shared Buffer Internal Buffer Register 12594 * --------------------------------------------- 12595 * The SBIB register configures per port buffers for internal use. The internal 12596 * buffers consume memory on the port buffers (note that the port buffers are 12597 * used also by PBMC). 12598 * 12599 * For Spectrum this is used for egress mirroring. 12600 */ 12601 #define MLXSW_REG_SBIB_ID 0xB006 12602 #define MLXSW_REG_SBIB_LEN 0x10 12603 12604 MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN); 12605 12606 /* reg_sbib_local_port 12607 * Local port number 12608 * Not supported for CPU port and router port 12609 * Access: Index 12610 */ 12611 MLXSW_ITEM32_LP(reg, sbib, 0x00, 16, 0x00, 12); 12612 12613 /* reg_sbib_buff_size 12614 * Units represented in cells 12615 * Allowed range is 0 to (cap_max_headroom_size - 1) 12616 * Default is 0 12617 * Access: RW 12618 */ 12619 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24); 12620 12621 static inline void mlxsw_reg_sbib_pack(char *payload, u16 local_port, 12622 u32 buff_size) 12623 { 12624 MLXSW_REG_ZERO(sbib, payload); 12625 mlxsw_reg_sbib_local_port_set(payload, local_port); 12626 mlxsw_reg_sbib_buff_size_set(payload, buff_size); 12627 } 12628 12629 static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { 12630 MLXSW_REG(sgcr), 12631 MLXSW_REG(spad), 12632 MLXSW_REG(sspr), 12633 MLXSW_REG(sfdat), 12634 MLXSW_REG(sfd), 12635 MLXSW_REG(sfn), 12636 MLXSW_REG(spms), 12637 MLXSW_REG(spvid), 12638 MLXSW_REG(spvm), 12639 MLXSW_REG(spaft), 12640 MLXSW_REG(sfgc), 12641 MLXSW_REG(sfdf), 12642 MLXSW_REG(sldr), 12643 MLXSW_REG(slcr), 12644 MLXSW_REG(slcor), 12645 MLXSW_REG(spmlr), 12646 MLXSW_REG(svfa), 12647 MLXSW_REG(spvtr), 12648 MLXSW_REG(svpe), 12649 MLXSW_REG(sfmr), 12650 MLXSW_REG(spvmlr), 12651 MLXSW_REG(spvc), 12652 MLXSW_REG(spevet), 12653 MLXSW_REG(smpe), 12654 MLXSW_REG(sftr2), 12655 MLXSW_REG(smid2), 12656 MLXSW_REG(cwtp), 12657 MLXSW_REG(cwtpm), 12658 MLXSW_REG(pgcr), 12659 MLXSW_REG(ppbt), 12660 MLXSW_REG(pacl), 12661 MLXSW_REG(pagt), 12662 MLXSW_REG(ptar), 12663 MLXSW_REG(ppbs), 12664 MLXSW_REG(prcr), 12665 MLXSW_REG(pefa), 12666 MLXSW_REG(pemrbt), 12667 MLXSW_REG(ptce2), 12668 MLXSW_REG(perpt), 12669 MLXSW_REG(peabfe), 12670 MLXSW_REG(perar), 12671 MLXSW_REG(ptce3), 12672 MLXSW_REG(percr), 12673 MLXSW_REG(pererp), 12674 MLXSW_REG(iedr), 12675 MLXSW_REG(qpts), 12676 MLXSW_REG(qpcr), 12677 MLXSW_REG(qtct), 12678 MLXSW_REG(qeec), 12679 MLXSW_REG(qrwe), 12680 MLXSW_REG(qpdsm), 12681 MLXSW_REG(qpdp), 12682 MLXSW_REG(qpdpm), 12683 MLXSW_REG(qtctm), 12684 MLXSW_REG(qpsc), 12685 MLXSW_REG(pmlp), 12686 MLXSW_REG(pmtu), 12687 MLXSW_REG(ptys), 12688 MLXSW_REG(ppad), 12689 MLXSW_REG(paos), 12690 MLXSW_REG(pfcc), 12691 MLXSW_REG(ppcnt), 12692 MLXSW_REG(plib), 12693 MLXSW_REG(pptb), 12694 MLXSW_REG(pbmc), 12695 MLXSW_REG(pspa), 12696 MLXSW_REG(pmaos), 12697 MLXSW_REG(pplr), 12698 MLXSW_REG(pmtdb), 12699 MLXSW_REG(pmecr), 12700 MLXSW_REG(pmpe), 12701 MLXSW_REG(pddr), 12702 MLXSW_REG(pmmp), 12703 MLXSW_REG(pllp), 12704 MLXSW_REG(pmtm), 12705 MLXSW_REG(htgt), 12706 MLXSW_REG(hpkt), 12707 MLXSW_REG(rgcr), 12708 MLXSW_REG(ritr), 12709 MLXSW_REG(rtar), 12710 MLXSW_REG(ratr), 12711 MLXSW_REG(rtdp), 12712 MLXSW_REG(rips), 12713 MLXSW_REG(ratrad), 12714 MLXSW_REG(rdpm), 12715 MLXSW_REG(ricnt), 12716 MLXSW_REG(rrcr), 12717 MLXSW_REG(ralta), 12718 MLXSW_REG(ralst), 12719 MLXSW_REG(raltb), 12720 MLXSW_REG(ralue), 12721 MLXSW_REG(rauht), 12722 MLXSW_REG(raleu), 12723 MLXSW_REG(rauhtd), 12724 MLXSW_REG(rigr2), 12725 MLXSW_REG(recr2), 12726 MLXSW_REG(rmft2), 12727 MLXSW_REG(reiv), 12728 MLXSW_REG(mfcr), 12729 MLXSW_REG(mfsc), 12730 MLXSW_REG(mfsm), 12731 MLXSW_REG(mfsl), 12732 MLXSW_REG(fore), 12733 MLXSW_REG(mtcap), 12734 MLXSW_REG(mtmp), 12735 MLXSW_REG(mtwe), 12736 MLXSW_REG(mtbr), 12737 MLXSW_REG(mcia), 12738 MLXSW_REG(mpat), 12739 MLXSW_REG(mpar), 12740 MLXSW_REG(mgir), 12741 MLXSW_REG(mrsr), 12742 MLXSW_REG(mlcr), 12743 MLXSW_REG(mcion), 12744 MLXSW_REG(mtpps), 12745 MLXSW_REG(mtutc), 12746 MLXSW_REG(mpsc), 12747 MLXSW_REG(mcqi), 12748 MLXSW_REG(mcc), 12749 MLXSW_REG(mcda), 12750 MLXSW_REG(mgpc), 12751 MLXSW_REG(mprs), 12752 MLXSW_REG(mogcr), 12753 MLXSW_REG(mpagr), 12754 MLXSW_REG(momte), 12755 MLXSW_REG(mtpppc), 12756 MLXSW_REG(mtpptr), 12757 MLXSW_REG(mtptpt), 12758 MLXSW_REG(mfgd), 12759 MLXSW_REG(mgpir), 12760 MLXSW_REG(mbct), 12761 MLXSW_REG(mddq), 12762 MLXSW_REG(mddc), 12763 MLXSW_REG(mfde), 12764 MLXSW_REG(tngcr), 12765 MLXSW_REG(tnumt), 12766 MLXSW_REG(tnqcr), 12767 MLXSW_REG(tnqdr), 12768 MLXSW_REG(tneem), 12769 MLXSW_REG(tndem), 12770 MLXSW_REG(tnpc), 12771 MLXSW_REG(tigcr), 12772 MLXSW_REG(tieem), 12773 MLXSW_REG(tidem), 12774 MLXSW_REG(sbpr), 12775 MLXSW_REG(sbcm), 12776 MLXSW_REG(sbpm), 12777 MLXSW_REG(sbmm), 12778 MLXSW_REG(sbsr), 12779 MLXSW_REG(sbib), 12780 }; 12781 12782 static inline const char *mlxsw_reg_id_str(u16 reg_id) 12783 { 12784 const struct mlxsw_reg_info *reg_info; 12785 int i; 12786 12787 for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) { 12788 reg_info = mlxsw_reg_infos[i]; 12789 if (reg_info->id == reg_id) 12790 return reg_info->name; 12791 } 12792 return "*UNKNOWN*"; 12793 } 12794 12795 /* PUDE - Port Up / Down Event 12796 * --------------------------- 12797 * Reports the operational state change of a port. 12798 */ 12799 #define MLXSW_REG_PUDE_LEN 0x10 12800 12801 /* reg_pude_swid 12802 * Switch partition ID with which to associate the port. 12803 * Access: Index 12804 */ 12805 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8); 12806 12807 /* reg_pude_local_port 12808 * Local port number. 12809 * Access: Index 12810 */ 12811 MLXSW_ITEM32_LP(reg, pude, 0x00, 16, 0x00, 12); 12812 12813 /* reg_pude_admin_status 12814 * Port administrative state (the desired state). 12815 * 1 - Up. 12816 * 2 - Down. 12817 * 3 - Up once. This means that in case of link failure, the port won't go 12818 * into polling mode, but will wait to be re-enabled by software. 12819 * 4 - Disabled by system. Can only be set by hardware. 12820 * Access: RO 12821 */ 12822 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4); 12823 12824 /* reg_pude_oper_status 12825 * Port operatioanl state. 12826 * 1 - Up. 12827 * 2 - Down. 12828 * 3 - Down by port failure. This means that the device will not let the 12829 * port up again until explicitly specified by software. 12830 * Access: RO 12831 */ 12832 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4); 12833 12834 #endif 12835