1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #ifndef _MLXSW_REG_H 5 #define _MLXSW_REG_H 6 7 #include <linux/kernel.h> 8 #include <linux/string.h> 9 #include <linux/bitops.h> 10 #include <linux/if_vlan.h> 11 12 #include "item.h" 13 #include "port.h" 14 15 struct mlxsw_reg_info { 16 u16 id; 17 u16 len; /* In u8 */ 18 const char *name; 19 }; 20 21 #define MLXSW_REG_DEFINE(_name, _id, _len) \ 22 static const struct mlxsw_reg_info mlxsw_reg_##_name = { \ 23 .id = _id, \ 24 .len = _len, \ 25 .name = #_name, \ 26 } 27 28 #define MLXSW_REG(type) (&mlxsw_reg_##type) 29 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len 30 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len) 31 32 /* SGCR - Switch General Configuration Register 33 * -------------------------------------------- 34 * This register is used for configuration of the switch capabilities. 35 */ 36 #define MLXSW_REG_SGCR_ID 0x2000 37 #define MLXSW_REG_SGCR_LEN 0x10 38 39 MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN); 40 41 /* reg_sgcr_lag_lookup_pgt_base 42 * Base address used for lookup in PGT table 43 * Supported when CONFIG_PROFILE.lag_mode = 1 44 * Note: when IGCR.ddd_lag_mode=0, the address shall be aligned to 8 entries. 45 * Access: RW 46 */ 47 MLXSW_ITEM32(reg, sgcr, lag_lookup_pgt_base, 0x0C, 0, 16); 48 49 static inline void mlxsw_reg_sgcr_pack(char *payload, u16 lag_lookup_pgt_base) 50 { 51 MLXSW_REG_ZERO(sgcr, payload); 52 mlxsw_reg_sgcr_lag_lookup_pgt_base_set(payload, lag_lookup_pgt_base); 53 } 54 55 /* SPAD - Switch Physical Address Register 56 * --------------------------------------- 57 * The SPAD register configures the switch physical MAC address. 58 */ 59 #define MLXSW_REG_SPAD_ID 0x2002 60 #define MLXSW_REG_SPAD_LEN 0x10 61 62 MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN); 63 64 /* reg_spad_base_mac 65 * Base MAC address for the switch partitions. 66 * Per switch partition MAC address is equal to: 67 * base_mac + swid 68 * Access: RW 69 */ 70 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6); 71 72 /* SSPR - Switch System Port Record Register 73 * ----------------------------------------- 74 * Configures the system port to local port mapping. 75 */ 76 #define MLXSW_REG_SSPR_ID 0x2008 77 #define MLXSW_REG_SSPR_LEN 0x8 78 79 MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN); 80 81 /* reg_sspr_m 82 * Master - if set, then the record describes the master system port. 83 * This is needed in case a local port is mapped into several system ports 84 * (for multipathing). That number will be reported as the source system 85 * port when packets are forwarded to the CPU. Only one master port is allowed 86 * per local port. 87 * 88 * Note: Must be set for Spectrum. 89 * Access: RW 90 */ 91 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1); 92 93 /* reg_sspr_local_port 94 * Local port number. 95 * 96 * Access: RW 97 */ 98 MLXSW_ITEM32_LP(reg, sspr, 0x00, 16, 0x00, 12); 99 100 /* reg_sspr_system_port 101 * Unique identifier within the stacking domain that represents all the ports 102 * that are available in the system (external ports). 103 * 104 * Currently, only single-ASIC configurations are supported, so we default to 105 * 1:1 mapping between system ports and local ports. 106 * Access: Index 107 */ 108 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16); 109 110 static inline void mlxsw_reg_sspr_pack(char *payload, u16 local_port) 111 { 112 MLXSW_REG_ZERO(sspr, payload); 113 mlxsw_reg_sspr_m_set(payload, 1); 114 mlxsw_reg_sspr_local_port_set(payload, local_port); 115 mlxsw_reg_sspr_system_port_set(payload, local_port); 116 } 117 118 /* SFDAT - Switch Filtering Database Aging Time 119 * -------------------------------------------- 120 * Controls the Switch aging time. Aging time is able to be set per Switch 121 * Partition. 122 */ 123 #define MLXSW_REG_SFDAT_ID 0x2009 124 #define MLXSW_REG_SFDAT_LEN 0x8 125 126 MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN); 127 128 /* reg_sfdat_swid 129 * Switch partition ID. 130 * Access: Index 131 */ 132 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8); 133 134 /* reg_sfdat_age_time 135 * Aging time in seconds 136 * Min - 10 seconds 137 * Max - 1,000,000 seconds 138 * Default is 300 seconds. 139 * Access: RW 140 */ 141 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20); 142 143 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time) 144 { 145 MLXSW_REG_ZERO(sfdat, payload); 146 mlxsw_reg_sfdat_swid_set(payload, 0); 147 mlxsw_reg_sfdat_age_time_set(payload, age_time); 148 } 149 150 /* SFD - Switch Filtering Database 151 * ------------------------------- 152 * The following register defines the access to the filtering database. 153 * The register supports querying, adding, removing and modifying the database. 154 * The access is optimized for bulk updates in which case more than one 155 * FDB record is present in the same command. 156 */ 157 #define MLXSW_REG_SFD_ID 0x200A 158 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */ 159 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */ 160 #define MLXSW_REG_SFD_REC_MAX_COUNT 64 161 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \ 162 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT) 163 164 MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN); 165 166 /* reg_sfd_swid 167 * Switch partition ID for queries. Reserved on Write. 168 * Access: Index 169 */ 170 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8); 171 172 enum mlxsw_reg_sfd_op { 173 /* Dump entire FDB a (process according to record_locator) */ 174 MLXSW_REG_SFD_OP_QUERY_DUMP = 0, 175 /* Query records by {MAC, VID/FID} value */ 176 MLXSW_REG_SFD_OP_QUERY_QUERY = 1, 177 /* Query and clear activity. Query records by {MAC, VID/FID} value */ 178 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2, 179 /* Test. Response indicates if each of the records could be 180 * added to the FDB. 181 */ 182 MLXSW_REG_SFD_OP_WRITE_TEST = 0, 183 /* Add/modify. Aged-out records cannot be added. This command removes 184 * the learning notification of the {MAC, VID/FID}. Response includes 185 * the entries that were added to the FDB. 186 */ 187 MLXSW_REG_SFD_OP_WRITE_EDIT = 1, 188 /* Remove record by {MAC, VID/FID}. This command also removes 189 * the learning notification and aged-out notifications 190 * of the {MAC, VID/FID}. The response provides current (pre-removal) 191 * entries as non-aged-out. 192 */ 193 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2, 194 /* Remove learned notification by {MAC, VID/FID}. The response provides 195 * the removed learning notification. 196 */ 197 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2, 198 }; 199 200 /* reg_sfd_op 201 * Operation. 202 * Access: OP 203 */ 204 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2); 205 206 /* reg_sfd_record_locator 207 * Used for querying the FDB. Use record_locator=0 to initiate the 208 * query. When a record is returned, a new record_locator is 209 * returned to be used in the subsequent query. 210 * Reserved for database update. 211 * Access: Index 212 */ 213 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30); 214 215 /* reg_sfd_num_rec 216 * Request: Number of records to read/add/modify/remove 217 * Response: Number of records read/added/replaced/removed 218 * See above description for more details. 219 * Ranges 0..64 220 * Access: RW 221 */ 222 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8); 223 224 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op, 225 u32 record_locator) 226 { 227 MLXSW_REG_ZERO(sfd, payload); 228 mlxsw_reg_sfd_op_set(payload, op); 229 mlxsw_reg_sfd_record_locator_set(payload, record_locator); 230 } 231 232 /* reg_sfd_rec_swid 233 * Switch partition ID. 234 * Access: Index 235 */ 236 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8, 237 MLXSW_REG_SFD_REC_LEN, 0x00, false); 238 239 enum mlxsw_reg_sfd_rec_type { 240 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0, 241 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1, 242 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2, 243 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL = 0xC, 244 }; 245 246 /* reg_sfd_rec_type 247 * FDB record type. 248 * Access: RW 249 */ 250 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4, 251 MLXSW_REG_SFD_REC_LEN, 0x00, false); 252 253 enum mlxsw_reg_sfd_rec_policy { 254 /* Replacement disabled, aging disabled. */ 255 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0, 256 /* (mlag remote): Replacement enabled, aging disabled, 257 * learning notification enabled on this port. 258 */ 259 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1, 260 /* (ingress device): Replacement enabled, aging enabled. */ 261 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3, 262 }; 263 264 /* reg_sfd_rec_policy 265 * Policy. 266 * Access: RW 267 */ 268 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2, 269 MLXSW_REG_SFD_REC_LEN, 0x00, false); 270 271 /* reg_sfd_rec_a 272 * Activity. Set for new static entries. Set for static entries if a frame SMAC 273 * lookup hits on the entry. 274 * To clear the a bit, use "query and clear activity" op. 275 * Access: RO 276 */ 277 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1, 278 MLXSW_REG_SFD_REC_LEN, 0x00, false); 279 280 /* reg_sfd_rec_mac 281 * MAC address. 282 * Access: Index 283 */ 284 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6, 285 MLXSW_REG_SFD_REC_LEN, 0x02); 286 287 enum mlxsw_reg_sfd_rec_action { 288 /* forward */ 289 MLXSW_REG_SFD_REC_ACTION_NOP = 0, 290 /* forward and trap, trap_id is FDB_TRAP */ 291 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1, 292 /* trap and do not forward, trap_id is FDB_TRAP */ 293 MLXSW_REG_SFD_REC_ACTION_TRAP = 2, 294 /* forward to IP router */ 295 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3, 296 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15, 297 }; 298 299 /* reg_sfd_rec_action 300 * Action to apply on the packet. 301 * Note: Dynamic entries can only be configured with NOP action. 302 * Access: RW 303 */ 304 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4, 305 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 306 307 /* reg_sfd_uc_sub_port 308 * VEPA channel on local port. 309 * Valid only if local port is a non-stacking port. Must be 0 if multichannel 310 * VEPA is not enabled. 311 * Access: RW 312 */ 313 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 314 MLXSW_REG_SFD_REC_LEN, 0x08, false); 315 316 /* reg_sfd_uc_set_vid 317 * Set VID. 318 * 0 - Do not update VID. 319 * 1 - Set VID. 320 * For Spectrum-2 when set_vid=0 and smpe_valid=1, the smpe will modify the vid. 321 * Access: RW 322 * 323 * Note: Reserved when legacy bridge model is used. 324 */ 325 MLXSW_ITEM32_INDEXED(reg, sfd, uc_set_vid, MLXSW_REG_SFD_BASE_LEN, 31, 1, 326 MLXSW_REG_SFD_REC_LEN, 0x08, false); 327 328 /* reg_sfd_uc_fid_vid 329 * Filtering ID or VLAN ID 330 * For SwitchX and SwitchX-2: 331 * - Dynamic entries (policy 2,3) use FID 332 * - Static entries (policy 0) use VID 333 * - When independent learning is configured, VID=FID 334 * For Spectrum: use FID for both Dynamic and Static entries. 335 * VID should not be used. 336 * Access: Index 337 */ 338 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 339 MLXSW_REG_SFD_REC_LEN, 0x08, false); 340 341 /* reg_sfd_uc_vid 342 * New VID when set_vid=1. 343 * Access: RW 344 * 345 * Note: Reserved when legacy bridge model is used and when set_vid=0. 346 */ 347 MLXSW_ITEM32_INDEXED(reg, sfd, uc_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, 348 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 349 350 /* reg_sfd_uc_system_port 351 * Unique port identifier for the final destination of the packet. 352 * Access: RW 353 */ 354 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16, 355 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 356 357 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index, 358 enum mlxsw_reg_sfd_rec_type rec_type, 359 const char *mac, 360 enum mlxsw_reg_sfd_rec_action action) 361 { 362 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload); 363 364 if (rec_index >= num_rec) 365 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1); 366 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0); 367 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type); 368 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac); 369 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action); 370 } 371 372 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index, 373 enum mlxsw_reg_sfd_rec_policy policy, 374 const char *mac, u16 fid_vid, u16 vid, 375 enum mlxsw_reg_sfd_rec_action action, 376 u16 local_port) 377 { 378 mlxsw_reg_sfd_rec_pack(payload, rec_index, 379 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action); 380 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 381 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0); 382 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid); 383 mlxsw_reg_sfd_uc_set_vid_set(payload, rec_index, vid ? true : false); 384 mlxsw_reg_sfd_uc_vid_set(payload, rec_index, vid); 385 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port); 386 } 387 388 /* reg_sfd_uc_lag_sub_port 389 * LAG sub port. 390 * Must be 0 if multichannel VEPA is not enabled. 391 * Access: RW 392 */ 393 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 394 MLXSW_REG_SFD_REC_LEN, 0x08, false); 395 396 /* reg_sfd_uc_lag_set_vid 397 * Set VID. 398 * 0 - Do not update VID. 399 * 1 - Set VID. 400 * For Spectrum-2 when set_vid=0 and smpe_valid=1, the smpe will modify the vid. 401 * Access: RW 402 * 403 * Note: Reserved when legacy bridge model is used. 404 */ 405 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_set_vid, MLXSW_REG_SFD_BASE_LEN, 31, 1, 406 MLXSW_REG_SFD_REC_LEN, 0x08, false); 407 408 /* reg_sfd_uc_lag_fid_vid 409 * Filtering ID or VLAN ID 410 * For SwitchX and SwitchX-2: 411 * - Dynamic entries (policy 2,3) use FID 412 * - Static entries (policy 0) use VID 413 * - When independent learning is configured, VID=FID 414 * For Spectrum: use FID for both Dynamic and Static entries. 415 * VID should not be used. 416 * Access: Index 417 */ 418 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 419 MLXSW_REG_SFD_REC_LEN, 0x08, false); 420 421 /* reg_sfd_uc_lag_lag_vid 422 * New vlan ID. 423 * Access: RW 424 * 425 * Note: Reserved when legacy bridge model is used and set_vid=0. 426 */ 427 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, 428 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 429 430 /* reg_sfd_uc_lag_lag_id 431 * LAG Identifier - pointer into the LAG descriptor table. 432 * Access: RW 433 */ 434 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10, 435 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 436 437 static inline void 438 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index, 439 enum mlxsw_reg_sfd_rec_policy policy, 440 const char *mac, u16 fid_vid, 441 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid, 442 u16 lag_id) 443 { 444 mlxsw_reg_sfd_rec_pack(payload, rec_index, 445 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG, 446 mac, action); 447 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 448 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0); 449 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid); 450 mlxsw_reg_sfd_uc_lag_set_vid_set(payload, rec_index, true); 451 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid); 452 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id); 453 } 454 455 /* reg_sfd_mc_pgi 456 * 457 * Multicast port group index - index into the port group table. 458 * Value 0x1FFF indicates the pgi should point to the MID entry. 459 * For Spectrum this value must be set to 0x1FFF 460 * Access: RW 461 */ 462 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13, 463 MLXSW_REG_SFD_REC_LEN, 0x08, false); 464 465 /* reg_sfd_mc_fid_vid 466 * 467 * Filtering ID or VLAN ID 468 * Access: Index 469 */ 470 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 471 MLXSW_REG_SFD_REC_LEN, 0x08, false); 472 473 /* reg_sfd_mc_mid 474 * 475 * Multicast identifier - global identifier that represents the multicast 476 * group across all devices. 477 * Access: RW 478 */ 479 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 480 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 481 482 static inline void 483 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index, 484 const char *mac, u16 fid_vid, 485 enum mlxsw_reg_sfd_rec_action action, u16 mid) 486 { 487 mlxsw_reg_sfd_rec_pack(payload, rec_index, 488 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action); 489 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF); 490 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid); 491 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid); 492 } 493 494 /* reg_sfd_uc_tunnel_uip_msb 495 * When protocol is IPv4, the most significant byte of the underlay IPv4 496 * destination IP. 497 * When protocol is IPv6, reserved. 498 * Access: RW 499 */ 500 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24, 501 8, MLXSW_REG_SFD_REC_LEN, 0x08, false); 502 503 /* reg_sfd_uc_tunnel_fid 504 * Filtering ID. 505 * Access: Index 506 */ 507 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 508 MLXSW_REG_SFD_REC_LEN, 0x08, false); 509 510 enum mlxsw_reg_sfd_uc_tunnel_protocol { 511 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4, 512 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6, 513 }; 514 515 /* reg_sfd_uc_tunnel_protocol 516 * IP protocol. 517 * Access: RW 518 */ 519 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27, 520 1, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 521 522 /* reg_sfd_uc_tunnel_uip_lsb 523 * When protocol is IPv4, the least significant bytes of the underlay 524 * IPv4 destination IP. 525 * When protocol is IPv6, pointer to the underlay IPv6 destination IP 526 * which is configured by RIPS. 527 * Access: RW 528 */ 529 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0, 530 24, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 531 532 static inline void 533 mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index, 534 enum mlxsw_reg_sfd_rec_policy policy, 535 const char *mac, u16 fid, 536 enum mlxsw_reg_sfd_rec_action action, 537 enum mlxsw_reg_sfd_uc_tunnel_protocol proto) 538 { 539 mlxsw_reg_sfd_rec_pack(payload, rec_index, 540 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL, mac, 541 action); 542 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 543 mlxsw_reg_sfd_uc_tunnel_fid_set(payload, rec_index, fid); 544 mlxsw_reg_sfd_uc_tunnel_protocol_set(payload, rec_index, proto); 545 } 546 547 static inline void 548 mlxsw_reg_sfd_uc_tunnel_pack4(char *payload, int rec_index, 549 enum mlxsw_reg_sfd_rec_policy policy, 550 const char *mac, u16 fid, 551 enum mlxsw_reg_sfd_rec_action action, u32 uip) 552 { 553 mlxsw_reg_sfd_uc_tunnel_uip_msb_set(payload, rec_index, uip >> 24); 554 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip); 555 mlxsw_reg_sfd_uc_tunnel_pack(payload, rec_index, policy, mac, fid, 556 action, 557 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4); 558 } 559 560 static inline void 561 mlxsw_reg_sfd_uc_tunnel_pack6(char *payload, int rec_index, const char *mac, 562 u16 fid, enum mlxsw_reg_sfd_rec_action action, 563 u32 uip_ptr) 564 { 565 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip_ptr); 566 /* Only static policy is supported for IPv6 unicast tunnel entry. */ 567 mlxsw_reg_sfd_uc_tunnel_pack(payload, rec_index, 568 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY, 569 mac, fid, action, 570 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6); 571 } 572 573 enum mlxsw_reg_tunnel_port { 574 MLXSW_REG_TUNNEL_PORT_NVE, 575 MLXSW_REG_TUNNEL_PORT_VPLS, 576 MLXSW_REG_TUNNEL_PORT_FLEX_TUNNEL0, 577 MLXSW_REG_TUNNEL_PORT_FLEX_TUNNEL1, 578 }; 579 580 /* SFN - Switch FDB Notification Register 581 * ------------------------------------------- 582 * The switch provides notifications on newly learned FDB entries and 583 * aged out entries. The notifications can be polled by software. 584 */ 585 #define MLXSW_REG_SFN_ID 0x200B 586 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */ 587 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */ 588 #define MLXSW_REG_SFN_REC_MAX_COUNT 64 589 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \ 590 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT) 591 592 MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN); 593 594 /* reg_sfn_swid 595 * Switch partition ID. 596 * Access: Index 597 */ 598 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8); 599 600 /* reg_sfn_end 601 * Forces the current session to end. 602 * Access: OP 603 */ 604 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1); 605 606 /* reg_sfn_num_rec 607 * Request: Number of learned notifications and aged-out notification 608 * records requested. 609 * Response: Number of notification records returned (must be smaller 610 * than or equal to the value requested) 611 * Ranges 0..64 612 * Access: OP 613 */ 614 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8); 615 616 static inline void mlxsw_reg_sfn_pack(char *payload) 617 { 618 MLXSW_REG_ZERO(sfn, payload); 619 mlxsw_reg_sfn_swid_set(payload, 0); 620 mlxsw_reg_sfn_end_set(payload, 0); 621 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT); 622 } 623 624 /* reg_sfn_rec_swid 625 * Switch partition ID. 626 * Access: RO 627 */ 628 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8, 629 MLXSW_REG_SFN_REC_LEN, 0x00, false); 630 631 enum mlxsw_reg_sfn_rec_type { 632 /* MAC addresses learned on a regular port. */ 633 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5, 634 /* MAC addresses learned on a LAG port. */ 635 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6, 636 /* Aged-out MAC address on a regular port. */ 637 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7, 638 /* Aged-out MAC address on a LAG port. */ 639 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8, 640 /* Learned unicast tunnel record. */ 641 MLXSW_REG_SFN_REC_TYPE_LEARNED_UNICAST_TUNNEL = 0xD, 642 /* Aged-out unicast tunnel record. */ 643 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_UNICAST_TUNNEL = 0xE, 644 }; 645 646 /* reg_sfn_rec_type 647 * Notification record type. 648 * Access: RO 649 */ 650 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4, 651 MLXSW_REG_SFN_REC_LEN, 0x00, false); 652 653 /* reg_sfn_rec_mac 654 * MAC address. 655 * Access: RO 656 */ 657 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6, 658 MLXSW_REG_SFN_REC_LEN, 0x02); 659 660 /* reg_sfn_mac_sub_port 661 * VEPA channel on the local port. 662 * 0 if multichannel VEPA is not enabled. 663 * Access: RO 664 */ 665 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8, 666 MLXSW_REG_SFN_REC_LEN, 0x08, false); 667 668 /* reg_sfn_mac_fid 669 * Filtering identifier. 670 * Access: RO 671 */ 672 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16, 673 MLXSW_REG_SFN_REC_LEN, 0x08, false); 674 675 /* reg_sfn_mac_system_port 676 * Unique port identifier for the final destination of the packet. 677 * Access: RO 678 */ 679 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16, 680 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 681 682 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index, 683 char *mac, u16 *p_vid, 684 u16 *p_local_port) 685 { 686 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 687 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 688 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index); 689 } 690 691 /* reg_sfn_mac_lag_lag_id 692 * LAG ID (pointer into the LAG descriptor table). 693 * Access: RO 694 */ 695 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10, 696 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 697 698 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index, 699 char *mac, u16 *p_vid, 700 u16 *p_lag_id) 701 { 702 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 703 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 704 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index); 705 } 706 707 /* reg_sfn_uc_tunnel_uip_msb 708 * When protocol is IPv4, the most significant byte of the underlay IPv4 709 * address of the remote VTEP. 710 * When protocol is IPv6, reserved. 711 * Access: RO 712 */ 713 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_msb, MLXSW_REG_SFN_BASE_LEN, 24, 714 8, MLXSW_REG_SFN_REC_LEN, 0x08, false); 715 716 enum mlxsw_reg_sfn_uc_tunnel_protocol { 717 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV4, 718 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV6, 719 }; 720 721 /* reg_sfn_uc_tunnel_protocol 722 * IP protocol. 723 * Access: RO 724 */ 725 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_protocol, MLXSW_REG_SFN_BASE_LEN, 27, 726 1, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 727 728 /* reg_sfn_uc_tunnel_uip_lsb 729 * When protocol is IPv4, the least significant bytes of the underlay 730 * IPv4 address of the remote VTEP. 731 * When protocol is IPv6, ipv6_id to be queried from TNIPSD. 732 * Access: RO 733 */ 734 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0, 735 24, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 736 737 /* reg_sfn_uc_tunnel_port 738 * Tunnel port. 739 * Reserved on Spectrum. 740 * Access: RO 741 */ 742 MLXSW_ITEM32_INDEXED(reg, sfn, tunnel_port, MLXSW_REG_SFN_BASE_LEN, 0, 4, 743 MLXSW_REG_SFN_REC_LEN, 0x10, false); 744 745 static inline void 746 mlxsw_reg_sfn_uc_tunnel_unpack(char *payload, int rec_index, char *mac, 747 u16 *p_fid, u32 *p_uip, 748 enum mlxsw_reg_sfn_uc_tunnel_protocol *p_proto) 749 { 750 u32 uip_msb, uip_lsb; 751 752 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 753 *p_fid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 754 uip_msb = mlxsw_reg_sfn_uc_tunnel_uip_msb_get(payload, rec_index); 755 uip_lsb = mlxsw_reg_sfn_uc_tunnel_uip_lsb_get(payload, rec_index); 756 *p_uip = uip_msb << 24 | uip_lsb; 757 *p_proto = mlxsw_reg_sfn_uc_tunnel_protocol_get(payload, rec_index); 758 } 759 760 /* SPMS - Switch Port MSTP/RSTP State Register 761 * ------------------------------------------- 762 * Configures the spanning tree state of a physical port. 763 */ 764 #define MLXSW_REG_SPMS_ID 0x200D 765 #define MLXSW_REG_SPMS_LEN 0x404 766 767 MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN); 768 769 /* reg_spms_local_port 770 * Local port number. 771 * Access: Index 772 */ 773 MLXSW_ITEM32_LP(reg, spms, 0x00, 16, 0x00, 12); 774 775 enum mlxsw_reg_spms_state { 776 MLXSW_REG_SPMS_STATE_NO_CHANGE, 777 MLXSW_REG_SPMS_STATE_DISCARDING, 778 MLXSW_REG_SPMS_STATE_LEARNING, 779 MLXSW_REG_SPMS_STATE_FORWARDING, 780 }; 781 782 /* reg_spms_state 783 * Spanning tree state of each VLAN ID (VID) of the local port. 784 * 0 - Do not change spanning tree state (used only when writing). 785 * 1 - Discarding. No learning or forwarding to/from this port (default). 786 * 2 - Learning. Port is learning, but not forwarding. 787 * 3 - Forwarding. Port is learning and forwarding. 788 * Access: RW 789 */ 790 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2); 791 792 static inline void mlxsw_reg_spms_pack(char *payload, u16 local_port) 793 { 794 MLXSW_REG_ZERO(spms, payload); 795 mlxsw_reg_spms_local_port_set(payload, local_port); 796 } 797 798 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid, 799 enum mlxsw_reg_spms_state state) 800 { 801 mlxsw_reg_spms_state_set(payload, vid, state); 802 } 803 804 /* SPVID - Switch Port VID 805 * ----------------------- 806 * The switch port VID configures the default VID for a port. 807 */ 808 #define MLXSW_REG_SPVID_ID 0x200E 809 #define MLXSW_REG_SPVID_LEN 0x08 810 811 MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN); 812 813 /* reg_spvid_tport 814 * Port is tunnel port. 815 * Reserved when SwitchX/-2 or Spectrum-1. 816 * Access: Index 817 */ 818 MLXSW_ITEM32(reg, spvid, tport, 0x00, 24, 1); 819 820 /* reg_spvid_local_port 821 * When tport = 0: Local port number. Not supported for CPU port. 822 * When tport = 1: Tunnel port. 823 * Access: Index 824 */ 825 MLXSW_ITEM32_LP(reg, spvid, 0x00, 16, 0x00, 12); 826 827 /* reg_spvid_sub_port 828 * Virtual port within the physical port. 829 * Should be set to 0 when virtual ports are not enabled on the port. 830 * Access: Index 831 */ 832 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8); 833 834 /* reg_spvid_egr_et_set 835 * When VLAN is pushed at ingress (for untagged packets or for 836 * QinQ push mode) then the EtherType is decided at the egress port. 837 * Reserved when Spectrum-1. 838 * Access: RW 839 */ 840 MLXSW_ITEM32(reg, spvid, egr_et_set, 0x04, 24, 1); 841 842 /* reg_spvid_et_vlan 843 * EtherType used for when VLAN is pushed at ingress (for untagged 844 * packets or for QinQ push mode). 845 * 0: ether_type0 - (default) 846 * 1: ether_type1 847 * 2: ether_type2 - Reserved when Spectrum-1, supported by Spectrum-2 848 * Ethertype IDs are configured by SVER. 849 * Reserved when egr_et_set = 1. 850 * Access: RW 851 */ 852 MLXSW_ITEM32(reg, spvid, et_vlan, 0x04, 16, 2); 853 854 /* reg_spvid_pvid 855 * Port default VID 856 * Access: RW 857 */ 858 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12); 859 860 static inline void mlxsw_reg_spvid_pack(char *payload, u16 local_port, u16 pvid, 861 u8 et_vlan) 862 { 863 MLXSW_REG_ZERO(spvid, payload); 864 mlxsw_reg_spvid_local_port_set(payload, local_port); 865 mlxsw_reg_spvid_pvid_set(payload, pvid); 866 mlxsw_reg_spvid_et_vlan_set(payload, et_vlan); 867 } 868 869 /* SPVM - Switch Port VLAN Membership 870 * ---------------------------------- 871 * The Switch Port VLAN Membership register configures the VLAN membership 872 * of a port in a VLAN denoted by VID. VLAN membership is managed per 873 * virtual port. The register can be used to add and remove VID(s) from a port. 874 */ 875 #define MLXSW_REG_SPVM_ID 0x200F 876 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */ 877 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */ 878 #define MLXSW_REG_SPVM_REC_MAX_COUNT 255 879 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \ 880 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT) 881 882 MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN); 883 884 /* reg_spvm_pt 885 * Priority tagged. If this bit is set, packets forwarded to the port with 886 * untagged VLAN membership (u bit is set) will be tagged with priority tag 887 * (VID=0) 888 * Access: RW 889 */ 890 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1); 891 892 /* reg_spvm_pte 893 * Priority Tagged Update Enable. On Write operations, if this bit is cleared, 894 * the pt bit will NOT be updated. To update the pt bit, pte must be set. 895 * Access: WO 896 */ 897 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1); 898 899 /* reg_spvm_local_port 900 * Local port number. 901 * Access: Index 902 */ 903 MLXSW_ITEM32_LP(reg, spvm, 0x00, 16, 0x00, 12); 904 905 /* reg_spvm_sub_port 906 * Virtual port within the physical port. 907 * Should be set to 0 when virtual ports are not enabled on the port. 908 * Access: Index 909 */ 910 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8); 911 912 /* reg_spvm_num_rec 913 * Number of records to update. Each record contains: i, e, u, vid. 914 * Access: OP 915 */ 916 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8); 917 918 /* reg_spvm_rec_i 919 * Ingress membership in VLAN ID. 920 * Access: Index 921 */ 922 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i, 923 MLXSW_REG_SPVM_BASE_LEN, 14, 1, 924 MLXSW_REG_SPVM_REC_LEN, 0, false); 925 926 /* reg_spvm_rec_e 927 * Egress membership in VLAN ID. 928 * Access: Index 929 */ 930 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e, 931 MLXSW_REG_SPVM_BASE_LEN, 13, 1, 932 MLXSW_REG_SPVM_REC_LEN, 0, false); 933 934 /* reg_spvm_rec_u 935 * Untagged - port is an untagged member - egress transmission uses untagged 936 * frames on VID<n> 937 * Access: Index 938 */ 939 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u, 940 MLXSW_REG_SPVM_BASE_LEN, 12, 1, 941 MLXSW_REG_SPVM_REC_LEN, 0, false); 942 943 /* reg_spvm_rec_vid 944 * Egress membership in VLAN ID. 945 * Access: Index 946 */ 947 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid, 948 MLXSW_REG_SPVM_BASE_LEN, 0, 12, 949 MLXSW_REG_SPVM_REC_LEN, 0, false); 950 951 static inline void mlxsw_reg_spvm_pack(char *payload, u16 local_port, 952 u16 vid_begin, u16 vid_end, 953 bool is_member, bool untagged) 954 { 955 int size = vid_end - vid_begin + 1; 956 int i; 957 958 MLXSW_REG_ZERO(spvm, payload); 959 mlxsw_reg_spvm_local_port_set(payload, local_port); 960 mlxsw_reg_spvm_num_rec_set(payload, size); 961 962 for (i = 0; i < size; i++) { 963 mlxsw_reg_spvm_rec_i_set(payload, i, is_member); 964 mlxsw_reg_spvm_rec_e_set(payload, i, is_member); 965 mlxsw_reg_spvm_rec_u_set(payload, i, untagged); 966 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i); 967 } 968 } 969 970 /* SPAFT - Switch Port Acceptable Frame Types 971 * ------------------------------------------ 972 * The Switch Port Acceptable Frame Types register configures the frame 973 * admittance of the port. 974 */ 975 #define MLXSW_REG_SPAFT_ID 0x2010 976 #define MLXSW_REG_SPAFT_LEN 0x08 977 978 MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN); 979 980 /* reg_spaft_local_port 981 * Local port number. 982 * Access: Index 983 * 984 * Note: CPU port is not supported (all tag types are allowed). 985 */ 986 MLXSW_ITEM32_LP(reg, spaft, 0x00, 16, 0x00, 12); 987 988 /* reg_spaft_sub_port 989 * Virtual port within the physical port. 990 * Should be set to 0 when virtual ports are not enabled on the port. 991 * Access: RW 992 */ 993 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8); 994 995 /* reg_spaft_allow_untagged 996 * When set, untagged frames on the ingress are allowed (default). 997 * Access: RW 998 */ 999 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1); 1000 1001 /* reg_spaft_allow_prio_tagged 1002 * When set, priority tagged frames on the ingress are allowed (default). 1003 * Access: RW 1004 */ 1005 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1); 1006 1007 /* reg_spaft_allow_tagged 1008 * When set, tagged frames on the ingress are allowed (default). 1009 * Access: RW 1010 */ 1011 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1); 1012 1013 static inline void mlxsw_reg_spaft_pack(char *payload, u16 local_port, 1014 bool allow_untagged) 1015 { 1016 MLXSW_REG_ZERO(spaft, payload); 1017 mlxsw_reg_spaft_local_port_set(payload, local_port); 1018 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged); 1019 mlxsw_reg_spaft_allow_prio_tagged_set(payload, allow_untagged); 1020 mlxsw_reg_spaft_allow_tagged_set(payload, true); 1021 } 1022 1023 /* SFGC - Switch Flooding Group Configuration 1024 * ------------------------------------------ 1025 * The following register controls the association of flooding tables and MIDs 1026 * to packet types used for flooding. 1027 * 1028 * Reserved when CONFIG_PROFILE.flood_mode = CFF. 1029 */ 1030 #define MLXSW_REG_SFGC_ID 0x2011 1031 #define MLXSW_REG_SFGC_LEN 0x14 1032 1033 MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN); 1034 1035 enum mlxsw_reg_sfgc_type { 1036 MLXSW_REG_SFGC_TYPE_BROADCAST, 1037 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST, 1038 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4, 1039 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6, 1040 MLXSW_REG_SFGC_TYPE_RESERVED, 1041 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP, 1042 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL, 1043 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST, 1044 MLXSW_REG_SFGC_TYPE_MAX, 1045 }; 1046 1047 /* reg_sfgc_type 1048 * The traffic type to reach the flooding table. 1049 * Access: Index 1050 */ 1051 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4); 1052 1053 /* bridge_type is used in SFGC and SFMR. */ 1054 enum mlxsw_reg_bridge_type { 1055 MLXSW_REG_BRIDGE_TYPE_0 = 0, /* Used for .1q FIDs. */ 1056 MLXSW_REG_BRIDGE_TYPE_1 = 1, /* Used for .1d FIDs. */ 1057 }; 1058 1059 /* reg_sfgc_bridge_type 1060 * Access: Index 1061 * 1062 * Note: SwitchX-2 only supports 802.1Q mode. 1063 */ 1064 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3); 1065 1066 enum mlxsw_flood_table_type { 1067 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1, 1068 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2, 1069 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0, 1070 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3, 1071 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4, 1072 }; 1073 1074 /* reg_sfgc_table_type 1075 * See mlxsw_flood_table_type 1076 * Access: RW 1077 * 1078 * Note: FID offset and FID types are not supported in SwitchX-2. 1079 */ 1080 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3); 1081 1082 /* reg_sfgc_flood_table 1083 * Flooding table index to associate with the specific type on the specific 1084 * switch partition. 1085 * Access: RW 1086 */ 1087 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6); 1088 1089 /* reg_sfgc_counter_set_type 1090 * Counter Set Type for flow counters. 1091 * Access: RW 1092 */ 1093 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8); 1094 1095 /* reg_sfgc_counter_index 1096 * Counter Index for flow counters. 1097 * Access: RW 1098 */ 1099 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24); 1100 1101 /* reg_sfgc_mid_base 1102 * MID Base. 1103 * Access: RW 1104 * 1105 * Note: Reserved when legacy bridge model is used. 1106 */ 1107 MLXSW_ITEM32(reg, sfgc, mid_base, 0x10, 0, 16); 1108 1109 static inline void 1110 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type, 1111 enum mlxsw_reg_bridge_type bridge_type, 1112 enum mlxsw_flood_table_type table_type, 1113 unsigned int flood_table, u16 mid_base) 1114 { 1115 MLXSW_REG_ZERO(sfgc, payload); 1116 mlxsw_reg_sfgc_type_set(payload, type); 1117 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type); 1118 mlxsw_reg_sfgc_table_type_set(payload, table_type); 1119 mlxsw_reg_sfgc_flood_table_set(payload, flood_table); 1120 mlxsw_reg_sfgc_mid_base_set(payload, mid_base); 1121 } 1122 1123 /* SFDF - Switch Filtering DB Flush 1124 * -------------------------------- 1125 * The switch filtering DB flush register is used to flush the FDB. 1126 * Note that FDB notifications are flushed as well. 1127 */ 1128 #define MLXSW_REG_SFDF_ID 0x2013 1129 #define MLXSW_REG_SFDF_LEN 0x14 1130 1131 MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN); 1132 1133 /* reg_sfdf_swid 1134 * Switch partition ID. 1135 * Access: Index 1136 */ 1137 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8); 1138 1139 enum mlxsw_reg_sfdf_flush_type { 1140 MLXSW_REG_SFDF_FLUSH_PER_SWID, 1141 MLXSW_REG_SFDF_FLUSH_PER_FID, 1142 MLXSW_REG_SFDF_FLUSH_PER_PORT, 1143 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID, 1144 MLXSW_REG_SFDF_FLUSH_PER_LAG, 1145 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID, 1146 MLXSW_REG_SFDF_FLUSH_PER_NVE, 1147 MLXSW_REG_SFDF_FLUSH_PER_NVE_AND_FID, 1148 }; 1149 1150 /* reg_sfdf_flush_type 1151 * Flush type. 1152 * 0 - All SWID dynamic entries are flushed. 1153 * 1 - All FID dynamic entries are flushed. 1154 * 2 - All dynamic entries pointing to port are flushed. 1155 * 3 - All FID dynamic entries pointing to port are flushed. 1156 * 4 - All dynamic entries pointing to LAG are flushed. 1157 * 5 - All FID dynamic entries pointing to LAG are flushed. 1158 * 6 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1159 * flushed. 1160 * 7 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1161 * flushed, per FID. 1162 * Access: RW 1163 */ 1164 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4); 1165 1166 /* reg_sfdf_flush_static 1167 * Static. 1168 * 0 - Flush only dynamic entries. 1169 * 1 - Flush both dynamic and static entries. 1170 * Access: RW 1171 */ 1172 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1); 1173 1174 static inline void mlxsw_reg_sfdf_pack(char *payload, 1175 enum mlxsw_reg_sfdf_flush_type type) 1176 { 1177 MLXSW_REG_ZERO(sfdf, payload); 1178 mlxsw_reg_sfdf_flush_type_set(payload, type); 1179 mlxsw_reg_sfdf_flush_static_set(payload, true); 1180 } 1181 1182 /* reg_sfdf_fid 1183 * FID to flush. 1184 * Access: RW 1185 */ 1186 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16); 1187 1188 /* reg_sfdf_system_port 1189 * Port to flush. 1190 * Access: RW 1191 */ 1192 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16); 1193 1194 /* reg_sfdf_port_fid_system_port 1195 * Port to flush, pointed to by FID. 1196 * Access: RW 1197 */ 1198 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16); 1199 1200 /* reg_sfdf_lag_id 1201 * LAG ID to flush. 1202 * Access: RW 1203 */ 1204 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10); 1205 1206 /* reg_sfdf_lag_fid_lag_id 1207 * LAG ID to flush, pointed to by FID. 1208 * Access: RW 1209 */ 1210 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10); 1211 1212 /* SLDR - Switch LAG Descriptor Register 1213 * ----------------------------------------- 1214 * The switch LAG descriptor register is populated by LAG descriptors. 1215 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to 1216 * max_lag-1. 1217 */ 1218 #define MLXSW_REG_SLDR_ID 0x2014 1219 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */ 1220 1221 MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN); 1222 1223 enum mlxsw_reg_sldr_op { 1224 /* Indicates a creation of a new LAG-ID, lag_id must be valid */ 1225 MLXSW_REG_SLDR_OP_LAG_CREATE, 1226 MLXSW_REG_SLDR_OP_LAG_DESTROY, 1227 /* Ports that appear in the list have the Distributor enabled */ 1228 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST, 1229 /* Removes ports from the disributor list */ 1230 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST, 1231 }; 1232 1233 /* reg_sldr_op 1234 * Operation. 1235 * Access: RW 1236 */ 1237 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3); 1238 1239 /* reg_sldr_lag_id 1240 * LAG identifier. The lag_id is the index into the LAG descriptor table. 1241 * Access: Index 1242 */ 1243 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10); 1244 1245 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id) 1246 { 1247 MLXSW_REG_ZERO(sldr, payload); 1248 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE); 1249 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1250 } 1251 1252 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id) 1253 { 1254 MLXSW_REG_ZERO(sldr, payload); 1255 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY); 1256 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1257 } 1258 1259 /* reg_sldr_num_ports 1260 * The number of member ports of the LAG. 1261 * Reserved for Create / Destroy operations 1262 * For Add / Remove operations - indicates the number of ports in the list. 1263 * Access: RW 1264 */ 1265 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8); 1266 1267 /* reg_sldr_system_port 1268 * System port. 1269 * Access: RW 1270 */ 1271 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false); 1272 1273 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id, 1274 u16 local_port) 1275 { 1276 MLXSW_REG_ZERO(sldr, payload); 1277 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST); 1278 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1279 mlxsw_reg_sldr_num_ports_set(payload, 1); 1280 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1281 } 1282 1283 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id, 1284 u16 local_port) 1285 { 1286 MLXSW_REG_ZERO(sldr, payload); 1287 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST); 1288 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1289 mlxsw_reg_sldr_num_ports_set(payload, 1); 1290 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1291 } 1292 1293 /* SLCR - Switch LAG Configuration 2 Register 1294 * ------------------------------------------- 1295 * The Switch LAG Configuration register is used for configuring the 1296 * LAG properties of the switch. 1297 */ 1298 #define MLXSW_REG_SLCR_ID 0x2015 1299 #define MLXSW_REG_SLCR_LEN 0x10 1300 1301 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN); 1302 1303 enum mlxsw_reg_slcr_pp { 1304 /* Global Configuration (for all ports) */ 1305 MLXSW_REG_SLCR_PP_GLOBAL, 1306 /* Per port configuration, based on local_port field */ 1307 MLXSW_REG_SLCR_PP_PER_PORT, 1308 }; 1309 1310 /* reg_slcr_pp 1311 * Per Port Configuration 1312 * Note: Reading at Global mode results in reading port 1 configuration. 1313 * Access: Index 1314 */ 1315 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1); 1316 1317 /* reg_slcr_local_port 1318 * Local port number 1319 * Supported from CPU port 1320 * Not supported from router port 1321 * Reserved when pp = Global Configuration 1322 * Access: Index 1323 */ 1324 MLXSW_ITEM32_LP(reg, slcr, 0x00, 16, 0x00, 12); 1325 1326 enum mlxsw_reg_slcr_type { 1327 MLXSW_REG_SLCR_TYPE_CRC, /* default */ 1328 MLXSW_REG_SLCR_TYPE_XOR, 1329 MLXSW_REG_SLCR_TYPE_RANDOM, 1330 }; 1331 1332 /* reg_slcr_type 1333 * Hash type 1334 * Access: RW 1335 */ 1336 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4); 1337 1338 /* Ingress port */ 1339 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0) 1340 /* SMAC - for IPv4 and IPv6 packets */ 1341 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1) 1342 /* SMAC - for non-IP packets */ 1343 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2) 1344 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \ 1345 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \ 1346 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP) 1347 /* DMAC - for IPv4 and IPv6 packets */ 1348 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3) 1349 /* DMAC - for non-IP packets */ 1350 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4) 1351 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \ 1352 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \ 1353 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP) 1354 /* Ethertype - for IPv4 and IPv6 packets */ 1355 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5) 1356 /* Ethertype - for non-IP packets */ 1357 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6) 1358 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \ 1359 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \ 1360 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP) 1361 /* VLAN ID - for IPv4 and IPv6 packets */ 1362 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7) 1363 /* VLAN ID - for non-IP packets */ 1364 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8) 1365 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \ 1366 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \ 1367 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP) 1368 /* Source IP address (can be IPv4 or IPv6) */ 1369 #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9) 1370 /* Destination IP address (can be IPv4 or IPv6) */ 1371 #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10) 1372 /* TCP/UDP source port */ 1373 #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11) 1374 /* TCP/UDP destination port*/ 1375 #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12) 1376 /* IPv4 Protocol/IPv6 Next Header */ 1377 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13) 1378 /* IPv6 Flow label */ 1379 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14) 1380 /* SID - FCoE source ID */ 1381 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15) 1382 /* DID - FCoE destination ID */ 1383 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16) 1384 /* OXID - FCoE originator exchange ID */ 1385 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17) 1386 /* Destination QP number - for RoCE packets */ 1387 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19) 1388 1389 /* reg_slcr_lag_hash 1390 * LAG hashing configuration. This is a bitmask, in which each set 1391 * bit includes the corresponding item in the LAG hash calculation. 1392 * The default lag_hash contains SMAC, DMAC, VLANID and 1393 * Ethertype (for all packet types). 1394 * Access: RW 1395 */ 1396 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20); 1397 1398 /* reg_slcr_seed 1399 * LAG seed value. The seed is the same for all ports. 1400 * Access: RW 1401 */ 1402 MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32); 1403 1404 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed) 1405 { 1406 MLXSW_REG_ZERO(slcr, payload); 1407 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL); 1408 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC); 1409 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash); 1410 mlxsw_reg_slcr_seed_set(payload, seed); 1411 } 1412 1413 /* SLCOR - Switch LAG Collector Register 1414 * ------------------------------------- 1415 * The Switch LAG Collector register controls the Local Port membership 1416 * in a LAG and enablement of the collector. 1417 */ 1418 #define MLXSW_REG_SLCOR_ID 0x2016 1419 #define MLXSW_REG_SLCOR_LEN 0x10 1420 1421 MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN); 1422 1423 enum mlxsw_reg_slcor_col { 1424 /* Port is added with collector disabled */ 1425 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT, 1426 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED, 1427 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED, 1428 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT, 1429 }; 1430 1431 /* reg_slcor_col 1432 * Collector configuration 1433 * Access: RW 1434 */ 1435 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2); 1436 1437 /* reg_slcor_local_port 1438 * Local port number 1439 * Not supported for CPU port 1440 * Access: Index 1441 */ 1442 MLXSW_ITEM32_LP(reg, slcor, 0x00, 16, 0x00, 12); 1443 1444 /* reg_slcor_lag_id 1445 * LAG Identifier. Index into the LAG descriptor table. 1446 * Access: Index 1447 */ 1448 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10); 1449 1450 /* reg_slcor_port_index 1451 * Port index in the LAG list. Only valid on Add Port to LAG col. 1452 * Valid range is from 0 to cap_max_lag_members-1 1453 * Access: RW 1454 */ 1455 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10); 1456 1457 static inline void mlxsw_reg_slcor_pack(char *payload, 1458 u16 local_port, u16 lag_id, 1459 enum mlxsw_reg_slcor_col col) 1460 { 1461 MLXSW_REG_ZERO(slcor, payload); 1462 mlxsw_reg_slcor_col_set(payload, col); 1463 mlxsw_reg_slcor_local_port_set(payload, local_port); 1464 mlxsw_reg_slcor_lag_id_set(payload, lag_id); 1465 } 1466 1467 static inline void mlxsw_reg_slcor_port_add_pack(char *payload, 1468 u16 local_port, u16 lag_id, 1469 u8 port_index) 1470 { 1471 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1472 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT); 1473 mlxsw_reg_slcor_port_index_set(payload, port_index); 1474 } 1475 1476 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload, 1477 u16 local_port, u16 lag_id) 1478 { 1479 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1480 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT); 1481 } 1482 1483 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload, 1484 u16 local_port, u16 lag_id) 1485 { 1486 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1487 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1488 } 1489 1490 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload, 1491 u16 local_port, u16 lag_id) 1492 { 1493 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1494 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1495 } 1496 1497 /* SPMLR - Switch Port MAC Learning Register 1498 * ----------------------------------------- 1499 * Controls the Switch MAC learning policy per port. 1500 */ 1501 #define MLXSW_REG_SPMLR_ID 0x2018 1502 #define MLXSW_REG_SPMLR_LEN 0x8 1503 1504 MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN); 1505 1506 /* reg_spmlr_local_port 1507 * Local port number. 1508 * Access: Index 1509 */ 1510 MLXSW_ITEM32_LP(reg, spmlr, 0x00, 16, 0x00, 12); 1511 1512 /* reg_spmlr_sub_port 1513 * Virtual port within the physical port. 1514 * Should be set to 0 when virtual ports are not enabled on the port. 1515 * Access: Index 1516 */ 1517 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8); 1518 1519 enum mlxsw_reg_spmlr_learn_mode { 1520 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0, 1521 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2, 1522 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3, 1523 }; 1524 1525 /* reg_spmlr_learn_mode 1526 * Learning mode on the port. 1527 * 0 - Learning disabled. 1528 * 2 - Learning enabled. 1529 * 3 - Security mode. 1530 * 1531 * In security mode the switch does not learn MACs on the port, but uses the 1532 * SMAC to see if it exists on another ingress port. If so, the packet is 1533 * classified as a bad packet and is discarded unless the software registers 1534 * to receive port security error packets usign HPKT. 1535 */ 1536 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2); 1537 1538 static inline void mlxsw_reg_spmlr_pack(char *payload, u16 local_port, 1539 enum mlxsw_reg_spmlr_learn_mode mode) 1540 { 1541 MLXSW_REG_ZERO(spmlr, payload); 1542 mlxsw_reg_spmlr_local_port_set(payload, local_port); 1543 mlxsw_reg_spmlr_sub_port_set(payload, 0); 1544 mlxsw_reg_spmlr_learn_mode_set(payload, mode); 1545 } 1546 1547 /* SVFA - Switch VID to FID Allocation Register 1548 * -------------------------------------------- 1549 * Controls the VID to FID mapping and {Port, VID} to FID mapping for 1550 * virtualized ports. 1551 */ 1552 #define MLXSW_REG_SVFA_ID 0x201C 1553 #define MLXSW_REG_SVFA_LEN 0x18 1554 1555 MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN); 1556 1557 /* reg_svfa_swid 1558 * Switch partition ID. 1559 * Access: Index 1560 */ 1561 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8); 1562 1563 /* reg_svfa_local_port 1564 * Local port number. 1565 * Access: Index 1566 * 1567 * Note: Reserved for 802.1Q FIDs. 1568 */ 1569 MLXSW_ITEM32_LP(reg, svfa, 0x00, 16, 0x00, 12); 1570 1571 enum mlxsw_reg_svfa_mt { 1572 MLXSW_REG_SVFA_MT_VID_TO_FID, 1573 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, 1574 MLXSW_REG_SVFA_MT_VNI_TO_FID, 1575 }; 1576 1577 /* reg_svfa_mapping_table 1578 * Mapping table: 1579 * 0 - VID to FID 1580 * 1 - {Port, VID} to FID 1581 * Access: Index 1582 * 1583 * Note: Reserved for SwitchX-2. 1584 */ 1585 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3); 1586 1587 /* reg_svfa_v 1588 * Valid. 1589 * Valid if set. 1590 * Access: RW 1591 * 1592 * Note: Reserved for SwitchX-2. 1593 */ 1594 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1); 1595 1596 /* reg_svfa_fid 1597 * Filtering ID. 1598 * Access: RW 1599 */ 1600 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16); 1601 1602 /* reg_svfa_vid 1603 * VLAN ID. 1604 * Access: Index 1605 */ 1606 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12); 1607 1608 /* reg_svfa_counter_set_type 1609 * Counter set type for flow counters. 1610 * Access: RW 1611 * 1612 * Note: Reserved for SwitchX-2. 1613 */ 1614 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8); 1615 1616 /* reg_svfa_counter_index 1617 * Counter index for flow counters. 1618 * Access: RW 1619 * 1620 * Note: Reserved for SwitchX-2. 1621 */ 1622 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24); 1623 1624 /* reg_svfa_vni 1625 * Virtual Network Identifier. 1626 * Access: Index 1627 * 1628 * Note: Reserved when mapping_table is not 2 (VNI mapping table). 1629 */ 1630 MLXSW_ITEM32(reg, svfa, vni, 0x10, 0, 24); 1631 1632 /* reg_svfa_irif_v 1633 * Ingress RIF valid. 1634 * 0 - Ingress RIF is not valid, no ingress RIF assigned. 1635 * 1 - Ingress RIF valid. 1636 * Must not be set for a non enabled RIF. 1637 * Access: RW 1638 * 1639 * Note: Reserved when legacy bridge model is used. 1640 */ 1641 MLXSW_ITEM32(reg, svfa, irif_v, 0x14, 24, 1); 1642 1643 /* reg_svfa_irif 1644 * Ingress RIF (Router Interface). 1645 * Range is 0..cap_max_router_interfaces-1. 1646 * Access: RW 1647 * 1648 * Note: Reserved when legacy bridge model is used and when irif_v=0. 1649 */ 1650 MLXSW_ITEM32(reg, svfa, irif, 0x14, 0, 16); 1651 1652 static inline void __mlxsw_reg_svfa_pack(char *payload, 1653 enum mlxsw_reg_svfa_mt mt, bool valid, 1654 u16 fid, bool irif_v, u16 irif) 1655 { 1656 MLXSW_REG_ZERO(svfa, payload); 1657 mlxsw_reg_svfa_swid_set(payload, 0); 1658 mlxsw_reg_svfa_mapping_table_set(payload, mt); 1659 mlxsw_reg_svfa_v_set(payload, valid); 1660 mlxsw_reg_svfa_fid_set(payload, fid); 1661 mlxsw_reg_svfa_irif_v_set(payload, irif_v); 1662 mlxsw_reg_svfa_irif_set(payload, irif_v ? irif : 0); 1663 } 1664 1665 static inline void mlxsw_reg_svfa_port_vid_pack(char *payload, u16 local_port, 1666 bool valid, u16 fid, u16 vid, 1667 bool irif_v, u16 irif) 1668 { 1669 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID; 1670 1671 __mlxsw_reg_svfa_pack(payload, mt, valid, fid, irif_v, irif); 1672 mlxsw_reg_svfa_local_port_set(payload, local_port); 1673 mlxsw_reg_svfa_vid_set(payload, vid); 1674 } 1675 1676 static inline void mlxsw_reg_svfa_vid_pack(char *payload, bool valid, u16 fid, 1677 u16 vid, bool irif_v, u16 irif) 1678 { 1679 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_VID_TO_FID; 1680 1681 __mlxsw_reg_svfa_pack(payload, mt, valid, fid, irif_v, irif); 1682 mlxsw_reg_svfa_vid_set(payload, vid); 1683 } 1684 1685 static inline void mlxsw_reg_svfa_vni_pack(char *payload, bool valid, u16 fid, 1686 u32 vni, bool irif_v, u16 irif) 1687 { 1688 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_VNI_TO_FID; 1689 1690 __mlxsw_reg_svfa_pack(payload, mt, valid, fid, irif_v, irif); 1691 mlxsw_reg_svfa_vni_set(payload, vni); 1692 } 1693 1694 /* SPVTR - Switch Port VLAN Stacking Register 1695 * ------------------------------------------ 1696 * The Switch Port VLAN Stacking register configures the VLAN mode of the port 1697 * to enable VLAN stacking. 1698 */ 1699 #define MLXSW_REG_SPVTR_ID 0x201D 1700 #define MLXSW_REG_SPVTR_LEN 0x10 1701 1702 MLXSW_REG_DEFINE(spvtr, MLXSW_REG_SPVTR_ID, MLXSW_REG_SPVTR_LEN); 1703 1704 /* reg_spvtr_tport 1705 * Port is tunnel port. 1706 * Access: Index 1707 * 1708 * Note: Reserved when SwitchX/-2 or Spectrum-1. 1709 */ 1710 MLXSW_ITEM32(reg, spvtr, tport, 0x00, 24, 1); 1711 1712 /* reg_spvtr_local_port 1713 * When tport = 0: local port number (Not supported from/to CPU). 1714 * When tport = 1: tunnel port. 1715 * Access: Index 1716 */ 1717 MLXSW_ITEM32_LP(reg, spvtr, 0x00, 16, 0x00, 12); 1718 1719 /* reg_spvtr_ippe 1720 * Ingress Port Prio Mode Update Enable. 1721 * When set, the Port Prio Mode is updated with the provided ipprio_mode field. 1722 * Reserved on Get operations. 1723 * Access: OP 1724 */ 1725 MLXSW_ITEM32(reg, spvtr, ippe, 0x04, 31, 1); 1726 1727 /* reg_spvtr_ipve 1728 * Ingress Port VID Mode Update Enable. 1729 * When set, the Ingress Port VID Mode is updated with the provided ipvid_mode 1730 * field. 1731 * Reserved on Get operations. 1732 * Access: OP 1733 */ 1734 MLXSW_ITEM32(reg, spvtr, ipve, 0x04, 30, 1); 1735 1736 /* reg_spvtr_epve 1737 * Egress Port VID Mode Update Enable. 1738 * When set, the Egress Port VID Mode is updated with the provided epvid_mode 1739 * field. 1740 * Access: OP 1741 */ 1742 MLXSW_ITEM32(reg, spvtr, epve, 0x04, 29, 1); 1743 1744 /* reg_spvtr_ipprio_mode 1745 * Ingress Port Priority Mode. 1746 * This controls the PCP and DEI of the new outer VLAN 1747 * Note: for SwitchX/-2 the DEI is not affected. 1748 * 0: use port default PCP and DEI (configured by QPDPC). 1749 * 1: use C-VLAN PCP and DEI. 1750 * Has no effect when ipvid_mode = 0. 1751 * Reserved when tport = 1. 1752 * Access: RW 1753 */ 1754 MLXSW_ITEM32(reg, spvtr, ipprio_mode, 0x04, 20, 4); 1755 1756 enum mlxsw_reg_spvtr_ipvid_mode { 1757 /* IEEE Compliant PVID (default) */ 1758 MLXSW_REG_SPVTR_IPVID_MODE_IEEE_COMPLIANT_PVID, 1759 /* Push VLAN (for VLAN stacking, except prio tagged packets) */ 1760 MLXSW_REG_SPVTR_IPVID_MODE_PUSH_VLAN_FOR_UNTAGGED_PACKET, 1761 /* Always push VLAN (also for prio tagged packets) */ 1762 MLXSW_REG_SPVTR_IPVID_MODE_ALWAYS_PUSH_VLAN, 1763 }; 1764 1765 /* reg_spvtr_ipvid_mode 1766 * Ingress Port VLAN-ID Mode. 1767 * For Spectrum family, this affects the values of SPVM.i 1768 * Access: RW 1769 */ 1770 MLXSW_ITEM32(reg, spvtr, ipvid_mode, 0x04, 16, 4); 1771 1772 enum mlxsw_reg_spvtr_epvid_mode { 1773 /* IEEE Compliant VLAN membership */ 1774 MLXSW_REG_SPVTR_EPVID_MODE_IEEE_COMPLIANT_VLAN_MEMBERSHIP, 1775 /* Pop VLAN (for VLAN stacking) */ 1776 MLXSW_REG_SPVTR_EPVID_MODE_POP_VLAN, 1777 }; 1778 1779 /* reg_spvtr_epvid_mode 1780 * Egress Port VLAN-ID Mode. 1781 * For Spectrum family, this affects the values of SPVM.e,u,pt. 1782 * Access: WO 1783 */ 1784 MLXSW_ITEM32(reg, spvtr, epvid_mode, 0x04, 0, 4); 1785 1786 static inline void mlxsw_reg_spvtr_pack(char *payload, bool tport, 1787 u16 local_port, 1788 enum mlxsw_reg_spvtr_ipvid_mode ipvid_mode) 1789 { 1790 MLXSW_REG_ZERO(spvtr, payload); 1791 mlxsw_reg_spvtr_tport_set(payload, tport); 1792 mlxsw_reg_spvtr_local_port_set(payload, local_port); 1793 mlxsw_reg_spvtr_ipvid_mode_set(payload, ipvid_mode); 1794 mlxsw_reg_spvtr_ipve_set(payload, true); 1795 } 1796 1797 /* SVPE - Switch Virtual-Port Enabling Register 1798 * -------------------------------------------- 1799 * Enables port virtualization. 1800 */ 1801 #define MLXSW_REG_SVPE_ID 0x201E 1802 #define MLXSW_REG_SVPE_LEN 0x4 1803 1804 MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN); 1805 1806 /* reg_svpe_local_port 1807 * Local port number 1808 * Access: Index 1809 * 1810 * Note: CPU port is not supported (uses VLAN mode only). 1811 */ 1812 MLXSW_ITEM32_LP(reg, svpe, 0x00, 16, 0x00, 12); 1813 1814 /* reg_svpe_vp_en 1815 * Virtual port enable. 1816 * 0 - Disable, VLAN mode (VID to FID). 1817 * 1 - Enable, Virtual port mode ({Port, VID} to FID). 1818 * Access: RW 1819 */ 1820 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1); 1821 1822 static inline void mlxsw_reg_svpe_pack(char *payload, u16 local_port, 1823 bool enable) 1824 { 1825 MLXSW_REG_ZERO(svpe, payload); 1826 mlxsw_reg_svpe_local_port_set(payload, local_port); 1827 mlxsw_reg_svpe_vp_en_set(payload, enable); 1828 } 1829 1830 /* SFMR - Switch FID Management Register 1831 * ------------------------------------- 1832 * Creates and configures FIDs. 1833 */ 1834 #define MLXSW_REG_SFMR_ID 0x201F 1835 #define MLXSW_REG_SFMR_LEN 0x30 1836 1837 MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN); 1838 1839 enum mlxsw_reg_sfmr_op { 1840 MLXSW_REG_SFMR_OP_CREATE_FID, 1841 MLXSW_REG_SFMR_OP_DESTROY_FID, 1842 }; 1843 1844 /* reg_sfmr_op 1845 * Operation. 1846 * 0 - Create or edit FID. 1847 * 1 - Destroy FID. 1848 * Access: WO 1849 */ 1850 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4); 1851 1852 /* reg_sfmr_fid 1853 * Filtering ID. 1854 * Access: Index 1855 */ 1856 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16); 1857 1858 /* reg_sfmr_flood_rsp 1859 * Router sub-port flooding table. 1860 * 0 - Regular flooding table. 1861 * 1 - Router sub-port flooding table. For this FID the flooding is per 1862 * router-sub-port local_port. Must not be set for a FID which is not a 1863 * router-sub-port and must be set prior to enabling the relevant RIF. 1864 * Access: RW 1865 * 1866 * Note: Reserved when legacy bridge model is used. 1867 * Reserved when CONFIG_PROFILE.flood_mode = CFF. 1868 */ 1869 MLXSW_ITEM32(reg, sfmr, flood_rsp, 0x08, 31, 1); 1870 1871 /* reg_sfmr_flood_bridge_type 1872 * Flood bridge type (see SFGC.bridge_type). 1873 * 0 - type_0. 1874 * 1 - type_1. 1875 * Access: RW 1876 * 1877 * Note: Reserved when legacy bridge model is used and when flood_rsp=1. 1878 * Reserved when CONFIG_PROFILE.flood_mode = CFF 1879 */ 1880 MLXSW_ITEM32(reg, sfmr, flood_bridge_type, 0x08, 28, 1); 1881 1882 /* reg_sfmr_fid_offset 1883 * FID offset. 1884 * Used to point into the flooding table selected by SFGC register if 1885 * the table is of type FID-Offset. Otherwise, this field is reserved. 1886 * Access: RW 1887 * 1888 * Note: Reserved when CONFIG_PROFILE.flood_mode = CFF 1889 */ 1890 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16); 1891 1892 /* reg_sfmr_vtfp 1893 * Valid Tunnel Flood Pointer. 1894 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL. 1895 * Access: RW 1896 * 1897 * Note: Reserved for 802.1Q FIDs. 1898 */ 1899 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1); 1900 1901 /* reg_sfmr_nve_tunnel_flood_ptr 1902 * Underlay Flooding and BC Pointer. 1903 * Used as a pointer to the first entry of the group based link lists of 1904 * flooding or BC entries (for NVE tunnels). 1905 * Access: RW 1906 */ 1907 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24); 1908 1909 /* reg_sfmr_vv 1910 * VNI Valid. 1911 * If not set, then vni is reserved. 1912 * Access: RW 1913 * 1914 * Note: Reserved for 802.1Q FIDs. 1915 */ 1916 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1); 1917 1918 /* reg_sfmr_vni 1919 * Virtual Network Identifier. 1920 * When legacy bridge model is used, a given VNI can only be assigned to one 1921 * FID. When unified bridge model is used, it configures only the FID->VNI, 1922 * the VNI->FID is done by SVFA. 1923 * Access: RW 1924 */ 1925 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24); 1926 1927 /* reg_sfmr_irif_v 1928 * Ingress RIF valid. 1929 * 0 - Ingress RIF is not valid, no ingress RIF assigned. 1930 * 1 - Ingress RIF valid. 1931 * Must not be set for a non valid RIF. 1932 * Access: RW 1933 * 1934 * Note: Reserved when legacy bridge model is used. 1935 */ 1936 MLXSW_ITEM32(reg, sfmr, irif_v, 0x14, 24, 1); 1937 1938 /* reg_sfmr_irif 1939 * Ingress RIF (Router Interface). 1940 * Range is 0..cap_max_router_interfaces-1. 1941 * Access: RW 1942 * 1943 * Note: Reserved when legacy bridge model is used and when irif_v=0. 1944 */ 1945 MLXSW_ITEM32(reg, sfmr, irif, 0x14, 0, 16); 1946 1947 /* reg_sfmr_cff_mid_base 1948 * Pointer to PGT table. 1949 * Range: 0..(cap_max_pgt-1) 1950 * Access: RW 1951 * 1952 * Note: Reserved when SwitchX/-2 and Spectrum-1. 1953 * Supported when CONFIG_PROFILE.flood_mode = CFF. 1954 */ 1955 MLXSW_ITEM32(reg, sfmr, cff_mid_base, 0x20, 0, 16); 1956 1957 /* reg_sfmr_nve_flood_prf_id 1958 * FID flooding profile_id for NVE Encap 1959 * Range 0..(max_cap_nve_flood_prf-1) 1960 * Access: RW 1961 * 1962 * Note: Reserved when SwitchX/-2 and Spectrum-1 1963 */ 1964 MLXSW_ITEM32(reg, sfmr, nve_flood_prf_id, 0x24, 8, 2); 1965 1966 /* reg_sfmr_cff_prf_id 1967 * Compressed Fid Flooding profile_id 1968 * Range 0..(max_cap_nve_flood_prf-1) 1969 * Access: RW 1970 * 1971 * Note: Reserved when SwitchX/-2 and Spectrum-1 1972 * Supported only when CONFIG_PROFLE.flood_mode = CFF. 1973 */ 1974 MLXSW_ITEM32(reg, sfmr, cff_prf_id, 0x24, 0, 2); 1975 1976 /* reg_sfmr_smpe_valid 1977 * SMPE is valid. 1978 * Access: RW 1979 * 1980 * Note: Reserved when legacy bridge model is used, when flood_rsp=1 and on 1981 * Spectrum-1. 1982 */ 1983 MLXSW_ITEM32(reg, sfmr, smpe_valid, 0x28, 20, 1); 1984 1985 /* reg_sfmr_smpe 1986 * Switch multicast port to egress VID. 1987 * Range is 0..cap_max_rmpe-1 1988 * Access: RW 1989 * 1990 * Note: Reserved when legacy bridge model is used, when flood_rsp=1 and on 1991 * Spectrum-1. 1992 */ 1993 MLXSW_ITEM32(reg, sfmr, smpe, 0x28, 0, 16); 1994 1995 static inline void mlxsw_reg_sfmr_pack(char *payload, 1996 enum mlxsw_reg_sfmr_op op, u16 fid, 1997 bool smpe_valid, u16 smpe) 1998 { 1999 MLXSW_REG_ZERO(sfmr, payload); 2000 mlxsw_reg_sfmr_op_set(payload, op); 2001 mlxsw_reg_sfmr_fid_set(payload, fid); 2002 mlxsw_reg_sfmr_smpe_valid_set(payload, smpe_valid); 2003 mlxsw_reg_sfmr_smpe_set(payload, smpe); 2004 } 2005 2006 /* SPVMLR - Switch Port VLAN MAC Learning Register 2007 * ----------------------------------------------- 2008 * Controls the switch MAC learning policy per {Port, VID}. 2009 */ 2010 #define MLXSW_REG_SPVMLR_ID 0x2020 2011 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */ 2012 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */ 2013 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255 2014 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \ 2015 MLXSW_REG_SPVMLR_REC_LEN * \ 2016 MLXSW_REG_SPVMLR_REC_MAX_COUNT) 2017 2018 MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN); 2019 2020 /* reg_spvmlr_local_port 2021 * Local ingress port. 2022 * Access: Index 2023 * 2024 * Note: CPU port is not supported. 2025 */ 2026 MLXSW_ITEM32_LP(reg, spvmlr, 0x00, 16, 0x00, 12); 2027 2028 /* reg_spvmlr_num_rec 2029 * Number of records to update. 2030 * Access: OP 2031 */ 2032 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8); 2033 2034 /* reg_spvmlr_rec_learn_enable 2035 * 0 - Disable learning for {Port, VID}. 2036 * 1 - Enable learning for {Port, VID}. 2037 * Access: RW 2038 */ 2039 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN, 2040 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 2041 2042 /* reg_spvmlr_rec_vid 2043 * VLAN ID to be added/removed from port or for querying. 2044 * Access: Index 2045 */ 2046 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12, 2047 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 2048 2049 static inline void mlxsw_reg_spvmlr_pack(char *payload, u16 local_port, 2050 u16 vid_begin, u16 vid_end, 2051 bool learn_enable) 2052 { 2053 int num_rec = vid_end - vid_begin + 1; 2054 int i; 2055 2056 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT); 2057 2058 MLXSW_REG_ZERO(spvmlr, payload); 2059 mlxsw_reg_spvmlr_local_port_set(payload, local_port); 2060 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec); 2061 2062 for (i = 0; i < num_rec; i++) { 2063 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable); 2064 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i); 2065 } 2066 } 2067 2068 /* SPFSR - Switch Port FDB Security Register 2069 * ----------------------------------------- 2070 * Configures the security mode per port. 2071 */ 2072 #define MLXSW_REG_SPFSR_ID 0x2023 2073 #define MLXSW_REG_SPFSR_LEN 0x08 2074 2075 MLXSW_REG_DEFINE(spfsr, MLXSW_REG_SPFSR_ID, MLXSW_REG_SPFSR_LEN); 2076 2077 /* reg_spfsr_local_port 2078 * Local port. 2079 * Access: Index 2080 * 2081 * Note: not supported for CPU port. 2082 */ 2083 MLXSW_ITEM32_LP(reg, spfsr, 0x00, 16, 0x00, 12); 2084 2085 /* reg_spfsr_security 2086 * Security checks. 2087 * 0: disabled (default) 2088 * 1: enabled 2089 * Access: RW 2090 */ 2091 MLXSW_ITEM32(reg, spfsr, security, 0x04, 31, 1); 2092 2093 static inline void mlxsw_reg_spfsr_pack(char *payload, u16 local_port, 2094 bool security) 2095 { 2096 MLXSW_REG_ZERO(spfsr, payload); 2097 mlxsw_reg_spfsr_local_port_set(payload, local_port); 2098 mlxsw_reg_spfsr_security_set(payload, security); 2099 } 2100 2101 /* SPVC - Switch Port VLAN Classification Register 2102 * ----------------------------------------------- 2103 * Configures the port to identify packets as untagged / single tagged / 2104 * double packets based on the packet EtherTypes. 2105 * Ethertype IDs are configured by SVER. 2106 */ 2107 #define MLXSW_REG_SPVC_ID 0x2026 2108 #define MLXSW_REG_SPVC_LEN 0x0C 2109 2110 MLXSW_REG_DEFINE(spvc, MLXSW_REG_SPVC_ID, MLXSW_REG_SPVC_LEN); 2111 2112 /* reg_spvc_local_port 2113 * Local port. 2114 * Access: Index 2115 * 2116 * Note: applies both to Rx port and Tx port, so if a packet traverses 2117 * through Rx port i and a Tx port j then port i and port j must have the 2118 * same configuration. 2119 */ 2120 MLXSW_ITEM32_LP(reg, spvc, 0x00, 16, 0x00, 12); 2121 2122 /* reg_spvc_inner_et2 2123 * Vlan Tag1 EtherType2 enable. 2124 * Packet is initially classified as double VLAN Tag if in addition to 2125 * being classified with a tag0 VLAN Tag its tag1 EtherType value is 2126 * equal to ether_type2. 2127 * 0: disable (default) 2128 * 1: enable 2129 * Access: RW 2130 */ 2131 MLXSW_ITEM32(reg, spvc, inner_et2, 0x08, 17, 1); 2132 2133 /* reg_spvc_et2 2134 * Vlan Tag0 EtherType2 enable. 2135 * Packet is initially classified as VLAN Tag if its tag0 EtherType is 2136 * equal to ether_type2. 2137 * 0: disable (default) 2138 * 1: enable 2139 * Access: RW 2140 */ 2141 MLXSW_ITEM32(reg, spvc, et2, 0x08, 16, 1); 2142 2143 /* reg_spvc_inner_et1 2144 * Vlan Tag1 EtherType1 enable. 2145 * Packet is initially classified as double VLAN Tag if in addition to 2146 * being classified with a tag0 VLAN Tag its tag1 EtherType value is 2147 * equal to ether_type1. 2148 * 0: disable 2149 * 1: enable (default) 2150 * Access: RW 2151 */ 2152 MLXSW_ITEM32(reg, spvc, inner_et1, 0x08, 9, 1); 2153 2154 /* reg_spvc_et1 2155 * Vlan Tag0 EtherType1 enable. 2156 * Packet is initially classified as VLAN Tag if its tag0 EtherType is 2157 * equal to ether_type1. 2158 * 0: disable 2159 * 1: enable (default) 2160 * Access: RW 2161 */ 2162 MLXSW_ITEM32(reg, spvc, et1, 0x08, 8, 1); 2163 2164 /* reg_inner_et0 2165 * Vlan Tag1 EtherType0 enable. 2166 * Packet is initially classified as double VLAN Tag if in addition to 2167 * being classified with a tag0 VLAN Tag its tag1 EtherType value is 2168 * equal to ether_type0. 2169 * 0: disable 2170 * 1: enable (default) 2171 * Access: RW 2172 */ 2173 MLXSW_ITEM32(reg, spvc, inner_et0, 0x08, 1, 1); 2174 2175 /* reg_et0 2176 * Vlan Tag0 EtherType0 enable. 2177 * Packet is initially classified as VLAN Tag if its tag0 EtherType is 2178 * equal to ether_type0. 2179 * 0: disable 2180 * 1: enable (default) 2181 * Access: RW 2182 */ 2183 MLXSW_ITEM32(reg, spvc, et0, 0x08, 0, 1); 2184 2185 static inline void mlxsw_reg_spvc_pack(char *payload, u16 local_port, bool et1, 2186 bool et0) 2187 { 2188 MLXSW_REG_ZERO(spvc, payload); 2189 mlxsw_reg_spvc_local_port_set(payload, local_port); 2190 /* Enable inner_et1 and inner_et0 to enable identification of double 2191 * tagged packets. 2192 */ 2193 mlxsw_reg_spvc_inner_et1_set(payload, 1); 2194 mlxsw_reg_spvc_inner_et0_set(payload, 1); 2195 mlxsw_reg_spvc_et1_set(payload, et1); 2196 mlxsw_reg_spvc_et0_set(payload, et0); 2197 } 2198 2199 /* SFFP - Switch FID Flooding Profiles Register 2200 * -------------------------------------------- 2201 * The SFFP register populates the fid flooding profile tables used for the NVE 2202 * flooding and Compressed-FID Flooding (CFF). 2203 * 2204 * Reserved on Spectrum-1. 2205 */ 2206 #define MLXSW_REG_SFFP_ID 0x2029 2207 #define MLXSW_REG_SFFP_LEN 0x0C 2208 2209 MLXSW_REG_DEFINE(sffp, MLXSW_REG_SFFP_ID, MLXSW_REG_SFFP_LEN); 2210 2211 /* reg_sffp_profile_id 2212 * Profile ID a.k.a. SFMR.nve_flood_prf_id or SFMR.cff_prf_id 2213 * Range 0..max_cap_nve_flood_prf-1 2214 * Access: Index 2215 */ 2216 MLXSW_ITEM32(reg, sffp, profile_id, 0x00, 16, 2); 2217 2218 /* reg_sffp_type 2219 * The traffic type to reach the flooding table. 2220 * Same as SFGC.type 2221 * Access: Index 2222 */ 2223 MLXSW_ITEM32(reg, sffp, type, 0x00, 0, 4); 2224 2225 /* reg_sffp_flood_offset 2226 * Flood offset. Offset to add to SFMR.cff_mid_base to get the final PGT address 2227 * for FID flood; or offset to add to SFMR.nve_tunnel_flood_ptr to get KVD 2228 * pointer for NVE underlay. 2229 * Access: RW 2230 */ 2231 MLXSW_ITEM32(reg, sffp, flood_offset, 0x04, 0, 3); 2232 2233 static inline void mlxsw_reg_sffp_pack(char *payload, u8 profile_id, 2234 enum mlxsw_reg_sfgc_type type, 2235 u8 flood_offset) 2236 { 2237 MLXSW_REG_ZERO(sffp, payload); 2238 mlxsw_reg_sffp_profile_id_set(payload, profile_id); 2239 mlxsw_reg_sffp_type_set(payload, type); 2240 mlxsw_reg_sffp_flood_offset_set(payload, flood_offset); 2241 } 2242 2243 /* SPEVET - Switch Port Egress VLAN EtherType 2244 * ------------------------------------------ 2245 * The switch port egress VLAN EtherType configures which EtherType to push at 2246 * egress for packets incoming through a local port for which 'SPVID.egr_et_set' 2247 * is set. 2248 */ 2249 #define MLXSW_REG_SPEVET_ID 0x202A 2250 #define MLXSW_REG_SPEVET_LEN 0x08 2251 2252 MLXSW_REG_DEFINE(spevet, MLXSW_REG_SPEVET_ID, MLXSW_REG_SPEVET_LEN); 2253 2254 /* reg_spevet_local_port 2255 * Egress Local port number. 2256 * Not supported to CPU port. 2257 * Access: Index 2258 */ 2259 MLXSW_ITEM32_LP(reg, spevet, 0x00, 16, 0x00, 12); 2260 2261 /* reg_spevet_et_vlan 2262 * Egress EtherType VLAN to push when SPVID.egr_et_set field set for the packet: 2263 * 0: ether_type0 - (default) 2264 * 1: ether_type1 2265 * 2: ether_type2 2266 * Access: RW 2267 */ 2268 MLXSW_ITEM32(reg, spevet, et_vlan, 0x04, 16, 2); 2269 2270 static inline void mlxsw_reg_spevet_pack(char *payload, u16 local_port, 2271 u8 et_vlan) 2272 { 2273 MLXSW_REG_ZERO(spevet, payload); 2274 mlxsw_reg_spevet_local_port_set(payload, local_port); 2275 mlxsw_reg_spevet_et_vlan_set(payload, et_vlan); 2276 } 2277 2278 /* SMPE - Switch Multicast Port to Egress VID 2279 * ------------------------------------------ 2280 * The switch multicast port to egress VID maps 2281 * {egress_port, SMPE index} -> {VID}. 2282 */ 2283 #define MLXSW_REG_SMPE_ID 0x202B 2284 #define MLXSW_REG_SMPE_LEN 0x0C 2285 2286 MLXSW_REG_DEFINE(smpe, MLXSW_REG_SMPE_ID, MLXSW_REG_SMPE_LEN); 2287 2288 /* reg_smpe_local_port 2289 * Local port number. 2290 * CPU port is not supported. 2291 * Access: Index 2292 */ 2293 MLXSW_ITEM32_LP(reg, smpe, 0x00, 16, 0x00, 12); 2294 2295 /* reg_smpe_smpe_index 2296 * Switch multicast port to egress VID. 2297 * Range is 0..cap_max_rmpe-1. 2298 * Access: Index 2299 */ 2300 MLXSW_ITEM32(reg, smpe, smpe_index, 0x04, 0, 16); 2301 2302 /* reg_smpe_evid 2303 * Egress VID. 2304 * Access: RW 2305 */ 2306 MLXSW_ITEM32(reg, smpe, evid, 0x08, 0, 12); 2307 2308 static inline void mlxsw_reg_smpe_pack(char *payload, u16 local_port, 2309 u16 smpe_index, u16 evid) 2310 { 2311 MLXSW_REG_ZERO(smpe, payload); 2312 mlxsw_reg_smpe_local_port_set(payload, local_port); 2313 mlxsw_reg_smpe_smpe_index_set(payload, smpe_index); 2314 mlxsw_reg_smpe_evid_set(payload, evid); 2315 } 2316 2317 /* SMID-V2 - Switch Multicast ID Version 2 Register 2318 * ------------------------------------------------ 2319 * The MID record maps from a MID (Multicast ID), which is a unique identifier 2320 * of the multicast group within the stacking domain, into a list of local 2321 * ports into which the packet is replicated. 2322 */ 2323 #define MLXSW_REG_SMID2_ID 0x2034 2324 #define MLXSW_REG_SMID2_LEN 0x120 2325 2326 MLXSW_REG_DEFINE(smid2, MLXSW_REG_SMID2_ID, MLXSW_REG_SMID2_LEN); 2327 2328 /* reg_smid2_swid 2329 * Switch partition ID. 2330 * Access: Index 2331 */ 2332 MLXSW_ITEM32(reg, smid2, swid, 0x00, 24, 8); 2333 2334 /* reg_smid2_mid 2335 * Multicast identifier - global identifier that represents the multicast group 2336 * across all devices. 2337 * Access: Index 2338 */ 2339 MLXSW_ITEM32(reg, smid2, mid, 0x00, 0, 16); 2340 2341 /* reg_smid2_smpe_valid 2342 * SMPE is valid. 2343 * When not valid, the egress VID will not be modified by the SMPE table. 2344 * Access: RW 2345 * 2346 * Note: Reserved when legacy bridge model is used and on Spectrum-2. 2347 */ 2348 MLXSW_ITEM32(reg, smid2, smpe_valid, 0x08, 20, 1); 2349 2350 /* reg_smid2_smpe 2351 * Switch multicast port to egress VID. 2352 * Access: RW 2353 * 2354 * Note: Reserved when legacy bridge model is used and on Spectrum-2. 2355 */ 2356 MLXSW_ITEM32(reg, smid2, smpe, 0x08, 0, 16); 2357 2358 /* reg_smid2_port 2359 * Local port memebership (1 bit per port). 2360 * Access: RW 2361 */ 2362 MLXSW_ITEM_BIT_ARRAY(reg, smid2, port, 0x20, 0x80, 1); 2363 2364 /* reg_smid2_port_mask 2365 * Local port mask (1 bit per port). 2366 * Access: WO 2367 */ 2368 MLXSW_ITEM_BIT_ARRAY(reg, smid2, port_mask, 0xA0, 0x80, 1); 2369 2370 static inline void mlxsw_reg_smid2_pack(char *payload, u16 mid, u16 port, 2371 bool set, bool smpe_valid, u16 smpe) 2372 { 2373 MLXSW_REG_ZERO(smid2, payload); 2374 mlxsw_reg_smid2_swid_set(payload, 0); 2375 mlxsw_reg_smid2_mid_set(payload, mid); 2376 mlxsw_reg_smid2_port_set(payload, port, set); 2377 mlxsw_reg_smid2_port_mask_set(payload, port, 1); 2378 mlxsw_reg_smid2_smpe_valid_set(payload, smpe_valid); 2379 mlxsw_reg_smid2_smpe_set(payload, smpe_valid ? smpe : 0); 2380 } 2381 2382 /* CWTP - Congetion WRED ECN TClass Profile 2383 * ---------------------------------------- 2384 * Configures the profiles for queues of egress port and traffic class 2385 */ 2386 #define MLXSW_REG_CWTP_ID 0x2802 2387 #define MLXSW_REG_CWTP_BASE_LEN 0x28 2388 #define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08 2389 #define MLXSW_REG_CWTP_LEN 0x40 2390 2391 MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN); 2392 2393 /* reg_cwtp_local_port 2394 * Local port number 2395 * Not supported for CPU port 2396 * Access: Index 2397 */ 2398 MLXSW_ITEM32_LP(reg, cwtp, 0x00, 16, 0x00, 12); 2399 2400 /* reg_cwtp_traffic_class 2401 * Traffic Class to configure 2402 * Access: Index 2403 */ 2404 MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8); 2405 2406 /* reg_cwtp_profile_min 2407 * Minimum Average Queue Size of the profile in cells. 2408 * Access: RW 2409 */ 2410 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN, 2411 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false); 2412 2413 /* reg_cwtp_profile_percent 2414 * Percentage of WRED and ECN marking for maximum Average Queue size 2415 * Range is 0 to 100, units of integer percentage 2416 * Access: RW 2417 */ 2418 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN, 2419 24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 2420 2421 /* reg_cwtp_profile_max 2422 * Maximum Average Queue size of the profile in cells 2423 * Access: RW 2424 */ 2425 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN, 2426 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 2427 2428 #define MLXSW_REG_CWTP_MIN_VALUE 64 2429 #define MLXSW_REG_CWTP_MAX_PROFILE 2 2430 #define MLXSW_REG_CWTP_DEFAULT_PROFILE 1 2431 2432 static inline void mlxsw_reg_cwtp_pack(char *payload, u16 local_port, 2433 u8 traffic_class) 2434 { 2435 int i; 2436 2437 MLXSW_REG_ZERO(cwtp, payload); 2438 mlxsw_reg_cwtp_local_port_set(payload, local_port); 2439 mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class); 2440 2441 for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) { 2442 mlxsw_reg_cwtp_profile_min_set(payload, i, 2443 MLXSW_REG_CWTP_MIN_VALUE); 2444 mlxsw_reg_cwtp_profile_max_set(payload, i, 2445 MLXSW_REG_CWTP_MIN_VALUE); 2446 } 2447 } 2448 2449 #define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1) 2450 2451 static inline void 2452 mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max, 2453 u32 probability) 2454 { 2455 u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile); 2456 2457 mlxsw_reg_cwtp_profile_min_set(payload, index, min); 2458 mlxsw_reg_cwtp_profile_max_set(payload, index, max); 2459 mlxsw_reg_cwtp_profile_percent_set(payload, index, probability); 2460 } 2461 2462 /* CWTPM - Congestion WRED ECN TClass and Pool Mapping 2463 * --------------------------------------------------- 2464 * The CWTPM register maps each egress port and traffic class to profile num. 2465 */ 2466 #define MLXSW_REG_CWTPM_ID 0x2803 2467 #define MLXSW_REG_CWTPM_LEN 0x44 2468 2469 MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN); 2470 2471 /* reg_cwtpm_local_port 2472 * Local port number 2473 * Not supported for CPU port 2474 * Access: Index 2475 */ 2476 MLXSW_ITEM32_LP(reg, cwtpm, 0x00, 16, 0x00, 12); 2477 2478 /* reg_cwtpm_traffic_class 2479 * Traffic Class to configure 2480 * Access: Index 2481 */ 2482 MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8); 2483 2484 /* reg_cwtpm_ew 2485 * Control enablement of WRED for traffic class: 2486 * 0 - Disable 2487 * 1 - Enable 2488 * Access: RW 2489 */ 2490 MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1); 2491 2492 /* reg_cwtpm_ee 2493 * Control enablement of ECN for traffic class: 2494 * 0 - Disable 2495 * 1 - Enable 2496 * Access: RW 2497 */ 2498 MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1); 2499 2500 /* reg_cwtpm_tcp_g 2501 * TCP Green Profile. 2502 * Index of the profile within {port, traffic class} to use. 2503 * 0 for disabling both WRED and ECN for this type of traffic. 2504 * Access: RW 2505 */ 2506 MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2); 2507 2508 /* reg_cwtpm_tcp_y 2509 * TCP Yellow Profile. 2510 * Index of the profile within {port, traffic class} to use. 2511 * 0 for disabling both WRED and ECN for this type of traffic. 2512 * Access: RW 2513 */ 2514 MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2); 2515 2516 /* reg_cwtpm_tcp_r 2517 * TCP Red Profile. 2518 * Index of the profile within {port, traffic class} to use. 2519 * 0 for disabling both WRED and ECN for this type of traffic. 2520 * Access: RW 2521 */ 2522 MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2); 2523 2524 /* reg_cwtpm_ntcp_g 2525 * Non-TCP Green Profile. 2526 * Index of the profile within {port, traffic class} to use. 2527 * 0 for disabling both WRED and ECN for this type of traffic. 2528 * Access: RW 2529 */ 2530 MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2); 2531 2532 /* reg_cwtpm_ntcp_y 2533 * Non-TCP Yellow Profile. 2534 * Index of the profile within {port, traffic class} to use. 2535 * 0 for disabling both WRED and ECN for this type of traffic. 2536 * Access: RW 2537 */ 2538 MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2); 2539 2540 /* reg_cwtpm_ntcp_r 2541 * Non-TCP Red Profile. 2542 * Index of the profile within {port, traffic class} to use. 2543 * 0 for disabling both WRED and ECN for this type of traffic. 2544 * Access: RW 2545 */ 2546 MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2); 2547 2548 #define MLXSW_REG_CWTPM_RESET_PROFILE 0 2549 2550 static inline void mlxsw_reg_cwtpm_pack(char *payload, u16 local_port, 2551 u8 traffic_class, u8 profile, 2552 bool wred, bool ecn) 2553 { 2554 MLXSW_REG_ZERO(cwtpm, payload); 2555 mlxsw_reg_cwtpm_local_port_set(payload, local_port); 2556 mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class); 2557 mlxsw_reg_cwtpm_ew_set(payload, wred); 2558 mlxsw_reg_cwtpm_ee_set(payload, ecn); 2559 mlxsw_reg_cwtpm_tcp_g_set(payload, profile); 2560 mlxsw_reg_cwtpm_tcp_y_set(payload, profile); 2561 mlxsw_reg_cwtpm_tcp_r_set(payload, profile); 2562 mlxsw_reg_cwtpm_ntcp_g_set(payload, profile); 2563 mlxsw_reg_cwtpm_ntcp_y_set(payload, profile); 2564 mlxsw_reg_cwtpm_ntcp_r_set(payload, profile); 2565 } 2566 2567 /* PGCR - Policy-Engine General Configuration Register 2568 * --------------------------------------------------- 2569 * This register configures general Policy-Engine settings. 2570 */ 2571 #define MLXSW_REG_PGCR_ID 0x3001 2572 #define MLXSW_REG_PGCR_LEN 0x20 2573 2574 MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN); 2575 2576 /* reg_pgcr_default_action_pointer_base 2577 * Default action pointer base. Each region has a default action pointer 2578 * which is equal to default_action_pointer_base + region_id. 2579 * Access: RW 2580 */ 2581 MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24); 2582 2583 static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base) 2584 { 2585 MLXSW_REG_ZERO(pgcr, payload); 2586 mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base); 2587 } 2588 2589 /* PPBT - Policy-Engine Port Binding Table 2590 * --------------------------------------- 2591 * This register is used for configuration of the Port Binding Table. 2592 */ 2593 #define MLXSW_REG_PPBT_ID 0x3002 2594 #define MLXSW_REG_PPBT_LEN 0x14 2595 2596 MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN); 2597 2598 enum mlxsw_reg_pxbt_e { 2599 MLXSW_REG_PXBT_E_IACL, 2600 MLXSW_REG_PXBT_E_EACL, 2601 }; 2602 2603 /* reg_ppbt_e 2604 * Access: Index 2605 */ 2606 MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1); 2607 2608 enum mlxsw_reg_pxbt_op { 2609 MLXSW_REG_PXBT_OP_BIND, 2610 MLXSW_REG_PXBT_OP_UNBIND, 2611 }; 2612 2613 /* reg_ppbt_op 2614 * Access: RW 2615 */ 2616 MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3); 2617 2618 /* reg_ppbt_local_port 2619 * Local port. Not including CPU port. 2620 * Access: Index 2621 */ 2622 MLXSW_ITEM32_LP(reg, ppbt, 0x00, 16, 0x00, 12); 2623 2624 /* reg_ppbt_g 2625 * group - When set, the binding is of an ACL group. When cleared, 2626 * the binding is of an ACL. 2627 * Must be set to 1 for Spectrum. 2628 * Access: RW 2629 */ 2630 MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1); 2631 2632 /* reg_ppbt_acl_info 2633 * ACL/ACL group identifier. If the g bit is set, this field should hold 2634 * the acl_group_id, else it should hold the acl_id. 2635 * Access: RW 2636 */ 2637 MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16); 2638 2639 static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e, 2640 enum mlxsw_reg_pxbt_op op, 2641 u16 local_port, u16 acl_info) 2642 { 2643 MLXSW_REG_ZERO(ppbt, payload); 2644 mlxsw_reg_ppbt_e_set(payload, e); 2645 mlxsw_reg_ppbt_op_set(payload, op); 2646 mlxsw_reg_ppbt_local_port_set(payload, local_port); 2647 mlxsw_reg_ppbt_g_set(payload, true); 2648 mlxsw_reg_ppbt_acl_info_set(payload, acl_info); 2649 } 2650 2651 /* PACL - Policy-Engine ACL Register 2652 * --------------------------------- 2653 * This register is used for configuration of the ACL. 2654 */ 2655 #define MLXSW_REG_PACL_ID 0x3004 2656 #define MLXSW_REG_PACL_LEN 0x70 2657 2658 MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN); 2659 2660 /* reg_pacl_v 2661 * Valid. Setting the v bit makes the ACL valid. It should not be cleared 2662 * while the ACL is bounded to either a port, VLAN or ACL rule. 2663 * Access: RW 2664 */ 2665 MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1); 2666 2667 /* reg_pacl_acl_id 2668 * An identifier representing the ACL (managed by software) 2669 * Range 0 .. cap_max_acl_regions - 1 2670 * Access: Index 2671 */ 2672 MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16); 2673 2674 #define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16 2675 2676 /* reg_pacl_tcam_region_info 2677 * Opaque object that represents a TCAM region. 2678 * Obtained through PTAR register. 2679 * Access: RW 2680 */ 2681 MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30, 2682 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2683 2684 static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id, 2685 bool valid, const char *tcam_region_info) 2686 { 2687 MLXSW_REG_ZERO(pacl, payload); 2688 mlxsw_reg_pacl_acl_id_set(payload, acl_id); 2689 mlxsw_reg_pacl_v_set(payload, valid); 2690 mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info); 2691 } 2692 2693 /* PAGT - Policy-Engine ACL Group Table 2694 * ------------------------------------ 2695 * This register is used for configuration of the ACL Group Table. 2696 */ 2697 #define MLXSW_REG_PAGT_ID 0x3005 2698 #define MLXSW_REG_PAGT_BASE_LEN 0x30 2699 #define MLXSW_REG_PAGT_ACL_LEN 4 2700 #define MLXSW_REG_PAGT_ACL_MAX_NUM 16 2701 #define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \ 2702 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN) 2703 2704 MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN); 2705 2706 /* reg_pagt_size 2707 * Number of ACLs in the group. 2708 * Size 0 invalidates a group. 2709 * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now) 2710 * Total number of ACLs in all groups must be lower or equal 2711 * to cap_max_acl_tot_groups 2712 * Note: a group which is binded must not be invalidated 2713 * Access: Index 2714 */ 2715 MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8); 2716 2717 /* reg_pagt_acl_group_id 2718 * An identifier (numbered from 0..cap_max_acl_groups-1) representing 2719 * the ACL Group identifier (managed by software). 2720 * Access: Index 2721 */ 2722 MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16); 2723 2724 /* reg_pagt_multi 2725 * Multi-ACL 2726 * 0 - This ACL is the last ACL in the multi-ACL 2727 * 1 - This ACL is part of a multi-ACL 2728 * Access: RW 2729 */ 2730 MLXSW_ITEM32_INDEXED(reg, pagt, multi, 0x30, 31, 1, 0x04, 0x00, false); 2731 2732 /* reg_pagt_acl_id 2733 * ACL identifier 2734 * Access: RW 2735 */ 2736 MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false); 2737 2738 static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id) 2739 { 2740 MLXSW_REG_ZERO(pagt, payload); 2741 mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id); 2742 } 2743 2744 static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index, 2745 u16 acl_id, bool multi) 2746 { 2747 u8 size = mlxsw_reg_pagt_size_get(payload); 2748 2749 if (index >= size) 2750 mlxsw_reg_pagt_size_set(payload, index + 1); 2751 mlxsw_reg_pagt_multi_set(payload, index, multi); 2752 mlxsw_reg_pagt_acl_id_set(payload, index, acl_id); 2753 } 2754 2755 /* PTAR - Policy-Engine TCAM Allocation Register 2756 * --------------------------------------------- 2757 * This register is used for allocation of regions in the TCAM. 2758 * Note: Query method is not supported on this register. 2759 */ 2760 #define MLXSW_REG_PTAR_ID 0x3006 2761 #define MLXSW_REG_PTAR_BASE_LEN 0x20 2762 #define MLXSW_REG_PTAR_KEY_ID_LEN 1 2763 #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16 2764 #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \ 2765 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN) 2766 2767 MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN); 2768 2769 enum mlxsw_reg_ptar_op { 2770 /* allocate a TCAM region */ 2771 MLXSW_REG_PTAR_OP_ALLOC, 2772 /* resize a TCAM region */ 2773 MLXSW_REG_PTAR_OP_RESIZE, 2774 /* deallocate TCAM region */ 2775 MLXSW_REG_PTAR_OP_FREE, 2776 /* test allocation */ 2777 MLXSW_REG_PTAR_OP_TEST, 2778 }; 2779 2780 /* reg_ptar_op 2781 * Access: OP 2782 */ 2783 MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4); 2784 2785 /* reg_ptar_action_set_type 2786 * Type of action set to be used on this region. 2787 * For Spectrum and Spectrum-2, this is always type 2 - "flexible" 2788 * Access: WO 2789 */ 2790 MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8); 2791 2792 enum mlxsw_reg_ptar_key_type { 2793 MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50, /* Spetrum */ 2794 MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51, /* Spectrum-2 */ 2795 }; 2796 2797 /* reg_ptar_key_type 2798 * TCAM key type for the region. 2799 * Access: WO 2800 */ 2801 MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8); 2802 2803 /* reg_ptar_region_size 2804 * TCAM region size. When allocating/resizing this is the requested size, 2805 * the response is the actual size. Note that actual size may be 2806 * larger than requested. 2807 * Allowed range 1 .. cap_max_rules-1 2808 * Reserved during op deallocate. 2809 * Access: WO 2810 */ 2811 MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16); 2812 2813 /* reg_ptar_region_id 2814 * Region identifier 2815 * Range 0 .. cap_max_regions-1 2816 * Access: Index 2817 */ 2818 MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16); 2819 2820 /* reg_ptar_tcam_region_info 2821 * Opaque object that represents the TCAM region. 2822 * Returned when allocating a region. 2823 * Provided by software for ACL generation and region deallocation and resize. 2824 * Access: RW 2825 */ 2826 MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10, 2827 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2828 2829 /* reg_ptar_flexible_key_id 2830 * Identifier of the Flexible Key. 2831 * Only valid if key_type == "FLEX_KEY" 2832 * The key size will be rounded up to one of the following values: 2833 * 9B, 18B, 36B, 54B. 2834 * This field is reserved for in resize operation. 2835 * Access: WO 2836 */ 2837 MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8, 2838 MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false); 2839 2840 static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op, 2841 enum mlxsw_reg_ptar_key_type key_type, 2842 u16 region_size, u16 region_id, 2843 const char *tcam_region_info) 2844 { 2845 MLXSW_REG_ZERO(ptar, payload); 2846 mlxsw_reg_ptar_op_set(payload, op); 2847 mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */ 2848 mlxsw_reg_ptar_key_type_set(payload, key_type); 2849 mlxsw_reg_ptar_region_size_set(payload, region_size); 2850 mlxsw_reg_ptar_region_id_set(payload, region_id); 2851 mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info); 2852 } 2853 2854 static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index, 2855 u16 key_id) 2856 { 2857 mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id); 2858 } 2859 2860 static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info) 2861 { 2862 mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info); 2863 } 2864 2865 /* PPRR - Policy-Engine Port Range Register 2866 * ---------------------------------------- 2867 * This register is used for configuring port range identification. 2868 */ 2869 #define MLXSW_REG_PPRR_ID 0x3008 2870 #define MLXSW_REG_PPRR_LEN 0x14 2871 2872 MLXSW_REG_DEFINE(pprr, MLXSW_REG_PPRR_ID, MLXSW_REG_PPRR_LEN); 2873 2874 /* reg_pprr_ipv4 2875 * Apply port range register to IPv4 packets. 2876 * Access: RW 2877 */ 2878 MLXSW_ITEM32(reg, pprr, ipv4, 0x00, 31, 1); 2879 2880 /* reg_pprr_ipv6 2881 * Apply port range register to IPv6 packets. 2882 * Access: RW 2883 */ 2884 MLXSW_ITEM32(reg, pprr, ipv6, 0x00, 30, 1); 2885 2886 /* reg_pprr_src 2887 * Apply port range register to source L4 ports. 2888 * Access: RW 2889 */ 2890 MLXSW_ITEM32(reg, pprr, src, 0x00, 29, 1); 2891 2892 /* reg_pprr_dst 2893 * Apply port range register to destination L4 ports. 2894 * Access: RW 2895 */ 2896 MLXSW_ITEM32(reg, pprr, dst, 0x00, 28, 1); 2897 2898 /* reg_pprr_tcp 2899 * Apply port range register to TCP packets. 2900 * Access: RW 2901 */ 2902 MLXSW_ITEM32(reg, pprr, tcp, 0x00, 27, 1); 2903 2904 /* reg_pprr_udp 2905 * Apply port range register to UDP packets. 2906 * Access: RW 2907 */ 2908 MLXSW_ITEM32(reg, pprr, udp, 0x00, 26, 1); 2909 2910 /* reg_pprr_register_index 2911 * Index of Port Range Register being accessed. 2912 * Range is 0..cap_max_acl_l4_port_range-1. 2913 * Access: Index 2914 */ 2915 MLXSW_ITEM32(reg, pprr, register_index, 0x00, 0, 8); 2916 2917 /* reg_prrr_port_range_min 2918 * Minimum port range for comparison. 2919 * Match is defined as: 2920 * port_range_min <= packet_port <= port_range_max. 2921 * Access: RW 2922 */ 2923 MLXSW_ITEM32(reg, pprr, port_range_min, 0x04, 16, 16); 2924 2925 /* reg_prrr_port_range_max 2926 * Maximum port range for comparison. 2927 * Access: RW 2928 */ 2929 MLXSW_ITEM32(reg, pprr, port_range_max, 0x04, 0, 16); 2930 2931 static inline void mlxsw_reg_pprr_pack(char *payload, u8 register_index) 2932 { 2933 MLXSW_REG_ZERO(pprr, payload); 2934 mlxsw_reg_pprr_register_index_set(payload, register_index); 2935 } 2936 2937 /* PPBS - Policy-Engine Policy Based Switching Register 2938 * ---------------------------------------------------- 2939 * This register retrieves and sets Policy Based Switching Table entries. 2940 */ 2941 #define MLXSW_REG_PPBS_ID 0x300C 2942 #define MLXSW_REG_PPBS_LEN 0x14 2943 2944 MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN); 2945 2946 /* reg_ppbs_pbs_ptr 2947 * Index into the PBS table. 2948 * For Spectrum, the index points to the KVD Linear. 2949 * Access: Index 2950 */ 2951 MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24); 2952 2953 /* reg_ppbs_system_port 2954 * Unique port identifier for the final destination of the packet. 2955 * Access: RW 2956 */ 2957 MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16); 2958 2959 static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr, 2960 u16 system_port) 2961 { 2962 MLXSW_REG_ZERO(ppbs, payload); 2963 mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr); 2964 mlxsw_reg_ppbs_system_port_set(payload, system_port); 2965 } 2966 2967 /* PRCR - Policy-Engine Rules Copy Register 2968 * ---------------------------------------- 2969 * This register is used for accessing rules within a TCAM region. 2970 */ 2971 #define MLXSW_REG_PRCR_ID 0x300D 2972 #define MLXSW_REG_PRCR_LEN 0x40 2973 2974 MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN); 2975 2976 enum mlxsw_reg_prcr_op { 2977 /* Move rules. Moves the rules from "tcam_region_info" starting 2978 * at offset "offset" to "dest_tcam_region_info" 2979 * at offset "dest_offset." 2980 */ 2981 MLXSW_REG_PRCR_OP_MOVE, 2982 /* Copy rules. Copies the rules from "tcam_region_info" starting 2983 * at offset "offset" to "dest_tcam_region_info" 2984 * at offset "dest_offset." 2985 */ 2986 MLXSW_REG_PRCR_OP_COPY, 2987 }; 2988 2989 /* reg_prcr_op 2990 * Access: OP 2991 */ 2992 MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4); 2993 2994 /* reg_prcr_offset 2995 * Offset within the source region to copy/move from. 2996 * Access: Index 2997 */ 2998 MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16); 2999 3000 /* reg_prcr_size 3001 * The number of rules to copy/move. 3002 * Access: WO 3003 */ 3004 MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16); 3005 3006 /* reg_prcr_tcam_region_info 3007 * Opaque object that represents the source TCAM region. 3008 * Access: Index 3009 */ 3010 MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10, 3011 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 3012 3013 /* reg_prcr_dest_offset 3014 * Offset within the source region to copy/move to. 3015 * Access: Index 3016 */ 3017 MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16); 3018 3019 /* reg_prcr_dest_tcam_region_info 3020 * Opaque object that represents the destination TCAM region. 3021 * Access: Index 3022 */ 3023 MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30, 3024 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 3025 3026 static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op, 3027 const char *src_tcam_region_info, 3028 u16 src_offset, 3029 const char *dest_tcam_region_info, 3030 u16 dest_offset, u16 size) 3031 { 3032 MLXSW_REG_ZERO(prcr, payload); 3033 mlxsw_reg_prcr_op_set(payload, op); 3034 mlxsw_reg_prcr_offset_set(payload, src_offset); 3035 mlxsw_reg_prcr_size_set(payload, size); 3036 mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload, 3037 src_tcam_region_info); 3038 mlxsw_reg_prcr_dest_offset_set(payload, dest_offset); 3039 mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload, 3040 dest_tcam_region_info); 3041 } 3042 3043 /* PEFA - Policy-Engine Extended Flexible Action Register 3044 * ------------------------------------------------------ 3045 * This register is used for accessing an extended flexible action entry 3046 * in the central KVD Linear Database. 3047 */ 3048 #define MLXSW_REG_PEFA_ID 0x300F 3049 #define MLXSW_REG_PEFA_LEN 0xB0 3050 3051 MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN); 3052 3053 /* reg_pefa_index 3054 * Index in the KVD Linear Centralized Database. 3055 * Access: Index 3056 */ 3057 MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24); 3058 3059 /* reg_pefa_a 3060 * Index in the KVD Linear Centralized Database. 3061 * Activity 3062 * For a new entry: set if ca=0, clear if ca=1 3063 * Set if a packet lookup has hit on the specific entry 3064 * Access: RO 3065 */ 3066 MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1); 3067 3068 /* reg_pefa_ca 3069 * Clear activity 3070 * When write: activity is according to this field 3071 * When read: after reading the activity is cleared according to ca 3072 * Access: OP 3073 */ 3074 MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1); 3075 3076 #define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8 3077 3078 /* reg_pefa_flex_action_set 3079 * Action-set to perform when rule is matched. 3080 * Must be zero padded if action set is shorter. 3081 * Access: RW 3082 */ 3083 MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN); 3084 3085 static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca, 3086 const char *flex_action_set) 3087 { 3088 MLXSW_REG_ZERO(pefa, payload); 3089 mlxsw_reg_pefa_index_set(payload, index); 3090 mlxsw_reg_pefa_ca_set(payload, ca); 3091 if (flex_action_set) 3092 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload, 3093 flex_action_set); 3094 } 3095 3096 static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a) 3097 { 3098 *p_a = mlxsw_reg_pefa_a_get(payload); 3099 } 3100 3101 /* PEMRBT - Policy-Engine Multicast Router Binding Table Register 3102 * -------------------------------------------------------------- 3103 * This register is used for binding Multicast router to an ACL group 3104 * that serves the MC router. 3105 * This register is not supported by SwitchX/-2 and Spectrum. 3106 */ 3107 #define MLXSW_REG_PEMRBT_ID 0x3014 3108 #define MLXSW_REG_PEMRBT_LEN 0x14 3109 3110 MLXSW_REG_DEFINE(pemrbt, MLXSW_REG_PEMRBT_ID, MLXSW_REG_PEMRBT_LEN); 3111 3112 enum mlxsw_reg_pemrbt_protocol { 3113 MLXSW_REG_PEMRBT_PROTO_IPV4, 3114 MLXSW_REG_PEMRBT_PROTO_IPV6, 3115 }; 3116 3117 /* reg_pemrbt_protocol 3118 * Access: Index 3119 */ 3120 MLXSW_ITEM32(reg, pemrbt, protocol, 0x00, 0, 1); 3121 3122 /* reg_pemrbt_group_id 3123 * ACL group identifier. 3124 * Range 0..cap_max_acl_groups-1 3125 * Access: RW 3126 */ 3127 MLXSW_ITEM32(reg, pemrbt, group_id, 0x10, 0, 16); 3128 3129 static inline void 3130 mlxsw_reg_pemrbt_pack(char *payload, enum mlxsw_reg_pemrbt_protocol protocol, 3131 u16 group_id) 3132 { 3133 MLXSW_REG_ZERO(pemrbt, payload); 3134 mlxsw_reg_pemrbt_protocol_set(payload, protocol); 3135 mlxsw_reg_pemrbt_group_id_set(payload, group_id); 3136 } 3137 3138 /* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2 3139 * ----------------------------------------------------- 3140 * This register is used for accessing rules within a TCAM region. 3141 * It is a new version of PTCE in order to support wider key, 3142 * mask and action within a TCAM region. This register is not supported 3143 * by SwitchX and SwitchX-2. 3144 */ 3145 #define MLXSW_REG_PTCE2_ID 0x3017 3146 #define MLXSW_REG_PTCE2_LEN 0x1D8 3147 3148 MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN); 3149 3150 /* reg_ptce2_v 3151 * Valid. 3152 * Access: RW 3153 */ 3154 MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1); 3155 3156 /* reg_ptce2_a 3157 * Activity. Set if a packet lookup has hit on the specific entry. 3158 * To clear the "a" bit, use "clear activity" op or "clear on read" op. 3159 * Access: RO 3160 */ 3161 MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1); 3162 3163 enum mlxsw_reg_ptce2_op { 3164 /* Read operation. */ 3165 MLXSW_REG_PTCE2_OP_QUERY_READ = 0, 3166 /* clear on read operation. Used to read entry 3167 * and clear Activity bit. 3168 */ 3169 MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1, 3170 /* Write operation. Used to write a new entry to the table. 3171 * All R/W fields are relevant for new entry. Activity bit is set 3172 * for new entries - Note write with v = 0 will delete the entry. 3173 */ 3174 MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0, 3175 /* Update action. Only action set will be updated. */ 3176 MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1, 3177 /* Clear activity. A bit is cleared for the entry. */ 3178 MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2, 3179 }; 3180 3181 /* reg_ptce2_op 3182 * Access: OP 3183 */ 3184 MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3); 3185 3186 /* reg_ptce2_offset 3187 * Access: Index 3188 */ 3189 MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16); 3190 3191 /* reg_ptce2_priority 3192 * Priority of the rule, higher values win. The range is 1..cap_kvd_size-1. 3193 * Note: priority does not have to be unique per rule. 3194 * Within a region, higher priority should have lower offset (no limitation 3195 * between regions in a multi-region). 3196 * Access: RW 3197 */ 3198 MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24); 3199 3200 /* reg_ptce2_tcam_region_info 3201 * Opaque object that represents the TCAM region. 3202 * Access: Index 3203 */ 3204 MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10, 3205 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 3206 3207 #define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 96 3208 3209 /* reg_ptce2_flex_key_blocks 3210 * ACL Key. 3211 * Access: RW 3212 */ 3213 MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20, 3214 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 3215 3216 /* reg_ptce2_mask 3217 * mask- in the same size as key. A bit that is set directs the TCAM 3218 * to compare the corresponding bit in key. A bit that is clear directs 3219 * the TCAM to ignore the corresponding bit in key. 3220 * Access: RW 3221 */ 3222 MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80, 3223 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 3224 3225 /* reg_ptce2_flex_action_set 3226 * ACL action set. 3227 * Access: RW 3228 */ 3229 MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0, 3230 MLXSW_REG_FLEX_ACTION_SET_LEN); 3231 3232 static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid, 3233 enum mlxsw_reg_ptce2_op op, 3234 const char *tcam_region_info, 3235 u16 offset, u32 priority) 3236 { 3237 MLXSW_REG_ZERO(ptce2, payload); 3238 mlxsw_reg_ptce2_v_set(payload, valid); 3239 mlxsw_reg_ptce2_op_set(payload, op); 3240 mlxsw_reg_ptce2_offset_set(payload, offset); 3241 mlxsw_reg_ptce2_priority_set(payload, priority); 3242 mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info); 3243 } 3244 3245 /* PERPT - Policy-Engine ERP Table Register 3246 * ---------------------------------------- 3247 * This register adds and removes eRPs from the eRP table. 3248 */ 3249 #define MLXSW_REG_PERPT_ID 0x3021 3250 #define MLXSW_REG_PERPT_LEN 0x80 3251 3252 MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN); 3253 3254 /* reg_perpt_erpt_bank 3255 * eRP table bank. 3256 * Range 0 .. cap_max_erp_table_banks - 1 3257 * Access: Index 3258 */ 3259 MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4); 3260 3261 /* reg_perpt_erpt_index 3262 * Index to eRP table within the eRP bank. 3263 * Range is 0 .. cap_max_erp_table_bank_size - 1 3264 * Access: Index 3265 */ 3266 MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8); 3267 3268 enum mlxsw_reg_perpt_key_size { 3269 MLXSW_REG_PERPT_KEY_SIZE_2KB, 3270 MLXSW_REG_PERPT_KEY_SIZE_4KB, 3271 MLXSW_REG_PERPT_KEY_SIZE_8KB, 3272 MLXSW_REG_PERPT_KEY_SIZE_12KB, 3273 }; 3274 3275 /* reg_perpt_key_size 3276 * Access: OP 3277 */ 3278 MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4); 3279 3280 /* reg_perpt_bf_bypass 3281 * 0 - The eRP is used only if bloom filter state is set for the given 3282 * rule. 3283 * 1 - The eRP is used regardless of bloom filter state. 3284 * The bypass is an OR condition of region_id or eRP. See PERCR.bf_bypass 3285 * Access: RW 3286 */ 3287 MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1); 3288 3289 /* reg_perpt_erp_id 3290 * eRP ID for use by the rules. 3291 * Access: RW 3292 */ 3293 MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4); 3294 3295 /* reg_perpt_erpt_base_bank 3296 * Base eRP table bank, points to head of erp_vector 3297 * Range is 0 .. cap_max_erp_table_banks - 1 3298 * Access: OP 3299 */ 3300 MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4); 3301 3302 /* reg_perpt_erpt_base_index 3303 * Base index to eRP table within the eRP bank 3304 * Range is 0 .. cap_max_erp_table_bank_size - 1 3305 * Access: OP 3306 */ 3307 MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8); 3308 3309 /* reg_perpt_erp_index_in_vector 3310 * eRP index in the vector. 3311 * Access: OP 3312 */ 3313 MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4); 3314 3315 /* reg_perpt_erp_vector 3316 * eRP vector. 3317 * Access: OP 3318 */ 3319 MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1); 3320 3321 /* reg_perpt_mask 3322 * Mask 3323 * 0 - A-TCAM will ignore the bit in key 3324 * 1 - A-TCAM will compare the bit in key 3325 * Access: RW 3326 */ 3327 MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 3328 3329 static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload, 3330 unsigned long *erp_vector, 3331 unsigned long size) 3332 { 3333 unsigned long bit; 3334 3335 for_each_set_bit(bit, erp_vector, size) 3336 mlxsw_reg_perpt_erp_vector_set(payload, bit, true); 3337 } 3338 3339 static inline void 3340 mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index, 3341 enum mlxsw_reg_perpt_key_size key_size, u8 erp_id, 3342 u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index, 3343 char *mask) 3344 { 3345 MLXSW_REG_ZERO(perpt, payload); 3346 mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank); 3347 mlxsw_reg_perpt_erpt_index_set(payload, erpt_index); 3348 mlxsw_reg_perpt_key_size_set(payload, key_size); 3349 mlxsw_reg_perpt_bf_bypass_set(payload, false); 3350 mlxsw_reg_perpt_erp_id_set(payload, erp_id); 3351 mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank); 3352 mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index); 3353 mlxsw_reg_perpt_erp_index_in_vector_set(payload, erp_index); 3354 mlxsw_reg_perpt_mask_memcpy_to(payload, mask); 3355 } 3356 3357 /* PERAR - Policy-Engine Region Association Register 3358 * ------------------------------------------------- 3359 * This register associates a hw region for region_id's. Changing on the fly 3360 * is supported by the device. 3361 */ 3362 #define MLXSW_REG_PERAR_ID 0x3026 3363 #define MLXSW_REG_PERAR_LEN 0x08 3364 3365 MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN); 3366 3367 /* reg_perar_region_id 3368 * Region identifier 3369 * Range 0 .. cap_max_regions-1 3370 * Access: Index 3371 */ 3372 MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16); 3373 3374 static inline unsigned int 3375 mlxsw_reg_perar_hw_regions_needed(unsigned int block_num) 3376 { 3377 return DIV_ROUND_UP(block_num, 4); 3378 } 3379 3380 /* reg_perar_hw_region 3381 * HW Region 3382 * Range 0 .. cap_max_regions-1 3383 * Default: hw_region = region_id 3384 * For a 8 key block region, 2 consecutive regions are used 3385 * For a 12 key block region, 3 consecutive regions are used 3386 * Access: RW 3387 */ 3388 MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16); 3389 3390 static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id, 3391 u16 hw_region) 3392 { 3393 MLXSW_REG_ZERO(perar, payload); 3394 mlxsw_reg_perar_region_id_set(payload, region_id); 3395 mlxsw_reg_perar_hw_region_set(payload, hw_region); 3396 } 3397 3398 /* PTCE-V3 - Policy-Engine TCAM Entry Register Version 3 3399 * ----------------------------------------------------- 3400 * This register is a new version of PTCE-V2 in order to support the 3401 * A-TCAM. This register is not supported by SwitchX/-2 and Spectrum. 3402 */ 3403 #define MLXSW_REG_PTCE3_ID 0x3027 3404 #define MLXSW_REG_PTCE3_LEN 0xF0 3405 3406 MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN); 3407 3408 /* reg_ptce3_v 3409 * Valid. 3410 * Access: RW 3411 */ 3412 MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1); 3413 3414 enum mlxsw_reg_ptce3_op { 3415 /* Write operation. Used to write a new entry to the table. 3416 * All R/W fields are relevant for new entry. Activity bit is set 3417 * for new entries. Write with v = 0 will delete the entry. Must 3418 * not be used if an entry exists. 3419 */ 3420 MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0, 3421 /* Update operation */ 3422 MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1, 3423 /* Read operation */ 3424 MLXSW_REG_PTCE3_OP_QUERY_READ = 0, 3425 }; 3426 3427 /* reg_ptce3_op 3428 * Access: OP 3429 */ 3430 MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3); 3431 3432 /* reg_ptce3_priority 3433 * Priority of the rule. Higher values win. 3434 * For Spectrum-2 range is 1..cap_kvd_size - 1 3435 * Note: Priority does not have to be unique per rule. 3436 * Access: RW 3437 */ 3438 MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24); 3439 3440 /* reg_ptce3_tcam_region_info 3441 * Opaque object that represents the TCAM region. 3442 * Access: Index 3443 */ 3444 MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10, 3445 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 3446 3447 /* reg_ptce3_flex2_key_blocks 3448 * ACL key. The key must be masked according to eRP (if exists) or 3449 * according to master mask. 3450 * Access: Index 3451 */ 3452 MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20, 3453 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 3454 3455 /* reg_ptce3_erp_id 3456 * eRP ID. 3457 * Access: Index 3458 */ 3459 MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4); 3460 3461 /* reg_ptce3_delta_start 3462 * Start point of delta_value and delta_mask, in bits. Must not exceed 3463 * num_key_blocks * 36 - 8. Reserved when delta_mask = 0. 3464 * Access: Index 3465 */ 3466 MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10); 3467 3468 /* reg_ptce3_delta_mask 3469 * Delta mask. 3470 * 0 - Ignore relevant bit in delta_value 3471 * 1 - Compare relevant bit in delta_value 3472 * Delta mask must not be set for reserved fields in the key blocks. 3473 * Note: No delta when no eRPs. Thus, for regions with 3474 * PERERP.erpt_pointer_valid = 0 the delta mask must be 0. 3475 * Access: Index 3476 */ 3477 MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8); 3478 3479 /* reg_ptce3_delta_value 3480 * Delta value. 3481 * Bits which are masked by delta_mask must be 0. 3482 * Access: Index 3483 */ 3484 MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8); 3485 3486 /* reg_ptce3_prune_vector 3487 * Pruning vector relative to the PERPT.erp_id. 3488 * Used for reducing lookups. 3489 * 0 - NEED: Do a lookup using the eRP. 3490 * 1 - PRUNE: Do not perform a lookup using the eRP. 3491 * Maybe be modified by PEAPBL and PEAPBM. 3492 * Note: In Spectrum-2, a region of 8 key blocks must be set to either 3493 * all 1's or all 0's. 3494 * Access: RW 3495 */ 3496 MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1); 3497 3498 /* reg_ptce3_prune_ctcam 3499 * Pruning on C-TCAM. Used for reducing lookups. 3500 * 0 - NEED: Do a lookup in the C-TCAM. 3501 * 1 - PRUNE: Do not perform a lookup in the C-TCAM. 3502 * Access: RW 3503 */ 3504 MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1); 3505 3506 /* reg_ptce3_large_exists 3507 * Large entry key ID exists. 3508 * Within the region: 3509 * 0 - SINGLE: The large_entry_key_id is not currently in use. 3510 * For rule insert: The MSB of the key (blocks 6..11) will be added. 3511 * For rule delete: The MSB of the key will be removed. 3512 * 1 - NON_SINGLE: The large_entry_key_id is currently in use. 3513 * For rule insert: The MSB of the key (blocks 6..11) will not be added. 3514 * For rule delete: The MSB of the key will not be removed. 3515 * Access: WO 3516 */ 3517 MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1); 3518 3519 /* reg_ptce3_large_entry_key_id 3520 * Large entry key ID. 3521 * A key for 12 key blocks rules. Reserved when region has less than 12 key 3522 * blocks. Must be different for different keys which have the same common 3523 * 6 key blocks (MSB, blocks 6..11) key within a region. 3524 * Range is 0..cap_max_pe_large_key_id - 1 3525 * Access: RW 3526 */ 3527 MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24); 3528 3529 /* reg_ptce3_action_pointer 3530 * Pointer to action. 3531 * Range is 0..cap_max_kvd_action_sets - 1 3532 * Access: RW 3533 */ 3534 MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24); 3535 3536 static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid, 3537 enum mlxsw_reg_ptce3_op op, 3538 u32 priority, 3539 const char *tcam_region_info, 3540 const char *key, u8 erp_id, 3541 u16 delta_start, u8 delta_mask, 3542 u8 delta_value, bool large_exists, 3543 u32 lkey_id, u32 action_pointer) 3544 { 3545 MLXSW_REG_ZERO(ptce3, payload); 3546 mlxsw_reg_ptce3_v_set(payload, valid); 3547 mlxsw_reg_ptce3_op_set(payload, op); 3548 mlxsw_reg_ptce3_priority_set(payload, priority); 3549 mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info); 3550 mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key); 3551 mlxsw_reg_ptce3_erp_id_set(payload, erp_id); 3552 mlxsw_reg_ptce3_delta_start_set(payload, delta_start); 3553 mlxsw_reg_ptce3_delta_mask_set(payload, delta_mask); 3554 mlxsw_reg_ptce3_delta_value_set(payload, delta_value); 3555 mlxsw_reg_ptce3_large_exists_set(payload, large_exists); 3556 mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id); 3557 mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer); 3558 } 3559 3560 /* PERCR - Policy-Engine Region Configuration Register 3561 * --------------------------------------------------- 3562 * This register configures the region parameters. The region_id must be 3563 * allocated. 3564 */ 3565 #define MLXSW_REG_PERCR_ID 0x302A 3566 #define MLXSW_REG_PERCR_LEN 0x80 3567 3568 MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN); 3569 3570 /* reg_percr_region_id 3571 * Region identifier. 3572 * Range 0..cap_max_regions-1 3573 * Access: Index 3574 */ 3575 MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16); 3576 3577 /* reg_percr_atcam_ignore_prune 3578 * Ignore prune_vector by other A-TCAM rules. Used e.g., for a new rule. 3579 * Access: RW 3580 */ 3581 MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1); 3582 3583 /* reg_percr_ctcam_ignore_prune 3584 * Ignore prune_ctcam by other A-TCAM rules. Used e.g., for a new rule. 3585 * Access: RW 3586 */ 3587 MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1); 3588 3589 /* reg_percr_bf_bypass 3590 * Bloom filter bypass. 3591 * 0 - Bloom filter is used (default) 3592 * 1 - Bloom filter is bypassed. The bypass is an OR condition of 3593 * region_id or eRP. See PERPT.bf_bypass 3594 * Access: RW 3595 */ 3596 MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1); 3597 3598 /* reg_percr_master_mask 3599 * Master mask. Logical OR mask of all masks of all rules of a region 3600 * (both A-TCAM and C-TCAM). When there are no eRPs 3601 * (erpt_pointer_valid = 0), then this provides the mask. 3602 * Access: RW 3603 */ 3604 MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96); 3605 3606 static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id) 3607 { 3608 MLXSW_REG_ZERO(percr, payload); 3609 mlxsw_reg_percr_region_id_set(payload, region_id); 3610 mlxsw_reg_percr_atcam_ignore_prune_set(payload, false); 3611 mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false); 3612 mlxsw_reg_percr_bf_bypass_set(payload, false); 3613 } 3614 3615 /* PERERP - Policy-Engine Region eRP Register 3616 * ------------------------------------------ 3617 * This register configures the region eRP. The region_id must be 3618 * allocated. 3619 */ 3620 #define MLXSW_REG_PERERP_ID 0x302B 3621 #define MLXSW_REG_PERERP_LEN 0x1C 3622 3623 MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN); 3624 3625 /* reg_pererp_region_id 3626 * Region identifier. 3627 * Range 0..cap_max_regions-1 3628 * Access: Index 3629 */ 3630 MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16); 3631 3632 /* reg_pererp_ctcam_le 3633 * C-TCAM lookup enable. Reserved when erpt_pointer_valid = 0. 3634 * Access: RW 3635 */ 3636 MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1); 3637 3638 /* reg_pererp_erpt_pointer_valid 3639 * erpt_pointer is valid. 3640 * Access: RW 3641 */ 3642 MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1); 3643 3644 /* reg_pererp_erpt_bank_pointer 3645 * Pointer to eRP table bank. May be modified at any time. 3646 * Range 0..cap_max_erp_table_banks-1 3647 * Reserved when erpt_pointer_valid = 0 3648 */ 3649 MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4); 3650 3651 /* reg_pererp_erpt_pointer 3652 * Pointer to eRP table within the eRP bank. Can be changed for an 3653 * existing region. 3654 * Range 0..cap_max_erp_table_size-1 3655 * Reserved when erpt_pointer_valid = 0 3656 * Access: RW 3657 */ 3658 MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8); 3659 3660 /* reg_pererp_erpt_vector 3661 * Vector of allowed eRP indexes starting from erpt_pointer within the 3662 * erpt_bank_pointer. Next entries will be in next bank. 3663 * Note that eRP index is used and not eRP ID. 3664 * Reserved when erpt_pointer_valid = 0 3665 * Access: RW 3666 */ 3667 MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1); 3668 3669 /* reg_pererp_master_rp_id 3670 * Master RP ID. When there are no eRPs, then this provides the eRP ID 3671 * for the lookup. Can be changed for an existing region. 3672 * Reserved when erpt_pointer_valid = 1 3673 * Access: RW 3674 */ 3675 MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4); 3676 3677 static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload, 3678 unsigned long *erp_vector, 3679 unsigned long size) 3680 { 3681 unsigned long bit; 3682 3683 for_each_set_bit(bit, erp_vector, size) 3684 mlxsw_reg_pererp_erpt_vector_set(payload, bit, true); 3685 } 3686 3687 static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id, 3688 bool ctcam_le, bool erpt_pointer_valid, 3689 u8 erpt_bank_pointer, u8 erpt_pointer, 3690 u8 master_rp_id) 3691 { 3692 MLXSW_REG_ZERO(pererp, payload); 3693 mlxsw_reg_pererp_region_id_set(payload, region_id); 3694 mlxsw_reg_pererp_ctcam_le_set(payload, ctcam_le); 3695 mlxsw_reg_pererp_erpt_pointer_valid_set(payload, erpt_pointer_valid); 3696 mlxsw_reg_pererp_erpt_bank_pointer_set(payload, erpt_bank_pointer); 3697 mlxsw_reg_pererp_erpt_pointer_set(payload, erpt_pointer); 3698 mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id); 3699 } 3700 3701 /* PEABFE - Policy-Engine Algorithmic Bloom Filter Entries Register 3702 * ---------------------------------------------------------------- 3703 * This register configures the Bloom filter entries. 3704 */ 3705 #define MLXSW_REG_PEABFE_ID 0x3022 3706 #define MLXSW_REG_PEABFE_BASE_LEN 0x10 3707 #define MLXSW_REG_PEABFE_BF_REC_LEN 0x4 3708 #define MLXSW_REG_PEABFE_BF_REC_MAX_COUNT 256 3709 #define MLXSW_REG_PEABFE_LEN (MLXSW_REG_PEABFE_BASE_LEN + \ 3710 MLXSW_REG_PEABFE_BF_REC_LEN * \ 3711 MLXSW_REG_PEABFE_BF_REC_MAX_COUNT) 3712 3713 MLXSW_REG_DEFINE(peabfe, MLXSW_REG_PEABFE_ID, MLXSW_REG_PEABFE_LEN); 3714 3715 /* reg_peabfe_size 3716 * Number of BF entries to be updated. 3717 * Range 1..256 3718 * Access: Op 3719 */ 3720 MLXSW_ITEM32(reg, peabfe, size, 0x00, 0, 9); 3721 3722 /* reg_peabfe_bf_entry_state 3723 * Bloom filter state 3724 * 0 - Clear 3725 * 1 - Set 3726 * Access: RW 3727 */ 3728 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_state, 3729 MLXSW_REG_PEABFE_BASE_LEN, 31, 1, 3730 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3731 3732 /* reg_peabfe_bf_entry_bank 3733 * Bloom filter bank ID 3734 * Range 0..cap_max_erp_table_banks-1 3735 * Access: Index 3736 */ 3737 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_bank, 3738 MLXSW_REG_PEABFE_BASE_LEN, 24, 4, 3739 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3740 3741 /* reg_peabfe_bf_entry_index 3742 * Bloom filter entry index 3743 * Range 0..2^cap_max_bf_log-1 3744 * Access: Index 3745 */ 3746 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_index, 3747 MLXSW_REG_PEABFE_BASE_LEN, 0, 24, 3748 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3749 3750 static inline void mlxsw_reg_peabfe_pack(char *payload) 3751 { 3752 MLXSW_REG_ZERO(peabfe, payload); 3753 } 3754 3755 static inline void mlxsw_reg_peabfe_rec_pack(char *payload, int rec_index, 3756 u8 state, u8 bank, u32 bf_index) 3757 { 3758 u8 num_rec = mlxsw_reg_peabfe_size_get(payload); 3759 3760 if (rec_index >= num_rec) 3761 mlxsw_reg_peabfe_size_set(payload, rec_index + 1); 3762 mlxsw_reg_peabfe_bf_entry_state_set(payload, rec_index, state); 3763 mlxsw_reg_peabfe_bf_entry_bank_set(payload, rec_index, bank); 3764 mlxsw_reg_peabfe_bf_entry_index_set(payload, rec_index, bf_index); 3765 } 3766 3767 /* IEDR - Infrastructure Entry Delete Register 3768 * ---------------------------------------------------- 3769 * This register is used for deleting entries from the entry tables. 3770 * It is legitimate to attempt to delete a nonexisting entry (the device will 3771 * respond as a good flow). 3772 */ 3773 #define MLXSW_REG_IEDR_ID 0x3804 3774 #define MLXSW_REG_IEDR_BASE_LEN 0x10 /* base length, without records */ 3775 #define MLXSW_REG_IEDR_REC_LEN 0x8 /* record length */ 3776 #define MLXSW_REG_IEDR_REC_MAX_COUNT 64 3777 #define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN + \ 3778 MLXSW_REG_IEDR_REC_LEN * \ 3779 MLXSW_REG_IEDR_REC_MAX_COUNT) 3780 3781 MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN); 3782 3783 /* reg_iedr_num_rec 3784 * Number of records. 3785 * Access: OP 3786 */ 3787 MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8); 3788 3789 /* reg_iedr_rec_type 3790 * Resource type. 3791 * Access: OP 3792 */ 3793 MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8, 3794 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3795 3796 /* reg_iedr_rec_size 3797 * Size of entries do be deleted. The unit is 1 entry, regardless of entry type. 3798 * Access: OP 3799 */ 3800 MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 13, 3801 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3802 3803 /* reg_iedr_rec_index_start 3804 * Resource index start. 3805 * Access: OP 3806 */ 3807 MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24, 3808 MLXSW_REG_IEDR_REC_LEN, 0x04, false); 3809 3810 static inline void mlxsw_reg_iedr_pack(char *payload) 3811 { 3812 MLXSW_REG_ZERO(iedr, payload); 3813 } 3814 3815 static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index, 3816 u8 rec_type, u16 rec_size, 3817 u32 rec_index_start) 3818 { 3819 u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload); 3820 3821 if (rec_index >= num_rec) 3822 mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1); 3823 mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type); 3824 mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size); 3825 mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start); 3826 } 3827 3828 /* QPTS - QoS Priority Trust State Register 3829 * ---------------------------------------- 3830 * This register controls the port policy to calculate the switch priority and 3831 * packet color based on incoming packet fields. 3832 */ 3833 #define MLXSW_REG_QPTS_ID 0x4002 3834 #define MLXSW_REG_QPTS_LEN 0x8 3835 3836 MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN); 3837 3838 /* reg_qpts_local_port 3839 * Local port number. 3840 * Access: Index 3841 * 3842 * Note: CPU port is supported. 3843 */ 3844 MLXSW_ITEM32_LP(reg, qpts, 0x00, 16, 0x00, 12); 3845 3846 enum mlxsw_reg_qpts_trust_state { 3847 MLXSW_REG_QPTS_TRUST_STATE_PCP = 1, 3848 MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2, /* For MPLS, trust EXP. */ 3849 }; 3850 3851 /* reg_qpts_trust_state 3852 * Trust state for a given port. 3853 * Access: RW 3854 */ 3855 MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3); 3856 3857 static inline void mlxsw_reg_qpts_pack(char *payload, u16 local_port, 3858 enum mlxsw_reg_qpts_trust_state ts) 3859 { 3860 MLXSW_REG_ZERO(qpts, payload); 3861 3862 mlxsw_reg_qpts_local_port_set(payload, local_port); 3863 mlxsw_reg_qpts_trust_state_set(payload, ts); 3864 } 3865 3866 /* QPCR - QoS Policer Configuration Register 3867 * ----------------------------------------- 3868 * The QPCR register is used to create policers - that limit 3869 * the rate of bytes or packets via some trap group. 3870 */ 3871 #define MLXSW_REG_QPCR_ID 0x4004 3872 #define MLXSW_REG_QPCR_LEN 0x28 3873 3874 MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN); 3875 3876 enum mlxsw_reg_qpcr_g { 3877 MLXSW_REG_QPCR_G_GLOBAL = 2, 3878 MLXSW_REG_QPCR_G_STORM_CONTROL = 3, 3879 }; 3880 3881 /* reg_qpcr_g 3882 * The policer type. 3883 * Access: Index 3884 */ 3885 MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2); 3886 3887 /* reg_qpcr_pid 3888 * Policer ID. 3889 * Access: Index 3890 */ 3891 MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14); 3892 3893 /* reg_qpcr_clear_counter 3894 * Clear counters. 3895 * Access: OP 3896 */ 3897 MLXSW_ITEM32(reg, qpcr, clear_counter, 0x04, 31, 1); 3898 3899 /* reg_qpcr_color_aware 3900 * Is the policer aware of colors. 3901 * Must be 0 (unaware) for cpu port. 3902 * Access: RW for unbounded policer. RO for bounded policer. 3903 */ 3904 MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1); 3905 3906 /* reg_qpcr_bytes 3907 * Is policer limit is for bytes per sec or packets per sec. 3908 * 0 - packets 3909 * 1 - bytes 3910 * Access: RW for unbounded policer. RO for bounded policer. 3911 */ 3912 MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1); 3913 3914 enum mlxsw_reg_qpcr_ir_units { 3915 MLXSW_REG_QPCR_IR_UNITS_M, 3916 MLXSW_REG_QPCR_IR_UNITS_K, 3917 }; 3918 3919 /* reg_qpcr_ir_units 3920 * Policer's units for cir and eir fields (for bytes limits only) 3921 * 1 - 10^3 3922 * 0 - 10^6 3923 * Access: OP 3924 */ 3925 MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1); 3926 3927 enum mlxsw_reg_qpcr_rate_type { 3928 MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1, 3929 MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2, 3930 }; 3931 3932 /* reg_qpcr_rate_type 3933 * Policer can have one limit (single rate) or 2 limits with specific operation 3934 * for packets that exceed the lower rate but not the upper one. 3935 * (For cpu port must be single rate) 3936 * Access: RW for unbounded policer. RO for bounded policer. 3937 */ 3938 MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2); 3939 3940 /* reg_qpc_cbs 3941 * Policer's committed burst size. 3942 * The policer is working with time slices of 50 nano sec. By default every 3943 * slice is granted the proportionate share of the committed rate. If we want to 3944 * allow a slice to exceed that share (while still keeping the rate per sec) we 3945 * can allow burst. The burst size is between the default proportionate share 3946 * (and no lower than 8) to 32Gb. (Even though giving a number higher than the 3947 * committed rate will result in exceeding the rate). The burst size must be a 3948 * log of 2 and will be determined by 2^cbs. 3949 * Access: RW 3950 */ 3951 MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6); 3952 3953 /* reg_qpcr_cir 3954 * Policer's committed rate. 3955 * The rate used for sungle rate, the lower rate for double rate. 3956 * For bytes limits, the rate will be this value * the unit from ir_units. 3957 * (Resolution error is up to 1%). 3958 * Access: RW 3959 */ 3960 MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32); 3961 3962 /* reg_qpcr_eir 3963 * Policer's exceed rate. 3964 * The higher rate for double rate, reserved for single rate. 3965 * Lower rate for double rate policer. 3966 * For bytes limits, the rate will be this value * the unit from ir_units. 3967 * (Resolution error is up to 1%). 3968 * Access: RW 3969 */ 3970 MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32); 3971 3972 #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2 3973 3974 /* reg_qpcr_exceed_action. 3975 * What to do with packets between the 2 limits for double rate. 3976 * Access: RW for unbounded policer. RO for bounded policer. 3977 */ 3978 MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4); 3979 3980 enum mlxsw_reg_qpcr_action { 3981 /* Discard */ 3982 MLXSW_REG_QPCR_ACTION_DISCARD = 1, 3983 /* Forward and set color to red. 3984 * If the packet is intended to cpu port, it will be dropped. 3985 */ 3986 MLXSW_REG_QPCR_ACTION_FORWARD = 2, 3987 }; 3988 3989 /* reg_qpcr_violate_action 3990 * What to do with packets that cross the cir limit (for single rate) or the eir 3991 * limit (for double rate). 3992 * Access: RW for unbounded policer. RO for bounded policer. 3993 */ 3994 MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4); 3995 3996 /* reg_qpcr_violate_count 3997 * Counts the number of times violate_action happened on this PID. 3998 * Access: RW 3999 */ 4000 MLXSW_ITEM64(reg, qpcr, violate_count, 0x20, 0, 64); 4001 4002 /* Packets */ 4003 #define MLXSW_REG_QPCR_LOWEST_CIR 1 4004 #define MLXSW_REG_QPCR_HIGHEST_CIR (2 * 1000 * 1000 * 1000) /* 2Gpps */ 4005 #define MLXSW_REG_QPCR_LOWEST_CBS 4 4006 #define MLXSW_REG_QPCR_HIGHEST_CBS 24 4007 4008 /* Bandwidth */ 4009 #define MLXSW_REG_QPCR_LOWEST_CIR_BITS 1024 /* bps */ 4010 #define MLXSW_REG_QPCR_HIGHEST_CIR_BITS 2000000000000ULL /* 2Tbps */ 4011 #define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP1 4 4012 #define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP2 4 4013 #define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP1 25 4014 #define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP2 31 4015 4016 static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid, 4017 enum mlxsw_reg_qpcr_ir_units ir_units, 4018 bool bytes, u32 cir, u16 cbs) 4019 { 4020 MLXSW_REG_ZERO(qpcr, payload); 4021 mlxsw_reg_qpcr_pid_set(payload, pid); 4022 mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL); 4023 mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE); 4024 mlxsw_reg_qpcr_violate_action_set(payload, 4025 MLXSW_REG_QPCR_ACTION_DISCARD); 4026 mlxsw_reg_qpcr_cir_set(payload, cir); 4027 mlxsw_reg_qpcr_ir_units_set(payload, ir_units); 4028 mlxsw_reg_qpcr_bytes_set(payload, bytes); 4029 mlxsw_reg_qpcr_cbs_set(payload, cbs); 4030 } 4031 4032 /* QTCT - QoS Switch Traffic Class Table 4033 * ------------------------------------- 4034 * Configures the mapping between the packet switch priority and the 4035 * traffic class on the transmit port. 4036 */ 4037 #define MLXSW_REG_QTCT_ID 0x400A 4038 #define MLXSW_REG_QTCT_LEN 0x08 4039 4040 MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN); 4041 4042 /* reg_qtct_local_port 4043 * Local port number. 4044 * Access: Index 4045 * 4046 * Note: CPU port is not supported. 4047 */ 4048 MLXSW_ITEM32_LP(reg, qtct, 0x00, 16, 0x00, 12); 4049 4050 /* reg_qtct_sub_port 4051 * Virtual port within the physical port. 4052 * Should be set to 0 when virtual ports are not enabled on the port. 4053 * Access: Index 4054 */ 4055 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8); 4056 4057 /* reg_qtct_switch_prio 4058 * Switch priority. 4059 * Access: Index 4060 */ 4061 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4); 4062 4063 /* reg_qtct_tclass 4064 * Traffic class. 4065 * Default values: 4066 * switch_prio 0 : tclass 1 4067 * switch_prio 1 : tclass 0 4068 * switch_prio i : tclass i, for i > 1 4069 * Access: RW 4070 */ 4071 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4); 4072 4073 static inline void mlxsw_reg_qtct_pack(char *payload, u16 local_port, 4074 u8 switch_prio, u8 tclass) 4075 { 4076 MLXSW_REG_ZERO(qtct, payload); 4077 mlxsw_reg_qtct_local_port_set(payload, local_port); 4078 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio); 4079 mlxsw_reg_qtct_tclass_set(payload, tclass); 4080 } 4081 4082 /* QEEC - QoS ETS Element Configuration Register 4083 * --------------------------------------------- 4084 * Configures the ETS elements. 4085 */ 4086 #define MLXSW_REG_QEEC_ID 0x400D 4087 #define MLXSW_REG_QEEC_LEN 0x20 4088 4089 MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN); 4090 4091 /* reg_qeec_local_port 4092 * Local port number. 4093 * Access: Index 4094 * 4095 * Note: CPU port is supported. 4096 */ 4097 MLXSW_ITEM32_LP(reg, qeec, 0x00, 16, 0x00, 12); 4098 4099 enum mlxsw_reg_qeec_hr { 4100 MLXSW_REG_QEEC_HR_PORT, 4101 MLXSW_REG_QEEC_HR_GROUP, 4102 MLXSW_REG_QEEC_HR_SUBGROUP, 4103 MLXSW_REG_QEEC_HR_TC, 4104 }; 4105 4106 /* reg_qeec_element_hierarchy 4107 * 0 - Port 4108 * 1 - Group 4109 * 2 - Subgroup 4110 * 3 - Traffic Class 4111 * Access: Index 4112 */ 4113 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4); 4114 4115 /* reg_qeec_element_index 4116 * The index of the element in the hierarchy. 4117 * Access: Index 4118 */ 4119 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8); 4120 4121 /* reg_qeec_next_element_index 4122 * The index of the next (lower) element in the hierarchy. 4123 * Access: RW 4124 * 4125 * Note: Reserved for element_hierarchy 0. 4126 */ 4127 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8); 4128 4129 /* reg_qeec_mise 4130 * Min shaper configuration enable. Enables configuration of the min 4131 * shaper on this ETS element 4132 * 0 - Disable 4133 * 1 - Enable 4134 * Access: RW 4135 */ 4136 MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1); 4137 4138 /* reg_qeec_ptps 4139 * PTP shaper 4140 * 0: regular shaper mode 4141 * 1: PTP oriented shaper 4142 * Allowed only for hierarchy 0 4143 * Not supported for CPU port 4144 * Note that ptps mode may affect the shaper rates of all hierarchies 4145 * Supported only on Spectrum-1 4146 * Access: RW 4147 */ 4148 MLXSW_ITEM32(reg, qeec, ptps, 0x0C, 29, 1); 4149 4150 enum { 4151 MLXSW_REG_QEEC_BYTES_MODE, 4152 MLXSW_REG_QEEC_PACKETS_MODE, 4153 }; 4154 4155 /* reg_qeec_pb 4156 * Packets or bytes mode. 4157 * 0 - Bytes mode 4158 * 1 - Packets mode 4159 * Access: RW 4160 * 4161 * Note: Used for max shaper configuration. For Spectrum, packets mode 4162 * is supported only for traffic classes of CPU port. 4163 */ 4164 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1); 4165 4166 /* The smallest permitted min shaper rate. */ 4167 #define MLXSW_REG_QEEC_MIS_MIN 200000 /* Kbps */ 4168 4169 /* reg_qeec_min_shaper_rate 4170 * Min shaper information rate. 4171 * For CPU port, can only be configured for port hierarchy. 4172 * When in bytes mode, value is specified in units of 1000bps. 4173 * Access: RW 4174 */ 4175 MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28); 4176 4177 /* reg_qeec_mase 4178 * Max shaper configuration enable. Enables configuration of the max 4179 * shaper on this ETS element. 4180 * 0 - Disable 4181 * 1 - Enable 4182 * Access: RW 4183 */ 4184 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1); 4185 4186 /* The largest max shaper value possible to disable the shaper. */ 4187 #define MLXSW_REG_QEEC_MAS_DIS ((1u << 31) - 1) /* Kbps */ 4188 4189 /* reg_qeec_max_shaper_rate 4190 * Max shaper information rate. 4191 * For CPU port, can only be configured for port hierarchy. 4192 * When in bytes mode, value is specified in units of 1000bps. 4193 * Access: RW 4194 */ 4195 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 31); 4196 4197 /* reg_qeec_de 4198 * DWRR configuration enable. Enables configuration of the dwrr and 4199 * dwrr_weight. 4200 * 0 - Disable 4201 * 1 - Enable 4202 * Access: RW 4203 */ 4204 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1); 4205 4206 /* reg_qeec_dwrr 4207 * Transmission selection algorithm to use on the link going down from 4208 * the ETS element. 4209 * 0 - Strict priority 4210 * 1 - DWRR 4211 * Access: RW 4212 */ 4213 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1); 4214 4215 /* reg_qeec_dwrr_weight 4216 * DWRR weight on the link going down from the ETS element. The 4217 * percentage of bandwidth guaranteed to an ETS element within 4218 * its hierarchy. The sum of all weights across all ETS elements 4219 * within one hierarchy should be equal to 100. Reserved when 4220 * transmission selection algorithm is strict priority. 4221 * Access: RW 4222 */ 4223 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8); 4224 4225 /* reg_qeec_max_shaper_bs 4226 * Max shaper burst size 4227 * Burst size is 2^max_shaper_bs * 512 bits 4228 * For Spectrum-1: Range is: 5..25 4229 * For Spectrum-2: Range is: 11..25 4230 * Reserved when ptps = 1 4231 * Access: RW 4232 */ 4233 MLXSW_ITEM32(reg, qeec, max_shaper_bs, 0x1C, 0, 6); 4234 4235 #define MLXSW_REG_QEEC_HIGHEST_SHAPER_BS 25 4236 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1 5 4237 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2 11 4238 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3 11 4239 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP4 11 4240 4241 static inline void mlxsw_reg_qeec_pack(char *payload, u16 local_port, 4242 enum mlxsw_reg_qeec_hr hr, u8 index, 4243 u8 next_index) 4244 { 4245 MLXSW_REG_ZERO(qeec, payload); 4246 mlxsw_reg_qeec_local_port_set(payload, local_port); 4247 mlxsw_reg_qeec_element_hierarchy_set(payload, hr); 4248 mlxsw_reg_qeec_element_index_set(payload, index); 4249 mlxsw_reg_qeec_next_element_index_set(payload, next_index); 4250 } 4251 4252 static inline void mlxsw_reg_qeec_ptps_pack(char *payload, u16 local_port, 4253 bool ptps) 4254 { 4255 MLXSW_REG_ZERO(qeec, payload); 4256 mlxsw_reg_qeec_local_port_set(payload, local_port); 4257 mlxsw_reg_qeec_element_hierarchy_set(payload, MLXSW_REG_QEEC_HR_PORT); 4258 mlxsw_reg_qeec_ptps_set(payload, ptps); 4259 } 4260 4261 /* QRWE - QoS ReWrite Enable 4262 * ------------------------- 4263 * This register configures the rewrite enable per receive port. 4264 */ 4265 #define MLXSW_REG_QRWE_ID 0x400F 4266 #define MLXSW_REG_QRWE_LEN 0x08 4267 4268 MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN); 4269 4270 /* reg_qrwe_local_port 4271 * Local port number. 4272 * Access: Index 4273 * 4274 * Note: CPU port is supported. No support for router port. 4275 */ 4276 MLXSW_ITEM32_LP(reg, qrwe, 0x00, 16, 0x00, 12); 4277 4278 /* reg_qrwe_dscp 4279 * Whether to enable DSCP rewrite (default is 0, don't rewrite). 4280 * Access: RW 4281 */ 4282 MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1); 4283 4284 /* reg_qrwe_pcp 4285 * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite). 4286 * Access: RW 4287 */ 4288 MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1); 4289 4290 static inline void mlxsw_reg_qrwe_pack(char *payload, u16 local_port, 4291 bool rewrite_pcp, bool rewrite_dscp) 4292 { 4293 MLXSW_REG_ZERO(qrwe, payload); 4294 mlxsw_reg_qrwe_local_port_set(payload, local_port); 4295 mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp); 4296 mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp); 4297 } 4298 4299 /* QPDSM - QoS Priority to DSCP Mapping 4300 * ------------------------------------ 4301 * QoS Priority to DSCP Mapping Register 4302 */ 4303 #define MLXSW_REG_QPDSM_ID 0x4011 4304 #define MLXSW_REG_QPDSM_BASE_LEN 0x04 /* base length, without records */ 4305 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4 /* record length */ 4306 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 16 4307 #define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN + \ 4308 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN * \ 4309 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT) 4310 4311 MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN); 4312 4313 /* reg_qpdsm_local_port 4314 * Local Port. Supported for data packets from CPU port. 4315 * Access: Index 4316 */ 4317 MLXSW_ITEM32_LP(reg, qpdsm, 0x00, 16, 0x00, 12); 4318 4319 /* reg_qpdsm_prio_entry_color0_e 4320 * Enable update of the entry for color 0 and a given port. 4321 * Access: WO 4322 */ 4323 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e, 4324 MLXSW_REG_QPDSM_BASE_LEN, 31, 1, 4325 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4326 4327 /* reg_qpdsm_prio_entry_color0_dscp 4328 * DSCP field in the outer label of the packet for color 0 and a given port. 4329 * Reserved when e=0. 4330 * Access: RW 4331 */ 4332 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp, 4333 MLXSW_REG_QPDSM_BASE_LEN, 24, 6, 4334 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4335 4336 /* reg_qpdsm_prio_entry_color1_e 4337 * Enable update of the entry for color 1 and a given port. 4338 * Access: WO 4339 */ 4340 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e, 4341 MLXSW_REG_QPDSM_BASE_LEN, 23, 1, 4342 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4343 4344 /* reg_qpdsm_prio_entry_color1_dscp 4345 * DSCP field in the outer label of the packet for color 1 and a given port. 4346 * Reserved when e=0. 4347 * Access: RW 4348 */ 4349 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp, 4350 MLXSW_REG_QPDSM_BASE_LEN, 16, 6, 4351 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4352 4353 /* reg_qpdsm_prio_entry_color2_e 4354 * Enable update of the entry for color 2 and a given port. 4355 * Access: WO 4356 */ 4357 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e, 4358 MLXSW_REG_QPDSM_BASE_LEN, 15, 1, 4359 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4360 4361 /* reg_qpdsm_prio_entry_color2_dscp 4362 * DSCP field in the outer label of the packet for color 2 and a given port. 4363 * Reserved when e=0. 4364 * Access: RW 4365 */ 4366 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp, 4367 MLXSW_REG_QPDSM_BASE_LEN, 8, 6, 4368 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 4369 4370 static inline void mlxsw_reg_qpdsm_pack(char *payload, u16 local_port) 4371 { 4372 MLXSW_REG_ZERO(qpdsm, payload); 4373 mlxsw_reg_qpdsm_local_port_set(payload, local_port); 4374 } 4375 4376 static inline void 4377 mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp) 4378 { 4379 mlxsw_reg_qpdsm_prio_entry_color0_e_set(payload, prio, 1); 4380 mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(payload, prio, dscp); 4381 mlxsw_reg_qpdsm_prio_entry_color1_e_set(payload, prio, 1); 4382 mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(payload, prio, dscp); 4383 mlxsw_reg_qpdsm_prio_entry_color2_e_set(payload, prio, 1); 4384 mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp); 4385 } 4386 4387 /* QPDP - QoS Port DSCP to Priority Mapping Register 4388 * ------------------------------------------------- 4389 * This register controls the port default Switch Priority and Color. The 4390 * default Switch Priority and Color are used for frames where the trust state 4391 * uses default values. All member ports of a LAG should be configured with the 4392 * same default values. 4393 */ 4394 #define MLXSW_REG_QPDP_ID 0x4007 4395 #define MLXSW_REG_QPDP_LEN 0x8 4396 4397 MLXSW_REG_DEFINE(qpdp, MLXSW_REG_QPDP_ID, MLXSW_REG_QPDP_LEN); 4398 4399 /* reg_qpdp_local_port 4400 * Local Port. Supported for data packets from CPU port. 4401 * Access: Index 4402 */ 4403 MLXSW_ITEM32_LP(reg, qpdp, 0x00, 16, 0x00, 12); 4404 4405 /* reg_qpdp_switch_prio 4406 * Default port Switch Priority (default 0) 4407 * Access: RW 4408 */ 4409 MLXSW_ITEM32(reg, qpdp, switch_prio, 0x04, 0, 4); 4410 4411 static inline void mlxsw_reg_qpdp_pack(char *payload, u16 local_port, 4412 u8 switch_prio) 4413 { 4414 MLXSW_REG_ZERO(qpdp, payload); 4415 mlxsw_reg_qpdp_local_port_set(payload, local_port); 4416 mlxsw_reg_qpdp_switch_prio_set(payload, switch_prio); 4417 } 4418 4419 /* QPDPM - QoS Port DSCP to Priority Mapping Register 4420 * -------------------------------------------------- 4421 * This register controls the mapping from DSCP field to 4422 * Switch Priority for IP packets. 4423 */ 4424 #define MLXSW_REG_QPDPM_ID 0x4013 4425 #define MLXSW_REG_QPDPM_BASE_LEN 0x4 /* base length, without records */ 4426 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2 /* record length */ 4427 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64 4428 #define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN + \ 4429 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN * \ 4430 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT) 4431 4432 MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN); 4433 4434 /* reg_qpdpm_local_port 4435 * Local Port. Supported for data packets from CPU port. 4436 * Access: Index 4437 */ 4438 MLXSW_ITEM32_LP(reg, qpdpm, 0x00, 16, 0x00, 12); 4439 4440 /* reg_qpdpm_dscp_e 4441 * Enable update of the specific entry. When cleared, the switch_prio and color 4442 * fields are ignored and the previous switch_prio and color values are 4443 * preserved. 4444 * Access: WO 4445 */ 4446 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1, 4447 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 4448 4449 /* reg_qpdpm_dscp_prio 4450 * The new Switch Priority value for the relevant DSCP value. 4451 * Access: RW 4452 */ 4453 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio, 4454 MLXSW_REG_QPDPM_BASE_LEN, 0, 4, 4455 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 4456 4457 static inline void mlxsw_reg_qpdpm_pack(char *payload, u16 local_port) 4458 { 4459 MLXSW_REG_ZERO(qpdpm, payload); 4460 mlxsw_reg_qpdpm_local_port_set(payload, local_port); 4461 } 4462 4463 static inline void 4464 mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio) 4465 { 4466 mlxsw_reg_qpdpm_dscp_entry_e_set(payload, dscp, 1); 4467 mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio); 4468 } 4469 4470 /* QTCTM - QoS Switch Traffic Class Table is Multicast-Aware Register 4471 * ------------------------------------------------------------------ 4472 * This register configures if the Switch Priority to Traffic Class mapping is 4473 * based on Multicast packet indication. If so, then multicast packets will get 4474 * a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by 4475 * QTCT. 4476 * By default, Switch Priority to Traffic Class mapping is not based on 4477 * Multicast packet indication. 4478 */ 4479 #define MLXSW_REG_QTCTM_ID 0x401A 4480 #define MLXSW_REG_QTCTM_LEN 0x08 4481 4482 MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN); 4483 4484 /* reg_qtctm_local_port 4485 * Local port number. 4486 * No support for CPU port. 4487 * Access: Index 4488 */ 4489 MLXSW_ITEM32_LP(reg, qtctm, 0x00, 16, 0x00, 12); 4490 4491 /* reg_qtctm_mc 4492 * Multicast Mode 4493 * Whether Switch Priority to Traffic Class mapping is based on Multicast packet 4494 * indication (default is 0, not based on Multicast packet indication). 4495 */ 4496 MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1); 4497 4498 static inline void 4499 mlxsw_reg_qtctm_pack(char *payload, u16 local_port, bool mc) 4500 { 4501 MLXSW_REG_ZERO(qtctm, payload); 4502 mlxsw_reg_qtctm_local_port_set(payload, local_port); 4503 mlxsw_reg_qtctm_mc_set(payload, mc); 4504 } 4505 4506 /* QPSC - QoS PTP Shaper Configuration Register 4507 * -------------------------------------------- 4508 * The QPSC allows advanced configuration of the shapers when QEEC.ptps=1. 4509 * Supported only on Spectrum-1. 4510 */ 4511 #define MLXSW_REG_QPSC_ID 0x401B 4512 #define MLXSW_REG_QPSC_LEN 0x28 4513 4514 MLXSW_REG_DEFINE(qpsc, MLXSW_REG_QPSC_ID, MLXSW_REG_QPSC_LEN); 4515 4516 enum mlxsw_reg_qpsc_port_speed { 4517 MLXSW_REG_QPSC_PORT_SPEED_100M, 4518 MLXSW_REG_QPSC_PORT_SPEED_1G, 4519 MLXSW_REG_QPSC_PORT_SPEED_10G, 4520 MLXSW_REG_QPSC_PORT_SPEED_25G, 4521 }; 4522 4523 /* reg_qpsc_port_speed 4524 * Port speed. 4525 * Access: Index 4526 */ 4527 MLXSW_ITEM32(reg, qpsc, port_speed, 0x00, 0, 4); 4528 4529 /* reg_qpsc_shaper_time_exp 4530 * The base-time-interval for updating the shapers tokens (for all hierarchies). 4531 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec 4532 * shaper_rate = 64bit * shaper_inc / shaper_update_rate 4533 * Access: RW 4534 */ 4535 MLXSW_ITEM32(reg, qpsc, shaper_time_exp, 0x04, 16, 4); 4536 4537 /* reg_qpsc_shaper_time_mantissa 4538 * The base-time-interval for updating the shapers tokens (for all hierarchies). 4539 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec 4540 * shaper_rate = 64bit * shaper_inc / shaper_update_rate 4541 * Access: RW 4542 */ 4543 MLXSW_ITEM32(reg, qpsc, shaper_time_mantissa, 0x04, 0, 5); 4544 4545 /* reg_qpsc_shaper_inc 4546 * Number of tokens added to shaper on each update. 4547 * Units of 8B. 4548 * Access: RW 4549 */ 4550 MLXSW_ITEM32(reg, qpsc, shaper_inc, 0x08, 0, 5); 4551 4552 /* reg_qpsc_shaper_bs 4553 * Max shaper Burst size. 4554 * Burst size is 2 ^ max_shaper_bs * 512 [bits] 4555 * Range is: 5..25 (from 2KB..2GB) 4556 * Access: RW 4557 */ 4558 MLXSW_ITEM32(reg, qpsc, shaper_bs, 0x0C, 0, 6); 4559 4560 /* reg_qpsc_ptsc_we 4561 * Write enable to port_to_shaper_credits. 4562 * Access: WO 4563 */ 4564 MLXSW_ITEM32(reg, qpsc, ptsc_we, 0x10, 31, 1); 4565 4566 /* reg_qpsc_port_to_shaper_credits 4567 * For split ports: range 1..57 4568 * For non-split ports: range 1..112 4569 * Written only when ptsc_we is set. 4570 * Access: RW 4571 */ 4572 MLXSW_ITEM32(reg, qpsc, port_to_shaper_credits, 0x10, 0, 8); 4573 4574 /* reg_qpsc_ing_timestamp_inc 4575 * Ingress timestamp increment. 4576 * 2's complement. 4577 * The timestamp of MTPPTR at ingress will be incremented by this value. Global 4578 * value for all ports. 4579 * Same units as used by MTPPTR. 4580 * Access: RW 4581 */ 4582 MLXSW_ITEM32(reg, qpsc, ing_timestamp_inc, 0x20, 0, 32); 4583 4584 /* reg_qpsc_egr_timestamp_inc 4585 * Egress timestamp increment. 4586 * 2's complement. 4587 * The timestamp of MTPPTR at egress will be incremented by this value. Global 4588 * value for all ports. 4589 * Same units as used by MTPPTR. 4590 * Access: RW 4591 */ 4592 MLXSW_ITEM32(reg, qpsc, egr_timestamp_inc, 0x24, 0, 32); 4593 4594 static inline void 4595 mlxsw_reg_qpsc_pack(char *payload, enum mlxsw_reg_qpsc_port_speed port_speed, 4596 u8 shaper_time_exp, u8 shaper_time_mantissa, u8 shaper_inc, 4597 u8 shaper_bs, u8 port_to_shaper_credits, 4598 int ing_timestamp_inc, int egr_timestamp_inc) 4599 { 4600 MLXSW_REG_ZERO(qpsc, payload); 4601 mlxsw_reg_qpsc_port_speed_set(payload, port_speed); 4602 mlxsw_reg_qpsc_shaper_time_exp_set(payload, shaper_time_exp); 4603 mlxsw_reg_qpsc_shaper_time_mantissa_set(payload, shaper_time_mantissa); 4604 mlxsw_reg_qpsc_shaper_inc_set(payload, shaper_inc); 4605 mlxsw_reg_qpsc_shaper_bs_set(payload, shaper_bs); 4606 mlxsw_reg_qpsc_ptsc_we_set(payload, true); 4607 mlxsw_reg_qpsc_port_to_shaper_credits_set(payload, port_to_shaper_credits); 4608 mlxsw_reg_qpsc_ing_timestamp_inc_set(payload, ing_timestamp_inc); 4609 mlxsw_reg_qpsc_egr_timestamp_inc_set(payload, egr_timestamp_inc); 4610 } 4611 4612 /* PMLP - Ports Module to Local Port Register 4613 * ------------------------------------------ 4614 * Configures the assignment of modules to local ports. 4615 */ 4616 #define MLXSW_REG_PMLP_ID 0x5002 4617 #define MLXSW_REG_PMLP_LEN 0x40 4618 4619 MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN); 4620 4621 /* reg_pmlp_rxtx 4622 * 0 - Tx value is used for both Tx and Rx. 4623 * 1 - Rx value is taken from a separte field. 4624 * Access: RW 4625 */ 4626 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1); 4627 4628 /* reg_pmlp_local_port 4629 * Local port number. 4630 * Access: Index 4631 */ 4632 MLXSW_ITEM32_LP(reg, pmlp, 0x00, 16, 0x00, 12); 4633 4634 /* reg_pmlp_width 4635 * 0 - Unmap local port. 4636 * 1 - Lane 0 is used. 4637 * 2 - Lanes 0 and 1 are used. 4638 * 4 - Lanes 0, 1, 2 and 3 are used. 4639 * 8 - Lanes 0-7 are used. 4640 * Access: RW 4641 */ 4642 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8); 4643 4644 /* reg_pmlp_module 4645 * Module number. 4646 * Access: RW 4647 */ 4648 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false); 4649 4650 /* reg_pmlp_slot_index 4651 * Module number. 4652 * Slot_index 4653 * Slot_index = 0 represent the onboard (motherboard). 4654 * In case of non-modular system only slot_index = 0 is available. 4655 * Access: RW 4656 */ 4657 MLXSW_ITEM32_INDEXED(reg, pmlp, slot_index, 0x04, 8, 4, 0x04, 0x00, false); 4658 4659 /* reg_pmlp_tx_lane 4660 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well. 4661 * Access: RW 4662 */ 4663 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 4, 0x04, 0x00, false); 4664 4665 /* reg_pmlp_rx_lane 4666 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is 4667 * equal to Tx lane. 4668 * Access: RW 4669 */ 4670 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 4, 0x04, 0x00, false); 4671 4672 static inline void mlxsw_reg_pmlp_pack(char *payload, u16 local_port) 4673 { 4674 MLXSW_REG_ZERO(pmlp, payload); 4675 mlxsw_reg_pmlp_local_port_set(payload, local_port); 4676 } 4677 4678 /* PMTU - Port MTU Register 4679 * ------------------------ 4680 * Configures and reports the port MTU. 4681 */ 4682 #define MLXSW_REG_PMTU_ID 0x5003 4683 #define MLXSW_REG_PMTU_LEN 0x10 4684 4685 MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN); 4686 4687 /* reg_pmtu_local_port 4688 * Local port number. 4689 * Access: Index 4690 */ 4691 MLXSW_ITEM32_LP(reg, pmtu, 0x00, 16, 0x00, 12); 4692 4693 /* reg_pmtu_max_mtu 4694 * Maximum MTU. 4695 * When port type (e.g. Ethernet) is configured, the relevant MTU is 4696 * reported, otherwise the minimum between the max_mtu of the different 4697 * types is reported. 4698 * Access: RO 4699 */ 4700 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16); 4701 4702 /* reg_pmtu_admin_mtu 4703 * MTU value to set port to. Must be smaller or equal to max_mtu. 4704 * Note: If port type is Infiniband, then port must be disabled, when its 4705 * MTU is set. 4706 * Access: RW 4707 */ 4708 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16); 4709 4710 /* reg_pmtu_oper_mtu 4711 * The actual MTU configured on the port. Packets exceeding this size 4712 * will be dropped. 4713 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband 4714 * oper_mtu might be smaller than admin_mtu. 4715 * Access: RO 4716 */ 4717 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16); 4718 4719 static inline void mlxsw_reg_pmtu_pack(char *payload, u16 local_port, 4720 u16 new_mtu) 4721 { 4722 MLXSW_REG_ZERO(pmtu, payload); 4723 mlxsw_reg_pmtu_local_port_set(payload, local_port); 4724 mlxsw_reg_pmtu_max_mtu_set(payload, 0); 4725 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu); 4726 mlxsw_reg_pmtu_oper_mtu_set(payload, 0); 4727 } 4728 4729 /* PTYS - Port Type and Speed Register 4730 * ----------------------------------- 4731 * Configures and reports the port speed type. 4732 * 4733 * Note: When set while the link is up, the changes will not take effect 4734 * until the port transitions from down to up state. 4735 */ 4736 #define MLXSW_REG_PTYS_ID 0x5004 4737 #define MLXSW_REG_PTYS_LEN 0x40 4738 4739 MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN); 4740 4741 /* an_disable_admin 4742 * Auto negotiation disable administrative configuration 4743 * 0 - Device doesn't support AN disable. 4744 * 1 - Device supports AN disable. 4745 * Access: RW 4746 */ 4747 MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1); 4748 4749 /* reg_ptys_local_port 4750 * Local port number. 4751 * Access: Index 4752 */ 4753 MLXSW_ITEM32_LP(reg, ptys, 0x00, 16, 0x00, 12); 4754 4755 #define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0) 4756 #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2) 4757 4758 /* reg_ptys_proto_mask 4759 * Protocol mask. Indicates which protocol is used. 4760 * 0 - Infiniband. 4761 * 1 - Fibre Channel. 4762 * 2 - Ethernet. 4763 * Access: Index 4764 */ 4765 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3); 4766 4767 enum { 4768 MLXSW_REG_PTYS_AN_STATUS_NA, 4769 MLXSW_REG_PTYS_AN_STATUS_OK, 4770 MLXSW_REG_PTYS_AN_STATUS_FAIL, 4771 }; 4772 4773 /* reg_ptys_an_status 4774 * Autonegotiation status. 4775 * Access: RO 4776 */ 4777 MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4); 4778 4779 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M BIT(0) 4780 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII BIT(1) 4781 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R BIT(3) 4782 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G BIT(4) 4783 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G BIT(5) 4784 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR BIT(6) 4785 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 BIT(7) 4786 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR BIT(8) 4787 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4 BIT(9) 4788 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2 BIT(10) 4789 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4 BIT(12) 4790 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_8 BIT(15) 4791 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_800GAUI_8 BIT(19) 4792 4793 /* reg_ptys_ext_eth_proto_cap 4794 * Extended Ethernet port supported speeds and protocols. 4795 * Access: RO 4796 */ 4797 MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32); 4798 4799 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0) 4800 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1) 4801 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2) 4802 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3) 4803 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4) 4804 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6) 4805 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7) 4806 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12) 4807 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13) 4808 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14) 4809 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15) 4810 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16) 4811 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18) 4812 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19) 4813 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20) 4814 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21) 4815 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22) 4816 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23) 4817 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(24) 4818 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_T BIT(25) 4819 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27) 4820 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28) 4821 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29) 4822 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30) 4823 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31) 4824 4825 /* reg_ptys_eth_proto_cap 4826 * Ethernet port supported speeds and protocols. 4827 * Access: RO 4828 */ 4829 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32); 4830 4831 /* reg_ptys_ext_eth_proto_admin 4832 * Extended speed and protocol to set port to. 4833 * Access: RW 4834 */ 4835 MLXSW_ITEM32(reg, ptys, ext_eth_proto_admin, 0x14, 0, 32); 4836 4837 /* reg_ptys_eth_proto_admin 4838 * Speed and protocol to set port to. 4839 * Access: RW 4840 */ 4841 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32); 4842 4843 /* reg_ptys_ext_eth_proto_oper 4844 * The extended current speed and protocol configured for the port. 4845 * Access: RO 4846 */ 4847 MLXSW_ITEM32(reg, ptys, ext_eth_proto_oper, 0x20, 0, 32); 4848 4849 /* reg_ptys_eth_proto_oper 4850 * The current speed and protocol configured for the port. 4851 * Access: RO 4852 */ 4853 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32); 4854 4855 enum mlxsw_reg_ptys_connector_type { 4856 MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR, 4857 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE, 4858 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP, 4859 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI, 4860 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC, 4861 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII, 4862 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE, 4863 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA, 4864 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER, 4865 }; 4866 4867 /* reg_ptys_connector_type 4868 * Connector type indication. 4869 * Access: RO 4870 */ 4871 MLXSW_ITEM32(reg, ptys, connector_type, 0x2C, 0, 4); 4872 4873 static inline void mlxsw_reg_ptys_eth_pack(char *payload, u16 local_port, 4874 u32 proto_admin, bool autoneg) 4875 { 4876 MLXSW_REG_ZERO(ptys, payload); 4877 mlxsw_reg_ptys_local_port_set(payload, local_port); 4878 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4879 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin); 4880 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4881 } 4882 4883 static inline void mlxsw_reg_ptys_ext_eth_pack(char *payload, u16 local_port, 4884 u32 proto_admin, bool autoneg) 4885 { 4886 MLXSW_REG_ZERO(ptys, payload); 4887 mlxsw_reg_ptys_local_port_set(payload, local_port); 4888 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4889 mlxsw_reg_ptys_ext_eth_proto_admin_set(payload, proto_admin); 4890 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4891 } 4892 4893 static inline void mlxsw_reg_ptys_eth_unpack(char *payload, 4894 u32 *p_eth_proto_cap, 4895 u32 *p_eth_proto_admin, 4896 u32 *p_eth_proto_oper) 4897 { 4898 if (p_eth_proto_cap) 4899 *p_eth_proto_cap = 4900 mlxsw_reg_ptys_eth_proto_cap_get(payload); 4901 if (p_eth_proto_admin) 4902 *p_eth_proto_admin = 4903 mlxsw_reg_ptys_eth_proto_admin_get(payload); 4904 if (p_eth_proto_oper) 4905 *p_eth_proto_oper = 4906 mlxsw_reg_ptys_eth_proto_oper_get(payload); 4907 } 4908 4909 static inline void mlxsw_reg_ptys_ext_eth_unpack(char *payload, 4910 u32 *p_eth_proto_cap, 4911 u32 *p_eth_proto_admin, 4912 u32 *p_eth_proto_oper) 4913 { 4914 if (p_eth_proto_cap) 4915 *p_eth_proto_cap = 4916 mlxsw_reg_ptys_ext_eth_proto_cap_get(payload); 4917 if (p_eth_proto_admin) 4918 *p_eth_proto_admin = 4919 mlxsw_reg_ptys_ext_eth_proto_admin_get(payload); 4920 if (p_eth_proto_oper) 4921 *p_eth_proto_oper = 4922 mlxsw_reg_ptys_ext_eth_proto_oper_get(payload); 4923 } 4924 4925 /* PPAD - Port Physical Address Register 4926 * ------------------------------------- 4927 * The PPAD register configures the per port physical MAC address. 4928 */ 4929 #define MLXSW_REG_PPAD_ID 0x5005 4930 #define MLXSW_REG_PPAD_LEN 0x10 4931 4932 MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN); 4933 4934 /* reg_ppad_single_base_mac 4935 * 0: base_mac, local port should be 0 and mac[7:0] is 4936 * reserved. HW will set incremental 4937 * 1: single_mac - mac of the local_port 4938 * Access: RW 4939 */ 4940 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1); 4941 4942 /* reg_ppad_local_port 4943 * port number, if single_base_mac = 0 then local_port is reserved 4944 * Access: RW 4945 */ 4946 MLXSW_ITEM32_LP(reg, ppad, 0x00, 16, 0x00, 24); 4947 4948 /* reg_ppad_mac 4949 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved. 4950 * If single_base_mac = 1 - the per port MAC address 4951 * Access: RW 4952 */ 4953 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6); 4954 4955 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac, 4956 u16 local_port) 4957 { 4958 MLXSW_REG_ZERO(ppad, payload); 4959 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac); 4960 mlxsw_reg_ppad_local_port_set(payload, local_port); 4961 } 4962 4963 /* PAOS - Ports Administrative and Operational Status Register 4964 * ----------------------------------------------------------- 4965 * Configures and retrieves per port administrative and operational status. 4966 */ 4967 #define MLXSW_REG_PAOS_ID 0x5006 4968 #define MLXSW_REG_PAOS_LEN 0x10 4969 4970 MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN); 4971 4972 /* reg_paos_swid 4973 * Switch partition ID with which to associate the port. 4974 * Note: while external ports uses unique local port numbers (and thus swid is 4975 * redundant), router ports use the same local port number where swid is the 4976 * only indication for the relevant port. 4977 * Access: Index 4978 */ 4979 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8); 4980 4981 /* reg_paos_local_port 4982 * Local port number. 4983 * Access: Index 4984 */ 4985 MLXSW_ITEM32_LP(reg, paos, 0x00, 16, 0x00, 12); 4986 4987 /* reg_paos_admin_status 4988 * Port administrative state (the desired state of the port): 4989 * 1 - Up. 4990 * 2 - Down. 4991 * 3 - Up once. This means that in case of link failure, the port won't go 4992 * into polling mode, but will wait to be re-enabled by software. 4993 * 4 - Disabled by system. Can only be set by hardware. 4994 * Access: RW 4995 */ 4996 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4); 4997 4998 /* reg_paos_oper_status 4999 * Port operational state (the current state): 5000 * 1 - Up. 5001 * 2 - Down. 5002 * 3 - Down by port failure. This means that the device will not let the 5003 * port up again until explicitly specified by software. 5004 * Access: RO 5005 */ 5006 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4); 5007 5008 /* reg_paos_ase 5009 * Admin state update enabled. 5010 * Access: WO 5011 */ 5012 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1); 5013 5014 /* reg_paos_ee 5015 * Event update enable. If this bit is set, event generation will be 5016 * updated based on the e field. 5017 * Access: WO 5018 */ 5019 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1); 5020 5021 /* reg_paos_e 5022 * Event generation on operational state change: 5023 * 0 - Do not generate event. 5024 * 1 - Generate Event. 5025 * 2 - Generate Single Event. 5026 * Access: RW 5027 */ 5028 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2); 5029 5030 static inline void mlxsw_reg_paos_pack(char *payload, u16 local_port, 5031 enum mlxsw_port_admin_status status) 5032 { 5033 MLXSW_REG_ZERO(paos, payload); 5034 mlxsw_reg_paos_swid_set(payload, 0); 5035 mlxsw_reg_paos_local_port_set(payload, local_port); 5036 mlxsw_reg_paos_admin_status_set(payload, status); 5037 mlxsw_reg_paos_oper_status_set(payload, 0); 5038 mlxsw_reg_paos_ase_set(payload, 1); 5039 mlxsw_reg_paos_ee_set(payload, 1); 5040 mlxsw_reg_paos_e_set(payload, 1); 5041 } 5042 5043 /* PFCC - Ports Flow Control Configuration Register 5044 * ------------------------------------------------ 5045 * Configures and retrieves the per port flow control configuration. 5046 */ 5047 #define MLXSW_REG_PFCC_ID 0x5007 5048 #define MLXSW_REG_PFCC_LEN 0x20 5049 5050 MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN); 5051 5052 /* reg_pfcc_local_port 5053 * Local port number. 5054 * Access: Index 5055 */ 5056 MLXSW_ITEM32_LP(reg, pfcc, 0x00, 16, 0x00, 12); 5057 5058 /* reg_pfcc_pnat 5059 * Port number access type. Determines the way local_port is interpreted: 5060 * 0 - Local port number. 5061 * 1 - IB / label port number. 5062 * Access: Index 5063 */ 5064 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2); 5065 5066 /* reg_pfcc_shl_cap 5067 * Send to higher layers capabilities: 5068 * 0 - No capability of sending Pause and PFC frames to higher layers. 5069 * 1 - Device has capability of sending Pause and PFC frames to higher 5070 * layers. 5071 * Access: RO 5072 */ 5073 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1); 5074 5075 /* reg_pfcc_shl_opr 5076 * Send to higher layers operation: 5077 * 0 - Pause and PFC frames are handled by the port (default). 5078 * 1 - Pause and PFC frames are handled by the port and also sent to 5079 * higher layers. Only valid if shl_cap = 1. 5080 * Access: RW 5081 */ 5082 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1); 5083 5084 /* reg_pfcc_ppan 5085 * Pause policy auto negotiation. 5086 * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx. 5087 * 1 - Enabled. When auto-negotiation is performed, set the Pause policy 5088 * based on the auto-negotiation resolution. 5089 * Access: RW 5090 * 5091 * Note: The auto-negotiation advertisement is set according to pptx and 5092 * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0. 5093 */ 5094 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4); 5095 5096 /* reg_pfcc_prio_mask_tx 5097 * Bit per priority indicating if Tx flow control policy should be 5098 * updated based on bit pfctx. 5099 * Access: WO 5100 */ 5101 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8); 5102 5103 /* reg_pfcc_prio_mask_rx 5104 * Bit per priority indicating if Rx flow control policy should be 5105 * updated based on bit pfcrx. 5106 * Access: WO 5107 */ 5108 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8); 5109 5110 /* reg_pfcc_pptx 5111 * Admin Pause policy on Tx. 5112 * 0 - Never generate Pause frames (default). 5113 * 1 - Generate Pause frames according to Rx buffer threshold. 5114 * Access: RW 5115 */ 5116 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1); 5117 5118 /* reg_pfcc_aptx 5119 * Active (operational) Pause policy on Tx. 5120 * 0 - Never generate Pause frames. 5121 * 1 - Generate Pause frames according to Rx buffer threshold. 5122 * Access: RO 5123 */ 5124 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1); 5125 5126 /* reg_pfcc_pfctx 5127 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask: 5128 * 0 - Never generate priority Pause frames on the specified priority 5129 * (default). 5130 * 1 - Generate priority Pause frames according to Rx buffer threshold on 5131 * the specified priority. 5132 * Access: RW 5133 * 5134 * Note: pfctx and pptx must be mutually exclusive. 5135 */ 5136 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8); 5137 5138 /* reg_pfcc_pprx 5139 * Admin Pause policy on Rx. 5140 * 0 - Ignore received Pause frames (default). 5141 * 1 - Respect received Pause frames. 5142 * Access: RW 5143 */ 5144 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1); 5145 5146 /* reg_pfcc_aprx 5147 * Active (operational) Pause policy on Rx. 5148 * 0 - Ignore received Pause frames. 5149 * 1 - Respect received Pause frames. 5150 * Access: RO 5151 */ 5152 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1); 5153 5154 /* reg_pfcc_pfcrx 5155 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask: 5156 * 0 - Ignore incoming priority Pause frames on the specified priority 5157 * (default). 5158 * 1 - Respect incoming priority Pause frames on the specified priority. 5159 * Access: RW 5160 */ 5161 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8); 5162 5163 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF 5164 5165 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en) 5166 { 5167 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 5168 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 5169 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en); 5170 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en); 5171 } 5172 5173 static inline void mlxsw_reg_pfcc_pack(char *payload, u16 local_port) 5174 { 5175 MLXSW_REG_ZERO(pfcc, payload); 5176 mlxsw_reg_pfcc_local_port_set(payload, local_port); 5177 } 5178 5179 /* PPCNT - Ports Performance Counters Register 5180 * ------------------------------------------- 5181 * The PPCNT register retrieves per port performance counters. 5182 */ 5183 #define MLXSW_REG_PPCNT_ID 0x5008 5184 #define MLXSW_REG_PPCNT_LEN 0x100 5185 #define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08 5186 5187 MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN); 5188 5189 /* reg_ppcnt_swid 5190 * For HCA: must be always 0. 5191 * Switch partition ID to associate port with. 5192 * Switch partitions are numbered from 0 to 7 inclusively. 5193 * Switch partition 254 indicates stacking ports. 5194 * Switch partition 255 indicates all switch partitions. 5195 * Only valid on Set() operation with local_port=255. 5196 * Access: Index 5197 */ 5198 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8); 5199 5200 /* reg_ppcnt_local_port 5201 * Local port number. 5202 * Access: Index 5203 */ 5204 MLXSW_ITEM32_LP(reg, ppcnt, 0x00, 16, 0x00, 12); 5205 5206 /* reg_ppcnt_pnat 5207 * Port number access type: 5208 * 0 - Local port number 5209 * 1 - IB port number 5210 * Access: Index 5211 */ 5212 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2); 5213 5214 enum mlxsw_reg_ppcnt_grp { 5215 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0, 5216 MLXSW_REG_PPCNT_RFC_2863_CNT = 0x1, 5217 MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2, 5218 MLXSW_REG_PPCNT_RFC_3635_CNT = 0x3, 5219 MLXSW_REG_PPCNT_EXT_CNT = 0x5, 5220 MLXSW_REG_PPCNT_DISCARD_CNT = 0x6, 5221 MLXSW_REG_PPCNT_PRIO_CNT = 0x10, 5222 MLXSW_REG_PPCNT_TC_CNT = 0x11, 5223 MLXSW_REG_PPCNT_TC_CONG_CNT = 0x13, 5224 }; 5225 5226 /* reg_ppcnt_grp 5227 * Performance counter group. 5228 * Group 63 indicates all groups. Only valid on Set() operation with 5229 * clr bit set. 5230 * 0x0: IEEE 802.3 Counters 5231 * 0x1: RFC 2863 Counters 5232 * 0x2: RFC 2819 Counters 5233 * 0x3: RFC 3635 Counters 5234 * 0x5: Ethernet Extended Counters 5235 * 0x6: Ethernet Discard Counters 5236 * 0x8: Link Level Retransmission Counters 5237 * 0x10: Per Priority Counters 5238 * 0x11: Per Traffic Class Counters 5239 * 0x12: Physical Layer Counters 5240 * 0x13: Per Traffic Class Congestion Counters 5241 * Access: Index 5242 */ 5243 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6); 5244 5245 /* reg_ppcnt_clr 5246 * Clear counters. Setting the clr bit will reset the counter value 5247 * for all counters in the counter group. This bit can be set 5248 * for both Set() and Get() operation. 5249 * Access: OP 5250 */ 5251 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1); 5252 5253 /* reg_ppcnt_lp_gl 5254 * Local port global variable. 5255 * 0: local_port 255 = all ports of the device. 5256 * 1: local_port indicates local port number for all ports. 5257 * Access: OP 5258 */ 5259 MLXSW_ITEM32(reg, ppcnt, lp_gl, 0x04, 30, 1); 5260 5261 /* reg_ppcnt_prio_tc 5262 * Priority for counter set that support per priority, valid values: 0-7. 5263 * Traffic class for counter set that support per traffic class, 5264 * valid values: 0- cap_max_tclass-1 . 5265 * For HCA: cap_max_tclass is always 8. 5266 * Otherwise must be 0. 5267 * Access: Index 5268 */ 5269 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5); 5270 5271 /* Ethernet IEEE 802.3 Counter Group */ 5272 5273 /* reg_ppcnt_a_frames_transmitted_ok 5274 * Access: RO 5275 */ 5276 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok, 5277 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5278 5279 /* reg_ppcnt_a_frames_received_ok 5280 * Access: RO 5281 */ 5282 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok, 5283 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5284 5285 /* reg_ppcnt_a_frame_check_sequence_errors 5286 * Access: RO 5287 */ 5288 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors, 5289 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 5290 5291 /* reg_ppcnt_a_alignment_errors 5292 * Access: RO 5293 */ 5294 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors, 5295 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 5296 5297 /* reg_ppcnt_a_octets_transmitted_ok 5298 * Access: RO 5299 */ 5300 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok, 5301 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5302 5303 /* reg_ppcnt_a_octets_received_ok 5304 * Access: RO 5305 */ 5306 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok, 5307 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5308 5309 /* reg_ppcnt_a_multicast_frames_xmitted_ok 5310 * Access: RO 5311 */ 5312 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok, 5313 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 5314 5315 /* reg_ppcnt_a_broadcast_frames_xmitted_ok 5316 * Access: RO 5317 */ 5318 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok, 5319 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 5320 5321 /* reg_ppcnt_a_multicast_frames_received_ok 5322 * Access: RO 5323 */ 5324 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok, 5325 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5326 5327 /* reg_ppcnt_a_broadcast_frames_received_ok 5328 * Access: RO 5329 */ 5330 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok, 5331 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 5332 5333 /* reg_ppcnt_a_in_range_length_errors 5334 * Access: RO 5335 */ 5336 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors, 5337 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5338 5339 /* reg_ppcnt_a_out_of_range_length_field 5340 * Access: RO 5341 */ 5342 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field, 5343 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5344 5345 /* reg_ppcnt_a_frame_too_long_errors 5346 * Access: RO 5347 */ 5348 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors, 5349 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5350 5351 /* reg_ppcnt_a_symbol_error_during_carrier 5352 * Access: RO 5353 */ 5354 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier, 5355 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5356 5357 /* reg_ppcnt_a_mac_control_frames_transmitted 5358 * Access: RO 5359 */ 5360 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted, 5361 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5362 5363 /* reg_ppcnt_a_mac_control_frames_received 5364 * Access: RO 5365 */ 5366 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received, 5367 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 5368 5369 /* reg_ppcnt_a_unsupported_opcodes_received 5370 * Access: RO 5371 */ 5372 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received, 5373 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 5374 5375 /* reg_ppcnt_a_pause_mac_ctrl_frames_received 5376 * Access: RO 5377 */ 5378 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received, 5379 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 5380 5381 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted 5382 * Access: RO 5383 */ 5384 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted, 5385 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 5386 5387 /* Ethernet RFC 2863 Counter Group */ 5388 5389 /* reg_ppcnt_if_in_discards 5390 * Access: RO 5391 */ 5392 MLXSW_ITEM64(reg, ppcnt, if_in_discards, 5393 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 5394 5395 /* reg_ppcnt_if_out_discards 5396 * Access: RO 5397 */ 5398 MLXSW_ITEM64(reg, ppcnt, if_out_discards, 5399 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 5400 5401 /* reg_ppcnt_if_out_errors 5402 * Access: RO 5403 */ 5404 MLXSW_ITEM64(reg, ppcnt, if_out_errors, 5405 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5406 5407 /* Ethernet RFC 2819 Counter Group */ 5408 5409 /* reg_ppcnt_ether_stats_undersize_pkts 5410 * Access: RO 5411 */ 5412 MLXSW_ITEM64(reg, ppcnt, ether_stats_undersize_pkts, 5413 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 5414 5415 /* reg_ppcnt_ether_stats_oversize_pkts 5416 * Access: RO 5417 */ 5418 MLXSW_ITEM64(reg, ppcnt, ether_stats_oversize_pkts, 5419 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 5420 5421 /* reg_ppcnt_ether_stats_fragments 5422 * Access: RO 5423 */ 5424 MLXSW_ITEM64(reg, ppcnt, ether_stats_fragments, 5425 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5426 5427 /* reg_ppcnt_ether_stats_pkts64octets 5428 * Access: RO 5429 */ 5430 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets, 5431 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5432 5433 /* reg_ppcnt_ether_stats_pkts65to127octets 5434 * Access: RO 5435 */ 5436 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets, 5437 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5438 5439 /* reg_ppcnt_ether_stats_pkts128to255octets 5440 * Access: RO 5441 */ 5442 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets, 5443 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5444 5445 /* reg_ppcnt_ether_stats_pkts256to511octets 5446 * Access: RO 5447 */ 5448 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets, 5449 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5450 5451 /* reg_ppcnt_ether_stats_pkts512to1023octets 5452 * Access: RO 5453 */ 5454 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets, 5455 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 5456 5457 /* reg_ppcnt_ether_stats_pkts1024to1518octets 5458 * Access: RO 5459 */ 5460 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets, 5461 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 5462 5463 /* reg_ppcnt_ether_stats_pkts1519to2047octets 5464 * Access: RO 5465 */ 5466 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets, 5467 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 5468 5469 /* reg_ppcnt_ether_stats_pkts2048to4095octets 5470 * Access: RO 5471 */ 5472 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets, 5473 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 5474 5475 /* reg_ppcnt_ether_stats_pkts4096to8191octets 5476 * Access: RO 5477 */ 5478 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets, 5479 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64); 5480 5481 /* reg_ppcnt_ether_stats_pkts8192to10239octets 5482 * Access: RO 5483 */ 5484 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets, 5485 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64); 5486 5487 /* Ethernet RFC 3635 Counter Group */ 5488 5489 /* reg_ppcnt_dot3stats_fcs_errors 5490 * Access: RO 5491 */ 5492 MLXSW_ITEM64(reg, ppcnt, dot3stats_fcs_errors, 5493 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5494 5495 /* reg_ppcnt_dot3stats_symbol_errors 5496 * Access: RO 5497 */ 5498 MLXSW_ITEM64(reg, ppcnt, dot3stats_symbol_errors, 5499 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5500 5501 /* reg_ppcnt_dot3control_in_unknown_opcodes 5502 * Access: RO 5503 */ 5504 MLXSW_ITEM64(reg, ppcnt, dot3control_in_unknown_opcodes, 5505 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5506 5507 /* reg_ppcnt_dot3in_pause_frames 5508 * Access: RO 5509 */ 5510 MLXSW_ITEM64(reg, ppcnt, dot3in_pause_frames, 5511 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5512 5513 /* Ethernet Extended Counter Group Counters */ 5514 5515 /* reg_ppcnt_ecn_marked 5516 * Access: RO 5517 */ 5518 MLXSW_ITEM64(reg, ppcnt, ecn_marked, 5519 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5520 5521 /* Ethernet Discard Counter Group Counters */ 5522 5523 /* reg_ppcnt_ingress_general 5524 * Access: RO 5525 */ 5526 MLXSW_ITEM64(reg, ppcnt, ingress_general, 5527 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5528 5529 /* reg_ppcnt_ingress_policy_engine 5530 * Access: RO 5531 */ 5532 MLXSW_ITEM64(reg, ppcnt, ingress_policy_engine, 5533 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5534 5535 /* reg_ppcnt_ingress_vlan_membership 5536 * Access: RO 5537 */ 5538 MLXSW_ITEM64(reg, ppcnt, ingress_vlan_membership, 5539 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 5540 5541 /* reg_ppcnt_ingress_tag_frame_type 5542 * Access: RO 5543 */ 5544 MLXSW_ITEM64(reg, ppcnt, ingress_tag_frame_type, 5545 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 5546 5547 /* reg_ppcnt_egress_vlan_membership 5548 * Access: RO 5549 */ 5550 MLXSW_ITEM64(reg, ppcnt, egress_vlan_membership, 5551 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5552 5553 /* reg_ppcnt_loopback_filter 5554 * Access: RO 5555 */ 5556 MLXSW_ITEM64(reg, ppcnt, loopback_filter, 5557 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5558 5559 /* reg_ppcnt_egress_general 5560 * Access: RO 5561 */ 5562 MLXSW_ITEM64(reg, ppcnt, egress_general, 5563 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 5564 5565 /* reg_ppcnt_egress_hoq 5566 * Access: RO 5567 */ 5568 MLXSW_ITEM64(reg, ppcnt, egress_hoq, 5569 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5570 5571 /* reg_ppcnt_egress_policy_engine 5572 * Access: RO 5573 */ 5574 MLXSW_ITEM64(reg, ppcnt, egress_policy_engine, 5575 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5576 5577 /* reg_ppcnt_ingress_tx_link_down 5578 * Access: RO 5579 */ 5580 MLXSW_ITEM64(reg, ppcnt, ingress_tx_link_down, 5581 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5582 5583 /* reg_ppcnt_egress_stp_filter 5584 * Access: RO 5585 */ 5586 MLXSW_ITEM64(reg, ppcnt, egress_stp_filter, 5587 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5588 5589 /* reg_ppcnt_egress_sll 5590 * Access: RO 5591 */ 5592 MLXSW_ITEM64(reg, ppcnt, egress_sll, 5593 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5594 5595 /* Ethernet Per Priority Group Counters */ 5596 5597 /* reg_ppcnt_rx_octets 5598 * Access: RO 5599 */ 5600 MLXSW_ITEM64(reg, ppcnt, rx_octets, 5601 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5602 5603 /* reg_ppcnt_rx_frames 5604 * Access: RO 5605 */ 5606 MLXSW_ITEM64(reg, ppcnt, rx_frames, 5607 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5608 5609 /* reg_ppcnt_tx_octets 5610 * Access: RO 5611 */ 5612 MLXSW_ITEM64(reg, ppcnt, tx_octets, 5613 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5614 5615 /* reg_ppcnt_tx_frames 5616 * Access: RO 5617 */ 5618 MLXSW_ITEM64(reg, ppcnt, tx_frames, 5619 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 5620 5621 /* reg_ppcnt_rx_pause 5622 * Access: RO 5623 */ 5624 MLXSW_ITEM64(reg, ppcnt, rx_pause, 5625 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5626 5627 /* reg_ppcnt_rx_pause_duration 5628 * Access: RO 5629 */ 5630 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration, 5631 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5632 5633 /* reg_ppcnt_tx_pause 5634 * Access: RO 5635 */ 5636 MLXSW_ITEM64(reg, ppcnt, tx_pause, 5637 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5638 5639 /* reg_ppcnt_tx_pause_duration 5640 * Access: RO 5641 */ 5642 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration, 5643 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5644 5645 /* reg_ppcnt_rx_pause_transition 5646 * Access: RO 5647 */ 5648 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition, 5649 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5650 5651 /* Ethernet Per Traffic Class Counters */ 5652 5653 /* reg_ppcnt_tc_transmit_queue 5654 * Contains the transmit queue depth in cells of traffic class 5655 * selected by prio_tc and the port selected by local_port. 5656 * The field cannot be cleared. 5657 * Access: RO 5658 */ 5659 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue, 5660 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5661 5662 /* reg_ppcnt_tc_no_buffer_discard_uc 5663 * The number of unicast packets dropped due to lack of shared 5664 * buffer resources. 5665 * Access: RO 5666 */ 5667 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc, 5668 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5669 5670 /* Ethernet Per Traffic Class Congestion Group Counters */ 5671 5672 /* reg_ppcnt_wred_discard 5673 * Access: RO 5674 */ 5675 MLXSW_ITEM64(reg, ppcnt, wred_discard, 5676 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5677 5678 /* reg_ppcnt_ecn_marked_tc 5679 * Access: RO 5680 */ 5681 MLXSW_ITEM64(reg, ppcnt, ecn_marked_tc, 5682 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5683 5684 static inline void mlxsw_reg_ppcnt_pack(char *payload, u16 local_port, 5685 enum mlxsw_reg_ppcnt_grp grp, 5686 u8 prio_tc) 5687 { 5688 MLXSW_REG_ZERO(ppcnt, payload); 5689 mlxsw_reg_ppcnt_swid_set(payload, 0); 5690 mlxsw_reg_ppcnt_local_port_set(payload, local_port); 5691 mlxsw_reg_ppcnt_pnat_set(payload, 0); 5692 mlxsw_reg_ppcnt_grp_set(payload, grp); 5693 mlxsw_reg_ppcnt_clr_set(payload, 0); 5694 mlxsw_reg_ppcnt_lp_gl_set(payload, 1); 5695 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc); 5696 } 5697 5698 /* PPTB - Port Prio To Buffer Register 5699 * ----------------------------------- 5700 * Configures the switch priority to buffer table. 5701 */ 5702 #define MLXSW_REG_PPTB_ID 0x500B 5703 #define MLXSW_REG_PPTB_LEN 0x10 5704 5705 MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN); 5706 5707 enum { 5708 MLXSW_REG_PPTB_MM_UM, 5709 MLXSW_REG_PPTB_MM_UNICAST, 5710 MLXSW_REG_PPTB_MM_MULTICAST, 5711 }; 5712 5713 /* reg_pptb_mm 5714 * Mapping mode. 5715 * 0 - Map both unicast and multicast packets to the same buffer. 5716 * 1 - Map only unicast packets. 5717 * 2 - Map only multicast packets. 5718 * Access: Index 5719 * 5720 * Note: SwitchX-2 only supports the first option. 5721 */ 5722 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2); 5723 5724 /* reg_pptb_local_port 5725 * Local port number. 5726 * Access: Index 5727 */ 5728 MLXSW_ITEM32_LP(reg, pptb, 0x00, 16, 0x00, 12); 5729 5730 /* reg_pptb_um 5731 * Enables the update of the untagged_buf field. 5732 * Access: RW 5733 */ 5734 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1); 5735 5736 /* reg_pptb_pm 5737 * Enables the update of the prio_to_buff field. 5738 * Bit <i> is a flag for updating the mapping for switch priority <i>. 5739 * Access: RW 5740 */ 5741 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8); 5742 5743 /* reg_pptb_prio_to_buff 5744 * Mapping of switch priority <i> to one of the allocated receive port 5745 * buffers. 5746 * Access: RW 5747 */ 5748 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4); 5749 5750 /* reg_pptb_pm_msb 5751 * Enables the update of the prio_to_buff field. 5752 * Bit <i> is a flag for updating the mapping for switch priority <i+8>. 5753 * Access: RW 5754 */ 5755 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8); 5756 5757 /* reg_pptb_untagged_buff 5758 * Mapping of untagged frames to one of the allocated receive port buffers. 5759 * Access: RW 5760 * 5761 * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for 5762 * Spectrum, as it maps untagged packets based on the default switch priority. 5763 */ 5764 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4); 5765 5766 /* reg_pptb_prio_to_buff_msb 5767 * Mapping of switch priority <i+8> to one of the allocated receive port 5768 * buffers. 5769 * Access: RW 5770 */ 5771 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4); 5772 5773 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF 5774 5775 static inline void mlxsw_reg_pptb_pack(char *payload, u16 local_port) 5776 { 5777 MLXSW_REG_ZERO(pptb, payload); 5778 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM); 5779 mlxsw_reg_pptb_local_port_set(payload, local_port); 5780 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 5781 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 5782 } 5783 5784 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio, 5785 u8 buff) 5786 { 5787 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff); 5788 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff); 5789 } 5790 5791 /* PBMC - Port Buffer Management Control Register 5792 * ---------------------------------------------- 5793 * The PBMC register configures and retrieves the port packet buffer 5794 * allocation for different Prios, and the Pause threshold management. 5795 */ 5796 #define MLXSW_REG_PBMC_ID 0x500C 5797 #define MLXSW_REG_PBMC_LEN 0x6C 5798 5799 MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN); 5800 5801 /* reg_pbmc_local_port 5802 * Local port number. 5803 * Access: Index 5804 */ 5805 MLXSW_ITEM32_LP(reg, pbmc, 0x00, 16, 0x00, 12); 5806 5807 /* reg_pbmc_xoff_timer_value 5808 * When device generates a pause frame, it uses this value as the pause 5809 * timer (time for the peer port to pause in quota-512 bit time). 5810 * Access: RW 5811 */ 5812 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16); 5813 5814 /* reg_pbmc_xoff_refresh 5815 * The time before a new pause frame should be sent to refresh the pause RW 5816 * state. Using the same units as xoff_timer_value above (in quota-512 bit 5817 * time). 5818 * Access: RW 5819 */ 5820 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16); 5821 5822 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11 5823 5824 /* reg_pbmc_buf_lossy 5825 * The field indicates if the buffer is lossy. 5826 * 0 - Lossless 5827 * 1 - Lossy 5828 * Access: RW 5829 */ 5830 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false); 5831 5832 /* reg_pbmc_buf_epsb 5833 * Eligible for Port Shared buffer. 5834 * If epsb is set, packets assigned to buffer are allowed to insert the port 5835 * shared buffer. 5836 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved. 5837 * Access: RW 5838 */ 5839 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false); 5840 5841 /* reg_pbmc_buf_size 5842 * The part of the packet buffer array is allocated for the specific buffer. 5843 * Units are represented in cells. 5844 * Access: RW 5845 */ 5846 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false); 5847 5848 /* reg_pbmc_buf_xoff_threshold 5849 * Once the amount of data in the buffer goes above this value, device 5850 * starts sending PFC frames for all priorities associated with the 5851 * buffer. Units are represented in cells. Reserved in case of lossy 5852 * buffer. 5853 * Access: RW 5854 * 5855 * Note: In Spectrum, reserved for buffer[9]. 5856 */ 5857 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16, 5858 0x08, 0x04, false); 5859 5860 /* reg_pbmc_buf_xon_threshold 5861 * When the amount of data in the buffer goes below this value, device 5862 * stops sending PFC frames for the priorities associated with the 5863 * buffer. Units are represented in cells. Reserved in case of lossy 5864 * buffer. 5865 * Access: RW 5866 * 5867 * Note: In Spectrum, reserved for buffer[9]. 5868 */ 5869 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16, 5870 0x08, 0x04, false); 5871 5872 static inline void mlxsw_reg_pbmc_pack(char *payload, u16 local_port, 5873 u16 xoff_timer_value, u16 xoff_refresh) 5874 { 5875 MLXSW_REG_ZERO(pbmc, payload); 5876 mlxsw_reg_pbmc_local_port_set(payload, local_port); 5877 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value); 5878 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh); 5879 } 5880 5881 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload, 5882 int buf_index, 5883 u16 size) 5884 { 5885 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1); 5886 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5887 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5888 } 5889 5890 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload, 5891 int buf_index, u16 size, 5892 u16 threshold) 5893 { 5894 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0); 5895 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5896 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5897 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold); 5898 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold); 5899 } 5900 5901 /* PSPA - Port Switch Partition Allocation 5902 * --------------------------------------- 5903 * Controls the association of a port with a switch partition and enables 5904 * configuring ports as stacking ports. 5905 */ 5906 #define MLXSW_REG_PSPA_ID 0x500D 5907 #define MLXSW_REG_PSPA_LEN 0x8 5908 5909 MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN); 5910 5911 /* reg_pspa_swid 5912 * Switch partition ID. 5913 * Access: RW 5914 */ 5915 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8); 5916 5917 /* reg_pspa_local_port 5918 * Local port number. 5919 * Access: Index 5920 */ 5921 MLXSW_ITEM32_LP(reg, pspa, 0x00, 16, 0x00, 0); 5922 5923 /* reg_pspa_sub_port 5924 * Virtual port within the local port. Set to 0 when virtual ports are 5925 * disabled on the local port. 5926 * Access: Index 5927 */ 5928 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8); 5929 5930 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u16 local_port) 5931 { 5932 MLXSW_REG_ZERO(pspa, payload); 5933 mlxsw_reg_pspa_swid_set(payload, swid); 5934 mlxsw_reg_pspa_local_port_set(payload, local_port); 5935 mlxsw_reg_pspa_sub_port_set(payload, 0); 5936 } 5937 5938 /* PMAOS - Ports Module Administrative and Operational Status 5939 * ---------------------------------------------------------- 5940 * This register configures and retrieves the per module status. 5941 */ 5942 #define MLXSW_REG_PMAOS_ID 0x5012 5943 #define MLXSW_REG_PMAOS_LEN 0x10 5944 5945 MLXSW_REG_DEFINE(pmaos, MLXSW_REG_PMAOS_ID, MLXSW_REG_PMAOS_LEN); 5946 5947 /* reg_pmaos_rst 5948 * Module reset toggle. 5949 * Note: Setting reset while module is plugged-in will result in transition to 5950 * "initializing" operational state. 5951 * Access: OP 5952 */ 5953 MLXSW_ITEM32(reg, pmaos, rst, 0x00, 31, 1); 5954 5955 /* reg_pmaos_slot_index 5956 * Slot index. 5957 * Access: Index 5958 */ 5959 MLXSW_ITEM32(reg, pmaos, slot_index, 0x00, 24, 4); 5960 5961 /* reg_pmaos_module 5962 * Module number. 5963 * Access: Index 5964 */ 5965 MLXSW_ITEM32(reg, pmaos, module, 0x00, 16, 8); 5966 5967 enum mlxsw_reg_pmaos_admin_status { 5968 MLXSW_REG_PMAOS_ADMIN_STATUS_ENABLED = 1, 5969 MLXSW_REG_PMAOS_ADMIN_STATUS_DISABLED = 2, 5970 /* If the module is active and then unplugged, or experienced an error 5971 * event, the operational status should go to "disabled" and can only 5972 * be enabled upon explicit enable command. 5973 */ 5974 MLXSW_REG_PMAOS_ADMIN_STATUS_ENABLED_ONCE = 3, 5975 }; 5976 5977 /* reg_pmaos_admin_status 5978 * Module administrative state (the desired state of the module). 5979 * Note: To disable a module, all ports associated with the port must be 5980 * administatively down first. 5981 * Access: RW 5982 */ 5983 MLXSW_ITEM32(reg, pmaos, admin_status, 0x00, 8, 4); 5984 5985 /* reg_pmaos_ase 5986 * Admin state update enable. 5987 * If this bit is set, admin state will be updated based on admin_state field. 5988 * Only relevant on Set() operations. 5989 * Access: WO 5990 */ 5991 MLXSW_ITEM32(reg, pmaos, ase, 0x04, 31, 1); 5992 5993 /* reg_pmaos_ee 5994 * Event update enable. 5995 * If this bit is set, event generation will be updated based on the e field. 5996 * Only relevant on Set operations. 5997 * Access: WO 5998 */ 5999 MLXSW_ITEM32(reg, pmaos, ee, 0x04, 30, 1); 6000 6001 enum mlxsw_reg_pmaos_e { 6002 MLXSW_REG_PMAOS_E_DO_NOT_GENERATE_EVENT, 6003 MLXSW_REG_PMAOS_E_GENERATE_EVENT, 6004 MLXSW_REG_PMAOS_E_GENERATE_SINGLE_EVENT, 6005 }; 6006 6007 /* reg_pmaos_e 6008 * Event Generation on operational state change. 6009 * Access: RW 6010 */ 6011 MLXSW_ITEM32(reg, pmaos, e, 0x04, 0, 2); 6012 6013 static inline void mlxsw_reg_pmaos_pack(char *payload, u8 slot_index, u8 module) 6014 { 6015 MLXSW_REG_ZERO(pmaos, payload); 6016 mlxsw_reg_pmaos_slot_index_set(payload, slot_index); 6017 mlxsw_reg_pmaos_module_set(payload, module); 6018 } 6019 6020 /* PPLR - Port Physical Loopback Register 6021 * -------------------------------------- 6022 * This register allows configuration of the port's loopback mode. 6023 */ 6024 #define MLXSW_REG_PPLR_ID 0x5018 6025 #define MLXSW_REG_PPLR_LEN 0x8 6026 6027 MLXSW_REG_DEFINE(pplr, MLXSW_REG_PPLR_ID, MLXSW_REG_PPLR_LEN); 6028 6029 /* reg_pplr_local_port 6030 * Local port number. 6031 * Access: Index 6032 */ 6033 MLXSW_ITEM32_LP(reg, pplr, 0x00, 16, 0x00, 12); 6034 6035 /* Phy local loopback. When set the port's egress traffic is looped back 6036 * to the receiver and the port transmitter is disabled. 6037 */ 6038 #define MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL BIT(1) 6039 6040 /* reg_pplr_lb_en 6041 * Loopback enable. 6042 * Access: RW 6043 */ 6044 MLXSW_ITEM32(reg, pplr, lb_en, 0x04, 0, 8); 6045 6046 static inline void mlxsw_reg_pplr_pack(char *payload, u16 local_port, 6047 bool phy_local) 6048 { 6049 MLXSW_REG_ZERO(pplr, payload); 6050 mlxsw_reg_pplr_local_port_set(payload, local_port); 6051 mlxsw_reg_pplr_lb_en_set(payload, 6052 phy_local ? 6053 MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL : 0); 6054 } 6055 6056 /* PMTDB - Port Module To local DataBase Register 6057 * ---------------------------------------------- 6058 * The PMTDB register allows to query the possible module<->local port 6059 * mapping than can be used in PMLP. It does not represent the actual/current 6060 * mapping of the local to module. Actual mapping is only defined by PMLP. 6061 */ 6062 #define MLXSW_REG_PMTDB_ID 0x501A 6063 #define MLXSW_REG_PMTDB_LEN 0x40 6064 6065 MLXSW_REG_DEFINE(pmtdb, MLXSW_REG_PMTDB_ID, MLXSW_REG_PMTDB_LEN); 6066 6067 /* reg_pmtdb_slot_index 6068 * Slot index (0: Main board). 6069 * Access: Index 6070 */ 6071 MLXSW_ITEM32(reg, pmtdb, slot_index, 0x00, 24, 4); 6072 6073 /* reg_pmtdb_module 6074 * Module number. 6075 * Access: Index 6076 */ 6077 MLXSW_ITEM32(reg, pmtdb, module, 0x00, 16, 8); 6078 6079 /* reg_pmtdb_ports_width 6080 * Port's width 6081 * Access: Index 6082 */ 6083 MLXSW_ITEM32(reg, pmtdb, ports_width, 0x00, 12, 4); 6084 6085 /* reg_pmtdb_num_ports 6086 * Number of ports in a single module (split/breakout) 6087 * Access: Index 6088 */ 6089 MLXSW_ITEM32(reg, pmtdb, num_ports, 0x00, 8, 4); 6090 6091 enum mlxsw_reg_pmtdb_status { 6092 MLXSW_REG_PMTDB_STATUS_SUCCESS, 6093 }; 6094 6095 /* reg_pmtdb_status 6096 * Status 6097 * Access: RO 6098 */ 6099 MLXSW_ITEM32(reg, pmtdb, status, 0x00, 0, 4); 6100 6101 /* reg_pmtdb_port_num 6102 * The local_port value which can be assigned to the module. 6103 * In case of more than one port, port<x> represent the /<x> port of 6104 * the module. 6105 * Access: RO 6106 */ 6107 MLXSW_ITEM16_INDEXED(reg, pmtdb, port_num, 0x04, 0, 10, 0x02, 0x00, false); 6108 6109 static inline void mlxsw_reg_pmtdb_pack(char *payload, u8 slot_index, u8 module, 6110 u8 ports_width, u8 num_ports) 6111 { 6112 MLXSW_REG_ZERO(pmtdb, payload); 6113 mlxsw_reg_pmtdb_slot_index_set(payload, slot_index); 6114 mlxsw_reg_pmtdb_module_set(payload, module); 6115 mlxsw_reg_pmtdb_ports_width_set(payload, ports_width); 6116 mlxsw_reg_pmtdb_num_ports_set(payload, num_ports); 6117 } 6118 6119 /* PMECR - Ports Mapping Event Configuration Register 6120 * -------------------------------------------------- 6121 * The PMECR register is used to enable/disable event triggering 6122 * in case of local port mapping change. 6123 */ 6124 #define MLXSW_REG_PMECR_ID 0x501B 6125 #define MLXSW_REG_PMECR_LEN 0x20 6126 6127 MLXSW_REG_DEFINE(pmecr, MLXSW_REG_PMECR_ID, MLXSW_REG_PMECR_LEN); 6128 6129 /* reg_pmecr_local_port 6130 * Local port number. 6131 * Access: Index 6132 */ 6133 MLXSW_ITEM32_LP(reg, pmecr, 0x00, 16, 0x00, 12); 6134 6135 /* reg_pmecr_ee 6136 * Event update enable. If this bit is set, event generation will be updated 6137 * based on the e field. Only relevant on Set operations. 6138 * Access: WO 6139 */ 6140 MLXSW_ITEM32(reg, pmecr, ee, 0x04, 30, 1); 6141 6142 /* reg_pmecr_eswi 6143 * Software ignore enable bit. If this bit is set, the value of swi is used. 6144 * If this bit is clear, the value of swi is ignored. 6145 * Only relevant on Set operations. 6146 * Access: WO 6147 */ 6148 MLXSW_ITEM32(reg, pmecr, eswi, 0x04, 24, 1); 6149 6150 /* reg_pmecr_swi 6151 * Software ignore. If this bit is set, the device shouldn't generate events 6152 * in case of PMLP SET operation but only upon self local port mapping change 6153 * (if applicable according to e configuration). This is supplementary 6154 * configuration on top of e value. 6155 * Access: RW 6156 */ 6157 MLXSW_ITEM32(reg, pmecr, swi, 0x04, 8, 1); 6158 6159 enum mlxsw_reg_pmecr_e { 6160 MLXSW_REG_PMECR_E_DO_NOT_GENERATE_EVENT, 6161 MLXSW_REG_PMECR_E_GENERATE_EVENT, 6162 MLXSW_REG_PMECR_E_GENERATE_SINGLE_EVENT, 6163 }; 6164 6165 /* reg_pmecr_e 6166 * Event generation on local port mapping change. 6167 * Access: RW 6168 */ 6169 MLXSW_ITEM32(reg, pmecr, e, 0x04, 0, 2); 6170 6171 static inline void mlxsw_reg_pmecr_pack(char *payload, u16 local_port, 6172 enum mlxsw_reg_pmecr_e e) 6173 { 6174 MLXSW_REG_ZERO(pmecr, payload); 6175 mlxsw_reg_pmecr_local_port_set(payload, local_port); 6176 mlxsw_reg_pmecr_e_set(payload, e); 6177 mlxsw_reg_pmecr_ee_set(payload, true); 6178 mlxsw_reg_pmecr_swi_set(payload, true); 6179 mlxsw_reg_pmecr_eswi_set(payload, true); 6180 } 6181 6182 /* PMPE - Port Module Plug/Unplug Event Register 6183 * --------------------------------------------- 6184 * This register reports any operational status change of a module. 6185 * A change in the module’s state will generate an event only if the change 6186 * happens after arming the event mechanism. Any changes to the module state 6187 * while the event mechanism is not armed will not be reported. Software can 6188 * query the PMPE register for module status. 6189 */ 6190 #define MLXSW_REG_PMPE_ID 0x5024 6191 #define MLXSW_REG_PMPE_LEN 0x10 6192 6193 MLXSW_REG_DEFINE(pmpe, MLXSW_REG_PMPE_ID, MLXSW_REG_PMPE_LEN); 6194 6195 /* reg_pmpe_slot_index 6196 * Slot index. 6197 * Access: Index 6198 */ 6199 MLXSW_ITEM32(reg, pmpe, slot_index, 0x00, 24, 4); 6200 6201 /* reg_pmpe_module 6202 * Module number. 6203 * Access: Index 6204 */ 6205 MLXSW_ITEM32(reg, pmpe, module, 0x00, 16, 8); 6206 6207 enum mlxsw_reg_pmpe_module_status { 6208 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_ENABLED = 1, 6209 MLXSW_REG_PMPE_MODULE_STATUS_UNPLUGGED, 6210 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_ERROR, 6211 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_DISABLED, 6212 }; 6213 6214 /* reg_pmpe_module_status 6215 * Module status. 6216 * Access: RO 6217 */ 6218 MLXSW_ITEM32(reg, pmpe, module_status, 0x00, 0, 4); 6219 6220 /* reg_pmpe_error_type 6221 * Module error details. 6222 * Access: RO 6223 */ 6224 MLXSW_ITEM32(reg, pmpe, error_type, 0x04, 8, 4); 6225 6226 /* PDDR - Port Diagnostics Database Register 6227 * ----------------------------------------- 6228 * The PDDR enables to read the Phy debug database 6229 */ 6230 #define MLXSW_REG_PDDR_ID 0x5031 6231 #define MLXSW_REG_PDDR_LEN 0x100 6232 6233 MLXSW_REG_DEFINE(pddr, MLXSW_REG_PDDR_ID, MLXSW_REG_PDDR_LEN); 6234 6235 /* reg_pddr_local_port 6236 * Local port number. 6237 * Access: Index 6238 */ 6239 MLXSW_ITEM32_LP(reg, pddr, 0x00, 16, 0x00, 12); 6240 6241 enum mlxsw_reg_pddr_page_select { 6242 MLXSW_REG_PDDR_PAGE_SELECT_TROUBLESHOOTING_INFO = 1, 6243 }; 6244 6245 /* reg_pddr_page_select 6246 * Page select index. 6247 * Access: Index 6248 */ 6249 MLXSW_ITEM32(reg, pddr, page_select, 0x04, 0, 8); 6250 6251 enum mlxsw_reg_pddr_trblsh_group_opcode { 6252 /* Monitor opcodes */ 6253 MLXSW_REG_PDDR_TRBLSH_GROUP_OPCODE_MONITOR, 6254 }; 6255 6256 /* reg_pddr_group_opcode 6257 * Group selector. 6258 * Access: Index 6259 */ 6260 MLXSW_ITEM32(reg, pddr, trblsh_group_opcode, 0x08, 0, 16); 6261 6262 /* reg_pddr_status_opcode 6263 * Group selector. 6264 * Access: RO 6265 */ 6266 MLXSW_ITEM32(reg, pddr, trblsh_status_opcode, 0x0C, 0, 16); 6267 6268 static inline void mlxsw_reg_pddr_pack(char *payload, u16 local_port, 6269 u8 page_select) 6270 { 6271 MLXSW_REG_ZERO(pddr, payload); 6272 mlxsw_reg_pddr_local_port_set(payload, local_port); 6273 mlxsw_reg_pddr_page_select_set(payload, page_select); 6274 } 6275 6276 /* PMMP - Port Module Memory Map Properties Register 6277 * ------------------------------------------------- 6278 * The PMMP register allows to override the module memory map advertisement. 6279 * The register can only be set when the module is disabled by PMAOS register. 6280 */ 6281 #define MLXSW_REG_PMMP_ID 0x5044 6282 #define MLXSW_REG_PMMP_LEN 0x2C 6283 6284 MLXSW_REG_DEFINE(pmmp, MLXSW_REG_PMMP_ID, MLXSW_REG_PMMP_LEN); 6285 6286 /* reg_pmmp_module 6287 * Module number. 6288 * Access: Index 6289 */ 6290 MLXSW_ITEM32(reg, pmmp, module, 0x00, 16, 8); 6291 6292 /* reg_pmmp_slot_index 6293 * Slot index. 6294 * Access: Index 6295 */ 6296 MLXSW_ITEM32(reg, pmmp, slot_index, 0x00, 24, 4); 6297 6298 /* reg_pmmp_sticky 6299 * When set, will keep eeprom_override values after plug-out event. 6300 * Access: OP 6301 */ 6302 MLXSW_ITEM32(reg, pmmp, sticky, 0x00, 0, 1); 6303 6304 /* reg_pmmp_eeprom_override_mask 6305 * Write mask bit (negative polarity). 6306 * 0 - Allow write 6307 * 1 - Ignore write 6308 * On write, indicates which of the bits from eeprom_override field are 6309 * updated. 6310 * Access: WO 6311 */ 6312 MLXSW_ITEM32(reg, pmmp, eeprom_override_mask, 0x04, 16, 16); 6313 6314 enum { 6315 /* Set module to low power mode */ 6316 MLXSW_REG_PMMP_EEPROM_OVERRIDE_LOW_POWER_MASK = BIT(8), 6317 }; 6318 6319 /* reg_pmmp_eeprom_override 6320 * Override / ignore EEPROM advertisement properties bitmask 6321 * Access: RW 6322 */ 6323 MLXSW_ITEM32(reg, pmmp, eeprom_override, 0x04, 0, 16); 6324 6325 static inline void mlxsw_reg_pmmp_pack(char *payload, u8 slot_index, u8 module) 6326 { 6327 MLXSW_REG_ZERO(pmmp, payload); 6328 mlxsw_reg_pmmp_slot_index_set(payload, slot_index); 6329 mlxsw_reg_pmmp_module_set(payload, module); 6330 } 6331 6332 /* PLLP - Port Local port to Label Port mapping Register 6333 * ----------------------------------------------------- 6334 * The PLLP register returns the mapping from Local Port into Label Port. 6335 */ 6336 #define MLXSW_REG_PLLP_ID 0x504A 6337 #define MLXSW_REG_PLLP_LEN 0x10 6338 6339 MLXSW_REG_DEFINE(pllp, MLXSW_REG_PLLP_ID, MLXSW_REG_PLLP_LEN); 6340 6341 /* reg_pllp_local_port 6342 * Local port number. 6343 * Access: Index 6344 */ 6345 MLXSW_ITEM32_LP(reg, pllp, 0x00, 16, 0x00, 12); 6346 6347 /* reg_pllp_label_port 6348 * Front panel label of the port. 6349 * Access: RO 6350 */ 6351 MLXSW_ITEM32(reg, pllp, label_port, 0x00, 0, 8); 6352 6353 /* reg_pllp_split_num 6354 * Label split mapping for local_port. 6355 * Access: RO 6356 */ 6357 MLXSW_ITEM32(reg, pllp, split_num, 0x04, 0, 4); 6358 6359 /* reg_pllp_slot_index 6360 * Slot index (0: Main board). 6361 * Access: RO 6362 */ 6363 MLXSW_ITEM32(reg, pllp, slot_index, 0x08, 0, 4); 6364 6365 static inline void mlxsw_reg_pllp_pack(char *payload, u16 local_port) 6366 { 6367 MLXSW_REG_ZERO(pllp, payload); 6368 mlxsw_reg_pllp_local_port_set(payload, local_port); 6369 } 6370 6371 static inline void mlxsw_reg_pllp_unpack(char *payload, u8 *label_port, 6372 u8 *split_num, u8 *slot_index) 6373 { 6374 *label_port = mlxsw_reg_pllp_label_port_get(payload); 6375 *split_num = mlxsw_reg_pllp_split_num_get(payload); 6376 *slot_index = mlxsw_reg_pllp_slot_index_get(payload); 6377 } 6378 6379 /* PMTM - Port Module Type Mapping Register 6380 * ---------------------------------------- 6381 * The PMTM register allows query or configuration of module types. 6382 * The register can only be set when the module is disabled by PMAOS register 6383 */ 6384 #define MLXSW_REG_PMTM_ID 0x5067 6385 #define MLXSW_REG_PMTM_LEN 0x10 6386 6387 MLXSW_REG_DEFINE(pmtm, MLXSW_REG_PMTM_ID, MLXSW_REG_PMTM_LEN); 6388 6389 /* reg_pmtm_slot_index 6390 * Slot index. 6391 * Access: Index 6392 */ 6393 MLXSW_ITEM32(reg, pmtm, slot_index, 0x00, 24, 4); 6394 6395 /* reg_pmtm_module 6396 * Module number. 6397 * Access: Index 6398 */ 6399 MLXSW_ITEM32(reg, pmtm, module, 0x00, 16, 8); 6400 6401 enum mlxsw_reg_pmtm_module_type { 6402 MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_4_LANES = 0, 6403 MLXSW_REG_PMTM_MODULE_TYPE_QSFP = 1, 6404 MLXSW_REG_PMTM_MODULE_TYPE_SFP = 2, 6405 MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_SINGLE_LANE = 4, 6406 MLXSW_REG_PMTM_MODULE_TYPE_BACKPLANE_2_LANES = 8, 6407 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP4X = 10, 6408 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP2X = 11, 6409 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP1X = 12, 6410 MLXSW_REG_PMTM_MODULE_TYPE_QSFP_DD = 14, 6411 MLXSW_REG_PMTM_MODULE_TYPE_OSFP = 15, 6412 MLXSW_REG_PMTM_MODULE_TYPE_SFP_DD = 16, 6413 MLXSW_REG_PMTM_MODULE_TYPE_DSFP = 17, 6414 MLXSW_REG_PMTM_MODULE_TYPE_CHIP2CHIP8X = 18, 6415 MLXSW_REG_PMTM_MODULE_TYPE_TWISTED_PAIR = 19, 6416 }; 6417 6418 /* reg_pmtm_module_type 6419 * Module type. 6420 * Access: RW 6421 */ 6422 MLXSW_ITEM32(reg, pmtm, module_type, 0x04, 0, 5); 6423 6424 static inline void mlxsw_reg_pmtm_pack(char *payload, u8 slot_index, u8 module) 6425 { 6426 MLXSW_REG_ZERO(pmtm, payload); 6427 mlxsw_reg_pmtm_slot_index_set(payload, slot_index); 6428 mlxsw_reg_pmtm_module_set(payload, module); 6429 } 6430 6431 /* HTGT - Host Trap Group Table 6432 * ---------------------------- 6433 * Configures the properties for forwarding to CPU. 6434 */ 6435 #define MLXSW_REG_HTGT_ID 0x7002 6436 #define MLXSW_REG_HTGT_LEN 0x20 6437 6438 MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN); 6439 6440 /* reg_htgt_swid 6441 * Switch partition ID. 6442 * Access: Index 6443 */ 6444 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8); 6445 6446 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */ 6447 6448 /* reg_htgt_type 6449 * CPU path type. 6450 * Access: RW 6451 */ 6452 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4); 6453 6454 enum mlxsw_reg_htgt_trap_group { 6455 MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 6456 MLXSW_REG_HTGT_TRAP_GROUP_CORE_EVENT, 6457 MLXSW_REG_HTGT_TRAP_GROUP_SP_STP, 6458 MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP, 6459 MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP, 6460 MLXSW_REG_HTGT_TRAP_GROUP_SP_MC_SNOOPING, 6461 MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP, 6462 MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF, 6463 MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM, 6464 MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST, 6465 MLXSW_REG_HTGT_TRAP_GROUP_SP_NEIGH_DISCOVERY, 6466 MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP, 6467 MLXSW_REG_HTGT_TRAP_GROUP_SP_EXTERNAL_ROUTE, 6468 MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME, 6469 MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP, 6470 MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT, 6471 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6, 6472 MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR, 6473 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0, 6474 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1, 6475 MLXSW_REG_HTGT_TRAP_GROUP_SP_VRRP, 6476 MLXSW_REG_HTGT_TRAP_GROUP_SP_PKT_SAMPLE, 6477 MLXSW_REG_HTGT_TRAP_GROUP_SP_FLOW_LOGGING, 6478 MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS, 6479 MLXSW_REG_HTGT_TRAP_GROUP_SP_BFD, 6480 MLXSW_REG_HTGT_TRAP_GROUP_SP_DUMMY, 6481 MLXSW_REG_HTGT_TRAP_GROUP_SP_L2_DISCARDS, 6482 MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_DISCARDS, 6483 MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_EXCEPTIONS, 6484 MLXSW_REG_HTGT_TRAP_GROUP_SP_TUNNEL_DISCARDS, 6485 MLXSW_REG_HTGT_TRAP_GROUP_SP_ACL_DISCARDS, 6486 MLXSW_REG_HTGT_TRAP_GROUP_SP_BUFFER_DISCARDS, 6487 MLXSW_REG_HTGT_TRAP_GROUP_SP_EAPOL, 6488 6489 __MLXSW_REG_HTGT_TRAP_GROUP_MAX, 6490 MLXSW_REG_HTGT_TRAP_GROUP_MAX = __MLXSW_REG_HTGT_TRAP_GROUP_MAX - 1 6491 }; 6492 6493 /* reg_htgt_trap_group 6494 * Trap group number. User defined number specifying which trap groups 6495 * should be forwarded to the CPU. The mapping between trap IDs and trap 6496 * groups is configured using HPKT register. 6497 * Access: Index 6498 */ 6499 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8); 6500 6501 enum { 6502 MLXSW_REG_HTGT_POLICER_DISABLE, 6503 MLXSW_REG_HTGT_POLICER_ENABLE, 6504 }; 6505 6506 /* reg_htgt_pide 6507 * Enable policer ID specified using 'pid' field. 6508 * Access: RW 6509 */ 6510 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1); 6511 6512 #define MLXSW_REG_HTGT_INVALID_POLICER 0xff 6513 6514 /* reg_htgt_pid 6515 * Policer ID for the trap group. 6516 * Access: RW 6517 */ 6518 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8); 6519 6520 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0 6521 6522 /* reg_htgt_mirror_action 6523 * Mirror action to use. 6524 * 0 - Trap to CPU. 6525 * 1 - Trap to CPU and mirror to a mirroring agent. 6526 * 2 - Mirror to a mirroring agent and do not trap to CPU. 6527 * Access: RW 6528 * 6529 * Note: Mirroring to a mirroring agent is only supported in Spectrum. 6530 */ 6531 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2); 6532 6533 /* reg_htgt_mirroring_agent 6534 * Mirroring agent. 6535 * Access: RW 6536 */ 6537 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3); 6538 6539 #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0 6540 6541 /* reg_htgt_priority 6542 * Trap group priority. 6543 * In case a packet matches multiple classification rules, the packet will 6544 * only be trapped once, based on the trap ID associated with the group (via 6545 * register HPKT) with the highest priority. 6546 * Supported values are 0-7, with 7 represnting the highest priority. 6547 * Access: RW 6548 * 6549 * Note: In SwitchX-2 this field is ignored and the priority value is replaced 6550 * by the 'trap_group' field. 6551 */ 6552 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4); 6553 6554 #define MLXSW_REG_HTGT_DEFAULT_TC 7 6555 6556 /* reg_htgt_local_path_cpu_tclass 6557 * CPU ingress traffic class for the trap group. 6558 * Access: RW 6559 */ 6560 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6); 6561 6562 enum mlxsw_reg_htgt_local_path_rdq { 6563 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13, 6564 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14, 6565 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15, 6566 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15, 6567 }; 6568 /* reg_htgt_local_path_rdq 6569 * Receive descriptor queue (RDQ) to use for the trap group. 6570 * Access: RW 6571 */ 6572 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6); 6573 6574 static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id, 6575 u8 priority, u8 tc) 6576 { 6577 MLXSW_REG_ZERO(htgt, payload); 6578 6579 if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) { 6580 mlxsw_reg_htgt_pide_set(payload, 6581 MLXSW_REG_HTGT_POLICER_DISABLE); 6582 } else { 6583 mlxsw_reg_htgt_pide_set(payload, 6584 MLXSW_REG_HTGT_POLICER_ENABLE); 6585 mlxsw_reg_htgt_pid_set(payload, policer_id); 6586 } 6587 6588 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL); 6589 mlxsw_reg_htgt_trap_group_set(payload, group); 6590 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU); 6591 mlxsw_reg_htgt_mirroring_agent_set(payload, 0); 6592 mlxsw_reg_htgt_priority_set(payload, priority); 6593 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc); 6594 mlxsw_reg_htgt_local_path_rdq_set(payload, group); 6595 } 6596 6597 /* HPKT - Host Packet Trap 6598 * ----------------------- 6599 * Configures trap IDs inside trap groups. 6600 */ 6601 #define MLXSW_REG_HPKT_ID 0x7003 6602 #define MLXSW_REG_HPKT_LEN 0x10 6603 6604 MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN); 6605 6606 enum { 6607 MLXSW_REG_HPKT_ACK_NOT_REQUIRED, 6608 MLXSW_REG_HPKT_ACK_REQUIRED, 6609 }; 6610 6611 /* reg_hpkt_ack 6612 * Require acknowledgements from the host for events. 6613 * If set, then the device will wait for the event it sent to be acknowledged 6614 * by the host. This option is only relevant for event trap IDs. 6615 * Access: RW 6616 * 6617 * Note: Currently not supported by firmware. 6618 */ 6619 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1); 6620 6621 enum mlxsw_reg_hpkt_action { 6622 MLXSW_REG_HPKT_ACTION_FORWARD, 6623 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU, 6624 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU, 6625 MLXSW_REG_HPKT_ACTION_DISCARD, 6626 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD, 6627 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD, 6628 MLXSW_REG_HPKT_ACTION_TRAP_EXCEPTION_TO_CPU, 6629 MLXSW_REG_HPKT_ACTION_SET_FW_DEFAULT = 15, 6630 }; 6631 6632 /* reg_hpkt_action 6633 * Action to perform on packet when trapped. 6634 * 0 - No action. Forward to CPU based on switching rules. 6635 * 1 - Trap to CPU (CPU receives sole copy). 6636 * 2 - Mirror to CPU (CPU receives a replica of the packet). 6637 * 3 - Discard. 6638 * 4 - Soft discard (allow other traps to act on the packet). 6639 * 5 - Trap and soft discard (allow other traps to overwrite this trap). 6640 * 6 - Trap to CPU (CPU receives sole copy) and count it as error. 6641 * 15 - Restore the firmware's default action. 6642 * Access: RW 6643 * 6644 * Note: Must be set to 0 (forward) for event trap IDs, as they are already 6645 * addressed to the CPU. 6646 */ 6647 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3); 6648 6649 /* reg_hpkt_trap_group 6650 * Trap group to associate the trap with. 6651 * Access: RW 6652 */ 6653 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6); 6654 6655 /* reg_hpkt_trap_id 6656 * Trap ID. 6657 * Access: Index 6658 * 6659 * Note: A trap ID can only be associated with a single trap group. The device 6660 * will associate the trap ID with the last trap group configured. 6661 */ 6662 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 10); 6663 6664 enum { 6665 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT, 6666 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER, 6667 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER, 6668 }; 6669 6670 /* reg_hpkt_ctrl 6671 * Configure dedicated buffer resources for control packets. 6672 * Ignored by SwitchX-2. 6673 * 0 - Keep factory defaults. 6674 * 1 - Do not use control buffer for this trap ID. 6675 * 2 - Use control buffer for this trap ID. 6676 * Access: RW 6677 */ 6678 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2); 6679 6680 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id, 6681 enum mlxsw_reg_htgt_trap_group trap_group, 6682 bool is_ctrl) 6683 { 6684 MLXSW_REG_ZERO(hpkt, payload); 6685 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED); 6686 mlxsw_reg_hpkt_action_set(payload, action); 6687 mlxsw_reg_hpkt_trap_group_set(payload, trap_group); 6688 mlxsw_reg_hpkt_trap_id_set(payload, trap_id); 6689 mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ? 6690 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER : 6691 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER); 6692 } 6693 6694 /* RGCR - Router General Configuration Register 6695 * -------------------------------------------- 6696 * The register is used for setting up the router configuration. 6697 */ 6698 #define MLXSW_REG_RGCR_ID 0x8001 6699 #define MLXSW_REG_RGCR_LEN 0x28 6700 6701 MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN); 6702 6703 /* reg_rgcr_ipv4_en 6704 * IPv4 router enable. 6705 * Access: RW 6706 */ 6707 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1); 6708 6709 /* reg_rgcr_ipv6_en 6710 * IPv6 router enable. 6711 * Access: RW 6712 */ 6713 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1); 6714 6715 /* reg_rgcr_max_router_interfaces 6716 * Defines the maximum number of active router interfaces for all virtual 6717 * routers. 6718 * Access: RW 6719 */ 6720 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16); 6721 6722 /* reg_rgcr_usp 6723 * Update switch priority and packet color. 6724 * 0 - Preserve the value of Switch Priority and packet color. 6725 * 1 - Recalculate the value of Switch Priority and packet color. 6726 * Access: RW 6727 * 6728 * Note: Not supported by SwitchX and SwitchX-2. 6729 */ 6730 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1); 6731 6732 /* reg_rgcr_pcp_rw 6733 * Indicates how to handle the pcp_rewrite_en value: 6734 * 0 - Preserve the value of pcp_rewrite_en. 6735 * 2 - Disable PCP rewrite. 6736 * 3 - Enable PCP rewrite. 6737 * Access: RW 6738 * 6739 * Note: Not supported by SwitchX and SwitchX-2. 6740 */ 6741 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2); 6742 6743 /* reg_rgcr_activity_dis 6744 * Activity disable: 6745 * 0 - Activity will be set when an entry is hit (default). 6746 * 1 - Activity will not be set when an entry is hit. 6747 * 6748 * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry 6749 * (RALUE). 6750 * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host 6751 * Entry (RAUHT). 6752 * Bits 2:7 are reserved. 6753 * Access: RW 6754 * 6755 * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB. 6756 */ 6757 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8); 6758 6759 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en, 6760 bool ipv6_en) 6761 { 6762 MLXSW_REG_ZERO(rgcr, payload); 6763 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en); 6764 mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en); 6765 } 6766 6767 /* RITR - Router Interface Table Register 6768 * -------------------------------------- 6769 * The register is used to configure the router interface table. 6770 */ 6771 #define MLXSW_REG_RITR_ID 0x8002 6772 #define MLXSW_REG_RITR_LEN 0x40 6773 6774 MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN); 6775 6776 /* reg_ritr_enable 6777 * Enables routing on the router interface. 6778 * Access: RW 6779 */ 6780 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1); 6781 6782 /* reg_ritr_ipv4 6783 * IPv4 routing enable. Enables routing of IPv4 traffic on the router 6784 * interface. 6785 * Access: RW 6786 */ 6787 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1); 6788 6789 /* reg_ritr_ipv6 6790 * IPv6 routing enable. Enables routing of IPv6 traffic on the router 6791 * interface. 6792 * Access: RW 6793 */ 6794 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1); 6795 6796 /* reg_ritr_ipv4_mc 6797 * IPv4 multicast routing enable. 6798 * Access: RW 6799 */ 6800 MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1); 6801 6802 /* reg_ritr_ipv6_mc 6803 * IPv6 multicast routing enable. 6804 * Access: RW 6805 */ 6806 MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1); 6807 6808 enum mlxsw_reg_ritr_if_type { 6809 /* VLAN interface. */ 6810 MLXSW_REG_RITR_VLAN_IF, 6811 /* FID interface. */ 6812 MLXSW_REG_RITR_FID_IF, 6813 /* Sub-port interface. */ 6814 MLXSW_REG_RITR_SP_IF, 6815 /* Loopback Interface. */ 6816 MLXSW_REG_RITR_LOOPBACK_IF, 6817 }; 6818 6819 /* reg_ritr_type 6820 * Router interface type as per enum mlxsw_reg_ritr_if_type. 6821 * Access: RW 6822 */ 6823 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3); 6824 6825 enum { 6826 MLXSW_REG_RITR_RIF_CREATE, 6827 MLXSW_REG_RITR_RIF_DEL, 6828 }; 6829 6830 /* reg_ritr_op 6831 * Opcode: 6832 * 0 - Create or edit RIF. 6833 * 1 - Delete RIF. 6834 * Reserved for SwitchX-2. For Spectrum, editing of interface properties 6835 * is not supported. An interface must be deleted and re-created in order 6836 * to update properties. 6837 * Access: WO 6838 */ 6839 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2); 6840 6841 /* reg_ritr_rif 6842 * Router interface index. A pointer to the Router Interface Table. 6843 * Access: Index 6844 */ 6845 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16); 6846 6847 /* reg_ritr_ipv4_fe 6848 * IPv4 Forwarding Enable. 6849 * Enables routing of IPv4 traffic on the router interface. When disabled, 6850 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 6851 * Not supported in SwitchX-2. 6852 * Access: RW 6853 */ 6854 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1); 6855 6856 /* reg_ritr_ipv6_fe 6857 * IPv6 Forwarding Enable. 6858 * Enables routing of IPv6 traffic on the router interface. When disabled, 6859 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 6860 * Not supported in SwitchX-2. 6861 * Access: RW 6862 */ 6863 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1); 6864 6865 /* reg_ritr_ipv4_mc_fe 6866 * IPv4 Multicast Forwarding Enable. 6867 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 6868 * will be enabled. 6869 * Access: RW 6870 */ 6871 MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1); 6872 6873 /* reg_ritr_ipv6_mc_fe 6874 * IPv6 Multicast Forwarding Enable. 6875 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 6876 * will be enabled. 6877 * Access: RW 6878 */ 6879 MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1); 6880 6881 /* reg_ritr_lb_en 6882 * Loop-back filter enable for unicast packets. 6883 * If the flag is set then loop-back filter for unicast packets is 6884 * implemented on the RIF. Multicast packets are always subject to 6885 * loop-back filtering. 6886 * Access: RW 6887 */ 6888 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1); 6889 6890 /* reg_ritr_virtual_router 6891 * Virtual router ID associated with the router interface. 6892 * Access: RW 6893 */ 6894 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16); 6895 6896 /* reg_ritr_mtu 6897 * Router interface MTU. 6898 * Access: RW 6899 */ 6900 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16); 6901 6902 /* reg_ritr_if_swid 6903 * Switch partition ID. 6904 * Access: RW 6905 */ 6906 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8); 6907 6908 /* reg_ritr_if_mac_profile_id 6909 * MAC msb profile ID. 6910 * Access: RW 6911 */ 6912 MLXSW_ITEM32(reg, ritr, if_mac_profile_id, 0x10, 16, 4); 6913 6914 /* reg_ritr_if_mac 6915 * Router interface MAC address. 6916 * In Spectrum, all MAC addresses must have the same 38 MSBits. 6917 * Access: RW 6918 */ 6919 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6); 6920 6921 /* reg_ritr_if_vrrp_id_ipv6 6922 * VRRP ID for IPv6 6923 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 6924 * Access: RW 6925 */ 6926 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8); 6927 6928 /* reg_ritr_if_vrrp_id_ipv4 6929 * VRRP ID for IPv4 6930 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 6931 * Access: RW 6932 */ 6933 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8); 6934 6935 /* VLAN Interface */ 6936 6937 /* reg_ritr_vlan_if_vlan_id 6938 * VLAN ID. 6939 * Access: RW 6940 */ 6941 MLXSW_ITEM32(reg, ritr, vlan_if_vlan_id, 0x08, 0, 12); 6942 6943 /* reg_ritr_vlan_if_efid 6944 * Egress FID. 6945 * Used to connect the RIF to a bridge. 6946 * Access: RW 6947 * 6948 * Note: Reserved when legacy bridge model is used and on Spectrum-1. 6949 */ 6950 MLXSW_ITEM32(reg, ritr, vlan_if_efid, 0x0C, 0, 16); 6951 6952 /* FID Interface */ 6953 6954 /* reg_ritr_fid_if_fid 6955 * Filtering ID. Used to connect a bridge to the router. 6956 * When legacy bridge model is used, only FIDs from the vFID range are 6957 * supported. When unified bridge model is used, this is the egress FID for 6958 * router to bridge. 6959 * Access: RW 6960 */ 6961 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16); 6962 6963 /* Sub-port Interface */ 6964 6965 /* reg_ritr_sp_if_lag 6966 * LAG indication. When this bit is set the system_port field holds the 6967 * LAG identifier. 6968 * Access: RW 6969 */ 6970 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1); 6971 6972 /* reg_ritr_sp_system_port 6973 * Port unique indentifier. When lag bit is set, this field holds the 6974 * lag_id in bits 0:9. 6975 * Access: RW 6976 */ 6977 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16); 6978 6979 /* reg_ritr_sp_if_efid 6980 * Egress filtering ID. 6981 * Used to connect the eRIF to a bridge if eRIF-ACL has modified the DMAC or 6982 * the VID. 6983 * Access: RW 6984 * 6985 * Note: Reserved when legacy bridge model is used. 6986 */ 6987 MLXSW_ITEM32(reg, ritr, sp_if_efid, 0x0C, 0, 16); 6988 6989 /* reg_ritr_sp_if_vid 6990 * VLAN ID. 6991 * Access: RW 6992 */ 6993 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12); 6994 6995 /* Loopback Interface */ 6996 6997 enum mlxsw_reg_ritr_loopback_protocol { 6998 /* IPinIP IPv4 underlay Unicast */ 6999 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4, 7000 /* IPinIP IPv6 underlay Unicast */ 7001 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6, 7002 /* IPinIP generic - used for Spectrum-2 underlay RIF */ 7003 MLXSW_REG_RITR_LOOPBACK_GENERIC, 7004 }; 7005 7006 /* reg_ritr_loopback_protocol 7007 * Access: RW 7008 */ 7009 MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4); 7010 7011 enum mlxsw_reg_ritr_loopback_ipip_type { 7012 /* Tunnel is IPinIP. */ 7013 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP, 7014 /* Tunnel is GRE, no key. */ 7015 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP, 7016 /* Tunnel is GRE, with a key. */ 7017 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP, 7018 }; 7019 7020 /* reg_ritr_loopback_ipip_type 7021 * Encapsulation type. 7022 * Access: RW 7023 */ 7024 MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4); 7025 7026 enum mlxsw_reg_ritr_loopback_ipip_options { 7027 /* The key is defined by gre_key. */ 7028 MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET, 7029 }; 7030 7031 /* reg_ritr_loopback_ipip_options 7032 * Access: RW 7033 */ 7034 MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4); 7035 7036 /* reg_ritr_loopback_ipip_uvr 7037 * Underlay Virtual Router ID. 7038 * Range is 0..cap_max_virtual_routers-1. 7039 * Reserved for Spectrum-2. 7040 * Access: RW 7041 */ 7042 MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16); 7043 7044 /* reg_ritr_loopback_ipip_underlay_rif 7045 * Underlay ingress router interface. 7046 * Reserved for Spectrum. 7047 * Access: RW 7048 */ 7049 MLXSW_ITEM32(reg, ritr, loopback_ipip_underlay_rif, 0x14, 0, 16); 7050 7051 /* reg_ritr_loopback_ipip_usip* 7052 * Encapsulation Underlay source IP. 7053 * Access: RW 7054 */ 7055 MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16); 7056 MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32); 7057 7058 /* reg_ritr_loopback_ipip_gre_key 7059 * GRE Key. 7060 * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP. 7061 * Access: RW 7062 */ 7063 MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32); 7064 7065 /* Shared between ingress/egress */ 7066 enum mlxsw_reg_ritr_counter_set_type { 7067 /* No Count. */ 7068 MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0, 7069 /* Basic. Used for router interfaces, counting the following: 7070 * - Error and Discard counters. 7071 * - Unicast, Multicast and Broadcast counters. Sharing the 7072 * same set of counters for the different type of traffic 7073 * (IPv4, IPv6 and mpls). 7074 */ 7075 MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9, 7076 }; 7077 7078 /* reg_ritr_ingress_counter_index 7079 * Counter Index for flow counter. 7080 * Access: RW 7081 */ 7082 MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24); 7083 7084 /* reg_ritr_ingress_counter_set_type 7085 * Igress Counter Set Type for router interface counter. 7086 * Access: RW 7087 */ 7088 MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8); 7089 7090 /* reg_ritr_egress_counter_index 7091 * Counter Index for flow counter. 7092 * Access: RW 7093 */ 7094 MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24); 7095 7096 /* reg_ritr_egress_counter_set_type 7097 * Egress Counter Set Type for router interface counter. 7098 * Access: RW 7099 */ 7100 MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8); 7101 7102 static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index, 7103 bool enable, bool egress) 7104 { 7105 enum mlxsw_reg_ritr_counter_set_type set_type; 7106 7107 if (enable) 7108 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC; 7109 else 7110 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT; 7111 7112 if (egress) { 7113 mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type); 7114 mlxsw_reg_ritr_egress_counter_index_set(payload, index); 7115 } else { 7116 mlxsw_reg_ritr_ingress_counter_set_type_set(payload, set_type); 7117 mlxsw_reg_ritr_ingress_counter_index_set(payload, index); 7118 } 7119 } 7120 7121 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif) 7122 { 7123 MLXSW_REG_ZERO(ritr, payload); 7124 mlxsw_reg_ritr_rif_set(payload, rif); 7125 } 7126 7127 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag, 7128 u16 system_port, u16 efid, u16 vid) 7129 { 7130 mlxsw_reg_ritr_sp_if_lag_set(payload, lag); 7131 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port); 7132 mlxsw_reg_ritr_sp_if_efid_set(payload, efid); 7133 mlxsw_reg_ritr_sp_if_vid_set(payload, vid); 7134 } 7135 7136 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable, 7137 enum mlxsw_reg_ritr_if_type type, 7138 u16 rif, u16 vr_id, u16 mtu) 7139 { 7140 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL; 7141 7142 MLXSW_REG_ZERO(ritr, payload); 7143 mlxsw_reg_ritr_enable_set(payload, enable); 7144 mlxsw_reg_ritr_ipv4_set(payload, 1); 7145 mlxsw_reg_ritr_ipv6_set(payload, 1); 7146 mlxsw_reg_ritr_ipv4_mc_set(payload, 1); 7147 mlxsw_reg_ritr_ipv6_mc_set(payload, 1); 7148 mlxsw_reg_ritr_type_set(payload, type); 7149 mlxsw_reg_ritr_op_set(payload, op); 7150 mlxsw_reg_ritr_rif_set(payload, rif); 7151 mlxsw_reg_ritr_ipv4_fe_set(payload, 1); 7152 mlxsw_reg_ritr_ipv6_fe_set(payload, 1); 7153 mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1); 7154 mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1); 7155 mlxsw_reg_ritr_lb_en_set(payload, 1); 7156 mlxsw_reg_ritr_virtual_router_set(payload, vr_id); 7157 mlxsw_reg_ritr_mtu_set(payload, mtu); 7158 } 7159 7160 static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac) 7161 { 7162 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac); 7163 } 7164 7165 static inline void 7166 mlxsw_reg_ritr_vlan_if_pack(char *payload, bool enable, u16 rif, u16 vr_id, 7167 u16 mtu, const char *mac, u8 mac_profile_id, 7168 u16 vlan_id, u16 efid) 7169 { 7170 enum mlxsw_reg_ritr_if_type type = MLXSW_REG_RITR_VLAN_IF; 7171 7172 mlxsw_reg_ritr_pack(payload, enable, type, rif, vr_id, mtu); 7173 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac); 7174 mlxsw_reg_ritr_if_mac_profile_id_set(payload, mac_profile_id); 7175 mlxsw_reg_ritr_vlan_if_vlan_id_set(payload, vlan_id); 7176 mlxsw_reg_ritr_vlan_if_efid_set(payload, efid); 7177 } 7178 7179 static inline void 7180 mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload, 7181 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 7182 enum mlxsw_reg_ritr_loopback_ipip_options options, 7183 u16 uvr_id, u16 underlay_rif, u32 gre_key) 7184 { 7185 mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type); 7186 mlxsw_reg_ritr_loopback_ipip_options_set(payload, options); 7187 mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id); 7188 mlxsw_reg_ritr_loopback_ipip_underlay_rif_set(payload, underlay_rif); 7189 mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key); 7190 } 7191 7192 static inline void 7193 mlxsw_reg_ritr_loopback_ipip4_pack(char *payload, 7194 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 7195 enum mlxsw_reg_ritr_loopback_ipip_options options, 7196 u16 uvr_id, u16 underlay_rif, u32 usip, u32 gre_key) 7197 { 7198 mlxsw_reg_ritr_loopback_protocol_set(payload, 7199 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4); 7200 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options, 7201 uvr_id, underlay_rif, gre_key); 7202 mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip); 7203 } 7204 7205 static inline void 7206 mlxsw_reg_ritr_loopback_ipip6_pack(char *payload, 7207 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 7208 enum mlxsw_reg_ritr_loopback_ipip_options options, 7209 u16 uvr_id, u16 underlay_rif, 7210 const struct in6_addr *usip, u32 gre_key) 7211 { 7212 enum mlxsw_reg_ritr_loopback_protocol protocol = 7213 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6; 7214 7215 mlxsw_reg_ritr_loopback_protocol_set(payload, protocol); 7216 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options, 7217 uvr_id, underlay_rif, gre_key); 7218 mlxsw_reg_ritr_loopback_ipip_usip6_memcpy_to(payload, 7219 (const char *)usip); 7220 } 7221 7222 /* RTAR - Router TCAM Allocation Register 7223 * -------------------------------------- 7224 * This register is used for allocation of regions in the TCAM table. 7225 */ 7226 #define MLXSW_REG_RTAR_ID 0x8004 7227 #define MLXSW_REG_RTAR_LEN 0x20 7228 7229 MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN); 7230 7231 enum mlxsw_reg_rtar_op { 7232 MLXSW_REG_RTAR_OP_ALLOCATE, 7233 MLXSW_REG_RTAR_OP_RESIZE, 7234 MLXSW_REG_RTAR_OP_DEALLOCATE, 7235 }; 7236 7237 /* reg_rtar_op 7238 * Access: WO 7239 */ 7240 MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4); 7241 7242 enum mlxsw_reg_rtar_key_type { 7243 MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1, 7244 MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3 7245 }; 7246 7247 /* reg_rtar_key_type 7248 * TCAM key type for the region. 7249 * Access: WO 7250 */ 7251 MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8); 7252 7253 /* reg_rtar_region_size 7254 * TCAM region size. When allocating/resizing this is the requested 7255 * size, the response is the actual size. 7256 * Note: Actual size may be larger than requested. 7257 * Reserved for op = Deallocate 7258 * Access: WO 7259 */ 7260 MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16); 7261 7262 static inline void mlxsw_reg_rtar_pack(char *payload, 7263 enum mlxsw_reg_rtar_op op, 7264 enum mlxsw_reg_rtar_key_type key_type, 7265 u16 region_size) 7266 { 7267 MLXSW_REG_ZERO(rtar, payload); 7268 mlxsw_reg_rtar_op_set(payload, op); 7269 mlxsw_reg_rtar_key_type_set(payload, key_type); 7270 mlxsw_reg_rtar_region_size_set(payload, region_size); 7271 } 7272 7273 /* RATR - Router Adjacency Table Register 7274 * -------------------------------------- 7275 * The RATR register is used to configure the Router Adjacency (next-hop) 7276 * Table. 7277 */ 7278 #define MLXSW_REG_RATR_ID 0x8008 7279 #define MLXSW_REG_RATR_LEN 0x2C 7280 7281 MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN); 7282 7283 enum mlxsw_reg_ratr_op { 7284 /* Read */ 7285 MLXSW_REG_RATR_OP_QUERY_READ = 0, 7286 /* Read and clear activity */ 7287 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2, 7288 /* Write Adjacency entry */ 7289 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1, 7290 /* Write Adjacency entry only if the activity is cleared. 7291 * The write may not succeed if the activity is set. There is not 7292 * direct feedback if the write has succeeded or not, however 7293 * the get will reveal the actual entry (SW can compare the get 7294 * response to the set command). 7295 */ 7296 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3, 7297 }; 7298 7299 /* reg_ratr_op 7300 * Note that Write operation may also be used for updating 7301 * counter_set_type and counter_index. In this case all other 7302 * fields must not be updated. 7303 * Access: OP 7304 */ 7305 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4); 7306 7307 /* reg_ratr_v 7308 * Valid bit. Indicates if the adjacency entry is valid. 7309 * Note: the device may need some time before reusing an invalidated 7310 * entry. During this time the entry can not be reused. It is 7311 * recommended to use another entry before reusing an invalidated 7312 * entry (e.g. software can put it at the end of the list for 7313 * reusing). Trying to access an invalidated entry not yet cleared 7314 * by the device results with failure indicating "Try Again" status. 7315 * When valid is '0' then egress_router_interface,trap_action, 7316 * adjacency_parameters and counters are reserved 7317 * Access: RW 7318 */ 7319 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1); 7320 7321 /* reg_ratr_a 7322 * Activity. Set for new entries. Set if a packet lookup has hit on 7323 * the specific entry. To clear the a bit, use "clear activity". 7324 * Access: RO 7325 */ 7326 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1); 7327 7328 enum mlxsw_reg_ratr_type { 7329 /* Ethernet */ 7330 MLXSW_REG_RATR_TYPE_ETHERNET, 7331 /* IPoIB Unicast without GRH. 7332 * Reserved for Spectrum. 7333 */ 7334 MLXSW_REG_RATR_TYPE_IPOIB_UC, 7335 /* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast 7336 * adjacency). 7337 * Reserved for Spectrum. 7338 */ 7339 MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH, 7340 /* IPoIB Multicast. 7341 * Reserved for Spectrum. 7342 */ 7343 MLXSW_REG_RATR_TYPE_IPOIB_MC, 7344 /* MPLS. 7345 * Reserved for SwitchX/-2. 7346 */ 7347 MLXSW_REG_RATR_TYPE_MPLS, 7348 /* IPinIP Encap. 7349 * Reserved for SwitchX/-2. 7350 */ 7351 MLXSW_REG_RATR_TYPE_IPIP, 7352 }; 7353 7354 /* reg_ratr_type 7355 * Adjacency entry type. 7356 * Access: RW 7357 */ 7358 MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4); 7359 7360 /* reg_ratr_adjacency_index_low 7361 * Bits 15:0 of index into the adjacency table. 7362 * For SwitchX and SwitchX-2, the adjacency table is linear and 7363 * used for adjacency entries only. 7364 * For Spectrum, the index is to the KVD linear. 7365 * Access: Index 7366 */ 7367 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16); 7368 7369 /* reg_ratr_egress_router_interface 7370 * Range is 0 .. cap_max_router_interfaces - 1 7371 * Access: RW 7372 */ 7373 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16); 7374 7375 enum mlxsw_reg_ratr_trap_action { 7376 MLXSW_REG_RATR_TRAP_ACTION_NOP, 7377 MLXSW_REG_RATR_TRAP_ACTION_TRAP, 7378 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU, 7379 MLXSW_REG_RATR_TRAP_ACTION_MIRROR, 7380 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS, 7381 }; 7382 7383 /* reg_ratr_trap_action 7384 * see mlxsw_reg_ratr_trap_action 7385 * Access: RW 7386 */ 7387 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4); 7388 7389 /* reg_ratr_adjacency_index_high 7390 * Bits 23:16 of the adjacency_index. 7391 * Access: Index 7392 */ 7393 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8); 7394 7395 enum mlxsw_reg_ratr_trap_id { 7396 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0, 7397 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1, 7398 }; 7399 7400 /* reg_ratr_trap_id 7401 * Trap ID to be reported to CPU. 7402 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 7403 * For trap_action of NOP, MIRROR and DISCARD_ERROR 7404 * Access: RW 7405 */ 7406 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8); 7407 7408 /* reg_ratr_eth_destination_mac 7409 * MAC address of the destination next-hop. 7410 * Access: RW 7411 */ 7412 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6); 7413 7414 enum mlxsw_reg_ratr_ipip_type { 7415 /* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */ 7416 MLXSW_REG_RATR_IPIP_TYPE_IPV4, 7417 /* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */ 7418 MLXSW_REG_RATR_IPIP_TYPE_IPV6, 7419 }; 7420 7421 /* reg_ratr_ipip_type 7422 * Underlay destination ip type. 7423 * Note: the type field must match the protocol of the router interface. 7424 * Access: RW 7425 */ 7426 MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4); 7427 7428 /* reg_ratr_ipip_ipv4_udip 7429 * Underlay ipv4 dip. 7430 * Reserved when ipip_type is IPv6. 7431 * Access: RW 7432 */ 7433 MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32); 7434 7435 /* reg_ratr_ipip_ipv6_ptr 7436 * Pointer to IPv6 underlay destination ip address. 7437 * For Spectrum: Pointer to KVD linear space. 7438 * Access: RW 7439 */ 7440 MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24); 7441 7442 enum mlxsw_reg_flow_counter_set_type { 7443 /* No count */ 7444 MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00, 7445 /* Count packets and bytes */ 7446 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03, 7447 /* Count only packets */ 7448 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05, 7449 }; 7450 7451 /* reg_ratr_counter_set_type 7452 * Counter set type for flow counters 7453 * Access: RW 7454 */ 7455 MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8); 7456 7457 /* reg_ratr_counter_index 7458 * Counter index for flow counters 7459 * Access: RW 7460 */ 7461 MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24); 7462 7463 static inline void 7464 mlxsw_reg_ratr_pack(char *payload, 7465 enum mlxsw_reg_ratr_op op, bool valid, 7466 enum mlxsw_reg_ratr_type type, 7467 u32 adjacency_index, u16 egress_rif) 7468 { 7469 MLXSW_REG_ZERO(ratr, payload); 7470 mlxsw_reg_ratr_op_set(payload, op); 7471 mlxsw_reg_ratr_v_set(payload, valid); 7472 mlxsw_reg_ratr_type_set(payload, type); 7473 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index); 7474 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16); 7475 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif); 7476 } 7477 7478 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload, 7479 const char *dest_mac) 7480 { 7481 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac); 7482 } 7483 7484 static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip) 7485 { 7486 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4); 7487 mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip); 7488 } 7489 7490 static inline void mlxsw_reg_ratr_ipip6_entry_pack(char *payload, u32 ipv6_ptr) 7491 { 7492 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV6); 7493 mlxsw_reg_ratr_ipip_ipv6_ptr_set(payload, ipv6_ptr); 7494 } 7495 7496 static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index, 7497 bool counter_enable) 7498 { 7499 enum mlxsw_reg_flow_counter_set_type set_type; 7500 7501 if (counter_enable) 7502 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES; 7503 else 7504 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT; 7505 7506 mlxsw_reg_ratr_counter_index_set(payload, counter_index); 7507 mlxsw_reg_ratr_counter_set_type_set(payload, set_type); 7508 } 7509 7510 /* RDPM - Router DSCP to Priority Mapping 7511 * -------------------------------------- 7512 * Controls the mapping from DSCP field to switch priority on routed packets 7513 */ 7514 #define MLXSW_REG_RDPM_ID 0x8009 7515 #define MLXSW_REG_RDPM_BASE_LEN 0x00 7516 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01 7517 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64 7518 #define MLXSW_REG_RDPM_LEN 0x40 7519 #define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \ 7520 MLXSW_REG_RDPM_LEN - \ 7521 MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN) 7522 7523 MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN); 7524 7525 /* reg_dscp_entry_e 7526 * Enable update of the specific entry 7527 * Access: Index 7528 */ 7529 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1, 7530 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 7531 7532 /* reg_dscp_entry_prio 7533 * Switch Priority 7534 * Access: RW 7535 */ 7536 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4, 7537 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 7538 7539 static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index, 7540 u8 prio) 7541 { 7542 mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1); 7543 mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio); 7544 } 7545 7546 /* RICNT - Router Interface Counter Register 7547 * ----------------------------------------- 7548 * The RICNT register retrieves per port performance counters 7549 */ 7550 #define MLXSW_REG_RICNT_ID 0x800B 7551 #define MLXSW_REG_RICNT_LEN 0x100 7552 7553 MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN); 7554 7555 /* reg_ricnt_counter_index 7556 * Counter index 7557 * Access: RW 7558 */ 7559 MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24); 7560 7561 enum mlxsw_reg_ricnt_counter_set_type { 7562 /* No Count. */ 7563 MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00, 7564 /* Basic. Used for router interfaces, counting the following: 7565 * - Error and Discard counters. 7566 * - Unicast, Multicast and Broadcast counters. Sharing the 7567 * same set of counters for the different type of traffic 7568 * (IPv4, IPv6 and mpls). 7569 */ 7570 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09, 7571 }; 7572 7573 /* reg_ricnt_counter_set_type 7574 * Counter Set Type for router interface counter 7575 * Access: RW 7576 */ 7577 MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8); 7578 7579 enum mlxsw_reg_ricnt_opcode { 7580 /* Nop. Supported only for read access*/ 7581 MLXSW_REG_RICNT_OPCODE_NOP = 0x00, 7582 /* Clear. Setting the clr bit will reset the counter value for 7583 * all counters of the specified Router Interface. 7584 */ 7585 MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08, 7586 }; 7587 7588 /* reg_ricnt_opcode 7589 * Opcode 7590 * Access: RW 7591 */ 7592 MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4); 7593 7594 /* reg_ricnt_good_unicast_packets 7595 * good unicast packets. 7596 * Access: RW 7597 */ 7598 MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64); 7599 7600 /* reg_ricnt_good_multicast_packets 7601 * good multicast packets. 7602 * Access: RW 7603 */ 7604 MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64); 7605 7606 /* reg_ricnt_good_broadcast_packets 7607 * good broadcast packets 7608 * Access: RW 7609 */ 7610 MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64); 7611 7612 /* reg_ricnt_good_unicast_bytes 7613 * A count of L3 data and padding octets not including L2 headers 7614 * for good unicast frames. 7615 * Access: RW 7616 */ 7617 MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64); 7618 7619 /* reg_ricnt_good_multicast_bytes 7620 * A count of L3 data and padding octets not including L2 headers 7621 * for good multicast frames. 7622 * Access: RW 7623 */ 7624 MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64); 7625 7626 /* reg_ritr_good_broadcast_bytes 7627 * A count of L3 data and padding octets not including L2 headers 7628 * for good broadcast frames. 7629 * Access: RW 7630 */ 7631 MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64); 7632 7633 /* reg_ricnt_error_packets 7634 * A count of errored frames that do not pass the router checks. 7635 * Access: RW 7636 */ 7637 MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64); 7638 7639 /* reg_ricnt_discrad_packets 7640 * A count of non-errored frames that do not pass the router checks. 7641 * Access: RW 7642 */ 7643 MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64); 7644 7645 /* reg_ricnt_error_bytes 7646 * A count of L3 data and padding octets not including L2 headers 7647 * for errored frames. 7648 * Access: RW 7649 */ 7650 MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64); 7651 7652 /* reg_ricnt_discard_bytes 7653 * A count of L3 data and padding octets not including L2 headers 7654 * for non-errored frames that do not pass the router checks. 7655 * Access: RW 7656 */ 7657 MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64); 7658 7659 static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index, 7660 enum mlxsw_reg_ricnt_opcode op) 7661 { 7662 MLXSW_REG_ZERO(ricnt, payload); 7663 mlxsw_reg_ricnt_op_set(payload, op); 7664 mlxsw_reg_ricnt_counter_index_set(payload, index); 7665 mlxsw_reg_ricnt_counter_set_type_set(payload, 7666 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC); 7667 } 7668 7669 /* RRCR - Router Rules Copy Register Layout 7670 * ---------------------------------------- 7671 * This register is used for moving and copying route entry rules. 7672 */ 7673 #define MLXSW_REG_RRCR_ID 0x800F 7674 #define MLXSW_REG_RRCR_LEN 0x24 7675 7676 MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN); 7677 7678 enum mlxsw_reg_rrcr_op { 7679 /* Move rules */ 7680 MLXSW_REG_RRCR_OP_MOVE, 7681 /* Copy rules */ 7682 MLXSW_REG_RRCR_OP_COPY, 7683 }; 7684 7685 /* reg_rrcr_op 7686 * Access: WO 7687 */ 7688 MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4); 7689 7690 /* reg_rrcr_offset 7691 * Offset within the region from which to copy/move. 7692 * Access: Index 7693 */ 7694 MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16); 7695 7696 /* reg_rrcr_size 7697 * The number of rules to copy/move. 7698 * Access: WO 7699 */ 7700 MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16); 7701 7702 /* reg_rrcr_table_id 7703 * Identifier of the table on which to perform the operation. Encoding is the 7704 * same as in RTAR.key_type 7705 * Access: Index 7706 */ 7707 MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4); 7708 7709 /* reg_rrcr_dest_offset 7710 * Offset within the region to which to copy/move 7711 * Access: Index 7712 */ 7713 MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16); 7714 7715 static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op, 7716 u16 offset, u16 size, 7717 enum mlxsw_reg_rtar_key_type table_id, 7718 u16 dest_offset) 7719 { 7720 MLXSW_REG_ZERO(rrcr, payload); 7721 mlxsw_reg_rrcr_op_set(payload, op); 7722 mlxsw_reg_rrcr_offset_set(payload, offset); 7723 mlxsw_reg_rrcr_size_set(payload, size); 7724 mlxsw_reg_rrcr_table_id_set(payload, table_id); 7725 mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset); 7726 } 7727 7728 /* RALTA - Router Algorithmic LPM Tree Allocation Register 7729 * ------------------------------------------------------- 7730 * RALTA is used to allocate the LPM trees of the SHSPM method. 7731 */ 7732 #define MLXSW_REG_RALTA_ID 0x8010 7733 #define MLXSW_REG_RALTA_LEN 0x04 7734 7735 MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN); 7736 7737 /* reg_ralta_op 7738 * opcode (valid for Write, must be 0 on Read) 7739 * 0 - allocate a tree 7740 * 1 - deallocate a tree 7741 * Access: OP 7742 */ 7743 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2); 7744 7745 enum mlxsw_reg_ralxx_protocol { 7746 MLXSW_REG_RALXX_PROTOCOL_IPV4, 7747 MLXSW_REG_RALXX_PROTOCOL_IPV6, 7748 }; 7749 7750 /* reg_ralta_protocol 7751 * Protocol. 7752 * Deallocation opcode: Reserved. 7753 * Access: RW 7754 */ 7755 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4); 7756 7757 /* reg_ralta_tree_id 7758 * An identifier (numbered from 1..cap_shspm_max_trees-1) representing 7759 * the tree identifier (managed by software). 7760 * Note that tree_id 0 is allocated for a default-route tree. 7761 * Access: Index 7762 */ 7763 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8); 7764 7765 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc, 7766 enum mlxsw_reg_ralxx_protocol protocol, 7767 u8 tree_id) 7768 { 7769 MLXSW_REG_ZERO(ralta, payload); 7770 mlxsw_reg_ralta_op_set(payload, !alloc); 7771 mlxsw_reg_ralta_protocol_set(payload, protocol); 7772 mlxsw_reg_ralta_tree_id_set(payload, tree_id); 7773 } 7774 7775 /* RALST - Router Algorithmic LPM Structure Tree Register 7776 * ------------------------------------------------------ 7777 * RALST is used to set and query the structure of an LPM tree. 7778 * The structure of the tree must be sorted as a sorted binary tree, while 7779 * each node is a bin that is tagged as the length of the prefixes the lookup 7780 * will refer to. Therefore, bin X refers to a set of entries with prefixes 7781 * of X bits to match with the destination address. The bin 0 indicates 7782 * the default action, when there is no match of any prefix. 7783 */ 7784 #define MLXSW_REG_RALST_ID 0x8011 7785 #define MLXSW_REG_RALST_LEN 0x104 7786 7787 MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN); 7788 7789 /* reg_ralst_root_bin 7790 * The bin number of the root bin. 7791 * 0<root_bin=<(length of IP address) 7792 * For a default-route tree configure 0xff 7793 * Access: RW 7794 */ 7795 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8); 7796 7797 /* reg_ralst_tree_id 7798 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 7799 * Access: Index 7800 */ 7801 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8); 7802 7803 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff 7804 #define MLXSW_REG_RALST_BIN_OFFSET 0x04 7805 #define MLXSW_REG_RALST_BIN_COUNT 128 7806 7807 /* reg_ralst_left_child_bin 7808 * Holding the children of the bin according to the stored tree's structure. 7809 * For trees composed of less than 4 blocks, the bins in excess are reserved. 7810 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 7811 * Access: RW 7812 */ 7813 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false); 7814 7815 /* reg_ralst_right_child_bin 7816 * Holding the children of the bin according to the stored tree's structure. 7817 * For trees composed of less than 4 blocks, the bins in excess are reserved. 7818 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 7819 * Access: RW 7820 */ 7821 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00, 7822 false); 7823 7824 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id) 7825 { 7826 MLXSW_REG_ZERO(ralst, payload); 7827 7828 /* Initialize all bins to have no left or right child */ 7829 memset(payload + MLXSW_REG_RALST_BIN_OFFSET, 7830 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2); 7831 7832 mlxsw_reg_ralst_root_bin_set(payload, root_bin); 7833 mlxsw_reg_ralst_tree_id_set(payload, tree_id); 7834 } 7835 7836 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number, 7837 u8 left_child_bin, 7838 u8 right_child_bin) 7839 { 7840 int bin_index = bin_number - 1; 7841 7842 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin); 7843 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index, 7844 right_child_bin); 7845 } 7846 7847 /* RALTB - Router Algorithmic LPM Tree Binding Register 7848 * ---------------------------------------------------- 7849 * RALTB is used to bind virtual router and protocol to an allocated LPM tree. 7850 */ 7851 #define MLXSW_REG_RALTB_ID 0x8012 7852 #define MLXSW_REG_RALTB_LEN 0x04 7853 7854 MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN); 7855 7856 /* reg_raltb_virtual_router 7857 * Virtual Router ID 7858 * Range is 0..cap_max_virtual_routers-1 7859 * Access: Index 7860 */ 7861 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16); 7862 7863 /* reg_raltb_protocol 7864 * Protocol. 7865 * Access: Index 7866 */ 7867 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4); 7868 7869 /* reg_raltb_tree_id 7870 * Tree to be used for the {virtual_router, protocol} 7871 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 7872 * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0. 7873 * Access: RW 7874 */ 7875 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8); 7876 7877 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router, 7878 enum mlxsw_reg_ralxx_protocol protocol, 7879 u8 tree_id) 7880 { 7881 MLXSW_REG_ZERO(raltb, payload); 7882 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router); 7883 mlxsw_reg_raltb_protocol_set(payload, protocol); 7884 mlxsw_reg_raltb_tree_id_set(payload, tree_id); 7885 } 7886 7887 /* RALUE - Router Algorithmic LPM Unicast Entry Register 7888 * ----------------------------------------------------- 7889 * RALUE is used to configure and query LPM entries that serve 7890 * the Unicast protocols. 7891 */ 7892 #define MLXSW_REG_RALUE_ID 0x8013 7893 #define MLXSW_REG_RALUE_LEN 0x38 7894 7895 MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN); 7896 7897 /* reg_ralue_protocol 7898 * Protocol. 7899 * Access: Index 7900 */ 7901 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4); 7902 7903 enum mlxsw_reg_ralue_op { 7904 /* Read operation. If entry doesn't exist, the operation fails. */ 7905 MLXSW_REG_RALUE_OP_QUERY_READ = 0, 7906 /* Clear on read operation. Used to read entry and 7907 * clear Activity bit. 7908 */ 7909 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1, 7910 /* Write operation. Used to write a new entry to the table. All RW 7911 * fields are written for new entry. Activity bit is set 7912 * for new entries. 7913 */ 7914 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0, 7915 /* Update operation. Used to update an existing route entry and 7916 * only update the RW fields that are detailed in the field 7917 * op_u_mask. If entry doesn't exist, the operation fails. 7918 */ 7919 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1, 7920 /* Clear activity. The Activity bit (the field a) is cleared 7921 * for the entry. 7922 */ 7923 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2, 7924 /* Delete operation. Used to delete an existing entry. If entry 7925 * doesn't exist, the operation fails. 7926 */ 7927 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3, 7928 }; 7929 7930 /* reg_ralue_op 7931 * Operation. 7932 * Access: OP 7933 */ 7934 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3); 7935 7936 /* reg_ralue_a 7937 * Activity. Set for new entries. Set if a packet lookup has hit on the 7938 * specific entry, only if the entry is a route. To clear the a bit, use 7939 * "clear activity" op. 7940 * Enabled by activity_dis in RGCR 7941 * Access: RO 7942 */ 7943 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1); 7944 7945 /* reg_ralue_virtual_router 7946 * Virtual Router ID 7947 * Range is 0..cap_max_virtual_routers-1 7948 * Access: Index 7949 */ 7950 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16); 7951 7952 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0) 7953 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1) 7954 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2) 7955 7956 /* reg_ralue_op_u_mask 7957 * opcode update mask. 7958 * On read operation, this field is reserved. 7959 * This field is valid for update opcode, otherwise - reserved. 7960 * This field is a bitmask of the fields that should be updated. 7961 * Access: WO 7962 */ 7963 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3); 7964 7965 /* reg_ralue_prefix_len 7966 * Number of bits in the prefix of the LPM route. 7967 * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes 7968 * two entries in the physical HW table. 7969 * Access: Index 7970 */ 7971 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8); 7972 7973 /* reg_ralue_dip* 7974 * The prefix of the route or of the marker that the object of the LPM 7975 * is compared with. The most significant bits of the dip are the prefix. 7976 * The least significant bits must be '0' if the prefix_len is smaller 7977 * than 128 for IPv6 or smaller than 32 for IPv4. 7978 * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved. 7979 * Access: Index 7980 */ 7981 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32); 7982 MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16); 7983 7984 enum mlxsw_reg_ralue_entry_type { 7985 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1, 7986 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2, 7987 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3, 7988 }; 7989 7990 /* reg_ralue_entry_type 7991 * Entry type. 7992 * Note - for Marker entries, the action_type and action fields are reserved. 7993 * Access: RW 7994 */ 7995 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2); 7996 7997 /* reg_ralue_bmp_len 7998 * The best match prefix length in the case that there is no match for 7999 * longer prefixes. 8000 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len 8001 * Note for any update operation with entry_type modification this 8002 * field must be set. 8003 * Access: RW 8004 */ 8005 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8); 8006 8007 enum mlxsw_reg_ralue_action_type { 8008 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE, 8009 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL, 8010 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME, 8011 }; 8012 8013 /* reg_ralue_action_type 8014 * Action Type 8015 * Indicates how the IP address is connected. 8016 * It can be connected to a local subnet through local_erif or can be 8017 * on a remote subnet connected through a next-hop router, 8018 * or transmitted to the CPU. 8019 * Reserved when entry_type = MARKER_ENTRY 8020 * Access: RW 8021 */ 8022 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2); 8023 8024 enum mlxsw_reg_ralue_trap_action { 8025 MLXSW_REG_RALUE_TRAP_ACTION_NOP, 8026 MLXSW_REG_RALUE_TRAP_ACTION_TRAP, 8027 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU, 8028 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR, 8029 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR, 8030 }; 8031 8032 /* reg_ralue_trap_action 8033 * Trap action. 8034 * For IP2ME action, only NOP and MIRROR are possible. 8035 * Access: RW 8036 */ 8037 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4); 8038 8039 /* reg_ralue_trap_id 8040 * Trap ID to be reported to CPU. 8041 * Trap ID is RTR_INGRESS0 or RTR_INGRESS1. 8042 * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved. 8043 * Access: RW 8044 */ 8045 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9); 8046 8047 /* reg_ralue_adjacency_index 8048 * Points to the first entry of the group-based ECMP. 8049 * Only relevant in case of REMOTE action. 8050 * Access: RW 8051 */ 8052 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24); 8053 8054 /* reg_ralue_ecmp_size 8055 * Amount of sequential entries starting 8056 * from the adjacency_index (the number of ECMPs). 8057 * The valid range is 1-64, 512, 1024, 2048 and 4096. 8058 * Reserved when trap_action is TRAP or DISCARD_ERROR. 8059 * Only relevant in case of REMOTE action. 8060 * Access: RW 8061 */ 8062 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13); 8063 8064 /* reg_ralue_local_erif 8065 * Egress Router Interface. 8066 * Only relevant in case of LOCAL action. 8067 * Access: RW 8068 */ 8069 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16); 8070 8071 /* reg_ralue_ip2me_v 8072 * Valid bit for the tunnel_ptr field. 8073 * If valid = 0 then trap to CPU as IP2ME trap ID. 8074 * If valid = 1 and the packet format allows NVE or IPinIP tunnel 8075 * decapsulation then tunnel decapsulation is done. 8076 * If valid = 1 and packet format does not allow NVE or IPinIP tunnel 8077 * decapsulation then trap as IP2ME trap ID. 8078 * Only relevant in case of IP2ME action. 8079 * Access: RW 8080 */ 8081 MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1); 8082 8083 /* reg_ralue_ip2me_tunnel_ptr 8084 * Tunnel Pointer for NVE or IPinIP tunnel decapsulation. 8085 * For Spectrum, pointer to KVD Linear. 8086 * Only relevant in case of IP2ME action. 8087 * Access: RW 8088 */ 8089 MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24); 8090 8091 static inline void mlxsw_reg_ralue_pack(char *payload, 8092 enum mlxsw_reg_ralxx_protocol protocol, 8093 enum mlxsw_reg_ralue_op op, 8094 u16 virtual_router, u8 prefix_len) 8095 { 8096 MLXSW_REG_ZERO(ralue, payload); 8097 mlxsw_reg_ralue_protocol_set(payload, protocol); 8098 mlxsw_reg_ralue_op_set(payload, op); 8099 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router); 8100 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len); 8101 mlxsw_reg_ralue_entry_type_set(payload, 8102 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY); 8103 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len); 8104 } 8105 8106 static inline void mlxsw_reg_ralue_pack4(char *payload, 8107 enum mlxsw_reg_ralxx_protocol protocol, 8108 enum mlxsw_reg_ralue_op op, 8109 u16 virtual_router, u8 prefix_len, 8110 u32 dip) 8111 { 8112 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 8113 mlxsw_reg_ralue_dip4_set(payload, dip); 8114 } 8115 8116 static inline void mlxsw_reg_ralue_pack6(char *payload, 8117 enum mlxsw_reg_ralxx_protocol protocol, 8118 enum mlxsw_reg_ralue_op op, 8119 u16 virtual_router, u8 prefix_len, 8120 const void *dip) 8121 { 8122 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 8123 mlxsw_reg_ralue_dip6_memcpy_to(payload, dip); 8124 } 8125 8126 static inline void 8127 mlxsw_reg_ralue_act_remote_pack(char *payload, 8128 enum mlxsw_reg_ralue_trap_action trap_action, 8129 u16 trap_id, u32 adjacency_index, u16 ecmp_size) 8130 { 8131 mlxsw_reg_ralue_action_type_set(payload, 8132 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE); 8133 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 8134 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 8135 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index); 8136 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size); 8137 } 8138 8139 static inline void 8140 mlxsw_reg_ralue_act_local_pack(char *payload, 8141 enum mlxsw_reg_ralue_trap_action trap_action, 8142 u16 trap_id, u16 local_erif) 8143 { 8144 mlxsw_reg_ralue_action_type_set(payload, 8145 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL); 8146 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 8147 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 8148 mlxsw_reg_ralue_local_erif_set(payload, local_erif); 8149 } 8150 8151 static inline void 8152 mlxsw_reg_ralue_act_ip2me_pack(char *payload) 8153 { 8154 mlxsw_reg_ralue_action_type_set(payload, 8155 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 8156 } 8157 8158 static inline void 8159 mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr) 8160 { 8161 mlxsw_reg_ralue_action_type_set(payload, 8162 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 8163 mlxsw_reg_ralue_ip2me_v_set(payload, 1); 8164 mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr); 8165 } 8166 8167 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register 8168 * ---------------------------------------------------------- 8169 * The RAUHT register is used to configure and query the Unicast Host table in 8170 * devices that implement the Algorithmic LPM. 8171 */ 8172 #define MLXSW_REG_RAUHT_ID 0x8014 8173 #define MLXSW_REG_RAUHT_LEN 0x74 8174 8175 MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN); 8176 8177 enum mlxsw_reg_rauht_type { 8178 MLXSW_REG_RAUHT_TYPE_IPV4, 8179 MLXSW_REG_RAUHT_TYPE_IPV6, 8180 }; 8181 8182 /* reg_rauht_type 8183 * Access: Index 8184 */ 8185 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2); 8186 8187 enum mlxsw_reg_rauht_op { 8188 MLXSW_REG_RAUHT_OP_QUERY_READ = 0, 8189 /* Read operation */ 8190 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1, 8191 /* Clear on read operation. Used to read entry and clear 8192 * activity bit. 8193 */ 8194 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0, 8195 /* Add. Used to write a new entry to the table. All R/W fields are 8196 * relevant for new entry. Activity bit is set for new entries. 8197 */ 8198 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1, 8199 /* Update action. Used to update an existing route entry and 8200 * only update the following fields: 8201 * trap_action, trap_id, mac, counter_set_type, counter_index 8202 */ 8203 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2, 8204 /* Clear activity. A bit is cleared for the entry. */ 8205 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3, 8206 /* Delete entry */ 8207 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4, 8208 /* Delete all host entries on a RIF. In this command, dip 8209 * field is reserved. 8210 */ 8211 }; 8212 8213 /* reg_rauht_op 8214 * Access: OP 8215 */ 8216 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3); 8217 8218 /* reg_rauht_a 8219 * Activity. Set for new entries. Set if a packet lookup has hit on 8220 * the specific entry. 8221 * To clear the a bit, use "clear activity" op. 8222 * Enabled by activity_dis in RGCR 8223 * Access: RO 8224 */ 8225 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1); 8226 8227 /* reg_rauht_rif 8228 * Router Interface 8229 * Access: Index 8230 */ 8231 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16); 8232 8233 /* reg_rauht_dip* 8234 * Destination address. 8235 * Access: Index 8236 */ 8237 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32); 8238 MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16); 8239 8240 enum mlxsw_reg_rauht_trap_action { 8241 MLXSW_REG_RAUHT_TRAP_ACTION_NOP, 8242 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP, 8243 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU, 8244 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR, 8245 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS, 8246 }; 8247 8248 /* reg_rauht_trap_action 8249 * Access: RW 8250 */ 8251 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4); 8252 8253 enum mlxsw_reg_rauht_trap_id { 8254 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0, 8255 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1, 8256 }; 8257 8258 /* reg_rauht_trap_id 8259 * Trap ID to be reported to CPU. 8260 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 8261 * For trap_action of NOP, MIRROR and DISCARD_ERROR, 8262 * trap_id is reserved. 8263 * Access: RW 8264 */ 8265 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9); 8266 8267 /* reg_rauht_counter_set_type 8268 * Counter set type for flow counters 8269 * Access: RW 8270 */ 8271 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8); 8272 8273 /* reg_rauht_counter_index 8274 * Counter index for flow counters 8275 * Access: RW 8276 */ 8277 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24); 8278 8279 /* reg_rauht_mac 8280 * MAC address. 8281 * Access: RW 8282 */ 8283 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6); 8284 8285 static inline void mlxsw_reg_rauht_pack(char *payload, 8286 enum mlxsw_reg_rauht_op op, u16 rif, 8287 const char *mac) 8288 { 8289 MLXSW_REG_ZERO(rauht, payload); 8290 mlxsw_reg_rauht_op_set(payload, op); 8291 mlxsw_reg_rauht_rif_set(payload, rif); 8292 mlxsw_reg_rauht_mac_memcpy_to(payload, mac); 8293 } 8294 8295 static inline void mlxsw_reg_rauht_pack4(char *payload, 8296 enum mlxsw_reg_rauht_op op, u16 rif, 8297 const char *mac, u32 dip) 8298 { 8299 mlxsw_reg_rauht_pack(payload, op, rif, mac); 8300 mlxsw_reg_rauht_dip4_set(payload, dip); 8301 } 8302 8303 static inline void mlxsw_reg_rauht_pack6(char *payload, 8304 enum mlxsw_reg_rauht_op op, u16 rif, 8305 const char *mac, const char *dip) 8306 { 8307 mlxsw_reg_rauht_pack(payload, op, rif, mac); 8308 mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6); 8309 mlxsw_reg_rauht_dip6_memcpy_to(payload, dip); 8310 } 8311 8312 static inline void mlxsw_reg_rauht_pack_counter(char *payload, 8313 u64 counter_index) 8314 { 8315 mlxsw_reg_rauht_counter_index_set(payload, counter_index); 8316 mlxsw_reg_rauht_counter_set_type_set(payload, 8317 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 8318 } 8319 8320 /* RALEU - Router Algorithmic LPM ECMP Update Register 8321 * --------------------------------------------------- 8322 * The register enables updating the ECMP section in the action for multiple 8323 * LPM Unicast entries in a single operation. The update is executed to 8324 * all entries of a {virtual router, protocol} tuple using the same ECMP group. 8325 */ 8326 #define MLXSW_REG_RALEU_ID 0x8015 8327 #define MLXSW_REG_RALEU_LEN 0x28 8328 8329 MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN); 8330 8331 /* reg_raleu_protocol 8332 * Protocol. 8333 * Access: Index 8334 */ 8335 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4); 8336 8337 /* reg_raleu_virtual_router 8338 * Virtual Router ID 8339 * Range is 0..cap_max_virtual_routers-1 8340 * Access: Index 8341 */ 8342 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16); 8343 8344 /* reg_raleu_adjacency_index 8345 * Adjacency Index used for matching on the existing entries. 8346 * Access: Index 8347 */ 8348 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24); 8349 8350 /* reg_raleu_ecmp_size 8351 * ECMP Size used for matching on the existing entries. 8352 * Access: Index 8353 */ 8354 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13); 8355 8356 /* reg_raleu_new_adjacency_index 8357 * New Adjacency Index. 8358 * Access: WO 8359 */ 8360 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24); 8361 8362 /* reg_raleu_new_ecmp_size 8363 * New ECMP Size. 8364 * Access: WO 8365 */ 8366 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13); 8367 8368 static inline void mlxsw_reg_raleu_pack(char *payload, 8369 enum mlxsw_reg_ralxx_protocol protocol, 8370 u16 virtual_router, 8371 u32 adjacency_index, u16 ecmp_size, 8372 u32 new_adjacency_index, 8373 u16 new_ecmp_size) 8374 { 8375 MLXSW_REG_ZERO(raleu, payload); 8376 mlxsw_reg_raleu_protocol_set(payload, protocol); 8377 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router); 8378 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index); 8379 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size); 8380 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index); 8381 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size); 8382 } 8383 8384 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register 8385 * ---------------------------------------------------------------- 8386 * The RAUHTD register allows dumping entries from the Router Unicast Host 8387 * Table. For a given session an entry is dumped no more than one time. The 8388 * first RAUHTD access after reset is a new session. A session ends when the 8389 * num_rec response is smaller than num_rec request or for IPv4 when the 8390 * num_entries is smaller than 4. The clear activity affect the current session 8391 * or the last session if a new session has not started. 8392 */ 8393 #define MLXSW_REG_RAUHTD_ID 0x8018 8394 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20 8395 #define MLXSW_REG_RAUHTD_REC_LEN 0x20 8396 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32 8397 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \ 8398 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN) 8399 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4 8400 8401 MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN); 8402 8403 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0) 8404 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3) 8405 8406 /* reg_rauhtd_filter_fields 8407 * if a bit is '0' then the relevant field is ignored and dump is done 8408 * regardless of the field value 8409 * Bit0 - filter by activity: entry_a 8410 * Bit3 - filter by entry rip: entry_rif 8411 * Access: Index 8412 */ 8413 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8); 8414 8415 enum mlxsw_reg_rauhtd_op { 8416 MLXSW_REG_RAUHTD_OP_DUMP, 8417 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR, 8418 }; 8419 8420 /* reg_rauhtd_op 8421 * Access: OP 8422 */ 8423 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2); 8424 8425 /* reg_rauhtd_num_rec 8426 * At request: number of records requested 8427 * At response: number of records dumped 8428 * For IPv4, each record has 4 entries at request and up to 4 entries 8429 * at response 8430 * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM 8431 * Access: Index 8432 */ 8433 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8); 8434 8435 /* reg_rauhtd_entry_a 8436 * Dump only if activity has value of entry_a 8437 * Reserved if filter_fields bit0 is '0' 8438 * Access: Index 8439 */ 8440 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1); 8441 8442 enum mlxsw_reg_rauhtd_type { 8443 MLXSW_REG_RAUHTD_TYPE_IPV4, 8444 MLXSW_REG_RAUHTD_TYPE_IPV6, 8445 }; 8446 8447 /* reg_rauhtd_type 8448 * Dump only if record type is: 8449 * 0 - IPv4 8450 * 1 - IPv6 8451 * Access: Index 8452 */ 8453 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4); 8454 8455 /* reg_rauhtd_entry_rif 8456 * Dump only if RIF has value of entry_rif 8457 * Reserved if filter_fields bit3 is '0' 8458 * Access: Index 8459 */ 8460 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16); 8461 8462 static inline void mlxsw_reg_rauhtd_pack(char *payload, 8463 enum mlxsw_reg_rauhtd_type type) 8464 { 8465 MLXSW_REG_ZERO(rauhtd, payload); 8466 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A); 8467 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR); 8468 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM); 8469 mlxsw_reg_rauhtd_entry_a_set(payload, 1); 8470 mlxsw_reg_rauhtd_type_set(payload, type); 8471 } 8472 8473 /* reg_rauhtd_ipv4_rec_num_entries 8474 * Number of valid entries in this record: 8475 * 0 - 1 valid entry 8476 * 1 - 2 valid entries 8477 * 2 - 3 valid entries 8478 * 3 - 4 valid entries 8479 * Access: RO 8480 */ 8481 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries, 8482 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2, 8483 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 8484 8485 /* reg_rauhtd_rec_type 8486 * Record type. 8487 * 0 - IPv4 8488 * 1 - IPv6 8489 * Access: RO 8490 */ 8491 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2, 8492 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 8493 8494 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8 8495 8496 /* reg_rauhtd_ipv4_ent_a 8497 * Activity. Set for new entries. Set if a packet lookup has hit on the 8498 * specific entry. 8499 * Access: RO 8500 */ 8501 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 8502 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 8503 8504 /* reg_rauhtd_ipv4_ent_rif 8505 * Router interface. 8506 * Access: RO 8507 */ 8508 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 8509 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 8510 8511 /* reg_rauhtd_ipv4_ent_dip 8512 * Destination IPv4 address. 8513 * Access: RO 8514 */ 8515 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0, 8516 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false); 8517 8518 #define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20 8519 8520 /* reg_rauhtd_ipv6_ent_a 8521 * Activity. Set for new entries. Set if a packet lookup has hit on the 8522 * specific entry. 8523 * Access: RO 8524 */ 8525 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 8526 MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 8527 8528 /* reg_rauhtd_ipv6_ent_rif 8529 * Router interface. 8530 * Access: RO 8531 */ 8532 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 8533 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 8534 8535 /* reg_rauhtd_ipv6_ent_dip 8536 * Destination IPv6 address. 8537 * Access: RO 8538 */ 8539 MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 8540 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10); 8541 8542 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload, 8543 int ent_index, u16 *p_rif, 8544 u32 *p_dip) 8545 { 8546 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index); 8547 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index); 8548 } 8549 8550 static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload, 8551 int rec_index, u16 *p_rif, 8552 char *p_dip) 8553 { 8554 *p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index); 8555 mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip); 8556 } 8557 8558 /* RTDP - Routing Tunnel Decap Properties Register 8559 * ----------------------------------------------- 8560 * The RTDP register is used for configuring the tunnel decap properties of NVE 8561 * and IPinIP. 8562 */ 8563 #define MLXSW_REG_RTDP_ID 0x8020 8564 #define MLXSW_REG_RTDP_LEN 0x44 8565 8566 MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN); 8567 8568 enum mlxsw_reg_rtdp_type { 8569 MLXSW_REG_RTDP_TYPE_NVE, 8570 MLXSW_REG_RTDP_TYPE_IPIP, 8571 }; 8572 8573 /* reg_rtdp_type 8574 * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type. 8575 * Access: RW 8576 */ 8577 MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4); 8578 8579 /* reg_rtdp_tunnel_index 8580 * Index to the Decap entry. 8581 * For Spectrum, Index to KVD Linear. 8582 * Access: Index 8583 */ 8584 MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24); 8585 8586 /* reg_rtdp_egress_router_interface 8587 * Underlay egress router interface. 8588 * Valid range is from 0 to cap_max_router_interfaces - 1 8589 * Access: RW 8590 */ 8591 MLXSW_ITEM32(reg, rtdp, egress_router_interface, 0x40, 0, 16); 8592 8593 /* IPinIP */ 8594 8595 /* reg_rtdp_ipip_irif 8596 * Ingress Router Interface for the overlay router 8597 * Access: RW 8598 */ 8599 MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16); 8600 8601 enum mlxsw_reg_rtdp_ipip_sip_check { 8602 /* No sip checks. */ 8603 MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO, 8604 /* Filter packet if underlay is not IPv4 or if underlay SIP does not 8605 * equal ipv4_usip. 8606 */ 8607 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4, 8608 /* Filter packet if underlay is not IPv6 or if underlay SIP does not 8609 * equal ipv6_usip. 8610 */ 8611 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3, 8612 }; 8613 8614 /* reg_rtdp_ipip_sip_check 8615 * SIP check to perform. If decapsulation failed due to these configurations 8616 * then trap_id is IPIP_DECAP_ERROR. 8617 * Access: RW 8618 */ 8619 MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3); 8620 8621 /* If set, allow decapsulation of IPinIP (without GRE). */ 8622 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP BIT(0) 8623 /* If set, allow decapsulation of IPinGREinIP without a key. */ 8624 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE BIT(1) 8625 /* If set, allow decapsulation of IPinGREinIP with a key. */ 8626 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY BIT(2) 8627 8628 /* reg_rtdp_ipip_type_check 8629 * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to 8630 * these configurations then trap_id is IPIP_DECAP_ERROR. 8631 * Access: RW 8632 */ 8633 MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3); 8634 8635 /* reg_rtdp_ipip_gre_key_check 8636 * Whether GRE key should be checked. When check is enabled: 8637 * - A packet received as IPinIP (without GRE) will always pass. 8638 * - A packet received as IPinGREinIP without a key will not pass the check. 8639 * - A packet received as IPinGREinIP with a key will pass the check only if the 8640 * key in the packet is equal to expected_gre_key. 8641 * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR. 8642 * Access: RW 8643 */ 8644 MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1); 8645 8646 /* reg_rtdp_ipip_ipv4_usip 8647 * Underlay IPv4 address for ipv4 source address check. 8648 * Reserved when sip_check is not '1'. 8649 * Access: RW 8650 */ 8651 MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32); 8652 8653 /* reg_rtdp_ipip_ipv6_usip_ptr 8654 * This field is valid when sip_check is "sipv6 check explicitly". This is a 8655 * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index 8656 * is to the KVD linear. 8657 * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6. 8658 * Access: RW 8659 */ 8660 MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24); 8661 8662 /* reg_rtdp_ipip_expected_gre_key 8663 * GRE key for checking. 8664 * Reserved when gre_key_check is '0'. 8665 * Access: RW 8666 */ 8667 MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32); 8668 8669 static inline void mlxsw_reg_rtdp_pack(char *payload, 8670 enum mlxsw_reg_rtdp_type type, 8671 u32 tunnel_index) 8672 { 8673 MLXSW_REG_ZERO(rtdp, payload); 8674 mlxsw_reg_rtdp_type_set(payload, type); 8675 mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index); 8676 } 8677 8678 static inline void 8679 mlxsw_reg_rtdp_ipip_pack(char *payload, u16 irif, 8680 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 8681 unsigned int type_check, bool gre_key_check, 8682 u32 expected_gre_key) 8683 { 8684 mlxsw_reg_rtdp_ipip_irif_set(payload, irif); 8685 mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check); 8686 mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check); 8687 mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check); 8688 mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key); 8689 } 8690 8691 static inline void 8692 mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif, 8693 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 8694 unsigned int type_check, bool gre_key_check, 8695 u32 ipv4_usip, u32 expected_gre_key) 8696 { 8697 mlxsw_reg_rtdp_ipip_pack(payload, irif, sip_check, type_check, 8698 gre_key_check, expected_gre_key); 8699 mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip); 8700 } 8701 8702 static inline void 8703 mlxsw_reg_rtdp_ipip6_pack(char *payload, u16 irif, 8704 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 8705 unsigned int type_check, bool gre_key_check, 8706 u32 ipv6_usip_ptr, u32 expected_gre_key) 8707 { 8708 mlxsw_reg_rtdp_ipip_pack(payload, irif, sip_check, type_check, 8709 gre_key_check, expected_gre_key); 8710 mlxsw_reg_rtdp_ipip_ipv6_usip_ptr_set(payload, ipv6_usip_ptr); 8711 } 8712 8713 /* RIPS - Router IP version Six Register 8714 * ------------------------------------- 8715 * The RIPS register is used to store IPv6 addresses for use by the NVE and 8716 * IPinIP 8717 */ 8718 #define MLXSW_REG_RIPS_ID 0x8021 8719 #define MLXSW_REG_RIPS_LEN 0x14 8720 8721 MLXSW_REG_DEFINE(rips, MLXSW_REG_RIPS_ID, MLXSW_REG_RIPS_LEN); 8722 8723 /* reg_rips_index 8724 * Index to IPv6 address. 8725 * For Spectrum, the index is to the KVD linear. 8726 * Access: Index 8727 */ 8728 MLXSW_ITEM32(reg, rips, index, 0x00, 0, 24); 8729 8730 /* reg_rips_ipv6 8731 * IPv6 address 8732 * Access: RW 8733 */ 8734 MLXSW_ITEM_BUF(reg, rips, ipv6, 0x04, 16); 8735 8736 static inline void mlxsw_reg_rips_pack(char *payload, u32 index, 8737 const struct in6_addr *ipv6) 8738 { 8739 MLXSW_REG_ZERO(rips, payload); 8740 mlxsw_reg_rips_index_set(payload, index); 8741 mlxsw_reg_rips_ipv6_memcpy_to(payload, (const char *)ipv6); 8742 } 8743 8744 /* RATRAD - Router Adjacency Table Activity Dump Register 8745 * ------------------------------------------------------ 8746 * The RATRAD register is used to dump and optionally clear activity bits of 8747 * router adjacency table entries. 8748 */ 8749 #define MLXSW_REG_RATRAD_ID 0x8022 8750 #define MLXSW_REG_RATRAD_LEN 0x210 8751 8752 MLXSW_REG_DEFINE(ratrad, MLXSW_REG_RATRAD_ID, MLXSW_REG_RATRAD_LEN); 8753 8754 enum { 8755 /* Read activity */ 8756 MLXSW_REG_RATRAD_OP_READ_ACTIVITY, 8757 /* Read and clear activity */ 8758 MLXSW_REG_RATRAD_OP_READ_CLEAR_ACTIVITY, 8759 }; 8760 8761 /* reg_ratrad_op 8762 * Access: Operation 8763 */ 8764 MLXSW_ITEM32(reg, ratrad, op, 0x00, 30, 2); 8765 8766 /* reg_ratrad_ecmp_size 8767 * ecmp_size is the amount of sequential entries from adjacency_index. Valid 8768 * ranges: 8769 * Spectrum-1: 32-64, 512, 1024, 2048, 4096 8770 * Spectrum-2/3: 32-128, 256, 512, 1024, 2048, 4096 8771 * Access: Index 8772 */ 8773 MLXSW_ITEM32(reg, ratrad, ecmp_size, 0x00, 0, 13); 8774 8775 /* reg_ratrad_adjacency_index 8776 * Index into the adjacency table. 8777 * Access: Index 8778 */ 8779 MLXSW_ITEM32(reg, ratrad, adjacency_index, 0x04, 0, 24); 8780 8781 /* reg_ratrad_activity_vector 8782 * Activity bit per adjacency index. 8783 * Bits higher than ecmp_size are reserved. 8784 * Access: RO 8785 */ 8786 MLXSW_ITEM_BIT_ARRAY(reg, ratrad, activity_vector, 0x10, 0x200, 1); 8787 8788 static inline void mlxsw_reg_ratrad_pack(char *payload, u32 adjacency_index, 8789 u16 ecmp_size) 8790 { 8791 MLXSW_REG_ZERO(ratrad, payload); 8792 mlxsw_reg_ratrad_op_set(payload, 8793 MLXSW_REG_RATRAD_OP_READ_CLEAR_ACTIVITY); 8794 mlxsw_reg_ratrad_ecmp_size_set(payload, ecmp_size); 8795 mlxsw_reg_ratrad_adjacency_index_set(payload, adjacency_index); 8796 } 8797 8798 /* RIGR-V2 - Router Interface Group Register Version 2 8799 * --------------------------------------------------- 8800 * The RIGR_V2 register is used to add, remove and query egress interface list 8801 * of a multicast forwarding entry. 8802 */ 8803 #define MLXSW_REG_RIGR2_ID 0x8023 8804 #define MLXSW_REG_RIGR2_LEN 0xB0 8805 8806 #define MLXSW_REG_RIGR2_MAX_ERIFS 32 8807 8808 MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN); 8809 8810 /* reg_rigr2_rigr_index 8811 * KVD Linear index. 8812 * Access: Index 8813 */ 8814 MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24); 8815 8816 /* reg_rigr2_vnext 8817 * Next RIGR Index is valid. 8818 * Access: RW 8819 */ 8820 MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1); 8821 8822 /* reg_rigr2_next_rigr_index 8823 * Next RIGR Index. The index is to the KVD linear. 8824 * Reserved when vnxet = '0'. 8825 * Access: RW 8826 */ 8827 MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24); 8828 8829 /* reg_rigr2_vrmid 8830 * RMID Index is valid. 8831 * Access: RW 8832 */ 8833 MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1); 8834 8835 /* reg_rigr2_rmid_index 8836 * RMID Index. 8837 * Range 0 .. max_mid - 1 8838 * Reserved when vrmid = '0'. 8839 * The index is to the Port Group Table (PGT) 8840 * Access: RW 8841 */ 8842 MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16); 8843 8844 /* reg_rigr2_erif_entry_v 8845 * Egress Router Interface is valid. 8846 * Note that low-entries must be set if high-entries are set. For 8847 * example: if erif_entry[2].v is set then erif_entry[1].v and 8848 * erif_entry[0].v must be set. 8849 * Index can be from 0 to cap_mc_erif_list_entries-1 8850 * Access: RW 8851 */ 8852 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false); 8853 8854 /* reg_rigr2_erif_entry_erif 8855 * Egress Router Interface. 8856 * Valid range is from 0 to cap_max_router_interfaces - 1 8857 * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1 8858 * Access: RW 8859 */ 8860 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false); 8861 8862 static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index, 8863 bool vnext, u32 next_rigr_index) 8864 { 8865 MLXSW_REG_ZERO(rigr2, payload); 8866 mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index); 8867 mlxsw_reg_rigr2_vnext_set(payload, vnext); 8868 mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index); 8869 mlxsw_reg_rigr2_vrmid_set(payload, 0); 8870 mlxsw_reg_rigr2_rmid_index_set(payload, 0); 8871 } 8872 8873 static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index, 8874 bool v, u16 erif) 8875 { 8876 mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v); 8877 mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif); 8878 } 8879 8880 /* RECR-V2 - Router ECMP Configuration Version 2 Register 8881 * ------------------------------------------------------ 8882 */ 8883 #define MLXSW_REG_RECR2_ID 0x8025 8884 #define MLXSW_REG_RECR2_LEN 0x38 8885 8886 MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN); 8887 8888 /* reg_recr2_pp 8889 * Per-port configuration 8890 * Access: Index 8891 */ 8892 MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1); 8893 8894 /* reg_recr2_sh 8895 * Symmetric hash 8896 * Access: RW 8897 */ 8898 MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1); 8899 8900 /* reg_recr2_seed 8901 * Seed 8902 * Access: RW 8903 */ 8904 MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32); 8905 8906 enum { 8907 /* Enable IPv4 fields if packet is not TCP and not UDP */ 8908 MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP = 3, 8909 /* Enable IPv4 fields if packet is TCP or UDP */ 8910 MLXSW_REG_RECR2_IPV4_EN_TCP_UDP = 4, 8911 /* Enable IPv6 fields if packet is not TCP and not UDP */ 8912 MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP = 5, 8913 /* Enable IPv6 fields if packet is TCP or UDP */ 8914 MLXSW_REG_RECR2_IPV6_EN_TCP_UDP = 6, 8915 /* Enable TCP/UDP header fields if packet is IPv4 */ 8916 MLXSW_REG_RECR2_TCP_UDP_EN_IPV4 = 7, 8917 /* Enable TCP/UDP header fields if packet is IPv6 */ 8918 MLXSW_REG_RECR2_TCP_UDP_EN_IPV6 = 8, 8919 8920 __MLXSW_REG_RECR2_HEADER_CNT, 8921 }; 8922 8923 /* reg_recr2_outer_header_enables 8924 * Bit mask where each bit enables a specific layer to be included in 8925 * the hash calculation. 8926 * Access: RW 8927 */ 8928 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1); 8929 8930 enum { 8931 /* IPv4 Source IP */ 8932 MLXSW_REG_RECR2_IPV4_SIP0 = 9, 8933 MLXSW_REG_RECR2_IPV4_SIP3 = 12, 8934 /* IPv4 Destination IP */ 8935 MLXSW_REG_RECR2_IPV4_DIP0 = 13, 8936 MLXSW_REG_RECR2_IPV4_DIP3 = 16, 8937 /* IP Protocol */ 8938 MLXSW_REG_RECR2_IPV4_PROTOCOL = 17, 8939 /* IPv6 Source IP */ 8940 MLXSW_REG_RECR2_IPV6_SIP0_7 = 21, 8941 MLXSW_REG_RECR2_IPV6_SIP8 = 29, 8942 MLXSW_REG_RECR2_IPV6_SIP15 = 36, 8943 /* IPv6 Destination IP */ 8944 MLXSW_REG_RECR2_IPV6_DIP0_7 = 37, 8945 MLXSW_REG_RECR2_IPV6_DIP8 = 45, 8946 MLXSW_REG_RECR2_IPV6_DIP15 = 52, 8947 /* IPv6 Next Header */ 8948 MLXSW_REG_RECR2_IPV6_NEXT_HEADER = 53, 8949 /* IPv6 Flow Label */ 8950 MLXSW_REG_RECR2_IPV6_FLOW_LABEL = 57, 8951 /* TCP/UDP Source Port */ 8952 MLXSW_REG_RECR2_TCP_UDP_SPORT = 74, 8953 /* TCP/UDP Destination Port */ 8954 MLXSW_REG_RECR2_TCP_UDP_DPORT = 75, 8955 8956 __MLXSW_REG_RECR2_FIELD_CNT, 8957 }; 8958 8959 /* reg_recr2_outer_header_fields_enable 8960 * Packet fields to enable for ECMP hash subject to outer_header_enable. 8961 * Access: RW 8962 */ 8963 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1); 8964 8965 /* reg_recr2_inner_header_enables 8966 * Bit mask where each bit enables a specific inner layer to be included in the 8967 * hash calculation. Same values as reg_recr2_outer_header_enables. 8968 * Access: RW 8969 */ 8970 MLXSW_ITEM_BIT_ARRAY(reg, recr2, inner_header_enables, 0x2C, 0x04, 1); 8971 8972 enum { 8973 /* Inner IPv4 Source IP */ 8974 MLXSW_REG_RECR2_INNER_IPV4_SIP0 = 3, 8975 MLXSW_REG_RECR2_INNER_IPV4_SIP3 = 6, 8976 /* Inner IPv4 Destination IP */ 8977 MLXSW_REG_RECR2_INNER_IPV4_DIP0 = 7, 8978 MLXSW_REG_RECR2_INNER_IPV4_DIP3 = 10, 8979 /* Inner IP Protocol */ 8980 MLXSW_REG_RECR2_INNER_IPV4_PROTOCOL = 11, 8981 /* Inner IPv6 Source IP */ 8982 MLXSW_REG_RECR2_INNER_IPV6_SIP0_7 = 12, 8983 MLXSW_REG_RECR2_INNER_IPV6_SIP8 = 20, 8984 MLXSW_REG_RECR2_INNER_IPV6_SIP15 = 27, 8985 /* Inner IPv6 Destination IP */ 8986 MLXSW_REG_RECR2_INNER_IPV6_DIP0_7 = 28, 8987 MLXSW_REG_RECR2_INNER_IPV6_DIP8 = 36, 8988 MLXSW_REG_RECR2_INNER_IPV6_DIP15 = 43, 8989 /* Inner IPv6 Next Header */ 8990 MLXSW_REG_RECR2_INNER_IPV6_NEXT_HEADER = 44, 8991 /* Inner IPv6 Flow Label */ 8992 MLXSW_REG_RECR2_INNER_IPV6_FLOW_LABEL = 45, 8993 /* Inner TCP/UDP Source Port */ 8994 MLXSW_REG_RECR2_INNER_TCP_UDP_SPORT = 46, 8995 /* Inner TCP/UDP Destination Port */ 8996 MLXSW_REG_RECR2_INNER_TCP_UDP_DPORT = 47, 8997 8998 __MLXSW_REG_RECR2_INNER_FIELD_CNT, 8999 }; 9000 9001 /* reg_recr2_inner_header_fields_enable 9002 * Inner packet fields to enable for ECMP hash subject to inner_header_enables. 9003 * Access: RW 9004 */ 9005 MLXSW_ITEM_BIT_ARRAY(reg, recr2, inner_header_fields_enable, 0x30, 0x08, 1); 9006 9007 static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed) 9008 { 9009 MLXSW_REG_ZERO(recr2, payload); 9010 mlxsw_reg_recr2_pp_set(payload, false); 9011 mlxsw_reg_recr2_sh_set(payload, true); 9012 mlxsw_reg_recr2_seed_set(payload, seed); 9013 } 9014 9015 /* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register 9016 * -------------------------------------------------------------- 9017 * The RMFT_V2 register is used to configure and query the multicast table. 9018 */ 9019 #define MLXSW_REG_RMFT2_ID 0x8027 9020 #define MLXSW_REG_RMFT2_LEN 0x174 9021 9022 MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN); 9023 9024 /* reg_rmft2_v 9025 * Valid 9026 * Access: RW 9027 */ 9028 MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1); 9029 9030 enum mlxsw_reg_rmft2_type { 9031 MLXSW_REG_RMFT2_TYPE_IPV4, 9032 MLXSW_REG_RMFT2_TYPE_IPV6 9033 }; 9034 9035 /* reg_rmft2_type 9036 * Access: Index 9037 */ 9038 MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2); 9039 9040 enum mlxsw_sp_reg_rmft2_op { 9041 /* For Write: 9042 * Write operation. Used to write a new entry to the table. All RW 9043 * fields are relevant for new entry. Activity bit is set for new 9044 * entries - Note write with v (Valid) 0 will delete the entry. 9045 * For Query: 9046 * Read operation 9047 */ 9048 MLXSW_REG_RMFT2_OP_READ_WRITE, 9049 }; 9050 9051 /* reg_rmft2_op 9052 * Operation. 9053 * Access: OP 9054 */ 9055 MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2); 9056 9057 /* reg_rmft2_a 9058 * Activity. Set for new entries. Set if a packet lookup has hit on the specific 9059 * entry. 9060 * Access: RO 9061 */ 9062 MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1); 9063 9064 /* reg_rmft2_offset 9065 * Offset within the multicast forwarding table to write to. 9066 * Access: Index 9067 */ 9068 MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16); 9069 9070 /* reg_rmft2_virtual_router 9071 * Virtual Router ID. Range from 0..cap_max_virtual_routers-1 9072 * Access: RW 9073 */ 9074 MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16); 9075 9076 enum mlxsw_reg_rmft2_irif_mask { 9077 MLXSW_REG_RMFT2_IRIF_MASK_IGNORE, 9078 MLXSW_REG_RMFT2_IRIF_MASK_COMPARE 9079 }; 9080 9081 /* reg_rmft2_irif_mask 9082 * Ingress RIF mask. 9083 * Access: RW 9084 */ 9085 MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1); 9086 9087 /* reg_rmft2_irif 9088 * Ingress RIF index. 9089 * Access: RW 9090 */ 9091 MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16); 9092 9093 /* reg_rmft2_dip{4,6} 9094 * Destination IPv4/6 address 9095 * Access: RW 9096 */ 9097 MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16); 9098 MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32); 9099 9100 /* reg_rmft2_dip{4,6}_mask 9101 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 9102 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 9103 * Access: RW 9104 */ 9105 MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16); 9106 MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32); 9107 9108 /* reg_rmft2_sip{4,6} 9109 * Source IPv4/6 address 9110 * Access: RW 9111 */ 9112 MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16); 9113 MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32); 9114 9115 /* reg_rmft2_sip{4,6}_mask 9116 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 9117 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 9118 * Access: RW 9119 */ 9120 MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16); 9121 MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32); 9122 9123 /* reg_rmft2_flexible_action_set 9124 * ACL action set. The only supported action types in this field and in any 9125 * action-set pointed from here are as follows: 9126 * 00h: ACTION_NULL 9127 * 01h: ACTION_MAC_TTL, only TTL configuration is supported. 9128 * 03h: ACTION_TRAP 9129 * 06h: ACTION_QOS 9130 * 08h: ACTION_POLICING_MONITORING 9131 * 10h: ACTION_ROUTER_MC 9132 * Access: RW 9133 */ 9134 MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80, 9135 MLXSW_REG_FLEX_ACTION_SET_LEN); 9136 9137 static inline void 9138 mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset, 9139 u16 virtual_router, 9140 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 9141 const char *flex_action_set) 9142 { 9143 MLXSW_REG_ZERO(rmft2, payload); 9144 mlxsw_reg_rmft2_v_set(payload, v); 9145 mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE); 9146 mlxsw_reg_rmft2_offset_set(payload, offset); 9147 mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router); 9148 mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask); 9149 mlxsw_reg_rmft2_irif_set(payload, irif); 9150 if (flex_action_set) 9151 mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload, 9152 flex_action_set); 9153 } 9154 9155 static inline void 9156 mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router, 9157 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 9158 u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask, 9159 const char *flexible_action_set) 9160 { 9161 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 9162 irif_mask, irif, flexible_action_set); 9163 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4); 9164 mlxsw_reg_rmft2_dip4_set(payload, dip4); 9165 mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask); 9166 mlxsw_reg_rmft2_sip4_set(payload, sip4); 9167 mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask); 9168 } 9169 9170 static inline void 9171 mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router, 9172 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 9173 struct in6_addr dip6, struct in6_addr dip6_mask, 9174 struct in6_addr sip6, struct in6_addr sip6_mask, 9175 const char *flexible_action_set) 9176 { 9177 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 9178 irif_mask, irif, flexible_action_set); 9179 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6); 9180 mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6); 9181 mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask); 9182 mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6); 9183 mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask); 9184 } 9185 9186 /* REIV - Router Egress Interface to VID Register 9187 * ---------------------------------------------- 9188 * The REIV register maps {eRIF, egress_port} -> VID. 9189 * This mapping is done at the egress, after the ACLs. 9190 * This mapping always takes effect after router, regardless of cast 9191 * (for unicast/multicast/port-base multicast), regardless of eRIF type and 9192 * regardless of bridge decisions (e.g. SFD for unicast or SMPE). 9193 * Reserved when the RIF is a loopback RIF. 9194 * 9195 * Note: Reserved when legacy bridge model is used. 9196 */ 9197 #define MLXSW_REG_REIV_ID 0x8034 9198 #define MLXSW_REG_REIV_BASE_LEN 0x20 /* base length, without records */ 9199 #define MLXSW_REG_REIV_REC_LEN 0x04 /* record length */ 9200 #define MLXSW_REG_REIV_REC_MAX_COUNT 256 /* firmware limitation */ 9201 #define MLXSW_REG_REIV_LEN (MLXSW_REG_REIV_BASE_LEN + \ 9202 MLXSW_REG_REIV_REC_LEN * \ 9203 MLXSW_REG_REIV_REC_MAX_COUNT) 9204 9205 MLXSW_REG_DEFINE(reiv, MLXSW_REG_REIV_ID, MLXSW_REG_REIV_LEN); 9206 9207 /* reg_reiv_port_page 9208 * Port page - elport_record[0] is 256*port_page. 9209 * Access: Index 9210 */ 9211 MLXSW_ITEM32(reg, reiv, port_page, 0x00, 0, 4); 9212 9213 /* reg_reiv_erif 9214 * Egress RIF. 9215 * Range is 0..cap_max_router_interfaces-1. 9216 * Access: Index 9217 */ 9218 MLXSW_ITEM32(reg, reiv, erif, 0x04, 0, 16); 9219 9220 /* reg_reiv_rec_update 9221 * Update enable (when write): 9222 * 0 - Do not update the entry. 9223 * 1 - Update the entry. 9224 * Access: OP 9225 */ 9226 MLXSW_ITEM32_INDEXED(reg, reiv, rec_update, MLXSW_REG_REIV_BASE_LEN, 31, 1, 9227 MLXSW_REG_REIV_REC_LEN, 0x00, false); 9228 9229 /* reg_reiv_rec_evid 9230 * Egress VID. 9231 * Range is 0..4095. 9232 * Access: RW 9233 */ 9234 MLXSW_ITEM32_INDEXED(reg, reiv, rec_evid, MLXSW_REG_REIV_BASE_LEN, 0, 12, 9235 MLXSW_REG_REIV_REC_LEN, 0x00, false); 9236 9237 static inline void mlxsw_reg_reiv_pack(char *payload, u8 port_page, u16 erif) 9238 { 9239 MLXSW_REG_ZERO(reiv, payload); 9240 mlxsw_reg_reiv_port_page_set(payload, port_page); 9241 mlxsw_reg_reiv_erif_set(payload, erif); 9242 } 9243 9244 /* MFCR - Management Fan Control Register 9245 * -------------------------------------- 9246 * This register controls the settings of the Fan Speed PWM mechanism. 9247 */ 9248 #define MLXSW_REG_MFCR_ID 0x9001 9249 #define MLXSW_REG_MFCR_LEN 0x08 9250 9251 MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN); 9252 9253 enum mlxsw_reg_mfcr_pwm_frequency { 9254 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00, 9255 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01, 9256 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02, 9257 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40, 9258 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41, 9259 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42, 9260 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43, 9261 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44, 9262 }; 9263 9264 /* reg_mfcr_pwm_frequency 9265 * Controls the frequency of the PWM signal. 9266 * Access: RW 9267 */ 9268 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7); 9269 9270 #define MLXSW_MFCR_TACHOS_MAX 10 9271 9272 /* reg_mfcr_tacho_active 9273 * Indicates which of the tachometer is active (bit per tachometer). 9274 * Access: RO 9275 */ 9276 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX); 9277 9278 #define MLXSW_MFCR_PWMS_MAX 5 9279 9280 /* reg_mfcr_pwm_active 9281 * Indicates which of the PWM control is active (bit per PWM). 9282 * Access: RO 9283 */ 9284 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX); 9285 9286 static inline void 9287 mlxsw_reg_mfcr_pack(char *payload, 9288 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency) 9289 { 9290 MLXSW_REG_ZERO(mfcr, payload); 9291 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency); 9292 } 9293 9294 static inline void 9295 mlxsw_reg_mfcr_unpack(char *payload, 9296 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency, 9297 u16 *p_tacho_active, u8 *p_pwm_active) 9298 { 9299 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload); 9300 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload); 9301 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload); 9302 } 9303 9304 /* MFSC - Management Fan Speed Control Register 9305 * -------------------------------------------- 9306 * This register controls the settings of the Fan Speed PWM mechanism. 9307 */ 9308 #define MLXSW_REG_MFSC_ID 0x9002 9309 #define MLXSW_REG_MFSC_LEN 0x08 9310 9311 MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN); 9312 9313 /* reg_mfsc_pwm 9314 * Fan pwm to control / monitor. 9315 * Access: Index 9316 */ 9317 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3); 9318 9319 /* reg_mfsc_pwm_duty_cycle 9320 * Controls the duty cycle of the PWM. Value range from 0..255 to 9321 * represent duty cycle of 0%...100%. 9322 * Access: RW 9323 */ 9324 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8); 9325 9326 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm, 9327 u8 pwm_duty_cycle) 9328 { 9329 MLXSW_REG_ZERO(mfsc, payload); 9330 mlxsw_reg_mfsc_pwm_set(payload, pwm); 9331 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle); 9332 } 9333 9334 /* MFSM - Management Fan Speed Measurement 9335 * --------------------------------------- 9336 * This register controls the settings of the Tacho measurements and 9337 * enables reading the Tachometer measurements. 9338 */ 9339 #define MLXSW_REG_MFSM_ID 0x9003 9340 #define MLXSW_REG_MFSM_LEN 0x08 9341 9342 MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN); 9343 9344 /* reg_mfsm_tacho 9345 * Fan tachometer index. 9346 * Access: Index 9347 */ 9348 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4); 9349 9350 /* reg_mfsm_rpm 9351 * Fan speed (round per minute). 9352 * Access: RO 9353 */ 9354 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16); 9355 9356 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho) 9357 { 9358 MLXSW_REG_ZERO(mfsm, payload); 9359 mlxsw_reg_mfsm_tacho_set(payload, tacho); 9360 } 9361 9362 /* MFSL - Management Fan Speed Limit Register 9363 * ------------------------------------------ 9364 * The Fan Speed Limit register is used to configure the fan speed 9365 * event / interrupt notification mechanism. Fan speed threshold are 9366 * defined for both under-speed and over-speed. 9367 */ 9368 #define MLXSW_REG_MFSL_ID 0x9004 9369 #define MLXSW_REG_MFSL_LEN 0x0C 9370 9371 MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN); 9372 9373 /* reg_mfsl_tacho 9374 * Fan tachometer index. 9375 * Access: Index 9376 */ 9377 MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4); 9378 9379 /* reg_mfsl_tach_min 9380 * Tachometer minimum value (minimum RPM). 9381 * Access: RW 9382 */ 9383 MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16); 9384 9385 /* reg_mfsl_tach_max 9386 * Tachometer maximum value (maximum RPM). 9387 * Access: RW 9388 */ 9389 MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16); 9390 9391 static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho, 9392 u16 tach_min, u16 tach_max) 9393 { 9394 MLXSW_REG_ZERO(mfsl, payload); 9395 mlxsw_reg_mfsl_tacho_set(payload, tacho); 9396 mlxsw_reg_mfsl_tach_min_set(payload, tach_min); 9397 mlxsw_reg_mfsl_tach_max_set(payload, tach_max); 9398 } 9399 9400 static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho, 9401 u16 *p_tach_min, u16 *p_tach_max) 9402 { 9403 if (p_tach_min) 9404 *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload); 9405 9406 if (p_tach_max) 9407 *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload); 9408 } 9409 9410 /* FORE - Fan Out of Range Event Register 9411 * -------------------------------------- 9412 * This register reports the status of the controlled fans compared to the 9413 * range defined by the MFSL register. 9414 */ 9415 #define MLXSW_REG_FORE_ID 0x9007 9416 #define MLXSW_REG_FORE_LEN 0x0C 9417 9418 MLXSW_REG_DEFINE(fore, MLXSW_REG_FORE_ID, MLXSW_REG_FORE_LEN); 9419 9420 /* fan_under_limit 9421 * Fan speed is below the low limit defined in MFSL register. Each bit relates 9422 * to a single tachometer and indicates the specific tachometer reading is 9423 * below the threshold. 9424 * Access: RO 9425 */ 9426 MLXSW_ITEM32(reg, fore, fan_under_limit, 0x00, 16, 10); 9427 9428 static inline void mlxsw_reg_fore_unpack(char *payload, u8 tacho, 9429 bool *fault) 9430 { 9431 u16 limit; 9432 9433 if (fault) { 9434 limit = mlxsw_reg_fore_fan_under_limit_get(payload); 9435 *fault = limit & BIT(tacho); 9436 } 9437 } 9438 9439 /* MTCAP - Management Temperature Capabilities 9440 * ------------------------------------------- 9441 * This register exposes the capabilities of the device and 9442 * system temperature sensing. 9443 */ 9444 #define MLXSW_REG_MTCAP_ID 0x9009 9445 #define MLXSW_REG_MTCAP_LEN 0x08 9446 9447 MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN); 9448 9449 /* reg_mtcap_sensor_count 9450 * Number of sensors supported by the device. 9451 * This includes the QSFP module sensors (if exists in the QSFP module). 9452 * Access: RO 9453 */ 9454 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7); 9455 9456 /* MTMP - Management Temperature 9457 * ----------------------------- 9458 * This register controls the settings of the temperature measurements 9459 * and enables reading the temperature measurements. Note that temperature 9460 * is in 0.125 degrees Celsius. 9461 */ 9462 #define MLXSW_REG_MTMP_ID 0x900A 9463 #define MLXSW_REG_MTMP_LEN 0x20 9464 9465 MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN); 9466 9467 /* reg_mtmp_slot_index 9468 * Slot index (0: Main board). 9469 * Access: Index 9470 */ 9471 MLXSW_ITEM32(reg, mtmp, slot_index, 0x00, 16, 4); 9472 9473 #define MLXSW_REG_MTMP_MODULE_INDEX_MIN 64 9474 #define MLXSW_REG_MTMP_GBOX_INDEX_MIN 256 9475 /* reg_mtmp_sensor_index 9476 * Sensors index to access. 9477 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially 9478 * (module 0 is mapped to sensor_index 64). 9479 * Access: Index 9480 */ 9481 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 12); 9482 9483 /* Convert to milli degrees Celsius */ 9484 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) ({ typeof(val) v_ = (val); \ 9485 ((v_) >= 0) ? ((v_) * 125) : \ 9486 ((s16)((GENMASK(15, 0) + (v_) + 1) \ 9487 * 125)); }) 9488 9489 /* reg_mtmp_max_operational_temperature 9490 * The highest temperature in the nominal operational range. Reading is in 9491 * 0.125 Celsius degrees units. 9492 * In case of module this is SFF critical temperature threshold. 9493 * Access: RO 9494 */ 9495 MLXSW_ITEM32(reg, mtmp, max_operational_temperature, 0x04, 16, 16); 9496 9497 /* reg_mtmp_temperature 9498 * Temperature reading from the sensor. Reading is in 0.125 Celsius 9499 * degrees units. 9500 * Access: RO 9501 */ 9502 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16); 9503 9504 /* reg_mtmp_mte 9505 * Max Temperature Enable - enables measuring the max temperature on a sensor. 9506 * Access: RW 9507 */ 9508 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1); 9509 9510 /* reg_mtmp_mtr 9511 * Max Temperature Reset - clears the value of the max temperature register. 9512 * Access: WO 9513 */ 9514 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1); 9515 9516 /* reg_mtmp_max_temperature 9517 * The highest measured temperature from the sensor. 9518 * When the bit mte is cleared, the field max_temperature is reserved. 9519 * Access: RO 9520 */ 9521 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16); 9522 9523 /* reg_mtmp_tee 9524 * Temperature Event Enable. 9525 * 0 - Do not generate event 9526 * 1 - Generate event 9527 * 2 - Generate single event 9528 * Access: RW 9529 */ 9530 9531 enum mlxsw_reg_mtmp_tee { 9532 MLXSW_REG_MTMP_TEE_NO_EVENT, 9533 MLXSW_REG_MTMP_TEE_GENERATE_EVENT, 9534 MLXSW_REG_MTMP_TEE_GENERATE_SINGLE_EVENT, 9535 }; 9536 9537 MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2); 9538 9539 #define MLXSW_REG_MTMP_THRESH_HI 0x348 /* 105 Celsius */ 9540 9541 /* reg_mtmp_temperature_threshold_hi 9542 * High threshold for Temperature Warning Event. In 0.125 Celsius. 9543 * Access: RW 9544 */ 9545 MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16); 9546 9547 #define MLXSW_REG_MTMP_HYSTERESIS_TEMP 0x28 /* 5 Celsius */ 9548 /* reg_mtmp_temperature_threshold_lo 9549 * Low threshold for Temperature Warning Event. In 0.125 Celsius. 9550 * Access: RW 9551 */ 9552 MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16); 9553 9554 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8 9555 9556 /* reg_mtmp_sensor_name 9557 * Sensor Name 9558 * Access: RO 9559 */ 9560 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE); 9561 9562 static inline void mlxsw_reg_mtmp_pack(char *payload, u8 slot_index, 9563 u16 sensor_index, bool max_temp_enable, 9564 bool max_temp_reset) 9565 { 9566 MLXSW_REG_ZERO(mtmp, payload); 9567 mlxsw_reg_mtmp_slot_index_set(payload, slot_index); 9568 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index); 9569 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable); 9570 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset); 9571 mlxsw_reg_mtmp_temperature_threshold_hi_set(payload, 9572 MLXSW_REG_MTMP_THRESH_HI); 9573 } 9574 9575 static inline void mlxsw_reg_mtmp_unpack(char *payload, int *p_temp, 9576 int *p_max_temp, int *p_temp_hi, 9577 int *p_max_oper_temp, 9578 char *sensor_name) 9579 { 9580 s16 temp; 9581 9582 if (p_temp) { 9583 temp = mlxsw_reg_mtmp_temperature_get(payload); 9584 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9585 } 9586 if (p_max_temp) { 9587 temp = mlxsw_reg_mtmp_max_temperature_get(payload); 9588 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9589 } 9590 if (p_temp_hi) { 9591 temp = mlxsw_reg_mtmp_temperature_threshold_hi_get(payload); 9592 *p_temp_hi = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9593 } 9594 if (p_max_oper_temp) { 9595 temp = mlxsw_reg_mtmp_max_operational_temperature_get(payload); 9596 *p_max_oper_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 9597 } 9598 if (sensor_name) 9599 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name); 9600 } 9601 9602 /* MTWE - Management Temperature Warning Event 9603 * ------------------------------------------- 9604 * This register is used for over temperature warning. 9605 */ 9606 #define MLXSW_REG_MTWE_ID 0x900B 9607 #define MLXSW_REG_MTWE_LEN 0x10 9608 9609 MLXSW_REG_DEFINE(mtwe, MLXSW_REG_MTWE_ID, MLXSW_REG_MTWE_LEN); 9610 9611 /* reg_mtwe_sensor_warning 9612 * Bit vector indicating which of the sensor reading is above threshold. 9613 * Address 00h bit31 is sensor_warning[127]. 9614 * Address 0Ch bit0 is sensor_warning[0]. 9615 * Access: RO 9616 */ 9617 MLXSW_ITEM_BIT_ARRAY(reg, mtwe, sensor_warning, 0x0, 0x10, 1); 9618 9619 /* MTBR - Management Temperature Bulk Register 9620 * ------------------------------------------- 9621 * This register is used for bulk temperature reading. 9622 */ 9623 #define MLXSW_REG_MTBR_ID 0x900F 9624 #define MLXSW_REG_MTBR_BASE_LEN 0x10 /* base length, without records */ 9625 #define MLXSW_REG_MTBR_REC_LEN 0x04 /* record length */ 9626 #define MLXSW_REG_MTBR_REC_MAX_COUNT 1 9627 #define MLXSW_REG_MTBR_LEN (MLXSW_REG_MTBR_BASE_LEN + \ 9628 MLXSW_REG_MTBR_REC_LEN * \ 9629 MLXSW_REG_MTBR_REC_MAX_COUNT) 9630 9631 MLXSW_REG_DEFINE(mtbr, MLXSW_REG_MTBR_ID, MLXSW_REG_MTBR_LEN); 9632 9633 /* reg_mtbr_slot_index 9634 * Slot index (0: Main board). 9635 * Access: Index 9636 */ 9637 MLXSW_ITEM32(reg, mtbr, slot_index, 0x00, 16, 4); 9638 9639 /* reg_mtbr_base_sensor_index 9640 * Base sensors index to access (0 - ASIC sensor, 1-63 - ambient sensors, 9641 * 64-127 are mapped to the SFP+/QSFP modules sequentially). 9642 * Access: Index 9643 */ 9644 MLXSW_ITEM32(reg, mtbr, base_sensor_index, 0x00, 0, 12); 9645 9646 /* reg_mtbr_num_rec 9647 * Request: Number of records to read 9648 * Response: Number of records read 9649 * See above description for more details. 9650 * Range 1..255 9651 * Access: RW 9652 */ 9653 MLXSW_ITEM32(reg, mtbr, num_rec, 0x04, 0, 8); 9654 9655 /* reg_mtbr_rec_max_temp 9656 * The highest measured temperature from the sensor. 9657 * When the bit mte is cleared, the field max_temperature is reserved. 9658 * Access: RO 9659 */ 9660 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_max_temp, MLXSW_REG_MTBR_BASE_LEN, 16, 9661 16, MLXSW_REG_MTBR_REC_LEN, 0x00, false); 9662 9663 /* reg_mtbr_rec_temp 9664 * Temperature reading from the sensor. Reading is in 0..125 Celsius 9665 * degrees units. 9666 * Access: RO 9667 */ 9668 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_temp, MLXSW_REG_MTBR_BASE_LEN, 0, 16, 9669 MLXSW_REG_MTBR_REC_LEN, 0x00, false); 9670 9671 static inline void mlxsw_reg_mtbr_pack(char *payload, u8 slot_index, 9672 u16 base_sensor_index) 9673 { 9674 MLXSW_REG_ZERO(mtbr, payload); 9675 mlxsw_reg_mtbr_slot_index_set(payload, slot_index); 9676 mlxsw_reg_mtbr_base_sensor_index_set(payload, base_sensor_index); 9677 mlxsw_reg_mtbr_num_rec_set(payload, 1); 9678 } 9679 9680 /* Error codes from temperatute reading */ 9681 enum mlxsw_reg_mtbr_temp_status { 9682 MLXSW_REG_MTBR_NO_CONN = 0x8000, 9683 MLXSW_REG_MTBR_NO_TEMP_SENS = 0x8001, 9684 MLXSW_REG_MTBR_INDEX_NA = 0x8002, 9685 MLXSW_REG_MTBR_BAD_SENS_INFO = 0x8003, 9686 }; 9687 9688 /* Base index for reading modules temperature */ 9689 #define MLXSW_REG_MTBR_BASE_MODULE_INDEX 64 9690 9691 static inline void mlxsw_reg_mtbr_temp_unpack(char *payload, int rec_ind, 9692 u16 *p_temp, u16 *p_max_temp) 9693 { 9694 if (p_temp) 9695 *p_temp = mlxsw_reg_mtbr_rec_temp_get(payload, rec_ind); 9696 if (p_max_temp) 9697 *p_max_temp = mlxsw_reg_mtbr_rec_max_temp_get(payload, rec_ind); 9698 } 9699 9700 /* MCIA - Management Cable Info Access 9701 * ----------------------------------- 9702 * MCIA register is used to access the SFP+ and QSFP connector's EPROM. 9703 */ 9704 9705 #define MLXSW_REG_MCIA_ID 0x9014 9706 #define MLXSW_REG_MCIA_LEN 0x94 9707 9708 MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN); 9709 9710 /* reg_mcia_module 9711 * Module number. 9712 * Access: Index 9713 */ 9714 MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8); 9715 9716 /* reg_mcia_slot_index 9717 * Slot index (0: Main board) 9718 * Access: Index 9719 */ 9720 MLXSW_ITEM32(reg, mcia, slot, 0x00, 12, 4); 9721 9722 enum { 9723 MLXSW_REG_MCIA_STATUS_GOOD = 0, 9724 /* No response from module's EEPROM. */ 9725 MLXSW_REG_MCIA_STATUS_NO_EEPROM_MODULE = 1, 9726 /* Module type not supported by the device. */ 9727 MLXSW_REG_MCIA_STATUS_MODULE_NOT_SUPPORTED = 2, 9728 /* No module present indication. */ 9729 MLXSW_REG_MCIA_STATUS_MODULE_NOT_CONNECTED = 3, 9730 /* Error occurred while trying to access module's EEPROM using I2C. */ 9731 MLXSW_REG_MCIA_STATUS_I2C_ERROR = 9, 9732 /* Module is disabled. */ 9733 MLXSW_REG_MCIA_STATUS_MODULE_DISABLED = 16, 9734 }; 9735 9736 /* reg_mcia_status 9737 * Module status. 9738 * Access: RO 9739 */ 9740 MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8); 9741 9742 /* reg_mcia_i2c_device_address 9743 * I2C device address. 9744 * Access: RW 9745 */ 9746 MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8); 9747 9748 /* reg_mcia_page_number 9749 * Page number. 9750 * Access: RW 9751 */ 9752 MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8); 9753 9754 /* reg_mcia_device_address 9755 * Device address. 9756 * Access: RW 9757 */ 9758 MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16); 9759 9760 /* reg_mcia_bank_number 9761 * Bank number. 9762 * Access: Index 9763 */ 9764 MLXSW_ITEM32(reg, mcia, bank_number, 0x08, 16, 8); 9765 9766 /* reg_mcia_size 9767 * Number of bytes to read/write (up to 48 bytes). 9768 * Access: RW 9769 */ 9770 MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16); 9771 9772 #define MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH 256 9773 #define MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH 128 9774 #define MLXSW_REG_MCIA_I2C_ADDR_LOW 0x50 9775 #define MLXSW_REG_MCIA_I2C_ADDR_HIGH 0x51 9776 #define MLXSW_REG_MCIA_PAGE0_LO_OFF 0xa0 9777 #define MLXSW_REG_MCIA_TH_ITEM_SIZE 2 9778 #define MLXSW_REG_MCIA_TH_PAGE_NUM 3 9779 #define MLXSW_REG_MCIA_TH_PAGE_CMIS_NUM 2 9780 #define MLXSW_REG_MCIA_PAGE0_LO 0 9781 #define MLXSW_REG_MCIA_TH_PAGE_OFF 0x80 9782 #define MLXSW_REG_MCIA_EEPROM_CMIS_FLAT_MEMORY BIT(7) 9783 9784 enum mlxsw_reg_mcia_eeprom_module_info_rev_id { 9785 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00, 9786 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01, 9787 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03, 9788 }; 9789 9790 enum mlxsw_reg_mcia_eeprom_module_info_id { 9791 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_SFP = 0x03, 9792 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP = 0x0C, 9793 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D, 9794 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11, 9795 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_DD = 0x18, 9796 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_OSFP = 0x19, 9797 }; 9798 9799 enum mlxsw_reg_mcia_eeprom_module_info { 9800 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID, 9801 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID, 9802 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_TYPE_ID, 9803 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_SIZE, 9804 }; 9805 9806 /* reg_mcia_eeprom 9807 * Bytes to read/write. 9808 * Access: RW 9809 */ 9810 MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, 128); 9811 9812 /* This is used to access the optional upper pages (1-3) in the QSFP+ 9813 * memory map. Page 1 is available on offset 256 through 383, page 2 - 9814 * on offset 384 through 511, page 3 - on offset 512 through 639. 9815 */ 9816 #define MLXSW_REG_MCIA_PAGE_GET(off) (((off) - \ 9817 MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH) / \ 9818 MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH + 1) 9819 9820 static inline void mlxsw_reg_mcia_pack(char *payload, u8 slot_index, u8 module, 9821 u8 page_number, u16 device_addr, u8 size, 9822 u8 i2c_device_addr) 9823 { 9824 MLXSW_REG_ZERO(mcia, payload); 9825 mlxsw_reg_mcia_slot_set(payload, slot_index); 9826 mlxsw_reg_mcia_module_set(payload, module); 9827 mlxsw_reg_mcia_page_number_set(payload, page_number); 9828 mlxsw_reg_mcia_device_address_set(payload, device_addr); 9829 mlxsw_reg_mcia_size_set(payload, size); 9830 mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr); 9831 } 9832 9833 /* MPAT - Monitoring Port Analyzer Table 9834 * ------------------------------------- 9835 * MPAT Register is used to query and configure the Switch PortAnalyzer Table. 9836 * For an enabled analyzer, all fields except e (enable) cannot be modified. 9837 */ 9838 #define MLXSW_REG_MPAT_ID 0x901A 9839 #define MLXSW_REG_MPAT_LEN 0x78 9840 9841 MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN); 9842 9843 /* reg_mpat_pa_id 9844 * Port Analyzer ID. 9845 * Access: Index 9846 */ 9847 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4); 9848 9849 /* reg_mpat_session_id 9850 * Mirror Session ID. 9851 * Used for MIRROR_SESSION<i> trap. 9852 * Access: RW 9853 */ 9854 MLXSW_ITEM32(reg, mpat, session_id, 0x00, 24, 4); 9855 9856 /* reg_mpat_system_port 9857 * A unique port identifier for the final destination of the packet. 9858 * Access: RW 9859 */ 9860 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16); 9861 9862 /* reg_mpat_e 9863 * Enable. Indicating the Port Analyzer is enabled. 9864 * Access: RW 9865 */ 9866 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1); 9867 9868 /* reg_mpat_qos 9869 * Quality Of Service Mode. 9870 * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation 9871 * PCP, DEI, DSCP or VL) are configured. 9872 * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the 9873 * same as in the original packet that has triggered the mirroring. For 9874 * SPAN also the pcp,dei are maintained. 9875 * Access: RW 9876 */ 9877 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1); 9878 9879 /* reg_mpat_be 9880 * Best effort mode. Indicates mirroring traffic should not cause packet 9881 * drop or back pressure, but will discard the mirrored packets. Mirrored 9882 * packets will be forwarded on a best effort manner. 9883 * 0: Do not discard mirrored packets 9884 * 1: Discard mirrored packets if causing congestion 9885 * Access: RW 9886 */ 9887 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1); 9888 9889 enum mlxsw_reg_mpat_span_type { 9890 /* Local SPAN Ethernet. 9891 * The original packet is not encapsulated. 9892 */ 9893 MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0, 9894 9895 /* Remote SPAN Ethernet VLAN. 9896 * The packet is forwarded to the monitoring port on the monitoring 9897 * VLAN. 9898 */ 9899 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1, 9900 9901 /* Encapsulated Remote SPAN Ethernet L3 GRE. 9902 * The packet is encapsulated with GRE header. 9903 */ 9904 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3, 9905 }; 9906 9907 /* reg_mpat_span_type 9908 * SPAN type. 9909 * Access: RW 9910 */ 9911 MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4); 9912 9913 /* reg_mpat_pide 9914 * Policer enable. 9915 * Access: RW 9916 */ 9917 MLXSW_ITEM32(reg, mpat, pide, 0x0C, 15, 1); 9918 9919 /* reg_mpat_pid 9920 * Policer ID. 9921 * Access: RW 9922 */ 9923 MLXSW_ITEM32(reg, mpat, pid, 0x0C, 0, 14); 9924 9925 /* Remote SPAN - Ethernet VLAN 9926 * - - - - - - - - - - - - - - 9927 */ 9928 9929 /* reg_mpat_eth_rspan_vid 9930 * Encapsulation header VLAN ID. 9931 * Access: RW 9932 */ 9933 MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12); 9934 9935 /* Encapsulated Remote SPAN - Ethernet L2 9936 * - - - - - - - - - - - - - - - - - - - 9937 */ 9938 9939 enum mlxsw_reg_mpat_eth_rspan_version { 9940 MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15, 9941 }; 9942 9943 /* reg_mpat_eth_rspan_version 9944 * RSPAN mirror header version. 9945 * Access: RW 9946 */ 9947 MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4); 9948 9949 /* reg_mpat_eth_rspan_mac 9950 * Destination MAC address. 9951 * Access: RW 9952 */ 9953 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6); 9954 9955 /* reg_mpat_eth_rspan_tp 9956 * Tag Packet. Indicates whether the mirroring header should be VLAN tagged. 9957 * Access: RW 9958 */ 9959 MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1); 9960 9961 /* Encapsulated Remote SPAN - Ethernet L3 9962 * - - - - - - - - - - - - - - - - - - - 9963 */ 9964 9965 enum mlxsw_reg_mpat_eth_rspan_protocol { 9966 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4, 9967 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6, 9968 }; 9969 9970 /* reg_mpat_eth_rspan_protocol 9971 * SPAN encapsulation protocol. 9972 * Access: RW 9973 */ 9974 MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4); 9975 9976 /* reg_mpat_eth_rspan_ttl 9977 * Encapsulation header Time-to-Live/HopLimit. 9978 * Access: RW 9979 */ 9980 MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8); 9981 9982 /* reg_mpat_eth_rspan_smac 9983 * Source MAC address 9984 * Access: RW 9985 */ 9986 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6); 9987 9988 /* reg_mpat_eth_rspan_dip* 9989 * Destination IP address. The IP version is configured by protocol. 9990 * Access: RW 9991 */ 9992 MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32); 9993 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16); 9994 9995 /* reg_mpat_eth_rspan_sip* 9996 * Source IP address. The IP version is configured by protocol. 9997 * Access: RW 9998 */ 9999 MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32); 10000 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16); 10001 10002 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id, 10003 u16 system_port, bool e, 10004 enum mlxsw_reg_mpat_span_type span_type) 10005 { 10006 MLXSW_REG_ZERO(mpat, payload); 10007 mlxsw_reg_mpat_pa_id_set(payload, pa_id); 10008 mlxsw_reg_mpat_system_port_set(payload, system_port); 10009 mlxsw_reg_mpat_e_set(payload, e); 10010 mlxsw_reg_mpat_qos_set(payload, 1); 10011 mlxsw_reg_mpat_be_set(payload, 1); 10012 mlxsw_reg_mpat_span_type_set(payload, span_type); 10013 } 10014 10015 static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid) 10016 { 10017 mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid); 10018 } 10019 10020 static inline void 10021 mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload, 10022 enum mlxsw_reg_mpat_eth_rspan_version version, 10023 const char *mac, 10024 bool tp) 10025 { 10026 mlxsw_reg_mpat_eth_rspan_version_set(payload, version); 10027 mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac); 10028 mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp); 10029 } 10030 10031 static inline void 10032 mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl, 10033 const char *smac, 10034 u32 sip, u32 dip) 10035 { 10036 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 10037 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 10038 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 10039 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4); 10040 mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip); 10041 mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip); 10042 } 10043 10044 static inline void 10045 mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl, 10046 const char *smac, 10047 struct in6_addr sip, struct in6_addr dip) 10048 { 10049 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 10050 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 10051 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 10052 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6); 10053 mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip); 10054 mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip); 10055 } 10056 10057 /* MPAR - Monitoring Port Analyzer Register 10058 * ---------------------------------------- 10059 * MPAR register is used to query and configure the port analyzer port mirroring 10060 * properties. 10061 */ 10062 #define MLXSW_REG_MPAR_ID 0x901B 10063 #define MLXSW_REG_MPAR_LEN 0x0C 10064 10065 MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN); 10066 10067 /* reg_mpar_local_port 10068 * The local port to mirror the packets from. 10069 * Access: Index 10070 */ 10071 MLXSW_ITEM32_LP(reg, mpar, 0x00, 16, 0x00, 4); 10072 10073 enum mlxsw_reg_mpar_i_e { 10074 MLXSW_REG_MPAR_TYPE_EGRESS, 10075 MLXSW_REG_MPAR_TYPE_INGRESS, 10076 }; 10077 10078 /* reg_mpar_i_e 10079 * Ingress/Egress 10080 * Access: Index 10081 */ 10082 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4); 10083 10084 /* reg_mpar_enable 10085 * Enable mirroring 10086 * By default, port mirroring is disabled for all ports. 10087 * Access: RW 10088 */ 10089 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1); 10090 10091 /* reg_mpar_pa_id 10092 * Port Analyzer ID. 10093 * Access: RW 10094 */ 10095 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4); 10096 10097 #define MLXSW_REG_MPAR_RATE_MAX 3500000000UL 10098 10099 /* reg_mpar_probability_rate 10100 * Sampling rate. 10101 * Valid values are: 1 to 3.5*10^9 10102 * Value of 1 means "sample all". Default is 1. 10103 * Reserved when Spectrum-1. 10104 * Access: RW 10105 */ 10106 MLXSW_ITEM32(reg, mpar, probability_rate, 0x08, 0, 32); 10107 10108 static inline void mlxsw_reg_mpar_pack(char *payload, u16 local_port, 10109 enum mlxsw_reg_mpar_i_e i_e, 10110 bool enable, u8 pa_id, 10111 u32 probability_rate) 10112 { 10113 MLXSW_REG_ZERO(mpar, payload); 10114 mlxsw_reg_mpar_local_port_set(payload, local_port); 10115 mlxsw_reg_mpar_enable_set(payload, enable); 10116 mlxsw_reg_mpar_i_e_set(payload, i_e); 10117 mlxsw_reg_mpar_pa_id_set(payload, pa_id); 10118 mlxsw_reg_mpar_probability_rate_set(payload, probability_rate); 10119 } 10120 10121 /* MGIR - Management General Information Register 10122 * ---------------------------------------------- 10123 * MGIR register allows software to query the hardware and firmware general 10124 * information. 10125 */ 10126 #define MLXSW_REG_MGIR_ID 0x9020 10127 #define MLXSW_REG_MGIR_LEN 0x9C 10128 10129 MLXSW_REG_DEFINE(mgir, MLXSW_REG_MGIR_ID, MLXSW_REG_MGIR_LEN); 10130 10131 /* reg_mgir_hw_info_device_hw_revision 10132 * Access: RO 10133 */ 10134 MLXSW_ITEM32(reg, mgir, hw_info_device_hw_revision, 0x0, 16, 16); 10135 10136 /* reg_mgir_fw_info_latency_tlv 10137 * When set, latency-TLV is supported. 10138 * Access: RO 10139 */ 10140 MLXSW_ITEM32(reg, mgir, fw_info_latency_tlv, 0x20, 29, 1); 10141 10142 /* reg_mgir_fw_info_string_tlv 10143 * When set, string-TLV is supported. 10144 * Access: RO 10145 */ 10146 MLXSW_ITEM32(reg, mgir, fw_info_string_tlv, 0x20, 28, 1); 10147 10148 #define MLXSW_REG_MGIR_FW_INFO_PSID_SIZE 16 10149 10150 /* reg_mgir_fw_info_psid 10151 * PSID (ASCII string). 10152 * Access: RO 10153 */ 10154 MLXSW_ITEM_BUF(reg, mgir, fw_info_psid, 0x30, MLXSW_REG_MGIR_FW_INFO_PSID_SIZE); 10155 10156 /* reg_mgir_fw_info_extended_major 10157 * Access: RO 10158 */ 10159 MLXSW_ITEM32(reg, mgir, fw_info_extended_major, 0x44, 0, 32); 10160 10161 /* reg_mgir_fw_info_extended_minor 10162 * Access: RO 10163 */ 10164 MLXSW_ITEM32(reg, mgir, fw_info_extended_minor, 0x48, 0, 32); 10165 10166 /* reg_mgir_fw_info_extended_sub_minor 10167 * Access: RO 10168 */ 10169 MLXSW_ITEM32(reg, mgir, fw_info_extended_sub_minor, 0x4C, 0, 32); 10170 10171 static inline void mlxsw_reg_mgir_pack(char *payload) 10172 { 10173 MLXSW_REG_ZERO(mgir, payload); 10174 } 10175 10176 static inline void 10177 mlxsw_reg_mgir_unpack(char *payload, u32 *hw_rev, char *fw_info_psid, 10178 u32 *fw_major, u32 *fw_minor, u32 *fw_sub_minor) 10179 { 10180 *hw_rev = mlxsw_reg_mgir_hw_info_device_hw_revision_get(payload); 10181 mlxsw_reg_mgir_fw_info_psid_memcpy_from(payload, fw_info_psid); 10182 *fw_major = mlxsw_reg_mgir_fw_info_extended_major_get(payload); 10183 *fw_minor = mlxsw_reg_mgir_fw_info_extended_minor_get(payload); 10184 *fw_sub_minor = mlxsw_reg_mgir_fw_info_extended_sub_minor_get(payload); 10185 } 10186 10187 /* MRSR - Management Reset and Shutdown Register 10188 * --------------------------------------------- 10189 * MRSR register is used to reset or shutdown the switch or 10190 * the entire system (when applicable). 10191 */ 10192 #define MLXSW_REG_MRSR_ID 0x9023 10193 #define MLXSW_REG_MRSR_LEN 0x08 10194 10195 MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN); 10196 10197 enum mlxsw_reg_mrsr_command { 10198 /* Switch soft reset, does not reset PCI firmware. */ 10199 MLXSW_REG_MRSR_COMMAND_SOFTWARE_RESET = 1, 10200 /* Reset will be done when PCI link will be disabled. 10201 * This command will reset PCI firmware also. 10202 */ 10203 MLXSW_REG_MRSR_COMMAND_RESET_AT_PCI_DISABLE = 6, 10204 }; 10205 10206 /* reg_mrsr_command 10207 * Reset/shutdown command 10208 * 0 - do nothing 10209 * 1 - software reset 10210 * Access: WO 10211 */ 10212 MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4); 10213 10214 static inline void mlxsw_reg_mrsr_pack(char *payload, 10215 enum mlxsw_reg_mrsr_command command) 10216 { 10217 MLXSW_REG_ZERO(mrsr, payload); 10218 mlxsw_reg_mrsr_command_set(payload, command); 10219 } 10220 10221 /* MLCR - Management LED Control Register 10222 * -------------------------------------- 10223 * Controls the system LEDs. 10224 */ 10225 #define MLXSW_REG_MLCR_ID 0x902B 10226 #define MLXSW_REG_MLCR_LEN 0x0C 10227 10228 MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN); 10229 10230 /* reg_mlcr_local_port 10231 * Local port number. 10232 * Access: RW 10233 */ 10234 MLXSW_ITEM32_LP(reg, mlcr, 0x00, 16, 0x00, 24); 10235 10236 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF 10237 10238 /* reg_mlcr_beacon_duration 10239 * Duration of the beacon to be active, in seconds. 10240 * 0x0 - Will turn off the beacon. 10241 * 0xFFFF - Will turn on the beacon until explicitly turned off. 10242 * Access: RW 10243 */ 10244 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16); 10245 10246 /* reg_mlcr_beacon_remain 10247 * Remaining duration of the beacon, in seconds. 10248 * 0xFFFF indicates an infinite amount of time. 10249 * Access: RO 10250 */ 10251 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16); 10252 10253 static inline void mlxsw_reg_mlcr_pack(char *payload, u16 local_port, 10254 bool active) 10255 { 10256 MLXSW_REG_ZERO(mlcr, payload); 10257 mlxsw_reg_mlcr_local_port_set(payload, local_port); 10258 mlxsw_reg_mlcr_beacon_duration_set(payload, active ? 10259 MLXSW_REG_MLCR_DURATION_MAX : 0); 10260 } 10261 10262 /* MCION - Management Cable IO and Notifications Register 10263 * ------------------------------------------------------ 10264 * The MCION register is used to query transceiver modules' IO pins and other 10265 * notifications. 10266 */ 10267 #define MLXSW_REG_MCION_ID 0x9052 10268 #define MLXSW_REG_MCION_LEN 0x18 10269 10270 MLXSW_REG_DEFINE(mcion, MLXSW_REG_MCION_ID, MLXSW_REG_MCION_LEN); 10271 10272 /* reg_mcion_module 10273 * Module number. 10274 * Access: Index 10275 */ 10276 MLXSW_ITEM32(reg, mcion, module, 0x00, 16, 8); 10277 10278 /* reg_mcion_slot_index 10279 * Slot index. 10280 * Access: Index 10281 */ 10282 MLXSW_ITEM32(reg, mcion, slot_index, 0x00, 12, 4); 10283 10284 enum { 10285 MLXSW_REG_MCION_MODULE_STATUS_BITS_PRESENT_MASK = BIT(0), 10286 MLXSW_REG_MCION_MODULE_STATUS_BITS_LOW_POWER_MASK = BIT(8), 10287 }; 10288 10289 /* reg_mcion_module_status_bits 10290 * Module IO status as defined by SFF. 10291 * Access: RO 10292 */ 10293 MLXSW_ITEM32(reg, mcion, module_status_bits, 0x04, 0, 16); 10294 10295 static inline void mlxsw_reg_mcion_pack(char *payload, u8 slot_index, u8 module) 10296 { 10297 MLXSW_REG_ZERO(mcion, payload); 10298 mlxsw_reg_mcion_slot_index_set(payload, slot_index); 10299 mlxsw_reg_mcion_module_set(payload, module); 10300 } 10301 10302 /* MTPPS - Management Pulse Per Second Register 10303 * -------------------------------------------- 10304 * This register provides the device PPS capabilities, configure the PPS in and 10305 * out modules and holds the PPS in time stamp. 10306 */ 10307 #define MLXSW_REG_MTPPS_ID 0x9053 10308 #define MLXSW_REG_MTPPS_LEN 0x3C 10309 10310 MLXSW_REG_DEFINE(mtpps, MLXSW_REG_MTPPS_ID, MLXSW_REG_MTPPS_LEN); 10311 10312 /* reg_mtpps_enable 10313 * Enables the PPS functionality the specific pin. 10314 * A boolean variable. 10315 * Access: RW 10316 */ 10317 MLXSW_ITEM32(reg, mtpps, enable, 0x20, 31, 1); 10318 10319 enum mlxsw_reg_mtpps_pin_mode { 10320 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN = 0x2, 10321 }; 10322 10323 /* reg_mtpps_pin_mode 10324 * Pin mode to be used. The mode must comply with the supported modes of the 10325 * requested pin. 10326 * Access: RW 10327 */ 10328 MLXSW_ITEM32(reg, mtpps, pin_mode, 0x20, 8, 4); 10329 10330 #define MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN 7 10331 10332 /* reg_mtpps_pin 10333 * Pin to be configured or queried out of the supported pins. 10334 * Access: Index 10335 */ 10336 MLXSW_ITEM32(reg, mtpps, pin, 0x20, 0, 8); 10337 10338 /* reg_mtpps_time_stamp 10339 * When pin_mode = pps_in, the latched device time when it was triggered from 10340 * the external GPIO pin. 10341 * When pin_mode = pps_out or virtual_pin or pps_out_and_virtual_pin, the target 10342 * time to generate next output signal. 10343 * Time is in units of device clock. 10344 * Access: RW 10345 */ 10346 MLXSW_ITEM64(reg, mtpps, time_stamp, 0x28, 0, 64); 10347 10348 static inline void 10349 mlxsw_reg_mtpps_vpin_pack(char *payload, u64 time_stamp) 10350 { 10351 MLXSW_REG_ZERO(mtpps, payload); 10352 mlxsw_reg_mtpps_pin_set(payload, MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN); 10353 mlxsw_reg_mtpps_pin_mode_set(payload, 10354 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN); 10355 mlxsw_reg_mtpps_enable_set(payload, true); 10356 mlxsw_reg_mtpps_time_stamp_set(payload, time_stamp); 10357 } 10358 10359 /* MTUTC - Management UTC Register 10360 * ------------------------------- 10361 * Configures the HW UTC counter. 10362 */ 10363 #define MLXSW_REG_MTUTC_ID 0x9055 10364 #define MLXSW_REG_MTUTC_LEN 0x1C 10365 10366 MLXSW_REG_DEFINE(mtutc, MLXSW_REG_MTUTC_ID, MLXSW_REG_MTUTC_LEN); 10367 10368 enum mlxsw_reg_mtutc_operation { 10369 MLXSW_REG_MTUTC_OPERATION_SET_TIME_AT_NEXT_SEC = 0, 10370 MLXSW_REG_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 1, 10371 MLXSW_REG_MTUTC_OPERATION_ADJUST_TIME = 2, 10372 MLXSW_REG_MTUTC_OPERATION_ADJUST_FREQ = 3, 10373 }; 10374 10375 /* reg_mtutc_operation 10376 * Operation. 10377 * Access: OP 10378 */ 10379 MLXSW_ITEM32(reg, mtutc, operation, 0x00, 0, 4); 10380 10381 /* reg_mtutc_freq_adjustment 10382 * Frequency adjustment: Every PPS the HW frequency will be 10383 * adjusted by this value. Units of HW clock, where HW counts 10384 * 10^9 HW clocks for 1 HW second. Range is from -50,000,000 to +50,000,000. 10385 * In Spectrum-2, the field is reversed, positive values mean to decrease the 10386 * frequency. 10387 * Access: RW 10388 */ 10389 MLXSW_ITEM32(reg, mtutc, freq_adjustment, 0x04, 0, 32); 10390 10391 #define MLXSW_REG_MTUTC_MAX_FREQ_ADJ (50 * 1000 * 1000) 10392 10393 /* reg_mtutc_utc_sec 10394 * UTC seconds. 10395 * Access: WO 10396 */ 10397 MLXSW_ITEM32(reg, mtutc, utc_sec, 0x10, 0, 32); 10398 10399 /* reg_mtutc_utc_nsec 10400 * UTC nSecs. 10401 * Range 0..(10^9-1) 10402 * Updated when operation is SET_TIME_IMMEDIATE. 10403 * Reserved on Spectrum-1. 10404 * Access: WO 10405 */ 10406 MLXSW_ITEM32(reg, mtutc, utc_nsec, 0x14, 0, 30); 10407 10408 /* reg_mtutc_time_adjustment 10409 * Time adjustment. 10410 * Units of nSec. 10411 * Range is from -32768 to +32767. 10412 * Updated when operation is ADJUST_TIME. 10413 * Reserved on Spectrum-1. 10414 * Access: WO 10415 */ 10416 MLXSW_ITEM32(reg, mtutc, time_adjustment, 0x18, 0, 32); 10417 10418 static inline void 10419 mlxsw_reg_mtutc_pack(char *payload, enum mlxsw_reg_mtutc_operation oper, 10420 u32 freq_adj, u32 utc_sec, u32 utc_nsec, u32 time_adj) 10421 { 10422 MLXSW_REG_ZERO(mtutc, payload); 10423 mlxsw_reg_mtutc_operation_set(payload, oper); 10424 mlxsw_reg_mtutc_freq_adjustment_set(payload, freq_adj); 10425 mlxsw_reg_mtutc_utc_sec_set(payload, utc_sec); 10426 mlxsw_reg_mtutc_utc_nsec_set(payload, utc_nsec); 10427 mlxsw_reg_mtutc_time_adjustment_set(payload, time_adj); 10428 } 10429 10430 /* MCQI - Management Component Query Information 10431 * --------------------------------------------- 10432 * This register allows querying information about firmware components. 10433 */ 10434 #define MLXSW_REG_MCQI_ID 0x9061 10435 #define MLXSW_REG_MCQI_BASE_LEN 0x18 10436 #define MLXSW_REG_MCQI_CAP_LEN 0x14 10437 #define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN) 10438 10439 MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN); 10440 10441 /* reg_mcqi_component_index 10442 * Index of the accessed component. 10443 * Access: Index 10444 */ 10445 MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16); 10446 10447 enum mlxfw_reg_mcqi_info_type { 10448 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES, 10449 }; 10450 10451 /* reg_mcqi_info_type 10452 * Component properties set. 10453 * Access: RW 10454 */ 10455 MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5); 10456 10457 /* reg_mcqi_offset 10458 * The requested/returned data offset from the section start, given in bytes. 10459 * Must be DWORD aligned. 10460 * Access: RW 10461 */ 10462 MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32); 10463 10464 /* reg_mcqi_data_size 10465 * The requested/returned data size, given in bytes. If data_size is not DWORD 10466 * aligned, the last bytes are zero padded. 10467 * Access: RW 10468 */ 10469 MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16); 10470 10471 /* reg_mcqi_cap_max_component_size 10472 * Maximum size for this component, given in bytes. 10473 * Access: RO 10474 */ 10475 MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32); 10476 10477 /* reg_mcqi_cap_log_mcda_word_size 10478 * Log 2 of the access word size in bytes. Read and write access must be aligned 10479 * to the word size. Write access must be done for an integer number of words. 10480 * Access: RO 10481 */ 10482 MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4); 10483 10484 /* reg_mcqi_cap_mcda_max_write_size 10485 * Maximal write size for MCDA register 10486 * Access: RO 10487 */ 10488 MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16); 10489 10490 static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index) 10491 { 10492 MLXSW_REG_ZERO(mcqi, payload); 10493 mlxsw_reg_mcqi_component_index_set(payload, component_index); 10494 mlxsw_reg_mcqi_info_type_set(payload, 10495 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES); 10496 mlxsw_reg_mcqi_offset_set(payload, 0); 10497 mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN); 10498 } 10499 10500 static inline void mlxsw_reg_mcqi_unpack(char *payload, 10501 u32 *p_cap_max_component_size, 10502 u8 *p_cap_log_mcda_word_size, 10503 u16 *p_cap_mcda_max_write_size) 10504 { 10505 *p_cap_max_component_size = 10506 mlxsw_reg_mcqi_cap_max_component_size_get(payload); 10507 *p_cap_log_mcda_word_size = 10508 mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload); 10509 *p_cap_mcda_max_write_size = 10510 mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload); 10511 } 10512 10513 /* MCC - Management Component Control 10514 * ---------------------------------- 10515 * Controls the firmware component and updates the FSM. 10516 */ 10517 #define MLXSW_REG_MCC_ID 0x9062 10518 #define MLXSW_REG_MCC_LEN 0x1C 10519 10520 MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN); 10521 10522 enum mlxsw_reg_mcc_instruction { 10523 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01, 10524 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02, 10525 MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03, 10526 MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04, 10527 MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06, 10528 MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08, 10529 }; 10530 10531 /* reg_mcc_instruction 10532 * Command to be executed by the FSM. 10533 * Applicable for write operation only. 10534 * Access: RW 10535 */ 10536 MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8); 10537 10538 /* reg_mcc_component_index 10539 * Index of the accessed component. Applicable only for commands that 10540 * refer to components. Otherwise, this field is reserved. 10541 * Access: Index 10542 */ 10543 MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16); 10544 10545 /* reg_mcc_update_handle 10546 * Token representing the current flow executed by the FSM. 10547 * Access: WO 10548 */ 10549 MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24); 10550 10551 /* reg_mcc_error_code 10552 * Indicates the successful completion of the instruction, or the reason it 10553 * failed 10554 * Access: RO 10555 */ 10556 MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8); 10557 10558 /* reg_mcc_control_state 10559 * Current FSM state 10560 * Access: RO 10561 */ 10562 MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4); 10563 10564 /* reg_mcc_component_size 10565 * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying 10566 * the size may shorten the update time. Value 0x0 means that size is 10567 * unspecified. 10568 * Access: WO 10569 */ 10570 MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32); 10571 10572 static inline void mlxsw_reg_mcc_pack(char *payload, 10573 enum mlxsw_reg_mcc_instruction instr, 10574 u16 component_index, u32 update_handle, 10575 u32 component_size) 10576 { 10577 MLXSW_REG_ZERO(mcc, payload); 10578 mlxsw_reg_mcc_instruction_set(payload, instr); 10579 mlxsw_reg_mcc_component_index_set(payload, component_index); 10580 mlxsw_reg_mcc_update_handle_set(payload, update_handle); 10581 mlxsw_reg_mcc_component_size_set(payload, component_size); 10582 } 10583 10584 static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle, 10585 u8 *p_error_code, u8 *p_control_state) 10586 { 10587 if (p_update_handle) 10588 *p_update_handle = mlxsw_reg_mcc_update_handle_get(payload); 10589 if (p_error_code) 10590 *p_error_code = mlxsw_reg_mcc_error_code_get(payload); 10591 if (p_control_state) 10592 *p_control_state = mlxsw_reg_mcc_control_state_get(payload); 10593 } 10594 10595 /* MCDA - Management Component Data Access 10596 * --------------------------------------- 10597 * This register allows reading and writing a firmware component. 10598 */ 10599 #define MLXSW_REG_MCDA_ID 0x9063 10600 #define MLXSW_REG_MCDA_BASE_LEN 0x10 10601 #define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80 10602 #define MLXSW_REG_MCDA_LEN \ 10603 (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN) 10604 10605 MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN); 10606 10607 /* reg_mcda_update_handle 10608 * Token representing the current flow executed by the FSM. 10609 * Access: RW 10610 */ 10611 MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24); 10612 10613 /* reg_mcda_offset 10614 * Offset of accessed address relative to component start. Accesses must be in 10615 * accordance to log_mcda_word_size in MCQI reg. 10616 * Access: RW 10617 */ 10618 MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32); 10619 10620 /* reg_mcda_size 10621 * Size of the data accessed, given in bytes. 10622 * Access: RW 10623 */ 10624 MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16); 10625 10626 /* reg_mcda_data 10627 * Data block accessed. 10628 * Access: RW 10629 */ 10630 MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false); 10631 10632 static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle, 10633 u32 offset, u16 size, u8 *data) 10634 { 10635 int i; 10636 10637 MLXSW_REG_ZERO(mcda, payload); 10638 mlxsw_reg_mcda_update_handle_set(payload, update_handle); 10639 mlxsw_reg_mcda_offset_set(payload, offset); 10640 mlxsw_reg_mcda_size_set(payload, size); 10641 10642 for (i = 0; i < size / 4; i++) 10643 mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]); 10644 } 10645 10646 /* MCAM - Management Capabilities Mask Register 10647 * -------------------------------------------- 10648 * Reports the device supported management features. 10649 */ 10650 #define MLXSW_REG_MCAM_ID 0x907F 10651 #define MLXSW_REG_MCAM_LEN 0x48 10652 10653 MLXSW_REG_DEFINE(mcam, MLXSW_REG_MCAM_ID, MLXSW_REG_MCAM_LEN); 10654 10655 enum mlxsw_reg_mcam_feature_group { 10656 /* Enhanced features. */ 10657 MLXSW_REG_MCAM_FEATURE_GROUP_ENHANCED_FEATURES, 10658 }; 10659 10660 /* reg_mcam_feature_group 10661 * Feature list mask index. 10662 * Access: Index 10663 */ 10664 MLXSW_ITEM32(reg, mcam, feature_group, 0x00, 16, 8); 10665 10666 enum mlxsw_reg_mcam_mng_feature_cap_mask_bits { 10667 /* If set, MCIA supports 128 bytes payloads. Otherwise, 48 bytes. */ 10668 MLXSW_REG_MCAM_MCIA_128B = 34, 10669 /* If set, MRSR.command=6 is supported. */ 10670 MLXSW_REG_MCAM_PCI_RESET = 48, 10671 }; 10672 10673 #define MLXSW_REG_BYTES_PER_DWORD 0x4 10674 10675 /* reg_mcam_mng_feature_cap_mask 10676 * Supported port's enhanced features. 10677 * Based on feature_group index. 10678 * When bit is set, the feature is supported in the device. 10679 * Access: RO 10680 */ 10681 #define MLXSW_REG_MCAM_MNG_FEATURE_CAP_MASK_DWORD(_dw_num, _offset) \ 10682 MLXSW_ITEM_BIT_ARRAY(reg, mcam, mng_feature_cap_mask_dw##_dw_num, \ 10683 _offset, MLXSW_REG_BYTES_PER_DWORD, 1) 10684 10685 /* The access to the bits in the field 'mng_feature_cap_mask' is not same to 10686 * other mask fields in other registers. In most of the cases bit #0 is the 10687 * first one in the last dword. In MCAM register, the first dword contains bits 10688 * #0-#31 and so on, so the access to the bits is simpler using bit array per 10689 * dword. Declare each dword of 'mng_feature_cap_mask' field separately. 10690 */ 10691 MLXSW_REG_MCAM_MNG_FEATURE_CAP_MASK_DWORD(0, 0x28); 10692 MLXSW_REG_MCAM_MNG_FEATURE_CAP_MASK_DWORD(1, 0x2C); 10693 MLXSW_REG_MCAM_MNG_FEATURE_CAP_MASK_DWORD(2, 0x30); 10694 MLXSW_REG_MCAM_MNG_FEATURE_CAP_MASK_DWORD(3, 0x34); 10695 10696 static inline void 10697 mlxsw_reg_mcam_pack(char *payload, enum mlxsw_reg_mcam_feature_group feat_group) 10698 { 10699 MLXSW_REG_ZERO(mcam, payload); 10700 mlxsw_reg_mcam_feature_group_set(payload, feat_group); 10701 } 10702 10703 static inline void 10704 mlxsw_reg_mcam_unpack(char *payload, 10705 enum mlxsw_reg_mcam_mng_feature_cap_mask_bits bit, 10706 bool *p_mng_feature_cap_val) 10707 { 10708 int offset = bit % (MLXSW_REG_BYTES_PER_DWORD * BITS_PER_BYTE); 10709 int dword = bit / (MLXSW_REG_BYTES_PER_DWORD * BITS_PER_BYTE); 10710 u8 (*getters[])(const char *, u16) = { 10711 mlxsw_reg_mcam_mng_feature_cap_mask_dw0_get, 10712 mlxsw_reg_mcam_mng_feature_cap_mask_dw1_get, 10713 mlxsw_reg_mcam_mng_feature_cap_mask_dw2_get, 10714 mlxsw_reg_mcam_mng_feature_cap_mask_dw3_get, 10715 }; 10716 10717 if (!WARN_ON_ONCE(dword >= ARRAY_SIZE(getters))) 10718 *p_mng_feature_cap_val = getters[dword](payload, offset); 10719 } 10720 10721 /* MPSC - Monitoring Packet Sampling Configuration Register 10722 * -------------------------------------------------------- 10723 * MPSC Register is used to configure the Packet Sampling mechanism. 10724 */ 10725 #define MLXSW_REG_MPSC_ID 0x9080 10726 #define MLXSW_REG_MPSC_LEN 0x1C 10727 10728 MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN); 10729 10730 /* reg_mpsc_local_port 10731 * Local port number 10732 * Not supported for CPU port 10733 * Access: Index 10734 */ 10735 MLXSW_ITEM32_LP(reg, mpsc, 0x00, 16, 0x00, 12); 10736 10737 /* reg_mpsc_e 10738 * Enable sampling on port local_port 10739 * Access: RW 10740 */ 10741 MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1); 10742 10743 #define MLXSW_REG_MPSC_RATE_MAX 3500000000UL 10744 10745 /* reg_mpsc_rate 10746 * Sampling rate = 1 out of rate packets (with randomization around 10747 * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX 10748 * Access: RW 10749 */ 10750 MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32); 10751 10752 static inline void mlxsw_reg_mpsc_pack(char *payload, u16 local_port, bool e, 10753 u32 rate) 10754 { 10755 MLXSW_REG_ZERO(mpsc, payload); 10756 mlxsw_reg_mpsc_local_port_set(payload, local_port); 10757 mlxsw_reg_mpsc_e_set(payload, e); 10758 mlxsw_reg_mpsc_rate_set(payload, rate); 10759 } 10760 10761 /* MGPC - Monitoring General Purpose Counter Set Register 10762 * The MGPC register retrieves and sets the General Purpose Counter Set. 10763 */ 10764 #define MLXSW_REG_MGPC_ID 0x9081 10765 #define MLXSW_REG_MGPC_LEN 0x18 10766 10767 MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN); 10768 10769 /* reg_mgpc_counter_set_type 10770 * Counter set type. 10771 * Access: OP 10772 */ 10773 MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8); 10774 10775 /* reg_mgpc_counter_index 10776 * Counter index. 10777 * Access: Index 10778 */ 10779 MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24); 10780 10781 enum mlxsw_reg_mgpc_opcode { 10782 /* Nop */ 10783 MLXSW_REG_MGPC_OPCODE_NOP = 0x00, 10784 /* Clear counters */ 10785 MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08, 10786 }; 10787 10788 /* reg_mgpc_opcode 10789 * Opcode. 10790 * Access: OP 10791 */ 10792 MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4); 10793 10794 /* reg_mgpc_byte_counter 10795 * Byte counter value. 10796 * Access: RW 10797 */ 10798 MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64); 10799 10800 /* reg_mgpc_packet_counter 10801 * Packet counter value. 10802 * Access: RW 10803 */ 10804 MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64); 10805 10806 static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index, 10807 enum mlxsw_reg_mgpc_opcode opcode, 10808 enum mlxsw_reg_flow_counter_set_type set_type) 10809 { 10810 MLXSW_REG_ZERO(mgpc, payload); 10811 mlxsw_reg_mgpc_counter_index_set(payload, counter_index); 10812 mlxsw_reg_mgpc_counter_set_type_set(payload, set_type); 10813 mlxsw_reg_mgpc_opcode_set(payload, opcode); 10814 } 10815 10816 /* MPRS - Monitoring Parsing State Register 10817 * ---------------------------------------- 10818 * The MPRS register is used for setting up the parsing for hash, 10819 * policy-engine and routing. 10820 */ 10821 #define MLXSW_REG_MPRS_ID 0x9083 10822 #define MLXSW_REG_MPRS_LEN 0x14 10823 10824 MLXSW_REG_DEFINE(mprs, MLXSW_REG_MPRS_ID, MLXSW_REG_MPRS_LEN); 10825 10826 /* reg_mprs_parsing_depth 10827 * Minimum parsing depth. 10828 * Need to enlarge parsing depth according to L3, MPLS, tunnels, ACL 10829 * rules, traps, hash, etc. Default is 96 bytes. Reserved when SwitchX-2. 10830 * Access: RW 10831 */ 10832 MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16); 10833 10834 /* reg_mprs_parsing_en 10835 * Parsing enable. 10836 * Bit 0 - Enable parsing of NVE of types VxLAN, VxLAN-GPE, GENEVE and 10837 * NVGRE. Default is enabled. Reserved when SwitchX-2. 10838 * Access: RW 10839 */ 10840 MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16); 10841 10842 /* reg_mprs_vxlan_udp_dport 10843 * VxLAN UDP destination port. 10844 * Used for identifying VxLAN packets and for dport field in 10845 * encapsulation. Default is 4789. 10846 * Access: RW 10847 */ 10848 MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16); 10849 10850 static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth, 10851 u16 vxlan_udp_dport) 10852 { 10853 MLXSW_REG_ZERO(mprs, payload); 10854 mlxsw_reg_mprs_parsing_depth_set(payload, parsing_depth); 10855 mlxsw_reg_mprs_parsing_en_set(payload, true); 10856 mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport); 10857 } 10858 10859 /* MOGCR - Monitoring Global Configuration Register 10860 * ------------------------------------------------ 10861 */ 10862 #define MLXSW_REG_MOGCR_ID 0x9086 10863 #define MLXSW_REG_MOGCR_LEN 0x20 10864 10865 MLXSW_REG_DEFINE(mogcr, MLXSW_REG_MOGCR_ID, MLXSW_REG_MOGCR_LEN); 10866 10867 /* reg_mogcr_ptp_iftc 10868 * PTP Ingress FIFO Trap Clear 10869 * The PTP_ING_FIFO trap provides MTPPTR with clr according 10870 * to this value. Default 0. 10871 * Reserved when IB switches and when SwitchX/-2, Spectrum-2 10872 * Access: RW 10873 */ 10874 MLXSW_ITEM32(reg, mogcr, ptp_iftc, 0x00, 1, 1); 10875 10876 /* reg_mogcr_ptp_eftc 10877 * PTP Egress FIFO Trap Clear 10878 * The PTP_EGR_FIFO trap provides MTPPTR with clr according 10879 * to this value. Default 0. 10880 * Reserved when IB switches and when SwitchX/-2, Spectrum-2 10881 * Access: RW 10882 */ 10883 MLXSW_ITEM32(reg, mogcr, ptp_eftc, 0x00, 0, 1); 10884 10885 /* reg_mogcr_mirroring_pid_base 10886 * Base policer id for mirroring policers. 10887 * Must have an even value (e.g. 1000, not 1001). 10888 * Reserved when SwitchX/-2, Switch-IB/2, Spectrum-1 and Quantum. 10889 * Access: RW 10890 */ 10891 MLXSW_ITEM32(reg, mogcr, mirroring_pid_base, 0x0C, 0, 14); 10892 10893 /* MPAGR - Monitoring Port Analyzer Global Register 10894 * ------------------------------------------------ 10895 * This register is used for global port analyzer configurations. 10896 * Note: This register is not supported by current FW versions for Spectrum-1. 10897 */ 10898 #define MLXSW_REG_MPAGR_ID 0x9089 10899 #define MLXSW_REG_MPAGR_LEN 0x0C 10900 10901 MLXSW_REG_DEFINE(mpagr, MLXSW_REG_MPAGR_ID, MLXSW_REG_MPAGR_LEN); 10902 10903 enum mlxsw_reg_mpagr_trigger { 10904 MLXSW_REG_MPAGR_TRIGGER_EGRESS, 10905 MLXSW_REG_MPAGR_TRIGGER_INGRESS, 10906 MLXSW_REG_MPAGR_TRIGGER_INGRESS_WRED, 10907 MLXSW_REG_MPAGR_TRIGGER_INGRESS_SHARED_BUFFER, 10908 MLXSW_REG_MPAGR_TRIGGER_INGRESS_ING_CONG, 10909 MLXSW_REG_MPAGR_TRIGGER_INGRESS_EGR_CONG, 10910 MLXSW_REG_MPAGR_TRIGGER_EGRESS_ECN, 10911 MLXSW_REG_MPAGR_TRIGGER_EGRESS_HIGH_LATENCY, 10912 }; 10913 10914 /* reg_mpagr_trigger 10915 * Mirror trigger. 10916 * Access: Index 10917 */ 10918 MLXSW_ITEM32(reg, mpagr, trigger, 0x00, 0, 4); 10919 10920 /* reg_mpagr_pa_id 10921 * Port analyzer ID. 10922 * Access: RW 10923 */ 10924 MLXSW_ITEM32(reg, mpagr, pa_id, 0x04, 0, 4); 10925 10926 #define MLXSW_REG_MPAGR_RATE_MAX 3500000000UL 10927 10928 /* reg_mpagr_probability_rate 10929 * Sampling rate. 10930 * Valid values are: 1 to 3.5*10^9 10931 * Value of 1 means "sample all". Default is 1. 10932 * Access: RW 10933 */ 10934 MLXSW_ITEM32(reg, mpagr, probability_rate, 0x08, 0, 32); 10935 10936 static inline void mlxsw_reg_mpagr_pack(char *payload, 10937 enum mlxsw_reg_mpagr_trigger trigger, 10938 u8 pa_id, u32 probability_rate) 10939 { 10940 MLXSW_REG_ZERO(mpagr, payload); 10941 mlxsw_reg_mpagr_trigger_set(payload, trigger); 10942 mlxsw_reg_mpagr_pa_id_set(payload, pa_id); 10943 mlxsw_reg_mpagr_probability_rate_set(payload, probability_rate); 10944 } 10945 10946 /* MOMTE - Monitoring Mirror Trigger Enable Register 10947 * ------------------------------------------------- 10948 * This register is used to configure the mirror enable for different mirror 10949 * reasons. 10950 */ 10951 #define MLXSW_REG_MOMTE_ID 0x908D 10952 #define MLXSW_REG_MOMTE_LEN 0x10 10953 10954 MLXSW_REG_DEFINE(momte, MLXSW_REG_MOMTE_ID, MLXSW_REG_MOMTE_LEN); 10955 10956 /* reg_momte_local_port 10957 * Local port number. 10958 * Access: Index 10959 */ 10960 MLXSW_ITEM32_LP(reg, momte, 0x00, 16, 0x00, 12); 10961 10962 enum mlxsw_reg_momte_type { 10963 MLXSW_REG_MOMTE_TYPE_WRED = 0x20, 10964 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS = 0x31, 10965 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS_DESCRIPTORS = 0x32, 10966 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_EGRESS_PORT = 0x33, 10967 MLXSW_REG_MOMTE_TYPE_ING_CONG = 0x40, 10968 MLXSW_REG_MOMTE_TYPE_EGR_CONG = 0x50, 10969 MLXSW_REG_MOMTE_TYPE_ECN = 0x60, 10970 MLXSW_REG_MOMTE_TYPE_HIGH_LATENCY = 0x70, 10971 }; 10972 10973 /* reg_momte_type 10974 * Type of mirroring. 10975 * Access: Index 10976 */ 10977 MLXSW_ITEM32(reg, momte, type, 0x04, 0, 8); 10978 10979 /* reg_momte_tclass_en 10980 * TClass/PG mirror enable. Each bit represents corresponding tclass. 10981 * 0: disable (default) 10982 * 1: enable 10983 * Access: RW 10984 */ 10985 MLXSW_ITEM_BIT_ARRAY(reg, momte, tclass_en, 0x08, 0x08, 1); 10986 10987 static inline void mlxsw_reg_momte_pack(char *payload, u16 local_port, 10988 enum mlxsw_reg_momte_type type) 10989 { 10990 MLXSW_REG_ZERO(momte, payload); 10991 mlxsw_reg_momte_local_port_set(payload, local_port); 10992 mlxsw_reg_momte_type_set(payload, type); 10993 } 10994 10995 /* MTPPPC - Time Precision Packet Port Configuration 10996 * ------------------------------------------------- 10997 * This register serves for configuration of which PTP messages should be 10998 * timestamped. This is a global configuration, despite the register name. 10999 * 11000 * Reserved when Spectrum-2. 11001 */ 11002 #define MLXSW_REG_MTPPPC_ID 0x9090 11003 #define MLXSW_REG_MTPPPC_LEN 0x28 11004 11005 MLXSW_REG_DEFINE(mtpppc, MLXSW_REG_MTPPPC_ID, MLXSW_REG_MTPPPC_LEN); 11006 11007 /* reg_mtpppc_ing_timestamp_message_type 11008 * Bitwise vector of PTP message types to timestamp at ingress. 11009 * MessageType field as defined by IEEE 1588 11010 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req) 11011 * Default all 0 11012 * Access: RW 11013 */ 11014 MLXSW_ITEM32(reg, mtpppc, ing_timestamp_message_type, 0x08, 0, 16); 11015 11016 /* reg_mtpppc_egr_timestamp_message_type 11017 * Bitwise vector of PTP message types to timestamp at egress. 11018 * MessageType field as defined by IEEE 1588 11019 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req) 11020 * Default all 0 11021 * Access: RW 11022 */ 11023 MLXSW_ITEM32(reg, mtpppc, egr_timestamp_message_type, 0x0C, 0, 16); 11024 11025 static inline void mlxsw_reg_mtpppc_pack(char *payload, u16 ing, u16 egr) 11026 { 11027 MLXSW_REG_ZERO(mtpppc, payload); 11028 mlxsw_reg_mtpppc_ing_timestamp_message_type_set(payload, ing); 11029 mlxsw_reg_mtpppc_egr_timestamp_message_type_set(payload, egr); 11030 } 11031 11032 /* MTPPTR - Time Precision Packet Timestamping Reading 11033 * --------------------------------------------------- 11034 * The MTPPTR is used for reading the per port PTP timestamp FIFO. 11035 * There is a trap for packets which are latched to the timestamp FIFO, thus the 11036 * SW knows which FIFO to read. Note that packets enter the FIFO before been 11037 * trapped. The sequence number is used to synchronize the timestamp FIFO 11038 * entries and the trapped packets. 11039 * Reserved when Spectrum-2. 11040 */ 11041 11042 #define MLXSW_REG_MTPPTR_ID 0x9091 11043 #define MLXSW_REG_MTPPTR_BASE_LEN 0x10 /* base length, without records */ 11044 #define MLXSW_REG_MTPPTR_REC_LEN 0x10 /* record length */ 11045 #define MLXSW_REG_MTPPTR_REC_MAX_COUNT 4 11046 #define MLXSW_REG_MTPPTR_LEN (MLXSW_REG_MTPPTR_BASE_LEN + \ 11047 MLXSW_REG_MTPPTR_REC_LEN * MLXSW_REG_MTPPTR_REC_MAX_COUNT) 11048 11049 MLXSW_REG_DEFINE(mtpptr, MLXSW_REG_MTPPTR_ID, MLXSW_REG_MTPPTR_LEN); 11050 11051 /* reg_mtpptr_local_port 11052 * Not supported for CPU port. 11053 * Access: Index 11054 */ 11055 MLXSW_ITEM32_LP(reg, mtpptr, 0x00, 16, 0x00, 12); 11056 11057 enum mlxsw_reg_mtpptr_dir { 11058 MLXSW_REG_MTPPTR_DIR_INGRESS, 11059 MLXSW_REG_MTPPTR_DIR_EGRESS, 11060 }; 11061 11062 /* reg_mtpptr_dir 11063 * Direction. 11064 * Access: Index 11065 */ 11066 MLXSW_ITEM32(reg, mtpptr, dir, 0x00, 0, 1); 11067 11068 /* reg_mtpptr_clr 11069 * Clear the records. 11070 * Access: OP 11071 */ 11072 MLXSW_ITEM32(reg, mtpptr, clr, 0x04, 31, 1); 11073 11074 /* reg_mtpptr_num_rec 11075 * Number of valid records in the response 11076 * Range 0.. cap_ptp_timestamp_fifo 11077 * Access: RO 11078 */ 11079 MLXSW_ITEM32(reg, mtpptr, num_rec, 0x08, 0, 4); 11080 11081 /* reg_mtpptr_rec_message_type 11082 * MessageType field as defined by IEEE 1588 Each bit corresponds to a value 11083 * (e.g. Bit0: Sync, Bit1: Delay_Req) 11084 * Access: RO 11085 */ 11086 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_message_type, 11087 MLXSW_REG_MTPPTR_BASE_LEN, 8, 4, 11088 MLXSW_REG_MTPPTR_REC_LEN, 0, false); 11089 11090 /* reg_mtpptr_rec_domain_number 11091 * DomainNumber field as defined by IEEE 1588 11092 * Access: RO 11093 */ 11094 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_domain_number, 11095 MLXSW_REG_MTPPTR_BASE_LEN, 0, 8, 11096 MLXSW_REG_MTPPTR_REC_LEN, 0, false); 11097 11098 /* reg_mtpptr_rec_sequence_id 11099 * SequenceId field as defined by IEEE 1588 11100 * Access: RO 11101 */ 11102 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_sequence_id, 11103 MLXSW_REG_MTPPTR_BASE_LEN, 0, 16, 11104 MLXSW_REG_MTPPTR_REC_LEN, 0x4, false); 11105 11106 /* reg_mtpptr_rec_timestamp_high 11107 * Timestamp of when the PTP packet has passed through the port Units of PLL 11108 * clock time. 11109 * For Spectrum-1 the PLL clock is 156.25Mhz and PLL clock time is 6.4nSec. 11110 * Access: RO 11111 */ 11112 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_high, 11113 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32, 11114 MLXSW_REG_MTPPTR_REC_LEN, 0x8, false); 11115 11116 /* reg_mtpptr_rec_timestamp_low 11117 * See rec_timestamp_high. 11118 * Access: RO 11119 */ 11120 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_low, 11121 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32, 11122 MLXSW_REG_MTPPTR_REC_LEN, 0xC, false); 11123 11124 static inline void mlxsw_reg_mtpptr_unpack(const char *payload, 11125 unsigned int rec, 11126 u8 *p_message_type, 11127 u8 *p_domain_number, 11128 u16 *p_sequence_id, 11129 u64 *p_timestamp) 11130 { 11131 u32 timestamp_high, timestamp_low; 11132 11133 *p_message_type = mlxsw_reg_mtpptr_rec_message_type_get(payload, rec); 11134 *p_domain_number = mlxsw_reg_mtpptr_rec_domain_number_get(payload, rec); 11135 *p_sequence_id = mlxsw_reg_mtpptr_rec_sequence_id_get(payload, rec); 11136 timestamp_high = mlxsw_reg_mtpptr_rec_timestamp_high_get(payload, rec); 11137 timestamp_low = mlxsw_reg_mtpptr_rec_timestamp_low_get(payload, rec); 11138 *p_timestamp = (u64)timestamp_high << 32 | timestamp_low; 11139 } 11140 11141 /* MTPTPT - Monitoring Precision Time Protocol Trap Register 11142 * --------------------------------------------------------- 11143 * This register is used for configuring under which trap to deliver PTP 11144 * packets depending on type of the packet. 11145 */ 11146 #define MLXSW_REG_MTPTPT_ID 0x9092 11147 #define MLXSW_REG_MTPTPT_LEN 0x08 11148 11149 MLXSW_REG_DEFINE(mtptpt, MLXSW_REG_MTPTPT_ID, MLXSW_REG_MTPTPT_LEN); 11150 11151 enum mlxsw_reg_mtptpt_trap_id { 11152 MLXSW_REG_MTPTPT_TRAP_ID_PTP0, 11153 MLXSW_REG_MTPTPT_TRAP_ID_PTP1, 11154 }; 11155 11156 /* reg_mtptpt_trap_id 11157 * Trap id. 11158 * Access: Index 11159 */ 11160 MLXSW_ITEM32(reg, mtptpt, trap_id, 0x00, 0, 4); 11161 11162 /* reg_mtptpt_message_type 11163 * Bitwise vector of PTP message types to trap. This is a necessary but 11164 * non-sufficient condition since need to enable also per port. See MTPPPC. 11165 * Message types are defined by IEEE 1588 Each bit corresponds to a value (e.g. 11166 * Bit0: Sync, Bit1: Delay_Req) 11167 */ 11168 MLXSW_ITEM32(reg, mtptpt, message_type, 0x04, 0, 16); 11169 11170 static inline void mlxsw_reg_mtptpt_pack(char *payload, 11171 enum mlxsw_reg_mtptpt_trap_id trap_id, 11172 u16 message_type) 11173 { 11174 MLXSW_REG_ZERO(mtptpt, payload); 11175 mlxsw_reg_mtptpt_trap_id_set(payload, trap_id); 11176 mlxsw_reg_mtptpt_message_type_set(payload, message_type); 11177 } 11178 11179 /* MTPCPC - Monitoring Time Precision Correction Port Configuration Register 11180 * ------------------------------------------------------------------------- 11181 */ 11182 #define MLXSW_REG_MTPCPC_ID 0x9093 11183 #define MLXSW_REG_MTPCPC_LEN 0x2C 11184 11185 MLXSW_REG_DEFINE(mtpcpc, MLXSW_REG_MTPCPC_ID, MLXSW_REG_MTPCPC_LEN); 11186 11187 /* reg_mtpcpc_pport 11188 * Per port: 11189 * 0: config is global. When reading - the local_port is 1. 11190 * 1: config is per port. 11191 * Access: Index 11192 */ 11193 MLXSW_ITEM32(reg, mtpcpc, pport, 0x00, 31, 1); 11194 11195 /* reg_mtpcpc_local_port 11196 * Local port number. 11197 * Supported to/from CPU port. 11198 * Reserved when pport = 0. 11199 * Access: Index 11200 */ 11201 MLXSW_ITEM32_LP(reg, mtpcpc, 0x00, 16, 0x00, 12); 11202 11203 /* reg_mtpcpc_ptp_trap_en 11204 * Enable PTP traps. 11205 * The trap_id is configured by MTPTPT. 11206 * Access: RW 11207 */ 11208 MLXSW_ITEM32(reg, mtpcpc, ptp_trap_en, 0x04, 0, 1); 11209 11210 /* reg_mtpcpc_ing_correction_message_type 11211 * Bitwise vector of PTP message types to update correction-field at ingress. 11212 * MessageType field as defined by IEEE 1588 Each bit corresponds to a value 11213 * (e.g. Bit0: Sync, Bit1: Delay_Req). Supported also from CPU port. 11214 * Default all 0 11215 * Access: RW 11216 */ 11217 MLXSW_ITEM32(reg, mtpcpc, ing_correction_message_type, 0x10, 0, 16); 11218 11219 /* reg_mtpcpc_egr_correction_message_type 11220 * Bitwise vector of PTP message types to update correction-field at egress. 11221 * MessageType field as defined by IEEE 1588 Each bit corresponds to a value 11222 * (e.g. Bit0: Sync, Bit1: Delay_Req). Supported also from CPU port. 11223 * Default all 0 11224 * Access: RW 11225 */ 11226 MLXSW_ITEM32(reg, mtpcpc, egr_correction_message_type, 0x14, 0, 16); 11227 11228 static inline void mlxsw_reg_mtpcpc_pack(char *payload, bool pport, 11229 u16 local_port, bool ptp_trap_en, 11230 u16 ing, u16 egr) 11231 { 11232 MLXSW_REG_ZERO(mtpcpc, payload); 11233 mlxsw_reg_mtpcpc_pport_set(payload, pport); 11234 mlxsw_reg_mtpcpc_local_port_set(payload, pport ? local_port : 0); 11235 mlxsw_reg_mtpcpc_ptp_trap_en_set(payload, ptp_trap_en); 11236 mlxsw_reg_mtpcpc_ing_correction_message_type_set(payload, ing); 11237 mlxsw_reg_mtpcpc_egr_correction_message_type_set(payload, egr); 11238 } 11239 11240 /* MFGD - Monitoring FW General Debug Register 11241 * ------------------------------------------- 11242 */ 11243 #define MLXSW_REG_MFGD_ID 0x90F0 11244 #define MLXSW_REG_MFGD_LEN 0x0C 11245 11246 MLXSW_REG_DEFINE(mfgd, MLXSW_REG_MFGD_ID, MLXSW_REG_MFGD_LEN); 11247 11248 /* reg_mfgd_fw_fatal_event_mode 11249 * 0 - don't check FW fatal (default) 11250 * 1 - check FW fatal - enable MFDE trap 11251 * Access: RW 11252 */ 11253 MLXSW_ITEM32(reg, mfgd, fatal_event_mode, 0x00, 9, 2); 11254 11255 /* reg_mfgd_trigger_test 11256 * Access: WO 11257 */ 11258 MLXSW_ITEM32(reg, mfgd, trigger_test, 0x00, 11, 1); 11259 11260 /* MGPIR - Management General Peripheral Information Register 11261 * ---------------------------------------------------------- 11262 * MGPIR register allows software to query the hardware and 11263 * firmware general information of peripheral entities. 11264 */ 11265 #define MLXSW_REG_MGPIR_ID 0x9100 11266 #define MLXSW_REG_MGPIR_LEN 0xA0 11267 11268 MLXSW_REG_DEFINE(mgpir, MLXSW_REG_MGPIR_ID, MLXSW_REG_MGPIR_LEN); 11269 11270 enum mlxsw_reg_mgpir_device_type { 11271 MLXSW_REG_MGPIR_DEVICE_TYPE_NONE, 11272 MLXSW_REG_MGPIR_DEVICE_TYPE_GEARBOX_DIE, 11273 }; 11274 11275 /* mgpir_slot_index 11276 * Slot index (0: Main board). 11277 * Access: Index 11278 */ 11279 MLXSW_ITEM32(reg, mgpir, slot_index, 0x00, 28, 4); 11280 11281 /* mgpir_device_type 11282 * Access: RO 11283 */ 11284 MLXSW_ITEM32(reg, mgpir, device_type, 0x00, 24, 4); 11285 11286 /* mgpir_devices_per_flash 11287 * Number of devices of device_type per flash (can be shared by few devices). 11288 * Access: RO 11289 */ 11290 MLXSW_ITEM32(reg, mgpir, devices_per_flash, 0x00, 16, 8); 11291 11292 /* mgpir_num_of_devices 11293 * Number of devices of device_type. 11294 * Access: RO 11295 */ 11296 MLXSW_ITEM32(reg, mgpir, num_of_devices, 0x00, 0, 8); 11297 11298 /* max_modules_per_slot 11299 * Maximum number of modules that can be connected per slot. 11300 * Access: RO 11301 */ 11302 MLXSW_ITEM32(reg, mgpir, max_modules_per_slot, 0x04, 16, 8); 11303 11304 /* mgpir_num_of_slots 11305 * Number of slots in the system. 11306 * Access: RO 11307 */ 11308 MLXSW_ITEM32(reg, mgpir, num_of_slots, 0x04, 8, 8); 11309 11310 /* mgpir_num_of_modules 11311 * Number of modules. 11312 * Access: RO 11313 */ 11314 MLXSW_ITEM32(reg, mgpir, num_of_modules, 0x04, 0, 8); 11315 11316 static inline void mlxsw_reg_mgpir_pack(char *payload, u8 slot_index) 11317 { 11318 MLXSW_REG_ZERO(mgpir, payload); 11319 mlxsw_reg_mgpir_slot_index_set(payload, slot_index); 11320 } 11321 11322 static inline void 11323 mlxsw_reg_mgpir_unpack(char *payload, u8 *num_of_devices, 11324 enum mlxsw_reg_mgpir_device_type *device_type, 11325 u8 *devices_per_flash, u8 *num_of_modules, 11326 u8 *num_of_slots) 11327 { 11328 if (num_of_devices) 11329 *num_of_devices = mlxsw_reg_mgpir_num_of_devices_get(payload); 11330 if (device_type) 11331 *device_type = mlxsw_reg_mgpir_device_type_get(payload); 11332 if (devices_per_flash) 11333 *devices_per_flash = 11334 mlxsw_reg_mgpir_devices_per_flash_get(payload); 11335 if (num_of_modules) 11336 *num_of_modules = mlxsw_reg_mgpir_num_of_modules_get(payload); 11337 if (num_of_slots) 11338 *num_of_slots = mlxsw_reg_mgpir_num_of_slots_get(payload); 11339 } 11340 11341 /* MBCT - Management Binary Code Transfer Register 11342 * ----------------------------------------------- 11343 * This register allows to transfer binary codes from the host to 11344 * the management FW by transferring it by chunks of maximum 1KB. 11345 */ 11346 #define MLXSW_REG_MBCT_ID 0x9120 11347 #define MLXSW_REG_MBCT_LEN 0x420 11348 11349 MLXSW_REG_DEFINE(mbct, MLXSW_REG_MBCT_ID, MLXSW_REG_MBCT_LEN); 11350 11351 /* reg_mbct_slot_index 11352 * Slot index. 0 is reserved. 11353 * Access: Index 11354 */ 11355 MLXSW_ITEM32(reg, mbct, slot_index, 0x00, 0, 4); 11356 11357 /* reg_mbct_data_size 11358 * Actual data field size in bytes for the current data transfer. 11359 * Access: WO 11360 */ 11361 MLXSW_ITEM32(reg, mbct, data_size, 0x04, 0, 11); 11362 11363 enum mlxsw_reg_mbct_op { 11364 MLXSW_REG_MBCT_OP_ERASE_INI_IMAGE = 1, 11365 MLXSW_REG_MBCT_OP_DATA_TRANSFER, /* Download */ 11366 MLXSW_REG_MBCT_OP_ACTIVATE, 11367 MLXSW_REG_MBCT_OP_CLEAR_ERRORS = 6, 11368 MLXSW_REG_MBCT_OP_QUERY_STATUS, 11369 }; 11370 11371 /* reg_mbct_op 11372 * Access: WO 11373 */ 11374 MLXSW_ITEM32(reg, mbct, op, 0x08, 28, 4); 11375 11376 /* reg_mbct_last 11377 * Indicates that the current data field is the last chunk of the INI. 11378 * Access: WO 11379 */ 11380 MLXSW_ITEM32(reg, mbct, last, 0x08, 26, 1); 11381 11382 /* reg_mbct_oee 11383 * Opcode Event Enable. When set a BCTOE event will be sent once the opcode 11384 * was executed and the fsm_state has changed. 11385 * Access: WO 11386 */ 11387 MLXSW_ITEM32(reg, mbct, oee, 0x08, 25, 1); 11388 11389 enum mlxsw_reg_mbct_status { 11390 /* Partial data transfer completed successfully and ready for next 11391 * data transfer. 11392 */ 11393 MLXSW_REG_MBCT_STATUS_PART_DATA = 2, 11394 MLXSW_REG_MBCT_STATUS_LAST_DATA, 11395 MLXSW_REG_MBCT_STATUS_ERASE_COMPLETE, 11396 /* Error - trying to erase INI while it being used. */ 11397 MLXSW_REG_MBCT_STATUS_ERROR_INI_IN_USE, 11398 /* Last data transfer completed, applying magic pattern. */ 11399 MLXSW_REG_MBCT_STATUS_ERASE_FAILED = 7, 11400 MLXSW_REG_MBCT_STATUS_INI_ERROR, 11401 MLXSW_REG_MBCT_STATUS_ACTIVATION_FAILED, 11402 MLXSW_REG_MBCT_STATUS_ILLEGAL_OPERATION = 11, 11403 }; 11404 11405 /* reg_mbct_status 11406 * Status. 11407 * Access: RO 11408 */ 11409 MLXSW_ITEM32(reg, mbct, status, 0x0C, 24, 5); 11410 11411 enum mlxsw_reg_mbct_fsm_state { 11412 MLXSW_REG_MBCT_FSM_STATE_INI_IN_USE = 5, 11413 MLXSW_REG_MBCT_FSM_STATE_ERROR, 11414 }; 11415 11416 /* reg_mbct_fsm_state 11417 * FSM state. 11418 * Access: RO 11419 */ 11420 MLXSW_ITEM32(reg, mbct, fsm_state, 0x0C, 16, 4); 11421 11422 #define MLXSW_REG_MBCT_DATA_LEN 1024 11423 11424 /* reg_mbct_data 11425 * Up to 1KB of data. 11426 * Access: WO 11427 */ 11428 MLXSW_ITEM_BUF(reg, mbct, data, 0x20, MLXSW_REG_MBCT_DATA_LEN); 11429 11430 static inline void mlxsw_reg_mbct_pack(char *payload, u8 slot_index, 11431 enum mlxsw_reg_mbct_op op, bool oee) 11432 { 11433 MLXSW_REG_ZERO(mbct, payload); 11434 mlxsw_reg_mbct_slot_index_set(payload, slot_index); 11435 mlxsw_reg_mbct_op_set(payload, op); 11436 mlxsw_reg_mbct_oee_set(payload, oee); 11437 } 11438 11439 static inline void mlxsw_reg_mbct_dt_pack(char *payload, 11440 u16 data_size, bool last, 11441 const char *data) 11442 { 11443 if (WARN_ON(data_size > MLXSW_REG_MBCT_DATA_LEN)) 11444 return; 11445 mlxsw_reg_mbct_data_size_set(payload, data_size); 11446 mlxsw_reg_mbct_last_set(payload, last); 11447 mlxsw_reg_mbct_data_memcpy_to(payload, data); 11448 } 11449 11450 static inline void 11451 mlxsw_reg_mbct_unpack(const char *payload, u8 *p_slot_index, 11452 enum mlxsw_reg_mbct_status *p_status, 11453 enum mlxsw_reg_mbct_fsm_state *p_fsm_state) 11454 { 11455 if (p_slot_index) 11456 *p_slot_index = mlxsw_reg_mbct_slot_index_get(payload); 11457 *p_status = mlxsw_reg_mbct_status_get(payload); 11458 if (p_fsm_state) 11459 *p_fsm_state = mlxsw_reg_mbct_fsm_state_get(payload); 11460 } 11461 11462 /* MDDT - Management DownStream Device Tunneling Register 11463 * ------------------------------------------------------ 11464 * This register allows to deliver query and request messages (PRM registers, 11465 * commands) to a DownStream device. 11466 */ 11467 #define MLXSW_REG_MDDT_ID 0x9160 11468 #define MLXSW_REG_MDDT_LEN 0x110 11469 11470 MLXSW_REG_DEFINE(mddt, MLXSW_REG_MDDT_ID, MLXSW_REG_MDDT_LEN); 11471 11472 /* reg_mddt_slot_index 11473 * Slot index. 11474 * Access: Index 11475 */ 11476 MLXSW_ITEM32(reg, mddt, slot_index, 0x00, 8, 4); 11477 11478 /* reg_mddt_device_index 11479 * Device index. 11480 * Access: Index 11481 */ 11482 MLXSW_ITEM32(reg, mddt, device_index, 0x00, 0, 8); 11483 11484 /* reg_mddt_read_size 11485 * Read size in D-Words. 11486 * Access: OP 11487 */ 11488 MLXSW_ITEM32(reg, mddt, read_size, 0x04, 24, 8); 11489 11490 /* reg_mddt_write_size 11491 * Write size in D-Words. 11492 * Access: OP 11493 */ 11494 MLXSW_ITEM32(reg, mddt, write_size, 0x04, 16, 8); 11495 11496 enum mlxsw_reg_mddt_status { 11497 MLXSW_REG_MDDT_STATUS_OK, 11498 }; 11499 11500 /* reg_mddt_status 11501 * Return code of the Downstream Device to the register that was sent. 11502 * Access: RO 11503 */ 11504 MLXSW_ITEM32(reg, mddt, status, 0x0C, 24, 8); 11505 11506 enum mlxsw_reg_mddt_method { 11507 MLXSW_REG_MDDT_METHOD_QUERY, 11508 MLXSW_REG_MDDT_METHOD_WRITE, 11509 }; 11510 11511 /* reg_mddt_method 11512 * Access: OP 11513 */ 11514 MLXSW_ITEM32(reg, mddt, method, 0x0C, 22, 2); 11515 11516 /* reg_mddt_register_id 11517 * Access: Index 11518 */ 11519 MLXSW_ITEM32(reg, mddt, register_id, 0x0C, 0, 16); 11520 11521 #define MLXSW_REG_MDDT_PAYLOAD_OFFSET 0x0C 11522 #define MLXSW_REG_MDDT_PRM_REGISTER_HEADER_LEN 4 11523 11524 static inline char *mlxsw_reg_mddt_inner_payload(char *payload) 11525 { 11526 return payload + MLXSW_REG_MDDT_PAYLOAD_OFFSET + 11527 MLXSW_REG_MDDT_PRM_REGISTER_HEADER_LEN; 11528 } 11529 11530 static inline void mlxsw_reg_mddt_pack(char *payload, u8 slot_index, 11531 u8 device_index, 11532 enum mlxsw_reg_mddt_method method, 11533 const struct mlxsw_reg_info *reg, 11534 char **inner_payload) 11535 { 11536 int len = reg->len + MLXSW_REG_MDDT_PRM_REGISTER_HEADER_LEN; 11537 11538 if (WARN_ON(len + MLXSW_REG_MDDT_PAYLOAD_OFFSET > MLXSW_REG_MDDT_LEN)) 11539 len = MLXSW_REG_MDDT_LEN - MLXSW_REG_MDDT_PAYLOAD_OFFSET; 11540 11541 MLXSW_REG_ZERO(mddt, payload); 11542 mlxsw_reg_mddt_slot_index_set(payload, slot_index); 11543 mlxsw_reg_mddt_device_index_set(payload, device_index); 11544 mlxsw_reg_mddt_method_set(payload, method); 11545 mlxsw_reg_mddt_register_id_set(payload, reg->id); 11546 mlxsw_reg_mddt_read_size_set(payload, len / 4); 11547 mlxsw_reg_mddt_write_size_set(payload, len / 4); 11548 *inner_payload = mlxsw_reg_mddt_inner_payload(payload); 11549 } 11550 11551 /* MDDQ - Management DownStream Device Query Register 11552 * -------------------------------------------------- 11553 * This register allows to query the DownStream device properties. The desired 11554 * information is chosen upon the query_type field and is delivered by 32B 11555 * of data blocks. 11556 */ 11557 #define MLXSW_REG_MDDQ_ID 0x9161 11558 #define MLXSW_REG_MDDQ_LEN 0x30 11559 11560 MLXSW_REG_DEFINE(mddq, MLXSW_REG_MDDQ_ID, MLXSW_REG_MDDQ_LEN); 11561 11562 /* reg_mddq_sie 11563 * Slot info event enable. 11564 * When set to '1', each change in the slot_info.provisioned / sr_valid / 11565 * active / ready will generate a DSDSC event. 11566 * Access: RW 11567 */ 11568 MLXSW_ITEM32(reg, mddq, sie, 0x00, 31, 1); 11569 11570 enum mlxsw_reg_mddq_query_type { 11571 MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_INFO = 1, 11572 MLXSW_REG_MDDQ_QUERY_TYPE_DEVICE_INFO, /* If there are no devices 11573 * on the slot, data_valid 11574 * will be '0'. 11575 */ 11576 MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_NAME, 11577 }; 11578 11579 /* reg_mddq_query_type 11580 * Access: Index 11581 */ 11582 MLXSW_ITEM32(reg, mddq, query_type, 0x00, 16, 8); 11583 11584 /* reg_mddq_slot_index 11585 * Slot index. 0 is reserved. 11586 * Access: Index 11587 */ 11588 MLXSW_ITEM32(reg, mddq, slot_index, 0x00, 0, 4); 11589 11590 /* reg_mddq_response_msg_seq 11591 * Response message sequential number. For a specific request, the response 11592 * message sequential number is the following one. In addition, the last 11593 * message should be 0. 11594 * Access: RO 11595 */ 11596 MLXSW_ITEM32(reg, mddq, response_msg_seq, 0x04, 16, 8); 11597 11598 /* reg_mddq_request_msg_seq 11599 * Request message sequential number. 11600 * The first message number should be 0. 11601 * Access: Index 11602 */ 11603 MLXSW_ITEM32(reg, mddq, request_msg_seq, 0x04, 0, 8); 11604 11605 /* reg_mddq_data_valid 11606 * If set, the data in the data field is valid and contain the information 11607 * for the queried index. 11608 * Access: RO 11609 */ 11610 MLXSW_ITEM32(reg, mddq, data_valid, 0x08, 31, 1); 11611 11612 /* reg_mddq_slot_info_provisioned 11613 * If set, the INI file is applied and the card is provisioned. 11614 * Access: RO 11615 */ 11616 MLXSW_ITEM32(reg, mddq, slot_info_provisioned, 0x10, 31, 1); 11617 11618 /* reg_mddq_slot_info_sr_valid 11619 * If set, Shift Register is valid (after being provisioned) and data 11620 * can be sent from the switch ASIC to the line-card CPLD over Shift-Register. 11621 * Access: RO 11622 */ 11623 MLXSW_ITEM32(reg, mddq, slot_info_sr_valid, 0x10, 30, 1); 11624 11625 enum mlxsw_reg_mddq_slot_info_ready { 11626 MLXSW_REG_MDDQ_SLOT_INFO_READY_NOT_READY, 11627 MLXSW_REG_MDDQ_SLOT_INFO_READY_READY, 11628 MLXSW_REG_MDDQ_SLOT_INFO_READY_ERROR, 11629 }; 11630 11631 /* reg_mddq_slot_info_lc_ready 11632 * If set, the LC is powered on, matching the INI version and a new FW 11633 * version can be burnt (if necessary). 11634 * Access: RO 11635 */ 11636 MLXSW_ITEM32(reg, mddq, slot_info_lc_ready, 0x10, 28, 2); 11637 11638 /* reg_mddq_slot_info_active 11639 * If set, the FW has completed the MDDC.device_enable command. 11640 * Access: RO 11641 */ 11642 MLXSW_ITEM32(reg, mddq, slot_info_active, 0x10, 27, 1); 11643 11644 /* reg_mddq_slot_info_hw_revision 11645 * Major user-configured version number of the current INI file. 11646 * Valid only when active or ready are '1'. 11647 * Access: RO 11648 */ 11649 MLXSW_ITEM32(reg, mddq, slot_info_hw_revision, 0x14, 16, 16); 11650 11651 /* reg_mddq_slot_info_ini_file_version 11652 * User-configured version number of the current INI file. 11653 * Valid only when active or lc_ready are '1'. 11654 * Access: RO 11655 */ 11656 MLXSW_ITEM32(reg, mddq, slot_info_ini_file_version, 0x14, 0, 16); 11657 11658 /* reg_mddq_slot_info_card_type 11659 * Access: RO 11660 */ 11661 MLXSW_ITEM32(reg, mddq, slot_info_card_type, 0x18, 0, 8); 11662 11663 static inline void 11664 __mlxsw_reg_mddq_pack(char *payload, u8 slot_index, 11665 enum mlxsw_reg_mddq_query_type query_type) 11666 { 11667 MLXSW_REG_ZERO(mddq, payload); 11668 mlxsw_reg_mddq_slot_index_set(payload, slot_index); 11669 mlxsw_reg_mddq_query_type_set(payload, query_type); 11670 } 11671 11672 static inline void 11673 mlxsw_reg_mddq_slot_info_pack(char *payload, u8 slot_index, bool sie) 11674 { 11675 __mlxsw_reg_mddq_pack(payload, slot_index, 11676 MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_INFO); 11677 mlxsw_reg_mddq_sie_set(payload, sie); 11678 } 11679 11680 static inline void 11681 mlxsw_reg_mddq_slot_info_unpack(const char *payload, u8 *p_slot_index, 11682 bool *p_provisioned, bool *p_sr_valid, 11683 enum mlxsw_reg_mddq_slot_info_ready *p_lc_ready, 11684 bool *p_active, u16 *p_hw_revision, 11685 u16 *p_ini_file_version, 11686 u8 *p_card_type) 11687 { 11688 *p_slot_index = mlxsw_reg_mddq_slot_index_get(payload); 11689 *p_provisioned = mlxsw_reg_mddq_slot_info_provisioned_get(payload); 11690 *p_sr_valid = mlxsw_reg_mddq_slot_info_sr_valid_get(payload); 11691 *p_lc_ready = mlxsw_reg_mddq_slot_info_lc_ready_get(payload); 11692 *p_active = mlxsw_reg_mddq_slot_info_active_get(payload); 11693 *p_hw_revision = mlxsw_reg_mddq_slot_info_hw_revision_get(payload); 11694 *p_ini_file_version = mlxsw_reg_mddq_slot_info_ini_file_version_get(payload); 11695 *p_card_type = mlxsw_reg_mddq_slot_info_card_type_get(payload); 11696 } 11697 11698 /* reg_mddq_device_info_flash_owner 11699 * If set, the device is the flash owner. Otherwise, a shared flash 11700 * is used by this device (another device is the flash owner). 11701 * Access: RO 11702 */ 11703 MLXSW_ITEM32(reg, mddq, device_info_flash_owner, 0x10, 30, 1); 11704 11705 /* reg_mddq_device_info_device_index 11706 * Device index. The first device should number 0. 11707 * Access: RO 11708 */ 11709 MLXSW_ITEM32(reg, mddq, device_info_device_index, 0x10, 0, 8); 11710 11711 /* reg_mddq_device_info_fw_major 11712 * Major FW version number. 11713 * Access: RO 11714 */ 11715 MLXSW_ITEM32(reg, mddq, device_info_fw_major, 0x14, 16, 16); 11716 11717 /* reg_mddq_device_info_fw_minor 11718 * Minor FW version number. 11719 * Access: RO 11720 */ 11721 MLXSW_ITEM32(reg, mddq, device_info_fw_minor, 0x18, 16, 16); 11722 11723 /* reg_mddq_device_info_fw_sub_minor 11724 * Sub-minor FW version number. 11725 * Access: RO 11726 */ 11727 MLXSW_ITEM32(reg, mddq, device_info_fw_sub_minor, 0x18, 0, 16); 11728 11729 static inline void 11730 mlxsw_reg_mddq_device_info_pack(char *payload, u8 slot_index, 11731 u8 request_msg_seq) 11732 { 11733 __mlxsw_reg_mddq_pack(payload, slot_index, 11734 MLXSW_REG_MDDQ_QUERY_TYPE_DEVICE_INFO); 11735 mlxsw_reg_mddq_request_msg_seq_set(payload, request_msg_seq); 11736 } 11737 11738 static inline void 11739 mlxsw_reg_mddq_device_info_unpack(const char *payload, u8 *p_response_msg_seq, 11740 bool *p_data_valid, bool *p_flash_owner, 11741 u8 *p_device_index, u16 *p_fw_major, 11742 u16 *p_fw_minor, u16 *p_fw_sub_minor) 11743 { 11744 *p_response_msg_seq = mlxsw_reg_mddq_response_msg_seq_get(payload); 11745 *p_data_valid = mlxsw_reg_mddq_data_valid_get(payload); 11746 *p_flash_owner = mlxsw_reg_mddq_device_info_flash_owner_get(payload); 11747 *p_device_index = mlxsw_reg_mddq_device_info_device_index_get(payload); 11748 *p_fw_major = mlxsw_reg_mddq_device_info_fw_major_get(payload); 11749 *p_fw_minor = mlxsw_reg_mddq_device_info_fw_minor_get(payload); 11750 *p_fw_sub_minor = mlxsw_reg_mddq_device_info_fw_sub_minor_get(payload); 11751 } 11752 11753 #define MLXSW_REG_MDDQ_SLOT_ASCII_NAME_LEN 20 11754 11755 /* reg_mddq_slot_ascii_name 11756 * Slot's ASCII name. 11757 * Access: RO 11758 */ 11759 MLXSW_ITEM_BUF(reg, mddq, slot_ascii_name, 0x10, 11760 MLXSW_REG_MDDQ_SLOT_ASCII_NAME_LEN); 11761 11762 static inline void 11763 mlxsw_reg_mddq_slot_name_pack(char *payload, u8 slot_index) 11764 { 11765 __mlxsw_reg_mddq_pack(payload, slot_index, 11766 MLXSW_REG_MDDQ_QUERY_TYPE_SLOT_NAME); 11767 } 11768 11769 static inline void 11770 mlxsw_reg_mddq_slot_name_unpack(const char *payload, char *slot_ascii_name) 11771 { 11772 mlxsw_reg_mddq_slot_ascii_name_memcpy_from(payload, slot_ascii_name); 11773 } 11774 11775 /* MDDC - Management DownStream Device Control Register 11776 * ---------------------------------------------------- 11777 * This register allows to control downstream devices and line cards. 11778 */ 11779 #define MLXSW_REG_MDDC_ID 0x9163 11780 #define MLXSW_REG_MDDC_LEN 0x30 11781 11782 MLXSW_REG_DEFINE(mddc, MLXSW_REG_MDDC_ID, MLXSW_REG_MDDC_LEN); 11783 11784 /* reg_mddc_slot_index 11785 * Slot index. 0 is reserved. 11786 * Access: Index 11787 */ 11788 MLXSW_ITEM32(reg, mddc, slot_index, 0x00, 0, 4); 11789 11790 /* reg_mddc_rst 11791 * Reset request. 11792 * Access: OP 11793 */ 11794 MLXSW_ITEM32(reg, mddc, rst, 0x04, 29, 1); 11795 11796 /* reg_mddc_device_enable 11797 * When set, FW is the manager and allowed to program the downstream device. 11798 * Access: RW 11799 */ 11800 MLXSW_ITEM32(reg, mddc, device_enable, 0x04, 28, 1); 11801 11802 static inline void mlxsw_reg_mddc_pack(char *payload, u8 slot_index, bool rst, 11803 bool device_enable) 11804 { 11805 MLXSW_REG_ZERO(mddc, payload); 11806 mlxsw_reg_mddc_slot_index_set(payload, slot_index); 11807 mlxsw_reg_mddc_rst_set(payload, rst); 11808 mlxsw_reg_mddc_device_enable_set(payload, device_enable); 11809 } 11810 11811 /* MFDE - Monitoring FW Debug Register 11812 * ----------------------------------- 11813 */ 11814 #define MLXSW_REG_MFDE_ID 0x9200 11815 #define MLXSW_REG_MFDE_LEN 0x30 11816 11817 MLXSW_REG_DEFINE(mfde, MLXSW_REG_MFDE_ID, MLXSW_REG_MFDE_LEN); 11818 11819 /* reg_mfde_irisc_id 11820 * Which irisc triggered the event 11821 * Access: RO 11822 */ 11823 MLXSW_ITEM32(reg, mfde, irisc_id, 0x00, 24, 8); 11824 11825 enum mlxsw_reg_mfde_severity { 11826 /* Unrecoverable switch behavior */ 11827 MLXSW_REG_MFDE_SEVERITY_FATL = 2, 11828 /* Unexpected state with possible systemic failure */ 11829 MLXSW_REG_MFDE_SEVERITY_NRML = 3, 11830 /* Unexpected state without systemic failure */ 11831 MLXSW_REG_MFDE_SEVERITY_INTR = 5, 11832 }; 11833 11834 /* reg_mfde_severity 11835 * The severity of the event. 11836 * Access: RO 11837 */ 11838 MLXSW_ITEM32(reg, mfde, severity, 0x00, 16, 8); 11839 11840 enum mlxsw_reg_mfde_event_id { 11841 /* CRspace timeout */ 11842 MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO = 1, 11843 /* KVD insertion machine stopped */ 11844 MLXSW_REG_MFDE_EVENT_ID_KVD_IM_STOP, 11845 /* Triggered by MFGD.trigger_test */ 11846 MLXSW_REG_MFDE_EVENT_ID_TEST, 11847 /* Triggered when firmware hits an assert */ 11848 MLXSW_REG_MFDE_EVENT_ID_FW_ASSERT, 11849 /* Fatal error interrupt from hardware */ 11850 MLXSW_REG_MFDE_EVENT_ID_FATAL_CAUSE, 11851 }; 11852 11853 /* reg_mfde_event_id 11854 * Access: RO 11855 */ 11856 MLXSW_ITEM32(reg, mfde, event_id, 0x00, 0, 16); 11857 11858 enum mlxsw_reg_mfde_method { 11859 MLXSW_REG_MFDE_METHOD_QUERY, 11860 MLXSW_REG_MFDE_METHOD_WRITE, 11861 }; 11862 11863 /* reg_mfde_method 11864 * Access: RO 11865 */ 11866 MLXSW_ITEM32(reg, mfde, method, 0x04, 29, 1); 11867 11868 /* reg_mfde_long_process 11869 * Indicates if the command is in long_process mode. 11870 * Access: RO 11871 */ 11872 MLXSW_ITEM32(reg, mfde, long_process, 0x04, 28, 1); 11873 11874 enum mlxsw_reg_mfde_command_type { 11875 MLXSW_REG_MFDE_COMMAND_TYPE_MAD, 11876 MLXSW_REG_MFDE_COMMAND_TYPE_EMAD, 11877 MLXSW_REG_MFDE_COMMAND_TYPE_CMDIF, 11878 }; 11879 11880 /* reg_mfde_command_type 11881 * Access: RO 11882 */ 11883 MLXSW_ITEM32(reg, mfde, command_type, 0x04, 24, 2); 11884 11885 /* reg_mfde_reg_attr_id 11886 * EMAD - register id, MAD - attibute id 11887 * Access: RO 11888 */ 11889 MLXSW_ITEM32(reg, mfde, reg_attr_id, 0x04, 0, 16); 11890 11891 /* reg_mfde_crspace_to_log_address 11892 * crspace address accessed, which resulted in timeout. 11893 * Access: RO 11894 */ 11895 MLXSW_ITEM32(reg, mfde, crspace_to_log_address, 0x10, 0, 32); 11896 11897 /* reg_mfde_crspace_to_oe 11898 * 0 - New event 11899 * 1 - Old event, occurred before MFGD activation. 11900 * Access: RO 11901 */ 11902 MLXSW_ITEM32(reg, mfde, crspace_to_oe, 0x14, 24, 1); 11903 11904 /* reg_mfde_crspace_to_log_id 11905 * Which irisc triggered the timeout. 11906 * Access: RO 11907 */ 11908 MLXSW_ITEM32(reg, mfde, crspace_to_log_id, 0x14, 0, 4); 11909 11910 /* reg_mfde_crspace_to_log_ip 11911 * IP (instruction pointer) that triggered the timeout. 11912 * Access: RO 11913 */ 11914 MLXSW_ITEM64(reg, mfde, crspace_to_log_ip, 0x18, 0, 64); 11915 11916 /* reg_mfde_kvd_im_stop_oe 11917 * 0 - New event 11918 * 1 - Old event, occurred before MFGD activation. 11919 * Access: RO 11920 */ 11921 MLXSW_ITEM32(reg, mfde, kvd_im_stop_oe, 0x10, 24, 1); 11922 11923 /* reg_mfde_kvd_im_stop_pipes_mask 11924 * Bit per kvh pipe. 11925 * Access: RO 11926 */ 11927 MLXSW_ITEM32(reg, mfde, kvd_im_stop_pipes_mask, 0x10, 0, 16); 11928 11929 /* reg_mfde_fw_assert_var0-4 11930 * Variables passed to assert. 11931 * Access: RO 11932 */ 11933 MLXSW_ITEM32(reg, mfde, fw_assert_var0, 0x10, 0, 32); 11934 MLXSW_ITEM32(reg, mfde, fw_assert_var1, 0x14, 0, 32); 11935 MLXSW_ITEM32(reg, mfde, fw_assert_var2, 0x18, 0, 32); 11936 MLXSW_ITEM32(reg, mfde, fw_assert_var3, 0x1C, 0, 32); 11937 MLXSW_ITEM32(reg, mfde, fw_assert_var4, 0x20, 0, 32); 11938 11939 /* reg_mfde_fw_assert_existptr 11940 * The instruction pointer when assert was triggered. 11941 * Access: RO 11942 */ 11943 MLXSW_ITEM32(reg, mfde, fw_assert_existptr, 0x24, 0, 32); 11944 11945 /* reg_mfde_fw_assert_callra 11946 * The return address after triggering assert. 11947 * Access: RO 11948 */ 11949 MLXSW_ITEM32(reg, mfde, fw_assert_callra, 0x28, 0, 32); 11950 11951 /* reg_mfde_fw_assert_oe 11952 * 0 - New event 11953 * 1 - Old event, occurred before MFGD activation. 11954 * Access: RO 11955 */ 11956 MLXSW_ITEM32(reg, mfde, fw_assert_oe, 0x2C, 24, 1); 11957 11958 /* reg_mfde_fw_assert_tile_v 11959 * 0: The assert was from main 11960 * 1: The assert was from a tile 11961 * Access: RO 11962 */ 11963 MLXSW_ITEM32(reg, mfde, fw_assert_tile_v, 0x2C, 23, 1); 11964 11965 /* reg_mfde_fw_assert_tile_index 11966 * When tile_v=1, the tile_index that caused the assert. 11967 * Access: RO 11968 */ 11969 MLXSW_ITEM32(reg, mfde, fw_assert_tile_index, 0x2C, 16, 6); 11970 11971 /* reg_mfde_fw_assert_ext_synd 11972 * A generated one-to-one identifier which is specific per-assert. 11973 * Access: RO 11974 */ 11975 MLXSW_ITEM32(reg, mfde, fw_assert_ext_synd, 0x2C, 0, 16); 11976 11977 /* reg_mfde_fatal_cause_id 11978 * HW interrupt cause id. 11979 * Access: RO 11980 */ 11981 MLXSW_ITEM32(reg, mfde, fatal_cause_id, 0x10, 0, 18); 11982 11983 /* reg_mfde_fatal_cause_tile_v 11984 * 0: The assert was from main 11985 * 1: The assert was from a tile 11986 * Access: RO 11987 */ 11988 MLXSW_ITEM32(reg, mfde, fatal_cause_tile_v, 0x14, 23, 1); 11989 11990 /* reg_mfde_fatal_cause_tile_index 11991 * When tile_v=1, the tile_index that caused the assert. 11992 * Access: RO 11993 */ 11994 MLXSW_ITEM32(reg, mfde, fatal_cause_tile_index, 0x14, 16, 6); 11995 11996 /* TNGCR - Tunneling NVE General Configuration Register 11997 * ---------------------------------------------------- 11998 * The TNGCR register is used for setting up the NVE Tunneling configuration. 11999 */ 12000 #define MLXSW_REG_TNGCR_ID 0xA001 12001 #define MLXSW_REG_TNGCR_LEN 0x44 12002 12003 MLXSW_REG_DEFINE(tngcr, MLXSW_REG_TNGCR_ID, MLXSW_REG_TNGCR_LEN); 12004 12005 enum mlxsw_reg_tngcr_type { 12006 MLXSW_REG_TNGCR_TYPE_VXLAN, 12007 MLXSW_REG_TNGCR_TYPE_VXLAN_GPE, 12008 MLXSW_REG_TNGCR_TYPE_GENEVE, 12009 MLXSW_REG_TNGCR_TYPE_NVGRE, 12010 }; 12011 12012 /* reg_tngcr_type 12013 * Tunnel type for encapsulation and decapsulation. The types are mutually 12014 * exclusive. 12015 * Note: For Spectrum the NVE parsing must be enabled in MPRS. 12016 * Access: RW 12017 */ 12018 MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4); 12019 12020 /* reg_tngcr_nve_valid 12021 * The VTEP is valid. Allows adding FDB entries for tunnel encapsulation. 12022 * Access: RW 12023 */ 12024 MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1); 12025 12026 /* reg_tngcr_nve_ttl_uc 12027 * The TTL for NVE tunnel encapsulation underlay unicast packets. 12028 * Access: RW 12029 */ 12030 MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8); 12031 12032 /* reg_tngcr_nve_ttl_mc 12033 * The TTL for NVE tunnel encapsulation underlay multicast packets. 12034 * Access: RW 12035 */ 12036 MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8); 12037 12038 enum { 12039 /* Do not copy flow label. Calculate flow label using nve_flh. */ 12040 MLXSW_REG_TNGCR_FL_NO_COPY, 12041 /* Copy flow label from inner packet if packet is IPv6 and 12042 * encapsulation is by IPv6. Otherwise, calculate flow label using 12043 * nve_flh. 12044 */ 12045 MLXSW_REG_TNGCR_FL_COPY, 12046 }; 12047 12048 /* reg_tngcr_nve_flc 12049 * For NVE tunnel encapsulation: Flow label copy from inner packet. 12050 * Access: RW 12051 */ 12052 MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1); 12053 12054 enum { 12055 /* Flow label is static. In Spectrum this means '0'. Spectrum-2 12056 * uses {nve_fl_prefix, nve_fl_suffix}. 12057 */ 12058 MLXSW_REG_TNGCR_FL_NO_HASH, 12059 /* 8 LSBs of the flow label are calculated from ECMP hash of the 12060 * inner packet. 12 MSBs are configured by nve_fl_prefix. 12061 */ 12062 MLXSW_REG_TNGCR_FL_HASH, 12063 }; 12064 12065 /* reg_tngcr_nve_flh 12066 * NVE flow label hash. 12067 * Access: RW 12068 */ 12069 MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1); 12070 12071 /* reg_tngcr_nve_fl_prefix 12072 * NVE flow label prefix. Constant 12 MSBs of the flow label. 12073 * Access: RW 12074 */ 12075 MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12); 12076 12077 /* reg_tngcr_nve_fl_suffix 12078 * NVE flow label suffix. Constant 8 LSBs of the flow label. 12079 * Reserved when nve_flh=1 and for Spectrum. 12080 * Access: RW 12081 */ 12082 MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8); 12083 12084 enum { 12085 /* Source UDP port is fixed (default '0') */ 12086 MLXSW_REG_TNGCR_UDP_SPORT_NO_HASH, 12087 /* Source UDP port is calculated based on hash */ 12088 MLXSW_REG_TNGCR_UDP_SPORT_HASH, 12089 }; 12090 12091 /* reg_tngcr_nve_udp_sport_type 12092 * NVE UDP source port type. 12093 * Spectrum uses LAG hash (SLCRv2). Spectrum-2 uses ECMP hash (RECRv2). 12094 * When the source UDP port is calculated based on hash, then the 8 LSBs 12095 * are calculated from hash the 8 MSBs are configured by 12096 * nve_udp_sport_prefix. 12097 * Access: RW 12098 */ 12099 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1); 12100 12101 /* reg_tngcr_nve_udp_sport_prefix 12102 * NVE UDP source port prefix. Constant 8 MSBs of the UDP source port. 12103 * Reserved when NVE type is NVGRE. 12104 * Access: RW 12105 */ 12106 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8); 12107 12108 /* reg_tngcr_nve_group_size_mc 12109 * The amount of sequential linked lists of MC entries. The first linked 12110 * list is configured by SFD.underlay_mc_ptr. 12111 * Valid values: 1, 2, 4, 8, 16, 32, 64 12112 * The linked list are configured by TNUMT. 12113 * The hash is set by LAG hash. 12114 * Access: RW 12115 */ 12116 MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8); 12117 12118 /* reg_tngcr_nve_group_size_flood 12119 * The amount of sequential linked lists of flooding entries. The first 12120 * linked list is configured by SFMR.nve_tunnel_flood_ptr 12121 * Valid values: 1, 2, 4, 8, 16, 32, 64 12122 * The linked list are configured by TNUMT. 12123 * The hash is set by LAG hash. 12124 * Access: RW 12125 */ 12126 MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8); 12127 12128 /* reg_tngcr_learn_enable 12129 * During decapsulation, whether to learn from NVE port. 12130 * Reserved when Spectrum-2. See TNPC. 12131 * Access: RW 12132 */ 12133 MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1); 12134 12135 /* reg_tngcr_underlay_virtual_router 12136 * Underlay virtual router. 12137 * Reserved when Spectrum-2. 12138 * Access: RW 12139 */ 12140 MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16); 12141 12142 /* reg_tngcr_underlay_rif 12143 * Underlay ingress router interface. RIF type should be loopback generic. 12144 * Reserved when Spectrum. 12145 * Access: RW 12146 */ 12147 MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16); 12148 12149 /* reg_tngcr_usipv4 12150 * Underlay source IPv4 address of the NVE. 12151 * Access: RW 12152 */ 12153 MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32); 12154 12155 /* reg_tngcr_usipv6 12156 * Underlay source IPv6 address of the NVE. For Spectrum, must not be 12157 * modified under traffic of NVE tunneling encapsulation. 12158 * Access: RW 12159 */ 12160 MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16); 12161 12162 static inline void mlxsw_reg_tngcr_pack(char *payload, 12163 enum mlxsw_reg_tngcr_type type, 12164 bool valid, u8 ttl) 12165 { 12166 MLXSW_REG_ZERO(tngcr, payload); 12167 mlxsw_reg_tngcr_type_set(payload, type); 12168 mlxsw_reg_tngcr_nve_valid_set(payload, valid); 12169 mlxsw_reg_tngcr_nve_ttl_uc_set(payload, ttl); 12170 mlxsw_reg_tngcr_nve_ttl_mc_set(payload, ttl); 12171 mlxsw_reg_tngcr_nve_flc_set(payload, MLXSW_REG_TNGCR_FL_NO_COPY); 12172 mlxsw_reg_tngcr_nve_flh_set(payload, 0); 12173 mlxsw_reg_tngcr_nve_udp_sport_type_set(payload, 12174 MLXSW_REG_TNGCR_UDP_SPORT_HASH); 12175 mlxsw_reg_tngcr_nve_udp_sport_prefix_set(payload, 0); 12176 mlxsw_reg_tngcr_nve_group_size_mc_set(payload, 1); 12177 mlxsw_reg_tngcr_nve_group_size_flood_set(payload, 1); 12178 } 12179 12180 /* TNUMT - Tunneling NVE Underlay Multicast Table Register 12181 * ------------------------------------------------------- 12182 * The TNUMT register is for building the underlay MC table. It is used 12183 * for MC, flooding and BC traffic into the NVE tunnel. 12184 */ 12185 #define MLXSW_REG_TNUMT_ID 0xA003 12186 #define MLXSW_REG_TNUMT_LEN 0x20 12187 12188 MLXSW_REG_DEFINE(tnumt, MLXSW_REG_TNUMT_ID, MLXSW_REG_TNUMT_LEN); 12189 12190 enum mlxsw_reg_tnumt_record_type { 12191 MLXSW_REG_TNUMT_RECORD_TYPE_IPV4, 12192 MLXSW_REG_TNUMT_RECORD_TYPE_IPV6, 12193 MLXSW_REG_TNUMT_RECORD_TYPE_LABEL, 12194 }; 12195 12196 /* reg_tnumt_record_type 12197 * Record type. 12198 * Access: RW 12199 */ 12200 MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4); 12201 12202 /* reg_tnumt_tunnel_port 12203 * Tunnel port. 12204 * Access: RW 12205 */ 12206 MLXSW_ITEM32(reg, tnumt, tunnel_port, 0x00, 24, 4); 12207 12208 /* reg_tnumt_underlay_mc_ptr 12209 * Index to the underlay multicast table. 12210 * For Spectrum the index is to the KVD linear. 12211 * Access: Index 12212 */ 12213 MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24); 12214 12215 /* reg_tnumt_vnext 12216 * The next_underlay_mc_ptr is valid. 12217 * Access: RW 12218 */ 12219 MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1); 12220 12221 /* reg_tnumt_next_underlay_mc_ptr 12222 * The next index to the underlay multicast table. 12223 * Access: RW 12224 */ 12225 MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24); 12226 12227 /* reg_tnumt_record_size 12228 * Number of IP addresses in the record. 12229 * Range is 1..cap_max_nve_mc_entries_ipv{4,6} 12230 * Access: RW 12231 */ 12232 MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3); 12233 12234 /* reg_tnumt_udip 12235 * The underlay IPv4 addresses. udip[i] is reserved if i >= size 12236 * Access: RW 12237 */ 12238 MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false); 12239 12240 /* reg_tnumt_udip_ptr 12241 * The pointer to the underlay IPv6 addresses. udip_ptr[i] is reserved if 12242 * i >= size. The IPv6 addresses are configured by RIPS. 12243 * Access: RW 12244 */ 12245 MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false); 12246 12247 static inline void mlxsw_reg_tnumt_pack(char *payload, 12248 enum mlxsw_reg_tnumt_record_type type, 12249 enum mlxsw_reg_tunnel_port tport, 12250 u32 underlay_mc_ptr, bool vnext, 12251 u32 next_underlay_mc_ptr, 12252 u8 record_size) 12253 { 12254 MLXSW_REG_ZERO(tnumt, payload); 12255 mlxsw_reg_tnumt_record_type_set(payload, type); 12256 mlxsw_reg_tnumt_tunnel_port_set(payload, tport); 12257 mlxsw_reg_tnumt_underlay_mc_ptr_set(payload, underlay_mc_ptr); 12258 mlxsw_reg_tnumt_vnext_set(payload, vnext); 12259 mlxsw_reg_tnumt_next_underlay_mc_ptr_set(payload, next_underlay_mc_ptr); 12260 mlxsw_reg_tnumt_record_size_set(payload, record_size); 12261 } 12262 12263 /* TNQCR - Tunneling NVE QoS Configuration Register 12264 * ------------------------------------------------ 12265 * The TNQCR register configures how QoS is set in encapsulation into the 12266 * underlay network. 12267 */ 12268 #define MLXSW_REG_TNQCR_ID 0xA010 12269 #define MLXSW_REG_TNQCR_LEN 0x0C 12270 12271 MLXSW_REG_DEFINE(tnqcr, MLXSW_REG_TNQCR_ID, MLXSW_REG_TNQCR_LEN); 12272 12273 /* reg_tnqcr_enc_set_dscp 12274 * For encapsulation: How to set DSCP field: 12275 * 0 - Copy the DSCP from the overlay (inner) IP header to the underlay 12276 * (outer) IP header. If there is no IP header, use TNQDR.dscp 12277 * 1 - Set the DSCP field as TNQDR.dscp 12278 * Access: RW 12279 */ 12280 MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1); 12281 12282 static inline void mlxsw_reg_tnqcr_pack(char *payload) 12283 { 12284 MLXSW_REG_ZERO(tnqcr, payload); 12285 mlxsw_reg_tnqcr_enc_set_dscp_set(payload, 0); 12286 } 12287 12288 /* TNQDR - Tunneling NVE QoS Default Register 12289 * ------------------------------------------ 12290 * The TNQDR register configures the default QoS settings for NVE 12291 * encapsulation. 12292 */ 12293 #define MLXSW_REG_TNQDR_ID 0xA011 12294 #define MLXSW_REG_TNQDR_LEN 0x08 12295 12296 MLXSW_REG_DEFINE(tnqdr, MLXSW_REG_TNQDR_ID, MLXSW_REG_TNQDR_LEN); 12297 12298 /* reg_tnqdr_local_port 12299 * Local port number (receive port). CPU port is supported. 12300 * Access: Index 12301 */ 12302 MLXSW_ITEM32_LP(reg, tnqdr, 0x00, 16, 0x00, 12); 12303 12304 /* reg_tnqdr_dscp 12305 * For encapsulation, the default DSCP. 12306 * Access: RW 12307 */ 12308 MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6); 12309 12310 static inline void mlxsw_reg_tnqdr_pack(char *payload, u16 local_port) 12311 { 12312 MLXSW_REG_ZERO(tnqdr, payload); 12313 mlxsw_reg_tnqdr_local_port_set(payload, local_port); 12314 mlxsw_reg_tnqdr_dscp_set(payload, 0); 12315 } 12316 12317 /* TNEEM - Tunneling NVE Encapsulation ECN Mapping Register 12318 * -------------------------------------------------------- 12319 * The TNEEM register maps ECN of the IP header at the ingress to the 12320 * encapsulation to the ECN of the underlay network. 12321 */ 12322 #define MLXSW_REG_TNEEM_ID 0xA012 12323 #define MLXSW_REG_TNEEM_LEN 0x0C 12324 12325 MLXSW_REG_DEFINE(tneem, MLXSW_REG_TNEEM_ID, MLXSW_REG_TNEEM_LEN); 12326 12327 /* reg_tneem_overlay_ecn 12328 * ECN of the IP header in the overlay network. 12329 * Access: Index 12330 */ 12331 MLXSW_ITEM32(reg, tneem, overlay_ecn, 0x04, 24, 2); 12332 12333 /* reg_tneem_underlay_ecn 12334 * ECN of the IP header in the underlay network. 12335 * Access: RW 12336 */ 12337 MLXSW_ITEM32(reg, tneem, underlay_ecn, 0x04, 16, 2); 12338 12339 static inline void mlxsw_reg_tneem_pack(char *payload, u8 overlay_ecn, 12340 u8 underlay_ecn) 12341 { 12342 MLXSW_REG_ZERO(tneem, payload); 12343 mlxsw_reg_tneem_overlay_ecn_set(payload, overlay_ecn); 12344 mlxsw_reg_tneem_underlay_ecn_set(payload, underlay_ecn); 12345 } 12346 12347 /* TNDEM - Tunneling NVE Decapsulation ECN Mapping Register 12348 * -------------------------------------------------------- 12349 * The TNDEM register configures the actions that are done in the 12350 * decapsulation. 12351 */ 12352 #define MLXSW_REG_TNDEM_ID 0xA013 12353 #define MLXSW_REG_TNDEM_LEN 0x0C 12354 12355 MLXSW_REG_DEFINE(tndem, MLXSW_REG_TNDEM_ID, MLXSW_REG_TNDEM_LEN); 12356 12357 /* reg_tndem_underlay_ecn 12358 * ECN field of the IP header in the underlay network. 12359 * Access: Index 12360 */ 12361 MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2); 12362 12363 /* reg_tndem_overlay_ecn 12364 * ECN field of the IP header in the overlay network. 12365 * Access: Index 12366 */ 12367 MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2); 12368 12369 /* reg_tndem_eip_ecn 12370 * Egress IP ECN. ECN field of the IP header of the packet which goes out 12371 * from the decapsulation. 12372 * Access: RW 12373 */ 12374 MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2); 12375 12376 /* reg_tndem_trap_en 12377 * Trap enable: 12378 * 0 - No trap due to decap ECN 12379 * 1 - Trap enable with trap_id 12380 * Access: RW 12381 */ 12382 MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4); 12383 12384 /* reg_tndem_trap_id 12385 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 12386 * Reserved when trap_en is '0'. 12387 * Access: RW 12388 */ 12389 MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9); 12390 12391 static inline void mlxsw_reg_tndem_pack(char *payload, u8 underlay_ecn, 12392 u8 overlay_ecn, u8 ecn, bool trap_en, 12393 u16 trap_id) 12394 { 12395 MLXSW_REG_ZERO(tndem, payload); 12396 mlxsw_reg_tndem_underlay_ecn_set(payload, underlay_ecn); 12397 mlxsw_reg_tndem_overlay_ecn_set(payload, overlay_ecn); 12398 mlxsw_reg_tndem_eip_ecn_set(payload, ecn); 12399 mlxsw_reg_tndem_trap_en_set(payload, trap_en); 12400 mlxsw_reg_tndem_trap_id_set(payload, trap_id); 12401 } 12402 12403 /* TNPC - Tunnel Port Configuration Register 12404 * ----------------------------------------- 12405 * The TNPC register is used for tunnel port configuration. 12406 * Reserved when Spectrum. 12407 */ 12408 #define MLXSW_REG_TNPC_ID 0xA020 12409 #define MLXSW_REG_TNPC_LEN 0x18 12410 12411 MLXSW_REG_DEFINE(tnpc, MLXSW_REG_TNPC_ID, MLXSW_REG_TNPC_LEN); 12412 12413 /* reg_tnpc_tunnel_port 12414 * Tunnel port. 12415 * Access: Index 12416 */ 12417 MLXSW_ITEM32(reg, tnpc, tunnel_port, 0x00, 0, 4); 12418 12419 /* reg_tnpc_learn_enable_v6 12420 * During IPv6 underlay decapsulation, whether to learn from tunnel port. 12421 * Access: RW 12422 */ 12423 MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1); 12424 12425 /* reg_tnpc_learn_enable_v4 12426 * During IPv4 underlay decapsulation, whether to learn from tunnel port. 12427 * Access: RW 12428 */ 12429 MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1); 12430 12431 static inline void mlxsw_reg_tnpc_pack(char *payload, 12432 enum mlxsw_reg_tunnel_port tport, 12433 bool learn_enable) 12434 { 12435 MLXSW_REG_ZERO(tnpc, payload); 12436 mlxsw_reg_tnpc_tunnel_port_set(payload, tport); 12437 mlxsw_reg_tnpc_learn_enable_v4_set(payload, learn_enable); 12438 mlxsw_reg_tnpc_learn_enable_v6_set(payload, learn_enable); 12439 } 12440 12441 /* TIGCR - Tunneling IPinIP General Configuration Register 12442 * ------------------------------------------------------- 12443 * The TIGCR register is used for setting up the IPinIP Tunnel configuration. 12444 */ 12445 #define MLXSW_REG_TIGCR_ID 0xA801 12446 #define MLXSW_REG_TIGCR_LEN 0x10 12447 12448 MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN); 12449 12450 /* reg_tigcr_ipip_ttlc 12451 * For IPinIP Tunnel encapsulation: whether to copy the ttl from the packet 12452 * header. 12453 * Access: RW 12454 */ 12455 MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1); 12456 12457 /* reg_tigcr_ipip_ttl_uc 12458 * The TTL for IPinIP Tunnel encapsulation of unicast packets if 12459 * reg_tigcr_ipip_ttlc is unset. 12460 * Access: RW 12461 */ 12462 MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8); 12463 12464 static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc) 12465 { 12466 MLXSW_REG_ZERO(tigcr, payload); 12467 mlxsw_reg_tigcr_ttlc_set(payload, ttlc); 12468 mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc); 12469 } 12470 12471 /* TIEEM - Tunneling IPinIP Encapsulation ECN Mapping Register 12472 * ----------------------------------------------------------- 12473 * The TIEEM register maps ECN of the IP header at the ingress to the 12474 * encapsulation to the ECN of the underlay network. 12475 */ 12476 #define MLXSW_REG_TIEEM_ID 0xA812 12477 #define MLXSW_REG_TIEEM_LEN 0x0C 12478 12479 MLXSW_REG_DEFINE(tieem, MLXSW_REG_TIEEM_ID, MLXSW_REG_TIEEM_LEN); 12480 12481 /* reg_tieem_overlay_ecn 12482 * ECN of the IP header in the overlay network. 12483 * Access: Index 12484 */ 12485 MLXSW_ITEM32(reg, tieem, overlay_ecn, 0x04, 24, 2); 12486 12487 /* reg_tineem_underlay_ecn 12488 * ECN of the IP header in the underlay network. 12489 * Access: RW 12490 */ 12491 MLXSW_ITEM32(reg, tieem, underlay_ecn, 0x04, 16, 2); 12492 12493 static inline void mlxsw_reg_tieem_pack(char *payload, u8 overlay_ecn, 12494 u8 underlay_ecn) 12495 { 12496 MLXSW_REG_ZERO(tieem, payload); 12497 mlxsw_reg_tieem_overlay_ecn_set(payload, overlay_ecn); 12498 mlxsw_reg_tieem_underlay_ecn_set(payload, underlay_ecn); 12499 } 12500 12501 /* TIDEM - Tunneling IPinIP Decapsulation ECN Mapping Register 12502 * ----------------------------------------------------------- 12503 * The TIDEM register configures the actions that are done in the 12504 * decapsulation. 12505 */ 12506 #define MLXSW_REG_TIDEM_ID 0xA813 12507 #define MLXSW_REG_TIDEM_LEN 0x0C 12508 12509 MLXSW_REG_DEFINE(tidem, MLXSW_REG_TIDEM_ID, MLXSW_REG_TIDEM_LEN); 12510 12511 /* reg_tidem_underlay_ecn 12512 * ECN field of the IP header in the underlay network. 12513 * Access: Index 12514 */ 12515 MLXSW_ITEM32(reg, tidem, underlay_ecn, 0x04, 24, 2); 12516 12517 /* reg_tidem_overlay_ecn 12518 * ECN field of the IP header in the overlay network. 12519 * Access: Index 12520 */ 12521 MLXSW_ITEM32(reg, tidem, overlay_ecn, 0x04, 16, 2); 12522 12523 /* reg_tidem_eip_ecn 12524 * Egress IP ECN. ECN field of the IP header of the packet which goes out 12525 * from the decapsulation. 12526 * Access: RW 12527 */ 12528 MLXSW_ITEM32(reg, tidem, eip_ecn, 0x04, 8, 2); 12529 12530 /* reg_tidem_trap_en 12531 * Trap enable: 12532 * 0 - No trap due to decap ECN 12533 * 1 - Trap enable with trap_id 12534 * Access: RW 12535 */ 12536 MLXSW_ITEM32(reg, tidem, trap_en, 0x08, 28, 4); 12537 12538 /* reg_tidem_trap_id 12539 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 12540 * Reserved when trap_en is '0'. 12541 * Access: RW 12542 */ 12543 MLXSW_ITEM32(reg, tidem, trap_id, 0x08, 0, 9); 12544 12545 static inline void mlxsw_reg_tidem_pack(char *payload, u8 underlay_ecn, 12546 u8 overlay_ecn, u8 eip_ecn, 12547 bool trap_en, u16 trap_id) 12548 { 12549 MLXSW_REG_ZERO(tidem, payload); 12550 mlxsw_reg_tidem_underlay_ecn_set(payload, underlay_ecn); 12551 mlxsw_reg_tidem_overlay_ecn_set(payload, overlay_ecn); 12552 mlxsw_reg_tidem_eip_ecn_set(payload, eip_ecn); 12553 mlxsw_reg_tidem_trap_en_set(payload, trap_en); 12554 mlxsw_reg_tidem_trap_id_set(payload, trap_id); 12555 } 12556 12557 /* SBPR - Shared Buffer Pools Register 12558 * ----------------------------------- 12559 * The SBPR configures and retrieves the shared buffer pools and configuration. 12560 */ 12561 #define MLXSW_REG_SBPR_ID 0xB001 12562 #define MLXSW_REG_SBPR_LEN 0x14 12563 12564 MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN); 12565 12566 /* reg_sbpr_desc 12567 * When set, configures descriptor buffer. 12568 * Access: Index 12569 */ 12570 MLXSW_ITEM32(reg, sbpr, desc, 0x00, 31, 1); 12571 12572 /* shared direstion enum for SBPR, SBCM, SBPM */ 12573 enum mlxsw_reg_sbxx_dir { 12574 MLXSW_REG_SBXX_DIR_INGRESS, 12575 MLXSW_REG_SBXX_DIR_EGRESS, 12576 }; 12577 12578 /* reg_sbpr_dir 12579 * Direction. 12580 * Access: Index 12581 */ 12582 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2); 12583 12584 /* reg_sbpr_pool 12585 * Pool index. 12586 * Access: Index 12587 */ 12588 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4); 12589 12590 /* reg_sbpr_infi_size 12591 * Size is infinite. 12592 * Access: RW 12593 */ 12594 MLXSW_ITEM32(reg, sbpr, infi_size, 0x04, 31, 1); 12595 12596 /* reg_sbpr_size 12597 * Pool size in buffer cells. 12598 * Reserved when infi_size = 1. 12599 * Access: RW 12600 */ 12601 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24); 12602 12603 enum mlxsw_reg_sbpr_mode { 12604 MLXSW_REG_SBPR_MODE_STATIC, 12605 MLXSW_REG_SBPR_MODE_DYNAMIC, 12606 }; 12607 12608 /* reg_sbpr_mode 12609 * Pool quota calculation mode. 12610 * Access: RW 12611 */ 12612 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4); 12613 12614 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool, 12615 enum mlxsw_reg_sbxx_dir dir, 12616 enum mlxsw_reg_sbpr_mode mode, u32 size, 12617 bool infi_size) 12618 { 12619 MLXSW_REG_ZERO(sbpr, payload); 12620 mlxsw_reg_sbpr_pool_set(payload, pool); 12621 mlxsw_reg_sbpr_dir_set(payload, dir); 12622 mlxsw_reg_sbpr_mode_set(payload, mode); 12623 mlxsw_reg_sbpr_size_set(payload, size); 12624 mlxsw_reg_sbpr_infi_size_set(payload, infi_size); 12625 } 12626 12627 /* SBCM - Shared Buffer Class Management Register 12628 * ---------------------------------------------- 12629 * The SBCM register configures and retrieves the shared buffer allocation 12630 * and configuration according to Port-PG, including the binding to pool 12631 * and definition of the associated quota. 12632 */ 12633 #define MLXSW_REG_SBCM_ID 0xB002 12634 #define MLXSW_REG_SBCM_LEN 0x28 12635 12636 MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN); 12637 12638 /* reg_sbcm_local_port 12639 * Local port number. 12640 * For Ingress: excludes CPU port and Router port 12641 * For Egress: excludes IP Router 12642 * Access: Index 12643 */ 12644 MLXSW_ITEM32_LP(reg, sbcm, 0x00, 16, 0x00, 4); 12645 12646 /* reg_sbcm_pg_buff 12647 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress) 12648 * For PG buffer: range is 0..cap_max_pg_buffers - 1 12649 * For traffic class: range is 0..cap_max_tclass - 1 12650 * Note that when traffic class is in MC aware mode then the traffic 12651 * classes which are MC aware cannot be configured. 12652 * Access: Index 12653 */ 12654 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6); 12655 12656 /* reg_sbcm_dir 12657 * Direction. 12658 * Access: Index 12659 */ 12660 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2); 12661 12662 /* reg_sbcm_min_buff 12663 * Minimum buffer size for the limiter, in cells. 12664 * Access: RW 12665 */ 12666 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24); 12667 12668 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */ 12669 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1 12670 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14 12671 12672 /* reg_sbcm_infi_max 12673 * Max buffer is infinite. 12674 * Access: RW 12675 */ 12676 MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1); 12677 12678 /* reg_sbcm_max_buff 12679 * When the pool associated to the port-pg/tclass is configured to 12680 * static, Maximum buffer size for the limiter configured in cells. 12681 * When the pool associated to the port-pg/tclass is configured to 12682 * dynamic, the max_buff holds the "alpha" parameter, supporting 12683 * the following values: 12684 * 0: 0 12685 * i: (1/128)*2^(i-1), for i=1..14 12686 * 0xFF: Infinity 12687 * Reserved when infi_max = 1. 12688 * Access: RW 12689 */ 12690 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24); 12691 12692 /* reg_sbcm_pool 12693 * Association of the port-priority to a pool. 12694 * Access: RW 12695 */ 12696 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4); 12697 12698 static inline void mlxsw_reg_sbcm_pack(char *payload, u16 local_port, u8 pg_buff, 12699 enum mlxsw_reg_sbxx_dir dir, 12700 u32 min_buff, u32 max_buff, 12701 bool infi_max, u8 pool) 12702 { 12703 MLXSW_REG_ZERO(sbcm, payload); 12704 mlxsw_reg_sbcm_local_port_set(payload, local_port); 12705 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff); 12706 mlxsw_reg_sbcm_dir_set(payload, dir); 12707 mlxsw_reg_sbcm_min_buff_set(payload, min_buff); 12708 mlxsw_reg_sbcm_max_buff_set(payload, max_buff); 12709 mlxsw_reg_sbcm_infi_max_set(payload, infi_max); 12710 mlxsw_reg_sbcm_pool_set(payload, pool); 12711 } 12712 12713 /* SBPM - Shared Buffer Port Management Register 12714 * --------------------------------------------- 12715 * The SBPM register configures and retrieves the shared buffer allocation 12716 * and configuration according to Port-Pool, including the definition 12717 * of the associated quota. 12718 */ 12719 #define MLXSW_REG_SBPM_ID 0xB003 12720 #define MLXSW_REG_SBPM_LEN 0x28 12721 12722 MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN); 12723 12724 /* reg_sbpm_local_port 12725 * Local port number. 12726 * For Ingress: excludes CPU port and Router port 12727 * For Egress: excludes IP Router 12728 * Access: Index 12729 */ 12730 MLXSW_ITEM32_LP(reg, sbpm, 0x00, 16, 0x00, 12); 12731 12732 /* reg_sbpm_pool 12733 * The pool associated to quota counting on the local_port. 12734 * Access: Index 12735 */ 12736 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4); 12737 12738 /* reg_sbpm_dir 12739 * Direction. 12740 * Access: Index 12741 */ 12742 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2); 12743 12744 /* reg_sbpm_buff_occupancy 12745 * Current buffer occupancy in cells. 12746 * Access: RO 12747 */ 12748 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24); 12749 12750 /* reg_sbpm_clr 12751 * Clear Max Buffer Occupancy 12752 * When this bit is set, max_buff_occupancy field is cleared (and a 12753 * new max value is tracked from the time the clear was performed). 12754 * Access: OP 12755 */ 12756 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1); 12757 12758 /* reg_sbpm_max_buff_occupancy 12759 * Maximum value of buffer occupancy in cells monitored. Cleared by 12760 * writing to the clr field. 12761 * Access: RO 12762 */ 12763 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24); 12764 12765 /* reg_sbpm_min_buff 12766 * Minimum buffer size for the limiter, in cells. 12767 * Access: RW 12768 */ 12769 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24); 12770 12771 /* reg_sbpm_max_buff 12772 * When the pool associated to the port-pg/tclass is configured to 12773 * static, Maximum buffer size for the limiter configured in cells. 12774 * When the pool associated to the port-pg/tclass is configured to 12775 * dynamic, the max_buff holds the "alpha" parameter, supporting 12776 * the following values: 12777 * 0: 0 12778 * i: (1/128)*2^(i-1), for i=1..14 12779 * 0xFF: Infinity 12780 * Access: RW 12781 */ 12782 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24); 12783 12784 static inline void mlxsw_reg_sbpm_pack(char *payload, u16 local_port, u8 pool, 12785 enum mlxsw_reg_sbxx_dir dir, bool clr, 12786 u32 min_buff, u32 max_buff) 12787 { 12788 MLXSW_REG_ZERO(sbpm, payload); 12789 mlxsw_reg_sbpm_local_port_set(payload, local_port); 12790 mlxsw_reg_sbpm_pool_set(payload, pool); 12791 mlxsw_reg_sbpm_dir_set(payload, dir); 12792 mlxsw_reg_sbpm_clr_set(payload, clr); 12793 mlxsw_reg_sbpm_min_buff_set(payload, min_buff); 12794 mlxsw_reg_sbpm_max_buff_set(payload, max_buff); 12795 } 12796 12797 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy, 12798 u32 *p_max_buff_occupancy) 12799 { 12800 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload); 12801 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload); 12802 } 12803 12804 /* SBMM - Shared Buffer Multicast Management Register 12805 * -------------------------------------------------- 12806 * The SBMM register configures and retrieves the shared buffer allocation 12807 * and configuration for MC packets according to Switch-Priority, including 12808 * the binding to pool and definition of the associated quota. 12809 */ 12810 #define MLXSW_REG_SBMM_ID 0xB004 12811 #define MLXSW_REG_SBMM_LEN 0x28 12812 12813 MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN); 12814 12815 /* reg_sbmm_prio 12816 * Switch Priority. 12817 * Access: Index 12818 */ 12819 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4); 12820 12821 /* reg_sbmm_min_buff 12822 * Minimum buffer size for the limiter, in cells. 12823 * Access: RW 12824 */ 12825 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24); 12826 12827 /* reg_sbmm_max_buff 12828 * When the pool associated to the port-pg/tclass is configured to 12829 * static, Maximum buffer size for the limiter configured in cells. 12830 * When the pool associated to the port-pg/tclass is configured to 12831 * dynamic, the max_buff holds the "alpha" parameter, supporting 12832 * the following values: 12833 * 0: 0 12834 * i: (1/128)*2^(i-1), for i=1..14 12835 * 0xFF: Infinity 12836 * Access: RW 12837 */ 12838 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24); 12839 12840 /* reg_sbmm_pool 12841 * Association of the port-priority to a pool. 12842 * Access: RW 12843 */ 12844 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4); 12845 12846 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff, 12847 u32 max_buff, u8 pool) 12848 { 12849 MLXSW_REG_ZERO(sbmm, payload); 12850 mlxsw_reg_sbmm_prio_set(payload, prio); 12851 mlxsw_reg_sbmm_min_buff_set(payload, min_buff); 12852 mlxsw_reg_sbmm_max_buff_set(payload, max_buff); 12853 mlxsw_reg_sbmm_pool_set(payload, pool); 12854 } 12855 12856 /* SBSR - Shared Buffer Status Register 12857 * ------------------------------------ 12858 * The SBSR register retrieves the shared buffer occupancy according to 12859 * Port-Pool. Note that this register enables reading a large amount of data. 12860 * It is the user's responsibility to limit the amount of data to ensure the 12861 * response can match the maximum transfer unit. In case the response exceeds 12862 * the maximum transport unit, it will be truncated with no special notice. 12863 */ 12864 #define MLXSW_REG_SBSR_ID 0xB005 12865 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */ 12866 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */ 12867 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120 12868 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \ 12869 MLXSW_REG_SBSR_REC_LEN * \ 12870 MLXSW_REG_SBSR_REC_MAX_COUNT) 12871 12872 MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN); 12873 12874 /* reg_sbsr_clr 12875 * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy 12876 * field is cleared (and a new max value is tracked from the time the clear 12877 * was performed). 12878 * Access: OP 12879 */ 12880 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1); 12881 12882 #define MLXSW_REG_SBSR_NUM_PORTS_IN_PAGE 256 12883 12884 /* reg_sbsr_port_page 12885 * Determines the range of the ports specified in the 'ingress_port_mask' 12886 * and 'egress_port_mask' bit masks. 12887 * {ingress,egress}_port_mask[x] is (256 * port_page) + x 12888 * Access: Index 12889 */ 12890 MLXSW_ITEM32(reg, sbsr, port_page, 0x04, 0, 4); 12891 12892 /* reg_sbsr_ingress_port_mask 12893 * Bit vector for all ingress network ports. 12894 * Indicates which of the ports (for which the relevant bit is set) 12895 * are affected by the set operation. Configuration of any other port 12896 * does not change. 12897 * Access: Index 12898 */ 12899 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1); 12900 12901 /* reg_sbsr_pg_buff_mask 12902 * Bit vector for all switch priority groups. 12903 * Indicates which of the priorities (for which the relevant bit is set) 12904 * are affected by the set operation. Configuration of any other priority 12905 * does not change. 12906 * Range is 0..cap_max_pg_buffers - 1 12907 * Access: Index 12908 */ 12909 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1); 12910 12911 /* reg_sbsr_egress_port_mask 12912 * Bit vector for all egress network ports. 12913 * Indicates which of the ports (for which the relevant bit is set) 12914 * are affected by the set operation. Configuration of any other port 12915 * does not change. 12916 * Access: Index 12917 */ 12918 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1); 12919 12920 /* reg_sbsr_tclass_mask 12921 * Bit vector for all traffic classes. 12922 * Indicates which of the traffic classes (for which the relevant bit is 12923 * set) are affected by the set operation. Configuration of any other 12924 * traffic class does not change. 12925 * Range is 0..cap_max_tclass - 1 12926 * Access: Index 12927 */ 12928 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1); 12929 12930 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr) 12931 { 12932 MLXSW_REG_ZERO(sbsr, payload); 12933 mlxsw_reg_sbsr_clr_set(payload, clr); 12934 } 12935 12936 /* reg_sbsr_rec_buff_occupancy 12937 * Current buffer occupancy in cells. 12938 * Access: RO 12939 */ 12940 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 12941 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false); 12942 12943 /* reg_sbsr_rec_max_buff_occupancy 12944 * Maximum value of buffer occupancy in cells monitored. Cleared by 12945 * writing to the clr field. 12946 * Access: RO 12947 */ 12948 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 12949 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false); 12950 12951 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index, 12952 u32 *p_buff_occupancy, 12953 u32 *p_max_buff_occupancy) 12954 { 12955 *p_buff_occupancy = 12956 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index); 12957 *p_max_buff_occupancy = 12958 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index); 12959 } 12960 12961 /* SBIB - Shared Buffer Internal Buffer Register 12962 * --------------------------------------------- 12963 * The SBIB register configures per port buffers for internal use. The internal 12964 * buffers consume memory on the port buffers (note that the port buffers are 12965 * used also by PBMC). 12966 * 12967 * For Spectrum this is used for egress mirroring. 12968 */ 12969 #define MLXSW_REG_SBIB_ID 0xB006 12970 #define MLXSW_REG_SBIB_LEN 0x10 12971 12972 MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN); 12973 12974 /* reg_sbib_local_port 12975 * Local port number 12976 * Not supported for CPU port and router port 12977 * Access: Index 12978 */ 12979 MLXSW_ITEM32_LP(reg, sbib, 0x00, 16, 0x00, 12); 12980 12981 /* reg_sbib_buff_size 12982 * Units represented in cells 12983 * Allowed range is 0 to (cap_max_headroom_size - 1) 12984 * Default is 0 12985 * Access: RW 12986 */ 12987 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24); 12988 12989 static inline void mlxsw_reg_sbib_pack(char *payload, u16 local_port, 12990 u32 buff_size) 12991 { 12992 MLXSW_REG_ZERO(sbib, payload); 12993 mlxsw_reg_sbib_local_port_set(payload, local_port); 12994 mlxsw_reg_sbib_buff_size_set(payload, buff_size); 12995 } 12996 12997 static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { 12998 MLXSW_REG(sgcr), 12999 MLXSW_REG(spad), 13000 MLXSW_REG(sspr), 13001 MLXSW_REG(sfdat), 13002 MLXSW_REG(sfd), 13003 MLXSW_REG(sfn), 13004 MLXSW_REG(spms), 13005 MLXSW_REG(spvid), 13006 MLXSW_REG(spvm), 13007 MLXSW_REG(spaft), 13008 MLXSW_REG(sfgc), 13009 MLXSW_REG(sfdf), 13010 MLXSW_REG(sldr), 13011 MLXSW_REG(slcr), 13012 MLXSW_REG(slcor), 13013 MLXSW_REG(spmlr), 13014 MLXSW_REG(svfa), 13015 MLXSW_REG(spvtr), 13016 MLXSW_REG(svpe), 13017 MLXSW_REG(sfmr), 13018 MLXSW_REG(spvmlr), 13019 MLXSW_REG(spfsr), 13020 MLXSW_REG(spvc), 13021 MLXSW_REG(sffp), 13022 MLXSW_REG(spevet), 13023 MLXSW_REG(smpe), 13024 MLXSW_REG(smid2), 13025 MLXSW_REG(cwtp), 13026 MLXSW_REG(cwtpm), 13027 MLXSW_REG(pgcr), 13028 MLXSW_REG(ppbt), 13029 MLXSW_REG(pacl), 13030 MLXSW_REG(pagt), 13031 MLXSW_REG(ptar), 13032 MLXSW_REG(pprr), 13033 MLXSW_REG(ppbs), 13034 MLXSW_REG(prcr), 13035 MLXSW_REG(pefa), 13036 MLXSW_REG(pemrbt), 13037 MLXSW_REG(ptce2), 13038 MLXSW_REG(perpt), 13039 MLXSW_REG(peabfe), 13040 MLXSW_REG(perar), 13041 MLXSW_REG(ptce3), 13042 MLXSW_REG(percr), 13043 MLXSW_REG(pererp), 13044 MLXSW_REG(iedr), 13045 MLXSW_REG(qpts), 13046 MLXSW_REG(qpcr), 13047 MLXSW_REG(qtct), 13048 MLXSW_REG(qeec), 13049 MLXSW_REG(qrwe), 13050 MLXSW_REG(qpdsm), 13051 MLXSW_REG(qpdp), 13052 MLXSW_REG(qpdpm), 13053 MLXSW_REG(qtctm), 13054 MLXSW_REG(qpsc), 13055 MLXSW_REG(pmlp), 13056 MLXSW_REG(pmtu), 13057 MLXSW_REG(ptys), 13058 MLXSW_REG(ppad), 13059 MLXSW_REG(paos), 13060 MLXSW_REG(pfcc), 13061 MLXSW_REG(ppcnt), 13062 MLXSW_REG(pptb), 13063 MLXSW_REG(pbmc), 13064 MLXSW_REG(pspa), 13065 MLXSW_REG(pmaos), 13066 MLXSW_REG(pplr), 13067 MLXSW_REG(pmtdb), 13068 MLXSW_REG(pmecr), 13069 MLXSW_REG(pmpe), 13070 MLXSW_REG(pddr), 13071 MLXSW_REG(pmmp), 13072 MLXSW_REG(pllp), 13073 MLXSW_REG(pmtm), 13074 MLXSW_REG(htgt), 13075 MLXSW_REG(hpkt), 13076 MLXSW_REG(rgcr), 13077 MLXSW_REG(ritr), 13078 MLXSW_REG(rtar), 13079 MLXSW_REG(ratr), 13080 MLXSW_REG(rtdp), 13081 MLXSW_REG(rips), 13082 MLXSW_REG(ratrad), 13083 MLXSW_REG(rdpm), 13084 MLXSW_REG(ricnt), 13085 MLXSW_REG(rrcr), 13086 MLXSW_REG(ralta), 13087 MLXSW_REG(ralst), 13088 MLXSW_REG(raltb), 13089 MLXSW_REG(ralue), 13090 MLXSW_REG(rauht), 13091 MLXSW_REG(raleu), 13092 MLXSW_REG(rauhtd), 13093 MLXSW_REG(rigr2), 13094 MLXSW_REG(recr2), 13095 MLXSW_REG(rmft2), 13096 MLXSW_REG(reiv), 13097 MLXSW_REG(mfcr), 13098 MLXSW_REG(mfsc), 13099 MLXSW_REG(mfsm), 13100 MLXSW_REG(mfsl), 13101 MLXSW_REG(fore), 13102 MLXSW_REG(mtcap), 13103 MLXSW_REG(mtmp), 13104 MLXSW_REG(mtwe), 13105 MLXSW_REG(mtbr), 13106 MLXSW_REG(mcia), 13107 MLXSW_REG(mpat), 13108 MLXSW_REG(mpar), 13109 MLXSW_REG(mgir), 13110 MLXSW_REG(mrsr), 13111 MLXSW_REG(mlcr), 13112 MLXSW_REG(mcion), 13113 MLXSW_REG(mtpps), 13114 MLXSW_REG(mtutc), 13115 MLXSW_REG(mcqi), 13116 MLXSW_REG(mcc), 13117 MLXSW_REG(mcda), 13118 MLXSW_REG(mcam), 13119 MLXSW_REG(mpsc), 13120 MLXSW_REG(mgpc), 13121 MLXSW_REG(mprs), 13122 MLXSW_REG(mogcr), 13123 MLXSW_REG(mpagr), 13124 MLXSW_REG(momte), 13125 MLXSW_REG(mtpppc), 13126 MLXSW_REG(mtpptr), 13127 MLXSW_REG(mtptpt), 13128 MLXSW_REG(mtpcpc), 13129 MLXSW_REG(mfgd), 13130 MLXSW_REG(mgpir), 13131 MLXSW_REG(mbct), 13132 MLXSW_REG(mddt), 13133 MLXSW_REG(mddq), 13134 MLXSW_REG(mddc), 13135 MLXSW_REG(mfde), 13136 MLXSW_REG(tngcr), 13137 MLXSW_REG(tnumt), 13138 MLXSW_REG(tnqcr), 13139 MLXSW_REG(tnqdr), 13140 MLXSW_REG(tneem), 13141 MLXSW_REG(tndem), 13142 MLXSW_REG(tnpc), 13143 MLXSW_REG(tigcr), 13144 MLXSW_REG(tieem), 13145 MLXSW_REG(tidem), 13146 MLXSW_REG(sbpr), 13147 MLXSW_REG(sbcm), 13148 MLXSW_REG(sbpm), 13149 MLXSW_REG(sbmm), 13150 MLXSW_REG(sbsr), 13151 MLXSW_REG(sbib), 13152 }; 13153 13154 static inline const char *mlxsw_reg_id_str(u16 reg_id) 13155 { 13156 const struct mlxsw_reg_info *reg_info; 13157 int i; 13158 13159 for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) { 13160 reg_info = mlxsw_reg_infos[i]; 13161 if (reg_info->id == reg_id) 13162 return reg_info->name; 13163 } 13164 return "*UNKNOWN*"; 13165 } 13166 13167 /* PUDE - Port Up / Down Event 13168 * --------------------------- 13169 * Reports the operational state change of a port. 13170 */ 13171 #define MLXSW_REG_PUDE_LEN 0x10 13172 13173 /* reg_pude_swid 13174 * Switch partition ID with which to associate the port. 13175 * Access: Index 13176 */ 13177 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8); 13178 13179 /* reg_pude_local_port 13180 * Local port number. 13181 * Access: Index 13182 */ 13183 MLXSW_ITEM32_LP(reg, pude, 0x00, 16, 0x00, 12); 13184 13185 /* reg_pude_admin_status 13186 * Port administrative state (the desired state). 13187 * 1 - Up. 13188 * 2 - Down. 13189 * 3 - Up once. This means that in case of link failure, the port won't go 13190 * into polling mode, but will wait to be re-enabled by software. 13191 * 4 - Disabled by system. Can only be set by hardware. 13192 * Access: RO 13193 */ 13194 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4); 13195 13196 /* reg_pude_oper_status 13197 * Port operatioanl state. 13198 * 1 - Up. 13199 * 2 - Down. 13200 * 3 - Down by port failure. This means that the device will not let the 13201 * port up again until explicitly specified by software. 13202 * Access: RO 13203 */ 13204 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4); 13205 13206 #endif 13207