1 /* 2 * drivers/net/ethernet/mellanox/mlxsw/pci.h 3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved. 4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the names of the copyright holders nor the names of its 15 * contributors may be used to endorse or promote products derived from 16 * this software without specific prior written permission. 17 * 18 * Alternatively, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") version 2 as published by the Free 20 * Software Foundation. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #ifndef _MLXSW_PCI_H 36 #define _MLXSW_PCI_H 37 38 #include <linux/bitops.h> 39 40 #include "item.h" 41 42 #define PCI_DEVICE_ID_MELLANOX_SWITCHX2 0xc738 43 #define MLXSW_PCI_BAR0_SIZE (1024 * 1024) /* 1MB */ 44 #define MLXSW_PCI_PAGE_SIZE 4096 45 46 #define MLXSW_PCI_CIR_BASE 0x71000 47 #define MLXSW_PCI_CIR_IN_PARAM_HI MLXSW_PCI_CIR_BASE 48 #define MLXSW_PCI_CIR_IN_PARAM_LO (MLXSW_PCI_CIR_BASE + 0x04) 49 #define MLXSW_PCI_CIR_IN_MODIFIER (MLXSW_PCI_CIR_BASE + 0x08) 50 #define MLXSW_PCI_CIR_OUT_PARAM_HI (MLXSW_PCI_CIR_BASE + 0x0C) 51 #define MLXSW_PCI_CIR_OUT_PARAM_LO (MLXSW_PCI_CIR_BASE + 0x10) 52 #define MLXSW_PCI_CIR_TOKEN (MLXSW_PCI_CIR_BASE + 0x14) 53 #define MLXSW_PCI_CIR_CTRL (MLXSW_PCI_CIR_BASE + 0x18) 54 #define MLXSW_PCI_CIR_CTRL_GO_BIT BIT(23) 55 #define MLXSW_PCI_CIR_CTRL_EVREQ_BIT BIT(22) 56 #define MLXSW_PCI_CIR_CTRL_OPCODE_MOD_SHIFT 12 57 #define MLXSW_PCI_CIR_CTRL_STATUS_SHIFT 24 58 #define MLXSW_PCI_CIR_TIMEOUT_MSECS 1000 59 60 #define MLXSW_PCI_SW_RESET 0xF0010 61 #define MLXSW_PCI_SW_RESET_RST_BIT BIT(0) 62 #define MLXSW_PCI_SW_RESET_TIMEOUT_MSECS 5000 63 64 #define MLXSW_PCI_DOORBELL_SDQ_OFFSET 0x000 65 #define MLXSW_PCI_DOORBELL_RDQ_OFFSET 0x200 66 #define MLXSW_PCI_DOORBELL_CQ_OFFSET 0x400 67 #define MLXSW_PCI_DOORBELL_EQ_OFFSET 0x600 68 #define MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET 0x800 69 #define MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET 0xA00 70 71 #define MLXSW_PCI_DOORBELL(offset, type_offset, num) \ 72 ((offset) + (type_offset) + (num) * 4) 73 74 #define MLXSW_PCI_CQS_MAX 96 75 #define MLXSW_PCI_EQS_COUNT 2 76 #define MLXSW_PCI_EQ_ASYNC_NUM 0 77 #define MLXSW_PCI_EQ_COMP_NUM 1 78 79 #define MLXSW_PCI_AQ_PAGES 8 80 #define MLXSW_PCI_AQ_SIZE (MLXSW_PCI_PAGE_SIZE * MLXSW_PCI_AQ_PAGES) 81 #define MLXSW_PCI_WQE_SIZE 32 /* 32 bytes per element */ 82 #define MLXSW_PCI_CQE_SIZE 16 /* 16 bytes per element */ 83 #define MLXSW_PCI_EQE_SIZE 16 /* 16 bytes per element */ 84 #define MLXSW_PCI_WQE_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_WQE_SIZE) 85 #define MLXSW_PCI_CQE_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_CQE_SIZE) 86 #define MLXSW_PCI_EQE_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_EQE_SIZE) 87 #define MLXSW_PCI_EQE_UPDATE_COUNT 0x80 88 89 #define MLXSW_PCI_WQE_SG_ENTRIES 3 90 #define MLXSW_PCI_WQE_TYPE_ETHERNET 0xA 91 92 /* pci_wqe_c 93 * If set it indicates that a completion should be reported upon 94 * execution of this descriptor. 95 */ 96 MLXSW_ITEM32(pci, wqe, c, 0x00, 31, 1); 97 98 /* pci_wqe_lp 99 * Local Processing, set if packet should be processed by the local 100 * switch hardware: 101 * For Ethernet EMAD (Direct Route and non Direct Route) - 102 * must be set if packet destination is local device 103 * For InfiniBand CTL - must be set if packet destination is local device 104 * Otherwise it must be clear 105 * Local Process packets must not exceed the size of 2K (including payload 106 * and headers). 107 */ 108 MLXSW_ITEM32(pci, wqe, lp, 0x00, 30, 1); 109 110 /* pci_wqe_type 111 * Packet type. 112 */ 113 MLXSW_ITEM32(pci, wqe, type, 0x00, 23, 4); 114 115 /* pci_wqe_byte_count 116 * Size of i-th scatter/gather entry, 0 if entry is unused. 117 */ 118 MLXSW_ITEM16_INDEXED(pci, wqe, byte_count, 0x02, 0, 14, 0x02, 0x00, false); 119 120 /* pci_wqe_address 121 * Physical address of i-th scatter/gather entry. 122 * Gather Entries must be 2Byte aligned. 123 */ 124 MLXSW_ITEM64_INDEXED(pci, wqe, address, 0x08, 0, 64, 0x8, 0x0, false); 125 126 /* pci_cqe_lag 127 * Packet arrives from a port which is a LAG 128 */ 129 MLXSW_ITEM32(pci, cqe, lag, 0x00, 23, 1); 130 131 /* pci_cqe_system_port 132 * When lag=0: System port on which the packet was received 133 * When lag=1: 134 * bits [15:4] LAG ID on which the packet was received 135 * bits [3:0] sub_port on which the packet was received 136 */ 137 MLXSW_ITEM32(pci, cqe, system_port, 0x00, 0, 16); 138 139 /* pci_cqe_wqe_counter 140 * WQE count of the WQEs completed on the associated dqn 141 */ 142 MLXSW_ITEM32(pci, cqe, wqe_counter, 0x04, 16, 16); 143 144 /* pci_cqe_byte_count 145 * Byte count of received packets including additional two 146 * Reserved Bytes that are append to the end of the frame. 147 * Reserved for Send CQE. 148 */ 149 MLXSW_ITEM32(pci, cqe, byte_count, 0x04, 0, 14); 150 151 /* pci_cqe_trap_id 152 * Trap ID that captured the packet. 153 */ 154 MLXSW_ITEM32(pci, cqe, trap_id, 0x08, 0, 8); 155 156 /* pci_cqe_crc 157 * Length include CRC. Indicates the length field includes 158 * the packet's CRC. 159 */ 160 MLXSW_ITEM32(pci, cqe, crc, 0x0C, 8, 1); 161 162 /* pci_cqe_e 163 * CQE with Error. 164 */ 165 MLXSW_ITEM32(pci, cqe, e, 0x0C, 7, 1); 166 167 /* pci_cqe_sr 168 * 1 - Send Queue 169 * 0 - Receive Queue 170 */ 171 MLXSW_ITEM32(pci, cqe, sr, 0x0C, 6, 1); 172 173 /* pci_cqe_dqn 174 * Descriptor Queue (DQ) Number. 175 */ 176 MLXSW_ITEM32(pci, cqe, dqn, 0x0C, 1, 5); 177 178 /* pci_cqe_owner 179 * Ownership bit. 180 */ 181 MLXSW_ITEM32(pci, cqe, owner, 0x0C, 0, 1); 182 183 /* pci_eqe_event_type 184 * Event type. 185 */ 186 MLXSW_ITEM32(pci, eqe, event_type, 0x0C, 24, 8); 187 #define MLXSW_PCI_EQE_EVENT_TYPE_COMP 0x00 188 #define MLXSW_PCI_EQE_EVENT_TYPE_CMD 0x0A 189 190 /* pci_eqe_event_sub_type 191 * Event type. 192 */ 193 MLXSW_ITEM32(pci, eqe, event_sub_type, 0x0C, 16, 8); 194 195 /* pci_eqe_cqn 196 * Completion Queue that triggeret this EQE. 197 */ 198 MLXSW_ITEM32(pci, eqe, cqn, 0x0C, 8, 7); 199 200 /* pci_eqe_owner 201 * Ownership bit. 202 */ 203 MLXSW_ITEM32(pci, eqe, owner, 0x0C, 0, 1); 204 205 /* pci_eqe_cmd_token 206 * Command completion event - token 207 */ 208 MLXSW_ITEM32(pci, eqe, cmd_token, 0x08, 16, 16); 209 210 /* pci_eqe_cmd_status 211 * Command completion event - status 212 */ 213 MLXSW_ITEM32(pci, eqe, cmd_status, 0x08, 0, 8); 214 215 /* pci_eqe_cmd_out_param_h 216 * Command completion event - output parameter - higher part 217 */ 218 MLXSW_ITEM32(pci, eqe, cmd_out_param_h, 0x0C, 0, 32); 219 220 /* pci_eqe_cmd_out_param_l 221 * Command completion event - output parameter - lower part 222 */ 223 MLXSW_ITEM32(pci, eqe, cmd_out_param_l, 0x10, 0, 32); 224 225 #endif 226