1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/export.h> 7 #include <linux/err.h> 8 #include <linux/device.h> 9 #include <linux/pci.h> 10 #include <linux/interrupt.h> 11 #include <linux/types.h> 12 #include <linux/skbuff.h> 13 #include <linux/if_vlan.h> 14 #include <linux/log2.h> 15 #include <linux/string.h> 16 #include <net/page_pool/helpers.h> 17 18 #include "pci_hw.h" 19 #include "pci.h" 20 #include "core.h" 21 #include "cmd.h" 22 #include "port.h" 23 #include "resources.h" 24 25 #define mlxsw_pci_write32(mlxsw_pci, reg, val) \ 26 iowrite32be(val, (mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg)) 27 #define mlxsw_pci_read32(mlxsw_pci, reg) \ 28 ioread32be((mlxsw_pci)->hw_addr + (MLXSW_PCI_ ## reg)) 29 30 enum mlxsw_pci_queue_type { 31 MLXSW_PCI_QUEUE_TYPE_SDQ, 32 MLXSW_PCI_QUEUE_TYPE_RDQ, 33 MLXSW_PCI_QUEUE_TYPE_CQ, 34 MLXSW_PCI_QUEUE_TYPE_EQ, 35 }; 36 37 #define MLXSW_PCI_QUEUE_TYPE_COUNT 4 38 39 enum mlxsw_pci_cq_type { 40 MLXSW_PCI_CQ_SDQ, 41 MLXSW_PCI_CQ_RDQ, 42 }; 43 44 static const u16 mlxsw_pci_doorbell_type_offset[] = { 45 MLXSW_PCI_DOORBELL_SDQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_SDQ */ 46 MLXSW_PCI_DOORBELL_RDQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_RDQ */ 47 MLXSW_PCI_DOORBELL_CQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_CQ */ 48 MLXSW_PCI_DOORBELL_EQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_EQ */ 49 }; 50 51 static const u16 mlxsw_pci_doorbell_arm_type_offset[] = { 52 0, /* unused */ 53 0, /* unused */ 54 MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_CQ */ 55 MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET, /* for type MLXSW_PCI_QUEUE_TYPE_EQ */ 56 }; 57 58 struct mlxsw_pci_mem_item { 59 char *buf; 60 dma_addr_t mapaddr; 61 size_t size; 62 }; 63 64 struct mlxsw_pci_queue_elem_info { 65 struct page *page; 66 char *elem; /* pointer to actual dma mapped element mem chunk */ 67 struct { 68 struct sk_buff *skb; 69 } sdq; 70 }; 71 72 struct mlxsw_pci_queue { 73 spinlock_t lock; /* for queue accesses */ 74 struct mlxsw_pci_mem_item mem_item; 75 struct mlxsw_pci_queue_elem_info *elem_info; 76 u16 producer_counter; 77 u16 consumer_counter; 78 u16 count; /* number of elements in queue */ 79 u8 num; /* queue number */ 80 u8 elem_size; /* size of one element */ 81 enum mlxsw_pci_queue_type type; 82 struct mlxsw_pci *pci; 83 union { 84 struct { 85 enum mlxsw_pci_cqe_v v; 86 struct mlxsw_pci_queue *dq; 87 struct napi_struct napi; 88 struct page_pool *page_pool; 89 } cq; 90 struct { 91 struct tasklet_struct tasklet; 92 } eq; 93 struct { 94 struct mlxsw_pci_queue *cq; 95 } rdq; 96 } u; 97 }; 98 99 struct mlxsw_pci_queue_type_group { 100 struct mlxsw_pci_queue *q; 101 u8 count; /* number of queues in group */ 102 }; 103 104 struct mlxsw_pci { 105 struct pci_dev *pdev; 106 u8 __iomem *hw_addr; 107 u64 free_running_clock_offset; 108 u64 utc_sec_offset; 109 u64 utc_nsec_offset; 110 bool lag_mode_support; 111 bool cff_support; 112 enum mlxsw_cmd_mbox_config_profile_lag_mode lag_mode; 113 enum mlxsw_cmd_mbox_config_profile_flood_mode flood_mode; 114 struct mlxsw_pci_queue_type_group queues[MLXSW_PCI_QUEUE_TYPE_COUNT]; 115 u32 doorbell_offset; 116 struct mlxsw_core *core; 117 struct { 118 struct mlxsw_pci_mem_item *items; 119 unsigned int count; 120 } fw_area; 121 struct { 122 struct mlxsw_pci_mem_item out_mbox; 123 struct mlxsw_pci_mem_item in_mbox; 124 struct mutex lock; /* Lock access to command registers */ 125 struct { 126 u8 status; 127 u64 out_param; 128 } comp; 129 } cmd; 130 struct mlxsw_bus_info bus_info; 131 const struct pci_device_id *id; 132 enum mlxsw_pci_cqe_v max_cqe_ver; /* Maximal supported CQE version */ 133 u8 num_cqs; /* Number of CQs */ 134 u8 num_sdqs; /* Number of SDQs */ 135 bool skip_reset; 136 struct net_device *napi_dev_tx; 137 struct net_device *napi_dev_rx; 138 }; 139 140 static int mlxsw_pci_napi_devs_init(struct mlxsw_pci *mlxsw_pci) 141 { 142 int err; 143 144 mlxsw_pci->napi_dev_tx = alloc_netdev_dummy(0); 145 if (!mlxsw_pci->napi_dev_tx) 146 return -ENOMEM; 147 strscpy(mlxsw_pci->napi_dev_tx->name, "mlxsw_tx", 148 sizeof(mlxsw_pci->napi_dev_tx->name)); 149 150 mlxsw_pci->napi_dev_rx = alloc_netdev_dummy(0); 151 if (!mlxsw_pci->napi_dev_rx) { 152 err = -ENOMEM; 153 goto err_alloc_rx; 154 } 155 strscpy(mlxsw_pci->napi_dev_rx->name, "mlxsw_rx", 156 sizeof(mlxsw_pci->napi_dev_rx->name)); 157 dev_set_threaded(mlxsw_pci->napi_dev_rx, true); 158 159 return 0; 160 161 err_alloc_rx: 162 free_netdev(mlxsw_pci->napi_dev_tx); 163 return err; 164 } 165 166 static void mlxsw_pci_napi_devs_fini(struct mlxsw_pci *mlxsw_pci) 167 { 168 free_netdev(mlxsw_pci->napi_dev_rx); 169 free_netdev(mlxsw_pci->napi_dev_tx); 170 } 171 172 static char *__mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue *q, 173 size_t elem_size, int elem_index) 174 { 175 return q->mem_item.buf + (elem_size * elem_index); 176 } 177 178 static struct mlxsw_pci_queue_elem_info * 179 mlxsw_pci_queue_elem_info_get(struct mlxsw_pci_queue *q, int elem_index) 180 { 181 return &q->elem_info[elem_index]; 182 } 183 184 static struct mlxsw_pci_queue_elem_info * 185 mlxsw_pci_queue_elem_info_producer_get(struct mlxsw_pci_queue *q) 186 { 187 int index = q->producer_counter & (q->count - 1); 188 189 if ((u16) (q->producer_counter - q->consumer_counter) == q->count) 190 return NULL; 191 return mlxsw_pci_queue_elem_info_get(q, index); 192 } 193 194 static struct mlxsw_pci_queue_elem_info * 195 mlxsw_pci_queue_elem_info_consumer_get(struct mlxsw_pci_queue *q) 196 { 197 int index = q->consumer_counter & (q->count - 1); 198 199 return mlxsw_pci_queue_elem_info_get(q, index); 200 } 201 202 static char *mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue *q, int elem_index) 203 { 204 return mlxsw_pci_queue_elem_info_get(q, elem_index)->elem; 205 } 206 207 static bool mlxsw_pci_elem_hw_owned(struct mlxsw_pci_queue *q, bool owner_bit) 208 { 209 return owner_bit != !!(q->consumer_counter & q->count); 210 } 211 212 static struct mlxsw_pci_queue_type_group * 213 mlxsw_pci_queue_type_group_get(struct mlxsw_pci *mlxsw_pci, 214 enum mlxsw_pci_queue_type q_type) 215 { 216 return &mlxsw_pci->queues[q_type]; 217 } 218 219 static struct mlxsw_pci_queue * 220 __mlxsw_pci_queue_get(struct mlxsw_pci *mlxsw_pci, 221 enum mlxsw_pci_queue_type q_type, u8 q_num) 222 { 223 return &mlxsw_pci->queues[q_type].q[q_num]; 224 } 225 226 static struct mlxsw_pci_queue *mlxsw_pci_sdq_get(struct mlxsw_pci *mlxsw_pci, 227 u8 q_num) 228 { 229 return __mlxsw_pci_queue_get(mlxsw_pci, 230 MLXSW_PCI_QUEUE_TYPE_SDQ, q_num); 231 } 232 233 static struct mlxsw_pci_queue *mlxsw_pci_cq_get(struct mlxsw_pci *mlxsw_pci, 234 u8 q_num) 235 { 236 return __mlxsw_pci_queue_get(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_CQ, q_num); 237 } 238 239 static struct mlxsw_pci_queue *mlxsw_pci_eq_get(struct mlxsw_pci *mlxsw_pci) 240 { 241 /* There is only one EQ at index 0. */ 242 return __mlxsw_pci_queue_get(mlxsw_pci, MLXSW_PCI_QUEUE_TYPE_EQ, 0); 243 } 244 245 static void __mlxsw_pci_queue_doorbell_set(struct mlxsw_pci *mlxsw_pci, 246 struct mlxsw_pci_queue *q, 247 u16 val) 248 { 249 mlxsw_pci_write32(mlxsw_pci, 250 DOORBELL(mlxsw_pci->doorbell_offset, 251 mlxsw_pci_doorbell_type_offset[q->type], 252 q->num), val); 253 } 254 255 static void __mlxsw_pci_queue_doorbell_arm_set(struct mlxsw_pci *mlxsw_pci, 256 struct mlxsw_pci_queue *q, 257 u16 val) 258 { 259 mlxsw_pci_write32(mlxsw_pci, 260 DOORBELL(mlxsw_pci->doorbell_offset, 261 mlxsw_pci_doorbell_arm_type_offset[q->type], 262 q->num), val); 263 } 264 265 static void mlxsw_pci_queue_doorbell_producer_ring(struct mlxsw_pci *mlxsw_pci, 266 struct mlxsw_pci_queue *q) 267 { 268 wmb(); /* ensure all writes are done before we ring a bell */ 269 __mlxsw_pci_queue_doorbell_set(mlxsw_pci, q, q->producer_counter); 270 } 271 272 static void mlxsw_pci_queue_doorbell_consumer_ring(struct mlxsw_pci *mlxsw_pci, 273 struct mlxsw_pci_queue *q) 274 { 275 wmb(); /* ensure all writes are done before we ring a bell */ 276 __mlxsw_pci_queue_doorbell_set(mlxsw_pci, q, 277 q->consumer_counter + q->count); 278 } 279 280 static void 281 mlxsw_pci_queue_doorbell_arm_consumer_ring(struct mlxsw_pci *mlxsw_pci, 282 struct mlxsw_pci_queue *q) 283 { 284 wmb(); /* ensure all writes are done before we ring a bell */ 285 __mlxsw_pci_queue_doorbell_arm_set(mlxsw_pci, q, q->consumer_counter); 286 } 287 288 static dma_addr_t __mlxsw_pci_queue_page_get(struct mlxsw_pci_queue *q, 289 int page_index) 290 { 291 return q->mem_item.mapaddr + MLXSW_PCI_PAGE_SIZE * page_index; 292 } 293 294 static int mlxsw_pci_sdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 295 struct mlxsw_pci_queue *q) 296 { 297 struct mlxsw_pci_queue *cq; 298 int tclass; 299 u8 cq_num; 300 int lp; 301 int i; 302 int err; 303 304 q->producer_counter = 0; 305 q->consumer_counter = 0; 306 tclass = q->num == MLXSW_PCI_SDQ_EMAD_INDEX ? MLXSW_PCI_SDQ_EMAD_TC : 307 MLXSW_PCI_SDQ_CTL_TC; 308 lp = q->num == MLXSW_PCI_SDQ_EMAD_INDEX ? MLXSW_CMD_MBOX_SW2HW_DQ_SDQ_LP_IGNORE_WQE : 309 MLXSW_CMD_MBOX_SW2HW_DQ_SDQ_LP_WQE; 310 311 /* Set CQ of same number of this SDQ. */ 312 cq_num = q->num; 313 mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, cq_num); 314 mlxsw_cmd_mbox_sw2hw_dq_sdq_lp_set(mbox, lp); 315 mlxsw_cmd_mbox_sw2hw_dq_sdq_tclass_set(mbox, tclass); 316 mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3); /* 8 pages */ 317 for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) { 318 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i); 319 320 mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr); 321 } 322 323 err = mlxsw_cmd_sw2hw_sdq(mlxsw_pci->core, mbox, q->num); 324 if (err) 325 return err; 326 327 cq = mlxsw_pci_cq_get(mlxsw_pci, cq_num); 328 cq->u.cq.dq = q; 329 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); 330 return 0; 331 } 332 333 static void mlxsw_pci_sdq_fini(struct mlxsw_pci *mlxsw_pci, 334 struct mlxsw_pci_queue *q) 335 { 336 mlxsw_cmd_hw2sw_sdq(mlxsw_pci->core, q->num); 337 } 338 339 #define MLXSW_PCI_SKB_HEADROOM (NET_SKB_PAD + NET_IP_ALIGN) 340 341 #define MLXSW_PCI_RX_BUF_SW_OVERHEAD \ 342 (MLXSW_PCI_SKB_HEADROOM + \ 343 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 344 345 static void 346 mlxsw_pci_wqe_rx_frag_set(struct mlxsw_pci *mlxsw_pci, struct page *page, 347 char *wqe, int index, size_t frag_len) 348 { 349 dma_addr_t mapaddr; 350 351 mapaddr = page_pool_get_dma_addr(page); 352 mapaddr += MLXSW_PCI_SKB_HEADROOM; 353 354 mlxsw_pci_wqe_address_set(wqe, index, mapaddr); 355 mlxsw_pci_wqe_byte_count_set(wqe, index, frag_len); 356 } 357 358 static int mlxsw_pci_wqe_frag_map(struct mlxsw_pci *mlxsw_pci, char *wqe, 359 int index, char *frag_data, size_t frag_len, 360 int direction) 361 { 362 struct pci_dev *pdev = mlxsw_pci->pdev; 363 dma_addr_t mapaddr; 364 365 mapaddr = dma_map_single(&pdev->dev, frag_data, frag_len, direction); 366 if (unlikely(dma_mapping_error(&pdev->dev, mapaddr))) { 367 dev_err_ratelimited(&pdev->dev, "failed to dma map tx frag\n"); 368 return -EIO; 369 } 370 mlxsw_pci_wqe_address_set(wqe, index, mapaddr); 371 mlxsw_pci_wqe_byte_count_set(wqe, index, frag_len); 372 return 0; 373 } 374 375 static void mlxsw_pci_wqe_frag_unmap(struct mlxsw_pci *mlxsw_pci, char *wqe, 376 int index, int direction) 377 { 378 struct pci_dev *pdev = mlxsw_pci->pdev; 379 size_t frag_len = mlxsw_pci_wqe_byte_count_get(wqe, index); 380 dma_addr_t mapaddr = mlxsw_pci_wqe_address_get(wqe, index); 381 382 if (!frag_len) 383 return; 384 dma_unmap_single(&pdev->dev, mapaddr, frag_len, direction); 385 } 386 387 static struct sk_buff *mlxsw_pci_rdq_build_skb(struct page *page, 388 u16 byte_count) 389 { 390 void *data = page_address(page); 391 unsigned int allocated_size; 392 struct sk_buff *skb; 393 394 net_prefetch(data); 395 allocated_size = page_size(page); 396 skb = napi_build_skb(data, allocated_size); 397 if (unlikely(!skb)) 398 return ERR_PTR(-ENOMEM); 399 400 skb_reserve(skb, MLXSW_PCI_SKB_HEADROOM); 401 skb_put(skb, byte_count); 402 return skb; 403 } 404 405 static int mlxsw_pci_rdq_page_alloc(struct mlxsw_pci_queue *q, 406 struct mlxsw_pci_queue_elem_info *elem_info) 407 { 408 struct mlxsw_pci_queue *cq = q->u.rdq.cq; 409 size_t buf_len = MLXSW_PORT_MAX_MTU; 410 char *wqe = elem_info->elem; 411 struct page *page; 412 413 page = page_pool_dev_alloc_pages(cq->u.cq.page_pool); 414 if (unlikely(!page)) 415 return -ENOMEM; 416 417 mlxsw_pci_wqe_rx_frag_set(q->pci, page, wqe, 0, buf_len); 418 elem_info->page = page; 419 return 0; 420 } 421 422 static void mlxsw_pci_rdq_page_free(struct mlxsw_pci_queue *q, 423 struct mlxsw_pci_queue_elem_info *elem_info) 424 { 425 struct mlxsw_pci_queue *cq = q->u.rdq.cq; 426 427 page_pool_put_page(cq->u.cq.page_pool, elem_info->page, -1, false); 428 } 429 430 static int mlxsw_pci_rdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 431 struct mlxsw_pci_queue *q) 432 { 433 struct mlxsw_pci_queue_elem_info *elem_info; 434 u8 sdq_count = mlxsw_pci->num_sdqs; 435 struct mlxsw_pci_queue *cq; 436 u8 cq_num; 437 int i; 438 int err; 439 440 q->producer_counter = 0; 441 q->consumer_counter = 0; 442 443 /* Set CQ of same number of this RDQ with base 444 * above SDQ count as the lower ones are assigned to SDQs. 445 */ 446 cq_num = sdq_count + q->num; 447 mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, cq_num); 448 mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3); /* 8 pages */ 449 for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) { 450 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i); 451 452 mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr); 453 } 454 455 err = mlxsw_cmd_sw2hw_rdq(mlxsw_pci->core, mbox, q->num); 456 if (err) 457 return err; 458 459 cq = mlxsw_pci_cq_get(mlxsw_pci, cq_num); 460 cq->u.cq.dq = q; 461 q->u.rdq.cq = cq; 462 463 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); 464 465 for (i = 0; i < q->count; i++) { 466 elem_info = mlxsw_pci_queue_elem_info_producer_get(q); 467 BUG_ON(!elem_info); 468 err = mlxsw_pci_rdq_page_alloc(q, elem_info); 469 if (err) 470 goto rollback; 471 /* Everything is set up, ring doorbell to pass elem to HW */ 472 q->producer_counter++; 473 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); 474 } 475 476 return 0; 477 478 rollback: 479 for (i--; i >= 0; i--) { 480 elem_info = mlxsw_pci_queue_elem_info_get(q, i); 481 mlxsw_pci_rdq_page_free(q, elem_info); 482 } 483 q->u.rdq.cq = NULL; 484 cq->u.cq.dq = NULL; 485 mlxsw_cmd_hw2sw_rdq(mlxsw_pci->core, q->num); 486 487 return err; 488 } 489 490 static void mlxsw_pci_rdq_fini(struct mlxsw_pci *mlxsw_pci, 491 struct mlxsw_pci_queue *q) 492 { 493 struct mlxsw_pci_queue_elem_info *elem_info; 494 int i; 495 496 mlxsw_cmd_hw2sw_rdq(mlxsw_pci->core, q->num); 497 for (i = 0; i < q->count; i++) { 498 elem_info = mlxsw_pci_queue_elem_info_get(q, i); 499 mlxsw_pci_rdq_page_free(q, elem_info); 500 } 501 } 502 503 static void mlxsw_pci_cq_pre_init(struct mlxsw_pci *mlxsw_pci, 504 struct mlxsw_pci_queue *q) 505 { 506 q->u.cq.v = mlxsw_pci->max_cqe_ver; 507 508 if (q->u.cq.v == MLXSW_PCI_CQE_V2 && 509 q->num < mlxsw_pci->num_sdqs && 510 !mlxsw_core_sdq_supports_cqe_v2(mlxsw_pci->core)) 511 q->u.cq.v = MLXSW_PCI_CQE_V1; 512 } 513 514 static unsigned int mlxsw_pci_read32_off(struct mlxsw_pci *mlxsw_pci, 515 ptrdiff_t off) 516 { 517 return ioread32be(mlxsw_pci->hw_addr + off); 518 } 519 520 static void mlxsw_pci_skb_cb_ts_set(struct mlxsw_pci *mlxsw_pci, 521 struct sk_buff *skb, 522 enum mlxsw_pci_cqe_v cqe_v, char *cqe) 523 { 524 u8 ts_type; 525 526 if (cqe_v != MLXSW_PCI_CQE_V2) 527 return; 528 529 ts_type = mlxsw_pci_cqe2_time_stamp_type_get(cqe); 530 531 if (ts_type != MLXSW_PCI_CQE_TIME_STAMP_TYPE_UTC && 532 ts_type != MLXSW_PCI_CQE_TIME_STAMP_TYPE_MIRROR_UTC) 533 return; 534 535 mlxsw_skb_cb(skb)->cqe_ts.sec = mlxsw_pci_cqe2_time_stamp_sec_get(cqe); 536 mlxsw_skb_cb(skb)->cqe_ts.nsec = 537 mlxsw_pci_cqe2_time_stamp_nsec_get(cqe); 538 } 539 540 static void mlxsw_pci_cqe_sdq_handle(struct mlxsw_pci *mlxsw_pci, 541 struct mlxsw_pci_queue *q, 542 u16 consumer_counter_limit, 543 enum mlxsw_pci_cqe_v cqe_v, 544 char *cqe, int budget) 545 { 546 struct pci_dev *pdev = mlxsw_pci->pdev; 547 struct mlxsw_pci_queue_elem_info *elem_info; 548 struct mlxsw_tx_info tx_info; 549 char *wqe; 550 struct sk_buff *skb; 551 int i; 552 553 spin_lock(&q->lock); 554 elem_info = mlxsw_pci_queue_elem_info_consumer_get(q); 555 tx_info = mlxsw_skb_cb(elem_info->sdq.skb)->tx_info; 556 skb = elem_info->sdq.skb; 557 wqe = elem_info->elem; 558 for (i = 0; i < MLXSW_PCI_WQE_SG_ENTRIES; i++) 559 mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, i, DMA_TO_DEVICE); 560 561 if (unlikely(!tx_info.is_emad && 562 skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 563 mlxsw_pci_skb_cb_ts_set(mlxsw_pci, skb, cqe_v, cqe); 564 mlxsw_core_ptp_transmitted(mlxsw_pci->core, skb, 565 tx_info.local_port); 566 skb = NULL; 567 } 568 569 if (skb) 570 napi_consume_skb(skb, budget); 571 elem_info->sdq.skb = NULL; 572 573 if (q->consumer_counter++ != consumer_counter_limit) 574 dev_dbg_ratelimited(&pdev->dev, "Consumer counter does not match limit in SDQ\n"); 575 spin_unlock(&q->lock); 576 } 577 578 static void mlxsw_pci_cqe_rdq_md_tx_port_init(struct sk_buff *skb, 579 const char *cqe) 580 { 581 struct mlxsw_skb_cb *cb = mlxsw_skb_cb(skb); 582 583 if (mlxsw_pci_cqe2_tx_lag_get(cqe)) { 584 cb->rx_md_info.tx_port_is_lag = true; 585 cb->rx_md_info.tx_lag_id = mlxsw_pci_cqe2_tx_lag_id_get(cqe); 586 cb->rx_md_info.tx_lag_port_index = 587 mlxsw_pci_cqe2_tx_lag_subport_get(cqe); 588 } else { 589 cb->rx_md_info.tx_port_is_lag = false; 590 cb->rx_md_info.tx_sys_port = 591 mlxsw_pci_cqe2_tx_system_port_get(cqe); 592 } 593 594 if (cb->rx_md_info.tx_sys_port != MLXSW_PCI_CQE2_TX_PORT_MULTI_PORT && 595 cb->rx_md_info.tx_sys_port != MLXSW_PCI_CQE2_TX_PORT_INVALID) 596 cb->rx_md_info.tx_port_valid = 1; 597 else 598 cb->rx_md_info.tx_port_valid = 0; 599 } 600 601 static void mlxsw_pci_cqe_rdq_md_init(struct sk_buff *skb, const char *cqe) 602 { 603 struct mlxsw_skb_cb *cb = mlxsw_skb_cb(skb); 604 605 cb->rx_md_info.tx_congestion = mlxsw_pci_cqe2_mirror_cong_get(cqe); 606 if (cb->rx_md_info.tx_congestion != MLXSW_PCI_CQE2_MIRROR_CONG_INVALID) 607 cb->rx_md_info.tx_congestion_valid = 1; 608 else 609 cb->rx_md_info.tx_congestion_valid = 0; 610 cb->rx_md_info.tx_congestion <<= MLXSW_PCI_CQE2_MIRROR_CONG_SHIFT; 611 612 cb->rx_md_info.latency = mlxsw_pci_cqe2_mirror_latency_get(cqe); 613 if (cb->rx_md_info.latency != MLXSW_PCI_CQE2_MIRROR_LATENCY_INVALID) 614 cb->rx_md_info.latency_valid = 1; 615 else 616 cb->rx_md_info.latency_valid = 0; 617 618 cb->rx_md_info.tx_tc = mlxsw_pci_cqe2_mirror_tclass_get(cqe); 619 if (cb->rx_md_info.tx_tc != MLXSW_PCI_CQE2_MIRROR_TCLASS_INVALID) 620 cb->rx_md_info.tx_tc_valid = 1; 621 else 622 cb->rx_md_info.tx_tc_valid = 0; 623 624 mlxsw_pci_cqe_rdq_md_tx_port_init(skb, cqe); 625 } 626 627 static void mlxsw_pci_cqe_rdq_handle(struct mlxsw_pci *mlxsw_pci, 628 struct mlxsw_pci_queue *q, 629 u16 consumer_counter_limit, 630 enum mlxsw_pci_cqe_v cqe_v, char *cqe) 631 { 632 struct pci_dev *pdev = mlxsw_pci->pdev; 633 struct mlxsw_pci_queue_elem_info *elem_info; 634 struct mlxsw_pci_queue *cq = q->u.rdq.cq; 635 struct mlxsw_rx_info rx_info = {}; 636 struct sk_buff *skb; 637 struct page *page; 638 u16 byte_count; 639 int err; 640 641 elem_info = mlxsw_pci_queue_elem_info_consumer_get(q); 642 643 if (q->consumer_counter++ != consumer_counter_limit) 644 dev_dbg_ratelimited(&pdev->dev, "Consumer counter does not match limit in RDQ\n"); 645 646 byte_count = mlxsw_pci_cqe_byte_count_get(cqe); 647 if (mlxsw_pci_cqe_crc_get(cqe_v, cqe)) 648 byte_count -= ETH_FCS_LEN; 649 650 page = elem_info->page; 651 652 err = mlxsw_pci_rdq_page_alloc(q, elem_info); 653 if (err) { 654 dev_err_ratelimited(&pdev->dev, "Failed to alloc page\n"); 655 goto out; 656 } 657 658 skb = mlxsw_pci_rdq_build_skb(page, byte_count); 659 if (IS_ERR(skb)) { 660 dev_err_ratelimited(&pdev->dev, "Failed to build skb for RDQ\n"); 661 page_pool_recycle_direct(cq->u.cq.page_pool, page); 662 goto out; 663 } 664 665 skb_mark_for_recycle(skb); 666 667 if (mlxsw_pci_cqe_lag_get(cqe_v, cqe)) { 668 rx_info.is_lag = true; 669 rx_info.u.lag_id = mlxsw_pci_cqe_lag_id_get(cqe_v, cqe); 670 rx_info.lag_port_index = 671 mlxsw_pci_cqe_lag_subport_get(cqe_v, cqe); 672 } else { 673 rx_info.is_lag = false; 674 rx_info.u.sys_port = mlxsw_pci_cqe_system_port_get(cqe); 675 } 676 677 rx_info.trap_id = mlxsw_pci_cqe_trap_id_get(cqe); 678 679 if (rx_info.trap_id == MLXSW_TRAP_ID_DISCARD_INGRESS_ACL || 680 rx_info.trap_id == MLXSW_TRAP_ID_DISCARD_EGRESS_ACL) { 681 u32 cookie_index = 0; 682 683 if (mlxsw_pci->max_cqe_ver >= MLXSW_PCI_CQE_V2) 684 cookie_index = mlxsw_pci_cqe2_user_def_val_orig_pkt_len_get(cqe); 685 mlxsw_skb_cb(skb)->rx_md_info.cookie_index = cookie_index; 686 } else if (rx_info.trap_id >= MLXSW_TRAP_ID_MIRROR_SESSION0 && 687 rx_info.trap_id <= MLXSW_TRAP_ID_MIRROR_SESSION7 && 688 mlxsw_pci->max_cqe_ver >= MLXSW_PCI_CQE_V2) { 689 rx_info.mirror_reason = mlxsw_pci_cqe2_mirror_reason_get(cqe); 690 mlxsw_pci_cqe_rdq_md_init(skb, cqe); 691 } else if (rx_info.trap_id == MLXSW_TRAP_ID_PKT_SAMPLE && 692 mlxsw_pci->max_cqe_ver >= MLXSW_PCI_CQE_V2) { 693 mlxsw_pci_cqe_rdq_md_tx_port_init(skb, cqe); 694 } 695 696 mlxsw_pci_skb_cb_ts_set(mlxsw_pci, skb, cqe_v, cqe); 697 698 mlxsw_core_skb_receive(mlxsw_pci->core, skb, &rx_info); 699 700 out: 701 q->producer_counter++; 702 return; 703 } 704 705 static char *mlxsw_pci_cq_sw_cqe_get(struct mlxsw_pci_queue *q) 706 { 707 struct mlxsw_pci_queue_elem_info *elem_info; 708 char *elem; 709 bool owner_bit; 710 711 elem_info = mlxsw_pci_queue_elem_info_consumer_get(q); 712 elem = elem_info->elem; 713 owner_bit = mlxsw_pci_cqe_owner_get(q->u.cq.v, elem); 714 if (mlxsw_pci_elem_hw_owned(q, owner_bit)) 715 return NULL; 716 q->consumer_counter++; 717 rmb(); /* make sure we read owned bit before the rest of elem */ 718 return elem; 719 } 720 721 static bool mlxsw_pci_cq_cqe_to_handle(struct mlxsw_pci_queue *q) 722 { 723 struct mlxsw_pci_queue_elem_info *elem_info; 724 bool owner_bit; 725 726 elem_info = mlxsw_pci_queue_elem_info_consumer_get(q); 727 owner_bit = mlxsw_pci_cqe_owner_get(q->u.cq.v, elem_info->elem); 728 return !mlxsw_pci_elem_hw_owned(q, owner_bit); 729 } 730 731 static int mlxsw_pci_napi_poll_cq_rx(struct napi_struct *napi, int budget) 732 { 733 struct mlxsw_pci_queue *q = container_of(napi, struct mlxsw_pci_queue, 734 u.cq.napi); 735 struct mlxsw_pci_queue *rdq = q->u.cq.dq; 736 struct mlxsw_pci *mlxsw_pci = q->pci; 737 int work_done = 0; 738 char *cqe; 739 740 /* If the budget is 0, Rx processing should be skipped. */ 741 if (unlikely(!budget)) 742 return 0; 743 744 while ((cqe = mlxsw_pci_cq_sw_cqe_get(q))) { 745 u16 wqe_counter = mlxsw_pci_cqe_wqe_counter_get(cqe); 746 u8 sendq = mlxsw_pci_cqe_sr_get(q->u.cq.v, cqe); 747 u8 dqn = mlxsw_pci_cqe_dqn_get(q->u.cq.v, cqe); 748 749 if (unlikely(sendq)) { 750 WARN_ON_ONCE(1); 751 continue; 752 } 753 754 if (unlikely(dqn != rdq->num)) { 755 WARN_ON_ONCE(1); 756 continue; 757 } 758 759 mlxsw_pci_cqe_rdq_handle(mlxsw_pci, rdq, 760 wqe_counter, q->u.cq.v, cqe); 761 762 if (++work_done == budget) 763 break; 764 } 765 766 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q); 767 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, rdq); 768 769 if (work_done < budget) 770 goto processing_completed; 771 772 /* The driver still has outstanding work to do, budget was exhausted. 773 * Return exactly budget. In that case, the NAPI instance will be polled 774 * again. 775 */ 776 if (mlxsw_pci_cq_cqe_to_handle(q)) 777 goto out; 778 779 /* The driver processed all the completions and handled exactly 780 * 'budget'. Return 'budget - 1' to distinguish from the case that 781 * driver still has completions to handle. 782 */ 783 if (work_done == budget) 784 work_done--; 785 786 processing_completed: 787 if (napi_complete_done(napi, work_done)) 788 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q); 789 out: 790 return work_done; 791 } 792 793 static int mlxsw_pci_napi_poll_cq_tx(struct napi_struct *napi, int budget) 794 { 795 struct mlxsw_pci_queue *q = container_of(napi, struct mlxsw_pci_queue, 796 u.cq.napi); 797 struct mlxsw_pci_queue *sdq = q->u.cq.dq; 798 struct mlxsw_pci *mlxsw_pci = q->pci; 799 int work_done = 0; 800 char *cqe; 801 802 while ((cqe = mlxsw_pci_cq_sw_cqe_get(q))) { 803 u16 wqe_counter = mlxsw_pci_cqe_wqe_counter_get(cqe); 804 u8 sendq = mlxsw_pci_cqe_sr_get(q->u.cq.v, cqe); 805 u8 dqn = mlxsw_pci_cqe_dqn_get(q->u.cq.v, cqe); 806 char ncqe[MLXSW_PCI_CQE_SIZE_MAX]; 807 808 if (unlikely(!sendq)) { 809 WARN_ON_ONCE(1); 810 continue; 811 } 812 813 if (unlikely(dqn != sdq->num)) { 814 WARN_ON_ONCE(1); 815 continue; 816 } 817 818 memcpy(ncqe, cqe, q->elem_size); 819 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q); 820 821 mlxsw_pci_cqe_sdq_handle(mlxsw_pci, sdq, 822 wqe_counter, q->u.cq.v, ncqe, budget); 823 824 work_done++; 825 } 826 827 /* If the budget is 0 napi_complete_done() should never be called. */ 828 if (unlikely(!budget)) 829 goto processing_completed; 830 831 work_done = min(work_done, budget - 1); 832 if (unlikely(!napi_complete_done(napi, work_done))) 833 goto out; 834 835 processing_completed: 836 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q); 837 out: 838 return work_done; 839 } 840 841 static enum mlxsw_pci_cq_type 842 mlxsw_pci_cq_type(const struct mlxsw_pci *mlxsw_pci, 843 const struct mlxsw_pci_queue *q) 844 { 845 /* Each CQ is mapped to one DQ. The first 'num_sdqs' queues are used 846 * for SDQs and the rest are used for RDQs. 847 */ 848 if (q->num < mlxsw_pci->num_sdqs) 849 return MLXSW_PCI_CQ_SDQ; 850 851 return MLXSW_PCI_CQ_RDQ; 852 } 853 854 static void mlxsw_pci_cq_napi_setup(struct mlxsw_pci_queue *q, 855 enum mlxsw_pci_cq_type cq_type) 856 { 857 struct mlxsw_pci *mlxsw_pci = q->pci; 858 859 switch (cq_type) { 860 case MLXSW_PCI_CQ_SDQ: 861 netif_napi_add(mlxsw_pci->napi_dev_tx, &q->u.cq.napi, 862 mlxsw_pci_napi_poll_cq_tx); 863 break; 864 case MLXSW_PCI_CQ_RDQ: 865 netif_napi_add(mlxsw_pci->napi_dev_rx, &q->u.cq.napi, 866 mlxsw_pci_napi_poll_cq_rx); 867 break; 868 } 869 } 870 871 static void mlxsw_pci_cq_napi_teardown(struct mlxsw_pci_queue *q) 872 { 873 netif_napi_del(&q->u.cq.napi); 874 } 875 876 static int mlxsw_pci_cq_page_pool_init(struct mlxsw_pci_queue *q, 877 enum mlxsw_pci_cq_type cq_type) 878 { 879 struct page_pool_params pp_params = {}; 880 struct mlxsw_pci *mlxsw_pci = q->pci; 881 struct page_pool *page_pool; 882 u32 max_pkt_size; 883 884 if (cq_type != MLXSW_PCI_CQ_RDQ) 885 return 0; 886 887 max_pkt_size = MLXSW_PORT_MAX_MTU + MLXSW_PCI_RX_BUF_SW_OVERHEAD; 888 pp_params.order = get_order(max_pkt_size); 889 pp_params.flags = PP_FLAG_DMA_MAP; 890 pp_params.pool_size = MLXSW_PCI_WQE_COUNT; 891 pp_params.nid = dev_to_node(&mlxsw_pci->pdev->dev); 892 pp_params.dev = &mlxsw_pci->pdev->dev; 893 pp_params.napi = &q->u.cq.napi; 894 pp_params.dma_dir = DMA_FROM_DEVICE; 895 896 page_pool = page_pool_create(&pp_params); 897 if (IS_ERR(page_pool)) 898 return PTR_ERR(page_pool); 899 900 q->u.cq.page_pool = page_pool; 901 return 0; 902 } 903 904 static void mlxsw_pci_cq_page_pool_fini(struct mlxsw_pci_queue *q, 905 enum mlxsw_pci_cq_type cq_type) 906 { 907 if (cq_type != MLXSW_PCI_CQ_RDQ) 908 return; 909 910 page_pool_destroy(q->u.cq.page_pool); 911 } 912 913 static int mlxsw_pci_cq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 914 struct mlxsw_pci_queue *q) 915 { 916 enum mlxsw_pci_cq_type cq_type = mlxsw_pci_cq_type(mlxsw_pci, q); 917 int i; 918 int err; 919 920 q->consumer_counter = 0; 921 922 for (i = 0; i < q->count; i++) { 923 char *elem = mlxsw_pci_queue_elem_get(q, i); 924 925 mlxsw_pci_cqe_owner_set(q->u.cq.v, elem, 1); 926 } 927 928 if (q->u.cq.v == MLXSW_PCI_CQE_V1) 929 mlxsw_cmd_mbox_sw2hw_cq_cqe_ver_set(mbox, 930 MLXSW_CMD_MBOX_SW2HW_CQ_CQE_VER_1); 931 else if (q->u.cq.v == MLXSW_PCI_CQE_V2) 932 mlxsw_cmd_mbox_sw2hw_cq_cqe_ver_set(mbox, 933 MLXSW_CMD_MBOX_SW2HW_CQ_CQE_VER_2); 934 935 mlxsw_cmd_mbox_sw2hw_cq_c_eqn_set(mbox, MLXSW_PCI_EQ_COMP_NUM); 936 mlxsw_cmd_mbox_sw2hw_cq_st_set(mbox, 0); 937 mlxsw_cmd_mbox_sw2hw_cq_log_cq_size_set(mbox, ilog2(q->count)); 938 for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) { 939 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i); 940 941 mlxsw_cmd_mbox_sw2hw_cq_pa_set(mbox, i, mapaddr); 942 } 943 err = mlxsw_cmd_sw2hw_cq(mlxsw_pci->core, mbox, q->num); 944 if (err) 945 return err; 946 mlxsw_pci_cq_napi_setup(q, cq_type); 947 948 err = mlxsw_pci_cq_page_pool_init(q, cq_type); 949 if (err) 950 goto err_page_pool_init; 951 952 napi_enable(&q->u.cq.napi); 953 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q); 954 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q); 955 return 0; 956 957 err_page_pool_init: 958 mlxsw_pci_cq_napi_teardown(q); 959 return err; 960 } 961 962 static void mlxsw_pci_cq_fini(struct mlxsw_pci *mlxsw_pci, 963 struct mlxsw_pci_queue *q) 964 { 965 enum mlxsw_pci_cq_type cq_type = mlxsw_pci_cq_type(mlxsw_pci, q); 966 967 napi_disable(&q->u.cq.napi); 968 mlxsw_pci_cq_page_pool_fini(q, cq_type); 969 mlxsw_pci_cq_napi_teardown(q); 970 mlxsw_cmd_hw2sw_cq(mlxsw_pci->core, q->num); 971 } 972 973 static u16 mlxsw_pci_cq_elem_count(const struct mlxsw_pci_queue *q) 974 { 975 return q->u.cq.v == MLXSW_PCI_CQE_V2 ? MLXSW_PCI_CQE2_COUNT : 976 MLXSW_PCI_CQE01_COUNT; 977 } 978 979 static u8 mlxsw_pci_cq_elem_size(const struct mlxsw_pci_queue *q) 980 { 981 return q->u.cq.v == MLXSW_PCI_CQE_V2 ? MLXSW_PCI_CQE2_SIZE : 982 MLXSW_PCI_CQE01_SIZE; 983 } 984 985 static char *mlxsw_pci_eq_sw_eqe_get(struct mlxsw_pci_queue *q) 986 { 987 struct mlxsw_pci_queue_elem_info *elem_info; 988 char *elem; 989 bool owner_bit; 990 991 elem_info = mlxsw_pci_queue_elem_info_consumer_get(q); 992 elem = elem_info->elem; 993 owner_bit = mlxsw_pci_eqe_owner_get(elem); 994 if (mlxsw_pci_elem_hw_owned(q, owner_bit)) 995 return NULL; 996 q->consumer_counter++; 997 rmb(); /* make sure we read owned bit before the rest of elem */ 998 return elem; 999 } 1000 1001 static void mlxsw_pci_eq_tasklet(struct tasklet_struct *t) 1002 { 1003 unsigned long active_cqns[BITS_TO_LONGS(MLXSW_PCI_CQS_MAX)]; 1004 struct mlxsw_pci_queue *q = from_tasklet(q, t, u.eq.tasklet); 1005 struct mlxsw_pci *mlxsw_pci = q->pci; 1006 int credits = q->count >> 1; 1007 u8 cqn, cq_count; 1008 int items = 0; 1009 char *eqe; 1010 1011 memset(&active_cqns, 0, sizeof(active_cqns)); 1012 1013 while ((eqe = mlxsw_pci_eq_sw_eqe_get(q))) { 1014 cqn = mlxsw_pci_eqe_cqn_get(eqe); 1015 set_bit(cqn, active_cqns); 1016 1017 if (++items == credits) 1018 break; 1019 } 1020 1021 if (!items) 1022 return; 1023 1024 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q); 1025 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q); 1026 1027 cq_count = mlxsw_pci->num_cqs; 1028 for_each_set_bit(cqn, active_cqns, cq_count) { 1029 q = mlxsw_pci_cq_get(mlxsw_pci, cqn); 1030 napi_schedule(&q->u.cq.napi); 1031 } 1032 } 1033 1034 static int mlxsw_pci_eq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 1035 struct mlxsw_pci_queue *q) 1036 { 1037 int i; 1038 int err; 1039 1040 /* We expect to initialize only one EQ, which gets num=0 as it is 1041 * located at index zero. We use the EQ as EQ1, so set the number for 1042 * future use. 1043 */ 1044 WARN_ON_ONCE(q->num); 1045 q->num = MLXSW_PCI_EQ_COMP_NUM; 1046 1047 q->consumer_counter = 0; 1048 1049 for (i = 0; i < q->count; i++) { 1050 char *elem = mlxsw_pci_queue_elem_get(q, i); 1051 1052 mlxsw_pci_eqe_owner_set(elem, 1); 1053 } 1054 1055 mlxsw_cmd_mbox_sw2hw_eq_int_msix_set(mbox, 1); /* MSI-X used */ 1056 mlxsw_cmd_mbox_sw2hw_eq_st_set(mbox, 1); /* armed */ 1057 mlxsw_cmd_mbox_sw2hw_eq_log_eq_size_set(mbox, ilog2(q->count)); 1058 for (i = 0; i < MLXSW_PCI_AQ_PAGES; i++) { 1059 dma_addr_t mapaddr = __mlxsw_pci_queue_page_get(q, i); 1060 1061 mlxsw_cmd_mbox_sw2hw_eq_pa_set(mbox, i, mapaddr); 1062 } 1063 err = mlxsw_cmd_sw2hw_eq(mlxsw_pci->core, mbox, q->num); 1064 if (err) 1065 return err; 1066 tasklet_setup(&q->u.eq.tasklet, mlxsw_pci_eq_tasklet); 1067 mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q); 1068 mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q); 1069 return 0; 1070 } 1071 1072 static void mlxsw_pci_eq_fini(struct mlxsw_pci *mlxsw_pci, 1073 struct mlxsw_pci_queue *q) 1074 { 1075 mlxsw_cmd_hw2sw_eq(mlxsw_pci->core, q->num); 1076 } 1077 1078 struct mlxsw_pci_queue_ops { 1079 const char *name; 1080 enum mlxsw_pci_queue_type type; 1081 void (*pre_init)(struct mlxsw_pci *mlxsw_pci, 1082 struct mlxsw_pci_queue *q); 1083 int (*init)(struct mlxsw_pci *mlxsw_pci, char *mbox, 1084 struct mlxsw_pci_queue *q); 1085 void (*fini)(struct mlxsw_pci *mlxsw_pci, 1086 struct mlxsw_pci_queue *q); 1087 u16 (*elem_count_f)(const struct mlxsw_pci_queue *q); 1088 u8 (*elem_size_f)(const struct mlxsw_pci_queue *q); 1089 u16 elem_count; 1090 u8 elem_size; 1091 }; 1092 1093 static const struct mlxsw_pci_queue_ops mlxsw_pci_sdq_ops = { 1094 .type = MLXSW_PCI_QUEUE_TYPE_SDQ, 1095 .init = mlxsw_pci_sdq_init, 1096 .fini = mlxsw_pci_sdq_fini, 1097 .elem_count = MLXSW_PCI_WQE_COUNT, 1098 .elem_size = MLXSW_PCI_WQE_SIZE, 1099 }; 1100 1101 static const struct mlxsw_pci_queue_ops mlxsw_pci_rdq_ops = { 1102 .type = MLXSW_PCI_QUEUE_TYPE_RDQ, 1103 .init = mlxsw_pci_rdq_init, 1104 .fini = mlxsw_pci_rdq_fini, 1105 .elem_count = MLXSW_PCI_WQE_COUNT, 1106 .elem_size = MLXSW_PCI_WQE_SIZE 1107 }; 1108 1109 static const struct mlxsw_pci_queue_ops mlxsw_pci_cq_ops = { 1110 .type = MLXSW_PCI_QUEUE_TYPE_CQ, 1111 .pre_init = mlxsw_pci_cq_pre_init, 1112 .init = mlxsw_pci_cq_init, 1113 .fini = mlxsw_pci_cq_fini, 1114 .elem_count_f = mlxsw_pci_cq_elem_count, 1115 .elem_size_f = mlxsw_pci_cq_elem_size 1116 }; 1117 1118 static const struct mlxsw_pci_queue_ops mlxsw_pci_eq_ops = { 1119 .type = MLXSW_PCI_QUEUE_TYPE_EQ, 1120 .init = mlxsw_pci_eq_init, 1121 .fini = mlxsw_pci_eq_fini, 1122 .elem_count = MLXSW_PCI_EQE_COUNT, 1123 .elem_size = MLXSW_PCI_EQE_SIZE 1124 }; 1125 1126 static int mlxsw_pci_queue_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 1127 const struct mlxsw_pci_queue_ops *q_ops, 1128 struct mlxsw_pci_queue *q, u8 q_num) 1129 { 1130 struct mlxsw_pci_mem_item *mem_item = &q->mem_item; 1131 int i; 1132 int err; 1133 1134 q->num = q_num; 1135 if (q_ops->pre_init) 1136 q_ops->pre_init(mlxsw_pci, q); 1137 1138 spin_lock_init(&q->lock); 1139 q->count = q_ops->elem_count_f ? q_ops->elem_count_f(q) : 1140 q_ops->elem_count; 1141 q->elem_size = q_ops->elem_size_f ? q_ops->elem_size_f(q) : 1142 q_ops->elem_size; 1143 q->type = q_ops->type; 1144 q->pci = mlxsw_pci; 1145 1146 mem_item->size = MLXSW_PCI_AQ_SIZE; 1147 mem_item->buf = dma_alloc_coherent(&mlxsw_pci->pdev->dev, 1148 mem_item->size, &mem_item->mapaddr, 1149 GFP_KERNEL); 1150 if (!mem_item->buf) 1151 return -ENOMEM; 1152 1153 q->elem_info = kcalloc(q->count, sizeof(*q->elem_info), GFP_KERNEL); 1154 if (!q->elem_info) { 1155 err = -ENOMEM; 1156 goto err_elem_info_alloc; 1157 } 1158 1159 /* Initialize dma mapped elements info elem_info for 1160 * future easy access. 1161 */ 1162 for (i = 0; i < q->count; i++) { 1163 struct mlxsw_pci_queue_elem_info *elem_info; 1164 1165 elem_info = mlxsw_pci_queue_elem_info_get(q, i); 1166 elem_info->elem = 1167 __mlxsw_pci_queue_elem_get(q, q->elem_size, i); 1168 } 1169 1170 mlxsw_cmd_mbox_zero(mbox); 1171 err = q_ops->init(mlxsw_pci, mbox, q); 1172 if (err) 1173 goto err_q_ops_init; 1174 return 0; 1175 1176 err_q_ops_init: 1177 kfree(q->elem_info); 1178 err_elem_info_alloc: 1179 dma_free_coherent(&mlxsw_pci->pdev->dev, mem_item->size, 1180 mem_item->buf, mem_item->mapaddr); 1181 return err; 1182 } 1183 1184 static void mlxsw_pci_queue_fini(struct mlxsw_pci *mlxsw_pci, 1185 const struct mlxsw_pci_queue_ops *q_ops, 1186 struct mlxsw_pci_queue *q) 1187 { 1188 struct mlxsw_pci_mem_item *mem_item = &q->mem_item; 1189 1190 q_ops->fini(mlxsw_pci, q); 1191 kfree(q->elem_info); 1192 dma_free_coherent(&mlxsw_pci->pdev->dev, mem_item->size, 1193 mem_item->buf, mem_item->mapaddr); 1194 } 1195 1196 static int mlxsw_pci_queue_group_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 1197 const struct mlxsw_pci_queue_ops *q_ops, 1198 u8 num_qs) 1199 { 1200 struct mlxsw_pci_queue_type_group *queue_group; 1201 int i; 1202 int err; 1203 1204 queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_ops->type); 1205 queue_group->q = kcalloc(num_qs, sizeof(*queue_group->q), GFP_KERNEL); 1206 if (!queue_group->q) 1207 return -ENOMEM; 1208 1209 for (i = 0; i < num_qs; i++) { 1210 err = mlxsw_pci_queue_init(mlxsw_pci, mbox, q_ops, 1211 &queue_group->q[i], i); 1212 if (err) 1213 goto err_queue_init; 1214 } 1215 queue_group->count = num_qs; 1216 1217 return 0; 1218 1219 err_queue_init: 1220 for (i--; i >= 0; i--) 1221 mlxsw_pci_queue_fini(mlxsw_pci, q_ops, &queue_group->q[i]); 1222 kfree(queue_group->q); 1223 return err; 1224 } 1225 1226 static void mlxsw_pci_queue_group_fini(struct mlxsw_pci *mlxsw_pci, 1227 const struct mlxsw_pci_queue_ops *q_ops) 1228 { 1229 struct mlxsw_pci_queue_type_group *queue_group; 1230 int i; 1231 1232 queue_group = mlxsw_pci_queue_type_group_get(mlxsw_pci, q_ops->type); 1233 for (i = 0; i < queue_group->count; i++) 1234 mlxsw_pci_queue_fini(mlxsw_pci, q_ops, &queue_group->q[i]); 1235 kfree(queue_group->q); 1236 } 1237 1238 static int mlxsw_pci_aqs_init(struct mlxsw_pci *mlxsw_pci, char *mbox) 1239 { 1240 struct pci_dev *pdev = mlxsw_pci->pdev; 1241 u8 num_sdqs; 1242 u8 sdq_log2sz; 1243 u8 num_rdqs; 1244 u8 rdq_log2sz; 1245 u8 num_cqs; 1246 u8 cq_log2sz; 1247 u8 cqv2_log2sz; 1248 u8 num_eqs; 1249 u8 eq_log2sz; 1250 int err; 1251 1252 mlxsw_cmd_mbox_zero(mbox); 1253 err = mlxsw_cmd_query_aq_cap(mlxsw_pci->core, mbox); 1254 if (err) 1255 return err; 1256 1257 num_sdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_sdqs_get(mbox); 1258 sdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_sdq_sz_get(mbox); 1259 num_rdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_rdqs_get(mbox); 1260 rdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_rdq_sz_get(mbox); 1261 num_cqs = mlxsw_cmd_mbox_query_aq_cap_max_num_cqs_get(mbox); 1262 cq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_cq_sz_get(mbox); 1263 cqv2_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_cqv2_sz_get(mbox); 1264 num_eqs = mlxsw_cmd_mbox_query_aq_cap_max_num_eqs_get(mbox); 1265 eq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_eq_sz_get(mbox); 1266 1267 if (num_sdqs + num_rdqs > num_cqs || 1268 num_sdqs < MLXSW_PCI_SDQS_MIN || 1269 num_cqs > MLXSW_PCI_CQS_MAX || num_eqs != MLXSW_PCI_EQS_MAX) { 1270 dev_err(&pdev->dev, "Unsupported number of queues\n"); 1271 return -EINVAL; 1272 } 1273 1274 if ((1 << sdq_log2sz != MLXSW_PCI_WQE_COUNT) || 1275 (1 << rdq_log2sz != MLXSW_PCI_WQE_COUNT) || 1276 (1 << cq_log2sz != MLXSW_PCI_CQE01_COUNT) || 1277 (mlxsw_pci->max_cqe_ver == MLXSW_PCI_CQE_V2 && 1278 (1 << cqv2_log2sz != MLXSW_PCI_CQE2_COUNT)) || 1279 (1 << eq_log2sz != MLXSW_PCI_EQE_COUNT)) { 1280 dev_err(&pdev->dev, "Unsupported number of async queue descriptors\n"); 1281 return -EINVAL; 1282 } 1283 1284 mlxsw_pci->num_cqs = num_cqs; 1285 mlxsw_pci->num_sdqs = num_sdqs; 1286 1287 err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_eq_ops, 1288 MLXSW_PCI_EQS_COUNT); 1289 if (err) { 1290 dev_err(&pdev->dev, "Failed to initialize event queues\n"); 1291 return err; 1292 } 1293 1294 err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_cq_ops, 1295 num_cqs); 1296 if (err) { 1297 dev_err(&pdev->dev, "Failed to initialize completion queues\n"); 1298 goto err_cqs_init; 1299 } 1300 1301 err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_sdq_ops, 1302 num_sdqs); 1303 if (err) { 1304 dev_err(&pdev->dev, "Failed to initialize send descriptor queues\n"); 1305 goto err_sdqs_init; 1306 } 1307 1308 err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_rdq_ops, 1309 num_rdqs); 1310 if (err) { 1311 dev_err(&pdev->dev, "Failed to initialize receive descriptor queues\n"); 1312 goto err_rdqs_init; 1313 } 1314 1315 return 0; 1316 1317 err_rdqs_init: 1318 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_sdq_ops); 1319 err_sdqs_init: 1320 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_cq_ops); 1321 err_cqs_init: 1322 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_eq_ops); 1323 return err; 1324 } 1325 1326 static void mlxsw_pci_aqs_fini(struct mlxsw_pci *mlxsw_pci) 1327 { 1328 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_rdq_ops); 1329 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_sdq_ops); 1330 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_cq_ops); 1331 mlxsw_pci_queue_group_fini(mlxsw_pci, &mlxsw_pci_eq_ops); 1332 } 1333 1334 static void 1335 mlxsw_pci_config_profile_swid_config(struct mlxsw_pci *mlxsw_pci, 1336 char *mbox, int index, 1337 const struct mlxsw_swid_config *swid) 1338 { 1339 u8 mask = 0; 1340 1341 if (swid->used_type) { 1342 mlxsw_cmd_mbox_config_profile_swid_config_type_set( 1343 mbox, index, swid->type); 1344 mask |= 1; 1345 } 1346 if (swid->used_properties) { 1347 mlxsw_cmd_mbox_config_profile_swid_config_properties_set( 1348 mbox, index, swid->properties); 1349 mask |= 2; 1350 } 1351 mlxsw_cmd_mbox_config_profile_swid_config_mask_set(mbox, index, mask); 1352 } 1353 1354 static int 1355 mlxsw_pci_profile_get_kvd_sizes(const struct mlxsw_pci *mlxsw_pci, 1356 const struct mlxsw_config_profile *profile, 1357 struct mlxsw_res *res) 1358 { 1359 u64 single_size, double_size, linear_size; 1360 int err; 1361 1362 err = mlxsw_core_kvd_sizes_get(mlxsw_pci->core, profile, 1363 &single_size, &double_size, 1364 &linear_size); 1365 if (err) 1366 return err; 1367 1368 MLXSW_RES_SET(res, KVD_SINGLE_SIZE, single_size); 1369 MLXSW_RES_SET(res, KVD_DOUBLE_SIZE, double_size); 1370 MLXSW_RES_SET(res, KVD_LINEAR_SIZE, linear_size); 1371 1372 return 0; 1373 } 1374 1375 static int mlxsw_pci_config_profile(struct mlxsw_pci *mlxsw_pci, char *mbox, 1376 const struct mlxsw_config_profile *profile, 1377 struct mlxsw_res *res) 1378 { 1379 int i; 1380 int err; 1381 1382 mlxsw_cmd_mbox_zero(mbox); 1383 1384 if (profile->used_max_vepa_channels) { 1385 mlxsw_cmd_mbox_config_profile_set_max_vepa_channels_set( 1386 mbox, 1); 1387 mlxsw_cmd_mbox_config_profile_max_vepa_channels_set( 1388 mbox, profile->max_vepa_channels); 1389 } 1390 if (profile->used_max_lag) { 1391 mlxsw_cmd_mbox_config_profile_set_max_lag_set(mbox, 1); 1392 mlxsw_cmd_mbox_config_profile_max_lag_set(mbox, 1393 profile->max_lag); 1394 } 1395 if (profile->used_max_mid) { 1396 mlxsw_cmd_mbox_config_profile_set_max_mid_set( 1397 mbox, 1); 1398 mlxsw_cmd_mbox_config_profile_max_mid_set( 1399 mbox, profile->max_mid); 1400 } 1401 if (profile->used_max_pgt) { 1402 mlxsw_cmd_mbox_config_profile_set_max_pgt_set( 1403 mbox, 1); 1404 mlxsw_cmd_mbox_config_profile_max_pgt_set( 1405 mbox, profile->max_pgt); 1406 } 1407 if (profile->used_max_system_port) { 1408 mlxsw_cmd_mbox_config_profile_set_max_system_port_set( 1409 mbox, 1); 1410 mlxsw_cmd_mbox_config_profile_max_system_port_set( 1411 mbox, profile->max_system_port); 1412 } 1413 if (profile->used_max_vlan_groups) { 1414 mlxsw_cmd_mbox_config_profile_set_max_vlan_groups_set( 1415 mbox, 1); 1416 mlxsw_cmd_mbox_config_profile_max_vlan_groups_set( 1417 mbox, profile->max_vlan_groups); 1418 } 1419 if (profile->used_max_regions) { 1420 mlxsw_cmd_mbox_config_profile_set_max_regions_set( 1421 mbox, 1); 1422 mlxsw_cmd_mbox_config_profile_max_regions_set( 1423 mbox, profile->max_regions); 1424 } 1425 if (profile->used_flood_tables) { 1426 mlxsw_cmd_mbox_config_profile_set_flood_tables_set( 1427 mbox, 1); 1428 mlxsw_cmd_mbox_config_profile_max_flood_tables_set( 1429 mbox, profile->max_flood_tables); 1430 mlxsw_cmd_mbox_config_profile_max_vid_flood_tables_set( 1431 mbox, profile->max_vid_flood_tables); 1432 mlxsw_cmd_mbox_config_profile_max_fid_offset_flood_tables_set( 1433 mbox, profile->max_fid_offset_flood_tables); 1434 mlxsw_cmd_mbox_config_profile_fid_offset_flood_table_size_set( 1435 mbox, profile->fid_offset_flood_table_size); 1436 mlxsw_cmd_mbox_config_profile_max_fid_flood_tables_set( 1437 mbox, profile->max_fid_flood_tables); 1438 mlxsw_cmd_mbox_config_profile_fid_flood_table_size_set( 1439 mbox, profile->fid_flood_table_size); 1440 } 1441 if (profile->flood_mode_prefer_cff && mlxsw_pci->cff_support) { 1442 enum mlxsw_cmd_mbox_config_profile_flood_mode flood_mode = 1443 MLXSW_CMD_MBOX_CONFIG_PROFILE_FLOOD_MODE_CFF; 1444 1445 mlxsw_cmd_mbox_config_profile_set_flood_mode_set(mbox, 1); 1446 mlxsw_cmd_mbox_config_profile_flood_mode_set(mbox, flood_mode); 1447 mlxsw_pci->flood_mode = flood_mode; 1448 } else if (profile->used_flood_mode) { 1449 mlxsw_cmd_mbox_config_profile_set_flood_mode_set( 1450 mbox, 1); 1451 mlxsw_cmd_mbox_config_profile_flood_mode_set( 1452 mbox, profile->flood_mode); 1453 mlxsw_pci->flood_mode = profile->flood_mode; 1454 } else { 1455 WARN_ON(1); 1456 return -EINVAL; 1457 } 1458 if (profile->used_max_ib_mc) { 1459 mlxsw_cmd_mbox_config_profile_set_max_ib_mc_set( 1460 mbox, 1); 1461 mlxsw_cmd_mbox_config_profile_max_ib_mc_set( 1462 mbox, profile->max_ib_mc); 1463 } 1464 if (profile->used_max_pkey) { 1465 mlxsw_cmd_mbox_config_profile_set_max_pkey_set( 1466 mbox, 1); 1467 mlxsw_cmd_mbox_config_profile_max_pkey_set( 1468 mbox, profile->max_pkey); 1469 } 1470 if (profile->used_ar_sec) { 1471 mlxsw_cmd_mbox_config_profile_set_ar_sec_set( 1472 mbox, 1); 1473 mlxsw_cmd_mbox_config_profile_ar_sec_set( 1474 mbox, profile->ar_sec); 1475 } 1476 if (profile->used_adaptive_routing_group_cap) { 1477 mlxsw_cmd_mbox_config_profile_set_adaptive_routing_group_cap_set( 1478 mbox, 1); 1479 mlxsw_cmd_mbox_config_profile_adaptive_routing_group_cap_set( 1480 mbox, profile->adaptive_routing_group_cap); 1481 } 1482 if (profile->used_ubridge) { 1483 mlxsw_cmd_mbox_config_profile_set_ubridge_set(mbox, 1); 1484 mlxsw_cmd_mbox_config_profile_ubridge_set(mbox, 1485 profile->ubridge); 1486 } 1487 if (profile->used_kvd_sizes && MLXSW_RES_VALID(res, KVD_SIZE)) { 1488 err = mlxsw_pci_profile_get_kvd_sizes(mlxsw_pci, profile, res); 1489 if (err) 1490 return err; 1491 1492 mlxsw_cmd_mbox_config_profile_set_kvd_linear_size_set(mbox, 1); 1493 mlxsw_cmd_mbox_config_profile_kvd_linear_size_set(mbox, 1494 MLXSW_RES_GET(res, KVD_LINEAR_SIZE)); 1495 mlxsw_cmd_mbox_config_profile_set_kvd_hash_single_size_set(mbox, 1496 1); 1497 mlxsw_cmd_mbox_config_profile_kvd_hash_single_size_set(mbox, 1498 MLXSW_RES_GET(res, KVD_SINGLE_SIZE)); 1499 mlxsw_cmd_mbox_config_profile_set_kvd_hash_double_size_set( 1500 mbox, 1); 1501 mlxsw_cmd_mbox_config_profile_kvd_hash_double_size_set(mbox, 1502 MLXSW_RES_GET(res, KVD_DOUBLE_SIZE)); 1503 } 1504 1505 for (i = 0; i < MLXSW_CONFIG_PROFILE_SWID_COUNT; i++) 1506 mlxsw_pci_config_profile_swid_config(mlxsw_pci, mbox, i, 1507 &profile->swid_config[i]); 1508 1509 if (mlxsw_pci->max_cqe_ver > MLXSW_PCI_CQE_V0) { 1510 mlxsw_cmd_mbox_config_profile_set_cqe_version_set(mbox, 1); 1511 mlxsw_cmd_mbox_config_profile_cqe_version_set(mbox, 1); 1512 } 1513 1514 if (profile->used_cqe_time_stamp_type) { 1515 mlxsw_cmd_mbox_config_profile_set_cqe_time_stamp_type_set(mbox, 1516 1); 1517 mlxsw_cmd_mbox_config_profile_cqe_time_stamp_type_set(mbox, 1518 profile->cqe_time_stamp_type); 1519 } 1520 1521 if (profile->lag_mode_prefer_sw && mlxsw_pci->lag_mode_support) { 1522 enum mlxsw_cmd_mbox_config_profile_lag_mode lag_mode = 1523 MLXSW_CMD_MBOX_CONFIG_PROFILE_LAG_MODE_SW; 1524 1525 mlxsw_cmd_mbox_config_profile_set_lag_mode_set(mbox, 1); 1526 mlxsw_cmd_mbox_config_profile_lag_mode_set(mbox, lag_mode); 1527 mlxsw_pci->lag_mode = lag_mode; 1528 } else { 1529 mlxsw_pci->lag_mode = MLXSW_CMD_MBOX_CONFIG_PROFILE_LAG_MODE_FW; 1530 } 1531 return mlxsw_cmd_config_profile_set(mlxsw_pci->core, mbox); 1532 } 1533 1534 static int mlxsw_pci_boardinfo(struct mlxsw_pci *mlxsw_pci, char *mbox) 1535 { 1536 struct mlxsw_bus_info *bus_info = &mlxsw_pci->bus_info; 1537 int err; 1538 1539 mlxsw_cmd_mbox_zero(mbox); 1540 err = mlxsw_cmd_boardinfo(mlxsw_pci->core, mbox); 1541 if (err) 1542 return err; 1543 mlxsw_cmd_mbox_boardinfo_vsd_memcpy_from(mbox, bus_info->vsd); 1544 mlxsw_cmd_mbox_boardinfo_psid_memcpy_from(mbox, bus_info->psid); 1545 return 0; 1546 } 1547 1548 static int mlxsw_pci_fw_area_init(struct mlxsw_pci *mlxsw_pci, char *mbox, 1549 u16 num_pages) 1550 { 1551 struct mlxsw_pci_mem_item *mem_item; 1552 int nent = 0; 1553 int i; 1554 int err; 1555 1556 mlxsw_pci->fw_area.items = kcalloc(num_pages, sizeof(*mem_item), 1557 GFP_KERNEL); 1558 if (!mlxsw_pci->fw_area.items) 1559 return -ENOMEM; 1560 mlxsw_pci->fw_area.count = num_pages; 1561 1562 mlxsw_cmd_mbox_zero(mbox); 1563 for (i = 0; i < num_pages; i++) { 1564 mem_item = &mlxsw_pci->fw_area.items[i]; 1565 1566 mem_item->size = MLXSW_PCI_PAGE_SIZE; 1567 mem_item->buf = dma_alloc_coherent(&mlxsw_pci->pdev->dev, 1568 mem_item->size, 1569 &mem_item->mapaddr, GFP_KERNEL); 1570 if (!mem_item->buf) { 1571 err = -ENOMEM; 1572 goto err_alloc; 1573 } 1574 mlxsw_cmd_mbox_map_fa_pa_set(mbox, nent, mem_item->mapaddr); 1575 mlxsw_cmd_mbox_map_fa_log2size_set(mbox, nent, 0); /* 1 page */ 1576 if (++nent == MLXSW_CMD_MAP_FA_VPM_ENTRIES_MAX) { 1577 err = mlxsw_cmd_map_fa(mlxsw_pci->core, mbox, nent); 1578 if (err) 1579 goto err_cmd_map_fa; 1580 nent = 0; 1581 mlxsw_cmd_mbox_zero(mbox); 1582 } 1583 } 1584 1585 if (nent) { 1586 err = mlxsw_cmd_map_fa(mlxsw_pci->core, mbox, nent); 1587 if (err) 1588 goto err_cmd_map_fa; 1589 } 1590 1591 return 0; 1592 1593 err_cmd_map_fa: 1594 err_alloc: 1595 for (i--; i >= 0; i--) { 1596 mem_item = &mlxsw_pci->fw_area.items[i]; 1597 1598 dma_free_coherent(&mlxsw_pci->pdev->dev, mem_item->size, 1599 mem_item->buf, mem_item->mapaddr); 1600 } 1601 kfree(mlxsw_pci->fw_area.items); 1602 return err; 1603 } 1604 1605 static void mlxsw_pci_fw_area_fini(struct mlxsw_pci *mlxsw_pci) 1606 { 1607 struct mlxsw_pci_mem_item *mem_item; 1608 int i; 1609 1610 mlxsw_cmd_unmap_fa(mlxsw_pci->core); 1611 1612 for (i = 0; i < mlxsw_pci->fw_area.count; i++) { 1613 mem_item = &mlxsw_pci->fw_area.items[i]; 1614 1615 dma_free_coherent(&mlxsw_pci->pdev->dev, mem_item->size, 1616 mem_item->buf, mem_item->mapaddr); 1617 } 1618 kfree(mlxsw_pci->fw_area.items); 1619 } 1620 1621 static irqreturn_t mlxsw_pci_eq_irq_handler(int irq, void *dev_id) 1622 { 1623 struct mlxsw_pci *mlxsw_pci = dev_id; 1624 struct mlxsw_pci_queue *q; 1625 1626 q = mlxsw_pci_eq_get(mlxsw_pci); 1627 tasklet_schedule(&q->u.eq.tasklet); 1628 return IRQ_HANDLED; 1629 } 1630 1631 static int mlxsw_pci_mbox_alloc(struct mlxsw_pci *mlxsw_pci, 1632 struct mlxsw_pci_mem_item *mbox) 1633 { 1634 struct pci_dev *pdev = mlxsw_pci->pdev; 1635 int err = 0; 1636 1637 mbox->size = MLXSW_CMD_MBOX_SIZE; 1638 mbox->buf = dma_alloc_coherent(&pdev->dev, MLXSW_CMD_MBOX_SIZE, 1639 &mbox->mapaddr, GFP_KERNEL); 1640 if (!mbox->buf) { 1641 dev_err(&pdev->dev, "Failed allocating memory for mailbox\n"); 1642 err = -ENOMEM; 1643 } 1644 1645 return err; 1646 } 1647 1648 static void mlxsw_pci_mbox_free(struct mlxsw_pci *mlxsw_pci, 1649 struct mlxsw_pci_mem_item *mbox) 1650 { 1651 struct pci_dev *pdev = mlxsw_pci->pdev; 1652 1653 dma_free_coherent(&pdev->dev, MLXSW_CMD_MBOX_SIZE, mbox->buf, 1654 mbox->mapaddr); 1655 } 1656 1657 static int mlxsw_pci_sys_ready_wait(struct mlxsw_pci *mlxsw_pci, 1658 const struct pci_device_id *id, 1659 u32 *p_sys_status) 1660 { 1661 unsigned long end; 1662 u32 val; 1663 1664 /* We must wait for the HW to become responsive. */ 1665 msleep(MLXSW_PCI_SW_RESET_WAIT_MSECS); 1666 1667 end = jiffies + msecs_to_jiffies(MLXSW_PCI_SW_RESET_TIMEOUT_MSECS); 1668 do { 1669 val = mlxsw_pci_read32(mlxsw_pci, FW_READY); 1670 if ((val & MLXSW_PCI_FW_READY_MASK) == MLXSW_PCI_FW_READY_MAGIC) 1671 return 0; 1672 cond_resched(); 1673 } while (time_before(jiffies, end)); 1674 1675 *p_sys_status = val & MLXSW_PCI_FW_READY_MASK; 1676 1677 return -EBUSY; 1678 } 1679 1680 static int mlxsw_pci_reset_at_pci_disable(struct mlxsw_pci *mlxsw_pci) 1681 { 1682 struct pci_dev *pdev = mlxsw_pci->pdev; 1683 char mrsr_pl[MLXSW_REG_MRSR_LEN]; 1684 int err; 1685 1686 mlxsw_reg_mrsr_pack(mrsr_pl, 1687 MLXSW_REG_MRSR_COMMAND_RESET_AT_PCI_DISABLE); 1688 err = mlxsw_reg_write(mlxsw_pci->core, MLXSW_REG(mrsr), mrsr_pl); 1689 if (err) 1690 return err; 1691 1692 device_lock_assert(&pdev->dev); 1693 1694 pci_cfg_access_lock(pdev); 1695 pci_save_state(pdev); 1696 1697 err = __pci_reset_function_locked(pdev); 1698 if (err) 1699 pci_err(pdev, "PCI function reset failed with %d\n", err); 1700 1701 pci_restore_state(pdev); 1702 pci_cfg_access_unlock(pdev); 1703 1704 return err; 1705 } 1706 1707 static int mlxsw_pci_reset_sw(struct mlxsw_pci *mlxsw_pci) 1708 { 1709 char mrsr_pl[MLXSW_REG_MRSR_LEN]; 1710 1711 mlxsw_reg_mrsr_pack(mrsr_pl, MLXSW_REG_MRSR_COMMAND_SOFTWARE_RESET); 1712 return mlxsw_reg_write(mlxsw_pci->core, MLXSW_REG(mrsr), mrsr_pl); 1713 } 1714 1715 static int 1716 mlxsw_pci_reset(struct mlxsw_pci *mlxsw_pci, const struct pci_device_id *id) 1717 { 1718 struct pci_dev *pdev = mlxsw_pci->pdev; 1719 char mcam_pl[MLXSW_REG_MCAM_LEN]; 1720 bool pci_reset_supported = false; 1721 u32 sys_status; 1722 int err; 1723 1724 err = mlxsw_pci_sys_ready_wait(mlxsw_pci, id, &sys_status); 1725 if (err) { 1726 dev_err(&pdev->dev, "Failed to reach system ready status before reset. Status is 0x%x\n", 1727 sys_status); 1728 return err; 1729 } 1730 1731 /* PCI core already issued a PCI reset, do not issue another reset. */ 1732 if (mlxsw_pci->skip_reset) 1733 return 0; 1734 1735 mlxsw_reg_mcam_pack(mcam_pl, 1736 MLXSW_REG_MCAM_FEATURE_GROUP_ENHANCED_FEATURES); 1737 err = mlxsw_reg_query(mlxsw_pci->core, MLXSW_REG(mcam), mcam_pl); 1738 if (!err) 1739 mlxsw_reg_mcam_unpack(mcam_pl, MLXSW_REG_MCAM_PCI_RESET, 1740 &pci_reset_supported); 1741 1742 if (pci_reset_supported) { 1743 pci_dbg(pdev, "Starting PCI reset flow\n"); 1744 err = mlxsw_pci_reset_at_pci_disable(mlxsw_pci); 1745 } else { 1746 pci_dbg(pdev, "Starting software reset flow\n"); 1747 err = mlxsw_pci_reset_sw(mlxsw_pci); 1748 } 1749 if (err) 1750 return err; 1751 1752 err = mlxsw_pci_sys_ready_wait(mlxsw_pci, id, &sys_status); 1753 if (err) { 1754 dev_err(&pdev->dev, "Failed to reach system ready status after reset. Status is 0x%x\n", 1755 sys_status); 1756 return err; 1757 } 1758 1759 return 0; 1760 } 1761 1762 static int mlxsw_pci_alloc_irq_vectors(struct mlxsw_pci *mlxsw_pci) 1763 { 1764 int err; 1765 1766 err = pci_alloc_irq_vectors(mlxsw_pci->pdev, 1, 1, PCI_IRQ_MSIX); 1767 if (err < 0) 1768 dev_err(&mlxsw_pci->pdev->dev, "MSI-X init failed\n"); 1769 return err; 1770 } 1771 1772 static void mlxsw_pci_free_irq_vectors(struct mlxsw_pci *mlxsw_pci) 1773 { 1774 pci_free_irq_vectors(mlxsw_pci->pdev); 1775 } 1776 1777 static int mlxsw_pci_init(void *bus_priv, struct mlxsw_core *mlxsw_core, 1778 const struct mlxsw_config_profile *profile, 1779 struct mlxsw_res *res) 1780 { 1781 struct mlxsw_pci *mlxsw_pci = bus_priv; 1782 struct pci_dev *pdev = mlxsw_pci->pdev; 1783 char *mbox; 1784 u16 num_pages; 1785 int err; 1786 1787 mlxsw_pci->core = mlxsw_core; 1788 1789 mbox = mlxsw_cmd_mbox_alloc(); 1790 if (!mbox) 1791 return -ENOMEM; 1792 1793 err = mlxsw_pci_reset(mlxsw_pci, mlxsw_pci->id); 1794 if (err) 1795 goto err_reset; 1796 1797 err = mlxsw_pci_alloc_irq_vectors(mlxsw_pci); 1798 if (err < 0) { 1799 dev_err(&pdev->dev, "MSI-X init failed\n"); 1800 goto err_alloc_irq; 1801 } 1802 1803 err = mlxsw_cmd_query_fw(mlxsw_core, mbox); 1804 if (err) 1805 goto err_query_fw; 1806 1807 mlxsw_pci->bus_info.fw_rev.major = 1808 mlxsw_cmd_mbox_query_fw_fw_rev_major_get(mbox); 1809 mlxsw_pci->bus_info.fw_rev.minor = 1810 mlxsw_cmd_mbox_query_fw_fw_rev_minor_get(mbox); 1811 mlxsw_pci->bus_info.fw_rev.subminor = 1812 mlxsw_cmd_mbox_query_fw_fw_rev_subminor_get(mbox); 1813 1814 if (mlxsw_cmd_mbox_query_fw_cmd_interface_rev_get(mbox) != 1) { 1815 dev_err(&pdev->dev, "Unsupported cmd interface revision ID queried from hw\n"); 1816 err = -EINVAL; 1817 goto err_iface_rev; 1818 } 1819 if (mlxsw_cmd_mbox_query_fw_doorbell_page_bar_get(mbox) != 0) { 1820 dev_err(&pdev->dev, "Unsupported doorbell page bar queried from hw\n"); 1821 err = -EINVAL; 1822 goto err_doorbell_page_bar; 1823 } 1824 1825 mlxsw_pci->doorbell_offset = 1826 mlxsw_cmd_mbox_query_fw_doorbell_page_offset_get(mbox); 1827 1828 if (mlxsw_cmd_mbox_query_fw_fr_rn_clk_bar_get(mbox) != 0) { 1829 dev_err(&pdev->dev, "Unsupported free running clock BAR queried from hw\n"); 1830 err = -EINVAL; 1831 goto err_fr_rn_clk_bar; 1832 } 1833 1834 mlxsw_pci->free_running_clock_offset = 1835 mlxsw_cmd_mbox_query_fw_free_running_clock_offset_get(mbox); 1836 1837 if (mlxsw_cmd_mbox_query_fw_utc_sec_bar_get(mbox) != 0) { 1838 dev_err(&pdev->dev, "Unsupported UTC sec BAR queried from hw\n"); 1839 err = -EINVAL; 1840 goto err_utc_sec_bar; 1841 } 1842 1843 mlxsw_pci->utc_sec_offset = 1844 mlxsw_cmd_mbox_query_fw_utc_sec_offset_get(mbox); 1845 1846 if (mlxsw_cmd_mbox_query_fw_utc_nsec_bar_get(mbox) != 0) { 1847 dev_err(&pdev->dev, "Unsupported UTC nsec BAR queried from hw\n"); 1848 err = -EINVAL; 1849 goto err_utc_nsec_bar; 1850 } 1851 1852 mlxsw_pci->utc_nsec_offset = 1853 mlxsw_cmd_mbox_query_fw_utc_nsec_offset_get(mbox); 1854 1855 mlxsw_pci->lag_mode_support = 1856 mlxsw_cmd_mbox_query_fw_lag_mode_support_get(mbox); 1857 mlxsw_pci->cff_support = 1858 mlxsw_cmd_mbox_query_fw_cff_support_get(mbox); 1859 1860 num_pages = mlxsw_cmd_mbox_query_fw_fw_pages_get(mbox); 1861 err = mlxsw_pci_fw_area_init(mlxsw_pci, mbox, num_pages); 1862 if (err) 1863 goto err_fw_area_init; 1864 1865 err = mlxsw_pci_boardinfo(mlxsw_pci, mbox); 1866 if (err) 1867 goto err_boardinfo; 1868 1869 err = mlxsw_core_resources_query(mlxsw_core, mbox, res); 1870 if (err) 1871 goto err_query_resources; 1872 1873 if (MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V2) && 1874 MLXSW_CORE_RES_GET(mlxsw_core, CQE_V2)) 1875 mlxsw_pci->max_cqe_ver = MLXSW_PCI_CQE_V2; 1876 else if (MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V1) && 1877 MLXSW_CORE_RES_GET(mlxsw_core, CQE_V1)) 1878 mlxsw_pci->max_cqe_ver = MLXSW_PCI_CQE_V1; 1879 else if ((MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V0) && 1880 MLXSW_CORE_RES_GET(mlxsw_core, CQE_V0)) || 1881 !MLXSW_CORE_RES_VALID(mlxsw_core, CQE_V0)) { 1882 mlxsw_pci->max_cqe_ver = MLXSW_PCI_CQE_V0; 1883 } else { 1884 dev_err(&pdev->dev, "Invalid supported CQE version combination reported\n"); 1885 goto err_cqe_v_check; 1886 } 1887 1888 err = mlxsw_pci_config_profile(mlxsw_pci, mbox, profile, res); 1889 if (err) 1890 goto err_config_profile; 1891 1892 /* Some resources depend on details of config_profile, such as unified 1893 * bridge model. Query the resources again to get correct values. 1894 */ 1895 err = mlxsw_core_resources_query(mlxsw_core, mbox, res); 1896 if (err) 1897 goto err_requery_resources; 1898 1899 err = mlxsw_pci_napi_devs_init(mlxsw_pci); 1900 if (err) 1901 goto err_napi_devs_init; 1902 1903 err = mlxsw_pci_aqs_init(mlxsw_pci, mbox); 1904 if (err) 1905 goto err_aqs_init; 1906 1907 err = request_irq(pci_irq_vector(pdev, 0), 1908 mlxsw_pci_eq_irq_handler, 0, 1909 mlxsw_pci->bus_info.device_kind, mlxsw_pci); 1910 if (err) { 1911 dev_err(&pdev->dev, "IRQ request failed\n"); 1912 goto err_request_eq_irq; 1913 } 1914 1915 goto mbox_put; 1916 1917 err_request_eq_irq: 1918 mlxsw_pci_aqs_fini(mlxsw_pci); 1919 err_aqs_init: 1920 mlxsw_pci_napi_devs_fini(mlxsw_pci); 1921 err_napi_devs_init: 1922 err_requery_resources: 1923 err_config_profile: 1924 err_cqe_v_check: 1925 err_query_resources: 1926 err_boardinfo: 1927 mlxsw_pci_fw_area_fini(mlxsw_pci); 1928 err_fw_area_init: 1929 err_utc_nsec_bar: 1930 err_utc_sec_bar: 1931 err_fr_rn_clk_bar: 1932 err_doorbell_page_bar: 1933 err_iface_rev: 1934 err_query_fw: 1935 mlxsw_pci_free_irq_vectors(mlxsw_pci); 1936 err_alloc_irq: 1937 err_reset: 1938 mbox_put: 1939 mlxsw_cmd_mbox_free(mbox); 1940 return err; 1941 } 1942 1943 static void mlxsw_pci_fini(void *bus_priv) 1944 { 1945 struct mlxsw_pci *mlxsw_pci = bus_priv; 1946 1947 free_irq(pci_irq_vector(mlxsw_pci->pdev, 0), mlxsw_pci); 1948 mlxsw_pci_aqs_fini(mlxsw_pci); 1949 mlxsw_pci_napi_devs_fini(mlxsw_pci); 1950 mlxsw_pci_fw_area_fini(mlxsw_pci); 1951 mlxsw_pci_free_irq_vectors(mlxsw_pci); 1952 } 1953 1954 static struct mlxsw_pci_queue * 1955 mlxsw_pci_sdq_pick(struct mlxsw_pci *mlxsw_pci, 1956 const struct mlxsw_tx_info *tx_info) 1957 { 1958 u8 ctl_sdq_count = mlxsw_pci->num_sdqs - 1; 1959 u8 sdqn; 1960 1961 if (tx_info->is_emad) { 1962 sdqn = MLXSW_PCI_SDQ_EMAD_INDEX; 1963 } else { 1964 BUILD_BUG_ON(MLXSW_PCI_SDQ_EMAD_INDEX != 0); 1965 sdqn = 1 + (tx_info->local_port % ctl_sdq_count); 1966 } 1967 1968 return mlxsw_pci_sdq_get(mlxsw_pci, sdqn); 1969 } 1970 1971 static bool mlxsw_pci_skb_transmit_busy(void *bus_priv, 1972 const struct mlxsw_tx_info *tx_info) 1973 { 1974 struct mlxsw_pci *mlxsw_pci = bus_priv; 1975 struct mlxsw_pci_queue *q = mlxsw_pci_sdq_pick(mlxsw_pci, tx_info); 1976 1977 return !mlxsw_pci_queue_elem_info_producer_get(q); 1978 } 1979 1980 static int mlxsw_pci_skb_transmit(void *bus_priv, struct sk_buff *skb, 1981 const struct mlxsw_tx_info *tx_info) 1982 { 1983 struct mlxsw_pci *mlxsw_pci = bus_priv; 1984 struct mlxsw_pci_queue *q; 1985 struct mlxsw_pci_queue_elem_info *elem_info; 1986 char *wqe; 1987 int i; 1988 int err; 1989 1990 if (skb_shinfo(skb)->nr_frags > MLXSW_PCI_WQE_SG_ENTRIES - 1) { 1991 err = skb_linearize(skb); 1992 if (err) 1993 return err; 1994 } 1995 1996 q = mlxsw_pci_sdq_pick(mlxsw_pci, tx_info); 1997 spin_lock_bh(&q->lock); 1998 elem_info = mlxsw_pci_queue_elem_info_producer_get(q); 1999 if (!elem_info) { 2000 /* queue is full */ 2001 err = -EAGAIN; 2002 goto unlock; 2003 } 2004 mlxsw_skb_cb(skb)->tx_info = *tx_info; 2005 elem_info->sdq.skb = skb; 2006 2007 wqe = elem_info->elem; 2008 mlxsw_pci_wqe_c_set(wqe, 1); /* always report completion */ 2009 mlxsw_pci_wqe_lp_set(wqe, 0); 2010 mlxsw_pci_wqe_type_set(wqe, MLXSW_PCI_WQE_TYPE_ETHERNET); 2011 2012 err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, 0, skb->data, 2013 skb_headlen(skb), DMA_TO_DEVICE); 2014 if (err) 2015 goto unlock; 2016 2017 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 2018 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2019 2020 err = mlxsw_pci_wqe_frag_map(mlxsw_pci, wqe, i + 1, 2021 skb_frag_address(frag), 2022 skb_frag_size(frag), 2023 DMA_TO_DEVICE); 2024 if (err) 2025 goto unmap_frags; 2026 } 2027 2028 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) 2029 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2030 2031 /* Set unused sq entries byte count to zero. */ 2032 for (i++; i < MLXSW_PCI_WQE_SG_ENTRIES; i++) 2033 mlxsw_pci_wqe_byte_count_set(wqe, i, 0); 2034 2035 /* Everything is set up, ring producer doorbell to get HW going */ 2036 q->producer_counter++; 2037 mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); 2038 2039 goto unlock; 2040 2041 unmap_frags: 2042 for (; i >= 0; i--) 2043 mlxsw_pci_wqe_frag_unmap(mlxsw_pci, wqe, i, DMA_TO_DEVICE); 2044 unlock: 2045 spin_unlock_bh(&q->lock); 2046 return err; 2047 } 2048 2049 static int mlxsw_pci_cmd_exec(void *bus_priv, u16 opcode, u8 opcode_mod, 2050 u32 in_mod, bool out_mbox_direct, 2051 char *in_mbox, size_t in_mbox_size, 2052 char *out_mbox, size_t out_mbox_size, 2053 u8 *p_status) 2054 { 2055 struct mlxsw_pci *mlxsw_pci = bus_priv; 2056 dma_addr_t in_mapaddr = 0, out_mapaddr = 0; 2057 unsigned long timeout = msecs_to_jiffies(MLXSW_PCI_CIR_TIMEOUT_MSECS); 2058 unsigned long end; 2059 bool wait_done; 2060 int err; 2061 2062 *p_status = MLXSW_CMD_STATUS_OK; 2063 2064 err = mutex_lock_interruptible(&mlxsw_pci->cmd.lock); 2065 if (err) 2066 return err; 2067 2068 if (in_mbox) { 2069 memcpy(mlxsw_pci->cmd.in_mbox.buf, in_mbox, in_mbox_size); 2070 in_mapaddr = mlxsw_pci->cmd.in_mbox.mapaddr; 2071 } 2072 mlxsw_pci_write32(mlxsw_pci, CIR_IN_PARAM_HI, upper_32_bits(in_mapaddr)); 2073 mlxsw_pci_write32(mlxsw_pci, CIR_IN_PARAM_LO, lower_32_bits(in_mapaddr)); 2074 2075 if (out_mbox) 2076 out_mapaddr = mlxsw_pci->cmd.out_mbox.mapaddr; 2077 mlxsw_pci_write32(mlxsw_pci, CIR_OUT_PARAM_HI, upper_32_bits(out_mapaddr)); 2078 mlxsw_pci_write32(mlxsw_pci, CIR_OUT_PARAM_LO, lower_32_bits(out_mapaddr)); 2079 2080 mlxsw_pci_write32(mlxsw_pci, CIR_IN_MODIFIER, in_mod); 2081 mlxsw_pci_write32(mlxsw_pci, CIR_TOKEN, 0); 2082 2083 wait_done = false; 2084 2085 wmb(); /* all needs to be written before we write control register */ 2086 mlxsw_pci_write32(mlxsw_pci, CIR_CTRL, 2087 MLXSW_PCI_CIR_CTRL_GO_BIT | 2088 (opcode_mod << MLXSW_PCI_CIR_CTRL_OPCODE_MOD_SHIFT) | 2089 opcode); 2090 2091 end = jiffies + timeout; 2092 do { 2093 u32 ctrl = mlxsw_pci_read32(mlxsw_pci, CIR_CTRL); 2094 2095 if (!(ctrl & MLXSW_PCI_CIR_CTRL_GO_BIT)) { 2096 wait_done = true; 2097 *p_status = ctrl >> MLXSW_PCI_CIR_CTRL_STATUS_SHIFT; 2098 break; 2099 } 2100 cond_resched(); 2101 } while (time_before(jiffies, end)); 2102 2103 err = 0; 2104 if (wait_done) { 2105 if (*p_status) 2106 err = -EIO; 2107 } else { 2108 err = -ETIMEDOUT; 2109 } 2110 2111 if (!err && out_mbox && out_mbox_direct) { 2112 /* Some commands don't use output param as address to mailbox 2113 * but they store output directly into registers. In that case, 2114 * copy registers into mbox buffer. 2115 */ 2116 __be32 tmp; 2117 2118 tmp = cpu_to_be32(mlxsw_pci_read32(mlxsw_pci, 2119 CIR_OUT_PARAM_HI)); 2120 memcpy(out_mbox, &tmp, sizeof(tmp)); 2121 tmp = cpu_to_be32(mlxsw_pci_read32(mlxsw_pci, 2122 CIR_OUT_PARAM_LO)); 2123 memcpy(out_mbox + sizeof(tmp), &tmp, sizeof(tmp)); 2124 } else if (!err && out_mbox) { 2125 memcpy(out_mbox, mlxsw_pci->cmd.out_mbox.buf, out_mbox_size); 2126 } 2127 2128 mutex_unlock(&mlxsw_pci->cmd.lock); 2129 2130 return err; 2131 } 2132 2133 static u32 mlxsw_pci_read_frc_h(void *bus_priv) 2134 { 2135 struct mlxsw_pci *mlxsw_pci = bus_priv; 2136 u64 frc_offset_h; 2137 2138 frc_offset_h = mlxsw_pci->free_running_clock_offset; 2139 return mlxsw_pci_read32_off(mlxsw_pci, frc_offset_h); 2140 } 2141 2142 static u32 mlxsw_pci_read_frc_l(void *bus_priv) 2143 { 2144 struct mlxsw_pci *mlxsw_pci = bus_priv; 2145 u64 frc_offset_l; 2146 2147 frc_offset_l = mlxsw_pci->free_running_clock_offset + 4; 2148 return mlxsw_pci_read32_off(mlxsw_pci, frc_offset_l); 2149 } 2150 2151 static u32 mlxsw_pci_read_utc_sec(void *bus_priv) 2152 { 2153 struct mlxsw_pci *mlxsw_pci = bus_priv; 2154 2155 return mlxsw_pci_read32_off(mlxsw_pci, mlxsw_pci->utc_sec_offset); 2156 } 2157 2158 static u32 mlxsw_pci_read_utc_nsec(void *bus_priv) 2159 { 2160 struct mlxsw_pci *mlxsw_pci = bus_priv; 2161 2162 return mlxsw_pci_read32_off(mlxsw_pci, mlxsw_pci->utc_nsec_offset); 2163 } 2164 2165 static enum mlxsw_cmd_mbox_config_profile_lag_mode 2166 mlxsw_pci_lag_mode(void *bus_priv) 2167 { 2168 struct mlxsw_pci *mlxsw_pci = bus_priv; 2169 2170 return mlxsw_pci->lag_mode; 2171 } 2172 2173 static enum mlxsw_cmd_mbox_config_profile_flood_mode 2174 mlxsw_pci_flood_mode(void *bus_priv) 2175 { 2176 struct mlxsw_pci *mlxsw_pci = bus_priv; 2177 2178 return mlxsw_pci->flood_mode; 2179 } 2180 2181 static const struct mlxsw_bus mlxsw_pci_bus = { 2182 .kind = "pci", 2183 .init = mlxsw_pci_init, 2184 .fini = mlxsw_pci_fini, 2185 .skb_transmit_busy = mlxsw_pci_skb_transmit_busy, 2186 .skb_transmit = mlxsw_pci_skb_transmit, 2187 .cmd_exec = mlxsw_pci_cmd_exec, 2188 .read_frc_h = mlxsw_pci_read_frc_h, 2189 .read_frc_l = mlxsw_pci_read_frc_l, 2190 .read_utc_sec = mlxsw_pci_read_utc_sec, 2191 .read_utc_nsec = mlxsw_pci_read_utc_nsec, 2192 .lag_mode = mlxsw_pci_lag_mode, 2193 .flood_mode = mlxsw_pci_flood_mode, 2194 .features = MLXSW_BUS_F_TXRX | MLXSW_BUS_F_RESET, 2195 }; 2196 2197 static int mlxsw_pci_cmd_init(struct mlxsw_pci *mlxsw_pci) 2198 { 2199 int err; 2200 2201 mutex_init(&mlxsw_pci->cmd.lock); 2202 2203 err = mlxsw_pci_mbox_alloc(mlxsw_pci, &mlxsw_pci->cmd.in_mbox); 2204 if (err) 2205 goto err_in_mbox_alloc; 2206 2207 err = mlxsw_pci_mbox_alloc(mlxsw_pci, &mlxsw_pci->cmd.out_mbox); 2208 if (err) 2209 goto err_out_mbox_alloc; 2210 2211 return 0; 2212 2213 err_out_mbox_alloc: 2214 mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.in_mbox); 2215 err_in_mbox_alloc: 2216 mutex_destroy(&mlxsw_pci->cmd.lock); 2217 return err; 2218 } 2219 2220 static void mlxsw_pci_cmd_fini(struct mlxsw_pci *mlxsw_pci) 2221 { 2222 mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.out_mbox); 2223 mlxsw_pci_mbox_free(mlxsw_pci, &mlxsw_pci->cmd.in_mbox); 2224 mutex_destroy(&mlxsw_pci->cmd.lock); 2225 } 2226 2227 static int mlxsw_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2228 { 2229 const char *driver_name = dev_driver_string(&pdev->dev); 2230 struct mlxsw_pci *mlxsw_pci; 2231 int err; 2232 2233 mlxsw_pci = kzalloc(sizeof(*mlxsw_pci), GFP_KERNEL); 2234 if (!mlxsw_pci) 2235 return -ENOMEM; 2236 2237 err = pci_enable_device(pdev); 2238 if (err) { 2239 dev_err(&pdev->dev, "pci_enable_device failed\n"); 2240 goto err_pci_enable_device; 2241 } 2242 2243 err = pci_request_regions(pdev, driver_name); 2244 if (err) { 2245 dev_err(&pdev->dev, "pci_request_regions failed\n"); 2246 goto err_pci_request_regions; 2247 } 2248 2249 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2250 if (err) { 2251 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 2252 if (err) { 2253 dev_err(&pdev->dev, "dma_set_mask failed\n"); 2254 goto err_pci_set_dma_mask; 2255 } 2256 } 2257 2258 if (pci_resource_len(pdev, 0) < MLXSW_PCI_BAR0_SIZE) { 2259 dev_err(&pdev->dev, "invalid PCI region size\n"); 2260 err = -EINVAL; 2261 goto err_pci_resource_len_check; 2262 } 2263 2264 mlxsw_pci->hw_addr = ioremap(pci_resource_start(pdev, 0), 2265 pci_resource_len(pdev, 0)); 2266 if (!mlxsw_pci->hw_addr) { 2267 dev_err(&pdev->dev, "ioremap failed\n"); 2268 err = -EIO; 2269 goto err_ioremap; 2270 } 2271 pci_set_master(pdev); 2272 2273 mlxsw_pci->pdev = pdev; 2274 pci_set_drvdata(pdev, mlxsw_pci); 2275 2276 err = mlxsw_pci_cmd_init(mlxsw_pci); 2277 if (err) 2278 goto err_pci_cmd_init; 2279 2280 mlxsw_pci->bus_info.device_kind = driver_name; 2281 mlxsw_pci->bus_info.device_name = pci_name(mlxsw_pci->pdev); 2282 mlxsw_pci->bus_info.dev = &pdev->dev; 2283 mlxsw_pci->bus_info.read_clock_capable = true; 2284 mlxsw_pci->id = id; 2285 2286 err = mlxsw_core_bus_device_register(&mlxsw_pci->bus_info, 2287 &mlxsw_pci_bus, mlxsw_pci, false, 2288 NULL, NULL); 2289 if (err) { 2290 dev_err(&pdev->dev, "cannot register bus device\n"); 2291 goto err_bus_device_register; 2292 } 2293 2294 return 0; 2295 2296 err_bus_device_register: 2297 mlxsw_pci_cmd_fini(mlxsw_pci); 2298 err_pci_cmd_init: 2299 iounmap(mlxsw_pci->hw_addr); 2300 err_ioremap: 2301 err_pci_resource_len_check: 2302 err_pci_set_dma_mask: 2303 pci_release_regions(pdev); 2304 err_pci_request_regions: 2305 pci_disable_device(pdev); 2306 err_pci_enable_device: 2307 kfree(mlxsw_pci); 2308 return err; 2309 } 2310 2311 static void mlxsw_pci_remove(struct pci_dev *pdev) 2312 { 2313 struct mlxsw_pci *mlxsw_pci = pci_get_drvdata(pdev); 2314 2315 mlxsw_core_bus_device_unregister(mlxsw_pci->core, false); 2316 mlxsw_pci_cmd_fini(mlxsw_pci); 2317 iounmap(mlxsw_pci->hw_addr); 2318 pci_release_regions(mlxsw_pci->pdev); 2319 pci_disable_device(mlxsw_pci->pdev); 2320 kfree(mlxsw_pci); 2321 } 2322 2323 static void mlxsw_pci_reset_prepare(struct pci_dev *pdev) 2324 { 2325 struct mlxsw_pci *mlxsw_pci = pci_get_drvdata(pdev); 2326 2327 mlxsw_core_bus_device_unregister(mlxsw_pci->core, false); 2328 } 2329 2330 static void mlxsw_pci_reset_done(struct pci_dev *pdev) 2331 { 2332 struct mlxsw_pci *mlxsw_pci = pci_get_drvdata(pdev); 2333 2334 mlxsw_pci->skip_reset = true; 2335 mlxsw_core_bus_device_register(&mlxsw_pci->bus_info, &mlxsw_pci_bus, 2336 mlxsw_pci, false, NULL, NULL); 2337 mlxsw_pci->skip_reset = false; 2338 } 2339 2340 static const struct pci_error_handlers mlxsw_pci_err_handler = { 2341 .reset_prepare = mlxsw_pci_reset_prepare, 2342 .reset_done = mlxsw_pci_reset_done, 2343 }; 2344 2345 int mlxsw_pci_driver_register(struct pci_driver *pci_driver) 2346 { 2347 pci_driver->probe = mlxsw_pci_probe; 2348 pci_driver->remove = mlxsw_pci_remove; 2349 pci_driver->shutdown = mlxsw_pci_remove; 2350 pci_driver->err_handler = &mlxsw_pci_err_handler; 2351 return pci_register_driver(pci_driver); 2352 } 2353 EXPORT_SYMBOL(mlxsw_pci_driver_register); 2354 2355 void mlxsw_pci_driver_unregister(struct pci_driver *pci_driver) 2356 { 2357 pci_unregister_driver(pci_driver); 2358 } 2359 EXPORT_SYMBOL(mlxsw_pci_driver_unregister); 2360 2361 static int __init mlxsw_pci_module_init(void) 2362 { 2363 return 0; 2364 } 2365 2366 static void __exit mlxsw_pci_module_exit(void) 2367 { 2368 } 2369 2370 module_init(mlxsw_pci_module_init); 2371 module_exit(mlxsw_pci_module_exit); 2372 2373 MODULE_LICENSE("Dual BSD/GPL"); 2374 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>"); 2375 MODULE_DESCRIPTION("Mellanox switch PCI interface driver"); 2376