1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #ifndef _MLXSW_CORE_H 5 #define _MLXSW_CORE_H 6 7 #include <linux/module.h> 8 #include <linux/device.h> 9 #include <linux/slab.h> 10 #include <linux/gfp.h> 11 #include <linux/types.h> 12 #include <linux/skbuff.h> 13 #include <linux/workqueue.h> 14 #include <net/devlink.h> 15 16 #include "trap.h" 17 #include "reg.h" 18 #include "cmd.h" 19 #include "resources.h" 20 21 struct mlxsw_core; 22 struct mlxsw_core_port; 23 struct mlxsw_driver; 24 struct mlxsw_bus; 25 struct mlxsw_bus_info; 26 27 unsigned int mlxsw_core_max_ports(const struct mlxsw_core *mlxsw_core); 28 29 void *mlxsw_core_driver_priv(struct mlxsw_core *mlxsw_core); 30 31 bool mlxsw_core_res_query_enabled(const struct mlxsw_core *mlxsw_core); 32 33 int mlxsw_core_driver_register(struct mlxsw_driver *mlxsw_driver); 34 void mlxsw_core_driver_unregister(struct mlxsw_driver *mlxsw_driver); 35 36 int mlxsw_core_bus_device_register(const struct mlxsw_bus_info *mlxsw_bus_info, 37 const struct mlxsw_bus *mlxsw_bus, 38 void *bus_priv, bool reload, 39 struct devlink *devlink); 40 void mlxsw_core_bus_device_unregister(struct mlxsw_core *mlxsw_core, bool reload); 41 42 struct mlxsw_tx_info { 43 u8 local_port; 44 bool is_emad; 45 }; 46 47 bool mlxsw_core_skb_transmit_busy(struct mlxsw_core *mlxsw_core, 48 const struct mlxsw_tx_info *tx_info); 49 int mlxsw_core_skb_transmit(struct mlxsw_core *mlxsw_core, struct sk_buff *skb, 50 const struct mlxsw_tx_info *tx_info); 51 52 struct mlxsw_rx_listener { 53 void (*func)(struct sk_buff *skb, u8 local_port, void *priv); 54 u8 local_port; 55 u16 trap_id; 56 enum mlxsw_reg_hpkt_action action; 57 }; 58 59 struct mlxsw_event_listener { 60 void (*func)(const struct mlxsw_reg_info *reg, 61 char *payload, void *priv); 62 enum mlxsw_event_trap_id trap_id; 63 }; 64 65 struct mlxsw_listener { 66 u16 trap_id; 67 union { 68 struct mlxsw_rx_listener rx_listener; 69 struct mlxsw_event_listener event_listener; 70 } u; 71 enum mlxsw_reg_hpkt_action action; 72 enum mlxsw_reg_hpkt_action unreg_action; 73 u8 trap_group; 74 bool is_ctrl; /* should go via control buffer or not */ 75 bool is_event; 76 }; 77 78 #define MLXSW_RXL(_func, _trap_id, _action, _is_ctrl, _trap_group, \ 79 _unreg_action) \ 80 { \ 81 .trap_id = MLXSW_TRAP_ID_##_trap_id, \ 82 .u.rx_listener = \ 83 { \ 84 .func = _func, \ 85 .local_port = MLXSW_PORT_DONT_CARE, \ 86 .trap_id = MLXSW_TRAP_ID_##_trap_id, \ 87 }, \ 88 .action = MLXSW_REG_HPKT_ACTION_##_action, \ 89 .unreg_action = MLXSW_REG_HPKT_ACTION_##_unreg_action, \ 90 .trap_group = MLXSW_REG_HTGT_TRAP_GROUP_##_trap_group, \ 91 .is_ctrl = _is_ctrl, \ 92 .is_event = false, \ 93 } 94 95 #define MLXSW_EVENTL(_func, _trap_id, _trap_group) \ 96 { \ 97 .trap_id = MLXSW_TRAP_ID_##_trap_id, \ 98 .u.event_listener = \ 99 { \ 100 .func = _func, \ 101 .trap_id = MLXSW_TRAP_ID_##_trap_id, \ 102 }, \ 103 .action = MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU, \ 104 .trap_group = MLXSW_REG_HTGT_TRAP_GROUP_##_trap_group, \ 105 .is_ctrl = false, \ 106 .is_event = true, \ 107 } 108 109 int mlxsw_core_rx_listener_register(struct mlxsw_core *mlxsw_core, 110 const struct mlxsw_rx_listener *rxl, 111 void *priv); 112 void mlxsw_core_rx_listener_unregister(struct mlxsw_core *mlxsw_core, 113 const struct mlxsw_rx_listener *rxl, 114 void *priv); 115 116 int mlxsw_core_event_listener_register(struct mlxsw_core *mlxsw_core, 117 const struct mlxsw_event_listener *el, 118 void *priv); 119 void mlxsw_core_event_listener_unregister(struct mlxsw_core *mlxsw_core, 120 const struct mlxsw_event_listener *el, 121 void *priv); 122 123 int mlxsw_core_trap_register(struct mlxsw_core *mlxsw_core, 124 const struct mlxsw_listener *listener, 125 void *priv); 126 void mlxsw_core_trap_unregister(struct mlxsw_core *mlxsw_core, 127 const struct mlxsw_listener *listener, 128 void *priv); 129 130 typedef void mlxsw_reg_trans_cb_t(struct mlxsw_core *mlxsw_core, char *payload, 131 size_t payload_len, unsigned long cb_priv); 132 133 int mlxsw_reg_trans_query(struct mlxsw_core *mlxsw_core, 134 const struct mlxsw_reg_info *reg, char *payload, 135 struct list_head *bulk_list, 136 mlxsw_reg_trans_cb_t *cb, unsigned long cb_priv); 137 int mlxsw_reg_trans_write(struct mlxsw_core *mlxsw_core, 138 const struct mlxsw_reg_info *reg, char *payload, 139 struct list_head *bulk_list, 140 mlxsw_reg_trans_cb_t *cb, unsigned long cb_priv); 141 int mlxsw_reg_trans_bulk_wait(struct list_head *bulk_list); 142 143 int mlxsw_reg_query(struct mlxsw_core *mlxsw_core, 144 const struct mlxsw_reg_info *reg, char *payload); 145 int mlxsw_reg_write(struct mlxsw_core *mlxsw_core, 146 const struct mlxsw_reg_info *reg, char *payload); 147 148 struct mlxsw_rx_info { 149 bool is_lag; 150 union { 151 u16 sys_port; 152 u16 lag_id; 153 } u; 154 u8 lag_port_index; 155 int trap_id; 156 }; 157 158 void mlxsw_core_skb_receive(struct mlxsw_core *mlxsw_core, struct sk_buff *skb, 159 struct mlxsw_rx_info *rx_info); 160 161 void mlxsw_core_lag_mapping_set(struct mlxsw_core *mlxsw_core, 162 u16 lag_id, u8 port_index, u8 local_port); 163 u8 mlxsw_core_lag_mapping_get(struct mlxsw_core *mlxsw_core, 164 u16 lag_id, u8 port_index); 165 void mlxsw_core_lag_mapping_clear(struct mlxsw_core *mlxsw_core, 166 u16 lag_id, u8 local_port); 167 168 void *mlxsw_core_port_driver_priv(struct mlxsw_core_port *mlxsw_core_port); 169 int mlxsw_core_port_init(struct mlxsw_core *mlxsw_core, u8 local_port, 170 u32 port_number, bool split, 171 u32 split_port_subnumber, 172 const unsigned char *switch_id, 173 unsigned char switch_id_len); 174 void mlxsw_core_port_fini(struct mlxsw_core *mlxsw_core, u8 local_port); 175 void mlxsw_core_port_eth_set(struct mlxsw_core *mlxsw_core, u8 local_port, 176 void *port_driver_priv, struct net_device *dev); 177 void mlxsw_core_port_ib_set(struct mlxsw_core *mlxsw_core, u8 local_port, 178 void *port_driver_priv); 179 void mlxsw_core_port_clear(struct mlxsw_core *mlxsw_core, u8 local_port, 180 void *port_driver_priv); 181 enum devlink_port_type mlxsw_core_port_type_get(struct mlxsw_core *mlxsw_core, 182 u8 local_port); 183 struct devlink_port * 184 mlxsw_core_port_devlink_port_get(struct mlxsw_core *mlxsw_core, 185 u8 local_port); 186 187 int mlxsw_core_schedule_dw(struct delayed_work *dwork, unsigned long delay); 188 bool mlxsw_core_schedule_work(struct work_struct *work); 189 void mlxsw_core_flush_owq(void); 190 int mlxsw_core_resources_query(struct mlxsw_core *mlxsw_core, char *mbox, 191 struct mlxsw_res *res); 192 193 #define MLXSW_CONFIG_PROFILE_SWID_COUNT 8 194 195 struct mlxsw_swid_config { 196 u8 used_type:1, 197 used_properties:1; 198 u8 type; 199 u8 properties; 200 }; 201 202 struct mlxsw_config_profile { 203 u16 used_max_vepa_channels:1, 204 used_max_mid:1, 205 used_max_pgt:1, 206 used_max_system_port:1, 207 used_max_vlan_groups:1, 208 used_max_regions:1, 209 used_flood_tables:1, 210 used_flood_mode:1, 211 used_max_ib_mc:1, 212 used_max_pkey:1, 213 used_ar_sec:1, 214 used_adaptive_routing_group_cap:1, 215 used_kvd_sizes:1; 216 u8 max_vepa_channels; 217 u16 max_mid; 218 u16 max_pgt; 219 u16 max_system_port; 220 u16 max_vlan_groups; 221 u16 max_regions; 222 u8 max_flood_tables; 223 u8 max_vid_flood_tables; 224 u8 flood_mode; 225 u8 max_fid_offset_flood_tables; 226 u16 fid_offset_flood_table_size; 227 u8 max_fid_flood_tables; 228 u16 fid_flood_table_size; 229 u16 max_ib_mc; 230 u16 max_pkey; 231 u8 ar_sec; 232 u16 adaptive_routing_group_cap; 233 u8 arn; 234 u32 kvd_linear_size; 235 u8 kvd_hash_single_parts; 236 u8 kvd_hash_double_parts; 237 struct mlxsw_swid_config swid_config[MLXSW_CONFIG_PROFILE_SWID_COUNT]; 238 }; 239 240 struct mlxsw_driver { 241 struct list_head list; 242 const char *kind; 243 size_t priv_size; 244 int (*init)(struct mlxsw_core *mlxsw_core, 245 const struct mlxsw_bus_info *mlxsw_bus_info); 246 void (*fini)(struct mlxsw_core *mlxsw_core); 247 int (*basic_trap_groups_set)(struct mlxsw_core *mlxsw_core); 248 int (*port_type_set)(struct mlxsw_core *mlxsw_core, u8 local_port, 249 enum devlink_port_type new_type); 250 int (*port_split)(struct mlxsw_core *mlxsw_core, u8 local_port, 251 unsigned int count, struct netlink_ext_ack *extack); 252 int (*port_unsplit)(struct mlxsw_core *mlxsw_core, u8 local_port, 253 struct netlink_ext_ack *extack); 254 int (*sb_pool_get)(struct mlxsw_core *mlxsw_core, 255 unsigned int sb_index, u16 pool_index, 256 struct devlink_sb_pool_info *pool_info); 257 int (*sb_pool_set)(struct mlxsw_core *mlxsw_core, 258 unsigned int sb_index, u16 pool_index, u32 size, 259 enum devlink_sb_threshold_type threshold_type, 260 struct netlink_ext_ack *extack); 261 int (*sb_port_pool_get)(struct mlxsw_core_port *mlxsw_core_port, 262 unsigned int sb_index, u16 pool_index, 263 u32 *p_threshold); 264 int (*sb_port_pool_set)(struct mlxsw_core_port *mlxsw_core_port, 265 unsigned int sb_index, u16 pool_index, 266 u32 threshold, struct netlink_ext_ack *extack); 267 int (*sb_tc_pool_bind_get)(struct mlxsw_core_port *mlxsw_core_port, 268 unsigned int sb_index, u16 tc_index, 269 enum devlink_sb_pool_type pool_type, 270 u16 *p_pool_index, u32 *p_threshold); 271 int (*sb_tc_pool_bind_set)(struct mlxsw_core_port *mlxsw_core_port, 272 unsigned int sb_index, u16 tc_index, 273 enum devlink_sb_pool_type pool_type, 274 u16 pool_index, u32 threshold, 275 struct netlink_ext_ack *extack); 276 int (*sb_occ_snapshot)(struct mlxsw_core *mlxsw_core, 277 unsigned int sb_index); 278 int (*sb_occ_max_clear)(struct mlxsw_core *mlxsw_core, 279 unsigned int sb_index); 280 int (*sb_occ_port_pool_get)(struct mlxsw_core_port *mlxsw_core_port, 281 unsigned int sb_index, u16 pool_index, 282 u32 *p_cur, u32 *p_max); 283 int (*sb_occ_tc_port_bind_get)(struct mlxsw_core_port *mlxsw_core_port, 284 unsigned int sb_index, u16 tc_index, 285 enum devlink_sb_pool_type pool_type, 286 u32 *p_cur, u32 *p_max); 287 int (*flash_update)(struct mlxsw_core *mlxsw_core, 288 const char *file_name, const char *component, 289 struct netlink_ext_ack *extack); 290 void (*txhdr_construct)(struct sk_buff *skb, 291 const struct mlxsw_tx_info *tx_info); 292 int (*resources_register)(struct mlxsw_core *mlxsw_core); 293 int (*kvd_sizes_get)(struct mlxsw_core *mlxsw_core, 294 const struct mlxsw_config_profile *profile, 295 u64 *p_single_size, u64 *p_double_size, 296 u64 *p_linear_size); 297 int (*params_register)(struct mlxsw_core *mlxsw_core); 298 void (*params_unregister)(struct mlxsw_core *mlxsw_core); 299 u8 txhdr_len; 300 const struct mlxsw_config_profile *profile; 301 bool res_query_enabled; 302 }; 303 304 int mlxsw_core_kvd_sizes_get(struct mlxsw_core *mlxsw_core, 305 const struct mlxsw_config_profile *profile, 306 u64 *p_single_size, u64 *p_double_size, 307 u64 *p_linear_size); 308 309 void mlxsw_core_fw_flash_start(struct mlxsw_core *mlxsw_core); 310 void mlxsw_core_fw_flash_end(struct mlxsw_core *mlxsw_core); 311 312 u32 mlxsw_core_read_frc_h(struct mlxsw_core *mlxsw_core); 313 u32 mlxsw_core_read_frc_l(struct mlxsw_core *mlxsw_core); 314 315 bool mlxsw_core_res_valid(struct mlxsw_core *mlxsw_core, 316 enum mlxsw_res_id res_id); 317 318 #define MLXSW_CORE_RES_VALID(mlxsw_core, short_res_id) \ 319 mlxsw_core_res_valid(mlxsw_core, MLXSW_RES_ID_##short_res_id) 320 321 u64 mlxsw_core_res_get(struct mlxsw_core *mlxsw_core, 322 enum mlxsw_res_id res_id); 323 324 #define MLXSW_CORE_RES_GET(mlxsw_core, short_res_id) \ 325 mlxsw_core_res_get(mlxsw_core, MLXSW_RES_ID_##short_res_id) 326 327 #define MLXSW_BUS_F_TXRX BIT(0) 328 #define MLXSW_BUS_F_RESET BIT(1) 329 330 struct mlxsw_bus { 331 const char *kind; 332 int (*init)(void *bus_priv, struct mlxsw_core *mlxsw_core, 333 const struct mlxsw_config_profile *profile, 334 struct mlxsw_res *res); 335 void (*fini)(void *bus_priv); 336 bool (*skb_transmit_busy)(void *bus_priv, 337 const struct mlxsw_tx_info *tx_info); 338 int (*skb_transmit)(void *bus_priv, struct sk_buff *skb, 339 const struct mlxsw_tx_info *tx_info); 340 int (*cmd_exec)(void *bus_priv, u16 opcode, u8 opcode_mod, 341 u32 in_mod, bool out_mbox_direct, 342 char *in_mbox, size_t in_mbox_size, 343 char *out_mbox, size_t out_mbox_size, 344 u8 *p_status); 345 u32 (*read_frc_h)(void *bus_priv); 346 u32 (*read_frc_l)(void *bus_priv); 347 u8 features; 348 }; 349 350 struct mlxsw_fw_rev { 351 u16 major; 352 u16 minor; 353 u16 subminor; 354 u16 can_reset_minor; 355 }; 356 357 struct mlxsw_bus_info { 358 const char *device_kind; 359 const char *device_name; 360 struct device *dev; 361 struct mlxsw_fw_rev fw_rev; 362 u8 vsd[MLXSW_CMD_BOARDINFO_VSD_LEN]; 363 u8 psid[MLXSW_CMD_BOARDINFO_PSID_LEN]; 364 u8 low_frequency:1, 365 read_frc_capable:1; 366 }; 367 368 struct mlxsw_hwmon; 369 370 #ifdef CONFIG_MLXSW_CORE_HWMON 371 372 int mlxsw_hwmon_init(struct mlxsw_core *mlxsw_core, 373 const struct mlxsw_bus_info *mlxsw_bus_info, 374 struct mlxsw_hwmon **p_hwmon); 375 void mlxsw_hwmon_fini(struct mlxsw_hwmon *mlxsw_hwmon); 376 377 #else 378 379 static inline int mlxsw_hwmon_init(struct mlxsw_core *mlxsw_core, 380 const struct mlxsw_bus_info *mlxsw_bus_info, 381 struct mlxsw_hwmon **p_hwmon) 382 { 383 return 0; 384 } 385 386 static inline void mlxsw_hwmon_fini(struct mlxsw_hwmon *mlxsw_hwmon) 387 { 388 } 389 390 #endif 391 392 struct mlxsw_thermal; 393 394 #ifdef CONFIG_MLXSW_CORE_THERMAL 395 396 int mlxsw_thermal_init(struct mlxsw_core *mlxsw_core, 397 const struct mlxsw_bus_info *mlxsw_bus_info, 398 struct mlxsw_thermal **p_thermal); 399 void mlxsw_thermal_fini(struct mlxsw_thermal *thermal); 400 401 #else 402 403 static inline int mlxsw_thermal_init(struct mlxsw_core *mlxsw_core, 404 const struct mlxsw_bus_info *mlxsw_bus_info, 405 struct mlxsw_thermal **p_thermal) 406 { 407 return 0; 408 } 409 410 static inline void mlxsw_thermal_fini(struct mlxsw_thermal *thermal) 411 { 412 } 413 414 #endif 415 416 enum mlxsw_devlink_param_id { 417 MLXSW_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX, 418 MLXSW_DEVLINK_PARAM_ID_ACL_REGION_REHASH_INTERVAL, 419 }; 420 421 #endif 422