1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/device.h> 7 #include <linux/export.h> 8 #include <linux/err.h> 9 #include <linux/if_link.h> 10 #include <linux/netdevice.h> 11 #include <linux/completion.h> 12 #include <linux/skbuff.h> 13 #include <linux/etherdevice.h> 14 #include <linux/types.h> 15 #include <linux/string.h> 16 #include <linux/gfp.h> 17 #include <linux/random.h> 18 #include <linux/jiffies.h> 19 #include <linux/mutex.h> 20 #include <linux/rcupdate.h> 21 #include <linux/slab.h> 22 #include <linux/workqueue.h> 23 #include <linux/firmware.h> 24 #include <asm/byteorder.h> 25 #include <net/devlink.h> 26 #include <trace/events/devlink.h> 27 28 #include "core.h" 29 #include "core_env.h" 30 #include "item.h" 31 #include "cmd.h" 32 #include "port.h" 33 #include "trap.h" 34 #include "emad.h" 35 #include "reg.h" 36 #include "resources.h" 37 #include "../mlxfw/mlxfw.h" 38 39 static LIST_HEAD(mlxsw_core_driver_list); 40 static DEFINE_SPINLOCK(mlxsw_core_driver_list_lock); 41 42 static const char mlxsw_core_driver_name[] = "mlxsw_core"; 43 44 static struct workqueue_struct *mlxsw_wq; 45 static struct workqueue_struct *mlxsw_owq; 46 47 struct mlxsw_core_port { 48 struct devlink_port devlink_port; 49 void *port_driver_priv; 50 u8 local_port; 51 }; 52 53 void *mlxsw_core_port_driver_priv(struct mlxsw_core_port *mlxsw_core_port) 54 { 55 return mlxsw_core_port->port_driver_priv; 56 } 57 EXPORT_SYMBOL(mlxsw_core_port_driver_priv); 58 59 static bool mlxsw_core_port_check(struct mlxsw_core_port *mlxsw_core_port) 60 { 61 return mlxsw_core_port->port_driver_priv != NULL; 62 } 63 64 struct mlxsw_core { 65 struct mlxsw_driver *driver; 66 const struct mlxsw_bus *bus; 67 void *bus_priv; 68 const struct mlxsw_bus_info *bus_info; 69 struct workqueue_struct *emad_wq; 70 struct list_head rx_listener_list; 71 struct list_head event_listener_list; 72 struct { 73 atomic64_t tid; 74 struct list_head trans_list; 75 spinlock_t trans_list_lock; /* protects trans_list writes */ 76 bool use_emad; 77 bool enable_string_tlv; 78 } emad; 79 struct { 80 u8 *mapping; /* lag_id+port_index to local_port mapping */ 81 } lag; 82 struct mlxsw_res res; 83 struct mlxsw_hwmon *hwmon; 84 struct mlxsw_thermal *thermal; 85 struct mlxsw_core_port *ports; 86 unsigned int max_ports; 87 bool fw_flash_in_progress; 88 struct { 89 struct devlink_health_reporter *fw_fatal; 90 } health; 91 struct mlxsw_env *env; 92 bool is_initialized; /* Denotes if core was already initialized. */ 93 unsigned long driver_priv[]; 94 /* driver_priv has to be always the last item */ 95 }; 96 97 #define MLXSW_PORT_MAX_PORTS_DEFAULT 0x40 98 99 static int mlxsw_ports_init(struct mlxsw_core *mlxsw_core) 100 { 101 /* Switch ports are numbered from 1 to queried value */ 102 if (MLXSW_CORE_RES_VALID(mlxsw_core, MAX_SYSTEM_PORT)) 103 mlxsw_core->max_ports = MLXSW_CORE_RES_GET(mlxsw_core, 104 MAX_SYSTEM_PORT) + 1; 105 else 106 mlxsw_core->max_ports = MLXSW_PORT_MAX_PORTS_DEFAULT + 1; 107 108 mlxsw_core->ports = kcalloc(mlxsw_core->max_ports, 109 sizeof(struct mlxsw_core_port), GFP_KERNEL); 110 if (!mlxsw_core->ports) 111 return -ENOMEM; 112 113 return 0; 114 } 115 116 static void mlxsw_ports_fini(struct mlxsw_core *mlxsw_core) 117 { 118 kfree(mlxsw_core->ports); 119 } 120 121 unsigned int mlxsw_core_max_ports(const struct mlxsw_core *mlxsw_core) 122 { 123 return mlxsw_core->max_ports; 124 } 125 EXPORT_SYMBOL(mlxsw_core_max_ports); 126 127 void *mlxsw_core_driver_priv(struct mlxsw_core *mlxsw_core) 128 { 129 return mlxsw_core->driver_priv; 130 } 131 EXPORT_SYMBOL(mlxsw_core_driver_priv); 132 133 bool mlxsw_core_res_query_enabled(const struct mlxsw_core *mlxsw_core) 134 { 135 return mlxsw_core->driver->res_query_enabled; 136 } 137 EXPORT_SYMBOL(mlxsw_core_res_query_enabled); 138 139 bool mlxsw_core_temp_warn_enabled(const struct mlxsw_core *mlxsw_core) 140 { 141 return mlxsw_core->driver->temp_warn_enabled; 142 } 143 144 bool 145 mlxsw_core_fw_rev_minor_subminor_validate(const struct mlxsw_fw_rev *rev, 146 const struct mlxsw_fw_rev *req_rev) 147 { 148 return rev->minor > req_rev->minor || 149 (rev->minor == req_rev->minor && 150 rev->subminor >= req_rev->subminor); 151 } 152 EXPORT_SYMBOL(mlxsw_core_fw_rev_minor_subminor_validate); 153 154 struct mlxsw_rx_listener_item { 155 struct list_head list; 156 struct mlxsw_rx_listener rxl; 157 void *priv; 158 bool enabled; 159 }; 160 161 struct mlxsw_event_listener_item { 162 struct list_head list; 163 struct mlxsw_event_listener el; 164 void *priv; 165 }; 166 167 /****************** 168 * EMAD processing 169 ******************/ 170 171 /* emad_eth_hdr_dmac 172 * Destination MAC in EMAD's Ethernet header. 173 * Must be set to 01:02:c9:00:00:01 174 */ 175 MLXSW_ITEM_BUF(emad, eth_hdr, dmac, 0x00, 6); 176 177 /* emad_eth_hdr_smac 178 * Source MAC in EMAD's Ethernet header. 179 * Must be set to 00:02:c9:01:02:03 180 */ 181 MLXSW_ITEM_BUF(emad, eth_hdr, smac, 0x06, 6); 182 183 /* emad_eth_hdr_ethertype 184 * Ethertype in EMAD's Ethernet header. 185 * Must be set to 0x8932 186 */ 187 MLXSW_ITEM32(emad, eth_hdr, ethertype, 0x0C, 16, 16); 188 189 /* emad_eth_hdr_mlx_proto 190 * Mellanox protocol. 191 * Must be set to 0x0. 192 */ 193 MLXSW_ITEM32(emad, eth_hdr, mlx_proto, 0x0C, 8, 8); 194 195 /* emad_eth_hdr_ver 196 * Mellanox protocol version. 197 * Must be set to 0x0. 198 */ 199 MLXSW_ITEM32(emad, eth_hdr, ver, 0x0C, 4, 4); 200 201 /* emad_op_tlv_type 202 * Type of the TLV. 203 * Must be set to 0x1 (operation TLV). 204 */ 205 MLXSW_ITEM32(emad, op_tlv, type, 0x00, 27, 5); 206 207 /* emad_op_tlv_len 208 * Length of the operation TLV in u32. 209 * Must be set to 0x4. 210 */ 211 MLXSW_ITEM32(emad, op_tlv, len, 0x00, 16, 11); 212 213 /* emad_op_tlv_dr 214 * Direct route bit. Setting to 1 indicates the EMAD is a direct route 215 * EMAD. DR TLV must follow. 216 * 217 * Note: Currently not supported and must not be set. 218 */ 219 MLXSW_ITEM32(emad, op_tlv, dr, 0x00, 15, 1); 220 221 /* emad_op_tlv_status 222 * Returned status in case of EMAD response. Must be set to 0 in case 223 * of EMAD request. 224 * 0x0 - success 225 * 0x1 - device is busy. Requester should retry 226 * 0x2 - Mellanox protocol version not supported 227 * 0x3 - unknown TLV 228 * 0x4 - register not supported 229 * 0x5 - operation class not supported 230 * 0x6 - EMAD method not supported 231 * 0x7 - bad parameter (e.g. port out of range) 232 * 0x8 - resource not available 233 * 0x9 - message receipt acknowledgment. Requester should retry 234 * 0x70 - internal error 235 */ 236 MLXSW_ITEM32(emad, op_tlv, status, 0x00, 8, 7); 237 238 /* emad_op_tlv_register_id 239 * Register ID of register within register TLV. 240 */ 241 MLXSW_ITEM32(emad, op_tlv, register_id, 0x04, 16, 16); 242 243 /* emad_op_tlv_r 244 * Response bit. Setting to 1 indicates Response, otherwise request. 245 */ 246 MLXSW_ITEM32(emad, op_tlv, r, 0x04, 15, 1); 247 248 /* emad_op_tlv_method 249 * EMAD method type. 250 * 0x1 - query 251 * 0x2 - write 252 * 0x3 - send (currently not supported) 253 * 0x4 - event 254 */ 255 MLXSW_ITEM32(emad, op_tlv, method, 0x04, 8, 7); 256 257 /* emad_op_tlv_class 258 * EMAD operation class. Must be set to 0x1 (REG_ACCESS). 259 */ 260 MLXSW_ITEM32(emad, op_tlv, class, 0x04, 0, 8); 261 262 /* emad_op_tlv_tid 263 * EMAD transaction ID. Used for pairing request and response EMADs. 264 */ 265 MLXSW_ITEM64(emad, op_tlv, tid, 0x08, 0, 64); 266 267 /* emad_string_tlv_type 268 * Type of the TLV. 269 * Must be set to 0x2 (string TLV). 270 */ 271 MLXSW_ITEM32(emad, string_tlv, type, 0x00, 27, 5); 272 273 /* emad_string_tlv_len 274 * Length of the string TLV in u32. 275 */ 276 MLXSW_ITEM32(emad, string_tlv, len, 0x00, 16, 11); 277 278 #define MLXSW_EMAD_STRING_TLV_STRING_LEN 128 279 280 /* emad_string_tlv_string 281 * String provided by the device's firmware in case of erroneous register access 282 */ 283 MLXSW_ITEM_BUF(emad, string_tlv, string, 0x04, 284 MLXSW_EMAD_STRING_TLV_STRING_LEN); 285 286 /* emad_reg_tlv_type 287 * Type of the TLV. 288 * Must be set to 0x3 (register TLV). 289 */ 290 MLXSW_ITEM32(emad, reg_tlv, type, 0x00, 27, 5); 291 292 /* emad_reg_tlv_len 293 * Length of the operation TLV in u32. 294 */ 295 MLXSW_ITEM32(emad, reg_tlv, len, 0x00, 16, 11); 296 297 /* emad_end_tlv_type 298 * Type of the TLV. 299 * Must be set to 0x0 (end TLV). 300 */ 301 MLXSW_ITEM32(emad, end_tlv, type, 0x00, 27, 5); 302 303 /* emad_end_tlv_len 304 * Length of the end TLV in u32. 305 * Must be set to 1. 306 */ 307 MLXSW_ITEM32(emad, end_tlv, len, 0x00, 16, 11); 308 309 enum mlxsw_core_reg_access_type { 310 MLXSW_CORE_REG_ACCESS_TYPE_QUERY, 311 MLXSW_CORE_REG_ACCESS_TYPE_WRITE, 312 }; 313 314 static inline const char * 315 mlxsw_core_reg_access_type_str(enum mlxsw_core_reg_access_type type) 316 { 317 switch (type) { 318 case MLXSW_CORE_REG_ACCESS_TYPE_QUERY: 319 return "query"; 320 case MLXSW_CORE_REG_ACCESS_TYPE_WRITE: 321 return "write"; 322 } 323 BUG(); 324 } 325 326 static void mlxsw_emad_pack_end_tlv(char *end_tlv) 327 { 328 mlxsw_emad_end_tlv_type_set(end_tlv, MLXSW_EMAD_TLV_TYPE_END); 329 mlxsw_emad_end_tlv_len_set(end_tlv, MLXSW_EMAD_END_TLV_LEN); 330 } 331 332 static void mlxsw_emad_pack_reg_tlv(char *reg_tlv, 333 const struct mlxsw_reg_info *reg, 334 char *payload) 335 { 336 mlxsw_emad_reg_tlv_type_set(reg_tlv, MLXSW_EMAD_TLV_TYPE_REG); 337 mlxsw_emad_reg_tlv_len_set(reg_tlv, reg->len / sizeof(u32) + 1); 338 memcpy(reg_tlv + sizeof(u32), payload, reg->len); 339 } 340 341 static void mlxsw_emad_pack_string_tlv(char *string_tlv) 342 { 343 mlxsw_emad_string_tlv_type_set(string_tlv, MLXSW_EMAD_TLV_TYPE_STRING); 344 mlxsw_emad_string_tlv_len_set(string_tlv, MLXSW_EMAD_STRING_TLV_LEN); 345 } 346 347 static void mlxsw_emad_pack_op_tlv(char *op_tlv, 348 const struct mlxsw_reg_info *reg, 349 enum mlxsw_core_reg_access_type type, 350 u64 tid) 351 { 352 mlxsw_emad_op_tlv_type_set(op_tlv, MLXSW_EMAD_TLV_TYPE_OP); 353 mlxsw_emad_op_tlv_len_set(op_tlv, MLXSW_EMAD_OP_TLV_LEN); 354 mlxsw_emad_op_tlv_dr_set(op_tlv, 0); 355 mlxsw_emad_op_tlv_status_set(op_tlv, 0); 356 mlxsw_emad_op_tlv_register_id_set(op_tlv, reg->id); 357 mlxsw_emad_op_tlv_r_set(op_tlv, MLXSW_EMAD_OP_TLV_REQUEST); 358 if (type == MLXSW_CORE_REG_ACCESS_TYPE_QUERY) 359 mlxsw_emad_op_tlv_method_set(op_tlv, 360 MLXSW_EMAD_OP_TLV_METHOD_QUERY); 361 else 362 mlxsw_emad_op_tlv_method_set(op_tlv, 363 MLXSW_EMAD_OP_TLV_METHOD_WRITE); 364 mlxsw_emad_op_tlv_class_set(op_tlv, 365 MLXSW_EMAD_OP_TLV_CLASS_REG_ACCESS); 366 mlxsw_emad_op_tlv_tid_set(op_tlv, tid); 367 } 368 369 static int mlxsw_emad_construct_eth_hdr(struct sk_buff *skb) 370 { 371 char *eth_hdr = skb_push(skb, MLXSW_EMAD_ETH_HDR_LEN); 372 373 mlxsw_emad_eth_hdr_dmac_memcpy_to(eth_hdr, MLXSW_EMAD_EH_DMAC); 374 mlxsw_emad_eth_hdr_smac_memcpy_to(eth_hdr, MLXSW_EMAD_EH_SMAC); 375 mlxsw_emad_eth_hdr_ethertype_set(eth_hdr, MLXSW_EMAD_EH_ETHERTYPE); 376 mlxsw_emad_eth_hdr_mlx_proto_set(eth_hdr, MLXSW_EMAD_EH_MLX_PROTO); 377 mlxsw_emad_eth_hdr_ver_set(eth_hdr, MLXSW_EMAD_EH_PROTO_VERSION); 378 379 skb_reset_mac_header(skb); 380 381 return 0; 382 } 383 384 static void mlxsw_emad_construct(struct sk_buff *skb, 385 const struct mlxsw_reg_info *reg, 386 char *payload, 387 enum mlxsw_core_reg_access_type type, 388 u64 tid, bool enable_string_tlv) 389 { 390 char *buf; 391 392 buf = skb_push(skb, MLXSW_EMAD_END_TLV_LEN * sizeof(u32)); 393 mlxsw_emad_pack_end_tlv(buf); 394 395 buf = skb_push(skb, reg->len + sizeof(u32)); 396 mlxsw_emad_pack_reg_tlv(buf, reg, payload); 397 398 if (enable_string_tlv) { 399 buf = skb_push(skb, MLXSW_EMAD_STRING_TLV_LEN * sizeof(u32)); 400 mlxsw_emad_pack_string_tlv(buf); 401 } 402 403 buf = skb_push(skb, MLXSW_EMAD_OP_TLV_LEN * sizeof(u32)); 404 mlxsw_emad_pack_op_tlv(buf, reg, type, tid); 405 406 mlxsw_emad_construct_eth_hdr(skb); 407 } 408 409 struct mlxsw_emad_tlv_offsets { 410 u16 op_tlv; 411 u16 string_tlv; 412 u16 reg_tlv; 413 }; 414 415 static bool mlxsw_emad_tlv_is_string_tlv(const char *tlv) 416 { 417 u8 tlv_type = mlxsw_emad_string_tlv_type_get(tlv); 418 419 return tlv_type == MLXSW_EMAD_TLV_TYPE_STRING; 420 } 421 422 static void mlxsw_emad_tlv_parse(struct sk_buff *skb) 423 { 424 struct mlxsw_emad_tlv_offsets *offsets = 425 (struct mlxsw_emad_tlv_offsets *) skb->cb; 426 427 offsets->op_tlv = MLXSW_EMAD_ETH_HDR_LEN; 428 offsets->string_tlv = 0; 429 offsets->reg_tlv = MLXSW_EMAD_ETH_HDR_LEN + 430 MLXSW_EMAD_OP_TLV_LEN * sizeof(u32); 431 432 /* If string TLV is present, it must come after the operation TLV. */ 433 if (mlxsw_emad_tlv_is_string_tlv(skb->data + offsets->reg_tlv)) { 434 offsets->string_tlv = offsets->reg_tlv; 435 offsets->reg_tlv += MLXSW_EMAD_STRING_TLV_LEN * sizeof(u32); 436 } 437 } 438 439 static char *mlxsw_emad_op_tlv(const struct sk_buff *skb) 440 { 441 struct mlxsw_emad_tlv_offsets *offsets = 442 (struct mlxsw_emad_tlv_offsets *) skb->cb; 443 444 return ((char *) (skb->data + offsets->op_tlv)); 445 } 446 447 static char *mlxsw_emad_string_tlv(const struct sk_buff *skb) 448 { 449 struct mlxsw_emad_tlv_offsets *offsets = 450 (struct mlxsw_emad_tlv_offsets *) skb->cb; 451 452 if (!offsets->string_tlv) 453 return NULL; 454 455 return ((char *) (skb->data + offsets->string_tlv)); 456 } 457 458 static char *mlxsw_emad_reg_tlv(const struct sk_buff *skb) 459 { 460 struct mlxsw_emad_tlv_offsets *offsets = 461 (struct mlxsw_emad_tlv_offsets *) skb->cb; 462 463 return ((char *) (skb->data + offsets->reg_tlv)); 464 } 465 466 static char *mlxsw_emad_reg_payload(const char *reg_tlv) 467 { 468 return ((char *) (reg_tlv + sizeof(u32))); 469 } 470 471 static char *mlxsw_emad_reg_payload_cmd(const char *mbox) 472 { 473 return ((char *) (mbox + (MLXSW_EMAD_OP_TLV_LEN + 1) * sizeof(u32))); 474 } 475 476 static u64 mlxsw_emad_get_tid(const struct sk_buff *skb) 477 { 478 char *op_tlv; 479 480 op_tlv = mlxsw_emad_op_tlv(skb); 481 return mlxsw_emad_op_tlv_tid_get(op_tlv); 482 } 483 484 static bool mlxsw_emad_is_resp(const struct sk_buff *skb) 485 { 486 char *op_tlv; 487 488 op_tlv = mlxsw_emad_op_tlv(skb); 489 return (mlxsw_emad_op_tlv_r_get(op_tlv) == MLXSW_EMAD_OP_TLV_RESPONSE); 490 } 491 492 static int mlxsw_emad_process_status(char *op_tlv, 493 enum mlxsw_emad_op_tlv_status *p_status) 494 { 495 *p_status = mlxsw_emad_op_tlv_status_get(op_tlv); 496 497 switch (*p_status) { 498 case MLXSW_EMAD_OP_TLV_STATUS_SUCCESS: 499 return 0; 500 case MLXSW_EMAD_OP_TLV_STATUS_BUSY: 501 case MLXSW_EMAD_OP_TLV_STATUS_MESSAGE_RECEIPT_ACK: 502 return -EAGAIN; 503 case MLXSW_EMAD_OP_TLV_STATUS_VERSION_NOT_SUPPORTED: 504 case MLXSW_EMAD_OP_TLV_STATUS_UNKNOWN_TLV: 505 case MLXSW_EMAD_OP_TLV_STATUS_REGISTER_NOT_SUPPORTED: 506 case MLXSW_EMAD_OP_TLV_STATUS_CLASS_NOT_SUPPORTED: 507 case MLXSW_EMAD_OP_TLV_STATUS_METHOD_NOT_SUPPORTED: 508 case MLXSW_EMAD_OP_TLV_STATUS_BAD_PARAMETER: 509 case MLXSW_EMAD_OP_TLV_STATUS_RESOURCE_NOT_AVAILABLE: 510 case MLXSW_EMAD_OP_TLV_STATUS_INTERNAL_ERROR: 511 default: 512 return -EIO; 513 } 514 } 515 516 static int 517 mlxsw_emad_process_status_skb(struct sk_buff *skb, 518 enum mlxsw_emad_op_tlv_status *p_status) 519 { 520 return mlxsw_emad_process_status(mlxsw_emad_op_tlv(skb), p_status); 521 } 522 523 struct mlxsw_reg_trans { 524 struct list_head list; 525 struct list_head bulk_list; 526 struct mlxsw_core *core; 527 struct sk_buff *tx_skb; 528 struct mlxsw_tx_info tx_info; 529 struct delayed_work timeout_dw; 530 unsigned int retries; 531 u64 tid; 532 struct completion completion; 533 atomic_t active; 534 mlxsw_reg_trans_cb_t *cb; 535 unsigned long cb_priv; 536 const struct mlxsw_reg_info *reg; 537 enum mlxsw_core_reg_access_type type; 538 int err; 539 char *emad_err_string; 540 enum mlxsw_emad_op_tlv_status emad_status; 541 struct rcu_head rcu; 542 }; 543 544 static void mlxsw_emad_process_string_tlv(const struct sk_buff *skb, 545 struct mlxsw_reg_trans *trans) 546 { 547 char *string_tlv; 548 char *string; 549 550 string_tlv = mlxsw_emad_string_tlv(skb); 551 if (!string_tlv) 552 return; 553 554 trans->emad_err_string = kzalloc(MLXSW_EMAD_STRING_TLV_STRING_LEN, 555 GFP_ATOMIC); 556 if (!trans->emad_err_string) 557 return; 558 559 string = mlxsw_emad_string_tlv_string_data(string_tlv); 560 strlcpy(trans->emad_err_string, string, 561 MLXSW_EMAD_STRING_TLV_STRING_LEN); 562 } 563 564 #define MLXSW_EMAD_TIMEOUT_DURING_FW_FLASH_MS 3000 565 #define MLXSW_EMAD_TIMEOUT_MS 200 566 567 static void mlxsw_emad_trans_timeout_schedule(struct mlxsw_reg_trans *trans) 568 { 569 unsigned long timeout = msecs_to_jiffies(MLXSW_EMAD_TIMEOUT_MS); 570 571 if (trans->core->fw_flash_in_progress) 572 timeout = msecs_to_jiffies(MLXSW_EMAD_TIMEOUT_DURING_FW_FLASH_MS); 573 574 queue_delayed_work(trans->core->emad_wq, &trans->timeout_dw, 575 timeout << trans->retries); 576 } 577 578 static int mlxsw_emad_transmit(struct mlxsw_core *mlxsw_core, 579 struct mlxsw_reg_trans *trans) 580 { 581 struct sk_buff *skb; 582 int err; 583 584 skb = skb_copy(trans->tx_skb, GFP_KERNEL); 585 if (!skb) 586 return -ENOMEM; 587 588 trace_devlink_hwmsg(priv_to_devlink(mlxsw_core), false, 0, 589 skb->data + mlxsw_core->driver->txhdr_len, 590 skb->len - mlxsw_core->driver->txhdr_len); 591 592 atomic_set(&trans->active, 1); 593 err = mlxsw_core_skb_transmit(mlxsw_core, skb, &trans->tx_info); 594 if (err) { 595 dev_kfree_skb(skb); 596 return err; 597 } 598 mlxsw_emad_trans_timeout_schedule(trans); 599 return 0; 600 } 601 602 static void mlxsw_emad_trans_finish(struct mlxsw_reg_trans *trans, int err) 603 { 604 struct mlxsw_core *mlxsw_core = trans->core; 605 606 dev_kfree_skb(trans->tx_skb); 607 spin_lock_bh(&mlxsw_core->emad.trans_list_lock); 608 list_del_rcu(&trans->list); 609 spin_unlock_bh(&mlxsw_core->emad.trans_list_lock); 610 trans->err = err; 611 complete(&trans->completion); 612 } 613 614 static void mlxsw_emad_transmit_retry(struct mlxsw_core *mlxsw_core, 615 struct mlxsw_reg_trans *trans) 616 { 617 int err; 618 619 if (trans->retries < MLXSW_EMAD_MAX_RETRY) { 620 trans->retries++; 621 err = mlxsw_emad_transmit(trans->core, trans); 622 if (err == 0) 623 return; 624 625 if (!atomic_dec_and_test(&trans->active)) 626 return; 627 } else { 628 err = -EIO; 629 } 630 mlxsw_emad_trans_finish(trans, err); 631 } 632 633 static void mlxsw_emad_trans_timeout_work(struct work_struct *work) 634 { 635 struct mlxsw_reg_trans *trans = container_of(work, 636 struct mlxsw_reg_trans, 637 timeout_dw.work); 638 639 if (!atomic_dec_and_test(&trans->active)) 640 return; 641 642 mlxsw_emad_transmit_retry(trans->core, trans); 643 } 644 645 static void mlxsw_emad_process_response(struct mlxsw_core *mlxsw_core, 646 struct mlxsw_reg_trans *trans, 647 struct sk_buff *skb) 648 { 649 int err; 650 651 if (!atomic_dec_and_test(&trans->active)) 652 return; 653 654 err = mlxsw_emad_process_status_skb(skb, &trans->emad_status); 655 if (err == -EAGAIN) { 656 mlxsw_emad_transmit_retry(mlxsw_core, trans); 657 } else { 658 if (err == 0) { 659 char *reg_tlv = mlxsw_emad_reg_tlv(skb); 660 661 if (trans->cb) 662 trans->cb(mlxsw_core, 663 mlxsw_emad_reg_payload(reg_tlv), 664 trans->reg->len, trans->cb_priv); 665 } else { 666 mlxsw_emad_process_string_tlv(skb, trans); 667 } 668 mlxsw_emad_trans_finish(trans, err); 669 } 670 } 671 672 /* called with rcu read lock held */ 673 static void mlxsw_emad_rx_listener_func(struct sk_buff *skb, u8 local_port, 674 void *priv) 675 { 676 struct mlxsw_core *mlxsw_core = priv; 677 struct mlxsw_reg_trans *trans; 678 679 trace_devlink_hwmsg(priv_to_devlink(mlxsw_core), true, 0, 680 skb->data, skb->len); 681 682 mlxsw_emad_tlv_parse(skb); 683 684 if (!mlxsw_emad_is_resp(skb)) 685 goto free_skb; 686 687 list_for_each_entry_rcu(trans, &mlxsw_core->emad.trans_list, list) { 688 if (mlxsw_emad_get_tid(skb) == trans->tid) { 689 mlxsw_emad_process_response(mlxsw_core, trans, skb); 690 break; 691 } 692 } 693 694 free_skb: 695 dev_kfree_skb(skb); 696 } 697 698 static const struct mlxsw_listener mlxsw_emad_rx_listener = 699 MLXSW_RXL(mlxsw_emad_rx_listener_func, ETHEMAD, TRAP_TO_CPU, false, 700 EMAD, DISCARD); 701 702 static int mlxsw_emad_init(struct mlxsw_core *mlxsw_core) 703 { 704 struct workqueue_struct *emad_wq; 705 u64 tid; 706 int err; 707 708 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_TXRX)) 709 return 0; 710 711 emad_wq = alloc_workqueue("mlxsw_core_emad", 0, 0); 712 if (!emad_wq) 713 return -ENOMEM; 714 mlxsw_core->emad_wq = emad_wq; 715 716 /* Set the upper 32 bits of the transaction ID field to a random 717 * number. This allows us to discard EMADs addressed to other 718 * devices. 719 */ 720 get_random_bytes(&tid, 4); 721 tid <<= 32; 722 atomic64_set(&mlxsw_core->emad.tid, tid); 723 724 INIT_LIST_HEAD(&mlxsw_core->emad.trans_list); 725 spin_lock_init(&mlxsw_core->emad.trans_list_lock); 726 727 err = mlxsw_core_trap_register(mlxsw_core, &mlxsw_emad_rx_listener, 728 mlxsw_core); 729 if (err) 730 goto err_trap_register; 731 732 err = mlxsw_core->driver->basic_trap_groups_set(mlxsw_core); 733 if (err) 734 goto err_emad_trap_set; 735 mlxsw_core->emad.use_emad = true; 736 737 return 0; 738 739 err_emad_trap_set: 740 mlxsw_core_trap_unregister(mlxsw_core, &mlxsw_emad_rx_listener, 741 mlxsw_core); 742 err_trap_register: 743 destroy_workqueue(mlxsw_core->emad_wq); 744 return err; 745 } 746 747 static void mlxsw_emad_fini(struct mlxsw_core *mlxsw_core) 748 { 749 750 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_TXRX)) 751 return; 752 753 mlxsw_core->emad.use_emad = false; 754 mlxsw_core_trap_unregister(mlxsw_core, &mlxsw_emad_rx_listener, 755 mlxsw_core); 756 destroy_workqueue(mlxsw_core->emad_wq); 757 } 758 759 static struct sk_buff *mlxsw_emad_alloc(const struct mlxsw_core *mlxsw_core, 760 u16 reg_len, bool enable_string_tlv) 761 { 762 struct sk_buff *skb; 763 u16 emad_len; 764 765 emad_len = (reg_len + sizeof(u32) + MLXSW_EMAD_ETH_HDR_LEN + 766 (MLXSW_EMAD_OP_TLV_LEN + MLXSW_EMAD_END_TLV_LEN) * 767 sizeof(u32) + mlxsw_core->driver->txhdr_len); 768 if (enable_string_tlv) 769 emad_len += MLXSW_EMAD_STRING_TLV_LEN * sizeof(u32); 770 if (emad_len > MLXSW_EMAD_MAX_FRAME_LEN) 771 return NULL; 772 773 skb = netdev_alloc_skb(NULL, emad_len); 774 if (!skb) 775 return NULL; 776 memset(skb->data, 0, emad_len); 777 skb_reserve(skb, emad_len); 778 779 return skb; 780 } 781 782 static int mlxsw_emad_reg_access(struct mlxsw_core *mlxsw_core, 783 const struct mlxsw_reg_info *reg, 784 char *payload, 785 enum mlxsw_core_reg_access_type type, 786 struct mlxsw_reg_trans *trans, 787 struct list_head *bulk_list, 788 mlxsw_reg_trans_cb_t *cb, 789 unsigned long cb_priv, u64 tid) 790 { 791 bool enable_string_tlv; 792 struct sk_buff *skb; 793 int err; 794 795 dev_dbg(mlxsw_core->bus_info->dev, "EMAD reg access (tid=%llx,reg_id=%x(%s),type=%s)\n", 796 tid, reg->id, mlxsw_reg_id_str(reg->id), 797 mlxsw_core_reg_access_type_str(type)); 798 799 /* Since this can be changed during emad_reg_access, read it once and 800 * use the value all the way. 801 */ 802 enable_string_tlv = mlxsw_core->emad.enable_string_tlv; 803 804 skb = mlxsw_emad_alloc(mlxsw_core, reg->len, enable_string_tlv); 805 if (!skb) 806 return -ENOMEM; 807 808 list_add_tail(&trans->bulk_list, bulk_list); 809 trans->core = mlxsw_core; 810 trans->tx_skb = skb; 811 trans->tx_info.local_port = MLXSW_PORT_CPU_PORT; 812 trans->tx_info.is_emad = true; 813 INIT_DELAYED_WORK(&trans->timeout_dw, mlxsw_emad_trans_timeout_work); 814 trans->tid = tid; 815 init_completion(&trans->completion); 816 trans->cb = cb; 817 trans->cb_priv = cb_priv; 818 trans->reg = reg; 819 trans->type = type; 820 821 mlxsw_emad_construct(skb, reg, payload, type, trans->tid, 822 enable_string_tlv); 823 mlxsw_core->driver->txhdr_construct(skb, &trans->tx_info); 824 825 spin_lock_bh(&mlxsw_core->emad.trans_list_lock); 826 list_add_tail_rcu(&trans->list, &mlxsw_core->emad.trans_list); 827 spin_unlock_bh(&mlxsw_core->emad.trans_list_lock); 828 err = mlxsw_emad_transmit(mlxsw_core, trans); 829 if (err) 830 goto err_out; 831 return 0; 832 833 err_out: 834 spin_lock_bh(&mlxsw_core->emad.trans_list_lock); 835 list_del_rcu(&trans->list); 836 spin_unlock_bh(&mlxsw_core->emad.trans_list_lock); 837 list_del(&trans->bulk_list); 838 dev_kfree_skb(trans->tx_skb); 839 return err; 840 } 841 842 /***************** 843 * Core functions 844 *****************/ 845 846 int mlxsw_core_driver_register(struct mlxsw_driver *mlxsw_driver) 847 { 848 spin_lock(&mlxsw_core_driver_list_lock); 849 list_add_tail(&mlxsw_driver->list, &mlxsw_core_driver_list); 850 spin_unlock(&mlxsw_core_driver_list_lock); 851 return 0; 852 } 853 EXPORT_SYMBOL(mlxsw_core_driver_register); 854 855 void mlxsw_core_driver_unregister(struct mlxsw_driver *mlxsw_driver) 856 { 857 spin_lock(&mlxsw_core_driver_list_lock); 858 list_del(&mlxsw_driver->list); 859 spin_unlock(&mlxsw_core_driver_list_lock); 860 } 861 EXPORT_SYMBOL(mlxsw_core_driver_unregister); 862 863 static struct mlxsw_driver *__driver_find(const char *kind) 864 { 865 struct mlxsw_driver *mlxsw_driver; 866 867 list_for_each_entry(mlxsw_driver, &mlxsw_core_driver_list, list) { 868 if (strcmp(mlxsw_driver->kind, kind) == 0) 869 return mlxsw_driver; 870 } 871 return NULL; 872 } 873 874 static struct mlxsw_driver *mlxsw_core_driver_get(const char *kind) 875 { 876 struct mlxsw_driver *mlxsw_driver; 877 878 spin_lock(&mlxsw_core_driver_list_lock); 879 mlxsw_driver = __driver_find(kind); 880 spin_unlock(&mlxsw_core_driver_list_lock); 881 return mlxsw_driver; 882 } 883 884 struct mlxsw_core_fw_info { 885 struct mlxfw_dev mlxfw_dev; 886 struct mlxsw_core *mlxsw_core; 887 }; 888 889 static int mlxsw_core_fw_component_query(struct mlxfw_dev *mlxfw_dev, 890 u16 component_index, u32 *p_max_size, 891 u8 *p_align_bits, u16 *p_max_write_size) 892 { 893 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 894 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 895 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 896 char mcqi_pl[MLXSW_REG_MCQI_LEN]; 897 int err; 898 899 mlxsw_reg_mcqi_pack(mcqi_pl, component_index); 900 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mcqi), mcqi_pl); 901 if (err) 902 return err; 903 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits, p_max_write_size); 904 905 *p_align_bits = max_t(u8, *p_align_bits, 2); 906 *p_max_write_size = min_t(u16, *p_max_write_size, MLXSW_REG_MCDA_MAX_DATA_LEN); 907 return 0; 908 } 909 910 static int mlxsw_core_fw_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle) 911 { 912 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 913 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 914 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 915 char mcc_pl[MLXSW_REG_MCC_LEN]; 916 u8 control_state; 917 int err; 918 919 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0); 920 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 921 if (err) 922 return err; 923 924 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state); 925 if (control_state != MLXFW_FSM_STATE_IDLE) 926 return -EBUSY; 927 928 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE, 0, *fwhandle, 0); 929 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 930 } 931 932 static int mlxsw_core_fw_fsm_component_update(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 933 u16 component_index, u32 component_size) 934 { 935 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 936 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 937 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 938 char mcc_pl[MLXSW_REG_MCC_LEN]; 939 940 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT, 941 component_index, fwhandle, component_size); 942 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 943 } 944 945 static int mlxsw_core_fw_fsm_block_download(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 946 u8 *data, u16 size, u32 offset) 947 { 948 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 949 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 950 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 951 char mcda_pl[MLXSW_REG_MCDA_LEN]; 952 953 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data); 954 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcda), mcda_pl); 955 } 956 957 static int mlxsw_core_fw_fsm_component_verify(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 958 u16 component_index) 959 { 960 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 961 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 962 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 963 char mcc_pl[MLXSW_REG_MCC_LEN]; 964 965 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT, 966 component_index, fwhandle, 0); 967 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 968 } 969 970 static int mlxsw_core_fw_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 971 { 972 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 973 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 974 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 975 char mcc_pl[MLXSW_REG_MCC_LEN]; 976 977 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0, fwhandle, 0); 978 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 979 } 980 981 static int mlxsw_core_fw_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 982 enum mlxfw_fsm_state *fsm_state, 983 enum mlxfw_fsm_state_err *fsm_state_err) 984 { 985 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 986 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 987 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 988 char mcc_pl[MLXSW_REG_MCC_LEN]; 989 u8 control_state; 990 u8 error_code; 991 int err; 992 993 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0); 994 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 995 if (err) 996 return err; 997 998 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state); 999 *fsm_state = control_state; 1000 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code, MLXFW_FSM_STATE_ERR_MAX); 1001 return 0; 1002 } 1003 1004 static void mlxsw_core_fw_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 1005 { 1006 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1007 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1008 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1009 char mcc_pl[MLXSW_REG_MCC_LEN]; 1010 1011 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0, fwhandle, 0); 1012 mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1013 } 1014 1015 static void mlxsw_core_fw_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 1016 { 1017 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1018 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1019 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1020 char mcc_pl[MLXSW_REG_MCC_LEN]; 1021 1022 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0, fwhandle, 0); 1023 mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1024 } 1025 1026 static const struct mlxfw_dev_ops mlxsw_core_fw_mlxsw_dev_ops = { 1027 .component_query = mlxsw_core_fw_component_query, 1028 .fsm_lock = mlxsw_core_fw_fsm_lock, 1029 .fsm_component_update = mlxsw_core_fw_fsm_component_update, 1030 .fsm_block_download = mlxsw_core_fw_fsm_block_download, 1031 .fsm_component_verify = mlxsw_core_fw_fsm_component_verify, 1032 .fsm_activate = mlxsw_core_fw_fsm_activate, 1033 .fsm_query_state = mlxsw_core_fw_fsm_query_state, 1034 .fsm_cancel = mlxsw_core_fw_fsm_cancel, 1035 .fsm_release = mlxsw_core_fw_fsm_release, 1036 }; 1037 1038 static int mlxsw_core_fw_flash(struct mlxsw_core *mlxsw_core, const struct firmware *firmware, 1039 struct netlink_ext_ack *extack) 1040 { 1041 struct mlxsw_core_fw_info mlxsw_core_fw_info = { 1042 .mlxfw_dev = { 1043 .ops = &mlxsw_core_fw_mlxsw_dev_ops, 1044 .psid = mlxsw_core->bus_info->psid, 1045 .psid_size = strlen(mlxsw_core->bus_info->psid), 1046 .devlink = priv_to_devlink(mlxsw_core), 1047 }, 1048 .mlxsw_core = mlxsw_core 1049 }; 1050 int err; 1051 1052 mlxsw_core->fw_flash_in_progress = true; 1053 err = mlxfw_firmware_flash(&mlxsw_core_fw_info.mlxfw_dev, firmware, extack); 1054 mlxsw_core->fw_flash_in_progress = false; 1055 1056 return err; 1057 } 1058 1059 static int mlxsw_core_fw_rev_validate(struct mlxsw_core *mlxsw_core, 1060 const struct mlxsw_bus_info *mlxsw_bus_info, 1061 const struct mlxsw_fw_rev *req_rev, 1062 const char *filename) 1063 { 1064 const struct mlxsw_fw_rev *rev = &mlxsw_bus_info->fw_rev; 1065 union devlink_param_value value; 1066 const struct firmware *firmware; 1067 int err; 1068 1069 /* Don't check if driver does not require it */ 1070 if (!req_rev || !filename) 1071 return 0; 1072 1073 /* Don't check if devlink 'fw_load_policy' param is 'flash' */ 1074 err = devlink_param_driverinit_value_get(priv_to_devlink(mlxsw_core), 1075 DEVLINK_PARAM_GENERIC_ID_FW_LOAD_POLICY, 1076 &value); 1077 if (err) 1078 return err; 1079 if (value.vu8 == DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_FLASH) 1080 return 0; 1081 1082 /* Validate driver & FW are compatible */ 1083 if (rev->major != req_rev->major) { 1084 WARN(1, "Mismatch in major FW version [%d:%d] is never expected; Please contact support\n", 1085 rev->major, req_rev->major); 1086 return -EINVAL; 1087 } 1088 if (mlxsw_core_fw_rev_minor_subminor_validate(rev, req_rev)) 1089 return 0; 1090 1091 dev_err(mlxsw_bus_info->dev, "The firmware version %d.%d.%d is incompatible with the driver (required >= %d.%d.%d)\n", 1092 rev->major, rev->minor, rev->subminor, req_rev->major, 1093 req_rev->minor, req_rev->subminor); 1094 dev_info(mlxsw_bus_info->dev, "Flashing firmware using file %s\n", filename); 1095 1096 err = request_firmware_direct(&firmware, filename, mlxsw_bus_info->dev); 1097 if (err) { 1098 dev_err(mlxsw_bus_info->dev, "Could not request firmware file %s\n", filename); 1099 return err; 1100 } 1101 1102 err = mlxsw_core_fw_flash(mlxsw_core, firmware, NULL); 1103 release_firmware(firmware); 1104 if (err) 1105 dev_err(mlxsw_bus_info->dev, "Could not upgrade firmware\n"); 1106 1107 /* On FW flash success, tell the caller FW reset is needed 1108 * if current FW supports it. 1109 */ 1110 if (rev->minor >= req_rev->can_reset_minor) 1111 return err ? err : -EAGAIN; 1112 else 1113 return 0; 1114 } 1115 1116 static int mlxsw_core_fw_flash_update(struct mlxsw_core *mlxsw_core, 1117 struct devlink_flash_update_params *params, 1118 struct netlink_ext_ack *extack) 1119 { 1120 return mlxsw_core_fw_flash(mlxsw_core, params->fw, extack); 1121 } 1122 1123 static int mlxsw_core_devlink_param_fw_load_policy_validate(struct devlink *devlink, u32 id, 1124 union devlink_param_value val, 1125 struct netlink_ext_ack *extack) 1126 { 1127 if (val.vu8 != DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_DRIVER && 1128 val.vu8 != DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_FLASH) { 1129 NL_SET_ERR_MSG_MOD(extack, "'fw_load_policy' must be 'driver' or 'flash'"); 1130 return -EINVAL; 1131 } 1132 1133 return 0; 1134 } 1135 1136 static const struct devlink_param mlxsw_core_fw_devlink_params[] = { 1137 DEVLINK_PARAM_GENERIC(FW_LOAD_POLICY, BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), NULL, NULL, 1138 mlxsw_core_devlink_param_fw_load_policy_validate), 1139 }; 1140 1141 static int mlxsw_core_fw_params_register(struct mlxsw_core *mlxsw_core) 1142 { 1143 struct devlink *devlink = priv_to_devlink(mlxsw_core); 1144 union devlink_param_value value; 1145 int err; 1146 1147 err = devlink_params_register(devlink, mlxsw_core_fw_devlink_params, 1148 ARRAY_SIZE(mlxsw_core_fw_devlink_params)); 1149 if (err) 1150 return err; 1151 1152 value.vu8 = DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_DRIVER; 1153 devlink_param_driverinit_value_set(devlink, DEVLINK_PARAM_GENERIC_ID_FW_LOAD_POLICY, value); 1154 return 0; 1155 } 1156 1157 static void mlxsw_core_fw_params_unregister(struct mlxsw_core *mlxsw_core) 1158 { 1159 devlink_params_unregister(priv_to_devlink(mlxsw_core), mlxsw_core_fw_devlink_params, 1160 ARRAY_SIZE(mlxsw_core_fw_devlink_params)); 1161 } 1162 1163 static int mlxsw_devlink_port_split(struct devlink *devlink, 1164 unsigned int port_index, 1165 unsigned int count, 1166 struct netlink_ext_ack *extack) 1167 { 1168 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1169 1170 if (port_index >= mlxsw_core->max_ports) { 1171 NL_SET_ERR_MSG_MOD(extack, "Port index exceeds maximum number of ports"); 1172 return -EINVAL; 1173 } 1174 if (!mlxsw_core->driver->port_split) 1175 return -EOPNOTSUPP; 1176 return mlxsw_core->driver->port_split(mlxsw_core, port_index, count, 1177 extack); 1178 } 1179 1180 static int mlxsw_devlink_port_unsplit(struct devlink *devlink, 1181 unsigned int port_index, 1182 struct netlink_ext_ack *extack) 1183 { 1184 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1185 1186 if (port_index >= mlxsw_core->max_ports) { 1187 NL_SET_ERR_MSG_MOD(extack, "Port index exceeds maximum number of ports"); 1188 return -EINVAL; 1189 } 1190 if (!mlxsw_core->driver->port_unsplit) 1191 return -EOPNOTSUPP; 1192 return mlxsw_core->driver->port_unsplit(mlxsw_core, port_index, 1193 extack); 1194 } 1195 1196 static int 1197 mlxsw_devlink_sb_pool_get(struct devlink *devlink, 1198 unsigned int sb_index, u16 pool_index, 1199 struct devlink_sb_pool_info *pool_info) 1200 { 1201 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1202 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1203 1204 if (!mlxsw_driver->sb_pool_get) 1205 return -EOPNOTSUPP; 1206 return mlxsw_driver->sb_pool_get(mlxsw_core, sb_index, 1207 pool_index, pool_info); 1208 } 1209 1210 static int 1211 mlxsw_devlink_sb_pool_set(struct devlink *devlink, 1212 unsigned int sb_index, u16 pool_index, u32 size, 1213 enum devlink_sb_threshold_type threshold_type, 1214 struct netlink_ext_ack *extack) 1215 { 1216 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1217 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1218 1219 if (!mlxsw_driver->sb_pool_set) 1220 return -EOPNOTSUPP; 1221 return mlxsw_driver->sb_pool_set(mlxsw_core, sb_index, 1222 pool_index, size, threshold_type, 1223 extack); 1224 } 1225 1226 static void *__dl_port(struct devlink_port *devlink_port) 1227 { 1228 return container_of(devlink_port, struct mlxsw_core_port, devlink_port); 1229 } 1230 1231 static int mlxsw_devlink_port_type_set(struct devlink_port *devlink_port, 1232 enum devlink_port_type port_type) 1233 { 1234 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1235 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1236 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1237 1238 if (!mlxsw_driver->port_type_set) 1239 return -EOPNOTSUPP; 1240 1241 return mlxsw_driver->port_type_set(mlxsw_core, 1242 mlxsw_core_port->local_port, 1243 port_type); 1244 } 1245 1246 static int mlxsw_devlink_sb_port_pool_get(struct devlink_port *devlink_port, 1247 unsigned int sb_index, u16 pool_index, 1248 u32 *p_threshold) 1249 { 1250 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1251 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1252 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1253 1254 if (!mlxsw_driver->sb_port_pool_get || 1255 !mlxsw_core_port_check(mlxsw_core_port)) 1256 return -EOPNOTSUPP; 1257 return mlxsw_driver->sb_port_pool_get(mlxsw_core_port, sb_index, 1258 pool_index, p_threshold); 1259 } 1260 1261 static int mlxsw_devlink_sb_port_pool_set(struct devlink_port *devlink_port, 1262 unsigned int sb_index, u16 pool_index, 1263 u32 threshold, 1264 struct netlink_ext_ack *extack) 1265 { 1266 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1267 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1268 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1269 1270 if (!mlxsw_driver->sb_port_pool_set || 1271 !mlxsw_core_port_check(mlxsw_core_port)) 1272 return -EOPNOTSUPP; 1273 return mlxsw_driver->sb_port_pool_set(mlxsw_core_port, sb_index, 1274 pool_index, threshold, extack); 1275 } 1276 1277 static int 1278 mlxsw_devlink_sb_tc_pool_bind_get(struct devlink_port *devlink_port, 1279 unsigned int sb_index, u16 tc_index, 1280 enum devlink_sb_pool_type pool_type, 1281 u16 *p_pool_index, u32 *p_threshold) 1282 { 1283 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1284 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1285 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1286 1287 if (!mlxsw_driver->sb_tc_pool_bind_get || 1288 !mlxsw_core_port_check(mlxsw_core_port)) 1289 return -EOPNOTSUPP; 1290 return mlxsw_driver->sb_tc_pool_bind_get(mlxsw_core_port, sb_index, 1291 tc_index, pool_type, 1292 p_pool_index, p_threshold); 1293 } 1294 1295 static int 1296 mlxsw_devlink_sb_tc_pool_bind_set(struct devlink_port *devlink_port, 1297 unsigned int sb_index, u16 tc_index, 1298 enum devlink_sb_pool_type pool_type, 1299 u16 pool_index, u32 threshold, 1300 struct netlink_ext_ack *extack) 1301 { 1302 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1303 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1304 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1305 1306 if (!mlxsw_driver->sb_tc_pool_bind_set || 1307 !mlxsw_core_port_check(mlxsw_core_port)) 1308 return -EOPNOTSUPP; 1309 return mlxsw_driver->sb_tc_pool_bind_set(mlxsw_core_port, sb_index, 1310 tc_index, pool_type, 1311 pool_index, threshold, extack); 1312 } 1313 1314 static int mlxsw_devlink_sb_occ_snapshot(struct devlink *devlink, 1315 unsigned int sb_index) 1316 { 1317 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1318 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1319 1320 if (!mlxsw_driver->sb_occ_snapshot) 1321 return -EOPNOTSUPP; 1322 return mlxsw_driver->sb_occ_snapshot(mlxsw_core, sb_index); 1323 } 1324 1325 static int mlxsw_devlink_sb_occ_max_clear(struct devlink *devlink, 1326 unsigned int sb_index) 1327 { 1328 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1329 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1330 1331 if (!mlxsw_driver->sb_occ_max_clear) 1332 return -EOPNOTSUPP; 1333 return mlxsw_driver->sb_occ_max_clear(mlxsw_core, sb_index); 1334 } 1335 1336 static int 1337 mlxsw_devlink_sb_occ_port_pool_get(struct devlink_port *devlink_port, 1338 unsigned int sb_index, u16 pool_index, 1339 u32 *p_cur, u32 *p_max) 1340 { 1341 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1342 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1343 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1344 1345 if (!mlxsw_driver->sb_occ_port_pool_get || 1346 !mlxsw_core_port_check(mlxsw_core_port)) 1347 return -EOPNOTSUPP; 1348 return mlxsw_driver->sb_occ_port_pool_get(mlxsw_core_port, sb_index, 1349 pool_index, p_cur, p_max); 1350 } 1351 1352 static int 1353 mlxsw_devlink_sb_occ_tc_port_bind_get(struct devlink_port *devlink_port, 1354 unsigned int sb_index, u16 tc_index, 1355 enum devlink_sb_pool_type pool_type, 1356 u32 *p_cur, u32 *p_max) 1357 { 1358 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1359 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1360 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1361 1362 if (!mlxsw_driver->sb_occ_tc_port_bind_get || 1363 !mlxsw_core_port_check(mlxsw_core_port)) 1364 return -EOPNOTSUPP; 1365 return mlxsw_driver->sb_occ_tc_port_bind_get(mlxsw_core_port, 1366 sb_index, tc_index, 1367 pool_type, p_cur, p_max); 1368 } 1369 1370 static int 1371 mlxsw_devlink_info_get(struct devlink *devlink, struct devlink_info_req *req, 1372 struct netlink_ext_ack *extack) 1373 { 1374 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1375 char fw_info_psid[MLXSW_REG_MGIR_FW_INFO_PSID_SIZE]; 1376 u32 hw_rev, fw_major, fw_minor, fw_sub_minor; 1377 char mgir_pl[MLXSW_REG_MGIR_LEN]; 1378 char buf[32]; 1379 int err; 1380 1381 err = devlink_info_driver_name_put(req, 1382 mlxsw_core->bus_info->device_kind); 1383 if (err) 1384 return err; 1385 1386 mlxsw_reg_mgir_pack(mgir_pl); 1387 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mgir), mgir_pl); 1388 if (err) 1389 return err; 1390 mlxsw_reg_mgir_unpack(mgir_pl, &hw_rev, fw_info_psid, &fw_major, 1391 &fw_minor, &fw_sub_minor); 1392 1393 sprintf(buf, "%X", hw_rev); 1394 err = devlink_info_version_fixed_put(req, "hw.revision", buf); 1395 if (err) 1396 return err; 1397 1398 err = devlink_info_version_fixed_put(req, "fw.psid", fw_info_psid); 1399 if (err) 1400 return err; 1401 1402 sprintf(buf, "%d.%d.%d", fw_major, fw_minor, fw_sub_minor); 1403 err = devlink_info_version_running_put(req, "fw.version", buf); 1404 if (err) 1405 return err; 1406 1407 return 0; 1408 } 1409 1410 static int 1411 mlxsw_devlink_core_bus_device_reload_down(struct devlink *devlink, 1412 bool netns_change, enum devlink_reload_action action, 1413 enum devlink_reload_limit limit, 1414 struct netlink_ext_ack *extack) 1415 { 1416 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1417 1418 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_RESET)) 1419 return -EOPNOTSUPP; 1420 1421 mlxsw_core_bus_device_unregister(mlxsw_core, true); 1422 return 0; 1423 } 1424 1425 static int 1426 mlxsw_devlink_core_bus_device_reload_up(struct devlink *devlink, enum devlink_reload_action action, 1427 enum devlink_reload_limit limit, u32 *actions_performed, 1428 struct netlink_ext_ack *extack) 1429 { 1430 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1431 1432 *actions_performed = BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT) | 1433 BIT(DEVLINK_RELOAD_ACTION_FW_ACTIVATE); 1434 return mlxsw_core_bus_device_register(mlxsw_core->bus_info, 1435 mlxsw_core->bus, 1436 mlxsw_core->bus_priv, true, 1437 devlink, extack); 1438 } 1439 1440 static int mlxsw_devlink_flash_update(struct devlink *devlink, 1441 struct devlink_flash_update_params *params, 1442 struct netlink_ext_ack *extack) 1443 { 1444 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1445 1446 return mlxsw_core_fw_flash_update(mlxsw_core, params, extack); 1447 } 1448 1449 static int mlxsw_devlink_trap_init(struct devlink *devlink, 1450 const struct devlink_trap *trap, 1451 void *trap_ctx) 1452 { 1453 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1454 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1455 1456 if (!mlxsw_driver->trap_init) 1457 return -EOPNOTSUPP; 1458 return mlxsw_driver->trap_init(mlxsw_core, trap, trap_ctx); 1459 } 1460 1461 static void mlxsw_devlink_trap_fini(struct devlink *devlink, 1462 const struct devlink_trap *trap, 1463 void *trap_ctx) 1464 { 1465 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1466 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1467 1468 if (!mlxsw_driver->trap_fini) 1469 return; 1470 mlxsw_driver->trap_fini(mlxsw_core, trap, trap_ctx); 1471 } 1472 1473 static int mlxsw_devlink_trap_action_set(struct devlink *devlink, 1474 const struct devlink_trap *trap, 1475 enum devlink_trap_action action, 1476 struct netlink_ext_ack *extack) 1477 { 1478 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1479 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1480 1481 if (!mlxsw_driver->trap_action_set) 1482 return -EOPNOTSUPP; 1483 return mlxsw_driver->trap_action_set(mlxsw_core, trap, action, extack); 1484 } 1485 1486 static int 1487 mlxsw_devlink_trap_group_init(struct devlink *devlink, 1488 const struct devlink_trap_group *group) 1489 { 1490 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1491 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1492 1493 if (!mlxsw_driver->trap_group_init) 1494 return -EOPNOTSUPP; 1495 return mlxsw_driver->trap_group_init(mlxsw_core, group); 1496 } 1497 1498 static int 1499 mlxsw_devlink_trap_group_set(struct devlink *devlink, 1500 const struct devlink_trap_group *group, 1501 const struct devlink_trap_policer *policer, 1502 struct netlink_ext_ack *extack) 1503 { 1504 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1505 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1506 1507 if (!mlxsw_driver->trap_group_set) 1508 return -EOPNOTSUPP; 1509 return mlxsw_driver->trap_group_set(mlxsw_core, group, policer, extack); 1510 } 1511 1512 static int 1513 mlxsw_devlink_trap_policer_init(struct devlink *devlink, 1514 const struct devlink_trap_policer *policer) 1515 { 1516 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1517 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1518 1519 if (!mlxsw_driver->trap_policer_init) 1520 return -EOPNOTSUPP; 1521 return mlxsw_driver->trap_policer_init(mlxsw_core, policer); 1522 } 1523 1524 static void 1525 mlxsw_devlink_trap_policer_fini(struct devlink *devlink, 1526 const struct devlink_trap_policer *policer) 1527 { 1528 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1529 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1530 1531 if (!mlxsw_driver->trap_policer_fini) 1532 return; 1533 mlxsw_driver->trap_policer_fini(mlxsw_core, policer); 1534 } 1535 1536 static int 1537 mlxsw_devlink_trap_policer_set(struct devlink *devlink, 1538 const struct devlink_trap_policer *policer, 1539 u64 rate, u64 burst, 1540 struct netlink_ext_ack *extack) 1541 { 1542 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1543 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1544 1545 if (!mlxsw_driver->trap_policer_set) 1546 return -EOPNOTSUPP; 1547 return mlxsw_driver->trap_policer_set(mlxsw_core, policer, rate, burst, 1548 extack); 1549 } 1550 1551 static int 1552 mlxsw_devlink_trap_policer_counter_get(struct devlink *devlink, 1553 const struct devlink_trap_policer *policer, 1554 u64 *p_drops) 1555 { 1556 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1557 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1558 1559 if (!mlxsw_driver->trap_policer_counter_get) 1560 return -EOPNOTSUPP; 1561 return mlxsw_driver->trap_policer_counter_get(mlxsw_core, policer, 1562 p_drops); 1563 } 1564 1565 static const struct devlink_ops mlxsw_devlink_ops = { 1566 .reload_actions = BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT) | 1567 BIT(DEVLINK_RELOAD_ACTION_FW_ACTIVATE), 1568 .reload_down = mlxsw_devlink_core_bus_device_reload_down, 1569 .reload_up = mlxsw_devlink_core_bus_device_reload_up, 1570 .port_type_set = mlxsw_devlink_port_type_set, 1571 .port_split = mlxsw_devlink_port_split, 1572 .port_unsplit = mlxsw_devlink_port_unsplit, 1573 .sb_pool_get = mlxsw_devlink_sb_pool_get, 1574 .sb_pool_set = mlxsw_devlink_sb_pool_set, 1575 .sb_port_pool_get = mlxsw_devlink_sb_port_pool_get, 1576 .sb_port_pool_set = mlxsw_devlink_sb_port_pool_set, 1577 .sb_tc_pool_bind_get = mlxsw_devlink_sb_tc_pool_bind_get, 1578 .sb_tc_pool_bind_set = mlxsw_devlink_sb_tc_pool_bind_set, 1579 .sb_occ_snapshot = mlxsw_devlink_sb_occ_snapshot, 1580 .sb_occ_max_clear = mlxsw_devlink_sb_occ_max_clear, 1581 .sb_occ_port_pool_get = mlxsw_devlink_sb_occ_port_pool_get, 1582 .sb_occ_tc_port_bind_get = mlxsw_devlink_sb_occ_tc_port_bind_get, 1583 .info_get = mlxsw_devlink_info_get, 1584 .flash_update = mlxsw_devlink_flash_update, 1585 .trap_init = mlxsw_devlink_trap_init, 1586 .trap_fini = mlxsw_devlink_trap_fini, 1587 .trap_action_set = mlxsw_devlink_trap_action_set, 1588 .trap_group_init = mlxsw_devlink_trap_group_init, 1589 .trap_group_set = mlxsw_devlink_trap_group_set, 1590 .trap_policer_init = mlxsw_devlink_trap_policer_init, 1591 .trap_policer_fini = mlxsw_devlink_trap_policer_fini, 1592 .trap_policer_set = mlxsw_devlink_trap_policer_set, 1593 .trap_policer_counter_get = mlxsw_devlink_trap_policer_counter_get, 1594 }; 1595 1596 static int mlxsw_core_params_register(struct mlxsw_core *mlxsw_core) 1597 { 1598 int err; 1599 1600 err = mlxsw_core_fw_params_register(mlxsw_core); 1601 if (err) 1602 return err; 1603 1604 if (mlxsw_core->driver->params_register) { 1605 err = mlxsw_core->driver->params_register(mlxsw_core); 1606 if (err) 1607 goto err_params_register; 1608 } 1609 return 0; 1610 1611 err_params_register: 1612 mlxsw_core_fw_params_unregister(mlxsw_core); 1613 return err; 1614 } 1615 1616 static void mlxsw_core_params_unregister(struct mlxsw_core *mlxsw_core) 1617 { 1618 mlxsw_core_fw_params_unregister(mlxsw_core); 1619 if (mlxsw_core->driver->params_register) 1620 mlxsw_core->driver->params_unregister(mlxsw_core); 1621 } 1622 1623 struct mlxsw_core_health_event { 1624 struct mlxsw_core *mlxsw_core; 1625 char mfde_pl[MLXSW_REG_MFDE_LEN]; 1626 struct work_struct work; 1627 }; 1628 1629 static void mlxsw_core_health_event_work(struct work_struct *work) 1630 { 1631 struct mlxsw_core_health_event *event; 1632 struct mlxsw_core *mlxsw_core; 1633 1634 event = container_of(work, struct mlxsw_core_health_event, work); 1635 mlxsw_core = event->mlxsw_core; 1636 devlink_health_report(mlxsw_core->health.fw_fatal, "FW fatal event occurred", 1637 event->mfde_pl); 1638 kfree(event); 1639 } 1640 1641 static void mlxsw_core_health_listener_func(const struct mlxsw_reg_info *reg, 1642 char *mfde_pl, void *priv) 1643 { 1644 struct mlxsw_core_health_event *event; 1645 struct mlxsw_core *mlxsw_core = priv; 1646 1647 event = kmalloc(sizeof(*event), GFP_ATOMIC); 1648 if (!event) 1649 return; 1650 event->mlxsw_core = mlxsw_core; 1651 memcpy(event->mfde_pl, mfde_pl, sizeof(event->mfde_pl)); 1652 INIT_WORK(&event->work, mlxsw_core_health_event_work); 1653 mlxsw_core_schedule_work(&event->work); 1654 } 1655 1656 static const struct mlxsw_listener mlxsw_core_health_listener = 1657 MLXSW_EVENTL(mlxsw_core_health_listener_func, MFDE, MFDE); 1658 1659 static int mlxsw_core_health_fw_fatal_dump(struct devlink_health_reporter *reporter, 1660 struct devlink_fmsg *fmsg, void *priv_ctx, 1661 struct netlink_ext_ack *extack) 1662 { 1663 char *mfde_pl = priv_ctx; 1664 char *val_str; 1665 u8 event_id; 1666 u32 val; 1667 int err; 1668 1669 if (!priv_ctx) 1670 /* User-triggered dumps are not possible */ 1671 return -EOPNOTSUPP; 1672 1673 val = mlxsw_reg_mfde_irisc_id_get(mfde_pl); 1674 err = devlink_fmsg_u8_pair_put(fmsg, "irisc_id", val); 1675 if (err) 1676 return err; 1677 err = devlink_fmsg_arr_pair_nest_start(fmsg, "event"); 1678 if (err) 1679 return err; 1680 1681 event_id = mlxsw_reg_mfde_event_id_get(mfde_pl); 1682 err = devlink_fmsg_u8_pair_put(fmsg, "id", event_id); 1683 if (err) 1684 return err; 1685 switch (event_id) { 1686 case MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO: 1687 val_str = "CR space timeout"; 1688 break; 1689 case MLXSW_REG_MFDE_EVENT_ID_KVD_IM_STOP: 1690 val_str = "KVD insertion machine stopped"; 1691 break; 1692 default: 1693 val_str = NULL; 1694 } 1695 if (val_str) { 1696 err = devlink_fmsg_string_pair_put(fmsg, "desc", val_str); 1697 if (err) 1698 return err; 1699 } 1700 err = devlink_fmsg_arr_pair_nest_end(fmsg); 1701 if (err) 1702 return err; 1703 1704 val = mlxsw_reg_mfde_method_get(mfde_pl); 1705 switch (val) { 1706 case MLXSW_REG_MFDE_METHOD_QUERY: 1707 val_str = "query"; 1708 break; 1709 case MLXSW_REG_MFDE_METHOD_WRITE: 1710 val_str = "write"; 1711 break; 1712 default: 1713 val_str = NULL; 1714 } 1715 if (val_str) { 1716 err = devlink_fmsg_string_pair_put(fmsg, "method", val_str); 1717 if (err) 1718 return err; 1719 } 1720 1721 val = mlxsw_reg_mfde_long_process_get(mfde_pl); 1722 err = devlink_fmsg_bool_pair_put(fmsg, "long_process", val); 1723 if (err) 1724 return err; 1725 1726 val = mlxsw_reg_mfde_command_type_get(mfde_pl); 1727 switch (val) { 1728 case MLXSW_REG_MFDE_COMMAND_TYPE_MAD: 1729 val_str = "mad"; 1730 break; 1731 case MLXSW_REG_MFDE_COMMAND_TYPE_EMAD: 1732 val_str = "emad"; 1733 break; 1734 case MLXSW_REG_MFDE_COMMAND_TYPE_CMDIF: 1735 val_str = "cmdif"; 1736 break; 1737 default: 1738 val_str = NULL; 1739 } 1740 if (val_str) { 1741 err = devlink_fmsg_string_pair_put(fmsg, "command_type", val_str); 1742 if (err) 1743 return err; 1744 } 1745 1746 val = mlxsw_reg_mfde_reg_attr_id_get(mfde_pl); 1747 err = devlink_fmsg_u32_pair_put(fmsg, "reg_attr_id", val); 1748 if (err) 1749 return err; 1750 1751 if (event_id == MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO) { 1752 val = mlxsw_reg_mfde_log_address_get(mfde_pl); 1753 err = devlink_fmsg_u32_pair_put(fmsg, "log_address", val); 1754 if (err) 1755 return err; 1756 val = mlxsw_reg_mfde_log_id_get(mfde_pl); 1757 err = devlink_fmsg_u8_pair_put(fmsg, "log_irisc_id", val); 1758 if (err) 1759 return err; 1760 } else if (event_id == MLXSW_REG_MFDE_EVENT_ID_KVD_IM_STOP) { 1761 val = mlxsw_reg_mfde_pipes_mask_get(mfde_pl); 1762 err = devlink_fmsg_u32_pair_put(fmsg, "pipes_mask", val); 1763 if (err) 1764 return err; 1765 } 1766 1767 return 0; 1768 } 1769 1770 static int 1771 mlxsw_core_health_fw_fatal_test(struct devlink_health_reporter *reporter, 1772 struct netlink_ext_ack *extack) 1773 { 1774 struct mlxsw_core *mlxsw_core = devlink_health_reporter_priv(reporter); 1775 char mfgd_pl[MLXSW_REG_MFGD_LEN]; 1776 int err; 1777 1778 /* Read the register first to make sure no other bits are changed. */ 1779 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mfgd), mfgd_pl); 1780 if (err) 1781 return err; 1782 mlxsw_reg_mfgd_trigger_test_set(mfgd_pl, true); 1783 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mfgd), mfgd_pl); 1784 } 1785 1786 static const struct devlink_health_reporter_ops 1787 mlxsw_core_health_fw_fatal_ops = { 1788 .name = "fw_fatal", 1789 .dump = mlxsw_core_health_fw_fatal_dump, 1790 .test = mlxsw_core_health_fw_fatal_test, 1791 }; 1792 1793 static int mlxsw_core_health_fw_fatal_config(struct mlxsw_core *mlxsw_core, 1794 bool enable) 1795 { 1796 char mfgd_pl[MLXSW_REG_MFGD_LEN]; 1797 int err; 1798 1799 /* Read the register first to make sure no other bits are changed. */ 1800 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mfgd), mfgd_pl); 1801 if (err) 1802 return err; 1803 mlxsw_reg_mfgd_fatal_event_mode_set(mfgd_pl, enable); 1804 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mfgd), mfgd_pl); 1805 } 1806 1807 static int mlxsw_core_health_init(struct mlxsw_core *mlxsw_core) 1808 { 1809 struct devlink *devlink = priv_to_devlink(mlxsw_core); 1810 struct devlink_health_reporter *fw_fatal; 1811 int err; 1812 1813 if (!mlxsw_core->driver->fw_fatal_enabled) 1814 return 0; 1815 1816 fw_fatal = devlink_health_reporter_create(devlink, &mlxsw_core_health_fw_fatal_ops, 1817 0, mlxsw_core); 1818 if (IS_ERR(fw_fatal)) { 1819 dev_err(mlxsw_core->bus_info->dev, "Failed to create fw fatal reporter"); 1820 return PTR_ERR(fw_fatal); 1821 } 1822 mlxsw_core->health.fw_fatal = fw_fatal; 1823 1824 err = mlxsw_core_trap_register(mlxsw_core, &mlxsw_core_health_listener, mlxsw_core); 1825 if (err) 1826 goto err_trap_register; 1827 1828 err = mlxsw_core_health_fw_fatal_config(mlxsw_core, true); 1829 if (err) 1830 goto err_fw_fatal_config; 1831 1832 return 0; 1833 1834 err_fw_fatal_config: 1835 mlxsw_core_trap_unregister(mlxsw_core, &mlxsw_core_health_listener, mlxsw_core); 1836 err_trap_register: 1837 devlink_health_reporter_destroy(mlxsw_core->health.fw_fatal); 1838 return err; 1839 } 1840 1841 static void mlxsw_core_health_fini(struct mlxsw_core *mlxsw_core) 1842 { 1843 if (!mlxsw_core->driver->fw_fatal_enabled) 1844 return; 1845 1846 mlxsw_core_health_fw_fatal_config(mlxsw_core, false); 1847 mlxsw_core_trap_unregister(mlxsw_core, &mlxsw_core_health_listener, mlxsw_core); 1848 /* Make sure there is no more event work scheduled */ 1849 mlxsw_core_flush_owq(); 1850 devlink_health_reporter_destroy(mlxsw_core->health.fw_fatal); 1851 } 1852 1853 static int 1854 __mlxsw_core_bus_device_register(const struct mlxsw_bus_info *mlxsw_bus_info, 1855 const struct mlxsw_bus *mlxsw_bus, 1856 void *bus_priv, bool reload, 1857 struct devlink *devlink, 1858 struct netlink_ext_ack *extack) 1859 { 1860 const char *device_kind = mlxsw_bus_info->device_kind; 1861 struct mlxsw_core *mlxsw_core; 1862 struct mlxsw_driver *mlxsw_driver; 1863 struct mlxsw_res *res; 1864 size_t alloc_size; 1865 int err; 1866 1867 mlxsw_driver = mlxsw_core_driver_get(device_kind); 1868 if (!mlxsw_driver) 1869 return -EINVAL; 1870 1871 if (!reload) { 1872 alloc_size = sizeof(*mlxsw_core) + mlxsw_driver->priv_size; 1873 devlink = devlink_alloc(&mlxsw_devlink_ops, alloc_size); 1874 if (!devlink) { 1875 err = -ENOMEM; 1876 goto err_devlink_alloc; 1877 } 1878 } 1879 1880 mlxsw_core = devlink_priv(devlink); 1881 INIT_LIST_HEAD(&mlxsw_core->rx_listener_list); 1882 INIT_LIST_HEAD(&mlxsw_core->event_listener_list); 1883 mlxsw_core->driver = mlxsw_driver; 1884 mlxsw_core->bus = mlxsw_bus; 1885 mlxsw_core->bus_priv = bus_priv; 1886 mlxsw_core->bus_info = mlxsw_bus_info; 1887 1888 res = mlxsw_driver->res_query_enabled ? &mlxsw_core->res : NULL; 1889 err = mlxsw_bus->init(bus_priv, mlxsw_core, mlxsw_driver->profile, res); 1890 if (err) 1891 goto err_bus_init; 1892 1893 if (mlxsw_driver->resources_register && !reload) { 1894 err = mlxsw_driver->resources_register(mlxsw_core); 1895 if (err) 1896 goto err_register_resources; 1897 } 1898 1899 err = mlxsw_ports_init(mlxsw_core); 1900 if (err) 1901 goto err_ports_init; 1902 1903 if (MLXSW_CORE_RES_VALID(mlxsw_core, MAX_LAG) && 1904 MLXSW_CORE_RES_VALID(mlxsw_core, MAX_LAG_MEMBERS)) { 1905 alloc_size = sizeof(u8) * 1906 MLXSW_CORE_RES_GET(mlxsw_core, MAX_LAG) * 1907 MLXSW_CORE_RES_GET(mlxsw_core, MAX_LAG_MEMBERS); 1908 mlxsw_core->lag.mapping = kzalloc(alloc_size, GFP_KERNEL); 1909 if (!mlxsw_core->lag.mapping) { 1910 err = -ENOMEM; 1911 goto err_alloc_lag_mapping; 1912 } 1913 } 1914 1915 err = mlxsw_emad_init(mlxsw_core); 1916 if (err) 1917 goto err_emad_init; 1918 1919 if (!reload) { 1920 err = devlink_register(devlink, mlxsw_bus_info->dev); 1921 if (err) 1922 goto err_devlink_register; 1923 } 1924 1925 if (!reload) { 1926 err = mlxsw_core_params_register(mlxsw_core); 1927 if (err) 1928 goto err_register_params; 1929 } 1930 1931 err = mlxsw_core_fw_rev_validate(mlxsw_core, mlxsw_bus_info, mlxsw_driver->fw_req_rev, 1932 mlxsw_driver->fw_filename); 1933 if (err) 1934 goto err_fw_rev_validate; 1935 1936 err = mlxsw_core_health_init(mlxsw_core); 1937 if (err) 1938 goto err_health_init; 1939 1940 if (mlxsw_driver->init) { 1941 err = mlxsw_driver->init(mlxsw_core, mlxsw_bus_info, extack); 1942 if (err) 1943 goto err_driver_init; 1944 } 1945 1946 err = mlxsw_hwmon_init(mlxsw_core, mlxsw_bus_info, &mlxsw_core->hwmon); 1947 if (err) 1948 goto err_hwmon_init; 1949 1950 err = mlxsw_thermal_init(mlxsw_core, mlxsw_bus_info, 1951 &mlxsw_core->thermal); 1952 if (err) 1953 goto err_thermal_init; 1954 1955 err = mlxsw_env_init(mlxsw_core, &mlxsw_core->env); 1956 if (err) 1957 goto err_env_init; 1958 1959 mlxsw_core->is_initialized = true; 1960 devlink_params_publish(devlink); 1961 1962 if (!reload) 1963 devlink_reload_enable(devlink); 1964 1965 return 0; 1966 1967 err_env_init: 1968 mlxsw_thermal_fini(mlxsw_core->thermal); 1969 err_thermal_init: 1970 mlxsw_hwmon_fini(mlxsw_core->hwmon); 1971 err_hwmon_init: 1972 if (mlxsw_core->driver->fini) 1973 mlxsw_core->driver->fini(mlxsw_core); 1974 err_driver_init: 1975 mlxsw_core_health_fini(mlxsw_core); 1976 err_health_init: 1977 err_fw_rev_validate: 1978 if (!reload) 1979 mlxsw_core_params_unregister(mlxsw_core); 1980 err_register_params: 1981 if (!reload) 1982 devlink_unregister(devlink); 1983 err_devlink_register: 1984 mlxsw_emad_fini(mlxsw_core); 1985 err_emad_init: 1986 kfree(mlxsw_core->lag.mapping); 1987 err_alloc_lag_mapping: 1988 mlxsw_ports_fini(mlxsw_core); 1989 err_ports_init: 1990 if (!reload) 1991 devlink_resources_unregister(devlink, NULL); 1992 err_register_resources: 1993 mlxsw_bus->fini(bus_priv); 1994 err_bus_init: 1995 if (!reload) 1996 devlink_free(devlink); 1997 err_devlink_alloc: 1998 return err; 1999 } 2000 2001 int mlxsw_core_bus_device_register(const struct mlxsw_bus_info *mlxsw_bus_info, 2002 const struct mlxsw_bus *mlxsw_bus, 2003 void *bus_priv, bool reload, 2004 struct devlink *devlink, 2005 struct netlink_ext_ack *extack) 2006 { 2007 bool called_again = false; 2008 int err; 2009 2010 again: 2011 err = __mlxsw_core_bus_device_register(mlxsw_bus_info, mlxsw_bus, 2012 bus_priv, reload, 2013 devlink, extack); 2014 /* -EAGAIN is returned in case the FW was updated. FW needs 2015 * a reset, so lets try to call __mlxsw_core_bus_device_register() 2016 * again. 2017 */ 2018 if (err == -EAGAIN && !called_again) { 2019 called_again = true; 2020 goto again; 2021 } 2022 2023 return err; 2024 } 2025 EXPORT_SYMBOL(mlxsw_core_bus_device_register); 2026 2027 void mlxsw_core_bus_device_unregister(struct mlxsw_core *mlxsw_core, 2028 bool reload) 2029 { 2030 struct devlink *devlink = priv_to_devlink(mlxsw_core); 2031 2032 if (!reload) 2033 devlink_reload_disable(devlink); 2034 if (devlink_is_reload_failed(devlink)) { 2035 if (!reload) 2036 /* Only the parts that were not de-initialized in the 2037 * failed reload attempt need to be de-initialized. 2038 */ 2039 goto reload_fail_deinit; 2040 else 2041 return; 2042 } 2043 2044 devlink_params_unpublish(devlink); 2045 mlxsw_core->is_initialized = false; 2046 mlxsw_env_fini(mlxsw_core->env); 2047 mlxsw_thermal_fini(mlxsw_core->thermal); 2048 mlxsw_hwmon_fini(mlxsw_core->hwmon); 2049 if (mlxsw_core->driver->fini) 2050 mlxsw_core->driver->fini(mlxsw_core); 2051 mlxsw_core_health_fini(mlxsw_core); 2052 if (!reload) 2053 mlxsw_core_params_unregister(mlxsw_core); 2054 if (!reload) 2055 devlink_unregister(devlink); 2056 mlxsw_emad_fini(mlxsw_core); 2057 kfree(mlxsw_core->lag.mapping); 2058 mlxsw_ports_fini(mlxsw_core); 2059 if (!reload) 2060 devlink_resources_unregister(devlink, NULL); 2061 mlxsw_core->bus->fini(mlxsw_core->bus_priv); 2062 if (!reload) 2063 devlink_free(devlink); 2064 2065 return; 2066 2067 reload_fail_deinit: 2068 mlxsw_core_params_unregister(mlxsw_core); 2069 devlink_unregister(devlink); 2070 devlink_resources_unregister(devlink, NULL); 2071 devlink_free(devlink); 2072 } 2073 EXPORT_SYMBOL(mlxsw_core_bus_device_unregister); 2074 2075 bool mlxsw_core_skb_transmit_busy(struct mlxsw_core *mlxsw_core, 2076 const struct mlxsw_tx_info *tx_info) 2077 { 2078 return mlxsw_core->bus->skb_transmit_busy(mlxsw_core->bus_priv, 2079 tx_info); 2080 } 2081 EXPORT_SYMBOL(mlxsw_core_skb_transmit_busy); 2082 2083 int mlxsw_core_skb_transmit(struct mlxsw_core *mlxsw_core, struct sk_buff *skb, 2084 const struct mlxsw_tx_info *tx_info) 2085 { 2086 return mlxsw_core->bus->skb_transmit(mlxsw_core->bus_priv, skb, 2087 tx_info); 2088 } 2089 EXPORT_SYMBOL(mlxsw_core_skb_transmit); 2090 2091 void mlxsw_core_ptp_transmitted(struct mlxsw_core *mlxsw_core, 2092 struct sk_buff *skb, u8 local_port) 2093 { 2094 if (mlxsw_core->driver->ptp_transmitted) 2095 mlxsw_core->driver->ptp_transmitted(mlxsw_core, skb, 2096 local_port); 2097 } 2098 EXPORT_SYMBOL(mlxsw_core_ptp_transmitted); 2099 2100 static bool __is_rx_listener_equal(const struct mlxsw_rx_listener *rxl_a, 2101 const struct mlxsw_rx_listener *rxl_b) 2102 { 2103 return (rxl_a->func == rxl_b->func && 2104 rxl_a->local_port == rxl_b->local_port && 2105 rxl_a->trap_id == rxl_b->trap_id && 2106 rxl_a->mirror_reason == rxl_b->mirror_reason); 2107 } 2108 2109 static struct mlxsw_rx_listener_item * 2110 __find_rx_listener_item(struct mlxsw_core *mlxsw_core, 2111 const struct mlxsw_rx_listener *rxl) 2112 { 2113 struct mlxsw_rx_listener_item *rxl_item; 2114 2115 list_for_each_entry(rxl_item, &mlxsw_core->rx_listener_list, list) { 2116 if (__is_rx_listener_equal(&rxl_item->rxl, rxl)) 2117 return rxl_item; 2118 } 2119 return NULL; 2120 } 2121 2122 int mlxsw_core_rx_listener_register(struct mlxsw_core *mlxsw_core, 2123 const struct mlxsw_rx_listener *rxl, 2124 void *priv, bool enabled) 2125 { 2126 struct mlxsw_rx_listener_item *rxl_item; 2127 2128 rxl_item = __find_rx_listener_item(mlxsw_core, rxl); 2129 if (rxl_item) 2130 return -EEXIST; 2131 rxl_item = kmalloc(sizeof(*rxl_item), GFP_KERNEL); 2132 if (!rxl_item) 2133 return -ENOMEM; 2134 rxl_item->rxl = *rxl; 2135 rxl_item->priv = priv; 2136 rxl_item->enabled = enabled; 2137 2138 list_add_rcu(&rxl_item->list, &mlxsw_core->rx_listener_list); 2139 return 0; 2140 } 2141 EXPORT_SYMBOL(mlxsw_core_rx_listener_register); 2142 2143 void mlxsw_core_rx_listener_unregister(struct mlxsw_core *mlxsw_core, 2144 const struct mlxsw_rx_listener *rxl) 2145 { 2146 struct mlxsw_rx_listener_item *rxl_item; 2147 2148 rxl_item = __find_rx_listener_item(mlxsw_core, rxl); 2149 if (!rxl_item) 2150 return; 2151 list_del_rcu(&rxl_item->list); 2152 synchronize_rcu(); 2153 kfree(rxl_item); 2154 } 2155 EXPORT_SYMBOL(mlxsw_core_rx_listener_unregister); 2156 2157 static void 2158 mlxsw_core_rx_listener_state_set(struct mlxsw_core *mlxsw_core, 2159 const struct mlxsw_rx_listener *rxl, 2160 bool enabled) 2161 { 2162 struct mlxsw_rx_listener_item *rxl_item; 2163 2164 rxl_item = __find_rx_listener_item(mlxsw_core, rxl); 2165 if (WARN_ON(!rxl_item)) 2166 return; 2167 rxl_item->enabled = enabled; 2168 } 2169 2170 static void mlxsw_core_event_listener_func(struct sk_buff *skb, u8 local_port, 2171 void *priv) 2172 { 2173 struct mlxsw_event_listener_item *event_listener_item = priv; 2174 struct mlxsw_reg_info reg; 2175 char *payload; 2176 char *reg_tlv; 2177 char *op_tlv; 2178 2179 mlxsw_emad_tlv_parse(skb); 2180 op_tlv = mlxsw_emad_op_tlv(skb); 2181 reg_tlv = mlxsw_emad_reg_tlv(skb); 2182 2183 reg.id = mlxsw_emad_op_tlv_register_id_get(op_tlv); 2184 reg.len = (mlxsw_emad_reg_tlv_len_get(reg_tlv) - 1) * sizeof(u32); 2185 payload = mlxsw_emad_reg_payload(reg_tlv); 2186 event_listener_item->el.func(®, payload, event_listener_item->priv); 2187 dev_kfree_skb(skb); 2188 } 2189 2190 static bool __is_event_listener_equal(const struct mlxsw_event_listener *el_a, 2191 const struct mlxsw_event_listener *el_b) 2192 { 2193 return (el_a->func == el_b->func && 2194 el_a->trap_id == el_b->trap_id); 2195 } 2196 2197 static struct mlxsw_event_listener_item * 2198 __find_event_listener_item(struct mlxsw_core *mlxsw_core, 2199 const struct mlxsw_event_listener *el) 2200 { 2201 struct mlxsw_event_listener_item *el_item; 2202 2203 list_for_each_entry(el_item, &mlxsw_core->event_listener_list, list) { 2204 if (__is_event_listener_equal(&el_item->el, el)) 2205 return el_item; 2206 } 2207 return NULL; 2208 } 2209 2210 int mlxsw_core_event_listener_register(struct mlxsw_core *mlxsw_core, 2211 const struct mlxsw_event_listener *el, 2212 void *priv) 2213 { 2214 int err; 2215 struct mlxsw_event_listener_item *el_item; 2216 const struct mlxsw_rx_listener rxl = { 2217 .func = mlxsw_core_event_listener_func, 2218 .local_port = MLXSW_PORT_DONT_CARE, 2219 .trap_id = el->trap_id, 2220 }; 2221 2222 el_item = __find_event_listener_item(mlxsw_core, el); 2223 if (el_item) 2224 return -EEXIST; 2225 el_item = kmalloc(sizeof(*el_item), GFP_KERNEL); 2226 if (!el_item) 2227 return -ENOMEM; 2228 el_item->el = *el; 2229 el_item->priv = priv; 2230 2231 err = mlxsw_core_rx_listener_register(mlxsw_core, &rxl, el_item, true); 2232 if (err) 2233 goto err_rx_listener_register; 2234 2235 /* No reason to save item if we did not manage to register an RX 2236 * listener for it. 2237 */ 2238 list_add_rcu(&el_item->list, &mlxsw_core->event_listener_list); 2239 2240 return 0; 2241 2242 err_rx_listener_register: 2243 kfree(el_item); 2244 return err; 2245 } 2246 EXPORT_SYMBOL(mlxsw_core_event_listener_register); 2247 2248 void mlxsw_core_event_listener_unregister(struct mlxsw_core *mlxsw_core, 2249 const struct mlxsw_event_listener *el) 2250 { 2251 struct mlxsw_event_listener_item *el_item; 2252 const struct mlxsw_rx_listener rxl = { 2253 .func = mlxsw_core_event_listener_func, 2254 .local_port = MLXSW_PORT_DONT_CARE, 2255 .trap_id = el->trap_id, 2256 }; 2257 2258 el_item = __find_event_listener_item(mlxsw_core, el); 2259 if (!el_item) 2260 return; 2261 mlxsw_core_rx_listener_unregister(mlxsw_core, &rxl); 2262 list_del(&el_item->list); 2263 kfree(el_item); 2264 } 2265 EXPORT_SYMBOL(mlxsw_core_event_listener_unregister); 2266 2267 static int mlxsw_core_listener_register(struct mlxsw_core *mlxsw_core, 2268 const struct mlxsw_listener *listener, 2269 void *priv, bool enabled) 2270 { 2271 if (listener->is_event) { 2272 WARN_ON(!enabled); 2273 return mlxsw_core_event_listener_register(mlxsw_core, 2274 &listener->event_listener, 2275 priv); 2276 } else { 2277 return mlxsw_core_rx_listener_register(mlxsw_core, 2278 &listener->rx_listener, 2279 priv, enabled); 2280 } 2281 } 2282 2283 static void mlxsw_core_listener_unregister(struct mlxsw_core *mlxsw_core, 2284 const struct mlxsw_listener *listener, 2285 void *priv) 2286 { 2287 if (listener->is_event) 2288 mlxsw_core_event_listener_unregister(mlxsw_core, 2289 &listener->event_listener); 2290 else 2291 mlxsw_core_rx_listener_unregister(mlxsw_core, 2292 &listener->rx_listener); 2293 } 2294 2295 int mlxsw_core_trap_register(struct mlxsw_core *mlxsw_core, 2296 const struct mlxsw_listener *listener, void *priv) 2297 { 2298 enum mlxsw_reg_htgt_trap_group trap_group; 2299 enum mlxsw_reg_hpkt_action action; 2300 char hpkt_pl[MLXSW_REG_HPKT_LEN]; 2301 int err; 2302 2303 err = mlxsw_core_listener_register(mlxsw_core, listener, priv, 2304 listener->enabled_on_register); 2305 if (err) 2306 return err; 2307 2308 action = listener->enabled_on_register ? listener->en_action : 2309 listener->dis_action; 2310 trap_group = listener->enabled_on_register ? listener->en_trap_group : 2311 listener->dis_trap_group; 2312 mlxsw_reg_hpkt_pack(hpkt_pl, action, listener->trap_id, 2313 trap_group, listener->is_ctrl); 2314 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(hpkt), hpkt_pl); 2315 if (err) 2316 goto err_trap_set; 2317 2318 return 0; 2319 2320 err_trap_set: 2321 mlxsw_core_listener_unregister(mlxsw_core, listener, priv); 2322 return err; 2323 } 2324 EXPORT_SYMBOL(mlxsw_core_trap_register); 2325 2326 void mlxsw_core_trap_unregister(struct mlxsw_core *mlxsw_core, 2327 const struct mlxsw_listener *listener, 2328 void *priv) 2329 { 2330 char hpkt_pl[MLXSW_REG_HPKT_LEN]; 2331 2332 if (!listener->is_event) { 2333 mlxsw_reg_hpkt_pack(hpkt_pl, listener->dis_action, 2334 listener->trap_id, listener->dis_trap_group, 2335 listener->is_ctrl); 2336 mlxsw_reg_write(mlxsw_core, MLXSW_REG(hpkt), hpkt_pl); 2337 } 2338 2339 mlxsw_core_listener_unregister(mlxsw_core, listener, priv); 2340 } 2341 EXPORT_SYMBOL(mlxsw_core_trap_unregister); 2342 2343 int mlxsw_core_trap_state_set(struct mlxsw_core *mlxsw_core, 2344 const struct mlxsw_listener *listener, 2345 bool enabled) 2346 { 2347 enum mlxsw_reg_htgt_trap_group trap_group; 2348 enum mlxsw_reg_hpkt_action action; 2349 char hpkt_pl[MLXSW_REG_HPKT_LEN]; 2350 int err; 2351 2352 /* Not supported for event listener */ 2353 if (WARN_ON(listener->is_event)) 2354 return -EINVAL; 2355 2356 action = enabled ? listener->en_action : listener->dis_action; 2357 trap_group = enabled ? listener->en_trap_group : 2358 listener->dis_trap_group; 2359 mlxsw_reg_hpkt_pack(hpkt_pl, action, listener->trap_id, 2360 trap_group, listener->is_ctrl); 2361 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(hpkt), hpkt_pl); 2362 if (err) 2363 return err; 2364 2365 mlxsw_core_rx_listener_state_set(mlxsw_core, &listener->rx_listener, 2366 enabled); 2367 return 0; 2368 } 2369 EXPORT_SYMBOL(mlxsw_core_trap_state_set); 2370 2371 static u64 mlxsw_core_tid_get(struct mlxsw_core *mlxsw_core) 2372 { 2373 return atomic64_inc_return(&mlxsw_core->emad.tid); 2374 } 2375 2376 static int mlxsw_core_reg_access_emad(struct mlxsw_core *mlxsw_core, 2377 const struct mlxsw_reg_info *reg, 2378 char *payload, 2379 enum mlxsw_core_reg_access_type type, 2380 struct list_head *bulk_list, 2381 mlxsw_reg_trans_cb_t *cb, 2382 unsigned long cb_priv) 2383 { 2384 u64 tid = mlxsw_core_tid_get(mlxsw_core); 2385 struct mlxsw_reg_trans *trans; 2386 int err; 2387 2388 trans = kzalloc(sizeof(*trans), GFP_KERNEL); 2389 if (!trans) 2390 return -ENOMEM; 2391 2392 err = mlxsw_emad_reg_access(mlxsw_core, reg, payload, type, trans, 2393 bulk_list, cb, cb_priv, tid); 2394 if (err) { 2395 kfree_rcu(trans, rcu); 2396 return err; 2397 } 2398 return 0; 2399 } 2400 2401 int mlxsw_reg_trans_query(struct mlxsw_core *mlxsw_core, 2402 const struct mlxsw_reg_info *reg, char *payload, 2403 struct list_head *bulk_list, 2404 mlxsw_reg_trans_cb_t *cb, unsigned long cb_priv) 2405 { 2406 return mlxsw_core_reg_access_emad(mlxsw_core, reg, payload, 2407 MLXSW_CORE_REG_ACCESS_TYPE_QUERY, 2408 bulk_list, cb, cb_priv); 2409 } 2410 EXPORT_SYMBOL(mlxsw_reg_trans_query); 2411 2412 int mlxsw_reg_trans_write(struct mlxsw_core *mlxsw_core, 2413 const struct mlxsw_reg_info *reg, char *payload, 2414 struct list_head *bulk_list, 2415 mlxsw_reg_trans_cb_t *cb, unsigned long cb_priv) 2416 { 2417 return mlxsw_core_reg_access_emad(mlxsw_core, reg, payload, 2418 MLXSW_CORE_REG_ACCESS_TYPE_WRITE, 2419 bulk_list, cb, cb_priv); 2420 } 2421 EXPORT_SYMBOL(mlxsw_reg_trans_write); 2422 2423 #define MLXSW_REG_TRANS_ERR_STRING_SIZE 256 2424 2425 static int mlxsw_reg_trans_wait(struct mlxsw_reg_trans *trans) 2426 { 2427 char err_string[MLXSW_REG_TRANS_ERR_STRING_SIZE]; 2428 struct mlxsw_core *mlxsw_core = trans->core; 2429 int err; 2430 2431 wait_for_completion(&trans->completion); 2432 cancel_delayed_work_sync(&trans->timeout_dw); 2433 err = trans->err; 2434 2435 if (trans->retries) 2436 dev_warn(mlxsw_core->bus_info->dev, "EMAD retries (%d/%d) (tid=%llx)\n", 2437 trans->retries, MLXSW_EMAD_MAX_RETRY, trans->tid); 2438 if (err) { 2439 dev_err(mlxsw_core->bus_info->dev, "EMAD reg access failed (tid=%llx,reg_id=%x(%s),type=%s,status=%x(%s))\n", 2440 trans->tid, trans->reg->id, 2441 mlxsw_reg_id_str(trans->reg->id), 2442 mlxsw_core_reg_access_type_str(trans->type), 2443 trans->emad_status, 2444 mlxsw_emad_op_tlv_status_str(trans->emad_status)); 2445 2446 snprintf(err_string, MLXSW_REG_TRANS_ERR_STRING_SIZE, 2447 "(tid=%llx,reg_id=%x(%s)) %s (%s)\n", trans->tid, 2448 trans->reg->id, mlxsw_reg_id_str(trans->reg->id), 2449 mlxsw_emad_op_tlv_status_str(trans->emad_status), 2450 trans->emad_err_string ? trans->emad_err_string : ""); 2451 2452 trace_devlink_hwerr(priv_to_devlink(mlxsw_core), 2453 trans->emad_status, err_string); 2454 2455 kfree(trans->emad_err_string); 2456 } 2457 2458 list_del(&trans->bulk_list); 2459 kfree_rcu(trans, rcu); 2460 return err; 2461 } 2462 2463 int mlxsw_reg_trans_bulk_wait(struct list_head *bulk_list) 2464 { 2465 struct mlxsw_reg_trans *trans; 2466 struct mlxsw_reg_trans *tmp; 2467 int sum_err = 0; 2468 int err; 2469 2470 list_for_each_entry_safe(trans, tmp, bulk_list, bulk_list) { 2471 err = mlxsw_reg_trans_wait(trans); 2472 if (err && sum_err == 0) 2473 sum_err = err; /* first error to be returned */ 2474 } 2475 return sum_err; 2476 } 2477 EXPORT_SYMBOL(mlxsw_reg_trans_bulk_wait); 2478 2479 static int mlxsw_core_reg_access_cmd(struct mlxsw_core *mlxsw_core, 2480 const struct mlxsw_reg_info *reg, 2481 char *payload, 2482 enum mlxsw_core_reg_access_type type) 2483 { 2484 enum mlxsw_emad_op_tlv_status status; 2485 int err, n_retry; 2486 bool reset_ok; 2487 char *in_mbox, *out_mbox, *tmp; 2488 2489 dev_dbg(mlxsw_core->bus_info->dev, "Reg cmd access (reg_id=%x(%s),type=%s)\n", 2490 reg->id, mlxsw_reg_id_str(reg->id), 2491 mlxsw_core_reg_access_type_str(type)); 2492 2493 in_mbox = mlxsw_cmd_mbox_alloc(); 2494 if (!in_mbox) 2495 return -ENOMEM; 2496 2497 out_mbox = mlxsw_cmd_mbox_alloc(); 2498 if (!out_mbox) { 2499 err = -ENOMEM; 2500 goto free_in_mbox; 2501 } 2502 2503 mlxsw_emad_pack_op_tlv(in_mbox, reg, type, 2504 mlxsw_core_tid_get(mlxsw_core)); 2505 tmp = in_mbox + MLXSW_EMAD_OP_TLV_LEN * sizeof(u32); 2506 mlxsw_emad_pack_reg_tlv(tmp, reg, payload); 2507 2508 /* There is a special treatment needed for MRSR (reset) register. 2509 * The command interface will return error after the command 2510 * is executed, so tell the lower layer to expect it 2511 * and cope accordingly. 2512 */ 2513 reset_ok = reg->id == MLXSW_REG_MRSR_ID; 2514 2515 n_retry = 0; 2516 retry: 2517 err = mlxsw_cmd_access_reg(mlxsw_core, reset_ok, in_mbox, out_mbox); 2518 if (!err) { 2519 err = mlxsw_emad_process_status(out_mbox, &status); 2520 if (err) { 2521 if (err == -EAGAIN && n_retry++ < MLXSW_EMAD_MAX_RETRY) 2522 goto retry; 2523 dev_err(mlxsw_core->bus_info->dev, "Reg cmd access status failed (status=%x(%s))\n", 2524 status, mlxsw_emad_op_tlv_status_str(status)); 2525 } 2526 } 2527 2528 if (!err) 2529 memcpy(payload, mlxsw_emad_reg_payload_cmd(out_mbox), 2530 reg->len); 2531 2532 mlxsw_cmd_mbox_free(out_mbox); 2533 free_in_mbox: 2534 mlxsw_cmd_mbox_free(in_mbox); 2535 if (err) 2536 dev_err(mlxsw_core->bus_info->dev, "Reg cmd access failed (reg_id=%x(%s),type=%s)\n", 2537 reg->id, mlxsw_reg_id_str(reg->id), 2538 mlxsw_core_reg_access_type_str(type)); 2539 return err; 2540 } 2541 2542 static void mlxsw_core_reg_access_cb(struct mlxsw_core *mlxsw_core, 2543 char *payload, size_t payload_len, 2544 unsigned long cb_priv) 2545 { 2546 char *orig_payload = (char *) cb_priv; 2547 2548 memcpy(orig_payload, payload, payload_len); 2549 } 2550 2551 static int mlxsw_core_reg_access(struct mlxsw_core *mlxsw_core, 2552 const struct mlxsw_reg_info *reg, 2553 char *payload, 2554 enum mlxsw_core_reg_access_type type) 2555 { 2556 LIST_HEAD(bulk_list); 2557 int err; 2558 2559 /* During initialization EMAD interface is not available to us, 2560 * so we default to command interface. We switch to EMAD interface 2561 * after setting the appropriate traps. 2562 */ 2563 if (!mlxsw_core->emad.use_emad) 2564 return mlxsw_core_reg_access_cmd(mlxsw_core, reg, 2565 payload, type); 2566 2567 err = mlxsw_core_reg_access_emad(mlxsw_core, reg, 2568 payload, type, &bulk_list, 2569 mlxsw_core_reg_access_cb, 2570 (unsigned long) payload); 2571 if (err) 2572 return err; 2573 return mlxsw_reg_trans_bulk_wait(&bulk_list); 2574 } 2575 2576 int mlxsw_reg_query(struct mlxsw_core *mlxsw_core, 2577 const struct mlxsw_reg_info *reg, char *payload) 2578 { 2579 return mlxsw_core_reg_access(mlxsw_core, reg, payload, 2580 MLXSW_CORE_REG_ACCESS_TYPE_QUERY); 2581 } 2582 EXPORT_SYMBOL(mlxsw_reg_query); 2583 2584 int mlxsw_reg_write(struct mlxsw_core *mlxsw_core, 2585 const struct mlxsw_reg_info *reg, char *payload) 2586 { 2587 return mlxsw_core_reg_access(mlxsw_core, reg, payload, 2588 MLXSW_CORE_REG_ACCESS_TYPE_WRITE); 2589 } 2590 EXPORT_SYMBOL(mlxsw_reg_write); 2591 2592 void mlxsw_core_skb_receive(struct mlxsw_core *mlxsw_core, struct sk_buff *skb, 2593 struct mlxsw_rx_info *rx_info) 2594 { 2595 struct mlxsw_rx_listener_item *rxl_item; 2596 const struct mlxsw_rx_listener *rxl; 2597 u8 local_port; 2598 bool found = false; 2599 2600 if (rx_info->is_lag) { 2601 dev_dbg_ratelimited(mlxsw_core->bus_info->dev, "%s: lag_id = %d, lag_port_index = 0x%x\n", 2602 __func__, rx_info->u.lag_id, 2603 rx_info->trap_id); 2604 /* Upper layer does not care if the skb came from LAG or not, 2605 * so just get the local_port for the lag port and push it up. 2606 */ 2607 local_port = mlxsw_core_lag_mapping_get(mlxsw_core, 2608 rx_info->u.lag_id, 2609 rx_info->lag_port_index); 2610 } else { 2611 local_port = rx_info->u.sys_port; 2612 } 2613 2614 dev_dbg_ratelimited(mlxsw_core->bus_info->dev, "%s: local_port = %d, trap_id = 0x%x\n", 2615 __func__, local_port, rx_info->trap_id); 2616 2617 if ((rx_info->trap_id >= MLXSW_TRAP_ID_MAX) || 2618 (local_port >= mlxsw_core->max_ports)) 2619 goto drop; 2620 2621 rcu_read_lock(); 2622 list_for_each_entry_rcu(rxl_item, &mlxsw_core->rx_listener_list, list) { 2623 rxl = &rxl_item->rxl; 2624 if ((rxl->local_port == MLXSW_PORT_DONT_CARE || 2625 rxl->local_port == local_port) && 2626 rxl->trap_id == rx_info->trap_id && 2627 rxl->mirror_reason == rx_info->mirror_reason) { 2628 if (rxl_item->enabled) 2629 found = true; 2630 break; 2631 } 2632 } 2633 if (!found) { 2634 rcu_read_unlock(); 2635 goto drop; 2636 } 2637 2638 rxl->func(skb, local_port, rxl_item->priv); 2639 rcu_read_unlock(); 2640 return; 2641 2642 drop: 2643 dev_kfree_skb(skb); 2644 } 2645 EXPORT_SYMBOL(mlxsw_core_skb_receive); 2646 2647 static int mlxsw_core_lag_mapping_index(struct mlxsw_core *mlxsw_core, 2648 u16 lag_id, u8 port_index) 2649 { 2650 return MLXSW_CORE_RES_GET(mlxsw_core, MAX_LAG_MEMBERS) * lag_id + 2651 port_index; 2652 } 2653 2654 void mlxsw_core_lag_mapping_set(struct mlxsw_core *mlxsw_core, 2655 u16 lag_id, u8 port_index, u8 local_port) 2656 { 2657 int index = mlxsw_core_lag_mapping_index(mlxsw_core, 2658 lag_id, port_index); 2659 2660 mlxsw_core->lag.mapping[index] = local_port; 2661 } 2662 EXPORT_SYMBOL(mlxsw_core_lag_mapping_set); 2663 2664 u8 mlxsw_core_lag_mapping_get(struct mlxsw_core *mlxsw_core, 2665 u16 lag_id, u8 port_index) 2666 { 2667 int index = mlxsw_core_lag_mapping_index(mlxsw_core, 2668 lag_id, port_index); 2669 2670 return mlxsw_core->lag.mapping[index]; 2671 } 2672 EXPORT_SYMBOL(mlxsw_core_lag_mapping_get); 2673 2674 void mlxsw_core_lag_mapping_clear(struct mlxsw_core *mlxsw_core, 2675 u16 lag_id, u8 local_port) 2676 { 2677 int i; 2678 2679 for (i = 0; i < MLXSW_CORE_RES_GET(mlxsw_core, MAX_LAG_MEMBERS); i++) { 2680 int index = mlxsw_core_lag_mapping_index(mlxsw_core, 2681 lag_id, i); 2682 2683 if (mlxsw_core->lag.mapping[index] == local_port) 2684 mlxsw_core->lag.mapping[index] = 0; 2685 } 2686 } 2687 EXPORT_SYMBOL(mlxsw_core_lag_mapping_clear); 2688 2689 bool mlxsw_core_res_valid(struct mlxsw_core *mlxsw_core, 2690 enum mlxsw_res_id res_id) 2691 { 2692 return mlxsw_res_valid(&mlxsw_core->res, res_id); 2693 } 2694 EXPORT_SYMBOL(mlxsw_core_res_valid); 2695 2696 u64 mlxsw_core_res_get(struct mlxsw_core *mlxsw_core, 2697 enum mlxsw_res_id res_id) 2698 { 2699 return mlxsw_res_get(&mlxsw_core->res, res_id); 2700 } 2701 EXPORT_SYMBOL(mlxsw_core_res_get); 2702 2703 static int __mlxsw_core_port_init(struct mlxsw_core *mlxsw_core, u8 local_port, 2704 enum devlink_port_flavour flavour, 2705 u32 port_number, bool split, 2706 u32 split_port_subnumber, 2707 bool splittable, u32 lanes, 2708 const unsigned char *switch_id, 2709 unsigned char switch_id_len) 2710 { 2711 struct devlink *devlink = priv_to_devlink(mlxsw_core); 2712 struct mlxsw_core_port *mlxsw_core_port = 2713 &mlxsw_core->ports[local_port]; 2714 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 2715 struct devlink_port_attrs attrs = {}; 2716 int err; 2717 2718 attrs.split = split; 2719 attrs.lanes = lanes; 2720 attrs.splittable = splittable; 2721 attrs.flavour = flavour; 2722 attrs.phys.port_number = port_number; 2723 attrs.phys.split_subport_number = split_port_subnumber; 2724 memcpy(attrs.switch_id.id, switch_id, switch_id_len); 2725 attrs.switch_id.id_len = switch_id_len; 2726 mlxsw_core_port->local_port = local_port; 2727 devlink_port_attrs_set(devlink_port, &attrs); 2728 err = devlink_port_register(devlink, devlink_port, local_port); 2729 if (err) 2730 memset(mlxsw_core_port, 0, sizeof(*mlxsw_core_port)); 2731 return err; 2732 } 2733 2734 static void __mlxsw_core_port_fini(struct mlxsw_core *mlxsw_core, u8 local_port) 2735 { 2736 struct mlxsw_core_port *mlxsw_core_port = 2737 &mlxsw_core->ports[local_port]; 2738 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 2739 2740 devlink_port_unregister(devlink_port); 2741 memset(mlxsw_core_port, 0, sizeof(*mlxsw_core_port)); 2742 } 2743 2744 int mlxsw_core_port_init(struct mlxsw_core *mlxsw_core, u8 local_port, 2745 u32 port_number, bool split, 2746 u32 split_port_subnumber, 2747 bool splittable, u32 lanes, 2748 const unsigned char *switch_id, 2749 unsigned char switch_id_len) 2750 { 2751 return __mlxsw_core_port_init(mlxsw_core, local_port, 2752 DEVLINK_PORT_FLAVOUR_PHYSICAL, 2753 port_number, split, split_port_subnumber, 2754 splittable, lanes, 2755 switch_id, switch_id_len); 2756 } 2757 EXPORT_SYMBOL(mlxsw_core_port_init); 2758 2759 void mlxsw_core_port_fini(struct mlxsw_core *mlxsw_core, u8 local_port) 2760 { 2761 __mlxsw_core_port_fini(mlxsw_core, local_port); 2762 } 2763 EXPORT_SYMBOL(mlxsw_core_port_fini); 2764 2765 int mlxsw_core_cpu_port_init(struct mlxsw_core *mlxsw_core, 2766 void *port_driver_priv, 2767 const unsigned char *switch_id, 2768 unsigned char switch_id_len) 2769 { 2770 struct mlxsw_core_port *mlxsw_core_port = 2771 &mlxsw_core->ports[MLXSW_PORT_CPU_PORT]; 2772 int err; 2773 2774 err = __mlxsw_core_port_init(mlxsw_core, MLXSW_PORT_CPU_PORT, 2775 DEVLINK_PORT_FLAVOUR_CPU, 2776 0, false, 0, false, 0, 2777 switch_id, switch_id_len); 2778 if (err) 2779 return err; 2780 2781 mlxsw_core_port->port_driver_priv = port_driver_priv; 2782 return 0; 2783 } 2784 EXPORT_SYMBOL(mlxsw_core_cpu_port_init); 2785 2786 void mlxsw_core_cpu_port_fini(struct mlxsw_core *mlxsw_core) 2787 { 2788 __mlxsw_core_port_fini(mlxsw_core, MLXSW_PORT_CPU_PORT); 2789 } 2790 EXPORT_SYMBOL(mlxsw_core_cpu_port_fini); 2791 2792 void mlxsw_core_port_eth_set(struct mlxsw_core *mlxsw_core, u8 local_port, 2793 void *port_driver_priv, struct net_device *dev) 2794 { 2795 struct mlxsw_core_port *mlxsw_core_port = 2796 &mlxsw_core->ports[local_port]; 2797 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 2798 2799 mlxsw_core_port->port_driver_priv = port_driver_priv; 2800 devlink_port_type_eth_set(devlink_port, dev); 2801 } 2802 EXPORT_SYMBOL(mlxsw_core_port_eth_set); 2803 2804 void mlxsw_core_port_ib_set(struct mlxsw_core *mlxsw_core, u8 local_port, 2805 void *port_driver_priv) 2806 { 2807 struct mlxsw_core_port *mlxsw_core_port = 2808 &mlxsw_core->ports[local_port]; 2809 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 2810 2811 mlxsw_core_port->port_driver_priv = port_driver_priv; 2812 devlink_port_type_ib_set(devlink_port, NULL); 2813 } 2814 EXPORT_SYMBOL(mlxsw_core_port_ib_set); 2815 2816 void mlxsw_core_port_clear(struct mlxsw_core *mlxsw_core, u8 local_port, 2817 void *port_driver_priv) 2818 { 2819 struct mlxsw_core_port *mlxsw_core_port = 2820 &mlxsw_core->ports[local_port]; 2821 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 2822 2823 mlxsw_core_port->port_driver_priv = port_driver_priv; 2824 devlink_port_type_clear(devlink_port); 2825 } 2826 EXPORT_SYMBOL(mlxsw_core_port_clear); 2827 2828 enum devlink_port_type mlxsw_core_port_type_get(struct mlxsw_core *mlxsw_core, 2829 u8 local_port) 2830 { 2831 struct mlxsw_core_port *mlxsw_core_port = 2832 &mlxsw_core->ports[local_port]; 2833 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 2834 2835 return devlink_port->type; 2836 } 2837 EXPORT_SYMBOL(mlxsw_core_port_type_get); 2838 2839 2840 struct devlink_port * 2841 mlxsw_core_port_devlink_port_get(struct mlxsw_core *mlxsw_core, 2842 u8 local_port) 2843 { 2844 struct mlxsw_core_port *mlxsw_core_port = 2845 &mlxsw_core->ports[local_port]; 2846 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 2847 2848 return devlink_port; 2849 } 2850 EXPORT_SYMBOL(mlxsw_core_port_devlink_port_get); 2851 2852 struct mlxsw_env *mlxsw_core_env(const struct mlxsw_core *mlxsw_core) 2853 { 2854 return mlxsw_core->env; 2855 } 2856 2857 bool mlxsw_core_is_initialized(const struct mlxsw_core *mlxsw_core) 2858 { 2859 return mlxsw_core->is_initialized; 2860 } 2861 2862 int mlxsw_core_module_max_width(struct mlxsw_core *mlxsw_core, u8 module) 2863 { 2864 enum mlxsw_reg_pmtm_module_type module_type; 2865 char pmtm_pl[MLXSW_REG_PMTM_LEN]; 2866 int err; 2867 2868 mlxsw_reg_pmtm_pack(pmtm_pl, module); 2869 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(pmtm), pmtm_pl); 2870 if (err) 2871 return err; 2872 mlxsw_reg_pmtm_unpack(pmtm_pl, &module_type); 2873 2874 /* Here we need to get the module width according to the module type. */ 2875 2876 switch (module_type) { 2877 case MLXSW_REG_PMTM_MODULE_TYPE_C2C8X: 2878 case MLXSW_REG_PMTM_MODULE_TYPE_QSFP_DD: 2879 case MLXSW_REG_PMTM_MODULE_TYPE_OSFP: 2880 return 8; 2881 case MLXSW_REG_PMTM_MODULE_TYPE_C2C4X: 2882 case MLXSW_REG_PMTM_MODULE_TYPE_BP_4X: 2883 case MLXSW_REG_PMTM_MODULE_TYPE_QSFP: 2884 return 4; 2885 case MLXSW_REG_PMTM_MODULE_TYPE_C2C2X: 2886 case MLXSW_REG_PMTM_MODULE_TYPE_BP_2X: 2887 case MLXSW_REG_PMTM_MODULE_TYPE_SFP_DD: 2888 case MLXSW_REG_PMTM_MODULE_TYPE_DSFP: 2889 return 2; 2890 case MLXSW_REG_PMTM_MODULE_TYPE_C2C1X: 2891 case MLXSW_REG_PMTM_MODULE_TYPE_BP_1X: 2892 case MLXSW_REG_PMTM_MODULE_TYPE_SFP: 2893 return 1; 2894 default: 2895 return -EINVAL; 2896 } 2897 } 2898 EXPORT_SYMBOL(mlxsw_core_module_max_width); 2899 2900 static void mlxsw_core_buf_dump_dbg(struct mlxsw_core *mlxsw_core, 2901 const char *buf, size_t size) 2902 { 2903 __be32 *m = (__be32 *) buf; 2904 int i; 2905 int count = size / sizeof(__be32); 2906 2907 for (i = count - 1; i >= 0; i--) 2908 if (m[i]) 2909 break; 2910 i++; 2911 count = i ? i : 1; 2912 for (i = 0; i < count; i += 4) 2913 dev_dbg(mlxsw_core->bus_info->dev, "%04x - %08x %08x %08x %08x\n", 2914 i * 4, be32_to_cpu(m[i]), be32_to_cpu(m[i + 1]), 2915 be32_to_cpu(m[i + 2]), be32_to_cpu(m[i + 3])); 2916 } 2917 2918 int mlxsw_cmd_exec(struct mlxsw_core *mlxsw_core, u16 opcode, u8 opcode_mod, 2919 u32 in_mod, bool out_mbox_direct, bool reset_ok, 2920 char *in_mbox, size_t in_mbox_size, 2921 char *out_mbox, size_t out_mbox_size) 2922 { 2923 u8 status; 2924 int err; 2925 2926 BUG_ON(in_mbox_size % sizeof(u32) || out_mbox_size % sizeof(u32)); 2927 if (!mlxsw_core->bus->cmd_exec) 2928 return -EOPNOTSUPP; 2929 2930 dev_dbg(mlxsw_core->bus_info->dev, "Cmd exec (opcode=%x(%s),opcode_mod=%x,in_mod=%x)\n", 2931 opcode, mlxsw_cmd_opcode_str(opcode), opcode_mod, in_mod); 2932 if (in_mbox) { 2933 dev_dbg(mlxsw_core->bus_info->dev, "Input mailbox:\n"); 2934 mlxsw_core_buf_dump_dbg(mlxsw_core, in_mbox, in_mbox_size); 2935 } 2936 2937 err = mlxsw_core->bus->cmd_exec(mlxsw_core->bus_priv, opcode, 2938 opcode_mod, in_mod, out_mbox_direct, 2939 in_mbox, in_mbox_size, 2940 out_mbox, out_mbox_size, &status); 2941 2942 if (!err && out_mbox) { 2943 dev_dbg(mlxsw_core->bus_info->dev, "Output mailbox:\n"); 2944 mlxsw_core_buf_dump_dbg(mlxsw_core, out_mbox, out_mbox_size); 2945 } 2946 2947 if (reset_ok && err == -EIO && 2948 status == MLXSW_CMD_STATUS_RUNNING_RESET) { 2949 err = 0; 2950 } else if (err == -EIO && status != MLXSW_CMD_STATUS_OK) { 2951 dev_err(mlxsw_core->bus_info->dev, "Cmd exec failed (opcode=%x(%s),opcode_mod=%x,in_mod=%x,status=%x(%s))\n", 2952 opcode, mlxsw_cmd_opcode_str(opcode), opcode_mod, 2953 in_mod, status, mlxsw_cmd_status_str(status)); 2954 } else if (err == -ETIMEDOUT) { 2955 dev_err(mlxsw_core->bus_info->dev, "Cmd exec timed-out (opcode=%x(%s),opcode_mod=%x,in_mod=%x)\n", 2956 opcode, mlxsw_cmd_opcode_str(opcode), opcode_mod, 2957 in_mod); 2958 } 2959 2960 return err; 2961 } 2962 EXPORT_SYMBOL(mlxsw_cmd_exec); 2963 2964 int mlxsw_core_schedule_dw(struct delayed_work *dwork, unsigned long delay) 2965 { 2966 return queue_delayed_work(mlxsw_wq, dwork, delay); 2967 } 2968 EXPORT_SYMBOL(mlxsw_core_schedule_dw); 2969 2970 bool mlxsw_core_schedule_work(struct work_struct *work) 2971 { 2972 return queue_work(mlxsw_owq, work); 2973 } 2974 EXPORT_SYMBOL(mlxsw_core_schedule_work); 2975 2976 void mlxsw_core_flush_owq(void) 2977 { 2978 flush_workqueue(mlxsw_owq); 2979 } 2980 EXPORT_SYMBOL(mlxsw_core_flush_owq); 2981 2982 int mlxsw_core_kvd_sizes_get(struct mlxsw_core *mlxsw_core, 2983 const struct mlxsw_config_profile *profile, 2984 u64 *p_single_size, u64 *p_double_size, 2985 u64 *p_linear_size) 2986 { 2987 struct mlxsw_driver *driver = mlxsw_core->driver; 2988 2989 if (!driver->kvd_sizes_get) 2990 return -EINVAL; 2991 2992 return driver->kvd_sizes_get(mlxsw_core, profile, 2993 p_single_size, p_double_size, 2994 p_linear_size); 2995 } 2996 EXPORT_SYMBOL(mlxsw_core_kvd_sizes_get); 2997 2998 int mlxsw_core_resources_query(struct mlxsw_core *mlxsw_core, char *mbox, 2999 struct mlxsw_res *res) 3000 { 3001 int index, i; 3002 u64 data; 3003 u16 id; 3004 int err; 3005 3006 if (!res) 3007 return 0; 3008 3009 mlxsw_cmd_mbox_zero(mbox); 3010 3011 for (index = 0; index < MLXSW_CMD_QUERY_RESOURCES_MAX_QUERIES; 3012 index++) { 3013 err = mlxsw_cmd_query_resources(mlxsw_core, mbox, index); 3014 if (err) 3015 return err; 3016 3017 for (i = 0; i < MLXSW_CMD_QUERY_RESOURCES_PER_QUERY; i++) { 3018 id = mlxsw_cmd_mbox_query_resource_id_get(mbox, i); 3019 data = mlxsw_cmd_mbox_query_resource_data_get(mbox, i); 3020 3021 if (id == MLXSW_CMD_QUERY_RESOURCES_TABLE_END_ID) 3022 return 0; 3023 3024 mlxsw_res_parse(res, id, data); 3025 } 3026 } 3027 3028 /* If after MLXSW_RESOURCES_QUERY_MAX_QUERIES we still didn't get 3029 * MLXSW_RESOURCES_TABLE_END_ID, something went bad in the FW. 3030 */ 3031 return -EIO; 3032 } 3033 EXPORT_SYMBOL(mlxsw_core_resources_query); 3034 3035 u32 mlxsw_core_read_frc_h(struct mlxsw_core *mlxsw_core) 3036 { 3037 return mlxsw_core->bus->read_frc_h(mlxsw_core->bus_priv); 3038 } 3039 EXPORT_SYMBOL(mlxsw_core_read_frc_h); 3040 3041 u32 mlxsw_core_read_frc_l(struct mlxsw_core *mlxsw_core) 3042 { 3043 return mlxsw_core->bus->read_frc_l(mlxsw_core->bus_priv); 3044 } 3045 EXPORT_SYMBOL(mlxsw_core_read_frc_l); 3046 3047 void mlxsw_core_emad_string_tlv_enable(struct mlxsw_core *mlxsw_core) 3048 { 3049 mlxsw_core->emad.enable_string_tlv = true; 3050 } 3051 EXPORT_SYMBOL(mlxsw_core_emad_string_tlv_enable); 3052 3053 static int __init mlxsw_core_module_init(void) 3054 { 3055 int err; 3056 3057 mlxsw_wq = alloc_workqueue(mlxsw_core_driver_name, 0, 0); 3058 if (!mlxsw_wq) 3059 return -ENOMEM; 3060 mlxsw_owq = alloc_ordered_workqueue("%s_ordered", 0, 3061 mlxsw_core_driver_name); 3062 if (!mlxsw_owq) { 3063 err = -ENOMEM; 3064 goto err_alloc_ordered_workqueue; 3065 } 3066 return 0; 3067 3068 err_alloc_ordered_workqueue: 3069 destroy_workqueue(mlxsw_wq); 3070 return err; 3071 } 3072 3073 static void __exit mlxsw_core_module_exit(void) 3074 { 3075 destroy_workqueue(mlxsw_owq); 3076 destroy_workqueue(mlxsw_wq); 3077 } 3078 3079 module_init(mlxsw_core_module_init); 3080 module_exit(mlxsw_core_module_exit); 3081 3082 MODULE_LICENSE("Dual BSD/GPL"); 3083 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>"); 3084 MODULE_DESCRIPTION("Mellanox switch device core driver"); 3085