1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/device.h> 7 #include <linux/export.h> 8 #include <linux/err.h> 9 #include <linux/if_link.h> 10 #include <linux/netdevice.h> 11 #include <linux/completion.h> 12 #include <linux/skbuff.h> 13 #include <linux/etherdevice.h> 14 #include <linux/types.h> 15 #include <linux/string.h> 16 #include <linux/gfp.h> 17 #include <linux/random.h> 18 #include <linux/jiffies.h> 19 #include <linux/mutex.h> 20 #include <linux/rcupdate.h> 21 #include <linux/slab.h> 22 #include <linux/workqueue.h> 23 #include <linux/firmware.h> 24 #include <asm/byteorder.h> 25 #include <net/devlink.h> 26 #include <trace/events/devlink.h> 27 28 #include "core.h" 29 #include "core_env.h" 30 #include "item.h" 31 #include "cmd.h" 32 #include "port.h" 33 #include "trap.h" 34 #include "emad.h" 35 #include "reg.h" 36 #include "resources.h" 37 #include "../mlxfw/mlxfw.h" 38 39 static LIST_HEAD(mlxsw_core_driver_list); 40 static DEFINE_SPINLOCK(mlxsw_core_driver_list_lock); 41 42 static const char mlxsw_core_driver_name[] = "mlxsw_core"; 43 44 static struct workqueue_struct *mlxsw_wq; 45 static struct workqueue_struct *mlxsw_owq; 46 47 struct mlxsw_core_port { 48 struct devlink_port devlink_port; 49 void *port_driver_priv; 50 u16 local_port; 51 struct mlxsw_linecard *linecard; 52 }; 53 54 void *mlxsw_core_port_driver_priv(struct mlxsw_core_port *mlxsw_core_port) 55 { 56 return mlxsw_core_port->port_driver_priv; 57 } 58 EXPORT_SYMBOL(mlxsw_core_port_driver_priv); 59 60 static bool mlxsw_core_port_check(struct mlxsw_core_port *mlxsw_core_port) 61 { 62 return mlxsw_core_port->port_driver_priv != NULL; 63 } 64 65 struct mlxsw_core { 66 struct mlxsw_driver *driver; 67 const struct mlxsw_bus *bus; 68 void *bus_priv; 69 const struct mlxsw_bus_info *bus_info; 70 struct workqueue_struct *emad_wq; 71 struct list_head rx_listener_list; 72 struct list_head event_listener_list; 73 struct list_head irq_event_handler_list; 74 struct mutex irq_event_handler_lock; /* Locks access to handlers list */ 75 struct { 76 atomic64_t tid; 77 struct list_head trans_list; 78 spinlock_t trans_list_lock; /* protects trans_list writes */ 79 bool use_emad; 80 bool enable_string_tlv; 81 bool enable_latency_tlv; 82 } emad; 83 struct { 84 u16 *mapping; /* lag_id+port_index to local_port mapping */ 85 } lag; 86 struct mlxsw_res res; 87 struct mlxsw_hwmon *hwmon; 88 struct mlxsw_thermal *thermal; 89 struct mlxsw_linecards *linecards; 90 struct mlxsw_core_port *ports; 91 unsigned int max_ports; 92 atomic_t active_ports_count; 93 bool fw_flash_in_progress; 94 struct { 95 struct devlink_health_reporter *fw_fatal; 96 } health; 97 struct mlxsw_env *env; 98 unsigned long driver_priv[]; 99 /* driver_priv has to be always the last item */ 100 }; 101 102 struct mlxsw_linecards *mlxsw_core_linecards(struct mlxsw_core *mlxsw_core) 103 { 104 return mlxsw_core->linecards; 105 } 106 107 void mlxsw_core_linecards_set(struct mlxsw_core *mlxsw_core, 108 struct mlxsw_linecards *linecards) 109 { 110 mlxsw_core->linecards = linecards; 111 } 112 113 #define MLXSW_PORT_MAX_PORTS_DEFAULT 0x40 114 115 static u64 mlxsw_ports_occ_get(void *priv) 116 { 117 struct mlxsw_core *mlxsw_core = priv; 118 119 return atomic_read(&mlxsw_core->active_ports_count); 120 } 121 122 static int mlxsw_core_resources_ports_register(struct mlxsw_core *mlxsw_core) 123 { 124 struct devlink *devlink = priv_to_devlink(mlxsw_core); 125 struct devlink_resource_size_params ports_num_params; 126 u32 max_ports; 127 128 max_ports = mlxsw_core->max_ports - 1; 129 devlink_resource_size_params_init(&ports_num_params, max_ports, 130 max_ports, 1, 131 DEVLINK_RESOURCE_UNIT_ENTRY); 132 133 return devl_resource_register(devlink, 134 DEVLINK_RESOURCE_GENERIC_NAME_PORTS, 135 max_ports, MLXSW_CORE_RESOURCE_PORTS, 136 DEVLINK_RESOURCE_ID_PARENT_TOP, 137 &ports_num_params); 138 } 139 140 static int mlxsw_ports_init(struct mlxsw_core *mlxsw_core, bool reload) 141 { 142 struct devlink *devlink = priv_to_devlink(mlxsw_core); 143 int err; 144 145 /* Switch ports are numbered from 1 to queried value */ 146 if (MLXSW_CORE_RES_VALID(mlxsw_core, MAX_SYSTEM_PORT)) 147 mlxsw_core->max_ports = MLXSW_CORE_RES_GET(mlxsw_core, 148 MAX_SYSTEM_PORT) + 1; 149 else 150 mlxsw_core->max_ports = MLXSW_PORT_MAX_PORTS_DEFAULT + 1; 151 152 mlxsw_core->ports = kcalloc(mlxsw_core->max_ports, 153 sizeof(struct mlxsw_core_port), GFP_KERNEL); 154 if (!mlxsw_core->ports) 155 return -ENOMEM; 156 157 if (!reload) { 158 err = mlxsw_core_resources_ports_register(mlxsw_core); 159 if (err) 160 goto err_resources_ports_register; 161 } 162 atomic_set(&mlxsw_core->active_ports_count, 0); 163 devl_resource_occ_get_register(devlink, MLXSW_CORE_RESOURCE_PORTS, 164 mlxsw_ports_occ_get, mlxsw_core); 165 166 return 0; 167 168 err_resources_ports_register: 169 kfree(mlxsw_core->ports); 170 return err; 171 } 172 173 static void mlxsw_ports_fini(struct mlxsw_core *mlxsw_core, bool reload) 174 { 175 struct devlink *devlink = priv_to_devlink(mlxsw_core); 176 177 devl_resource_occ_get_unregister(devlink, MLXSW_CORE_RESOURCE_PORTS); 178 if (!reload) 179 devl_resources_unregister(priv_to_devlink(mlxsw_core)); 180 181 kfree(mlxsw_core->ports); 182 } 183 184 unsigned int mlxsw_core_max_ports(const struct mlxsw_core *mlxsw_core) 185 { 186 return mlxsw_core->max_ports; 187 } 188 EXPORT_SYMBOL(mlxsw_core_max_ports); 189 190 int mlxsw_core_max_lag(struct mlxsw_core *mlxsw_core, u16 *p_max_lag) 191 { 192 struct mlxsw_driver *driver = mlxsw_core->driver; 193 194 if (driver->profile->used_max_lag) { 195 *p_max_lag = driver->profile->max_lag; 196 return 0; 197 } 198 199 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_LAG)) 200 return -EIO; 201 202 *p_max_lag = MLXSW_CORE_RES_GET(mlxsw_core, MAX_LAG); 203 return 0; 204 } 205 EXPORT_SYMBOL(mlxsw_core_max_lag); 206 207 void *mlxsw_core_driver_priv(struct mlxsw_core *mlxsw_core) 208 { 209 return mlxsw_core->driver_priv; 210 } 211 EXPORT_SYMBOL(mlxsw_core_driver_priv); 212 213 bool 214 mlxsw_core_fw_rev_minor_subminor_validate(const struct mlxsw_fw_rev *rev, 215 const struct mlxsw_fw_rev *req_rev) 216 { 217 return rev->minor > req_rev->minor || 218 (rev->minor == req_rev->minor && 219 rev->subminor >= req_rev->subminor); 220 } 221 EXPORT_SYMBOL(mlxsw_core_fw_rev_minor_subminor_validate); 222 223 struct mlxsw_rx_listener_item { 224 struct list_head list; 225 struct mlxsw_rx_listener rxl; 226 void *priv; 227 bool enabled; 228 }; 229 230 struct mlxsw_event_listener_item { 231 struct list_head list; 232 struct mlxsw_core *mlxsw_core; 233 struct mlxsw_event_listener el; 234 void *priv; 235 }; 236 237 static const u8 mlxsw_core_trap_groups[] = { 238 MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 239 MLXSW_REG_HTGT_TRAP_GROUP_CORE_EVENT, 240 }; 241 242 static int mlxsw_core_trap_groups_set(struct mlxsw_core *mlxsw_core) 243 { 244 char htgt_pl[MLXSW_REG_HTGT_LEN]; 245 int err; 246 int i; 247 248 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_TXRX)) 249 return 0; 250 251 for (i = 0; i < ARRAY_SIZE(mlxsw_core_trap_groups); i++) { 252 mlxsw_reg_htgt_pack(htgt_pl, mlxsw_core_trap_groups[i], 253 MLXSW_REG_HTGT_INVALID_POLICER, 254 MLXSW_REG_HTGT_DEFAULT_PRIORITY, 255 MLXSW_REG_HTGT_DEFAULT_TC); 256 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl); 257 if (err) 258 return err; 259 } 260 return 0; 261 } 262 263 /****************** 264 * EMAD processing 265 ******************/ 266 267 /* emad_eth_hdr_dmac 268 * Destination MAC in EMAD's Ethernet header. 269 * Must be set to 01:02:c9:00:00:01 270 */ 271 MLXSW_ITEM_BUF(emad, eth_hdr, dmac, 0x00, 6); 272 273 /* emad_eth_hdr_smac 274 * Source MAC in EMAD's Ethernet header. 275 * Must be set to 00:02:c9:01:02:03 276 */ 277 MLXSW_ITEM_BUF(emad, eth_hdr, smac, 0x06, 6); 278 279 /* emad_eth_hdr_ethertype 280 * Ethertype in EMAD's Ethernet header. 281 * Must be set to 0x8932 282 */ 283 MLXSW_ITEM32(emad, eth_hdr, ethertype, 0x0C, 16, 16); 284 285 /* emad_eth_hdr_mlx_proto 286 * Mellanox protocol. 287 * Must be set to 0x0. 288 */ 289 MLXSW_ITEM32(emad, eth_hdr, mlx_proto, 0x0C, 8, 8); 290 291 /* emad_eth_hdr_ver 292 * Mellanox protocol version. 293 * Must be set to 0x0. 294 */ 295 MLXSW_ITEM32(emad, eth_hdr, ver, 0x0C, 4, 4); 296 297 /* emad_op_tlv_type 298 * Type of the TLV. 299 * Must be set to 0x1 (operation TLV). 300 */ 301 MLXSW_ITEM32(emad, op_tlv, type, 0x00, 27, 5); 302 303 /* emad_op_tlv_len 304 * Length of the operation TLV in u32. 305 * Must be set to 0x4. 306 */ 307 MLXSW_ITEM32(emad, op_tlv, len, 0x00, 16, 11); 308 309 /* emad_op_tlv_dr 310 * Direct route bit. Setting to 1 indicates the EMAD is a direct route 311 * EMAD. DR TLV must follow. 312 * 313 * Note: Currently not supported and must not be set. 314 */ 315 MLXSW_ITEM32(emad, op_tlv, dr, 0x00, 15, 1); 316 317 /* emad_op_tlv_status 318 * Returned status in case of EMAD response. Must be set to 0 in case 319 * of EMAD request. 320 * 0x0 - success 321 * 0x1 - device is busy. Requester should retry 322 * 0x2 - Mellanox protocol version not supported 323 * 0x3 - unknown TLV 324 * 0x4 - register not supported 325 * 0x5 - operation class not supported 326 * 0x6 - EMAD method not supported 327 * 0x7 - bad parameter (e.g. port out of range) 328 * 0x8 - resource not available 329 * 0x9 - message receipt acknowledgment. Requester should retry 330 * 0x70 - internal error 331 */ 332 MLXSW_ITEM32(emad, op_tlv, status, 0x00, 8, 7); 333 334 /* emad_op_tlv_register_id 335 * Register ID of register within register TLV. 336 */ 337 MLXSW_ITEM32(emad, op_tlv, register_id, 0x04, 16, 16); 338 339 /* emad_op_tlv_r 340 * Response bit. Setting to 1 indicates Response, otherwise request. 341 */ 342 MLXSW_ITEM32(emad, op_tlv, r, 0x04, 15, 1); 343 344 /* emad_op_tlv_method 345 * EMAD method type. 346 * 0x1 - query 347 * 0x2 - write 348 * 0x3 - send (currently not supported) 349 * 0x4 - event 350 */ 351 MLXSW_ITEM32(emad, op_tlv, method, 0x04, 8, 7); 352 353 /* emad_op_tlv_class 354 * EMAD operation class. Must be set to 0x1 (REG_ACCESS). 355 */ 356 MLXSW_ITEM32(emad, op_tlv, class, 0x04, 0, 8); 357 358 /* emad_op_tlv_tid 359 * EMAD transaction ID. Used for pairing request and response EMADs. 360 */ 361 MLXSW_ITEM64(emad, op_tlv, tid, 0x08, 0, 64); 362 363 /* emad_string_tlv_type 364 * Type of the TLV. 365 * Must be set to 0x2 (string TLV). 366 */ 367 MLXSW_ITEM32(emad, string_tlv, type, 0x00, 27, 5); 368 369 /* emad_string_tlv_len 370 * Length of the string TLV in u32. 371 */ 372 MLXSW_ITEM32(emad, string_tlv, len, 0x00, 16, 11); 373 374 #define MLXSW_EMAD_STRING_TLV_STRING_LEN 128 375 376 /* emad_string_tlv_string 377 * String provided by the device's firmware in case of erroneous register access 378 */ 379 MLXSW_ITEM_BUF(emad, string_tlv, string, 0x04, 380 MLXSW_EMAD_STRING_TLV_STRING_LEN); 381 382 /* emad_latency_tlv_type 383 * Type of the TLV. 384 * Must be set to 0x4 (latency TLV). 385 */ 386 MLXSW_ITEM32(emad, latency_tlv, type, 0x00, 27, 5); 387 388 /* emad_latency_tlv_len 389 * Length of the latency TLV in u32. 390 */ 391 MLXSW_ITEM32(emad, latency_tlv, len, 0x00, 16, 11); 392 393 /* emad_latency_tlv_latency_time 394 * EMAD latency time in units of uSec. 395 */ 396 MLXSW_ITEM32(emad, latency_tlv, latency_time, 0x04, 0, 32); 397 398 /* emad_reg_tlv_type 399 * Type of the TLV. 400 * Must be set to 0x3 (register TLV). 401 */ 402 MLXSW_ITEM32(emad, reg_tlv, type, 0x00, 27, 5); 403 404 /* emad_reg_tlv_len 405 * Length of the operation TLV in u32. 406 */ 407 MLXSW_ITEM32(emad, reg_tlv, len, 0x00, 16, 11); 408 409 /* emad_end_tlv_type 410 * Type of the TLV. 411 * Must be set to 0x0 (end TLV). 412 */ 413 MLXSW_ITEM32(emad, end_tlv, type, 0x00, 27, 5); 414 415 /* emad_end_tlv_len 416 * Length of the end TLV in u32. 417 * Must be set to 1. 418 */ 419 MLXSW_ITEM32(emad, end_tlv, len, 0x00, 16, 11); 420 421 enum mlxsw_core_reg_access_type { 422 MLXSW_CORE_REG_ACCESS_TYPE_QUERY, 423 MLXSW_CORE_REG_ACCESS_TYPE_WRITE, 424 }; 425 426 static inline const char * 427 mlxsw_core_reg_access_type_str(enum mlxsw_core_reg_access_type type) 428 { 429 switch (type) { 430 case MLXSW_CORE_REG_ACCESS_TYPE_QUERY: 431 return "query"; 432 case MLXSW_CORE_REG_ACCESS_TYPE_WRITE: 433 return "write"; 434 } 435 BUG(); 436 } 437 438 static void mlxsw_emad_pack_end_tlv(char *end_tlv) 439 { 440 mlxsw_emad_end_tlv_type_set(end_tlv, MLXSW_EMAD_TLV_TYPE_END); 441 mlxsw_emad_end_tlv_len_set(end_tlv, MLXSW_EMAD_END_TLV_LEN); 442 } 443 444 static void mlxsw_emad_pack_reg_tlv(char *reg_tlv, 445 const struct mlxsw_reg_info *reg, 446 char *payload) 447 { 448 mlxsw_emad_reg_tlv_type_set(reg_tlv, MLXSW_EMAD_TLV_TYPE_REG); 449 mlxsw_emad_reg_tlv_len_set(reg_tlv, reg->len / sizeof(u32) + 1); 450 memcpy(reg_tlv + sizeof(u32), payload, reg->len); 451 } 452 453 static void mlxsw_emad_pack_string_tlv(char *string_tlv) 454 { 455 mlxsw_emad_string_tlv_type_set(string_tlv, MLXSW_EMAD_TLV_TYPE_STRING); 456 mlxsw_emad_string_tlv_len_set(string_tlv, MLXSW_EMAD_STRING_TLV_LEN); 457 } 458 459 static void mlxsw_emad_pack_op_tlv(char *op_tlv, 460 const struct mlxsw_reg_info *reg, 461 enum mlxsw_core_reg_access_type type, 462 u64 tid) 463 { 464 mlxsw_emad_op_tlv_type_set(op_tlv, MLXSW_EMAD_TLV_TYPE_OP); 465 mlxsw_emad_op_tlv_len_set(op_tlv, MLXSW_EMAD_OP_TLV_LEN); 466 mlxsw_emad_op_tlv_dr_set(op_tlv, 0); 467 mlxsw_emad_op_tlv_status_set(op_tlv, 0); 468 mlxsw_emad_op_tlv_register_id_set(op_tlv, reg->id); 469 mlxsw_emad_op_tlv_r_set(op_tlv, MLXSW_EMAD_OP_TLV_REQUEST); 470 if (type == MLXSW_CORE_REG_ACCESS_TYPE_QUERY) 471 mlxsw_emad_op_tlv_method_set(op_tlv, 472 MLXSW_EMAD_OP_TLV_METHOD_QUERY); 473 else 474 mlxsw_emad_op_tlv_method_set(op_tlv, 475 MLXSW_EMAD_OP_TLV_METHOD_WRITE); 476 mlxsw_emad_op_tlv_class_set(op_tlv, 477 MLXSW_EMAD_OP_TLV_CLASS_REG_ACCESS); 478 mlxsw_emad_op_tlv_tid_set(op_tlv, tid); 479 } 480 481 static void mlxsw_emad_pack_latency_tlv(char *latency_tlv) 482 { 483 mlxsw_emad_latency_tlv_type_set(latency_tlv, MLXSW_EMAD_TLV_TYPE_LATENCY); 484 mlxsw_emad_latency_tlv_len_set(latency_tlv, MLXSW_EMAD_LATENCY_TLV_LEN); 485 } 486 487 static int mlxsw_emad_construct_eth_hdr(struct sk_buff *skb) 488 { 489 char *eth_hdr = skb_push(skb, MLXSW_EMAD_ETH_HDR_LEN); 490 491 mlxsw_emad_eth_hdr_dmac_memcpy_to(eth_hdr, MLXSW_EMAD_EH_DMAC); 492 mlxsw_emad_eth_hdr_smac_memcpy_to(eth_hdr, MLXSW_EMAD_EH_SMAC); 493 mlxsw_emad_eth_hdr_ethertype_set(eth_hdr, MLXSW_EMAD_EH_ETHERTYPE); 494 mlxsw_emad_eth_hdr_mlx_proto_set(eth_hdr, MLXSW_EMAD_EH_MLX_PROTO); 495 mlxsw_emad_eth_hdr_ver_set(eth_hdr, MLXSW_EMAD_EH_PROTO_VERSION); 496 497 skb_reset_mac_header(skb); 498 499 return 0; 500 } 501 502 static void mlxsw_emad_construct(const struct mlxsw_core *mlxsw_core, 503 struct sk_buff *skb, 504 const struct mlxsw_reg_info *reg, 505 char *payload, 506 enum mlxsw_core_reg_access_type type, u64 tid) 507 { 508 char *buf; 509 510 buf = skb_push(skb, MLXSW_EMAD_END_TLV_LEN * sizeof(u32)); 511 mlxsw_emad_pack_end_tlv(buf); 512 513 buf = skb_push(skb, reg->len + sizeof(u32)); 514 mlxsw_emad_pack_reg_tlv(buf, reg, payload); 515 516 if (mlxsw_core->emad.enable_latency_tlv) { 517 buf = skb_push(skb, MLXSW_EMAD_LATENCY_TLV_LEN * sizeof(u32)); 518 mlxsw_emad_pack_latency_tlv(buf); 519 } 520 521 if (mlxsw_core->emad.enable_string_tlv) { 522 buf = skb_push(skb, MLXSW_EMAD_STRING_TLV_LEN * sizeof(u32)); 523 mlxsw_emad_pack_string_tlv(buf); 524 } 525 526 buf = skb_push(skb, MLXSW_EMAD_OP_TLV_LEN * sizeof(u32)); 527 mlxsw_emad_pack_op_tlv(buf, reg, type, tid); 528 529 mlxsw_emad_construct_eth_hdr(skb); 530 } 531 532 struct mlxsw_emad_tlv_offsets { 533 u16 op_tlv; 534 u16 string_tlv; 535 u16 latency_tlv; 536 u16 reg_tlv; 537 }; 538 539 static bool mlxsw_emad_tlv_is_string_tlv(const char *tlv) 540 { 541 u8 tlv_type = mlxsw_emad_string_tlv_type_get(tlv); 542 543 return tlv_type == MLXSW_EMAD_TLV_TYPE_STRING; 544 } 545 546 static bool mlxsw_emad_tlv_is_latency_tlv(const char *tlv) 547 { 548 u8 tlv_type = mlxsw_emad_latency_tlv_type_get(tlv); 549 550 return tlv_type == MLXSW_EMAD_TLV_TYPE_LATENCY; 551 } 552 553 static void mlxsw_emad_tlv_parse(struct sk_buff *skb) 554 { 555 struct mlxsw_emad_tlv_offsets *offsets = 556 (struct mlxsw_emad_tlv_offsets *) skb->cb; 557 558 offsets->op_tlv = MLXSW_EMAD_ETH_HDR_LEN; 559 offsets->string_tlv = 0; 560 offsets->latency_tlv = 0; 561 562 offsets->reg_tlv = MLXSW_EMAD_ETH_HDR_LEN + 563 MLXSW_EMAD_OP_TLV_LEN * sizeof(u32); 564 565 /* If string TLV is present, it must come after the operation TLV. */ 566 if (mlxsw_emad_tlv_is_string_tlv(skb->data + offsets->reg_tlv)) { 567 offsets->string_tlv = offsets->reg_tlv; 568 offsets->reg_tlv += MLXSW_EMAD_STRING_TLV_LEN * sizeof(u32); 569 } 570 571 if (mlxsw_emad_tlv_is_latency_tlv(skb->data + offsets->reg_tlv)) { 572 offsets->latency_tlv = offsets->reg_tlv; 573 offsets->reg_tlv += MLXSW_EMAD_LATENCY_TLV_LEN * sizeof(u32); 574 } 575 } 576 577 static char *mlxsw_emad_op_tlv(const struct sk_buff *skb) 578 { 579 struct mlxsw_emad_tlv_offsets *offsets = 580 (struct mlxsw_emad_tlv_offsets *) skb->cb; 581 582 return ((char *) (skb->data + offsets->op_tlv)); 583 } 584 585 static char *mlxsw_emad_string_tlv(const struct sk_buff *skb) 586 { 587 struct mlxsw_emad_tlv_offsets *offsets = 588 (struct mlxsw_emad_tlv_offsets *) skb->cb; 589 590 if (!offsets->string_tlv) 591 return NULL; 592 593 return ((char *) (skb->data + offsets->string_tlv)); 594 } 595 596 static char *mlxsw_emad_reg_tlv(const struct sk_buff *skb) 597 { 598 struct mlxsw_emad_tlv_offsets *offsets = 599 (struct mlxsw_emad_tlv_offsets *) skb->cb; 600 601 return ((char *) (skb->data + offsets->reg_tlv)); 602 } 603 604 static char *mlxsw_emad_reg_payload(const char *reg_tlv) 605 { 606 return ((char *) (reg_tlv + sizeof(u32))); 607 } 608 609 static char *mlxsw_emad_reg_payload_cmd(const char *mbox) 610 { 611 return ((char *) (mbox + (MLXSW_EMAD_OP_TLV_LEN + 1) * sizeof(u32))); 612 } 613 614 static u64 mlxsw_emad_get_tid(const struct sk_buff *skb) 615 { 616 char *op_tlv; 617 618 op_tlv = mlxsw_emad_op_tlv(skb); 619 return mlxsw_emad_op_tlv_tid_get(op_tlv); 620 } 621 622 static bool mlxsw_emad_is_resp(const struct sk_buff *skb) 623 { 624 char *op_tlv; 625 626 op_tlv = mlxsw_emad_op_tlv(skb); 627 return (mlxsw_emad_op_tlv_r_get(op_tlv) == MLXSW_EMAD_OP_TLV_RESPONSE); 628 } 629 630 static int mlxsw_emad_process_status(char *op_tlv, 631 enum mlxsw_emad_op_tlv_status *p_status) 632 { 633 *p_status = mlxsw_emad_op_tlv_status_get(op_tlv); 634 635 switch (*p_status) { 636 case MLXSW_EMAD_OP_TLV_STATUS_SUCCESS: 637 return 0; 638 case MLXSW_EMAD_OP_TLV_STATUS_BUSY: 639 case MLXSW_EMAD_OP_TLV_STATUS_MESSAGE_RECEIPT_ACK: 640 return -EAGAIN; 641 case MLXSW_EMAD_OP_TLV_STATUS_VERSION_NOT_SUPPORTED: 642 case MLXSW_EMAD_OP_TLV_STATUS_UNKNOWN_TLV: 643 case MLXSW_EMAD_OP_TLV_STATUS_REGISTER_NOT_SUPPORTED: 644 case MLXSW_EMAD_OP_TLV_STATUS_CLASS_NOT_SUPPORTED: 645 case MLXSW_EMAD_OP_TLV_STATUS_METHOD_NOT_SUPPORTED: 646 case MLXSW_EMAD_OP_TLV_STATUS_BAD_PARAMETER: 647 case MLXSW_EMAD_OP_TLV_STATUS_RESOURCE_NOT_AVAILABLE: 648 case MLXSW_EMAD_OP_TLV_STATUS_INTERNAL_ERROR: 649 default: 650 return -EIO; 651 } 652 } 653 654 static int 655 mlxsw_emad_process_status_skb(struct sk_buff *skb, 656 enum mlxsw_emad_op_tlv_status *p_status) 657 { 658 return mlxsw_emad_process_status(mlxsw_emad_op_tlv(skb), p_status); 659 } 660 661 struct mlxsw_reg_trans { 662 struct list_head list; 663 struct list_head bulk_list; 664 struct mlxsw_core *core; 665 struct sk_buff *tx_skb; 666 struct mlxsw_tx_info tx_info; 667 struct delayed_work timeout_dw; 668 unsigned int retries; 669 u64 tid; 670 struct completion completion; 671 atomic_t active; 672 mlxsw_reg_trans_cb_t *cb; 673 unsigned long cb_priv; 674 const struct mlxsw_reg_info *reg; 675 enum mlxsw_core_reg_access_type type; 676 int err; 677 char *emad_err_string; 678 enum mlxsw_emad_op_tlv_status emad_status; 679 struct rcu_head rcu; 680 }; 681 682 static void mlxsw_emad_process_string_tlv(const struct sk_buff *skb, 683 struct mlxsw_reg_trans *trans) 684 { 685 char *string_tlv; 686 char *string; 687 688 string_tlv = mlxsw_emad_string_tlv(skb); 689 if (!string_tlv) 690 return; 691 692 trans->emad_err_string = kzalloc(MLXSW_EMAD_STRING_TLV_STRING_LEN, 693 GFP_ATOMIC); 694 if (!trans->emad_err_string) 695 return; 696 697 string = mlxsw_emad_string_tlv_string_data(string_tlv); 698 strscpy(trans->emad_err_string, string, 699 MLXSW_EMAD_STRING_TLV_STRING_LEN); 700 } 701 702 #define MLXSW_EMAD_TIMEOUT_DURING_FW_FLASH_MS 3000 703 #define MLXSW_EMAD_TIMEOUT_MS 200 704 705 static void mlxsw_emad_trans_timeout_schedule(struct mlxsw_reg_trans *trans) 706 { 707 unsigned long timeout = msecs_to_jiffies(MLXSW_EMAD_TIMEOUT_MS); 708 709 if (trans->core->fw_flash_in_progress) 710 timeout = msecs_to_jiffies(MLXSW_EMAD_TIMEOUT_DURING_FW_FLASH_MS); 711 712 queue_delayed_work(trans->core->emad_wq, &trans->timeout_dw, 713 timeout << trans->retries); 714 } 715 716 static int mlxsw_emad_transmit(struct mlxsw_core *mlxsw_core, 717 struct mlxsw_reg_trans *trans) 718 { 719 struct sk_buff *skb; 720 int err; 721 722 skb = skb_clone(trans->tx_skb, GFP_KERNEL); 723 if (!skb) 724 return -ENOMEM; 725 726 trace_devlink_hwmsg(priv_to_devlink(mlxsw_core), false, 0, 727 skb->data + mlxsw_core->driver->txhdr_len, 728 skb->len - mlxsw_core->driver->txhdr_len); 729 730 atomic_set(&trans->active, 1); 731 err = mlxsw_core_skb_transmit(mlxsw_core, skb, &trans->tx_info); 732 if (err) { 733 dev_kfree_skb(skb); 734 return err; 735 } 736 mlxsw_emad_trans_timeout_schedule(trans); 737 return 0; 738 } 739 740 static void mlxsw_emad_trans_finish(struct mlxsw_reg_trans *trans, int err) 741 { 742 struct mlxsw_core *mlxsw_core = trans->core; 743 744 dev_kfree_skb(trans->tx_skb); 745 spin_lock_bh(&mlxsw_core->emad.trans_list_lock); 746 list_del_rcu(&trans->list); 747 spin_unlock_bh(&mlxsw_core->emad.trans_list_lock); 748 trans->err = err; 749 complete(&trans->completion); 750 } 751 752 static void mlxsw_emad_transmit_retry(struct mlxsw_core *mlxsw_core, 753 struct mlxsw_reg_trans *trans) 754 { 755 int err; 756 757 if (trans->retries < MLXSW_EMAD_MAX_RETRY) { 758 trans->retries++; 759 err = mlxsw_emad_transmit(trans->core, trans); 760 if (err == 0) 761 return; 762 763 if (!atomic_dec_and_test(&trans->active)) 764 return; 765 } else { 766 err = -EIO; 767 } 768 mlxsw_emad_trans_finish(trans, err); 769 } 770 771 static void mlxsw_emad_trans_timeout_work(struct work_struct *work) 772 { 773 struct mlxsw_reg_trans *trans = container_of(work, 774 struct mlxsw_reg_trans, 775 timeout_dw.work); 776 777 if (!atomic_dec_and_test(&trans->active)) 778 return; 779 780 mlxsw_emad_transmit_retry(trans->core, trans); 781 } 782 783 static void mlxsw_emad_process_response(struct mlxsw_core *mlxsw_core, 784 struct mlxsw_reg_trans *trans, 785 struct sk_buff *skb) 786 { 787 int err; 788 789 if (!atomic_dec_and_test(&trans->active)) 790 return; 791 792 err = mlxsw_emad_process_status_skb(skb, &trans->emad_status); 793 if (err == -EAGAIN) { 794 mlxsw_emad_transmit_retry(mlxsw_core, trans); 795 } else { 796 if (err == 0) { 797 char *reg_tlv = mlxsw_emad_reg_tlv(skb); 798 799 if (trans->cb) 800 trans->cb(mlxsw_core, 801 mlxsw_emad_reg_payload(reg_tlv), 802 trans->reg->len, trans->cb_priv); 803 } else { 804 mlxsw_emad_process_string_tlv(skb, trans); 805 } 806 mlxsw_emad_trans_finish(trans, err); 807 } 808 } 809 810 /* called with rcu read lock held */ 811 static void mlxsw_emad_rx_listener_func(struct sk_buff *skb, u16 local_port, 812 void *priv) 813 { 814 struct mlxsw_core *mlxsw_core = priv; 815 struct mlxsw_reg_trans *trans; 816 817 trace_devlink_hwmsg(priv_to_devlink(mlxsw_core), true, 0, 818 skb->data, skb->len); 819 820 mlxsw_emad_tlv_parse(skb); 821 822 if (!mlxsw_emad_is_resp(skb)) 823 goto free_skb; 824 825 list_for_each_entry_rcu(trans, &mlxsw_core->emad.trans_list, list) { 826 if (mlxsw_emad_get_tid(skb) == trans->tid) { 827 mlxsw_emad_process_response(mlxsw_core, trans, skb); 828 break; 829 } 830 } 831 832 free_skb: 833 dev_kfree_skb(skb); 834 } 835 836 static const struct mlxsw_listener mlxsw_emad_rx_listener = 837 MLXSW_RXL(mlxsw_emad_rx_listener_func, ETHEMAD, TRAP_TO_CPU, false, 838 EMAD, DISCARD); 839 840 static int mlxsw_emad_tlv_enable(struct mlxsw_core *mlxsw_core) 841 { 842 char mgir_pl[MLXSW_REG_MGIR_LEN]; 843 bool string_tlv, latency_tlv; 844 int err; 845 846 mlxsw_reg_mgir_pack(mgir_pl); 847 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mgir), mgir_pl); 848 if (err) 849 return err; 850 851 string_tlv = mlxsw_reg_mgir_fw_info_string_tlv_get(mgir_pl); 852 mlxsw_core->emad.enable_string_tlv = string_tlv; 853 854 latency_tlv = mlxsw_reg_mgir_fw_info_latency_tlv_get(mgir_pl); 855 mlxsw_core->emad.enable_latency_tlv = latency_tlv; 856 857 return 0; 858 } 859 860 static void mlxsw_emad_tlv_disable(struct mlxsw_core *mlxsw_core) 861 { 862 mlxsw_core->emad.enable_latency_tlv = false; 863 mlxsw_core->emad.enable_string_tlv = false; 864 } 865 866 static int mlxsw_emad_init(struct mlxsw_core *mlxsw_core) 867 { 868 struct workqueue_struct *emad_wq; 869 u64 tid; 870 int err; 871 872 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_TXRX)) 873 return 0; 874 875 emad_wq = alloc_workqueue("mlxsw_core_emad", 0, 0); 876 if (!emad_wq) 877 return -ENOMEM; 878 mlxsw_core->emad_wq = emad_wq; 879 880 /* Set the upper 32 bits of the transaction ID field to a random 881 * number. This allows us to discard EMADs addressed to other 882 * devices. 883 */ 884 get_random_bytes(&tid, 4); 885 tid <<= 32; 886 atomic64_set(&mlxsw_core->emad.tid, tid); 887 888 INIT_LIST_HEAD(&mlxsw_core->emad.trans_list); 889 spin_lock_init(&mlxsw_core->emad.trans_list_lock); 890 891 err = mlxsw_core_trap_register(mlxsw_core, &mlxsw_emad_rx_listener, 892 mlxsw_core); 893 if (err) 894 goto err_trap_register; 895 896 err = mlxsw_emad_tlv_enable(mlxsw_core); 897 if (err) 898 goto err_emad_tlv_enable; 899 900 mlxsw_core->emad.use_emad = true; 901 902 return 0; 903 904 err_emad_tlv_enable: 905 mlxsw_core_trap_unregister(mlxsw_core, &mlxsw_emad_rx_listener, 906 mlxsw_core); 907 err_trap_register: 908 destroy_workqueue(mlxsw_core->emad_wq); 909 return err; 910 } 911 912 static void mlxsw_emad_fini(struct mlxsw_core *mlxsw_core) 913 { 914 915 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_TXRX)) 916 return; 917 918 mlxsw_core->emad.use_emad = false; 919 mlxsw_emad_tlv_disable(mlxsw_core); 920 mlxsw_core_trap_unregister(mlxsw_core, &mlxsw_emad_rx_listener, 921 mlxsw_core); 922 destroy_workqueue(mlxsw_core->emad_wq); 923 } 924 925 static struct sk_buff *mlxsw_emad_alloc(const struct mlxsw_core *mlxsw_core, 926 u16 reg_len) 927 { 928 struct sk_buff *skb; 929 u16 emad_len; 930 931 emad_len = (reg_len + sizeof(u32) + MLXSW_EMAD_ETH_HDR_LEN + 932 (MLXSW_EMAD_OP_TLV_LEN + MLXSW_EMAD_END_TLV_LEN) * 933 sizeof(u32) + mlxsw_core->driver->txhdr_len); 934 if (mlxsw_core->emad.enable_string_tlv) 935 emad_len += MLXSW_EMAD_STRING_TLV_LEN * sizeof(u32); 936 if (mlxsw_core->emad.enable_latency_tlv) 937 emad_len += MLXSW_EMAD_LATENCY_TLV_LEN * sizeof(u32); 938 if (emad_len > MLXSW_EMAD_MAX_FRAME_LEN) 939 return NULL; 940 941 skb = netdev_alloc_skb(NULL, emad_len); 942 if (!skb) 943 return NULL; 944 memset(skb->data, 0, emad_len); 945 skb_reserve(skb, emad_len); 946 947 return skb; 948 } 949 950 static int mlxsw_emad_reg_access(struct mlxsw_core *mlxsw_core, 951 const struct mlxsw_reg_info *reg, 952 char *payload, 953 enum mlxsw_core_reg_access_type type, 954 struct mlxsw_reg_trans *trans, 955 struct list_head *bulk_list, 956 mlxsw_reg_trans_cb_t *cb, 957 unsigned long cb_priv, u64 tid) 958 { 959 struct sk_buff *skb; 960 int err; 961 962 dev_dbg(mlxsw_core->bus_info->dev, "EMAD reg access (tid=%llx,reg_id=%x(%s),type=%s)\n", 963 tid, reg->id, mlxsw_reg_id_str(reg->id), 964 mlxsw_core_reg_access_type_str(type)); 965 966 skb = mlxsw_emad_alloc(mlxsw_core, reg->len); 967 if (!skb) 968 return -ENOMEM; 969 970 list_add_tail(&trans->bulk_list, bulk_list); 971 trans->core = mlxsw_core; 972 trans->tx_skb = skb; 973 trans->tx_info.local_port = MLXSW_PORT_CPU_PORT; 974 trans->tx_info.is_emad = true; 975 INIT_DELAYED_WORK(&trans->timeout_dw, mlxsw_emad_trans_timeout_work); 976 trans->tid = tid; 977 init_completion(&trans->completion); 978 trans->cb = cb; 979 trans->cb_priv = cb_priv; 980 trans->reg = reg; 981 trans->type = type; 982 983 mlxsw_emad_construct(mlxsw_core, skb, reg, payload, type, trans->tid); 984 mlxsw_core->driver->txhdr_construct(skb, &trans->tx_info); 985 986 spin_lock_bh(&mlxsw_core->emad.trans_list_lock); 987 list_add_tail_rcu(&trans->list, &mlxsw_core->emad.trans_list); 988 spin_unlock_bh(&mlxsw_core->emad.trans_list_lock); 989 err = mlxsw_emad_transmit(mlxsw_core, trans); 990 if (err) 991 goto err_out; 992 return 0; 993 994 err_out: 995 spin_lock_bh(&mlxsw_core->emad.trans_list_lock); 996 list_del_rcu(&trans->list); 997 spin_unlock_bh(&mlxsw_core->emad.trans_list_lock); 998 list_del(&trans->bulk_list); 999 dev_kfree_skb(trans->tx_skb); 1000 return err; 1001 } 1002 1003 /***************** 1004 * Core functions 1005 *****************/ 1006 1007 int mlxsw_core_driver_register(struct mlxsw_driver *mlxsw_driver) 1008 { 1009 spin_lock(&mlxsw_core_driver_list_lock); 1010 list_add_tail(&mlxsw_driver->list, &mlxsw_core_driver_list); 1011 spin_unlock(&mlxsw_core_driver_list_lock); 1012 return 0; 1013 } 1014 EXPORT_SYMBOL(mlxsw_core_driver_register); 1015 1016 void mlxsw_core_driver_unregister(struct mlxsw_driver *mlxsw_driver) 1017 { 1018 spin_lock(&mlxsw_core_driver_list_lock); 1019 list_del(&mlxsw_driver->list); 1020 spin_unlock(&mlxsw_core_driver_list_lock); 1021 } 1022 EXPORT_SYMBOL(mlxsw_core_driver_unregister); 1023 1024 static struct mlxsw_driver *__driver_find(const char *kind) 1025 { 1026 struct mlxsw_driver *mlxsw_driver; 1027 1028 list_for_each_entry(mlxsw_driver, &mlxsw_core_driver_list, list) { 1029 if (strcmp(mlxsw_driver->kind, kind) == 0) 1030 return mlxsw_driver; 1031 } 1032 return NULL; 1033 } 1034 1035 static struct mlxsw_driver *mlxsw_core_driver_get(const char *kind) 1036 { 1037 struct mlxsw_driver *mlxsw_driver; 1038 1039 spin_lock(&mlxsw_core_driver_list_lock); 1040 mlxsw_driver = __driver_find(kind); 1041 spin_unlock(&mlxsw_core_driver_list_lock); 1042 return mlxsw_driver; 1043 } 1044 1045 int mlxsw_core_fw_flash(struct mlxsw_core *mlxsw_core, 1046 struct mlxfw_dev *mlxfw_dev, 1047 const struct firmware *firmware, 1048 struct netlink_ext_ack *extack) 1049 { 1050 int err; 1051 1052 mlxsw_core->fw_flash_in_progress = true; 1053 err = mlxfw_firmware_flash(mlxfw_dev, firmware, extack); 1054 mlxsw_core->fw_flash_in_progress = false; 1055 1056 return err; 1057 } 1058 1059 struct mlxsw_core_fw_info { 1060 struct mlxfw_dev mlxfw_dev; 1061 struct mlxsw_core *mlxsw_core; 1062 }; 1063 1064 static int mlxsw_core_fw_component_query(struct mlxfw_dev *mlxfw_dev, 1065 u16 component_index, u32 *p_max_size, 1066 u8 *p_align_bits, u16 *p_max_write_size) 1067 { 1068 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1069 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1070 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1071 char mcqi_pl[MLXSW_REG_MCQI_LEN]; 1072 int err; 1073 1074 mlxsw_reg_mcqi_pack(mcqi_pl, component_index); 1075 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mcqi), mcqi_pl); 1076 if (err) 1077 return err; 1078 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits, p_max_write_size); 1079 1080 *p_align_bits = max_t(u8, *p_align_bits, 2); 1081 *p_max_write_size = min_t(u16, *p_max_write_size, MLXSW_REG_MCDA_MAX_DATA_LEN); 1082 return 0; 1083 } 1084 1085 static int mlxsw_core_fw_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle) 1086 { 1087 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1088 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1089 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1090 char mcc_pl[MLXSW_REG_MCC_LEN]; 1091 u8 control_state; 1092 int err; 1093 1094 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0); 1095 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1096 if (err) 1097 return err; 1098 1099 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state); 1100 if (control_state != MLXFW_FSM_STATE_IDLE) 1101 return -EBUSY; 1102 1103 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE, 0, *fwhandle, 0); 1104 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1105 } 1106 1107 static int mlxsw_core_fw_fsm_component_update(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 1108 u16 component_index, u32 component_size) 1109 { 1110 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1111 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1112 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1113 char mcc_pl[MLXSW_REG_MCC_LEN]; 1114 1115 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT, 1116 component_index, fwhandle, component_size); 1117 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1118 } 1119 1120 static int mlxsw_core_fw_fsm_block_download(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 1121 u8 *data, u16 size, u32 offset) 1122 { 1123 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1124 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1125 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1126 char mcda_pl[MLXSW_REG_MCDA_LEN]; 1127 1128 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data); 1129 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcda), mcda_pl); 1130 } 1131 1132 static int mlxsw_core_fw_fsm_component_verify(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 1133 u16 component_index) 1134 { 1135 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1136 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1137 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1138 char mcc_pl[MLXSW_REG_MCC_LEN]; 1139 1140 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT, 1141 component_index, fwhandle, 0); 1142 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1143 } 1144 1145 static int mlxsw_core_fw_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 1146 { 1147 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1148 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1149 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1150 char mcc_pl[MLXSW_REG_MCC_LEN]; 1151 1152 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0, fwhandle, 0); 1153 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1154 } 1155 1156 static int mlxsw_core_fw_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 1157 enum mlxfw_fsm_state *fsm_state, 1158 enum mlxfw_fsm_state_err *fsm_state_err) 1159 { 1160 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1161 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1162 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1163 char mcc_pl[MLXSW_REG_MCC_LEN]; 1164 u8 control_state; 1165 u8 error_code; 1166 int err; 1167 1168 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0); 1169 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1170 if (err) 1171 return err; 1172 1173 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state); 1174 *fsm_state = control_state; 1175 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code, MLXFW_FSM_STATE_ERR_MAX); 1176 return 0; 1177 } 1178 1179 static void mlxsw_core_fw_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 1180 { 1181 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1182 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1183 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1184 char mcc_pl[MLXSW_REG_MCC_LEN]; 1185 1186 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0, fwhandle, 0); 1187 mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1188 } 1189 1190 static void mlxsw_core_fw_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 1191 { 1192 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1193 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1194 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1195 char mcc_pl[MLXSW_REG_MCC_LEN]; 1196 1197 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0, fwhandle, 0); 1198 mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1199 } 1200 1201 static const struct mlxfw_dev_ops mlxsw_core_fw_mlxsw_dev_ops = { 1202 .component_query = mlxsw_core_fw_component_query, 1203 .fsm_lock = mlxsw_core_fw_fsm_lock, 1204 .fsm_component_update = mlxsw_core_fw_fsm_component_update, 1205 .fsm_block_download = mlxsw_core_fw_fsm_block_download, 1206 .fsm_component_verify = mlxsw_core_fw_fsm_component_verify, 1207 .fsm_activate = mlxsw_core_fw_fsm_activate, 1208 .fsm_query_state = mlxsw_core_fw_fsm_query_state, 1209 .fsm_cancel = mlxsw_core_fw_fsm_cancel, 1210 .fsm_release = mlxsw_core_fw_fsm_release, 1211 }; 1212 1213 static int mlxsw_core_dev_fw_flash(struct mlxsw_core *mlxsw_core, 1214 const struct firmware *firmware, 1215 struct netlink_ext_ack *extack) 1216 { 1217 struct mlxsw_core_fw_info mlxsw_core_fw_info = { 1218 .mlxfw_dev = { 1219 .ops = &mlxsw_core_fw_mlxsw_dev_ops, 1220 .psid = mlxsw_core->bus_info->psid, 1221 .psid_size = strlen(mlxsw_core->bus_info->psid), 1222 .devlink = priv_to_devlink(mlxsw_core), 1223 }, 1224 .mlxsw_core = mlxsw_core 1225 }; 1226 1227 return mlxsw_core_fw_flash(mlxsw_core, &mlxsw_core_fw_info.mlxfw_dev, 1228 firmware, extack); 1229 } 1230 1231 static int mlxsw_core_fw_rev_validate(struct mlxsw_core *mlxsw_core, 1232 const struct mlxsw_bus_info *mlxsw_bus_info, 1233 const struct mlxsw_fw_rev *req_rev, 1234 const char *filename) 1235 { 1236 const struct mlxsw_fw_rev *rev = &mlxsw_bus_info->fw_rev; 1237 union devlink_param_value value; 1238 const struct firmware *firmware; 1239 int err; 1240 1241 /* Don't check if driver does not require it */ 1242 if (!req_rev || !filename) 1243 return 0; 1244 1245 /* Don't check if devlink 'fw_load_policy' param is 'flash' */ 1246 err = devlink_param_driverinit_value_get(priv_to_devlink(mlxsw_core), 1247 DEVLINK_PARAM_GENERIC_ID_FW_LOAD_POLICY, 1248 &value); 1249 if (err) 1250 return err; 1251 if (value.vu8 == DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_FLASH) 1252 return 0; 1253 1254 /* Validate driver & FW are compatible */ 1255 if (rev->major != req_rev->major) { 1256 WARN(1, "Mismatch in major FW version [%d:%d] is never expected; Please contact support\n", 1257 rev->major, req_rev->major); 1258 return -EINVAL; 1259 } 1260 if (mlxsw_core_fw_rev_minor_subminor_validate(rev, req_rev)) 1261 return 0; 1262 1263 dev_err(mlxsw_bus_info->dev, "The firmware version %d.%d.%d is incompatible with the driver (required >= %d.%d.%d)\n", 1264 rev->major, rev->minor, rev->subminor, req_rev->major, 1265 req_rev->minor, req_rev->subminor); 1266 dev_info(mlxsw_bus_info->dev, "Flashing firmware using file %s\n", filename); 1267 1268 err = request_firmware_direct(&firmware, filename, mlxsw_bus_info->dev); 1269 if (err) { 1270 dev_err(mlxsw_bus_info->dev, "Could not request firmware file %s\n", filename); 1271 return err; 1272 } 1273 1274 err = mlxsw_core_dev_fw_flash(mlxsw_core, firmware, NULL); 1275 release_firmware(firmware); 1276 if (err) 1277 dev_err(mlxsw_bus_info->dev, "Could not upgrade firmware\n"); 1278 1279 /* On FW flash success, tell the caller FW reset is needed 1280 * if current FW supports it. 1281 */ 1282 if (rev->minor >= req_rev->can_reset_minor) 1283 return err ? err : -EAGAIN; 1284 else 1285 return 0; 1286 } 1287 1288 static int mlxsw_core_fw_flash_update(struct mlxsw_core *mlxsw_core, 1289 struct devlink_flash_update_params *params, 1290 struct netlink_ext_ack *extack) 1291 { 1292 return mlxsw_core_dev_fw_flash(mlxsw_core, params->fw, extack); 1293 } 1294 1295 static int mlxsw_core_devlink_param_fw_load_policy_validate(struct devlink *devlink, u32 id, 1296 union devlink_param_value val, 1297 struct netlink_ext_ack *extack) 1298 { 1299 if (val.vu8 != DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_DRIVER && 1300 val.vu8 != DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_FLASH) { 1301 NL_SET_ERR_MSG_MOD(extack, "'fw_load_policy' must be 'driver' or 'flash'"); 1302 return -EINVAL; 1303 } 1304 1305 return 0; 1306 } 1307 1308 static const struct devlink_param mlxsw_core_fw_devlink_params[] = { 1309 DEVLINK_PARAM_GENERIC(FW_LOAD_POLICY, BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), NULL, NULL, 1310 mlxsw_core_devlink_param_fw_load_policy_validate), 1311 }; 1312 1313 static int mlxsw_core_fw_params_register(struct mlxsw_core *mlxsw_core) 1314 { 1315 struct devlink *devlink = priv_to_devlink(mlxsw_core); 1316 union devlink_param_value value; 1317 int err; 1318 1319 err = devlink_params_register(devlink, mlxsw_core_fw_devlink_params, 1320 ARRAY_SIZE(mlxsw_core_fw_devlink_params)); 1321 if (err) 1322 return err; 1323 1324 value.vu8 = DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_DRIVER; 1325 devlink_param_driverinit_value_set(devlink, DEVLINK_PARAM_GENERIC_ID_FW_LOAD_POLICY, value); 1326 return 0; 1327 } 1328 1329 static void mlxsw_core_fw_params_unregister(struct mlxsw_core *mlxsw_core) 1330 { 1331 devlink_params_unregister(priv_to_devlink(mlxsw_core), mlxsw_core_fw_devlink_params, 1332 ARRAY_SIZE(mlxsw_core_fw_devlink_params)); 1333 } 1334 1335 static void *__dl_port(struct devlink_port *devlink_port) 1336 { 1337 return container_of(devlink_port, struct mlxsw_core_port, devlink_port); 1338 } 1339 1340 static int mlxsw_devlink_port_split(struct devlink *devlink, 1341 struct devlink_port *port, 1342 unsigned int count, 1343 struct netlink_ext_ack *extack) 1344 { 1345 struct mlxsw_core_port *mlxsw_core_port = __dl_port(port); 1346 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1347 1348 if (!mlxsw_core->driver->port_split) 1349 return -EOPNOTSUPP; 1350 return mlxsw_core->driver->port_split(mlxsw_core, 1351 mlxsw_core_port->local_port, 1352 count, extack); 1353 } 1354 1355 static int mlxsw_devlink_port_unsplit(struct devlink *devlink, 1356 struct devlink_port *port, 1357 struct netlink_ext_ack *extack) 1358 { 1359 struct mlxsw_core_port *mlxsw_core_port = __dl_port(port); 1360 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1361 1362 if (!mlxsw_core->driver->port_unsplit) 1363 return -EOPNOTSUPP; 1364 return mlxsw_core->driver->port_unsplit(mlxsw_core, 1365 mlxsw_core_port->local_port, 1366 extack); 1367 } 1368 1369 static int 1370 mlxsw_devlink_sb_pool_get(struct devlink *devlink, 1371 unsigned int sb_index, u16 pool_index, 1372 struct devlink_sb_pool_info *pool_info) 1373 { 1374 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1375 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1376 1377 if (!mlxsw_driver->sb_pool_get) 1378 return -EOPNOTSUPP; 1379 return mlxsw_driver->sb_pool_get(mlxsw_core, sb_index, 1380 pool_index, pool_info); 1381 } 1382 1383 static int 1384 mlxsw_devlink_sb_pool_set(struct devlink *devlink, 1385 unsigned int sb_index, u16 pool_index, u32 size, 1386 enum devlink_sb_threshold_type threshold_type, 1387 struct netlink_ext_ack *extack) 1388 { 1389 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1390 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1391 1392 if (!mlxsw_driver->sb_pool_set) 1393 return -EOPNOTSUPP; 1394 return mlxsw_driver->sb_pool_set(mlxsw_core, sb_index, 1395 pool_index, size, threshold_type, 1396 extack); 1397 } 1398 1399 static int mlxsw_devlink_sb_port_pool_get(struct devlink_port *devlink_port, 1400 unsigned int sb_index, u16 pool_index, 1401 u32 *p_threshold) 1402 { 1403 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1404 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1405 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1406 1407 if (!mlxsw_driver->sb_port_pool_get || 1408 !mlxsw_core_port_check(mlxsw_core_port)) 1409 return -EOPNOTSUPP; 1410 return mlxsw_driver->sb_port_pool_get(mlxsw_core_port, sb_index, 1411 pool_index, p_threshold); 1412 } 1413 1414 static int mlxsw_devlink_sb_port_pool_set(struct devlink_port *devlink_port, 1415 unsigned int sb_index, u16 pool_index, 1416 u32 threshold, 1417 struct netlink_ext_ack *extack) 1418 { 1419 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1420 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1421 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1422 1423 if (!mlxsw_driver->sb_port_pool_set || 1424 !mlxsw_core_port_check(mlxsw_core_port)) 1425 return -EOPNOTSUPP; 1426 return mlxsw_driver->sb_port_pool_set(mlxsw_core_port, sb_index, 1427 pool_index, threshold, extack); 1428 } 1429 1430 static int 1431 mlxsw_devlink_sb_tc_pool_bind_get(struct devlink_port *devlink_port, 1432 unsigned int sb_index, u16 tc_index, 1433 enum devlink_sb_pool_type pool_type, 1434 u16 *p_pool_index, u32 *p_threshold) 1435 { 1436 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1437 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1438 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1439 1440 if (!mlxsw_driver->sb_tc_pool_bind_get || 1441 !mlxsw_core_port_check(mlxsw_core_port)) 1442 return -EOPNOTSUPP; 1443 return mlxsw_driver->sb_tc_pool_bind_get(mlxsw_core_port, sb_index, 1444 tc_index, pool_type, 1445 p_pool_index, p_threshold); 1446 } 1447 1448 static int 1449 mlxsw_devlink_sb_tc_pool_bind_set(struct devlink_port *devlink_port, 1450 unsigned int sb_index, u16 tc_index, 1451 enum devlink_sb_pool_type pool_type, 1452 u16 pool_index, u32 threshold, 1453 struct netlink_ext_ack *extack) 1454 { 1455 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1456 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1457 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1458 1459 if (!mlxsw_driver->sb_tc_pool_bind_set || 1460 !mlxsw_core_port_check(mlxsw_core_port)) 1461 return -EOPNOTSUPP; 1462 return mlxsw_driver->sb_tc_pool_bind_set(mlxsw_core_port, sb_index, 1463 tc_index, pool_type, 1464 pool_index, threshold, extack); 1465 } 1466 1467 static int mlxsw_devlink_sb_occ_snapshot(struct devlink *devlink, 1468 unsigned int sb_index) 1469 { 1470 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1471 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1472 1473 if (!mlxsw_driver->sb_occ_snapshot) 1474 return -EOPNOTSUPP; 1475 return mlxsw_driver->sb_occ_snapshot(mlxsw_core, sb_index); 1476 } 1477 1478 static int mlxsw_devlink_sb_occ_max_clear(struct devlink *devlink, 1479 unsigned int sb_index) 1480 { 1481 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1482 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1483 1484 if (!mlxsw_driver->sb_occ_max_clear) 1485 return -EOPNOTSUPP; 1486 return mlxsw_driver->sb_occ_max_clear(mlxsw_core, sb_index); 1487 } 1488 1489 static int 1490 mlxsw_devlink_sb_occ_port_pool_get(struct devlink_port *devlink_port, 1491 unsigned int sb_index, u16 pool_index, 1492 u32 *p_cur, u32 *p_max) 1493 { 1494 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1495 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1496 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1497 1498 if (!mlxsw_driver->sb_occ_port_pool_get || 1499 !mlxsw_core_port_check(mlxsw_core_port)) 1500 return -EOPNOTSUPP; 1501 return mlxsw_driver->sb_occ_port_pool_get(mlxsw_core_port, sb_index, 1502 pool_index, p_cur, p_max); 1503 } 1504 1505 static int 1506 mlxsw_devlink_sb_occ_tc_port_bind_get(struct devlink_port *devlink_port, 1507 unsigned int sb_index, u16 tc_index, 1508 enum devlink_sb_pool_type pool_type, 1509 u32 *p_cur, u32 *p_max) 1510 { 1511 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1512 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1513 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1514 1515 if (!mlxsw_driver->sb_occ_tc_port_bind_get || 1516 !mlxsw_core_port_check(mlxsw_core_port)) 1517 return -EOPNOTSUPP; 1518 return mlxsw_driver->sb_occ_tc_port_bind_get(mlxsw_core_port, 1519 sb_index, tc_index, 1520 pool_type, p_cur, p_max); 1521 } 1522 1523 static int 1524 mlxsw_devlink_info_get(struct devlink *devlink, struct devlink_info_req *req, 1525 struct netlink_ext_ack *extack) 1526 { 1527 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1528 char fw_info_psid[MLXSW_REG_MGIR_FW_INFO_PSID_SIZE]; 1529 u32 hw_rev, fw_major, fw_minor, fw_sub_minor; 1530 char mgir_pl[MLXSW_REG_MGIR_LEN]; 1531 char buf[32]; 1532 int err; 1533 1534 mlxsw_reg_mgir_pack(mgir_pl); 1535 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mgir), mgir_pl); 1536 if (err) 1537 return err; 1538 mlxsw_reg_mgir_unpack(mgir_pl, &hw_rev, fw_info_psid, &fw_major, 1539 &fw_minor, &fw_sub_minor); 1540 1541 sprintf(buf, "%X", hw_rev); 1542 err = devlink_info_version_fixed_put(req, "hw.revision", buf); 1543 if (err) 1544 return err; 1545 1546 err = devlink_info_version_fixed_put(req, 1547 DEVLINK_INFO_VERSION_GENERIC_FW_PSID, 1548 fw_info_psid); 1549 if (err) 1550 return err; 1551 1552 sprintf(buf, "%d.%d.%d", fw_major, fw_minor, fw_sub_minor); 1553 err = devlink_info_version_running_put(req, "fw.version", buf); 1554 if (err) 1555 return err; 1556 1557 return devlink_info_version_running_put(req, 1558 DEVLINK_INFO_VERSION_GENERIC_FW, 1559 buf); 1560 } 1561 1562 static int 1563 mlxsw_devlink_core_bus_device_reload_down(struct devlink *devlink, 1564 bool netns_change, enum devlink_reload_action action, 1565 enum devlink_reload_limit limit, 1566 struct netlink_ext_ack *extack) 1567 { 1568 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1569 1570 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_RESET)) 1571 return -EOPNOTSUPP; 1572 1573 mlxsw_core_bus_device_unregister(mlxsw_core, true); 1574 return 0; 1575 } 1576 1577 static int 1578 mlxsw_devlink_core_bus_device_reload_up(struct devlink *devlink, enum devlink_reload_action action, 1579 enum devlink_reload_limit limit, u32 *actions_performed, 1580 struct netlink_ext_ack *extack) 1581 { 1582 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1583 int err; 1584 1585 *actions_performed = BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT) | 1586 BIT(DEVLINK_RELOAD_ACTION_FW_ACTIVATE); 1587 err = mlxsw_core_bus_device_register(mlxsw_core->bus_info, 1588 mlxsw_core->bus, 1589 mlxsw_core->bus_priv, true, 1590 devlink, extack); 1591 return err; 1592 } 1593 1594 static int mlxsw_devlink_flash_update(struct devlink *devlink, 1595 struct devlink_flash_update_params *params, 1596 struct netlink_ext_ack *extack) 1597 { 1598 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1599 1600 return mlxsw_core_fw_flash_update(mlxsw_core, params, extack); 1601 } 1602 1603 static int mlxsw_devlink_trap_init(struct devlink *devlink, 1604 const struct devlink_trap *trap, 1605 void *trap_ctx) 1606 { 1607 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1608 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1609 1610 if (!mlxsw_driver->trap_init) 1611 return -EOPNOTSUPP; 1612 return mlxsw_driver->trap_init(mlxsw_core, trap, trap_ctx); 1613 } 1614 1615 static void mlxsw_devlink_trap_fini(struct devlink *devlink, 1616 const struct devlink_trap *trap, 1617 void *trap_ctx) 1618 { 1619 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1620 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1621 1622 if (!mlxsw_driver->trap_fini) 1623 return; 1624 mlxsw_driver->trap_fini(mlxsw_core, trap, trap_ctx); 1625 } 1626 1627 static int mlxsw_devlink_trap_action_set(struct devlink *devlink, 1628 const struct devlink_trap *trap, 1629 enum devlink_trap_action action, 1630 struct netlink_ext_ack *extack) 1631 { 1632 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1633 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1634 1635 if (!mlxsw_driver->trap_action_set) 1636 return -EOPNOTSUPP; 1637 return mlxsw_driver->trap_action_set(mlxsw_core, trap, action, extack); 1638 } 1639 1640 static int 1641 mlxsw_devlink_trap_group_init(struct devlink *devlink, 1642 const struct devlink_trap_group *group) 1643 { 1644 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1645 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1646 1647 if (!mlxsw_driver->trap_group_init) 1648 return -EOPNOTSUPP; 1649 return mlxsw_driver->trap_group_init(mlxsw_core, group); 1650 } 1651 1652 static int 1653 mlxsw_devlink_trap_group_set(struct devlink *devlink, 1654 const struct devlink_trap_group *group, 1655 const struct devlink_trap_policer *policer, 1656 struct netlink_ext_ack *extack) 1657 { 1658 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1659 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1660 1661 if (!mlxsw_driver->trap_group_set) 1662 return -EOPNOTSUPP; 1663 return mlxsw_driver->trap_group_set(mlxsw_core, group, policer, extack); 1664 } 1665 1666 static int 1667 mlxsw_devlink_trap_policer_init(struct devlink *devlink, 1668 const struct devlink_trap_policer *policer) 1669 { 1670 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1671 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1672 1673 if (!mlxsw_driver->trap_policer_init) 1674 return -EOPNOTSUPP; 1675 return mlxsw_driver->trap_policer_init(mlxsw_core, policer); 1676 } 1677 1678 static void 1679 mlxsw_devlink_trap_policer_fini(struct devlink *devlink, 1680 const struct devlink_trap_policer *policer) 1681 { 1682 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1683 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1684 1685 if (!mlxsw_driver->trap_policer_fini) 1686 return; 1687 mlxsw_driver->trap_policer_fini(mlxsw_core, policer); 1688 } 1689 1690 static int 1691 mlxsw_devlink_trap_policer_set(struct devlink *devlink, 1692 const struct devlink_trap_policer *policer, 1693 u64 rate, u64 burst, 1694 struct netlink_ext_ack *extack) 1695 { 1696 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1697 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1698 1699 if (!mlxsw_driver->trap_policer_set) 1700 return -EOPNOTSUPP; 1701 return mlxsw_driver->trap_policer_set(mlxsw_core, policer, rate, burst, 1702 extack); 1703 } 1704 1705 static int 1706 mlxsw_devlink_trap_policer_counter_get(struct devlink *devlink, 1707 const struct devlink_trap_policer *policer, 1708 u64 *p_drops) 1709 { 1710 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1711 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1712 1713 if (!mlxsw_driver->trap_policer_counter_get) 1714 return -EOPNOTSUPP; 1715 return mlxsw_driver->trap_policer_counter_get(mlxsw_core, policer, 1716 p_drops); 1717 } 1718 1719 static const struct devlink_ops mlxsw_devlink_ops = { 1720 .reload_actions = BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT) | 1721 BIT(DEVLINK_RELOAD_ACTION_FW_ACTIVATE), 1722 .reload_down = mlxsw_devlink_core_bus_device_reload_down, 1723 .reload_up = mlxsw_devlink_core_bus_device_reload_up, 1724 .port_split = mlxsw_devlink_port_split, 1725 .port_unsplit = mlxsw_devlink_port_unsplit, 1726 .sb_pool_get = mlxsw_devlink_sb_pool_get, 1727 .sb_pool_set = mlxsw_devlink_sb_pool_set, 1728 .sb_port_pool_get = mlxsw_devlink_sb_port_pool_get, 1729 .sb_port_pool_set = mlxsw_devlink_sb_port_pool_set, 1730 .sb_tc_pool_bind_get = mlxsw_devlink_sb_tc_pool_bind_get, 1731 .sb_tc_pool_bind_set = mlxsw_devlink_sb_tc_pool_bind_set, 1732 .sb_occ_snapshot = mlxsw_devlink_sb_occ_snapshot, 1733 .sb_occ_max_clear = mlxsw_devlink_sb_occ_max_clear, 1734 .sb_occ_port_pool_get = mlxsw_devlink_sb_occ_port_pool_get, 1735 .sb_occ_tc_port_bind_get = mlxsw_devlink_sb_occ_tc_port_bind_get, 1736 .info_get = mlxsw_devlink_info_get, 1737 .flash_update = mlxsw_devlink_flash_update, 1738 .trap_init = mlxsw_devlink_trap_init, 1739 .trap_fini = mlxsw_devlink_trap_fini, 1740 .trap_action_set = mlxsw_devlink_trap_action_set, 1741 .trap_group_init = mlxsw_devlink_trap_group_init, 1742 .trap_group_set = mlxsw_devlink_trap_group_set, 1743 .trap_policer_init = mlxsw_devlink_trap_policer_init, 1744 .trap_policer_fini = mlxsw_devlink_trap_policer_fini, 1745 .trap_policer_set = mlxsw_devlink_trap_policer_set, 1746 .trap_policer_counter_get = mlxsw_devlink_trap_policer_counter_get, 1747 }; 1748 1749 static int mlxsw_core_params_register(struct mlxsw_core *mlxsw_core) 1750 { 1751 int err; 1752 1753 err = mlxsw_core_fw_params_register(mlxsw_core); 1754 if (err) 1755 return err; 1756 1757 if (mlxsw_core->driver->params_register) { 1758 err = mlxsw_core->driver->params_register(mlxsw_core); 1759 if (err) 1760 goto err_params_register; 1761 } 1762 return 0; 1763 1764 err_params_register: 1765 mlxsw_core_fw_params_unregister(mlxsw_core); 1766 return err; 1767 } 1768 1769 static void mlxsw_core_params_unregister(struct mlxsw_core *mlxsw_core) 1770 { 1771 mlxsw_core_fw_params_unregister(mlxsw_core); 1772 if (mlxsw_core->driver->params_register) 1773 mlxsw_core->driver->params_unregister(mlxsw_core); 1774 } 1775 1776 struct mlxsw_core_health_event { 1777 struct mlxsw_core *mlxsw_core; 1778 char mfde_pl[MLXSW_REG_MFDE_LEN]; 1779 struct work_struct work; 1780 }; 1781 1782 static void mlxsw_core_health_event_work(struct work_struct *work) 1783 { 1784 struct mlxsw_core_health_event *event; 1785 struct mlxsw_core *mlxsw_core; 1786 1787 event = container_of(work, struct mlxsw_core_health_event, work); 1788 mlxsw_core = event->mlxsw_core; 1789 devlink_health_report(mlxsw_core->health.fw_fatal, "FW fatal event occurred", 1790 event->mfde_pl); 1791 kfree(event); 1792 } 1793 1794 static void mlxsw_core_health_listener_func(const struct mlxsw_reg_info *reg, 1795 char *mfde_pl, void *priv) 1796 { 1797 struct mlxsw_core_health_event *event; 1798 struct mlxsw_core *mlxsw_core = priv; 1799 1800 event = kmalloc(sizeof(*event), GFP_ATOMIC); 1801 if (!event) 1802 return; 1803 event->mlxsw_core = mlxsw_core; 1804 memcpy(event->mfde_pl, mfde_pl, sizeof(event->mfde_pl)); 1805 INIT_WORK(&event->work, mlxsw_core_health_event_work); 1806 mlxsw_core_schedule_work(&event->work); 1807 } 1808 1809 static const struct mlxsw_listener mlxsw_core_health_listener = 1810 MLXSW_CORE_EVENTL(mlxsw_core_health_listener_func, MFDE); 1811 1812 static int 1813 mlxsw_core_health_fw_fatal_dump_fatal_cause(const char *mfde_pl, 1814 struct devlink_fmsg *fmsg) 1815 { 1816 u32 val, tile_v; 1817 int err; 1818 1819 val = mlxsw_reg_mfde_fatal_cause_id_get(mfde_pl); 1820 err = devlink_fmsg_u32_pair_put(fmsg, "cause_id", val); 1821 if (err) 1822 return err; 1823 tile_v = mlxsw_reg_mfde_fatal_cause_tile_v_get(mfde_pl); 1824 if (tile_v) { 1825 val = mlxsw_reg_mfde_fatal_cause_tile_index_get(mfde_pl); 1826 err = devlink_fmsg_u8_pair_put(fmsg, "tile_index", val); 1827 if (err) 1828 return err; 1829 } 1830 1831 return 0; 1832 } 1833 1834 static int 1835 mlxsw_core_health_fw_fatal_dump_fw_assert(const char *mfde_pl, 1836 struct devlink_fmsg *fmsg) 1837 { 1838 u32 val, tile_v; 1839 int err; 1840 1841 val = mlxsw_reg_mfde_fw_assert_var0_get(mfde_pl); 1842 err = devlink_fmsg_u32_pair_put(fmsg, "var0", val); 1843 if (err) 1844 return err; 1845 val = mlxsw_reg_mfde_fw_assert_var1_get(mfde_pl); 1846 err = devlink_fmsg_u32_pair_put(fmsg, "var1", val); 1847 if (err) 1848 return err; 1849 val = mlxsw_reg_mfde_fw_assert_var2_get(mfde_pl); 1850 err = devlink_fmsg_u32_pair_put(fmsg, "var2", val); 1851 if (err) 1852 return err; 1853 val = mlxsw_reg_mfde_fw_assert_var3_get(mfde_pl); 1854 err = devlink_fmsg_u32_pair_put(fmsg, "var3", val); 1855 if (err) 1856 return err; 1857 val = mlxsw_reg_mfde_fw_assert_var4_get(mfde_pl); 1858 err = devlink_fmsg_u32_pair_put(fmsg, "var4", val); 1859 if (err) 1860 return err; 1861 val = mlxsw_reg_mfde_fw_assert_existptr_get(mfde_pl); 1862 err = devlink_fmsg_u32_pair_put(fmsg, "existptr", val); 1863 if (err) 1864 return err; 1865 val = mlxsw_reg_mfde_fw_assert_callra_get(mfde_pl); 1866 err = devlink_fmsg_u32_pair_put(fmsg, "callra", val); 1867 if (err) 1868 return err; 1869 val = mlxsw_reg_mfde_fw_assert_oe_get(mfde_pl); 1870 err = devlink_fmsg_bool_pair_put(fmsg, "old_event", val); 1871 if (err) 1872 return err; 1873 tile_v = mlxsw_reg_mfde_fw_assert_tile_v_get(mfde_pl); 1874 if (tile_v) { 1875 val = mlxsw_reg_mfde_fw_assert_tile_index_get(mfde_pl); 1876 err = devlink_fmsg_u8_pair_put(fmsg, "tile_index", val); 1877 if (err) 1878 return err; 1879 } 1880 val = mlxsw_reg_mfde_fw_assert_ext_synd_get(mfde_pl); 1881 err = devlink_fmsg_u32_pair_put(fmsg, "ext_synd", val); 1882 if (err) 1883 return err; 1884 1885 return 0; 1886 } 1887 1888 static int 1889 mlxsw_core_health_fw_fatal_dump_kvd_im_stop(const char *mfde_pl, 1890 struct devlink_fmsg *fmsg) 1891 { 1892 u32 val; 1893 int err; 1894 1895 val = mlxsw_reg_mfde_kvd_im_stop_oe_get(mfde_pl); 1896 err = devlink_fmsg_bool_pair_put(fmsg, "old_event", val); 1897 if (err) 1898 return err; 1899 val = mlxsw_reg_mfde_kvd_im_stop_pipes_mask_get(mfde_pl); 1900 return devlink_fmsg_u32_pair_put(fmsg, "pipes_mask", val); 1901 } 1902 1903 static int 1904 mlxsw_core_health_fw_fatal_dump_crspace_to(const char *mfde_pl, 1905 struct devlink_fmsg *fmsg) 1906 { 1907 u32 val; 1908 int err; 1909 1910 val = mlxsw_reg_mfde_crspace_to_log_address_get(mfde_pl); 1911 err = devlink_fmsg_u32_pair_put(fmsg, "log_address", val); 1912 if (err) 1913 return err; 1914 val = mlxsw_reg_mfde_crspace_to_oe_get(mfde_pl); 1915 err = devlink_fmsg_bool_pair_put(fmsg, "old_event", val); 1916 if (err) 1917 return err; 1918 val = mlxsw_reg_mfde_crspace_to_log_id_get(mfde_pl); 1919 err = devlink_fmsg_u8_pair_put(fmsg, "log_irisc_id", val); 1920 if (err) 1921 return err; 1922 val = mlxsw_reg_mfde_crspace_to_log_ip_get(mfde_pl); 1923 err = devlink_fmsg_u64_pair_put(fmsg, "log_ip", val); 1924 if (err) 1925 return err; 1926 1927 return 0; 1928 } 1929 1930 static int mlxsw_core_health_fw_fatal_dump(struct devlink_health_reporter *reporter, 1931 struct devlink_fmsg *fmsg, void *priv_ctx, 1932 struct netlink_ext_ack *extack) 1933 { 1934 char *mfde_pl = priv_ctx; 1935 char *val_str; 1936 u8 event_id; 1937 u32 val; 1938 int err; 1939 1940 if (!priv_ctx) 1941 /* User-triggered dumps are not possible */ 1942 return -EOPNOTSUPP; 1943 1944 val = mlxsw_reg_mfde_irisc_id_get(mfde_pl); 1945 err = devlink_fmsg_u8_pair_put(fmsg, "irisc_id", val); 1946 if (err) 1947 return err; 1948 err = devlink_fmsg_arr_pair_nest_start(fmsg, "event"); 1949 if (err) 1950 return err; 1951 1952 event_id = mlxsw_reg_mfde_event_id_get(mfde_pl); 1953 err = devlink_fmsg_u32_pair_put(fmsg, "id", event_id); 1954 if (err) 1955 return err; 1956 switch (event_id) { 1957 case MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO: 1958 val_str = "CR space timeout"; 1959 break; 1960 case MLXSW_REG_MFDE_EVENT_ID_KVD_IM_STOP: 1961 val_str = "KVD insertion machine stopped"; 1962 break; 1963 case MLXSW_REG_MFDE_EVENT_ID_TEST: 1964 val_str = "Test"; 1965 break; 1966 case MLXSW_REG_MFDE_EVENT_ID_FW_ASSERT: 1967 val_str = "FW assert"; 1968 break; 1969 case MLXSW_REG_MFDE_EVENT_ID_FATAL_CAUSE: 1970 val_str = "Fatal cause"; 1971 break; 1972 default: 1973 val_str = NULL; 1974 } 1975 if (val_str) { 1976 err = devlink_fmsg_string_pair_put(fmsg, "desc", val_str); 1977 if (err) 1978 return err; 1979 } 1980 1981 err = devlink_fmsg_arr_pair_nest_end(fmsg); 1982 if (err) 1983 return err; 1984 1985 err = devlink_fmsg_arr_pair_nest_start(fmsg, "severity"); 1986 if (err) 1987 return err; 1988 1989 val = mlxsw_reg_mfde_severity_get(mfde_pl); 1990 err = devlink_fmsg_u8_pair_put(fmsg, "id", val); 1991 if (err) 1992 return err; 1993 switch (val) { 1994 case MLXSW_REG_MFDE_SEVERITY_FATL: 1995 val_str = "Fatal"; 1996 break; 1997 case MLXSW_REG_MFDE_SEVERITY_NRML: 1998 val_str = "Normal"; 1999 break; 2000 case MLXSW_REG_MFDE_SEVERITY_INTR: 2001 val_str = "Debug"; 2002 break; 2003 default: 2004 val_str = NULL; 2005 } 2006 if (val_str) { 2007 err = devlink_fmsg_string_pair_put(fmsg, "desc", val_str); 2008 if (err) 2009 return err; 2010 } 2011 2012 err = devlink_fmsg_arr_pair_nest_end(fmsg); 2013 if (err) 2014 return err; 2015 2016 val = mlxsw_reg_mfde_method_get(mfde_pl); 2017 switch (val) { 2018 case MLXSW_REG_MFDE_METHOD_QUERY: 2019 val_str = "query"; 2020 break; 2021 case MLXSW_REG_MFDE_METHOD_WRITE: 2022 val_str = "write"; 2023 break; 2024 default: 2025 val_str = NULL; 2026 } 2027 if (val_str) { 2028 err = devlink_fmsg_string_pair_put(fmsg, "method", val_str); 2029 if (err) 2030 return err; 2031 } 2032 2033 val = mlxsw_reg_mfde_long_process_get(mfde_pl); 2034 err = devlink_fmsg_bool_pair_put(fmsg, "long_process", val); 2035 if (err) 2036 return err; 2037 2038 val = mlxsw_reg_mfde_command_type_get(mfde_pl); 2039 switch (val) { 2040 case MLXSW_REG_MFDE_COMMAND_TYPE_MAD: 2041 val_str = "mad"; 2042 break; 2043 case MLXSW_REG_MFDE_COMMAND_TYPE_EMAD: 2044 val_str = "emad"; 2045 break; 2046 case MLXSW_REG_MFDE_COMMAND_TYPE_CMDIF: 2047 val_str = "cmdif"; 2048 break; 2049 default: 2050 val_str = NULL; 2051 } 2052 if (val_str) { 2053 err = devlink_fmsg_string_pair_put(fmsg, "command_type", val_str); 2054 if (err) 2055 return err; 2056 } 2057 2058 val = mlxsw_reg_mfde_reg_attr_id_get(mfde_pl); 2059 err = devlink_fmsg_u32_pair_put(fmsg, "reg_attr_id", val); 2060 if (err) 2061 return err; 2062 2063 switch (event_id) { 2064 case MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO: 2065 return mlxsw_core_health_fw_fatal_dump_crspace_to(mfde_pl, 2066 fmsg); 2067 case MLXSW_REG_MFDE_EVENT_ID_KVD_IM_STOP: 2068 return mlxsw_core_health_fw_fatal_dump_kvd_im_stop(mfde_pl, 2069 fmsg); 2070 case MLXSW_REG_MFDE_EVENT_ID_FW_ASSERT: 2071 return mlxsw_core_health_fw_fatal_dump_fw_assert(mfde_pl, fmsg); 2072 case MLXSW_REG_MFDE_EVENT_ID_FATAL_CAUSE: 2073 return mlxsw_core_health_fw_fatal_dump_fatal_cause(mfde_pl, 2074 fmsg); 2075 } 2076 2077 return 0; 2078 } 2079 2080 static int 2081 mlxsw_core_health_fw_fatal_test(struct devlink_health_reporter *reporter, 2082 struct netlink_ext_ack *extack) 2083 { 2084 struct mlxsw_core *mlxsw_core = devlink_health_reporter_priv(reporter); 2085 char mfgd_pl[MLXSW_REG_MFGD_LEN]; 2086 int err; 2087 2088 /* Read the register first to make sure no other bits are changed. */ 2089 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mfgd), mfgd_pl); 2090 if (err) 2091 return err; 2092 mlxsw_reg_mfgd_trigger_test_set(mfgd_pl, true); 2093 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mfgd), mfgd_pl); 2094 } 2095 2096 static const struct devlink_health_reporter_ops 2097 mlxsw_core_health_fw_fatal_ops = { 2098 .name = "fw_fatal", 2099 .dump = mlxsw_core_health_fw_fatal_dump, 2100 .test = mlxsw_core_health_fw_fatal_test, 2101 }; 2102 2103 static int mlxsw_core_health_fw_fatal_config(struct mlxsw_core *mlxsw_core, 2104 bool enable) 2105 { 2106 char mfgd_pl[MLXSW_REG_MFGD_LEN]; 2107 int err; 2108 2109 /* Read the register first to make sure no other bits are changed. */ 2110 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mfgd), mfgd_pl); 2111 if (err) 2112 return err; 2113 mlxsw_reg_mfgd_fatal_event_mode_set(mfgd_pl, enable); 2114 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mfgd), mfgd_pl); 2115 } 2116 2117 static int mlxsw_core_health_init(struct mlxsw_core *mlxsw_core) 2118 { 2119 struct devlink *devlink = priv_to_devlink(mlxsw_core); 2120 struct devlink_health_reporter *fw_fatal; 2121 int err; 2122 2123 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_TXRX)) 2124 return 0; 2125 2126 fw_fatal = devl_health_reporter_create(devlink, &mlxsw_core_health_fw_fatal_ops, 2127 0, mlxsw_core); 2128 if (IS_ERR(fw_fatal)) { 2129 dev_err(mlxsw_core->bus_info->dev, "Failed to create fw fatal reporter"); 2130 return PTR_ERR(fw_fatal); 2131 } 2132 mlxsw_core->health.fw_fatal = fw_fatal; 2133 2134 err = mlxsw_core_trap_register(mlxsw_core, &mlxsw_core_health_listener, mlxsw_core); 2135 if (err) 2136 goto err_trap_register; 2137 2138 err = mlxsw_core_health_fw_fatal_config(mlxsw_core, true); 2139 if (err) 2140 goto err_fw_fatal_config; 2141 2142 return 0; 2143 2144 err_fw_fatal_config: 2145 mlxsw_core_trap_unregister(mlxsw_core, &mlxsw_core_health_listener, mlxsw_core); 2146 err_trap_register: 2147 devl_health_reporter_destroy(mlxsw_core->health.fw_fatal); 2148 return err; 2149 } 2150 2151 static void mlxsw_core_health_fini(struct mlxsw_core *mlxsw_core) 2152 { 2153 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_TXRX)) 2154 return; 2155 2156 mlxsw_core_health_fw_fatal_config(mlxsw_core, false); 2157 mlxsw_core_trap_unregister(mlxsw_core, &mlxsw_core_health_listener, mlxsw_core); 2158 /* Make sure there is no more event work scheduled */ 2159 mlxsw_core_flush_owq(); 2160 devl_health_reporter_destroy(mlxsw_core->health.fw_fatal); 2161 } 2162 2163 static void mlxsw_core_irq_event_handler_init(struct mlxsw_core *mlxsw_core) 2164 { 2165 INIT_LIST_HEAD(&mlxsw_core->irq_event_handler_list); 2166 mutex_init(&mlxsw_core->irq_event_handler_lock); 2167 } 2168 2169 static void mlxsw_core_irq_event_handler_fini(struct mlxsw_core *mlxsw_core) 2170 { 2171 mutex_destroy(&mlxsw_core->irq_event_handler_lock); 2172 WARN_ON(!list_empty(&mlxsw_core->irq_event_handler_list)); 2173 } 2174 2175 static int 2176 __mlxsw_core_bus_device_register(const struct mlxsw_bus_info *mlxsw_bus_info, 2177 const struct mlxsw_bus *mlxsw_bus, 2178 void *bus_priv, bool reload, 2179 struct devlink *devlink, 2180 struct netlink_ext_ack *extack) 2181 { 2182 const char *device_kind = mlxsw_bus_info->device_kind; 2183 struct mlxsw_core *mlxsw_core; 2184 struct mlxsw_driver *mlxsw_driver; 2185 size_t alloc_size; 2186 u16 max_lag; 2187 int err; 2188 2189 mlxsw_driver = mlxsw_core_driver_get(device_kind); 2190 if (!mlxsw_driver) 2191 return -EINVAL; 2192 2193 if (!reload) { 2194 alloc_size = sizeof(*mlxsw_core) + mlxsw_driver->priv_size; 2195 devlink = devlink_alloc(&mlxsw_devlink_ops, alloc_size, 2196 mlxsw_bus_info->dev); 2197 if (!devlink) { 2198 err = -ENOMEM; 2199 goto err_devlink_alloc; 2200 } 2201 devl_lock(devlink); 2202 } 2203 2204 mlxsw_core = devlink_priv(devlink); 2205 INIT_LIST_HEAD(&mlxsw_core->rx_listener_list); 2206 INIT_LIST_HEAD(&mlxsw_core->event_listener_list); 2207 mlxsw_core->driver = mlxsw_driver; 2208 mlxsw_core->bus = mlxsw_bus; 2209 mlxsw_core->bus_priv = bus_priv; 2210 mlxsw_core->bus_info = mlxsw_bus_info; 2211 mlxsw_core_irq_event_handler_init(mlxsw_core); 2212 2213 err = mlxsw_bus->init(bus_priv, mlxsw_core, mlxsw_driver->profile, 2214 &mlxsw_core->res); 2215 if (err) 2216 goto err_bus_init; 2217 2218 if (mlxsw_driver->resources_register && !reload) { 2219 err = mlxsw_driver->resources_register(mlxsw_core); 2220 if (err) 2221 goto err_register_resources; 2222 } 2223 2224 err = mlxsw_ports_init(mlxsw_core, reload); 2225 if (err) 2226 goto err_ports_init; 2227 2228 err = mlxsw_core_max_lag(mlxsw_core, &max_lag); 2229 if (!err && MLXSW_CORE_RES_VALID(mlxsw_core, MAX_LAG_MEMBERS)) { 2230 alloc_size = sizeof(*mlxsw_core->lag.mapping) * max_lag * 2231 MLXSW_CORE_RES_GET(mlxsw_core, MAX_LAG_MEMBERS); 2232 mlxsw_core->lag.mapping = kzalloc(alloc_size, GFP_KERNEL); 2233 if (!mlxsw_core->lag.mapping) { 2234 err = -ENOMEM; 2235 goto err_alloc_lag_mapping; 2236 } 2237 } 2238 2239 err = mlxsw_core_trap_groups_set(mlxsw_core); 2240 if (err) 2241 goto err_trap_groups_set; 2242 2243 err = mlxsw_emad_init(mlxsw_core); 2244 if (err) 2245 goto err_emad_init; 2246 2247 if (!reload) { 2248 err = mlxsw_core_params_register(mlxsw_core); 2249 if (err) 2250 goto err_register_params; 2251 } 2252 2253 err = mlxsw_core_fw_rev_validate(mlxsw_core, mlxsw_bus_info, mlxsw_driver->fw_req_rev, 2254 mlxsw_driver->fw_filename); 2255 if (err) 2256 goto err_fw_rev_validate; 2257 2258 err = mlxsw_linecards_init(mlxsw_core, mlxsw_bus_info); 2259 if (err) 2260 goto err_linecards_init; 2261 2262 err = mlxsw_core_health_init(mlxsw_core); 2263 if (err) 2264 goto err_health_init; 2265 2266 err = mlxsw_hwmon_init(mlxsw_core, mlxsw_bus_info, &mlxsw_core->hwmon); 2267 if (err) 2268 goto err_hwmon_init; 2269 2270 err = mlxsw_thermal_init(mlxsw_core, mlxsw_bus_info, 2271 &mlxsw_core->thermal); 2272 if (err) 2273 goto err_thermal_init; 2274 2275 err = mlxsw_env_init(mlxsw_core, mlxsw_bus_info, &mlxsw_core->env); 2276 if (err) 2277 goto err_env_init; 2278 2279 if (mlxsw_driver->init) { 2280 err = mlxsw_driver->init(mlxsw_core, mlxsw_bus_info, extack); 2281 if (err) 2282 goto err_driver_init; 2283 } 2284 2285 if (!reload) { 2286 devlink_set_features(devlink, DEVLINK_F_RELOAD); 2287 devl_unlock(devlink); 2288 devlink_register(devlink); 2289 } 2290 return 0; 2291 2292 err_driver_init: 2293 mlxsw_env_fini(mlxsw_core->env); 2294 err_env_init: 2295 mlxsw_thermal_fini(mlxsw_core->thermal); 2296 err_thermal_init: 2297 mlxsw_hwmon_fini(mlxsw_core->hwmon); 2298 err_hwmon_init: 2299 mlxsw_core_health_fini(mlxsw_core); 2300 err_health_init: 2301 mlxsw_linecards_fini(mlxsw_core); 2302 err_linecards_init: 2303 err_fw_rev_validate: 2304 if (!reload) 2305 mlxsw_core_params_unregister(mlxsw_core); 2306 err_register_params: 2307 mlxsw_emad_fini(mlxsw_core); 2308 err_emad_init: 2309 err_trap_groups_set: 2310 kfree(mlxsw_core->lag.mapping); 2311 err_alloc_lag_mapping: 2312 mlxsw_ports_fini(mlxsw_core, reload); 2313 err_ports_init: 2314 if (!reload) 2315 devl_resources_unregister(devlink); 2316 err_register_resources: 2317 mlxsw_bus->fini(bus_priv); 2318 err_bus_init: 2319 mlxsw_core_irq_event_handler_fini(mlxsw_core); 2320 if (!reload) { 2321 devl_unlock(devlink); 2322 devlink_free(devlink); 2323 } 2324 err_devlink_alloc: 2325 return err; 2326 } 2327 2328 int mlxsw_core_bus_device_register(const struct mlxsw_bus_info *mlxsw_bus_info, 2329 const struct mlxsw_bus *mlxsw_bus, 2330 void *bus_priv, bool reload, 2331 struct devlink *devlink, 2332 struct netlink_ext_ack *extack) 2333 { 2334 bool called_again = false; 2335 int err; 2336 2337 again: 2338 err = __mlxsw_core_bus_device_register(mlxsw_bus_info, mlxsw_bus, 2339 bus_priv, reload, 2340 devlink, extack); 2341 /* -EAGAIN is returned in case the FW was updated. FW needs 2342 * a reset, so lets try to call __mlxsw_core_bus_device_register() 2343 * again. 2344 */ 2345 if (err == -EAGAIN && !called_again) { 2346 called_again = true; 2347 goto again; 2348 } 2349 2350 return err; 2351 } 2352 EXPORT_SYMBOL(mlxsw_core_bus_device_register); 2353 2354 void mlxsw_core_bus_device_unregister(struct mlxsw_core *mlxsw_core, 2355 bool reload) 2356 { 2357 struct devlink *devlink = priv_to_devlink(mlxsw_core); 2358 2359 if (!reload) { 2360 devlink_unregister(devlink); 2361 devl_lock(devlink); 2362 } 2363 2364 if (devlink_is_reload_failed(devlink)) { 2365 if (!reload) 2366 /* Only the parts that were not de-initialized in the 2367 * failed reload attempt need to be de-initialized. 2368 */ 2369 goto reload_fail_deinit; 2370 else 2371 return; 2372 } 2373 2374 if (mlxsw_core->driver->fini) 2375 mlxsw_core->driver->fini(mlxsw_core); 2376 mlxsw_env_fini(mlxsw_core->env); 2377 mlxsw_thermal_fini(mlxsw_core->thermal); 2378 mlxsw_hwmon_fini(mlxsw_core->hwmon); 2379 mlxsw_core_health_fini(mlxsw_core); 2380 mlxsw_linecards_fini(mlxsw_core); 2381 if (!reload) 2382 mlxsw_core_params_unregister(mlxsw_core); 2383 mlxsw_emad_fini(mlxsw_core); 2384 kfree(mlxsw_core->lag.mapping); 2385 mlxsw_ports_fini(mlxsw_core, reload); 2386 if (!reload) 2387 devl_resources_unregister(devlink); 2388 mlxsw_core->bus->fini(mlxsw_core->bus_priv); 2389 mlxsw_core_irq_event_handler_fini(mlxsw_core); 2390 if (!reload) { 2391 devl_unlock(devlink); 2392 devlink_free(devlink); 2393 } 2394 2395 return; 2396 2397 reload_fail_deinit: 2398 mlxsw_core_params_unregister(mlxsw_core); 2399 devl_resources_unregister(devlink); 2400 devl_unlock(devlink); 2401 devlink_free(devlink); 2402 } 2403 EXPORT_SYMBOL(mlxsw_core_bus_device_unregister); 2404 2405 bool mlxsw_core_skb_transmit_busy(struct mlxsw_core *mlxsw_core, 2406 const struct mlxsw_tx_info *tx_info) 2407 { 2408 return mlxsw_core->bus->skb_transmit_busy(mlxsw_core->bus_priv, 2409 tx_info); 2410 } 2411 EXPORT_SYMBOL(mlxsw_core_skb_transmit_busy); 2412 2413 int mlxsw_core_skb_transmit(struct mlxsw_core *mlxsw_core, struct sk_buff *skb, 2414 const struct mlxsw_tx_info *tx_info) 2415 { 2416 return mlxsw_core->bus->skb_transmit(mlxsw_core->bus_priv, skb, 2417 tx_info); 2418 } 2419 EXPORT_SYMBOL(mlxsw_core_skb_transmit); 2420 2421 void mlxsw_core_ptp_transmitted(struct mlxsw_core *mlxsw_core, 2422 struct sk_buff *skb, u16 local_port) 2423 { 2424 if (mlxsw_core->driver->ptp_transmitted) 2425 mlxsw_core->driver->ptp_transmitted(mlxsw_core, skb, 2426 local_port); 2427 } 2428 EXPORT_SYMBOL(mlxsw_core_ptp_transmitted); 2429 2430 static bool __is_rx_listener_equal(const struct mlxsw_rx_listener *rxl_a, 2431 const struct mlxsw_rx_listener *rxl_b) 2432 { 2433 return (rxl_a->func == rxl_b->func && 2434 rxl_a->local_port == rxl_b->local_port && 2435 rxl_a->trap_id == rxl_b->trap_id && 2436 rxl_a->mirror_reason == rxl_b->mirror_reason); 2437 } 2438 2439 static struct mlxsw_rx_listener_item * 2440 __find_rx_listener_item(struct mlxsw_core *mlxsw_core, 2441 const struct mlxsw_rx_listener *rxl) 2442 { 2443 struct mlxsw_rx_listener_item *rxl_item; 2444 2445 list_for_each_entry(rxl_item, &mlxsw_core->rx_listener_list, list) { 2446 if (__is_rx_listener_equal(&rxl_item->rxl, rxl)) 2447 return rxl_item; 2448 } 2449 return NULL; 2450 } 2451 2452 int mlxsw_core_rx_listener_register(struct mlxsw_core *mlxsw_core, 2453 const struct mlxsw_rx_listener *rxl, 2454 void *priv, bool enabled) 2455 { 2456 struct mlxsw_rx_listener_item *rxl_item; 2457 2458 rxl_item = __find_rx_listener_item(mlxsw_core, rxl); 2459 if (rxl_item) 2460 return -EEXIST; 2461 rxl_item = kmalloc(sizeof(*rxl_item), GFP_KERNEL); 2462 if (!rxl_item) 2463 return -ENOMEM; 2464 rxl_item->rxl = *rxl; 2465 rxl_item->priv = priv; 2466 rxl_item->enabled = enabled; 2467 2468 list_add_rcu(&rxl_item->list, &mlxsw_core->rx_listener_list); 2469 return 0; 2470 } 2471 EXPORT_SYMBOL(mlxsw_core_rx_listener_register); 2472 2473 void mlxsw_core_rx_listener_unregister(struct mlxsw_core *mlxsw_core, 2474 const struct mlxsw_rx_listener *rxl) 2475 { 2476 struct mlxsw_rx_listener_item *rxl_item; 2477 2478 rxl_item = __find_rx_listener_item(mlxsw_core, rxl); 2479 if (!rxl_item) 2480 return; 2481 list_del_rcu(&rxl_item->list); 2482 synchronize_rcu(); 2483 kfree(rxl_item); 2484 } 2485 EXPORT_SYMBOL(mlxsw_core_rx_listener_unregister); 2486 2487 static void 2488 mlxsw_core_rx_listener_state_set(struct mlxsw_core *mlxsw_core, 2489 const struct mlxsw_rx_listener *rxl, 2490 bool enabled) 2491 { 2492 struct mlxsw_rx_listener_item *rxl_item; 2493 2494 rxl_item = __find_rx_listener_item(mlxsw_core, rxl); 2495 if (WARN_ON(!rxl_item)) 2496 return; 2497 rxl_item->enabled = enabled; 2498 } 2499 2500 static void mlxsw_core_event_listener_func(struct sk_buff *skb, u16 local_port, 2501 void *priv) 2502 { 2503 struct mlxsw_event_listener_item *event_listener_item = priv; 2504 struct mlxsw_core *mlxsw_core; 2505 struct mlxsw_reg_info reg; 2506 char *payload; 2507 char *reg_tlv; 2508 char *op_tlv; 2509 2510 mlxsw_core = event_listener_item->mlxsw_core; 2511 trace_devlink_hwmsg(priv_to_devlink(mlxsw_core), true, 0, 2512 skb->data, skb->len); 2513 2514 mlxsw_emad_tlv_parse(skb); 2515 op_tlv = mlxsw_emad_op_tlv(skb); 2516 reg_tlv = mlxsw_emad_reg_tlv(skb); 2517 2518 reg.id = mlxsw_emad_op_tlv_register_id_get(op_tlv); 2519 reg.len = (mlxsw_emad_reg_tlv_len_get(reg_tlv) - 1) * sizeof(u32); 2520 payload = mlxsw_emad_reg_payload(reg_tlv); 2521 event_listener_item->el.func(®, payload, event_listener_item->priv); 2522 dev_kfree_skb(skb); 2523 } 2524 2525 static bool __is_event_listener_equal(const struct mlxsw_event_listener *el_a, 2526 const struct mlxsw_event_listener *el_b) 2527 { 2528 return (el_a->func == el_b->func && 2529 el_a->trap_id == el_b->trap_id); 2530 } 2531 2532 static struct mlxsw_event_listener_item * 2533 __find_event_listener_item(struct mlxsw_core *mlxsw_core, 2534 const struct mlxsw_event_listener *el) 2535 { 2536 struct mlxsw_event_listener_item *el_item; 2537 2538 list_for_each_entry(el_item, &mlxsw_core->event_listener_list, list) { 2539 if (__is_event_listener_equal(&el_item->el, el)) 2540 return el_item; 2541 } 2542 return NULL; 2543 } 2544 2545 int mlxsw_core_event_listener_register(struct mlxsw_core *mlxsw_core, 2546 const struct mlxsw_event_listener *el, 2547 void *priv) 2548 { 2549 int err; 2550 struct mlxsw_event_listener_item *el_item; 2551 const struct mlxsw_rx_listener rxl = { 2552 .func = mlxsw_core_event_listener_func, 2553 .local_port = MLXSW_PORT_DONT_CARE, 2554 .trap_id = el->trap_id, 2555 }; 2556 2557 el_item = __find_event_listener_item(mlxsw_core, el); 2558 if (el_item) 2559 return -EEXIST; 2560 el_item = kmalloc(sizeof(*el_item), GFP_KERNEL); 2561 if (!el_item) 2562 return -ENOMEM; 2563 el_item->mlxsw_core = mlxsw_core; 2564 el_item->el = *el; 2565 el_item->priv = priv; 2566 2567 err = mlxsw_core_rx_listener_register(mlxsw_core, &rxl, el_item, true); 2568 if (err) 2569 goto err_rx_listener_register; 2570 2571 /* No reason to save item if we did not manage to register an RX 2572 * listener for it. 2573 */ 2574 list_add_rcu(&el_item->list, &mlxsw_core->event_listener_list); 2575 2576 return 0; 2577 2578 err_rx_listener_register: 2579 kfree(el_item); 2580 return err; 2581 } 2582 EXPORT_SYMBOL(mlxsw_core_event_listener_register); 2583 2584 void mlxsw_core_event_listener_unregister(struct mlxsw_core *mlxsw_core, 2585 const struct mlxsw_event_listener *el) 2586 { 2587 struct mlxsw_event_listener_item *el_item; 2588 const struct mlxsw_rx_listener rxl = { 2589 .func = mlxsw_core_event_listener_func, 2590 .local_port = MLXSW_PORT_DONT_CARE, 2591 .trap_id = el->trap_id, 2592 }; 2593 2594 el_item = __find_event_listener_item(mlxsw_core, el); 2595 if (!el_item) 2596 return; 2597 mlxsw_core_rx_listener_unregister(mlxsw_core, &rxl); 2598 list_del(&el_item->list); 2599 kfree(el_item); 2600 } 2601 EXPORT_SYMBOL(mlxsw_core_event_listener_unregister); 2602 2603 static int mlxsw_core_listener_register(struct mlxsw_core *mlxsw_core, 2604 const struct mlxsw_listener *listener, 2605 void *priv, bool enabled) 2606 { 2607 if (listener->is_event) { 2608 WARN_ON(!enabled); 2609 return mlxsw_core_event_listener_register(mlxsw_core, 2610 &listener->event_listener, 2611 priv); 2612 } else { 2613 return mlxsw_core_rx_listener_register(mlxsw_core, 2614 &listener->rx_listener, 2615 priv, enabled); 2616 } 2617 } 2618 2619 static void mlxsw_core_listener_unregister(struct mlxsw_core *mlxsw_core, 2620 const struct mlxsw_listener *listener, 2621 void *priv) 2622 { 2623 if (listener->is_event) 2624 mlxsw_core_event_listener_unregister(mlxsw_core, 2625 &listener->event_listener); 2626 else 2627 mlxsw_core_rx_listener_unregister(mlxsw_core, 2628 &listener->rx_listener); 2629 } 2630 2631 int mlxsw_core_trap_register(struct mlxsw_core *mlxsw_core, 2632 const struct mlxsw_listener *listener, void *priv) 2633 { 2634 enum mlxsw_reg_htgt_trap_group trap_group; 2635 enum mlxsw_reg_hpkt_action action; 2636 char hpkt_pl[MLXSW_REG_HPKT_LEN]; 2637 int err; 2638 2639 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_TXRX)) 2640 return 0; 2641 2642 err = mlxsw_core_listener_register(mlxsw_core, listener, priv, 2643 listener->enabled_on_register); 2644 if (err) 2645 return err; 2646 2647 action = listener->enabled_on_register ? listener->en_action : 2648 listener->dis_action; 2649 trap_group = listener->enabled_on_register ? listener->en_trap_group : 2650 listener->dis_trap_group; 2651 mlxsw_reg_hpkt_pack(hpkt_pl, action, listener->trap_id, 2652 trap_group, listener->is_ctrl); 2653 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(hpkt), hpkt_pl); 2654 if (err) 2655 goto err_trap_set; 2656 2657 return 0; 2658 2659 err_trap_set: 2660 mlxsw_core_listener_unregister(mlxsw_core, listener, priv); 2661 return err; 2662 } 2663 EXPORT_SYMBOL(mlxsw_core_trap_register); 2664 2665 void mlxsw_core_trap_unregister(struct mlxsw_core *mlxsw_core, 2666 const struct mlxsw_listener *listener, 2667 void *priv) 2668 { 2669 char hpkt_pl[MLXSW_REG_HPKT_LEN]; 2670 2671 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_TXRX)) 2672 return; 2673 2674 if (!listener->is_event) { 2675 mlxsw_reg_hpkt_pack(hpkt_pl, listener->dis_action, 2676 listener->trap_id, listener->dis_trap_group, 2677 listener->is_ctrl); 2678 mlxsw_reg_write(mlxsw_core, MLXSW_REG(hpkt), hpkt_pl); 2679 } 2680 2681 mlxsw_core_listener_unregister(mlxsw_core, listener, priv); 2682 } 2683 EXPORT_SYMBOL(mlxsw_core_trap_unregister); 2684 2685 int mlxsw_core_traps_register(struct mlxsw_core *mlxsw_core, 2686 const struct mlxsw_listener *listeners, 2687 size_t listeners_count, void *priv) 2688 { 2689 int i, err; 2690 2691 for (i = 0; i < listeners_count; i++) { 2692 err = mlxsw_core_trap_register(mlxsw_core, 2693 &listeners[i], 2694 priv); 2695 if (err) 2696 goto err_listener_register; 2697 } 2698 return 0; 2699 2700 err_listener_register: 2701 for (i--; i >= 0; i--) { 2702 mlxsw_core_trap_unregister(mlxsw_core, 2703 &listeners[i], 2704 priv); 2705 } 2706 return err; 2707 } 2708 EXPORT_SYMBOL(mlxsw_core_traps_register); 2709 2710 void mlxsw_core_traps_unregister(struct mlxsw_core *mlxsw_core, 2711 const struct mlxsw_listener *listeners, 2712 size_t listeners_count, void *priv) 2713 { 2714 int i; 2715 2716 for (i = 0; i < listeners_count; i++) { 2717 mlxsw_core_trap_unregister(mlxsw_core, 2718 &listeners[i], 2719 priv); 2720 } 2721 } 2722 EXPORT_SYMBOL(mlxsw_core_traps_unregister); 2723 2724 int mlxsw_core_trap_state_set(struct mlxsw_core *mlxsw_core, 2725 const struct mlxsw_listener *listener, 2726 bool enabled) 2727 { 2728 enum mlxsw_reg_htgt_trap_group trap_group; 2729 enum mlxsw_reg_hpkt_action action; 2730 char hpkt_pl[MLXSW_REG_HPKT_LEN]; 2731 int err; 2732 2733 /* Not supported for event listener */ 2734 if (WARN_ON(listener->is_event)) 2735 return -EINVAL; 2736 2737 action = enabled ? listener->en_action : listener->dis_action; 2738 trap_group = enabled ? listener->en_trap_group : 2739 listener->dis_trap_group; 2740 mlxsw_reg_hpkt_pack(hpkt_pl, action, listener->trap_id, 2741 trap_group, listener->is_ctrl); 2742 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(hpkt), hpkt_pl); 2743 if (err) 2744 return err; 2745 2746 mlxsw_core_rx_listener_state_set(mlxsw_core, &listener->rx_listener, 2747 enabled); 2748 return 0; 2749 } 2750 EXPORT_SYMBOL(mlxsw_core_trap_state_set); 2751 2752 static u64 mlxsw_core_tid_get(struct mlxsw_core *mlxsw_core) 2753 { 2754 return atomic64_inc_return(&mlxsw_core->emad.tid); 2755 } 2756 2757 static int mlxsw_core_reg_access_emad(struct mlxsw_core *mlxsw_core, 2758 const struct mlxsw_reg_info *reg, 2759 char *payload, 2760 enum mlxsw_core_reg_access_type type, 2761 struct list_head *bulk_list, 2762 mlxsw_reg_trans_cb_t *cb, 2763 unsigned long cb_priv) 2764 { 2765 u64 tid = mlxsw_core_tid_get(mlxsw_core); 2766 struct mlxsw_reg_trans *trans; 2767 int err; 2768 2769 trans = kzalloc(sizeof(*trans), GFP_KERNEL); 2770 if (!trans) 2771 return -ENOMEM; 2772 2773 err = mlxsw_emad_reg_access(mlxsw_core, reg, payload, type, trans, 2774 bulk_list, cb, cb_priv, tid); 2775 if (err) { 2776 kfree_rcu(trans, rcu); 2777 return err; 2778 } 2779 return 0; 2780 } 2781 2782 int mlxsw_reg_trans_query(struct mlxsw_core *mlxsw_core, 2783 const struct mlxsw_reg_info *reg, char *payload, 2784 struct list_head *bulk_list, 2785 mlxsw_reg_trans_cb_t *cb, unsigned long cb_priv) 2786 { 2787 return mlxsw_core_reg_access_emad(mlxsw_core, reg, payload, 2788 MLXSW_CORE_REG_ACCESS_TYPE_QUERY, 2789 bulk_list, cb, cb_priv); 2790 } 2791 EXPORT_SYMBOL(mlxsw_reg_trans_query); 2792 2793 int mlxsw_reg_trans_write(struct mlxsw_core *mlxsw_core, 2794 const struct mlxsw_reg_info *reg, char *payload, 2795 struct list_head *bulk_list, 2796 mlxsw_reg_trans_cb_t *cb, unsigned long cb_priv) 2797 { 2798 return mlxsw_core_reg_access_emad(mlxsw_core, reg, payload, 2799 MLXSW_CORE_REG_ACCESS_TYPE_WRITE, 2800 bulk_list, cb, cb_priv); 2801 } 2802 EXPORT_SYMBOL(mlxsw_reg_trans_write); 2803 2804 #define MLXSW_REG_TRANS_ERR_STRING_SIZE 256 2805 2806 static int mlxsw_reg_trans_wait(struct mlxsw_reg_trans *trans) 2807 { 2808 char err_string[MLXSW_REG_TRANS_ERR_STRING_SIZE]; 2809 struct mlxsw_core *mlxsw_core = trans->core; 2810 int err; 2811 2812 wait_for_completion(&trans->completion); 2813 cancel_delayed_work_sync(&trans->timeout_dw); 2814 err = trans->err; 2815 2816 if (trans->retries) 2817 dev_warn(mlxsw_core->bus_info->dev, "EMAD retries (%d/%d) (tid=%llx)\n", 2818 trans->retries, MLXSW_EMAD_MAX_RETRY, trans->tid); 2819 if (err) { 2820 dev_err(mlxsw_core->bus_info->dev, "EMAD reg access failed (tid=%llx,reg_id=%x(%s),type=%s,status=%x(%s))\n", 2821 trans->tid, trans->reg->id, 2822 mlxsw_reg_id_str(trans->reg->id), 2823 mlxsw_core_reg_access_type_str(trans->type), 2824 trans->emad_status, 2825 mlxsw_emad_op_tlv_status_str(trans->emad_status)); 2826 2827 snprintf(err_string, MLXSW_REG_TRANS_ERR_STRING_SIZE, 2828 "(tid=%llx,reg_id=%x(%s)) %s (%s)\n", trans->tid, 2829 trans->reg->id, mlxsw_reg_id_str(trans->reg->id), 2830 mlxsw_emad_op_tlv_status_str(trans->emad_status), 2831 trans->emad_err_string ? trans->emad_err_string : ""); 2832 2833 trace_devlink_hwerr(priv_to_devlink(mlxsw_core), 2834 trans->emad_status, err_string); 2835 2836 kfree(trans->emad_err_string); 2837 } 2838 2839 list_del(&trans->bulk_list); 2840 kfree_rcu(trans, rcu); 2841 return err; 2842 } 2843 2844 int mlxsw_reg_trans_bulk_wait(struct list_head *bulk_list) 2845 { 2846 struct mlxsw_reg_trans *trans; 2847 struct mlxsw_reg_trans *tmp; 2848 int sum_err = 0; 2849 int err; 2850 2851 list_for_each_entry_safe(trans, tmp, bulk_list, bulk_list) { 2852 err = mlxsw_reg_trans_wait(trans); 2853 if (err && sum_err == 0) 2854 sum_err = err; /* first error to be returned */ 2855 } 2856 return sum_err; 2857 } 2858 EXPORT_SYMBOL(mlxsw_reg_trans_bulk_wait); 2859 2860 struct mlxsw_core_irq_event_handler_item { 2861 struct list_head list; 2862 void (*cb)(struct mlxsw_core *mlxsw_core); 2863 }; 2864 2865 int mlxsw_core_irq_event_handler_register(struct mlxsw_core *mlxsw_core, 2866 mlxsw_irq_event_cb_t cb) 2867 { 2868 struct mlxsw_core_irq_event_handler_item *item; 2869 2870 item = kzalloc(sizeof(*item), GFP_KERNEL); 2871 if (!item) 2872 return -ENOMEM; 2873 item->cb = cb; 2874 mutex_lock(&mlxsw_core->irq_event_handler_lock); 2875 list_add_tail(&item->list, &mlxsw_core->irq_event_handler_list); 2876 mutex_unlock(&mlxsw_core->irq_event_handler_lock); 2877 return 0; 2878 } 2879 EXPORT_SYMBOL(mlxsw_core_irq_event_handler_register); 2880 2881 void mlxsw_core_irq_event_handler_unregister(struct mlxsw_core *mlxsw_core, 2882 mlxsw_irq_event_cb_t cb) 2883 { 2884 struct mlxsw_core_irq_event_handler_item *item, *tmp; 2885 2886 mutex_lock(&mlxsw_core->irq_event_handler_lock); 2887 list_for_each_entry_safe(item, tmp, 2888 &mlxsw_core->irq_event_handler_list, list) { 2889 if (item->cb == cb) { 2890 list_del(&item->list); 2891 kfree(item); 2892 } 2893 } 2894 mutex_unlock(&mlxsw_core->irq_event_handler_lock); 2895 } 2896 EXPORT_SYMBOL(mlxsw_core_irq_event_handler_unregister); 2897 2898 void mlxsw_core_irq_event_handlers_call(struct mlxsw_core *mlxsw_core) 2899 { 2900 struct mlxsw_core_irq_event_handler_item *item; 2901 2902 mutex_lock(&mlxsw_core->irq_event_handler_lock); 2903 list_for_each_entry(item, &mlxsw_core->irq_event_handler_list, list) { 2904 if (item->cb) 2905 item->cb(mlxsw_core); 2906 } 2907 mutex_unlock(&mlxsw_core->irq_event_handler_lock); 2908 } 2909 EXPORT_SYMBOL(mlxsw_core_irq_event_handlers_call); 2910 2911 static int mlxsw_core_reg_access_cmd(struct mlxsw_core *mlxsw_core, 2912 const struct mlxsw_reg_info *reg, 2913 char *payload, 2914 enum mlxsw_core_reg_access_type type) 2915 { 2916 enum mlxsw_emad_op_tlv_status status; 2917 int err, n_retry; 2918 bool reset_ok; 2919 char *in_mbox, *out_mbox, *tmp; 2920 2921 dev_dbg(mlxsw_core->bus_info->dev, "Reg cmd access (reg_id=%x(%s),type=%s)\n", 2922 reg->id, mlxsw_reg_id_str(reg->id), 2923 mlxsw_core_reg_access_type_str(type)); 2924 2925 in_mbox = mlxsw_cmd_mbox_alloc(); 2926 if (!in_mbox) 2927 return -ENOMEM; 2928 2929 out_mbox = mlxsw_cmd_mbox_alloc(); 2930 if (!out_mbox) { 2931 err = -ENOMEM; 2932 goto free_in_mbox; 2933 } 2934 2935 mlxsw_emad_pack_op_tlv(in_mbox, reg, type, 2936 mlxsw_core_tid_get(mlxsw_core)); 2937 tmp = in_mbox + MLXSW_EMAD_OP_TLV_LEN * sizeof(u32); 2938 mlxsw_emad_pack_reg_tlv(tmp, reg, payload); 2939 2940 /* There is a special treatment needed for MRSR (reset) register. 2941 * The command interface will return error after the command 2942 * is executed, so tell the lower layer to expect it 2943 * and cope accordingly. 2944 */ 2945 reset_ok = reg->id == MLXSW_REG_MRSR_ID; 2946 2947 n_retry = 0; 2948 retry: 2949 err = mlxsw_cmd_access_reg(mlxsw_core, reset_ok, in_mbox, out_mbox); 2950 if (!err) { 2951 err = mlxsw_emad_process_status(out_mbox, &status); 2952 if (err) { 2953 if (err == -EAGAIN && n_retry++ < MLXSW_EMAD_MAX_RETRY) 2954 goto retry; 2955 dev_err(mlxsw_core->bus_info->dev, "Reg cmd access status failed (status=%x(%s))\n", 2956 status, mlxsw_emad_op_tlv_status_str(status)); 2957 } 2958 } 2959 2960 if (!err) 2961 memcpy(payload, mlxsw_emad_reg_payload_cmd(out_mbox), 2962 reg->len); 2963 2964 mlxsw_cmd_mbox_free(out_mbox); 2965 free_in_mbox: 2966 mlxsw_cmd_mbox_free(in_mbox); 2967 if (err) 2968 dev_err(mlxsw_core->bus_info->dev, "Reg cmd access failed (reg_id=%x(%s),type=%s)\n", 2969 reg->id, mlxsw_reg_id_str(reg->id), 2970 mlxsw_core_reg_access_type_str(type)); 2971 return err; 2972 } 2973 2974 static void mlxsw_core_reg_access_cb(struct mlxsw_core *mlxsw_core, 2975 char *payload, size_t payload_len, 2976 unsigned long cb_priv) 2977 { 2978 char *orig_payload = (char *) cb_priv; 2979 2980 memcpy(orig_payload, payload, payload_len); 2981 } 2982 2983 static int mlxsw_core_reg_access(struct mlxsw_core *mlxsw_core, 2984 const struct mlxsw_reg_info *reg, 2985 char *payload, 2986 enum mlxsw_core_reg_access_type type) 2987 { 2988 LIST_HEAD(bulk_list); 2989 int err; 2990 2991 /* During initialization EMAD interface is not available to us, 2992 * so we default to command interface. We switch to EMAD interface 2993 * after setting the appropriate traps. 2994 */ 2995 if (!mlxsw_core->emad.use_emad) 2996 return mlxsw_core_reg_access_cmd(mlxsw_core, reg, 2997 payload, type); 2998 2999 err = mlxsw_core_reg_access_emad(mlxsw_core, reg, 3000 payload, type, &bulk_list, 3001 mlxsw_core_reg_access_cb, 3002 (unsigned long) payload); 3003 if (err) 3004 return err; 3005 return mlxsw_reg_trans_bulk_wait(&bulk_list); 3006 } 3007 3008 int mlxsw_reg_query(struct mlxsw_core *mlxsw_core, 3009 const struct mlxsw_reg_info *reg, char *payload) 3010 { 3011 return mlxsw_core_reg_access(mlxsw_core, reg, payload, 3012 MLXSW_CORE_REG_ACCESS_TYPE_QUERY); 3013 } 3014 EXPORT_SYMBOL(mlxsw_reg_query); 3015 3016 int mlxsw_reg_write(struct mlxsw_core *mlxsw_core, 3017 const struct mlxsw_reg_info *reg, char *payload) 3018 { 3019 return mlxsw_core_reg_access(mlxsw_core, reg, payload, 3020 MLXSW_CORE_REG_ACCESS_TYPE_WRITE); 3021 } 3022 EXPORT_SYMBOL(mlxsw_reg_write); 3023 3024 void mlxsw_core_skb_receive(struct mlxsw_core *mlxsw_core, struct sk_buff *skb, 3025 struct mlxsw_rx_info *rx_info) 3026 { 3027 struct mlxsw_rx_listener_item *rxl_item; 3028 const struct mlxsw_rx_listener *rxl; 3029 u16 local_port; 3030 bool found = false; 3031 3032 if (rx_info->is_lag) { 3033 dev_dbg_ratelimited(mlxsw_core->bus_info->dev, "%s: lag_id = %d, lag_port_index = 0x%x\n", 3034 __func__, rx_info->u.lag_id, 3035 rx_info->trap_id); 3036 /* Upper layer does not care if the skb came from LAG or not, 3037 * so just get the local_port for the lag port and push it up. 3038 */ 3039 local_port = mlxsw_core_lag_mapping_get(mlxsw_core, 3040 rx_info->u.lag_id, 3041 rx_info->lag_port_index); 3042 } else { 3043 local_port = rx_info->u.sys_port; 3044 } 3045 3046 dev_dbg_ratelimited(mlxsw_core->bus_info->dev, "%s: local_port = %d, trap_id = 0x%x\n", 3047 __func__, local_port, rx_info->trap_id); 3048 3049 if ((rx_info->trap_id >= MLXSW_TRAP_ID_MAX) || 3050 (local_port >= mlxsw_core->max_ports)) 3051 goto drop; 3052 3053 rcu_read_lock(); 3054 list_for_each_entry_rcu(rxl_item, &mlxsw_core->rx_listener_list, list) { 3055 rxl = &rxl_item->rxl; 3056 if ((rxl->local_port == MLXSW_PORT_DONT_CARE || 3057 rxl->local_port == local_port) && 3058 rxl->trap_id == rx_info->trap_id && 3059 rxl->mirror_reason == rx_info->mirror_reason) { 3060 if (rxl_item->enabled) 3061 found = true; 3062 break; 3063 } 3064 } 3065 if (!found) { 3066 rcu_read_unlock(); 3067 goto drop; 3068 } 3069 3070 rxl->func(skb, local_port, rxl_item->priv); 3071 rcu_read_unlock(); 3072 return; 3073 3074 drop: 3075 dev_kfree_skb(skb); 3076 } 3077 EXPORT_SYMBOL(mlxsw_core_skb_receive); 3078 3079 static int mlxsw_core_lag_mapping_index(struct mlxsw_core *mlxsw_core, 3080 u16 lag_id, u8 port_index) 3081 { 3082 return MLXSW_CORE_RES_GET(mlxsw_core, MAX_LAG_MEMBERS) * lag_id + 3083 port_index; 3084 } 3085 3086 void mlxsw_core_lag_mapping_set(struct mlxsw_core *mlxsw_core, 3087 u16 lag_id, u8 port_index, u16 local_port) 3088 { 3089 int index = mlxsw_core_lag_mapping_index(mlxsw_core, 3090 lag_id, port_index); 3091 3092 mlxsw_core->lag.mapping[index] = local_port; 3093 } 3094 EXPORT_SYMBOL(mlxsw_core_lag_mapping_set); 3095 3096 u16 mlxsw_core_lag_mapping_get(struct mlxsw_core *mlxsw_core, 3097 u16 lag_id, u8 port_index) 3098 { 3099 int index = mlxsw_core_lag_mapping_index(mlxsw_core, 3100 lag_id, port_index); 3101 3102 return mlxsw_core->lag.mapping[index]; 3103 } 3104 EXPORT_SYMBOL(mlxsw_core_lag_mapping_get); 3105 3106 void mlxsw_core_lag_mapping_clear(struct mlxsw_core *mlxsw_core, 3107 u16 lag_id, u16 local_port) 3108 { 3109 int i; 3110 3111 for (i = 0; i < MLXSW_CORE_RES_GET(mlxsw_core, MAX_LAG_MEMBERS); i++) { 3112 int index = mlxsw_core_lag_mapping_index(mlxsw_core, 3113 lag_id, i); 3114 3115 if (mlxsw_core->lag.mapping[index] == local_port) 3116 mlxsw_core->lag.mapping[index] = 0; 3117 } 3118 } 3119 EXPORT_SYMBOL(mlxsw_core_lag_mapping_clear); 3120 3121 bool mlxsw_core_res_valid(struct mlxsw_core *mlxsw_core, 3122 enum mlxsw_res_id res_id) 3123 { 3124 return mlxsw_res_valid(&mlxsw_core->res, res_id); 3125 } 3126 EXPORT_SYMBOL(mlxsw_core_res_valid); 3127 3128 u64 mlxsw_core_res_get(struct mlxsw_core *mlxsw_core, 3129 enum mlxsw_res_id res_id) 3130 { 3131 return mlxsw_res_get(&mlxsw_core->res, res_id); 3132 } 3133 EXPORT_SYMBOL(mlxsw_core_res_get); 3134 3135 static int __mlxsw_core_port_init(struct mlxsw_core *mlxsw_core, u16 local_port, 3136 enum devlink_port_flavour flavour, 3137 u8 slot_index, u32 port_number, bool split, 3138 u32 split_port_subnumber, 3139 bool splittable, u32 lanes, 3140 const unsigned char *switch_id, 3141 unsigned char switch_id_len) 3142 { 3143 struct devlink *devlink = priv_to_devlink(mlxsw_core); 3144 struct mlxsw_core_port *mlxsw_core_port = 3145 &mlxsw_core->ports[local_port]; 3146 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 3147 struct devlink_port_attrs attrs = {}; 3148 int err; 3149 3150 attrs.split = split; 3151 attrs.lanes = lanes; 3152 attrs.splittable = splittable; 3153 attrs.flavour = flavour; 3154 attrs.phys.port_number = port_number; 3155 attrs.phys.split_subport_number = split_port_subnumber; 3156 memcpy(attrs.switch_id.id, switch_id, switch_id_len); 3157 attrs.switch_id.id_len = switch_id_len; 3158 mlxsw_core_port->local_port = local_port; 3159 devlink_port_attrs_set(devlink_port, &attrs); 3160 if (slot_index) { 3161 struct mlxsw_linecard *linecard; 3162 3163 linecard = mlxsw_linecard_get(mlxsw_core->linecards, 3164 slot_index); 3165 mlxsw_core_port->linecard = linecard; 3166 devlink_port_linecard_set(devlink_port, 3167 linecard->devlink_linecard); 3168 } 3169 err = devl_port_register(devlink, devlink_port, local_port); 3170 if (err) 3171 memset(mlxsw_core_port, 0, sizeof(*mlxsw_core_port)); 3172 return err; 3173 } 3174 3175 static void __mlxsw_core_port_fini(struct mlxsw_core *mlxsw_core, u16 local_port) 3176 { 3177 struct mlxsw_core_port *mlxsw_core_port = 3178 &mlxsw_core->ports[local_port]; 3179 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 3180 3181 devl_port_unregister(devlink_port); 3182 memset(mlxsw_core_port, 0, sizeof(*mlxsw_core_port)); 3183 } 3184 3185 int mlxsw_core_port_init(struct mlxsw_core *mlxsw_core, u16 local_port, 3186 u8 slot_index, u32 port_number, bool split, 3187 u32 split_port_subnumber, 3188 bool splittable, u32 lanes, 3189 const unsigned char *switch_id, 3190 unsigned char switch_id_len) 3191 { 3192 int err; 3193 3194 err = __mlxsw_core_port_init(mlxsw_core, local_port, 3195 DEVLINK_PORT_FLAVOUR_PHYSICAL, slot_index, 3196 port_number, split, split_port_subnumber, 3197 splittable, lanes, 3198 switch_id, switch_id_len); 3199 if (err) 3200 return err; 3201 3202 atomic_inc(&mlxsw_core->active_ports_count); 3203 return 0; 3204 } 3205 EXPORT_SYMBOL(mlxsw_core_port_init); 3206 3207 void mlxsw_core_port_fini(struct mlxsw_core *mlxsw_core, u16 local_port) 3208 { 3209 atomic_dec(&mlxsw_core->active_ports_count); 3210 3211 __mlxsw_core_port_fini(mlxsw_core, local_port); 3212 } 3213 EXPORT_SYMBOL(mlxsw_core_port_fini); 3214 3215 int mlxsw_core_cpu_port_init(struct mlxsw_core *mlxsw_core, 3216 void *port_driver_priv, 3217 const unsigned char *switch_id, 3218 unsigned char switch_id_len) 3219 { 3220 struct mlxsw_core_port *mlxsw_core_port = 3221 &mlxsw_core->ports[MLXSW_PORT_CPU_PORT]; 3222 int err; 3223 3224 err = __mlxsw_core_port_init(mlxsw_core, MLXSW_PORT_CPU_PORT, 3225 DEVLINK_PORT_FLAVOUR_CPU, 3226 0, 0, false, 0, false, 0, 3227 switch_id, switch_id_len); 3228 if (err) 3229 return err; 3230 3231 mlxsw_core_port->port_driver_priv = port_driver_priv; 3232 return 0; 3233 } 3234 EXPORT_SYMBOL(mlxsw_core_cpu_port_init); 3235 3236 void mlxsw_core_cpu_port_fini(struct mlxsw_core *mlxsw_core) 3237 { 3238 __mlxsw_core_port_fini(mlxsw_core, MLXSW_PORT_CPU_PORT); 3239 } 3240 EXPORT_SYMBOL(mlxsw_core_cpu_port_fini); 3241 3242 void mlxsw_core_port_netdev_link(struct mlxsw_core *mlxsw_core, u16 local_port, 3243 void *port_driver_priv, struct net_device *dev) 3244 { 3245 struct mlxsw_core_port *mlxsw_core_port = 3246 &mlxsw_core->ports[local_port]; 3247 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 3248 3249 mlxsw_core_port->port_driver_priv = port_driver_priv; 3250 SET_NETDEV_DEVLINK_PORT(dev, devlink_port); 3251 } 3252 EXPORT_SYMBOL(mlxsw_core_port_netdev_link); 3253 3254 struct devlink_port * 3255 mlxsw_core_port_devlink_port_get(struct mlxsw_core *mlxsw_core, 3256 u16 local_port) 3257 { 3258 struct mlxsw_core_port *mlxsw_core_port = 3259 &mlxsw_core->ports[local_port]; 3260 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 3261 3262 return devlink_port; 3263 } 3264 EXPORT_SYMBOL(mlxsw_core_port_devlink_port_get); 3265 3266 struct mlxsw_linecard * 3267 mlxsw_core_port_linecard_get(struct mlxsw_core *mlxsw_core, 3268 u16 local_port) 3269 { 3270 struct mlxsw_core_port *mlxsw_core_port = 3271 &mlxsw_core->ports[local_port]; 3272 3273 return mlxsw_core_port->linecard; 3274 } 3275 3276 void mlxsw_core_ports_remove_selected(struct mlxsw_core *mlxsw_core, 3277 bool (*selector)(void *priv, u16 local_port), 3278 void *priv) 3279 { 3280 if (WARN_ON_ONCE(!mlxsw_core->driver->ports_remove_selected)) 3281 return; 3282 mlxsw_core->driver->ports_remove_selected(mlxsw_core, selector, priv); 3283 } 3284 3285 struct mlxsw_env *mlxsw_core_env(const struct mlxsw_core *mlxsw_core) 3286 { 3287 return mlxsw_core->env; 3288 } 3289 3290 static void mlxsw_core_buf_dump_dbg(struct mlxsw_core *mlxsw_core, 3291 const char *buf, size_t size) 3292 { 3293 __be32 *m = (__be32 *) buf; 3294 int i; 3295 int count = size / sizeof(__be32); 3296 3297 for (i = count - 1; i >= 0; i--) 3298 if (m[i]) 3299 break; 3300 i++; 3301 count = i ? i : 1; 3302 for (i = 0; i < count; i += 4) 3303 dev_dbg(mlxsw_core->bus_info->dev, "%04x - %08x %08x %08x %08x\n", 3304 i * 4, be32_to_cpu(m[i]), be32_to_cpu(m[i + 1]), 3305 be32_to_cpu(m[i + 2]), be32_to_cpu(m[i + 3])); 3306 } 3307 3308 int mlxsw_cmd_exec(struct mlxsw_core *mlxsw_core, u16 opcode, u8 opcode_mod, 3309 u32 in_mod, bool out_mbox_direct, bool reset_ok, 3310 char *in_mbox, size_t in_mbox_size, 3311 char *out_mbox, size_t out_mbox_size) 3312 { 3313 u8 status; 3314 int err; 3315 3316 BUG_ON(in_mbox_size % sizeof(u32) || out_mbox_size % sizeof(u32)); 3317 if (!mlxsw_core->bus->cmd_exec) 3318 return -EOPNOTSUPP; 3319 3320 dev_dbg(mlxsw_core->bus_info->dev, "Cmd exec (opcode=%x(%s),opcode_mod=%x,in_mod=%x)\n", 3321 opcode, mlxsw_cmd_opcode_str(opcode), opcode_mod, in_mod); 3322 if (in_mbox) { 3323 dev_dbg(mlxsw_core->bus_info->dev, "Input mailbox:\n"); 3324 mlxsw_core_buf_dump_dbg(mlxsw_core, in_mbox, in_mbox_size); 3325 } 3326 3327 err = mlxsw_core->bus->cmd_exec(mlxsw_core->bus_priv, opcode, 3328 opcode_mod, in_mod, out_mbox_direct, 3329 in_mbox, in_mbox_size, 3330 out_mbox, out_mbox_size, &status); 3331 3332 if (!err && out_mbox) { 3333 dev_dbg(mlxsw_core->bus_info->dev, "Output mailbox:\n"); 3334 mlxsw_core_buf_dump_dbg(mlxsw_core, out_mbox, out_mbox_size); 3335 } 3336 3337 if (reset_ok && err == -EIO && 3338 status == MLXSW_CMD_STATUS_RUNNING_RESET) { 3339 err = 0; 3340 } else if (err == -EIO && status != MLXSW_CMD_STATUS_OK) { 3341 dev_err(mlxsw_core->bus_info->dev, "Cmd exec failed (opcode=%x(%s),opcode_mod=%x,in_mod=%x,status=%x(%s))\n", 3342 opcode, mlxsw_cmd_opcode_str(opcode), opcode_mod, 3343 in_mod, status, mlxsw_cmd_status_str(status)); 3344 } else if (err == -ETIMEDOUT) { 3345 dev_err(mlxsw_core->bus_info->dev, "Cmd exec timed-out (opcode=%x(%s),opcode_mod=%x,in_mod=%x)\n", 3346 opcode, mlxsw_cmd_opcode_str(opcode), opcode_mod, 3347 in_mod); 3348 } 3349 3350 return err; 3351 } 3352 EXPORT_SYMBOL(mlxsw_cmd_exec); 3353 3354 int mlxsw_core_schedule_dw(struct delayed_work *dwork, unsigned long delay) 3355 { 3356 return queue_delayed_work(mlxsw_wq, dwork, delay); 3357 } 3358 EXPORT_SYMBOL(mlxsw_core_schedule_dw); 3359 3360 bool mlxsw_core_schedule_work(struct work_struct *work) 3361 { 3362 return queue_work(mlxsw_owq, work); 3363 } 3364 EXPORT_SYMBOL(mlxsw_core_schedule_work); 3365 3366 void mlxsw_core_flush_owq(void) 3367 { 3368 flush_workqueue(mlxsw_owq); 3369 } 3370 EXPORT_SYMBOL(mlxsw_core_flush_owq); 3371 3372 int mlxsw_core_kvd_sizes_get(struct mlxsw_core *mlxsw_core, 3373 const struct mlxsw_config_profile *profile, 3374 u64 *p_single_size, u64 *p_double_size, 3375 u64 *p_linear_size) 3376 { 3377 struct mlxsw_driver *driver = mlxsw_core->driver; 3378 3379 if (!driver->kvd_sizes_get) 3380 return -EINVAL; 3381 3382 return driver->kvd_sizes_get(mlxsw_core, profile, 3383 p_single_size, p_double_size, 3384 p_linear_size); 3385 } 3386 EXPORT_SYMBOL(mlxsw_core_kvd_sizes_get); 3387 3388 int mlxsw_core_resources_query(struct mlxsw_core *mlxsw_core, char *mbox, 3389 struct mlxsw_res *res) 3390 { 3391 int index, i; 3392 u64 data; 3393 u16 id; 3394 int err; 3395 3396 mlxsw_cmd_mbox_zero(mbox); 3397 3398 for (index = 0; index < MLXSW_CMD_QUERY_RESOURCES_MAX_QUERIES; 3399 index++) { 3400 err = mlxsw_cmd_query_resources(mlxsw_core, mbox, index); 3401 if (err) 3402 return err; 3403 3404 for (i = 0; i < MLXSW_CMD_QUERY_RESOURCES_PER_QUERY; i++) { 3405 id = mlxsw_cmd_mbox_query_resource_id_get(mbox, i); 3406 data = mlxsw_cmd_mbox_query_resource_data_get(mbox, i); 3407 3408 if (id == MLXSW_CMD_QUERY_RESOURCES_TABLE_END_ID) 3409 return 0; 3410 3411 mlxsw_res_parse(res, id, data); 3412 } 3413 } 3414 3415 /* If after MLXSW_RESOURCES_QUERY_MAX_QUERIES we still didn't get 3416 * MLXSW_RESOURCES_TABLE_END_ID, something went bad in the FW. 3417 */ 3418 return -EIO; 3419 } 3420 EXPORT_SYMBOL(mlxsw_core_resources_query); 3421 3422 u32 mlxsw_core_read_frc_h(struct mlxsw_core *mlxsw_core) 3423 { 3424 return mlxsw_core->bus->read_frc_h(mlxsw_core->bus_priv); 3425 } 3426 EXPORT_SYMBOL(mlxsw_core_read_frc_h); 3427 3428 u32 mlxsw_core_read_frc_l(struct mlxsw_core *mlxsw_core) 3429 { 3430 return mlxsw_core->bus->read_frc_l(mlxsw_core->bus_priv); 3431 } 3432 EXPORT_SYMBOL(mlxsw_core_read_frc_l); 3433 3434 u32 mlxsw_core_read_utc_sec(struct mlxsw_core *mlxsw_core) 3435 { 3436 return mlxsw_core->bus->read_utc_sec(mlxsw_core->bus_priv); 3437 } 3438 EXPORT_SYMBOL(mlxsw_core_read_utc_sec); 3439 3440 u32 mlxsw_core_read_utc_nsec(struct mlxsw_core *mlxsw_core) 3441 { 3442 return mlxsw_core->bus->read_utc_nsec(mlxsw_core->bus_priv); 3443 } 3444 EXPORT_SYMBOL(mlxsw_core_read_utc_nsec); 3445 3446 bool mlxsw_core_sdq_supports_cqe_v2(struct mlxsw_core *mlxsw_core) 3447 { 3448 return mlxsw_core->driver->sdq_supports_cqe_v2; 3449 } 3450 EXPORT_SYMBOL(mlxsw_core_sdq_supports_cqe_v2); 3451 3452 static int __init mlxsw_core_module_init(void) 3453 { 3454 int err; 3455 3456 err = mlxsw_linecard_driver_register(); 3457 if (err) 3458 return err; 3459 3460 mlxsw_wq = alloc_workqueue(mlxsw_core_driver_name, 0, 0); 3461 if (!mlxsw_wq) { 3462 err = -ENOMEM; 3463 goto err_alloc_workqueue; 3464 } 3465 mlxsw_owq = alloc_ordered_workqueue("%s_ordered", 0, 3466 mlxsw_core_driver_name); 3467 if (!mlxsw_owq) { 3468 err = -ENOMEM; 3469 goto err_alloc_ordered_workqueue; 3470 } 3471 return 0; 3472 3473 err_alloc_ordered_workqueue: 3474 destroy_workqueue(mlxsw_wq); 3475 err_alloc_workqueue: 3476 mlxsw_linecard_driver_unregister(); 3477 return err; 3478 } 3479 3480 static void __exit mlxsw_core_module_exit(void) 3481 { 3482 destroy_workqueue(mlxsw_owq); 3483 destroy_workqueue(mlxsw_wq); 3484 mlxsw_linecard_driver_unregister(); 3485 } 3486 3487 module_init(mlxsw_core_module_init); 3488 module_exit(mlxsw_core_module_exit); 3489 3490 MODULE_LICENSE("Dual BSD/GPL"); 3491 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>"); 3492 MODULE_DESCRIPTION("Mellanox switch device core driver"); 3493