1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/device.h> 7 #include <linux/export.h> 8 #include <linux/err.h> 9 #include <linux/if_link.h> 10 #include <linux/netdevice.h> 11 #include <linux/completion.h> 12 #include <linux/skbuff.h> 13 #include <linux/etherdevice.h> 14 #include <linux/types.h> 15 #include <linux/string.h> 16 #include <linux/gfp.h> 17 #include <linux/random.h> 18 #include <linux/jiffies.h> 19 #include <linux/mutex.h> 20 #include <linux/rcupdate.h> 21 #include <linux/slab.h> 22 #include <linux/workqueue.h> 23 #include <linux/firmware.h> 24 #include <asm/byteorder.h> 25 #include <net/devlink.h> 26 #include <trace/events/devlink.h> 27 28 #include "core.h" 29 #include "core_env.h" 30 #include "item.h" 31 #include "cmd.h" 32 #include "port.h" 33 #include "trap.h" 34 #include "emad.h" 35 #include "reg.h" 36 #include "resources.h" 37 #include "../mlxfw/mlxfw.h" 38 39 static LIST_HEAD(mlxsw_core_driver_list); 40 static DEFINE_SPINLOCK(mlxsw_core_driver_list_lock); 41 42 static const char mlxsw_core_driver_name[] = "mlxsw_core"; 43 44 static struct workqueue_struct *mlxsw_wq; 45 static struct workqueue_struct *mlxsw_owq; 46 47 struct mlxsw_core_port { 48 struct devlink_port devlink_port; 49 void *port_driver_priv; 50 u16 local_port; 51 }; 52 53 void *mlxsw_core_port_driver_priv(struct mlxsw_core_port *mlxsw_core_port) 54 { 55 return mlxsw_core_port->port_driver_priv; 56 } 57 EXPORT_SYMBOL(mlxsw_core_port_driver_priv); 58 59 static bool mlxsw_core_port_check(struct mlxsw_core_port *mlxsw_core_port) 60 { 61 return mlxsw_core_port->port_driver_priv != NULL; 62 } 63 64 struct mlxsw_core { 65 struct mlxsw_driver *driver; 66 const struct mlxsw_bus *bus; 67 void *bus_priv; 68 const struct mlxsw_bus_info *bus_info; 69 struct workqueue_struct *emad_wq; 70 struct list_head rx_listener_list; 71 struct list_head event_listener_list; 72 struct { 73 atomic64_t tid; 74 struct list_head trans_list; 75 spinlock_t trans_list_lock; /* protects trans_list writes */ 76 bool use_emad; 77 bool enable_string_tlv; 78 } emad; 79 struct { 80 u16 *mapping; /* lag_id+port_index to local_port mapping */ 81 } lag; 82 struct mlxsw_res res; 83 struct mlxsw_hwmon *hwmon; 84 struct mlxsw_thermal *thermal; 85 struct mlxsw_core_port *ports; 86 unsigned int max_ports; 87 atomic_t active_ports_count; 88 bool fw_flash_in_progress; 89 struct { 90 struct devlink_health_reporter *fw_fatal; 91 } health; 92 struct mlxsw_env *env; 93 unsigned long driver_priv[]; 94 /* driver_priv has to be always the last item */ 95 }; 96 97 #define MLXSW_PORT_MAX_PORTS_DEFAULT 0x40 98 99 static u64 mlxsw_ports_occ_get(void *priv) 100 { 101 struct mlxsw_core *mlxsw_core = priv; 102 103 return atomic_read(&mlxsw_core->active_ports_count); 104 } 105 106 static int mlxsw_core_resources_ports_register(struct mlxsw_core *mlxsw_core) 107 { 108 struct devlink *devlink = priv_to_devlink(mlxsw_core); 109 struct devlink_resource_size_params ports_num_params; 110 u32 max_ports; 111 112 max_ports = mlxsw_core->max_ports - 1; 113 devlink_resource_size_params_init(&ports_num_params, max_ports, 114 max_ports, 1, 115 DEVLINK_RESOURCE_UNIT_ENTRY); 116 117 return devlink_resource_register(devlink, 118 DEVLINK_RESOURCE_GENERIC_NAME_PORTS, 119 max_ports, MLXSW_CORE_RESOURCE_PORTS, 120 DEVLINK_RESOURCE_ID_PARENT_TOP, 121 &ports_num_params); 122 } 123 124 static int mlxsw_ports_init(struct mlxsw_core *mlxsw_core, bool reload) 125 { 126 struct devlink *devlink = priv_to_devlink(mlxsw_core); 127 int err; 128 129 /* Switch ports are numbered from 1 to queried value */ 130 if (MLXSW_CORE_RES_VALID(mlxsw_core, MAX_SYSTEM_PORT)) 131 mlxsw_core->max_ports = MLXSW_CORE_RES_GET(mlxsw_core, 132 MAX_SYSTEM_PORT) + 1; 133 else 134 mlxsw_core->max_ports = MLXSW_PORT_MAX_PORTS_DEFAULT + 1; 135 136 mlxsw_core->ports = kcalloc(mlxsw_core->max_ports, 137 sizeof(struct mlxsw_core_port), GFP_KERNEL); 138 if (!mlxsw_core->ports) 139 return -ENOMEM; 140 141 if (!reload) { 142 err = mlxsw_core_resources_ports_register(mlxsw_core); 143 if (err) 144 goto err_resources_ports_register; 145 } 146 atomic_set(&mlxsw_core->active_ports_count, 0); 147 devlink_resource_occ_get_register(devlink, MLXSW_CORE_RESOURCE_PORTS, 148 mlxsw_ports_occ_get, mlxsw_core); 149 150 return 0; 151 152 err_resources_ports_register: 153 kfree(mlxsw_core->ports); 154 return err; 155 } 156 157 static void mlxsw_ports_fini(struct mlxsw_core *mlxsw_core, bool reload) 158 { 159 struct devlink *devlink = priv_to_devlink(mlxsw_core); 160 161 devlink_resource_occ_get_unregister(devlink, MLXSW_CORE_RESOURCE_PORTS); 162 if (!reload) 163 devlink_resources_unregister(priv_to_devlink(mlxsw_core)); 164 165 kfree(mlxsw_core->ports); 166 } 167 168 unsigned int mlxsw_core_max_ports(const struct mlxsw_core *mlxsw_core) 169 { 170 return mlxsw_core->max_ports; 171 } 172 EXPORT_SYMBOL(mlxsw_core_max_ports); 173 174 void *mlxsw_core_driver_priv(struct mlxsw_core *mlxsw_core) 175 { 176 return mlxsw_core->driver_priv; 177 } 178 EXPORT_SYMBOL(mlxsw_core_driver_priv); 179 180 bool mlxsw_core_res_query_enabled(const struct mlxsw_core *mlxsw_core) 181 { 182 return mlxsw_core->driver->res_query_enabled; 183 } 184 EXPORT_SYMBOL(mlxsw_core_res_query_enabled); 185 186 bool mlxsw_core_temp_warn_enabled(const struct mlxsw_core *mlxsw_core) 187 { 188 return mlxsw_core->driver->temp_warn_enabled; 189 } 190 191 bool 192 mlxsw_core_fw_rev_minor_subminor_validate(const struct mlxsw_fw_rev *rev, 193 const struct mlxsw_fw_rev *req_rev) 194 { 195 return rev->minor > req_rev->minor || 196 (rev->minor == req_rev->minor && 197 rev->subminor >= req_rev->subminor); 198 } 199 EXPORT_SYMBOL(mlxsw_core_fw_rev_minor_subminor_validate); 200 201 struct mlxsw_rx_listener_item { 202 struct list_head list; 203 struct mlxsw_rx_listener rxl; 204 void *priv; 205 bool enabled; 206 }; 207 208 struct mlxsw_event_listener_item { 209 struct list_head list; 210 struct mlxsw_core *mlxsw_core; 211 struct mlxsw_event_listener el; 212 void *priv; 213 }; 214 215 static const u8 mlxsw_core_trap_groups[] = { 216 MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 217 MLXSW_REG_HTGT_TRAP_GROUP_CORE_EVENT, 218 }; 219 220 static int mlxsw_core_trap_groups_set(struct mlxsw_core *mlxsw_core) 221 { 222 char htgt_pl[MLXSW_REG_HTGT_LEN]; 223 int err; 224 int i; 225 226 for (i = 0; i < ARRAY_SIZE(mlxsw_core_trap_groups); i++) { 227 mlxsw_reg_htgt_pack(htgt_pl, mlxsw_core_trap_groups[i], 228 MLXSW_REG_HTGT_INVALID_POLICER, 229 MLXSW_REG_HTGT_DEFAULT_PRIORITY, 230 MLXSW_REG_HTGT_DEFAULT_TC); 231 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl); 232 if (err) 233 return err; 234 } 235 return 0; 236 } 237 238 /****************** 239 * EMAD processing 240 ******************/ 241 242 /* emad_eth_hdr_dmac 243 * Destination MAC in EMAD's Ethernet header. 244 * Must be set to 01:02:c9:00:00:01 245 */ 246 MLXSW_ITEM_BUF(emad, eth_hdr, dmac, 0x00, 6); 247 248 /* emad_eth_hdr_smac 249 * Source MAC in EMAD's Ethernet header. 250 * Must be set to 00:02:c9:01:02:03 251 */ 252 MLXSW_ITEM_BUF(emad, eth_hdr, smac, 0x06, 6); 253 254 /* emad_eth_hdr_ethertype 255 * Ethertype in EMAD's Ethernet header. 256 * Must be set to 0x8932 257 */ 258 MLXSW_ITEM32(emad, eth_hdr, ethertype, 0x0C, 16, 16); 259 260 /* emad_eth_hdr_mlx_proto 261 * Mellanox protocol. 262 * Must be set to 0x0. 263 */ 264 MLXSW_ITEM32(emad, eth_hdr, mlx_proto, 0x0C, 8, 8); 265 266 /* emad_eth_hdr_ver 267 * Mellanox protocol version. 268 * Must be set to 0x0. 269 */ 270 MLXSW_ITEM32(emad, eth_hdr, ver, 0x0C, 4, 4); 271 272 /* emad_op_tlv_type 273 * Type of the TLV. 274 * Must be set to 0x1 (operation TLV). 275 */ 276 MLXSW_ITEM32(emad, op_tlv, type, 0x00, 27, 5); 277 278 /* emad_op_tlv_len 279 * Length of the operation TLV in u32. 280 * Must be set to 0x4. 281 */ 282 MLXSW_ITEM32(emad, op_tlv, len, 0x00, 16, 11); 283 284 /* emad_op_tlv_dr 285 * Direct route bit. Setting to 1 indicates the EMAD is a direct route 286 * EMAD. DR TLV must follow. 287 * 288 * Note: Currently not supported and must not be set. 289 */ 290 MLXSW_ITEM32(emad, op_tlv, dr, 0x00, 15, 1); 291 292 /* emad_op_tlv_status 293 * Returned status in case of EMAD response. Must be set to 0 in case 294 * of EMAD request. 295 * 0x0 - success 296 * 0x1 - device is busy. Requester should retry 297 * 0x2 - Mellanox protocol version not supported 298 * 0x3 - unknown TLV 299 * 0x4 - register not supported 300 * 0x5 - operation class not supported 301 * 0x6 - EMAD method not supported 302 * 0x7 - bad parameter (e.g. port out of range) 303 * 0x8 - resource not available 304 * 0x9 - message receipt acknowledgment. Requester should retry 305 * 0x70 - internal error 306 */ 307 MLXSW_ITEM32(emad, op_tlv, status, 0x00, 8, 7); 308 309 /* emad_op_tlv_register_id 310 * Register ID of register within register TLV. 311 */ 312 MLXSW_ITEM32(emad, op_tlv, register_id, 0x04, 16, 16); 313 314 /* emad_op_tlv_r 315 * Response bit. Setting to 1 indicates Response, otherwise request. 316 */ 317 MLXSW_ITEM32(emad, op_tlv, r, 0x04, 15, 1); 318 319 /* emad_op_tlv_method 320 * EMAD method type. 321 * 0x1 - query 322 * 0x2 - write 323 * 0x3 - send (currently not supported) 324 * 0x4 - event 325 */ 326 MLXSW_ITEM32(emad, op_tlv, method, 0x04, 8, 7); 327 328 /* emad_op_tlv_class 329 * EMAD operation class. Must be set to 0x1 (REG_ACCESS). 330 */ 331 MLXSW_ITEM32(emad, op_tlv, class, 0x04, 0, 8); 332 333 /* emad_op_tlv_tid 334 * EMAD transaction ID. Used for pairing request and response EMADs. 335 */ 336 MLXSW_ITEM64(emad, op_tlv, tid, 0x08, 0, 64); 337 338 /* emad_string_tlv_type 339 * Type of the TLV. 340 * Must be set to 0x2 (string TLV). 341 */ 342 MLXSW_ITEM32(emad, string_tlv, type, 0x00, 27, 5); 343 344 /* emad_string_tlv_len 345 * Length of the string TLV in u32. 346 */ 347 MLXSW_ITEM32(emad, string_tlv, len, 0x00, 16, 11); 348 349 #define MLXSW_EMAD_STRING_TLV_STRING_LEN 128 350 351 /* emad_string_tlv_string 352 * String provided by the device's firmware in case of erroneous register access 353 */ 354 MLXSW_ITEM_BUF(emad, string_tlv, string, 0x04, 355 MLXSW_EMAD_STRING_TLV_STRING_LEN); 356 357 /* emad_reg_tlv_type 358 * Type of the TLV. 359 * Must be set to 0x3 (register TLV). 360 */ 361 MLXSW_ITEM32(emad, reg_tlv, type, 0x00, 27, 5); 362 363 /* emad_reg_tlv_len 364 * Length of the operation TLV in u32. 365 */ 366 MLXSW_ITEM32(emad, reg_tlv, len, 0x00, 16, 11); 367 368 /* emad_end_tlv_type 369 * Type of the TLV. 370 * Must be set to 0x0 (end TLV). 371 */ 372 MLXSW_ITEM32(emad, end_tlv, type, 0x00, 27, 5); 373 374 /* emad_end_tlv_len 375 * Length of the end TLV in u32. 376 * Must be set to 1. 377 */ 378 MLXSW_ITEM32(emad, end_tlv, len, 0x00, 16, 11); 379 380 enum mlxsw_core_reg_access_type { 381 MLXSW_CORE_REG_ACCESS_TYPE_QUERY, 382 MLXSW_CORE_REG_ACCESS_TYPE_WRITE, 383 }; 384 385 static inline const char * 386 mlxsw_core_reg_access_type_str(enum mlxsw_core_reg_access_type type) 387 { 388 switch (type) { 389 case MLXSW_CORE_REG_ACCESS_TYPE_QUERY: 390 return "query"; 391 case MLXSW_CORE_REG_ACCESS_TYPE_WRITE: 392 return "write"; 393 } 394 BUG(); 395 } 396 397 static void mlxsw_emad_pack_end_tlv(char *end_tlv) 398 { 399 mlxsw_emad_end_tlv_type_set(end_tlv, MLXSW_EMAD_TLV_TYPE_END); 400 mlxsw_emad_end_tlv_len_set(end_tlv, MLXSW_EMAD_END_TLV_LEN); 401 } 402 403 static void mlxsw_emad_pack_reg_tlv(char *reg_tlv, 404 const struct mlxsw_reg_info *reg, 405 char *payload) 406 { 407 mlxsw_emad_reg_tlv_type_set(reg_tlv, MLXSW_EMAD_TLV_TYPE_REG); 408 mlxsw_emad_reg_tlv_len_set(reg_tlv, reg->len / sizeof(u32) + 1); 409 memcpy(reg_tlv + sizeof(u32), payload, reg->len); 410 } 411 412 static void mlxsw_emad_pack_string_tlv(char *string_tlv) 413 { 414 mlxsw_emad_string_tlv_type_set(string_tlv, MLXSW_EMAD_TLV_TYPE_STRING); 415 mlxsw_emad_string_tlv_len_set(string_tlv, MLXSW_EMAD_STRING_TLV_LEN); 416 } 417 418 static void mlxsw_emad_pack_op_tlv(char *op_tlv, 419 const struct mlxsw_reg_info *reg, 420 enum mlxsw_core_reg_access_type type, 421 u64 tid) 422 { 423 mlxsw_emad_op_tlv_type_set(op_tlv, MLXSW_EMAD_TLV_TYPE_OP); 424 mlxsw_emad_op_tlv_len_set(op_tlv, MLXSW_EMAD_OP_TLV_LEN); 425 mlxsw_emad_op_tlv_dr_set(op_tlv, 0); 426 mlxsw_emad_op_tlv_status_set(op_tlv, 0); 427 mlxsw_emad_op_tlv_register_id_set(op_tlv, reg->id); 428 mlxsw_emad_op_tlv_r_set(op_tlv, MLXSW_EMAD_OP_TLV_REQUEST); 429 if (type == MLXSW_CORE_REG_ACCESS_TYPE_QUERY) 430 mlxsw_emad_op_tlv_method_set(op_tlv, 431 MLXSW_EMAD_OP_TLV_METHOD_QUERY); 432 else 433 mlxsw_emad_op_tlv_method_set(op_tlv, 434 MLXSW_EMAD_OP_TLV_METHOD_WRITE); 435 mlxsw_emad_op_tlv_class_set(op_tlv, 436 MLXSW_EMAD_OP_TLV_CLASS_REG_ACCESS); 437 mlxsw_emad_op_tlv_tid_set(op_tlv, tid); 438 } 439 440 static int mlxsw_emad_construct_eth_hdr(struct sk_buff *skb) 441 { 442 char *eth_hdr = skb_push(skb, MLXSW_EMAD_ETH_HDR_LEN); 443 444 mlxsw_emad_eth_hdr_dmac_memcpy_to(eth_hdr, MLXSW_EMAD_EH_DMAC); 445 mlxsw_emad_eth_hdr_smac_memcpy_to(eth_hdr, MLXSW_EMAD_EH_SMAC); 446 mlxsw_emad_eth_hdr_ethertype_set(eth_hdr, MLXSW_EMAD_EH_ETHERTYPE); 447 mlxsw_emad_eth_hdr_mlx_proto_set(eth_hdr, MLXSW_EMAD_EH_MLX_PROTO); 448 mlxsw_emad_eth_hdr_ver_set(eth_hdr, MLXSW_EMAD_EH_PROTO_VERSION); 449 450 skb_reset_mac_header(skb); 451 452 return 0; 453 } 454 455 static void mlxsw_emad_construct(struct sk_buff *skb, 456 const struct mlxsw_reg_info *reg, 457 char *payload, 458 enum mlxsw_core_reg_access_type type, 459 u64 tid, bool enable_string_tlv) 460 { 461 char *buf; 462 463 buf = skb_push(skb, MLXSW_EMAD_END_TLV_LEN * sizeof(u32)); 464 mlxsw_emad_pack_end_tlv(buf); 465 466 buf = skb_push(skb, reg->len + sizeof(u32)); 467 mlxsw_emad_pack_reg_tlv(buf, reg, payload); 468 469 if (enable_string_tlv) { 470 buf = skb_push(skb, MLXSW_EMAD_STRING_TLV_LEN * sizeof(u32)); 471 mlxsw_emad_pack_string_tlv(buf); 472 } 473 474 buf = skb_push(skb, MLXSW_EMAD_OP_TLV_LEN * sizeof(u32)); 475 mlxsw_emad_pack_op_tlv(buf, reg, type, tid); 476 477 mlxsw_emad_construct_eth_hdr(skb); 478 } 479 480 struct mlxsw_emad_tlv_offsets { 481 u16 op_tlv; 482 u16 string_tlv; 483 u16 reg_tlv; 484 }; 485 486 static bool mlxsw_emad_tlv_is_string_tlv(const char *tlv) 487 { 488 u8 tlv_type = mlxsw_emad_string_tlv_type_get(tlv); 489 490 return tlv_type == MLXSW_EMAD_TLV_TYPE_STRING; 491 } 492 493 static void mlxsw_emad_tlv_parse(struct sk_buff *skb) 494 { 495 struct mlxsw_emad_tlv_offsets *offsets = 496 (struct mlxsw_emad_tlv_offsets *) skb->cb; 497 498 offsets->op_tlv = MLXSW_EMAD_ETH_HDR_LEN; 499 offsets->string_tlv = 0; 500 offsets->reg_tlv = MLXSW_EMAD_ETH_HDR_LEN + 501 MLXSW_EMAD_OP_TLV_LEN * sizeof(u32); 502 503 /* If string TLV is present, it must come after the operation TLV. */ 504 if (mlxsw_emad_tlv_is_string_tlv(skb->data + offsets->reg_tlv)) { 505 offsets->string_tlv = offsets->reg_tlv; 506 offsets->reg_tlv += MLXSW_EMAD_STRING_TLV_LEN * sizeof(u32); 507 } 508 } 509 510 static char *mlxsw_emad_op_tlv(const struct sk_buff *skb) 511 { 512 struct mlxsw_emad_tlv_offsets *offsets = 513 (struct mlxsw_emad_tlv_offsets *) skb->cb; 514 515 return ((char *) (skb->data + offsets->op_tlv)); 516 } 517 518 static char *mlxsw_emad_string_tlv(const struct sk_buff *skb) 519 { 520 struct mlxsw_emad_tlv_offsets *offsets = 521 (struct mlxsw_emad_tlv_offsets *) skb->cb; 522 523 if (!offsets->string_tlv) 524 return NULL; 525 526 return ((char *) (skb->data + offsets->string_tlv)); 527 } 528 529 static char *mlxsw_emad_reg_tlv(const struct sk_buff *skb) 530 { 531 struct mlxsw_emad_tlv_offsets *offsets = 532 (struct mlxsw_emad_tlv_offsets *) skb->cb; 533 534 return ((char *) (skb->data + offsets->reg_tlv)); 535 } 536 537 static char *mlxsw_emad_reg_payload(const char *reg_tlv) 538 { 539 return ((char *) (reg_tlv + sizeof(u32))); 540 } 541 542 static char *mlxsw_emad_reg_payload_cmd(const char *mbox) 543 { 544 return ((char *) (mbox + (MLXSW_EMAD_OP_TLV_LEN + 1) * sizeof(u32))); 545 } 546 547 static u64 mlxsw_emad_get_tid(const struct sk_buff *skb) 548 { 549 char *op_tlv; 550 551 op_tlv = mlxsw_emad_op_tlv(skb); 552 return mlxsw_emad_op_tlv_tid_get(op_tlv); 553 } 554 555 static bool mlxsw_emad_is_resp(const struct sk_buff *skb) 556 { 557 char *op_tlv; 558 559 op_tlv = mlxsw_emad_op_tlv(skb); 560 return (mlxsw_emad_op_tlv_r_get(op_tlv) == MLXSW_EMAD_OP_TLV_RESPONSE); 561 } 562 563 static int mlxsw_emad_process_status(char *op_tlv, 564 enum mlxsw_emad_op_tlv_status *p_status) 565 { 566 *p_status = mlxsw_emad_op_tlv_status_get(op_tlv); 567 568 switch (*p_status) { 569 case MLXSW_EMAD_OP_TLV_STATUS_SUCCESS: 570 return 0; 571 case MLXSW_EMAD_OP_TLV_STATUS_BUSY: 572 case MLXSW_EMAD_OP_TLV_STATUS_MESSAGE_RECEIPT_ACK: 573 return -EAGAIN; 574 case MLXSW_EMAD_OP_TLV_STATUS_VERSION_NOT_SUPPORTED: 575 case MLXSW_EMAD_OP_TLV_STATUS_UNKNOWN_TLV: 576 case MLXSW_EMAD_OP_TLV_STATUS_REGISTER_NOT_SUPPORTED: 577 case MLXSW_EMAD_OP_TLV_STATUS_CLASS_NOT_SUPPORTED: 578 case MLXSW_EMAD_OP_TLV_STATUS_METHOD_NOT_SUPPORTED: 579 case MLXSW_EMAD_OP_TLV_STATUS_BAD_PARAMETER: 580 case MLXSW_EMAD_OP_TLV_STATUS_RESOURCE_NOT_AVAILABLE: 581 case MLXSW_EMAD_OP_TLV_STATUS_INTERNAL_ERROR: 582 default: 583 return -EIO; 584 } 585 } 586 587 static int 588 mlxsw_emad_process_status_skb(struct sk_buff *skb, 589 enum mlxsw_emad_op_tlv_status *p_status) 590 { 591 return mlxsw_emad_process_status(mlxsw_emad_op_tlv(skb), p_status); 592 } 593 594 struct mlxsw_reg_trans { 595 struct list_head list; 596 struct list_head bulk_list; 597 struct mlxsw_core *core; 598 struct sk_buff *tx_skb; 599 struct mlxsw_tx_info tx_info; 600 struct delayed_work timeout_dw; 601 unsigned int retries; 602 u64 tid; 603 struct completion completion; 604 atomic_t active; 605 mlxsw_reg_trans_cb_t *cb; 606 unsigned long cb_priv; 607 const struct mlxsw_reg_info *reg; 608 enum mlxsw_core_reg_access_type type; 609 int err; 610 char *emad_err_string; 611 enum mlxsw_emad_op_tlv_status emad_status; 612 struct rcu_head rcu; 613 }; 614 615 static void mlxsw_emad_process_string_tlv(const struct sk_buff *skb, 616 struct mlxsw_reg_trans *trans) 617 { 618 char *string_tlv; 619 char *string; 620 621 string_tlv = mlxsw_emad_string_tlv(skb); 622 if (!string_tlv) 623 return; 624 625 trans->emad_err_string = kzalloc(MLXSW_EMAD_STRING_TLV_STRING_LEN, 626 GFP_ATOMIC); 627 if (!trans->emad_err_string) 628 return; 629 630 string = mlxsw_emad_string_tlv_string_data(string_tlv); 631 strlcpy(trans->emad_err_string, string, 632 MLXSW_EMAD_STRING_TLV_STRING_LEN); 633 } 634 635 #define MLXSW_EMAD_TIMEOUT_DURING_FW_FLASH_MS 3000 636 #define MLXSW_EMAD_TIMEOUT_MS 200 637 638 static void mlxsw_emad_trans_timeout_schedule(struct mlxsw_reg_trans *trans) 639 { 640 unsigned long timeout = msecs_to_jiffies(MLXSW_EMAD_TIMEOUT_MS); 641 642 if (trans->core->fw_flash_in_progress) 643 timeout = msecs_to_jiffies(MLXSW_EMAD_TIMEOUT_DURING_FW_FLASH_MS); 644 645 queue_delayed_work(trans->core->emad_wq, &trans->timeout_dw, 646 timeout << trans->retries); 647 } 648 649 static int mlxsw_emad_transmit(struct mlxsw_core *mlxsw_core, 650 struct mlxsw_reg_trans *trans) 651 { 652 struct sk_buff *skb; 653 int err; 654 655 skb = skb_clone(trans->tx_skb, GFP_KERNEL); 656 if (!skb) 657 return -ENOMEM; 658 659 trace_devlink_hwmsg(priv_to_devlink(mlxsw_core), false, 0, 660 skb->data + mlxsw_core->driver->txhdr_len, 661 skb->len - mlxsw_core->driver->txhdr_len); 662 663 atomic_set(&trans->active, 1); 664 err = mlxsw_core_skb_transmit(mlxsw_core, skb, &trans->tx_info); 665 if (err) { 666 dev_kfree_skb(skb); 667 return err; 668 } 669 mlxsw_emad_trans_timeout_schedule(trans); 670 return 0; 671 } 672 673 static void mlxsw_emad_trans_finish(struct mlxsw_reg_trans *trans, int err) 674 { 675 struct mlxsw_core *mlxsw_core = trans->core; 676 677 dev_kfree_skb(trans->tx_skb); 678 spin_lock_bh(&mlxsw_core->emad.trans_list_lock); 679 list_del_rcu(&trans->list); 680 spin_unlock_bh(&mlxsw_core->emad.trans_list_lock); 681 trans->err = err; 682 complete(&trans->completion); 683 } 684 685 static void mlxsw_emad_transmit_retry(struct mlxsw_core *mlxsw_core, 686 struct mlxsw_reg_trans *trans) 687 { 688 int err; 689 690 if (trans->retries < MLXSW_EMAD_MAX_RETRY) { 691 trans->retries++; 692 err = mlxsw_emad_transmit(trans->core, trans); 693 if (err == 0) 694 return; 695 696 if (!atomic_dec_and_test(&trans->active)) 697 return; 698 } else { 699 err = -EIO; 700 } 701 mlxsw_emad_trans_finish(trans, err); 702 } 703 704 static void mlxsw_emad_trans_timeout_work(struct work_struct *work) 705 { 706 struct mlxsw_reg_trans *trans = container_of(work, 707 struct mlxsw_reg_trans, 708 timeout_dw.work); 709 710 if (!atomic_dec_and_test(&trans->active)) 711 return; 712 713 mlxsw_emad_transmit_retry(trans->core, trans); 714 } 715 716 static void mlxsw_emad_process_response(struct mlxsw_core *mlxsw_core, 717 struct mlxsw_reg_trans *trans, 718 struct sk_buff *skb) 719 { 720 int err; 721 722 if (!atomic_dec_and_test(&trans->active)) 723 return; 724 725 err = mlxsw_emad_process_status_skb(skb, &trans->emad_status); 726 if (err == -EAGAIN) { 727 mlxsw_emad_transmit_retry(mlxsw_core, trans); 728 } else { 729 if (err == 0) { 730 char *reg_tlv = mlxsw_emad_reg_tlv(skb); 731 732 if (trans->cb) 733 trans->cb(mlxsw_core, 734 mlxsw_emad_reg_payload(reg_tlv), 735 trans->reg->len, trans->cb_priv); 736 } else { 737 mlxsw_emad_process_string_tlv(skb, trans); 738 } 739 mlxsw_emad_trans_finish(trans, err); 740 } 741 } 742 743 /* called with rcu read lock held */ 744 static void mlxsw_emad_rx_listener_func(struct sk_buff *skb, u16 local_port, 745 void *priv) 746 { 747 struct mlxsw_core *mlxsw_core = priv; 748 struct mlxsw_reg_trans *trans; 749 750 trace_devlink_hwmsg(priv_to_devlink(mlxsw_core), true, 0, 751 skb->data, skb->len); 752 753 mlxsw_emad_tlv_parse(skb); 754 755 if (!mlxsw_emad_is_resp(skb)) 756 goto free_skb; 757 758 list_for_each_entry_rcu(trans, &mlxsw_core->emad.trans_list, list) { 759 if (mlxsw_emad_get_tid(skb) == trans->tid) { 760 mlxsw_emad_process_response(mlxsw_core, trans, skb); 761 break; 762 } 763 } 764 765 free_skb: 766 dev_kfree_skb(skb); 767 } 768 769 static const struct mlxsw_listener mlxsw_emad_rx_listener = 770 MLXSW_RXL(mlxsw_emad_rx_listener_func, ETHEMAD, TRAP_TO_CPU, false, 771 EMAD, DISCARD); 772 773 static int mlxsw_emad_init(struct mlxsw_core *mlxsw_core) 774 { 775 struct workqueue_struct *emad_wq; 776 u64 tid; 777 int err; 778 779 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_TXRX)) 780 return 0; 781 782 emad_wq = alloc_workqueue("mlxsw_core_emad", 0, 0); 783 if (!emad_wq) 784 return -ENOMEM; 785 mlxsw_core->emad_wq = emad_wq; 786 787 /* Set the upper 32 bits of the transaction ID field to a random 788 * number. This allows us to discard EMADs addressed to other 789 * devices. 790 */ 791 get_random_bytes(&tid, 4); 792 tid <<= 32; 793 atomic64_set(&mlxsw_core->emad.tid, tid); 794 795 INIT_LIST_HEAD(&mlxsw_core->emad.trans_list); 796 spin_lock_init(&mlxsw_core->emad.trans_list_lock); 797 798 err = mlxsw_core_trap_register(mlxsw_core, &mlxsw_emad_rx_listener, 799 mlxsw_core); 800 if (err) 801 goto err_trap_register; 802 803 mlxsw_core->emad.use_emad = true; 804 805 return 0; 806 807 err_trap_register: 808 destroy_workqueue(mlxsw_core->emad_wq); 809 return err; 810 } 811 812 static void mlxsw_emad_fini(struct mlxsw_core *mlxsw_core) 813 { 814 815 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_TXRX)) 816 return; 817 818 mlxsw_core->emad.use_emad = false; 819 mlxsw_core_trap_unregister(mlxsw_core, &mlxsw_emad_rx_listener, 820 mlxsw_core); 821 destroy_workqueue(mlxsw_core->emad_wq); 822 } 823 824 static struct sk_buff *mlxsw_emad_alloc(const struct mlxsw_core *mlxsw_core, 825 u16 reg_len, bool enable_string_tlv) 826 { 827 struct sk_buff *skb; 828 u16 emad_len; 829 830 emad_len = (reg_len + sizeof(u32) + MLXSW_EMAD_ETH_HDR_LEN + 831 (MLXSW_EMAD_OP_TLV_LEN + MLXSW_EMAD_END_TLV_LEN) * 832 sizeof(u32) + mlxsw_core->driver->txhdr_len); 833 if (enable_string_tlv) 834 emad_len += MLXSW_EMAD_STRING_TLV_LEN * sizeof(u32); 835 if (emad_len > MLXSW_EMAD_MAX_FRAME_LEN) 836 return NULL; 837 838 skb = netdev_alloc_skb(NULL, emad_len); 839 if (!skb) 840 return NULL; 841 memset(skb->data, 0, emad_len); 842 skb_reserve(skb, emad_len); 843 844 return skb; 845 } 846 847 static int mlxsw_emad_reg_access(struct mlxsw_core *mlxsw_core, 848 const struct mlxsw_reg_info *reg, 849 char *payload, 850 enum mlxsw_core_reg_access_type type, 851 struct mlxsw_reg_trans *trans, 852 struct list_head *bulk_list, 853 mlxsw_reg_trans_cb_t *cb, 854 unsigned long cb_priv, u64 tid) 855 { 856 bool enable_string_tlv; 857 struct sk_buff *skb; 858 int err; 859 860 dev_dbg(mlxsw_core->bus_info->dev, "EMAD reg access (tid=%llx,reg_id=%x(%s),type=%s)\n", 861 tid, reg->id, mlxsw_reg_id_str(reg->id), 862 mlxsw_core_reg_access_type_str(type)); 863 864 /* Since this can be changed during emad_reg_access, read it once and 865 * use the value all the way. 866 */ 867 enable_string_tlv = mlxsw_core->emad.enable_string_tlv; 868 869 skb = mlxsw_emad_alloc(mlxsw_core, reg->len, enable_string_tlv); 870 if (!skb) 871 return -ENOMEM; 872 873 list_add_tail(&trans->bulk_list, bulk_list); 874 trans->core = mlxsw_core; 875 trans->tx_skb = skb; 876 trans->tx_info.local_port = MLXSW_PORT_CPU_PORT; 877 trans->tx_info.is_emad = true; 878 INIT_DELAYED_WORK(&trans->timeout_dw, mlxsw_emad_trans_timeout_work); 879 trans->tid = tid; 880 init_completion(&trans->completion); 881 trans->cb = cb; 882 trans->cb_priv = cb_priv; 883 trans->reg = reg; 884 trans->type = type; 885 886 mlxsw_emad_construct(skb, reg, payload, type, trans->tid, 887 enable_string_tlv); 888 mlxsw_core->driver->txhdr_construct(skb, &trans->tx_info); 889 890 spin_lock_bh(&mlxsw_core->emad.trans_list_lock); 891 list_add_tail_rcu(&trans->list, &mlxsw_core->emad.trans_list); 892 spin_unlock_bh(&mlxsw_core->emad.trans_list_lock); 893 err = mlxsw_emad_transmit(mlxsw_core, trans); 894 if (err) 895 goto err_out; 896 return 0; 897 898 err_out: 899 spin_lock_bh(&mlxsw_core->emad.trans_list_lock); 900 list_del_rcu(&trans->list); 901 spin_unlock_bh(&mlxsw_core->emad.trans_list_lock); 902 list_del(&trans->bulk_list); 903 dev_kfree_skb(trans->tx_skb); 904 return err; 905 } 906 907 /***************** 908 * Core functions 909 *****************/ 910 911 int mlxsw_core_driver_register(struct mlxsw_driver *mlxsw_driver) 912 { 913 spin_lock(&mlxsw_core_driver_list_lock); 914 list_add_tail(&mlxsw_driver->list, &mlxsw_core_driver_list); 915 spin_unlock(&mlxsw_core_driver_list_lock); 916 return 0; 917 } 918 EXPORT_SYMBOL(mlxsw_core_driver_register); 919 920 void mlxsw_core_driver_unregister(struct mlxsw_driver *mlxsw_driver) 921 { 922 spin_lock(&mlxsw_core_driver_list_lock); 923 list_del(&mlxsw_driver->list); 924 spin_unlock(&mlxsw_core_driver_list_lock); 925 } 926 EXPORT_SYMBOL(mlxsw_core_driver_unregister); 927 928 static struct mlxsw_driver *__driver_find(const char *kind) 929 { 930 struct mlxsw_driver *mlxsw_driver; 931 932 list_for_each_entry(mlxsw_driver, &mlxsw_core_driver_list, list) { 933 if (strcmp(mlxsw_driver->kind, kind) == 0) 934 return mlxsw_driver; 935 } 936 return NULL; 937 } 938 939 static struct mlxsw_driver *mlxsw_core_driver_get(const char *kind) 940 { 941 struct mlxsw_driver *mlxsw_driver; 942 943 spin_lock(&mlxsw_core_driver_list_lock); 944 mlxsw_driver = __driver_find(kind); 945 spin_unlock(&mlxsw_core_driver_list_lock); 946 return mlxsw_driver; 947 } 948 949 struct mlxsw_core_fw_info { 950 struct mlxfw_dev mlxfw_dev; 951 struct mlxsw_core *mlxsw_core; 952 }; 953 954 static int mlxsw_core_fw_component_query(struct mlxfw_dev *mlxfw_dev, 955 u16 component_index, u32 *p_max_size, 956 u8 *p_align_bits, u16 *p_max_write_size) 957 { 958 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 959 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 960 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 961 char mcqi_pl[MLXSW_REG_MCQI_LEN]; 962 int err; 963 964 mlxsw_reg_mcqi_pack(mcqi_pl, component_index); 965 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mcqi), mcqi_pl); 966 if (err) 967 return err; 968 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits, p_max_write_size); 969 970 *p_align_bits = max_t(u8, *p_align_bits, 2); 971 *p_max_write_size = min_t(u16, *p_max_write_size, MLXSW_REG_MCDA_MAX_DATA_LEN); 972 return 0; 973 } 974 975 static int mlxsw_core_fw_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle) 976 { 977 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 978 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 979 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 980 char mcc_pl[MLXSW_REG_MCC_LEN]; 981 u8 control_state; 982 int err; 983 984 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0); 985 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 986 if (err) 987 return err; 988 989 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state); 990 if (control_state != MLXFW_FSM_STATE_IDLE) 991 return -EBUSY; 992 993 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE, 0, *fwhandle, 0); 994 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 995 } 996 997 static int mlxsw_core_fw_fsm_component_update(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 998 u16 component_index, u32 component_size) 999 { 1000 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1001 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1002 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1003 char mcc_pl[MLXSW_REG_MCC_LEN]; 1004 1005 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT, 1006 component_index, fwhandle, component_size); 1007 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1008 } 1009 1010 static int mlxsw_core_fw_fsm_block_download(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 1011 u8 *data, u16 size, u32 offset) 1012 { 1013 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1014 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1015 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1016 char mcda_pl[MLXSW_REG_MCDA_LEN]; 1017 1018 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data); 1019 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcda), mcda_pl); 1020 } 1021 1022 static int mlxsw_core_fw_fsm_component_verify(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 1023 u16 component_index) 1024 { 1025 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1026 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1027 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1028 char mcc_pl[MLXSW_REG_MCC_LEN]; 1029 1030 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT, 1031 component_index, fwhandle, 0); 1032 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1033 } 1034 1035 static int mlxsw_core_fw_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 1036 { 1037 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1038 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1039 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1040 char mcc_pl[MLXSW_REG_MCC_LEN]; 1041 1042 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0, fwhandle, 0); 1043 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1044 } 1045 1046 static int mlxsw_core_fw_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 1047 enum mlxfw_fsm_state *fsm_state, 1048 enum mlxfw_fsm_state_err *fsm_state_err) 1049 { 1050 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1051 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1052 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1053 char mcc_pl[MLXSW_REG_MCC_LEN]; 1054 u8 control_state; 1055 u8 error_code; 1056 int err; 1057 1058 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0); 1059 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1060 if (err) 1061 return err; 1062 1063 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state); 1064 *fsm_state = control_state; 1065 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code, MLXFW_FSM_STATE_ERR_MAX); 1066 return 0; 1067 } 1068 1069 static void mlxsw_core_fw_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 1070 { 1071 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1072 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1073 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1074 char mcc_pl[MLXSW_REG_MCC_LEN]; 1075 1076 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0, fwhandle, 0); 1077 mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1078 } 1079 1080 static void mlxsw_core_fw_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 1081 { 1082 struct mlxsw_core_fw_info *mlxsw_core_fw_info = 1083 container_of(mlxfw_dev, struct mlxsw_core_fw_info, mlxfw_dev); 1084 struct mlxsw_core *mlxsw_core = mlxsw_core_fw_info->mlxsw_core; 1085 char mcc_pl[MLXSW_REG_MCC_LEN]; 1086 1087 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0, fwhandle, 0); 1088 mlxsw_reg_write(mlxsw_core, MLXSW_REG(mcc), mcc_pl); 1089 } 1090 1091 static const struct mlxfw_dev_ops mlxsw_core_fw_mlxsw_dev_ops = { 1092 .component_query = mlxsw_core_fw_component_query, 1093 .fsm_lock = mlxsw_core_fw_fsm_lock, 1094 .fsm_component_update = mlxsw_core_fw_fsm_component_update, 1095 .fsm_block_download = mlxsw_core_fw_fsm_block_download, 1096 .fsm_component_verify = mlxsw_core_fw_fsm_component_verify, 1097 .fsm_activate = mlxsw_core_fw_fsm_activate, 1098 .fsm_query_state = mlxsw_core_fw_fsm_query_state, 1099 .fsm_cancel = mlxsw_core_fw_fsm_cancel, 1100 .fsm_release = mlxsw_core_fw_fsm_release, 1101 }; 1102 1103 static int mlxsw_core_fw_flash(struct mlxsw_core *mlxsw_core, const struct firmware *firmware, 1104 struct netlink_ext_ack *extack) 1105 { 1106 struct mlxsw_core_fw_info mlxsw_core_fw_info = { 1107 .mlxfw_dev = { 1108 .ops = &mlxsw_core_fw_mlxsw_dev_ops, 1109 .psid = mlxsw_core->bus_info->psid, 1110 .psid_size = strlen(mlxsw_core->bus_info->psid), 1111 .devlink = priv_to_devlink(mlxsw_core), 1112 }, 1113 .mlxsw_core = mlxsw_core 1114 }; 1115 int err; 1116 1117 mlxsw_core->fw_flash_in_progress = true; 1118 err = mlxfw_firmware_flash(&mlxsw_core_fw_info.mlxfw_dev, firmware, extack); 1119 mlxsw_core->fw_flash_in_progress = false; 1120 1121 return err; 1122 } 1123 1124 static int mlxsw_core_fw_rev_validate(struct mlxsw_core *mlxsw_core, 1125 const struct mlxsw_bus_info *mlxsw_bus_info, 1126 const struct mlxsw_fw_rev *req_rev, 1127 const char *filename) 1128 { 1129 const struct mlxsw_fw_rev *rev = &mlxsw_bus_info->fw_rev; 1130 union devlink_param_value value; 1131 const struct firmware *firmware; 1132 int err; 1133 1134 /* Don't check if driver does not require it */ 1135 if (!req_rev || !filename) 1136 return 0; 1137 1138 /* Don't check if devlink 'fw_load_policy' param is 'flash' */ 1139 err = devlink_param_driverinit_value_get(priv_to_devlink(mlxsw_core), 1140 DEVLINK_PARAM_GENERIC_ID_FW_LOAD_POLICY, 1141 &value); 1142 if (err) 1143 return err; 1144 if (value.vu8 == DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_FLASH) 1145 return 0; 1146 1147 /* Validate driver & FW are compatible */ 1148 if (rev->major != req_rev->major) { 1149 WARN(1, "Mismatch in major FW version [%d:%d] is never expected; Please contact support\n", 1150 rev->major, req_rev->major); 1151 return -EINVAL; 1152 } 1153 if (mlxsw_core_fw_rev_minor_subminor_validate(rev, req_rev)) 1154 return 0; 1155 1156 dev_err(mlxsw_bus_info->dev, "The firmware version %d.%d.%d is incompatible with the driver (required >= %d.%d.%d)\n", 1157 rev->major, rev->minor, rev->subminor, req_rev->major, 1158 req_rev->minor, req_rev->subminor); 1159 dev_info(mlxsw_bus_info->dev, "Flashing firmware using file %s\n", filename); 1160 1161 err = request_firmware_direct(&firmware, filename, mlxsw_bus_info->dev); 1162 if (err) { 1163 dev_err(mlxsw_bus_info->dev, "Could not request firmware file %s\n", filename); 1164 return err; 1165 } 1166 1167 err = mlxsw_core_fw_flash(mlxsw_core, firmware, NULL); 1168 release_firmware(firmware); 1169 if (err) 1170 dev_err(mlxsw_bus_info->dev, "Could not upgrade firmware\n"); 1171 1172 /* On FW flash success, tell the caller FW reset is needed 1173 * if current FW supports it. 1174 */ 1175 if (rev->minor >= req_rev->can_reset_minor) 1176 return err ? err : -EAGAIN; 1177 else 1178 return 0; 1179 } 1180 1181 static int mlxsw_core_fw_flash_update(struct mlxsw_core *mlxsw_core, 1182 struct devlink_flash_update_params *params, 1183 struct netlink_ext_ack *extack) 1184 { 1185 return mlxsw_core_fw_flash(mlxsw_core, params->fw, extack); 1186 } 1187 1188 static int mlxsw_core_devlink_param_fw_load_policy_validate(struct devlink *devlink, u32 id, 1189 union devlink_param_value val, 1190 struct netlink_ext_ack *extack) 1191 { 1192 if (val.vu8 != DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_DRIVER && 1193 val.vu8 != DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_FLASH) { 1194 NL_SET_ERR_MSG_MOD(extack, "'fw_load_policy' must be 'driver' or 'flash'"); 1195 return -EINVAL; 1196 } 1197 1198 return 0; 1199 } 1200 1201 static const struct devlink_param mlxsw_core_fw_devlink_params[] = { 1202 DEVLINK_PARAM_GENERIC(FW_LOAD_POLICY, BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), NULL, NULL, 1203 mlxsw_core_devlink_param_fw_load_policy_validate), 1204 }; 1205 1206 static int mlxsw_core_fw_params_register(struct mlxsw_core *mlxsw_core) 1207 { 1208 struct devlink *devlink = priv_to_devlink(mlxsw_core); 1209 union devlink_param_value value; 1210 int err; 1211 1212 err = devlink_params_register(devlink, mlxsw_core_fw_devlink_params, 1213 ARRAY_SIZE(mlxsw_core_fw_devlink_params)); 1214 if (err) 1215 return err; 1216 1217 value.vu8 = DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_DRIVER; 1218 devlink_param_driverinit_value_set(devlink, DEVLINK_PARAM_GENERIC_ID_FW_LOAD_POLICY, value); 1219 return 0; 1220 } 1221 1222 static void mlxsw_core_fw_params_unregister(struct mlxsw_core *mlxsw_core) 1223 { 1224 devlink_params_unregister(priv_to_devlink(mlxsw_core), mlxsw_core_fw_devlink_params, 1225 ARRAY_SIZE(mlxsw_core_fw_devlink_params)); 1226 } 1227 1228 static int mlxsw_devlink_port_split(struct devlink *devlink, 1229 unsigned int port_index, 1230 unsigned int count, 1231 struct netlink_ext_ack *extack) 1232 { 1233 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1234 1235 if (port_index >= mlxsw_core->max_ports) { 1236 NL_SET_ERR_MSG_MOD(extack, "Port index exceeds maximum number of ports"); 1237 return -EINVAL; 1238 } 1239 if (!mlxsw_core->driver->port_split) 1240 return -EOPNOTSUPP; 1241 return mlxsw_core->driver->port_split(mlxsw_core, port_index, count, 1242 extack); 1243 } 1244 1245 static int mlxsw_devlink_port_unsplit(struct devlink *devlink, 1246 unsigned int port_index, 1247 struct netlink_ext_ack *extack) 1248 { 1249 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1250 1251 if (port_index >= mlxsw_core->max_ports) { 1252 NL_SET_ERR_MSG_MOD(extack, "Port index exceeds maximum number of ports"); 1253 return -EINVAL; 1254 } 1255 if (!mlxsw_core->driver->port_unsplit) 1256 return -EOPNOTSUPP; 1257 return mlxsw_core->driver->port_unsplit(mlxsw_core, port_index, 1258 extack); 1259 } 1260 1261 static int 1262 mlxsw_devlink_sb_pool_get(struct devlink *devlink, 1263 unsigned int sb_index, u16 pool_index, 1264 struct devlink_sb_pool_info *pool_info) 1265 { 1266 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1267 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1268 1269 if (!mlxsw_driver->sb_pool_get) 1270 return -EOPNOTSUPP; 1271 return mlxsw_driver->sb_pool_get(mlxsw_core, sb_index, 1272 pool_index, pool_info); 1273 } 1274 1275 static int 1276 mlxsw_devlink_sb_pool_set(struct devlink *devlink, 1277 unsigned int sb_index, u16 pool_index, u32 size, 1278 enum devlink_sb_threshold_type threshold_type, 1279 struct netlink_ext_ack *extack) 1280 { 1281 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1282 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1283 1284 if (!mlxsw_driver->sb_pool_set) 1285 return -EOPNOTSUPP; 1286 return mlxsw_driver->sb_pool_set(mlxsw_core, sb_index, 1287 pool_index, size, threshold_type, 1288 extack); 1289 } 1290 1291 static void *__dl_port(struct devlink_port *devlink_port) 1292 { 1293 return container_of(devlink_port, struct mlxsw_core_port, devlink_port); 1294 } 1295 1296 static int mlxsw_devlink_port_type_set(struct devlink_port *devlink_port, 1297 enum devlink_port_type port_type) 1298 { 1299 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1300 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1301 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1302 1303 if (!mlxsw_driver->port_type_set) 1304 return -EOPNOTSUPP; 1305 1306 return mlxsw_driver->port_type_set(mlxsw_core, 1307 mlxsw_core_port->local_port, 1308 port_type); 1309 } 1310 1311 static int mlxsw_devlink_sb_port_pool_get(struct devlink_port *devlink_port, 1312 unsigned int sb_index, u16 pool_index, 1313 u32 *p_threshold) 1314 { 1315 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1316 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1317 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1318 1319 if (!mlxsw_driver->sb_port_pool_get || 1320 !mlxsw_core_port_check(mlxsw_core_port)) 1321 return -EOPNOTSUPP; 1322 return mlxsw_driver->sb_port_pool_get(mlxsw_core_port, sb_index, 1323 pool_index, p_threshold); 1324 } 1325 1326 static int mlxsw_devlink_sb_port_pool_set(struct devlink_port *devlink_port, 1327 unsigned int sb_index, u16 pool_index, 1328 u32 threshold, 1329 struct netlink_ext_ack *extack) 1330 { 1331 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1332 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1333 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1334 1335 if (!mlxsw_driver->sb_port_pool_set || 1336 !mlxsw_core_port_check(mlxsw_core_port)) 1337 return -EOPNOTSUPP; 1338 return mlxsw_driver->sb_port_pool_set(mlxsw_core_port, sb_index, 1339 pool_index, threshold, extack); 1340 } 1341 1342 static int 1343 mlxsw_devlink_sb_tc_pool_bind_get(struct devlink_port *devlink_port, 1344 unsigned int sb_index, u16 tc_index, 1345 enum devlink_sb_pool_type pool_type, 1346 u16 *p_pool_index, u32 *p_threshold) 1347 { 1348 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1349 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1350 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1351 1352 if (!mlxsw_driver->sb_tc_pool_bind_get || 1353 !mlxsw_core_port_check(mlxsw_core_port)) 1354 return -EOPNOTSUPP; 1355 return mlxsw_driver->sb_tc_pool_bind_get(mlxsw_core_port, sb_index, 1356 tc_index, pool_type, 1357 p_pool_index, p_threshold); 1358 } 1359 1360 static int 1361 mlxsw_devlink_sb_tc_pool_bind_set(struct devlink_port *devlink_port, 1362 unsigned int sb_index, u16 tc_index, 1363 enum devlink_sb_pool_type pool_type, 1364 u16 pool_index, u32 threshold, 1365 struct netlink_ext_ack *extack) 1366 { 1367 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1368 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1369 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1370 1371 if (!mlxsw_driver->sb_tc_pool_bind_set || 1372 !mlxsw_core_port_check(mlxsw_core_port)) 1373 return -EOPNOTSUPP; 1374 return mlxsw_driver->sb_tc_pool_bind_set(mlxsw_core_port, sb_index, 1375 tc_index, pool_type, 1376 pool_index, threshold, extack); 1377 } 1378 1379 static int mlxsw_devlink_sb_occ_snapshot(struct devlink *devlink, 1380 unsigned int sb_index) 1381 { 1382 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1383 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1384 1385 if (!mlxsw_driver->sb_occ_snapshot) 1386 return -EOPNOTSUPP; 1387 return mlxsw_driver->sb_occ_snapshot(mlxsw_core, sb_index); 1388 } 1389 1390 static int mlxsw_devlink_sb_occ_max_clear(struct devlink *devlink, 1391 unsigned int sb_index) 1392 { 1393 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1394 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1395 1396 if (!mlxsw_driver->sb_occ_max_clear) 1397 return -EOPNOTSUPP; 1398 return mlxsw_driver->sb_occ_max_clear(mlxsw_core, sb_index); 1399 } 1400 1401 static int 1402 mlxsw_devlink_sb_occ_port_pool_get(struct devlink_port *devlink_port, 1403 unsigned int sb_index, u16 pool_index, 1404 u32 *p_cur, u32 *p_max) 1405 { 1406 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1407 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1408 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1409 1410 if (!mlxsw_driver->sb_occ_port_pool_get || 1411 !mlxsw_core_port_check(mlxsw_core_port)) 1412 return -EOPNOTSUPP; 1413 return mlxsw_driver->sb_occ_port_pool_get(mlxsw_core_port, sb_index, 1414 pool_index, p_cur, p_max); 1415 } 1416 1417 static int 1418 mlxsw_devlink_sb_occ_tc_port_bind_get(struct devlink_port *devlink_port, 1419 unsigned int sb_index, u16 tc_index, 1420 enum devlink_sb_pool_type pool_type, 1421 u32 *p_cur, u32 *p_max) 1422 { 1423 struct mlxsw_core *mlxsw_core = devlink_priv(devlink_port->devlink); 1424 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1425 struct mlxsw_core_port *mlxsw_core_port = __dl_port(devlink_port); 1426 1427 if (!mlxsw_driver->sb_occ_tc_port_bind_get || 1428 !mlxsw_core_port_check(mlxsw_core_port)) 1429 return -EOPNOTSUPP; 1430 return mlxsw_driver->sb_occ_tc_port_bind_get(mlxsw_core_port, 1431 sb_index, tc_index, 1432 pool_type, p_cur, p_max); 1433 } 1434 1435 static int 1436 mlxsw_devlink_info_get(struct devlink *devlink, struct devlink_info_req *req, 1437 struct netlink_ext_ack *extack) 1438 { 1439 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1440 char fw_info_psid[MLXSW_REG_MGIR_FW_INFO_PSID_SIZE]; 1441 u32 hw_rev, fw_major, fw_minor, fw_sub_minor; 1442 char mgir_pl[MLXSW_REG_MGIR_LEN]; 1443 char buf[32]; 1444 int err; 1445 1446 err = devlink_info_driver_name_put(req, 1447 mlxsw_core->bus_info->device_kind); 1448 if (err) 1449 return err; 1450 1451 mlxsw_reg_mgir_pack(mgir_pl); 1452 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mgir), mgir_pl); 1453 if (err) 1454 return err; 1455 mlxsw_reg_mgir_unpack(mgir_pl, &hw_rev, fw_info_psid, &fw_major, 1456 &fw_minor, &fw_sub_minor); 1457 1458 sprintf(buf, "%X", hw_rev); 1459 err = devlink_info_version_fixed_put(req, "hw.revision", buf); 1460 if (err) 1461 return err; 1462 1463 err = devlink_info_version_fixed_put(req, 1464 DEVLINK_INFO_VERSION_GENERIC_FW_PSID, 1465 fw_info_psid); 1466 if (err) 1467 return err; 1468 1469 sprintf(buf, "%d.%d.%d", fw_major, fw_minor, fw_sub_minor); 1470 err = devlink_info_version_running_put(req, "fw.version", buf); 1471 if (err) 1472 return err; 1473 1474 return devlink_info_version_running_put(req, 1475 DEVLINK_INFO_VERSION_GENERIC_FW, 1476 buf); 1477 } 1478 1479 static int 1480 mlxsw_devlink_core_bus_device_reload_down(struct devlink *devlink, 1481 bool netns_change, enum devlink_reload_action action, 1482 enum devlink_reload_limit limit, 1483 struct netlink_ext_ack *extack) 1484 { 1485 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1486 1487 if (!(mlxsw_core->bus->features & MLXSW_BUS_F_RESET)) 1488 return -EOPNOTSUPP; 1489 1490 mlxsw_core_bus_device_unregister(mlxsw_core, true); 1491 return 0; 1492 } 1493 1494 static int 1495 mlxsw_devlink_core_bus_device_reload_up(struct devlink *devlink, enum devlink_reload_action action, 1496 enum devlink_reload_limit limit, u32 *actions_performed, 1497 struct netlink_ext_ack *extack) 1498 { 1499 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1500 1501 *actions_performed = BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT) | 1502 BIT(DEVLINK_RELOAD_ACTION_FW_ACTIVATE); 1503 return mlxsw_core_bus_device_register(mlxsw_core->bus_info, 1504 mlxsw_core->bus, 1505 mlxsw_core->bus_priv, true, 1506 devlink, extack); 1507 } 1508 1509 static int mlxsw_devlink_flash_update(struct devlink *devlink, 1510 struct devlink_flash_update_params *params, 1511 struct netlink_ext_ack *extack) 1512 { 1513 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1514 1515 return mlxsw_core_fw_flash_update(mlxsw_core, params, extack); 1516 } 1517 1518 static int mlxsw_devlink_trap_init(struct devlink *devlink, 1519 const struct devlink_trap *trap, 1520 void *trap_ctx) 1521 { 1522 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1523 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1524 1525 if (!mlxsw_driver->trap_init) 1526 return -EOPNOTSUPP; 1527 return mlxsw_driver->trap_init(mlxsw_core, trap, trap_ctx); 1528 } 1529 1530 static void mlxsw_devlink_trap_fini(struct devlink *devlink, 1531 const struct devlink_trap *trap, 1532 void *trap_ctx) 1533 { 1534 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1535 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1536 1537 if (!mlxsw_driver->trap_fini) 1538 return; 1539 mlxsw_driver->trap_fini(mlxsw_core, trap, trap_ctx); 1540 } 1541 1542 static int mlxsw_devlink_trap_action_set(struct devlink *devlink, 1543 const struct devlink_trap *trap, 1544 enum devlink_trap_action action, 1545 struct netlink_ext_ack *extack) 1546 { 1547 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1548 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1549 1550 if (!mlxsw_driver->trap_action_set) 1551 return -EOPNOTSUPP; 1552 return mlxsw_driver->trap_action_set(mlxsw_core, trap, action, extack); 1553 } 1554 1555 static int 1556 mlxsw_devlink_trap_group_init(struct devlink *devlink, 1557 const struct devlink_trap_group *group) 1558 { 1559 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1560 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1561 1562 if (!mlxsw_driver->trap_group_init) 1563 return -EOPNOTSUPP; 1564 return mlxsw_driver->trap_group_init(mlxsw_core, group); 1565 } 1566 1567 static int 1568 mlxsw_devlink_trap_group_set(struct devlink *devlink, 1569 const struct devlink_trap_group *group, 1570 const struct devlink_trap_policer *policer, 1571 struct netlink_ext_ack *extack) 1572 { 1573 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1574 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1575 1576 if (!mlxsw_driver->trap_group_set) 1577 return -EOPNOTSUPP; 1578 return mlxsw_driver->trap_group_set(mlxsw_core, group, policer, extack); 1579 } 1580 1581 static int 1582 mlxsw_devlink_trap_policer_init(struct devlink *devlink, 1583 const struct devlink_trap_policer *policer) 1584 { 1585 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1586 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1587 1588 if (!mlxsw_driver->trap_policer_init) 1589 return -EOPNOTSUPP; 1590 return mlxsw_driver->trap_policer_init(mlxsw_core, policer); 1591 } 1592 1593 static void 1594 mlxsw_devlink_trap_policer_fini(struct devlink *devlink, 1595 const struct devlink_trap_policer *policer) 1596 { 1597 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1598 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1599 1600 if (!mlxsw_driver->trap_policer_fini) 1601 return; 1602 mlxsw_driver->trap_policer_fini(mlxsw_core, policer); 1603 } 1604 1605 static int 1606 mlxsw_devlink_trap_policer_set(struct devlink *devlink, 1607 const struct devlink_trap_policer *policer, 1608 u64 rate, u64 burst, 1609 struct netlink_ext_ack *extack) 1610 { 1611 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1612 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1613 1614 if (!mlxsw_driver->trap_policer_set) 1615 return -EOPNOTSUPP; 1616 return mlxsw_driver->trap_policer_set(mlxsw_core, policer, rate, burst, 1617 extack); 1618 } 1619 1620 static int 1621 mlxsw_devlink_trap_policer_counter_get(struct devlink *devlink, 1622 const struct devlink_trap_policer *policer, 1623 u64 *p_drops) 1624 { 1625 struct mlxsw_core *mlxsw_core = devlink_priv(devlink); 1626 struct mlxsw_driver *mlxsw_driver = mlxsw_core->driver; 1627 1628 if (!mlxsw_driver->trap_policer_counter_get) 1629 return -EOPNOTSUPP; 1630 return mlxsw_driver->trap_policer_counter_get(mlxsw_core, policer, 1631 p_drops); 1632 } 1633 1634 static const struct devlink_ops mlxsw_devlink_ops = { 1635 .reload_actions = BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT) | 1636 BIT(DEVLINK_RELOAD_ACTION_FW_ACTIVATE), 1637 .reload_down = mlxsw_devlink_core_bus_device_reload_down, 1638 .reload_up = mlxsw_devlink_core_bus_device_reload_up, 1639 .port_type_set = mlxsw_devlink_port_type_set, 1640 .port_split = mlxsw_devlink_port_split, 1641 .port_unsplit = mlxsw_devlink_port_unsplit, 1642 .sb_pool_get = mlxsw_devlink_sb_pool_get, 1643 .sb_pool_set = mlxsw_devlink_sb_pool_set, 1644 .sb_port_pool_get = mlxsw_devlink_sb_port_pool_get, 1645 .sb_port_pool_set = mlxsw_devlink_sb_port_pool_set, 1646 .sb_tc_pool_bind_get = mlxsw_devlink_sb_tc_pool_bind_get, 1647 .sb_tc_pool_bind_set = mlxsw_devlink_sb_tc_pool_bind_set, 1648 .sb_occ_snapshot = mlxsw_devlink_sb_occ_snapshot, 1649 .sb_occ_max_clear = mlxsw_devlink_sb_occ_max_clear, 1650 .sb_occ_port_pool_get = mlxsw_devlink_sb_occ_port_pool_get, 1651 .sb_occ_tc_port_bind_get = mlxsw_devlink_sb_occ_tc_port_bind_get, 1652 .info_get = mlxsw_devlink_info_get, 1653 .flash_update = mlxsw_devlink_flash_update, 1654 .trap_init = mlxsw_devlink_trap_init, 1655 .trap_fini = mlxsw_devlink_trap_fini, 1656 .trap_action_set = mlxsw_devlink_trap_action_set, 1657 .trap_group_init = mlxsw_devlink_trap_group_init, 1658 .trap_group_set = mlxsw_devlink_trap_group_set, 1659 .trap_policer_init = mlxsw_devlink_trap_policer_init, 1660 .trap_policer_fini = mlxsw_devlink_trap_policer_fini, 1661 .trap_policer_set = mlxsw_devlink_trap_policer_set, 1662 .trap_policer_counter_get = mlxsw_devlink_trap_policer_counter_get, 1663 }; 1664 1665 static int mlxsw_core_params_register(struct mlxsw_core *mlxsw_core) 1666 { 1667 int err; 1668 1669 err = mlxsw_core_fw_params_register(mlxsw_core); 1670 if (err) 1671 return err; 1672 1673 if (mlxsw_core->driver->params_register) { 1674 err = mlxsw_core->driver->params_register(mlxsw_core); 1675 if (err) 1676 goto err_params_register; 1677 } 1678 return 0; 1679 1680 err_params_register: 1681 mlxsw_core_fw_params_unregister(mlxsw_core); 1682 return err; 1683 } 1684 1685 static void mlxsw_core_params_unregister(struct mlxsw_core *mlxsw_core) 1686 { 1687 mlxsw_core_fw_params_unregister(mlxsw_core); 1688 if (mlxsw_core->driver->params_register) 1689 mlxsw_core->driver->params_unregister(mlxsw_core); 1690 } 1691 1692 struct mlxsw_core_health_event { 1693 struct mlxsw_core *mlxsw_core; 1694 char mfde_pl[MLXSW_REG_MFDE_LEN]; 1695 struct work_struct work; 1696 }; 1697 1698 static void mlxsw_core_health_event_work(struct work_struct *work) 1699 { 1700 struct mlxsw_core_health_event *event; 1701 struct mlxsw_core *mlxsw_core; 1702 1703 event = container_of(work, struct mlxsw_core_health_event, work); 1704 mlxsw_core = event->mlxsw_core; 1705 devlink_health_report(mlxsw_core->health.fw_fatal, "FW fatal event occurred", 1706 event->mfde_pl); 1707 kfree(event); 1708 } 1709 1710 static void mlxsw_core_health_listener_func(const struct mlxsw_reg_info *reg, 1711 char *mfde_pl, void *priv) 1712 { 1713 struct mlxsw_core_health_event *event; 1714 struct mlxsw_core *mlxsw_core = priv; 1715 1716 event = kmalloc(sizeof(*event), GFP_ATOMIC); 1717 if (!event) 1718 return; 1719 event->mlxsw_core = mlxsw_core; 1720 memcpy(event->mfde_pl, mfde_pl, sizeof(event->mfde_pl)); 1721 INIT_WORK(&event->work, mlxsw_core_health_event_work); 1722 mlxsw_core_schedule_work(&event->work); 1723 } 1724 1725 static const struct mlxsw_listener mlxsw_core_health_listener = 1726 MLXSW_CORE_EVENTL(mlxsw_core_health_listener_func, MFDE); 1727 1728 static int 1729 mlxsw_core_health_fw_fatal_dump_fatal_cause(const char *mfde_pl, 1730 struct devlink_fmsg *fmsg) 1731 { 1732 u32 val, tile_v; 1733 int err; 1734 1735 val = mlxsw_reg_mfde_fatal_cause_id_get(mfde_pl); 1736 err = devlink_fmsg_u32_pair_put(fmsg, "cause_id", val); 1737 if (err) 1738 return err; 1739 tile_v = mlxsw_reg_mfde_fatal_cause_tile_v_get(mfde_pl); 1740 if (tile_v) { 1741 val = mlxsw_reg_mfde_fatal_cause_tile_index_get(mfde_pl); 1742 err = devlink_fmsg_u8_pair_put(fmsg, "tile_index", val); 1743 if (err) 1744 return err; 1745 } 1746 1747 return 0; 1748 } 1749 1750 static int 1751 mlxsw_core_health_fw_fatal_dump_fw_assert(const char *mfde_pl, 1752 struct devlink_fmsg *fmsg) 1753 { 1754 u32 val, tile_v; 1755 int err; 1756 1757 val = mlxsw_reg_mfde_fw_assert_var0_get(mfde_pl); 1758 err = devlink_fmsg_u32_pair_put(fmsg, "var0", val); 1759 if (err) 1760 return err; 1761 val = mlxsw_reg_mfde_fw_assert_var1_get(mfde_pl); 1762 err = devlink_fmsg_u32_pair_put(fmsg, "var1", val); 1763 if (err) 1764 return err; 1765 val = mlxsw_reg_mfde_fw_assert_var2_get(mfde_pl); 1766 err = devlink_fmsg_u32_pair_put(fmsg, "var2", val); 1767 if (err) 1768 return err; 1769 val = mlxsw_reg_mfde_fw_assert_var3_get(mfde_pl); 1770 err = devlink_fmsg_u32_pair_put(fmsg, "var3", val); 1771 if (err) 1772 return err; 1773 val = mlxsw_reg_mfde_fw_assert_var4_get(mfde_pl); 1774 err = devlink_fmsg_u32_pair_put(fmsg, "var4", val); 1775 if (err) 1776 return err; 1777 val = mlxsw_reg_mfde_fw_assert_existptr_get(mfde_pl); 1778 err = devlink_fmsg_u32_pair_put(fmsg, "existptr", val); 1779 if (err) 1780 return err; 1781 val = mlxsw_reg_mfde_fw_assert_callra_get(mfde_pl); 1782 err = devlink_fmsg_u32_pair_put(fmsg, "callra", val); 1783 if (err) 1784 return err; 1785 val = mlxsw_reg_mfde_fw_assert_oe_get(mfde_pl); 1786 err = devlink_fmsg_bool_pair_put(fmsg, "old_event", val); 1787 if (err) 1788 return err; 1789 tile_v = mlxsw_reg_mfde_fw_assert_tile_v_get(mfde_pl); 1790 if (tile_v) { 1791 val = mlxsw_reg_mfde_fw_assert_tile_index_get(mfde_pl); 1792 err = devlink_fmsg_u8_pair_put(fmsg, "tile_index", val); 1793 if (err) 1794 return err; 1795 } 1796 val = mlxsw_reg_mfde_fw_assert_ext_synd_get(mfde_pl); 1797 err = devlink_fmsg_u32_pair_put(fmsg, "ext_synd", val); 1798 if (err) 1799 return err; 1800 1801 return 0; 1802 } 1803 1804 static int 1805 mlxsw_core_health_fw_fatal_dump_kvd_im_stop(const char *mfde_pl, 1806 struct devlink_fmsg *fmsg) 1807 { 1808 u32 val; 1809 int err; 1810 1811 val = mlxsw_reg_mfde_kvd_im_stop_oe_get(mfde_pl); 1812 err = devlink_fmsg_bool_pair_put(fmsg, "old_event", val); 1813 if (err) 1814 return err; 1815 val = mlxsw_reg_mfde_kvd_im_stop_pipes_mask_get(mfde_pl); 1816 return devlink_fmsg_u32_pair_put(fmsg, "pipes_mask", val); 1817 } 1818 1819 static int 1820 mlxsw_core_health_fw_fatal_dump_crspace_to(const char *mfde_pl, 1821 struct devlink_fmsg *fmsg) 1822 { 1823 u32 val; 1824 int err; 1825 1826 val = mlxsw_reg_mfde_crspace_to_log_address_get(mfde_pl); 1827 err = devlink_fmsg_u32_pair_put(fmsg, "log_address", val); 1828 if (err) 1829 return err; 1830 val = mlxsw_reg_mfde_crspace_to_oe_get(mfde_pl); 1831 err = devlink_fmsg_bool_pair_put(fmsg, "old_event", val); 1832 if (err) 1833 return err; 1834 val = mlxsw_reg_mfde_crspace_to_log_id_get(mfde_pl); 1835 err = devlink_fmsg_u8_pair_put(fmsg, "log_irisc_id", val); 1836 if (err) 1837 return err; 1838 val = mlxsw_reg_mfde_crspace_to_log_ip_get(mfde_pl); 1839 err = devlink_fmsg_u64_pair_put(fmsg, "log_ip", val); 1840 if (err) 1841 return err; 1842 1843 return 0; 1844 } 1845 1846 static int mlxsw_core_health_fw_fatal_dump(struct devlink_health_reporter *reporter, 1847 struct devlink_fmsg *fmsg, void *priv_ctx, 1848 struct netlink_ext_ack *extack) 1849 { 1850 char *mfde_pl = priv_ctx; 1851 char *val_str; 1852 u8 event_id; 1853 u32 val; 1854 int err; 1855 1856 if (!priv_ctx) 1857 /* User-triggered dumps are not possible */ 1858 return -EOPNOTSUPP; 1859 1860 val = mlxsw_reg_mfde_irisc_id_get(mfde_pl); 1861 err = devlink_fmsg_u8_pair_put(fmsg, "irisc_id", val); 1862 if (err) 1863 return err; 1864 err = devlink_fmsg_arr_pair_nest_start(fmsg, "event"); 1865 if (err) 1866 return err; 1867 1868 event_id = mlxsw_reg_mfde_event_id_get(mfde_pl); 1869 err = devlink_fmsg_u32_pair_put(fmsg, "id", event_id); 1870 if (err) 1871 return err; 1872 switch (event_id) { 1873 case MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO: 1874 val_str = "CR space timeout"; 1875 break; 1876 case MLXSW_REG_MFDE_EVENT_ID_KVD_IM_STOP: 1877 val_str = "KVD insertion machine stopped"; 1878 break; 1879 case MLXSW_REG_MFDE_EVENT_ID_TEST: 1880 val_str = "Test"; 1881 break; 1882 case MLXSW_REG_MFDE_EVENT_ID_FW_ASSERT: 1883 val_str = "FW assert"; 1884 break; 1885 case MLXSW_REG_MFDE_EVENT_ID_FATAL_CAUSE: 1886 val_str = "Fatal cause"; 1887 break; 1888 default: 1889 val_str = NULL; 1890 } 1891 if (val_str) { 1892 err = devlink_fmsg_string_pair_put(fmsg, "desc", val_str); 1893 if (err) 1894 return err; 1895 } 1896 1897 err = devlink_fmsg_arr_pair_nest_end(fmsg); 1898 if (err) 1899 return err; 1900 1901 err = devlink_fmsg_arr_pair_nest_start(fmsg, "severity"); 1902 if (err) 1903 return err; 1904 1905 val = mlxsw_reg_mfde_severity_get(mfde_pl); 1906 err = devlink_fmsg_u8_pair_put(fmsg, "id", val); 1907 if (err) 1908 return err; 1909 switch (val) { 1910 case MLXSW_REG_MFDE_SEVERITY_FATL: 1911 val_str = "Fatal"; 1912 break; 1913 case MLXSW_REG_MFDE_SEVERITY_NRML: 1914 val_str = "Normal"; 1915 break; 1916 case MLXSW_REG_MFDE_SEVERITY_INTR: 1917 val_str = "Debug"; 1918 break; 1919 default: 1920 val_str = NULL; 1921 } 1922 if (val_str) { 1923 err = devlink_fmsg_string_pair_put(fmsg, "desc", val_str); 1924 if (err) 1925 return err; 1926 } 1927 1928 err = devlink_fmsg_arr_pair_nest_end(fmsg); 1929 if (err) 1930 return err; 1931 1932 val = mlxsw_reg_mfde_method_get(mfde_pl); 1933 switch (val) { 1934 case MLXSW_REG_MFDE_METHOD_QUERY: 1935 val_str = "query"; 1936 break; 1937 case MLXSW_REG_MFDE_METHOD_WRITE: 1938 val_str = "write"; 1939 break; 1940 default: 1941 val_str = NULL; 1942 } 1943 if (val_str) { 1944 err = devlink_fmsg_string_pair_put(fmsg, "method", val_str); 1945 if (err) 1946 return err; 1947 } 1948 1949 val = mlxsw_reg_mfde_long_process_get(mfde_pl); 1950 err = devlink_fmsg_bool_pair_put(fmsg, "long_process", val); 1951 if (err) 1952 return err; 1953 1954 val = mlxsw_reg_mfde_command_type_get(mfde_pl); 1955 switch (val) { 1956 case MLXSW_REG_MFDE_COMMAND_TYPE_MAD: 1957 val_str = "mad"; 1958 break; 1959 case MLXSW_REG_MFDE_COMMAND_TYPE_EMAD: 1960 val_str = "emad"; 1961 break; 1962 case MLXSW_REG_MFDE_COMMAND_TYPE_CMDIF: 1963 val_str = "cmdif"; 1964 break; 1965 default: 1966 val_str = NULL; 1967 } 1968 if (val_str) { 1969 err = devlink_fmsg_string_pair_put(fmsg, "command_type", val_str); 1970 if (err) 1971 return err; 1972 } 1973 1974 val = mlxsw_reg_mfde_reg_attr_id_get(mfde_pl); 1975 err = devlink_fmsg_u32_pair_put(fmsg, "reg_attr_id", val); 1976 if (err) 1977 return err; 1978 1979 switch (event_id) { 1980 case MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO: 1981 return mlxsw_core_health_fw_fatal_dump_crspace_to(mfde_pl, 1982 fmsg); 1983 case MLXSW_REG_MFDE_EVENT_ID_KVD_IM_STOP: 1984 return mlxsw_core_health_fw_fatal_dump_kvd_im_stop(mfde_pl, 1985 fmsg); 1986 case MLXSW_REG_MFDE_EVENT_ID_FW_ASSERT: 1987 return mlxsw_core_health_fw_fatal_dump_fw_assert(mfde_pl, fmsg); 1988 case MLXSW_REG_MFDE_EVENT_ID_FATAL_CAUSE: 1989 return mlxsw_core_health_fw_fatal_dump_fatal_cause(mfde_pl, 1990 fmsg); 1991 } 1992 1993 return 0; 1994 } 1995 1996 static int 1997 mlxsw_core_health_fw_fatal_test(struct devlink_health_reporter *reporter, 1998 struct netlink_ext_ack *extack) 1999 { 2000 struct mlxsw_core *mlxsw_core = devlink_health_reporter_priv(reporter); 2001 char mfgd_pl[MLXSW_REG_MFGD_LEN]; 2002 int err; 2003 2004 /* Read the register first to make sure no other bits are changed. */ 2005 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mfgd), mfgd_pl); 2006 if (err) 2007 return err; 2008 mlxsw_reg_mfgd_trigger_test_set(mfgd_pl, true); 2009 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mfgd), mfgd_pl); 2010 } 2011 2012 static const struct devlink_health_reporter_ops 2013 mlxsw_core_health_fw_fatal_ops = { 2014 .name = "fw_fatal", 2015 .dump = mlxsw_core_health_fw_fatal_dump, 2016 .test = mlxsw_core_health_fw_fatal_test, 2017 }; 2018 2019 static int mlxsw_core_health_fw_fatal_config(struct mlxsw_core *mlxsw_core, 2020 bool enable) 2021 { 2022 char mfgd_pl[MLXSW_REG_MFGD_LEN]; 2023 int err; 2024 2025 /* Read the register first to make sure no other bits are changed. */ 2026 err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(mfgd), mfgd_pl); 2027 if (err) 2028 return err; 2029 mlxsw_reg_mfgd_fatal_event_mode_set(mfgd_pl, enable); 2030 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(mfgd), mfgd_pl); 2031 } 2032 2033 static int mlxsw_core_health_init(struct mlxsw_core *mlxsw_core) 2034 { 2035 struct devlink *devlink = priv_to_devlink(mlxsw_core); 2036 struct devlink_health_reporter *fw_fatal; 2037 int err; 2038 2039 if (!mlxsw_core->driver->fw_fatal_enabled) 2040 return 0; 2041 2042 fw_fatal = devlink_health_reporter_create(devlink, &mlxsw_core_health_fw_fatal_ops, 2043 0, mlxsw_core); 2044 if (IS_ERR(fw_fatal)) { 2045 dev_err(mlxsw_core->bus_info->dev, "Failed to create fw fatal reporter"); 2046 return PTR_ERR(fw_fatal); 2047 } 2048 mlxsw_core->health.fw_fatal = fw_fatal; 2049 2050 err = mlxsw_core_trap_register(mlxsw_core, &mlxsw_core_health_listener, mlxsw_core); 2051 if (err) 2052 goto err_trap_register; 2053 2054 err = mlxsw_core_health_fw_fatal_config(mlxsw_core, true); 2055 if (err) 2056 goto err_fw_fatal_config; 2057 2058 return 0; 2059 2060 err_fw_fatal_config: 2061 mlxsw_core_trap_unregister(mlxsw_core, &mlxsw_core_health_listener, mlxsw_core); 2062 err_trap_register: 2063 devlink_health_reporter_destroy(mlxsw_core->health.fw_fatal); 2064 return err; 2065 } 2066 2067 static void mlxsw_core_health_fini(struct mlxsw_core *mlxsw_core) 2068 { 2069 if (!mlxsw_core->driver->fw_fatal_enabled) 2070 return; 2071 2072 mlxsw_core_health_fw_fatal_config(mlxsw_core, false); 2073 mlxsw_core_trap_unregister(mlxsw_core, &mlxsw_core_health_listener, mlxsw_core); 2074 /* Make sure there is no more event work scheduled */ 2075 mlxsw_core_flush_owq(); 2076 devlink_health_reporter_destroy(mlxsw_core->health.fw_fatal); 2077 } 2078 2079 static int 2080 __mlxsw_core_bus_device_register(const struct mlxsw_bus_info *mlxsw_bus_info, 2081 const struct mlxsw_bus *mlxsw_bus, 2082 void *bus_priv, bool reload, 2083 struct devlink *devlink, 2084 struct netlink_ext_ack *extack) 2085 { 2086 const char *device_kind = mlxsw_bus_info->device_kind; 2087 struct mlxsw_core *mlxsw_core; 2088 struct mlxsw_driver *mlxsw_driver; 2089 struct mlxsw_res *res; 2090 size_t alloc_size; 2091 int err; 2092 2093 mlxsw_driver = mlxsw_core_driver_get(device_kind); 2094 if (!mlxsw_driver) 2095 return -EINVAL; 2096 2097 if (!reload) { 2098 alloc_size = sizeof(*mlxsw_core) + mlxsw_driver->priv_size; 2099 devlink = devlink_alloc(&mlxsw_devlink_ops, alloc_size, 2100 mlxsw_bus_info->dev); 2101 if (!devlink) { 2102 err = -ENOMEM; 2103 goto err_devlink_alloc; 2104 } 2105 } 2106 2107 mlxsw_core = devlink_priv(devlink); 2108 INIT_LIST_HEAD(&mlxsw_core->rx_listener_list); 2109 INIT_LIST_HEAD(&mlxsw_core->event_listener_list); 2110 mlxsw_core->driver = mlxsw_driver; 2111 mlxsw_core->bus = mlxsw_bus; 2112 mlxsw_core->bus_priv = bus_priv; 2113 mlxsw_core->bus_info = mlxsw_bus_info; 2114 2115 res = mlxsw_driver->res_query_enabled ? &mlxsw_core->res : NULL; 2116 err = mlxsw_bus->init(bus_priv, mlxsw_core, mlxsw_driver->profile, res); 2117 if (err) 2118 goto err_bus_init; 2119 2120 if (mlxsw_driver->resources_register && !reload) { 2121 err = mlxsw_driver->resources_register(mlxsw_core); 2122 if (err) 2123 goto err_register_resources; 2124 } 2125 2126 err = mlxsw_ports_init(mlxsw_core, reload); 2127 if (err) 2128 goto err_ports_init; 2129 2130 if (MLXSW_CORE_RES_VALID(mlxsw_core, MAX_LAG) && 2131 MLXSW_CORE_RES_VALID(mlxsw_core, MAX_LAG_MEMBERS)) { 2132 alloc_size = sizeof(*mlxsw_core->lag.mapping) * 2133 MLXSW_CORE_RES_GET(mlxsw_core, MAX_LAG) * 2134 MLXSW_CORE_RES_GET(mlxsw_core, MAX_LAG_MEMBERS); 2135 mlxsw_core->lag.mapping = kzalloc(alloc_size, GFP_KERNEL); 2136 if (!mlxsw_core->lag.mapping) { 2137 err = -ENOMEM; 2138 goto err_alloc_lag_mapping; 2139 } 2140 } 2141 2142 err = mlxsw_core_trap_groups_set(mlxsw_core); 2143 if (err) 2144 goto err_trap_groups_set; 2145 2146 err = mlxsw_emad_init(mlxsw_core); 2147 if (err) 2148 goto err_emad_init; 2149 2150 if (!reload) { 2151 err = mlxsw_core_params_register(mlxsw_core); 2152 if (err) 2153 goto err_register_params; 2154 } 2155 2156 err = mlxsw_core_fw_rev_validate(mlxsw_core, mlxsw_bus_info, mlxsw_driver->fw_req_rev, 2157 mlxsw_driver->fw_filename); 2158 if (err) 2159 goto err_fw_rev_validate; 2160 2161 err = mlxsw_core_health_init(mlxsw_core); 2162 if (err) 2163 goto err_health_init; 2164 2165 err = mlxsw_hwmon_init(mlxsw_core, mlxsw_bus_info, &mlxsw_core->hwmon); 2166 if (err) 2167 goto err_hwmon_init; 2168 2169 err = mlxsw_thermal_init(mlxsw_core, mlxsw_bus_info, 2170 &mlxsw_core->thermal); 2171 if (err) 2172 goto err_thermal_init; 2173 2174 err = mlxsw_env_init(mlxsw_core, &mlxsw_core->env); 2175 if (err) 2176 goto err_env_init; 2177 2178 if (mlxsw_driver->init) { 2179 err = mlxsw_driver->init(mlxsw_core, mlxsw_bus_info, extack); 2180 if (err) 2181 goto err_driver_init; 2182 } 2183 2184 if (!reload) { 2185 devlink_set_features(devlink, DEVLINK_F_RELOAD); 2186 devlink_register(devlink); 2187 } 2188 return 0; 2189 2190 err_driver_init: 2191 mlxsw_env_fini(mlxsw_core->env); 2192 err_env_init: 2193 mlxsw_thermal_fini(mlxsw_core->thermal); 2194 err_thermal_init: 2195 mlxsw_hwmon_fini(mlxsw_core->hwmon); 2196 err_hwmon_init: 2197 mlxsw_core_health_fini(mlxsw_core); 2198 err_health_init: 2199 err_fw_rev_validate: 2200 if (!reload) 2201 mlxsw_core_params_unregister(mlxsw_core); 2202 err_register_params: 2203 mlxsw_emad_fini(mlxsw_core); 2204 err_emad_init: 2205 err_trap_groups_set: 2206 kfree(mlxsw_core->lag.mapping); 2207 err_alloc_lag_mapping: 2208 mlxsw_ports_fini(mlxsw_core, reload); 2209 err_ports_init: 2210 if (!reload) 2211 devlink_resources_unregister(devlink); 2212 err_register_resources: 2213 mlxsw_bus->fini(bus_priv); 2214 err_bus_init: 2215 if (!reload) 2216 devlink_free(devlink); 2217 err_devlink_alloc: 2218 return err; 2219 } 2220 2221 int mlxsw_core_bus_device_register(const struct mlxsw_bus_info *mlxsw_bus_info, 2222 const struct mlxsw_bus *mlxsw_bus, 2223 void *bus_priv, bool reload, 2224 struct devlink *devlink, 2225 struct netlink_ext_ack *extack) 2226 { 2227 bool called_again = false; 2228 int err; 2229 2230 again: 2231 err = __mlxsw_core_bus_device_register(mlxsw_bus_info, mlxsw_bus, 2232 bus_priv, reload, 2233 devlink, extack); 2234 /* -EAGAIN is returned in case the FW was updated. FW needs 2235 * a reset, so lets try to call __mlxsw_core_bus_device_register() 2236 * again. 2237 */ 2238 if (err == -EAGAIN && !called_again) { 2239 called_again = true; 2240 goto again; 2241 } 2242 2243 return err; 2244 } 2245 EXPORT_SYMBOL(mlxsw_core_bus_device_register); 2246 2247 void mlxsw_core_bus_device_unregister(struct mlxsw_core *mlxsw_core, 2248 bool reload) 2249 { 2250 struct devlink *devlink = priv_to_devlink(mlxsw_core); 2251 2252 if (!reload) 2253 devlink_unregister(devlink); 2254 2255 if (devlink_is_reload_failed(devlink)) { 2256 if (!reload) 2257 /* Only the parts that were not de-initialized in the 2258 * failed reload attempt need to be de-initialized. 2259 */ 2260 goto reload_fail_deinit; 2261 else 2262 return; 2263 } 2264 2265 if (mlxsw_core->driver->fini) 2266 mlxsw_core->driver->fini(mlxsw_core); 2267 mlxsw_env_fini(mlxsw_core->env); 2268 mlxsw_thermal_fini(mlxsw_core->thermal); 2269 mlxsw_hwmon_fini(mlxsw_core->hwmon); 2270 mlxsw_core_health_fini(mlxsw_core); 2271 if (!reload) 2272 mlxsw_core_params_unregister(mlxsw_core); 2273 mlxsw_emad_fini(mlxsw_core); 2274 kfree(mlxsw_core->lag.mapping); 2275 mlxsw_ports_fini(mlxsw_core, reload); 2276 if (!reload) 2277 devlink_resources_unregister(devlink); 2278 mlxsw_core->bus->fini(mlxsw_core->bus_priv); 2279 if (!reload) 2280 devlink_free(devlink); 2281 2282 return; 2283 2284 reload_fail_deinit: 2285 mlxsw_core_params_unregister(mlxsw_core); 2286 devlink_resources_unregister(devlink); 2287 devlink_free(devlink); 2288 } 2289 EXPORT_SYMBOL(mlxsw_core_bus_device_unregister); 2290 2291 bool mlxsw_core_skb_transmit_busy(struct mlxsw_core *mlxsw_core, 2292 const struct mlxsw_tx_info *tx_info) 2293 { 2294 return mlxsw_core->bus->skb_transmit_busy(mlxsw_core->bus_priv, 2295 tx_info); 2296 } 2297 EXPORT_SYMBOL(mlxsw_core_skb_transmit_busy); 2298 2299 int mlxsw_core_skb_transmit(struct mlxsw_core *mlxsw_core, struct sk_buff *skb, 2300 const struct mlxsw_tx_info *tx_info) 2301 { 2302 return mlxsw_core->bus->skb_transmit(mlxsw_core->bus_priv, skb, 2303 tx_info); 2304 } 2305 EXPORT_SYMBOL(mlxsw_core_skb_transmit); 2306 2307 void mlxsw_core_ptp_transmitted(struct mlxsw_core *mlxsw_core, 2308 struct sk_buff *skb, u16 local_port) 2309 { 2310 if (mlxsw_core->driver->ptp_transmitted) 2311 mlxsw_core->driver->ptp_transmitted(mlxsw_core, skb, 2312 local_port); 2313 } 2314 EXPORT_SYMBOL(mlxsw_core_ptp_transmitted); 2315 2316 static bool __is_rx_listener_equal(const struct mlxsw_rx_listener *rxl_a, 2317 const struct mlxsw_rx_listener *rxl_b) 2318 { 2319 return (rxl_a->func == rxl_b->func && 2320 rxl_a->local_port == rxl_b->local_port && 2321 rxl_a->trap_id == rxl_b->trap_id && 2322 rxl_a->mirror_reason == rxl_b->mirror_reason); 2323 } 2324 2325 static struct mlxsw_rx_listener_item * 2326 __find_rx_listener_item(struct mlxsw_core *mlxsw_core, 2327 const struct mlxsw_rx_listener *rxl) 2328 { 2329 struct mlxsw_rx_listener_item *rxl_item; 2330 2331 list_for_each_entry(rxl_item, &mlxsw_core->rx_listener_list, list) { 2332 if (__is_rx_listener_equal(&rxl_item->rxl, rxl)) 2333 return rxl_item; 2334 } 2335 return NULL; 2336 } 2337 2338 int mlxsw_core_rx_listener_register(struct mlxsw_core *mlxsw_core, 2339 const struct mlxsw_rx_listener *rxl, 2340 void *priv, bool enabled) 2341 { 2342 struct mlxsw_rx_listener_item *rxl_item; 2343 2344 rxl_item = __find_rx_listener_item(mlxsw_core, rxl); 2345 if (rxl_item) 2346 return -EEXIST; 2347 rxl_item = kmalloc(sizeof(*rxl_item), GFP_KERNEL); 2348 if (!rxl_item) 2349 return -ENOMEM; 2350 rxl_item->rxl = *rxl; 2351 rxl_item->priv = priv; 2352 rxl_item->enabled = enabled; 2353 2354 list_add_rcu(&rxl_item->list, &mlxsw_core->rx_listener_list); 2355 return 0; 2356 } 2357 EXPORT_SYMBOL(mlxsw_core_rx_listener_register); 2358 2359 void mlxsw_core_rx_listener_unregister(struct mlxsw_core *mlxsw_core, 2360 const struct mlxsw_rx_listener *rxl) 2361 { 2362 struct mlxsw_rx_listener_item *rxl_item; 2363 2364 rxl_item = __find_rx_listener_item(mlxsw_core, rxl); 2365 if (!rxl_item) 2366 return; 2367 list_del_rcu(&rxl_item->list); 2368 synchronize_rcu(); 2369 kfree(rxl_item); 2370 } 2371 EXPORT_SYMBOL(mlxsw_core_rx_listener_unregister); 2372 2373 static void 2374 mlxsw_core_rx_listener_state_set(struct mlxsw_core *mlxsw_core, 2375 const struct mlxsw_rx_listener *rxl, 2376 bool enabled) 2377 { 2378 struct mlxsw_rx_listener_item *rxl_item; 2379 2380 rxl_item = __find_rx_listener_item(mlxsw_core, rxl); 2381 if (WARN_ON(!rxl_item)) 2382 return; 2383 rxl_item->enabled = enabled; 2384 } 2385 2386 static void mlxsw_core_event_listener_func(struct sk_buff *skb, u16 local_port, 2387 void *priv) 2388 { 2389 struct mlxsw_event_listener_item *event_listener_item = priv; 2390 struct mlxsw_core *mlxsw_core; 2391 struct mlxsw_reg_info reg; 2392 char *payload; 2393 char *reg_tlv; 2394 char *op_tlv; 2395 2396 mlxsw_core = event_listener_item->mlxsw_core; 2397 trace_devlink_hwmsg(priv_to_devlink(mlxsw_core), true, 0, 2398 skb->data, skb->len); 2399 2400 mlxsw_emad_tlv_parse(skb); 2401 op_tlv = mlxsw_emad_op_tlv(skb); 2402 reg_tlv = mlxsw_emad_reg_tlv(skb); 2403 2404 reg.id = mlxsw_emad_op_tlv_register_id_get(op_tlv); 2405 reg.len = (mlxsw_emad_reg_tlv_len_get(reg_tlv) - 1) * sizeof(u32); 2406 payload = mlxsw_emad_reg_payload(reg_tlv); 2407 event_listener_item->el.func(®, payload, event_listener_item->priv); 2408 dev_kfree_skb(skb); 2409 } 2410 2411 static bool __is_event_listener_equal(const struct mlxsw_event_listener *el_a, 2412 const struct mlxsw_event_listener *el_b) 2413 { 2414 return (el_a->func == el_b->func && 2415 el_a->trap_id == el_b->trap_id); 2416 } 2417 2418 static struct mlxsw_event_listener_item * 2419 __find_event_listener_item(struct mlxsw_core *mlxsw_core, 2420 const struct mlxsw_event_listener *el) 2421 { 2422 struct mlxsw_event_listener_item *el_item; 2423 2424 list_for_each_entry(el_item, &mlxsw_core->event_listener_list, list) { 2425 if (__is_event_listener_equal(&el_item->el, el)) 2426 return el_item; 2427 } 2428 return NULL; 2429 } 2430 2431 int mlxsw_core_event_listener_register(struct mlxsw_core *mlxsw_core, 2432 const struct mlxsw_event_listener *el, 2433 void *priv) 2434 { 2435 int err; 2436 struct mlxsw_event_listener_item *el_item; 2437 const struct mlxsw_rx_listener rxl = { 2438 .func = mlxsw_core_event_listener_func, 2439 .local_port = MLXSW_PORT_DONT_CARE, 2440 .trap_id = el->trap_id, 2441 }; 2442 2443 el_item = __find_event_listener_item(mlxsw_core, el); 2444 if (el_item) 2445 return -EEXIST; 2446 el_item = kmalloc(sizeof(*el_item), GFP_KERNEL); 2447 if (!el_item) 2448 return -ENOMEM; 2449 el_item->mlxsw_core = mlxsw_core; 2450 el_item->el = *el; 2451 el_item->priv = priv; 2452 2453 err = mlxsw_core_rx_listener_register(mlxsw_core, &rxl, el_item, true); 2454 if (err) 2455 goto err_rx_listener_register; 2456 2457 /* No reason to save item if we did not manage to register an RX 2458 * listener for it. 2459 */ 2460 list_add_rcu(&el_item->list, &mlxsw_core->event_listener_list); 2461 2462 return 0; 2463 2464 err_rx_listener_register: 2465 kfree(el_item); 2466 return err; 2467 } 2468 EXPORT_SYMBOL(mlxsw_core_event_listener_register); 2469 2470 void mlxsw_core_event_listener_unregister(struct mlxsw_core *mlxsw_core, 2471 const struct mlxsw_event_listener *el) 2472 { 2473 struct mlxsw_event_listener_item *el_item; 2474 const struct mlxsw_rx_listener rxl = { 2475 .func = mlxsw_core_event_listener_func, 2476 .local_port = MLXSW_PORT_DONT_CARE, 2477 .trap_id = el->trap_id, 2478 }; 2479 2480 el_item = __find_event_listener_item(mlxsw_core, el); 2481 if (!el_item) 2482 return; 2483 mlxsw_core_rx_listener_unregister(mlxsw_core, &rxl); 2484 list_del(&el_item->list); 2485 kfree(el_item); 2486 } 2487 EXPORT_SYMBOL(mlxsw_core_event_listener_unregister); 2488 2489 static int mlxsw_core_listener_register(struct mlxsw_core *mlxsw_core, 2490 const struct mlxsw_listener *listener, 2491 void *priv, bool enabled) 2492 { 2493 if (listener->is_event) { 2494 WARN_ON(!enabled); 2495 return mlxsw_core_event_listener_register(mlxsw_core, 2496 &listener->event_listener, 2497 priv); 2498 } else { 2499 return mlxsw_core_rx_listener_register(mlxsw_core, 2500 &listener->rx_listener, 2501 priv, enabled); 2502 } 2503 } 2504 2505 static void mlxsw_core_listener_unregister(struct mlxsw_core *mlxsw_core, 2506 const struct mlxsw_listener *listener, 2507 void *priv) 2508 { 2509 if (listener->is_event) 2510 mlxsw_core_event_listener_unregister(mlxsw_core, 2511 &listener->event_listener); 2512 else 2513 mlxsw_core_rx_listener_unregister(mlxsw_core, 2514 &listener->rx_listener); 2515 } 2516 2517 int mlxsw_core_trap_register(struct mlxsw_core *mlxsw_core, 2518 const struct mlxsw_listener *listener, void *priv) 2519 { 2520 enum mlxsw_reg_htgt_trap_group trap_group; 2521 enum mlxsw_reg_hpkt_action action; 2522 char hpkt_pl[MLXSW_REG_HPKT_LEN]; 2523 int err; 2524 2525 err = mlxsw_core_listener_register(mlxsw_core, listener, priv, 2526 listener->enabled_on_register); 2527 if (err) 2528 return err; 2529 2530 action = listener->enabled_on_register ? listener->en_action : 2531 listener->dis_action; 2532 trap_group = listener->enabled_on_register ? listener->en_trap_group : 2533 listener->dis_trap_group; 2534 mlxsw_reg_hpkt_pack(hpkt_pl, action, listener->trap_id, 2535 trap_group, listener->is_ctrl); 2536 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(hpkt), hpkt_pl); 2537 if (err) 2538 goto err_trap_set; 2539 2540 return 0; 2541 2542 err_trap_set: 2543 mlxsw_core_listener_unregister(mlxsw_core, listener, priv); 2544 return err; 2545 } 2546 EXPORT_SYMBOL(mlxsw_core_trap_register); 2547 2548 void mlxsw_core_trap_unregister(struct mlxsw_core *mlxsw_core, 2549 const struct mlxsw_listener *listener, 2550 void *priv) 2551 { 2552 char hpkt_pl[MLXSW_REG_HPKT_LEN]; 2553 2554 if (!listener->is_event) { 2555 mlxsw_reg_hpkt_pack(hpkt_pl, listener->dis_action, 2556 listener->trap_id, listener->dis_trap_group, 2557 listener->is_ctrl); 2558 mlxsw_reg_write(mlxsw_core, MLXSW_REG(hpkt), hpkt_pl); 2559 } 2560 2561 mlxsw_core_listener_unregister(mlxsw_core, listener, priv); 2562 } 2563 EXPORT_SYMBOL(mlxsw_core_trap_unregister); 2564 2565 int mlxsw_core_traps_register(struct mlxsw_core *mlxsw_core, 2566 const struct mlxsw_listener *listeners, 2567 size_t listeners_count, void *priv) 2568 { 2569 int i, err; 2570 2571 for (i = 0; i < listeners_count; i++) { 2572 err = mlxsw_core_trap_register(mlxsw_core, 2573 &listeners[i], 2574 priv); 2575 if (err) 2576 goto err_listener_register; 2577 } 2578 return 0; 2579 2580 err_listener_register: 2581 for (i--; i >= 0; i--) { 2582 mlxsw_core_trap_unregister(mlxsw_core, 2583 &listeners[i], 2584 priv); 2585 } 2586 return err; 2587 } 2588 EXPORT_SYMBOL(mlxsw_core_traps_register); 2589 2590 void mlxsw_core_traps_unregister(struct mlxsw_core *mlxsw_core, 2591 const struct mlxsw_listener *listeners, 2592 size_t listeners_count, void *priv) 2593 { 2594 int i; 2595 2596 for (i = 0; i < listeners_count; i++) { 2597 mlxsw_core_trap_unregister(mlxsw_core, 2598 &listeners[i], 2599 priv); 2600 } 2601 } 2602 EXPORT_SYMBOL(mlxsw_core_traps_unregister); 2603 2604 int mlxsw_core_trap_state_set(struct mlxsw_core *mlxsw_core, 2605 const struct mlxsw_listener *listener, 2606 bool enabled) 2607 { 2608 enum mlxsw_reg_htgt_trap_group trap_group; 2609 enum mlxsw_reg_hpkt_action action; 2610 char hpkt_pl[MLXSW_REG_HPKT_LEN]; 2611 int err; 2612 2613 /* Not supported for event listener */ 2614 if (WARN_ON(listener->is_event)) 2615 return -EINVAL; 2616 2617 action = enabled ? listener->en_action : listener->dis_action; 2618 trap_group = enabled ? listener->en_trap_group : 2619 listener->dis_trap_group; 2620 mlxsw_reg_hpkt_pack(hpkt_pl, action, listener->trap_id, 2621 trap_group, listener->is_ctrl); 2622 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(hpkt), hpkt_pl); 2623 if (err) 2624 return err; 2625 2626 mlxsw_core_rx_listener_state_set(mlxsw_core, &listener->rx_listener, 2627 enabled); 2628 return 0; 2629 } 2630 EXPORT_SYMBOL(mlxsw_core_trap_state_set); 2631 2632 static u64 mlxsw_core_tid_get(struct mlxsw_core *mlxsw_core) 2633 { 2634 return atomic64_inc_return(&mlxsw_core->emad.tid); 2635 } 2636 2637 static int mlxsw_core_reg_access_emad(struct mlxsw_core *mlxsw_core, 2638 const struct mlxsw_reg_info *reg, 2639 char *payload, 2640 enum mlxsw_core_reg_access_type type, 2641 struct list_head *bulk_list, 2642 mlxsw_reg_trans_cb_t *cb, 2643 unsigned long cb_priv) 2644 { 2645 u64 tid = mlxsw_core_tid_get(mlxsw_core); 2646 struct mlxsw_reg_trans *trans; 2647 int err; 2648 2649 trans = kzalloc(sizeof(*trans), GFP_KERNEL); 2650 if (!trans) 2651 return -ENOMEM; 2652 2653 err = mlxsw_emad_reg_access(mlxsw_core, reg, payload, type, trans, 2654 bulk_list, cb, cb_priv, tid); 2655 if (err) { 2656 kfree_rcu(trans, rcu); 2657 return err; 2658 } 2659 return 0; 2660 } 2661 2662 int mlxsw_reg_trans_query(struct mlxsw_core *mlxsw_core, 2663 const struct mlxsw_reg_info *reg, char *payload, 2664 struct list_head *bulk_list, 2665 mlxsw_reg_trans_cb_t *cb, unsigned long cb_priv) 2666 { 2667 return mlxsw_core_reg_access_emad(mlxsw_core, reg, payload, 2668 MLXSW_CORE_REG_ACCESS_TYPE_QUERY, 2669 bulk_list, cb, cb_priv); 2670 } 2671 EXPORT_SYMBOL(mlxsw_reg_trans_query); 2672 2673 int mlxsw_reg_trans_write(struct mlxsw_core *mlxsw_core, 2674 const struct mlxsw_reg_info *reg, char *payload, 2675 struct list_head *bulk_list, 2676 mlxsw_reg_trans_cb_t *cb, unsigned long cb_priv) 2677 { 2678 return mlxsw_core_reg_access_emad(mlxsw_core, reg, payload, 2679 MLXSW_CORE_REG_ACCESS_TYPE_WRITE, 2680 bulk_list, cb, cb_priv); 2681 } 2682 EXPORT_SYMBOL(mlxsw_reg_trans_write); 2683 2684 #define MLXSW_REG_TRANS_ERR_STRING_SIZE 256 2685 2686 static int mlxsw_reg_trans_wait(struct mlxsw_reg_trans *trans) 2687 { 2688 char err_string[MLXSW_REG_TRANS_ERR_STRING_SIZE]; 2689 struct mlxsw_core *mlxsw_core = trans->core; 2690 int err; 2691 2692 wait_for_completion(&trans->completion); 2693 cancel_delayed_work_sync(&trans->timeout_dw); 2694 err = trans->err; 2695 2696 if (trans->retries) 2697 dev_warn(mlxsw_core->bus_info->dev, "EMAD retries (%d/%d) (tid=%llx)\n", 2698 trans->retries, MLXSW_EMAD_MAX_RETRY, trans->tid); 2699 if (err) { 2700 dev_err(mlxsw_core->bus_info->dev, "EMAD reg access failed (tid=%llx,reg_id=%x(%s),type=%s,status=%x(%s))\n", 2701 trans->tid, trans->reg->id, 2702 mlxsw_reg_id_str(trans->reg->id), 2703 mlxsw_core_reg_access_type_str(trans->type), 2704 trans->emad_status, 2705 mlxsw_emad_op_tlv_status_str(trans->emad_status)); 2706 2707 snprintf(err_string, MLXSW_REG_TRANS_ERR_STRING_SIZE, 2708 "(tid=%llx,reg_id=%x(%s)) %s (%s)\n", trans->tid, 2709 trans->reg->id, mlxsw_reg_id_str(trans->reg->id), 2710 mlxsw_emad_op_tlv_status_str(trans->emad_status), 2711 trans->emad_err_string ? trans->emad_err_string : ""); 2712 2713 trace_devlink_hwerr(priv_to_devlink(mlxsw_core), 2714 trans->emad_status, err_string); 2715 2716 kfree(trans->emad_err_string); 2717 } 2718 2719 list_del(&trans->bulk_list); 2720 kfree_rcu(trans, rcu); 2721 return err; 2722 } 2723 2724 int mlxsw_reg_trans_bulk_wait(struct list_head *bulk_list) 2725 { 2726 struct mlxsw_reg_trans *trans; 2727 struct mlxsw_reg_trans *tmp; 2728 int sum_err = 0; 2729 int err; 2730 2731 list_for_each_entry_safe(trans, tmp, bulk_list, bulk_list) { 2732 err = mlxsw_reg_trans_wait(trans); 2733 if (err && sum_err == 0) 2734 sum_err = err; /* first error to be returned */ 2735 } 2736 return sum_err; 2737 } 2738 EXPORT_SYMBOL(mlxsw_reg_trans_bulk_wait); 2739 2740 static int mlxsw_core_reg_access_cmd(struct mlxsw_core *mlxsw_core, 2741 const struct mlxsw_reg_info *reg, 2742 char *payload, 2743 enum mlxsw_core_reg_access_type type) 2744 { 2745 enum mlxsw_emad_op_tlv_status status; 2746 int err, n_retry; 2747 bool reset_ok; 2748 char *in_mbox, *out_mbox, *tmp; 2749 2750 dev_dbg(mlxsw_core->bus_info->dev, "Reg cmd access (reg_id=%x(%s),type=%s)\n", 2751 reg->id, mlxsw_reg_id_str(reg->id), 2752 mlxsw_core_reg_access_type_str(type)); 2753 2754 in_mbox = mlxsw_cmd_mbox_alloc(); 2755 if (!in_mbox) 2756 return -ENOMEM; 2757 2758 out_mbox = mlxsw_cmd_mbox_alloc(); 2759 if (!out_mbox) { 2760 err = -ENOMEM; 2761 goto free_in_mbox; 2762 } 2763 2764 mlxsw_emad_pack_op_tlv(in_mbox, reg, type, 2765 mlxsw_core_tid_get(mlxsw_core)); 2766 tmp = in_mbox + MLXSW_EMAD_OP_TLV_LEN * sizeof(u32); 2767 mlxsw_emad_pack_reg_tlv(tmp, reg, payload); 2768 2769 /* There is a special treatment needed for MRSR (reset) register. 2770 * The command interface will return error after the command 2771 * is executed, so tell the lower layer to expect it 2772 * and cope accordingly. 2773 */ 2774 reset_ok = reg->id == MLXSW_REG_MRSR_ID; 2775 2776 n_retry = 0; 2777 retry: 2778 err = mlxsw_cmd_access_reg(mlxsw_core, reset_ok, in_mbox, out_mbox); 2779 if (!err) { 2780 err = mlxsw_emad_process_status(out_mbox, &status); 2781 if (err) { 2782 if (err == -EAGAIN && n_retry++ < MLXSW_EMAD_MAX_RETRY) 2783 goto retry; 2784 dev_err(mlxsw_core->bus_info->dev, "Reg cmd access status failed (status=%x(%s))\n", 2785 status, mlxsw_emad_op_tlv_status_str(status)); 2786 } 2787 } 2788 2789 if (!err) 2790 memcpy(payload, mlxsw_emad_reg_payload_cmd(out_mbox), 2791 reg->len); 2792 2793 mlxsw_cmd_mbox_free(out_mbox); 2794 free_in_mbox: 2795 mlxsw_cmd_mbox_free(in_mbox); 2796 if (err) 2797 dev_err(mlxsw_core->bus_info->dev, "Reg cmd access failed (reg_id=%x(%s),type=%s)\n", 2798 reg->id, mlxsw_reg_id_str(reg->id), 2799 mlxsw_core_reg_access_type_str(type)); 2800 return err; 2801 } 2802 2803 static void mlxsw_core_reg_access_cb(struct mlxsw_core *mlxsw_core, 2804 char *payload, size_t payload_len, 2805 unsigned long cb_priv) 2806 { 2807 char *orig_payload = (char *) cb_priv; 2808 2809 memcpy(orig_payload, payload, payload_len); 2810 } 2811 2812 static int mlxsw_core_reg_access(struct mlxsw_core *mlxsw_core, 2813 const struct mlxsw_reg_info *reg, 2814 char *payload, 2815 enum mlxsw_core_reg_access_type type) 2816 { 2817 LIST_HEAD(bulk_list); 2818 int err; 2819 2820 /* During initialization EMAD interface is not available to us, 2821 * so we default to command interface. We switch to EMAD interface 2822 * after setting the appropriate traps. 2823 */ 2824 if (!mlxsw_core->emad.use_emad) 2825 return mlxsw_core_reg_access_cmd(mlxsw_core, reg, 2826 payload, type); 2827 2828 err = mlxsw_core_reg_access_emad(mlxsw_core, reg, 2829 payload, type, &bulk_list, 2830 mlxsw_core_reg_access_cb, 2831 (unsigned long) payload); 2832 if (err) 2833 return err; 2834 return mlxsw_reg_trans_bulk_wait(&bulk_list); 2835 } 2836 2837 int mlxsw_reg_query(struct mlxsw_core *mlxsw_core, 2838 const struct mlxsw_reg_info *reg, char *payload) 2839 { 2840 return mlxsw_core_reg_access(mlxsw_core, reg, payload, 2841 MLXSW_CORE_REG_ACCESS_TYPE_QUERY); 2842 } 2843 EXPORT_SYMBOL(mlxsw_reg_query); 2844 2845 int mlxsw_reg_write(struct mlxsw_core *mlxsw_core, 2846 const struct mlxsw_reg_info *reg, char *payload) 2847 { 2848 return mlxsw_core_reg_access(mlxsw_core, reg, payload, 2849 MLXSW_CORE_REG_ACCESS_TYPE_WRITE); 2850 } 2851 EXPORT_SYMBOL(mlxsw_reg_write); 2852 2853 void mlxsw_core_skb_receive(struct mlxsw_core *mlxsw_core, struct sk_buff *skb, 2854 struct mlxsw_rx_info *rx_info) 2855 { 2856 struct mlxsw_rx_listener_item *rxl_item; 2857 const struct mlxsw_rx_listener *rxl; 2858 u16 local_port; 2859 bool found = false; 2860 2861 if (rx_info->is_lag) { 2862 dev_dbg_ratelimited(mlxsw_core->bus_info->dev, "%s: lag_id = %d, lag_port_index = 0x%x\n", 2863 __func__, rx_info->u.lag_id, 2864 rx_info->trap_id); 2865 /* Upper layer does not care if the skb came from LAG or not, 2866 * so just get the local_port for the lag port and push it up. 2867 */ 2868 local_port = mlxsw_core_lag_mapping_get(mlxsw_core, 2869 rx_info->u.lag_id, 2870 rx_info->lag_port_index); 2871 } else { 2872 local_port = rx_info->u.sys_port; 2873 } 2874 2875 dev_dbg_ratelimited(mlxsw_core->bus_info->dev, "%s: local_port = %d, trap_id = 0x%x\n", 2876 __func__, local_port, rx_info->trap_id); 2877 2878 if ((rx_info->trap_id >= MLXSW_TRAP_ID_MAX) || 2879 (local_port >= mlxsw_core->max_ports)) 2880 goto drop; 2881 2882 rcu_read_lock(); 2883 list_for_each_entry_rcu(rxl_item, &mlxsw_core->rx_listener_list, list) { 2884 rxl = &rxl_item->rxl; 2885 if ((rxl->local_port == MLXSW_PORT_DONT_CARE || 2886 rxl->local_port == local_port) && 2887 rxl->trap_id == rx_info->trap_id && 2888 rxl->mirror_reason == rx_info->mirror_reason) { 2889 if (rxl_item->enabled) 2890 found = true; 2891 break; 2892 } 2893 } 2894 if (!found) { 2895 rcu_read_unlock(); 2896 goto drop; 2897 } 2898 2899 rxl->func(skb, local_port, rxl_item->priv); 2900 rcu_read_unlock(); 2901 return; 2902 2903 drop: 2904 dev_kfree_skb(skb); 2905 } 2906 EXPORT_SYMBOL(mlxsw_core_skb_receive); 2907 2908 static int mlxsw_core_lag_mapping_index(struct mlxsw_core *mlxsw_core, 2909 u16 lag_id, u8 port_index) 2910 { 2911 return MLXSW_CORE_RES_GET(mlxsw_core, MAX_LAG_MEMBERS) * lag_id + 2912 port_index; 2913 } 2914 2915 void mlxsw_core_lag_mapping_set(struct mlxsw_core *mlxsw_core, 2916 u16 lag_id, u8 port_index, u16 local_port) 2917 { 2918 int index = mlxsw_core_lag_mapping_index(mlxsw_core, 2919 lag_id, port_index); 2920 2921 mlxsw_core->lag.mapping[index] = local_port; 2922 } 2923 EXPORT_SYMBOL(mlxsw_core_lag_mapping_set); 2924 2925 u16 mlxsw_core_lag_mapping_get(struct mlxsw_core *mlxsw_core, 2926 u16 lag_id, u8 port_index) 2927 { 2928 int index = mlxsw_core_lag_mapping_index(mlxsw_core, 2929 lag_id, port_index); 2930 2931 return mlxsw_core->lag.mapping[index]; 2932 } 2933 EXPORT_SYMBOL(mlxsw_core_lag_mapping_get); 2934 2935 void mlxsw_core_lag_mapping_clear(struct mlxsw_core *mlxsw_core, 2936 u16 lag_id, u16 local_port) 2937 { 2938 int i; 2939 2940 for (i = 0; i < MLXSW_CORE_RES_GET(mlxsw_core, MAX_LAG_MEMBERS); i++) { 2941 int index = mlxsw_core_lag_mapping_index(mlxsw_core, 2942 lag_id, i); 2943 2944 if (mlxsw_core->lag.mapping[index] == local_port) 2945 mlxsw_core->lag.mapping[index] = 0; 2946 } 2947 } 2948 EXPORT_SYMBOL(mlxsw_core_lag_mapping_clear); 2949 2950 bool mlxsw_core_res_valid(struct mlxsw_core *mlxsw_core, 2951 enum mlxsw_res_id res_id) 2952 { 2953 return mlxsw_res_valid(&mlxsw_core->res, res_id); 2954 } 2955 EXPORT_SYMBOL(mlxsw_core_res_valid); 2956 2957 u64 mlxsw_core_res_get(struct mlxsw_core *mlxsw_core, 2958 enum mlxsw_res_id res_id) 2959 { 2960 return mlxsw_res_get(&mlxsw_core->res, res_id); 2961 } 2962 EXPORT_SYMBOL(mlxsw_core_res_get); 2963 2964 static int __mlxsw_core_port_init(struct mlxsw_core *mlxsw_core, u16 local_port, 2965 enum devlink_port_flavour flavour, 2966 u32 port_number, bool split, 2967 u32 split_port_subnumber, 2968 bool splittable, u32 lanes, 2969 const unsigned char *switch_id, 2970 unsigned char switch_id_len) 2971 { 2972 struct devlink *devlink = priv_to_devlink(mlxsw_core); 2973 struct mlxsw_core_port *mlxsw_core_port = 2974 &mlxsw_core->ports[local_port]; 2975 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 2976 struct devlink_port_attrs attrs = {}; 2977 int err; 2978 2979 attrs.split = split; 2980 attrs.lanes = lanes; 2981 attrs.splittable = splittable; 2982 attrs.flavour = flavour; 2983 attrs.phys.port_number = port_number; 2984 attrs.phys.split_subport_number = split_port_subnumber; 2985 memcpy(attrs.switch_id.id, switch_id, switch_id_len); 2986 attrs.switch_id.id_len = switch_id_len; 2987 mlxsw_core_port->local_port = local_port; 2988 devlink_port_attrs_set(devlink_port, &attrs); 2989 err = devlink_port_register(devlink, devlink_port, local_port); 2990 if (err) 2991 memset(mlxsw_core_port, 0, sizeof(*mlxsw_core_port)); 2992 return err; 2993 } 2994 2995 static void __mlxsw_core_port_fini(struct mlxsw_core *mlxsw_core, u16 local_port) 2996 { 2997 struct mlxsw_core_port *mlxsw_core_port = 2998 &mlxsw_core->ports[local_port]; 2999 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 3000 3001 devlink_port_unregister(devlink_port); 3002 memset(mlxsw_core_port, 0, sizeof(*mlxsw_core_port)); 3003 } 3004 3005 int mlxsw_core_port_init(struct mlxsw_core *mlxsw_core, u16 local_port, 3006 u32 port_number, bool split, 3007 u32 split_port_subnumber, 3008 bool splittable, u32 lanes, 3009 const unsigned char *switch_id, 3010 unsigned char switch_id_len) 3011 { 3012 int err; 3013 3014 err = __mlxsw_core_port_init(mlxsw_core, local_port, 3015 DEVLINK_PORT_FLAVOUR_PHYSICAL, 3016 port_number, split, split_port_subnumber, 3017 splittable, lanes, 3018 switch_id, switch_id_len); 3019 if (err) 3020 return err; 3021 3022 atomic_inc(&mlxsw_core->active_ports_count); 3023 return 0; 3024 } 3025 EXPORT_SYMBOL(mlxsw_core_port_init); 3026 3027 void mlxsw_core_port_fini(struct mlxsw_core *mlxsw_core, u16 local_port) 3028 { 3029 atomic_dec(&mlxsw_core->active_ports_count); 3030 3031 __mlxsw_core_port_fini(mlxsw_core, local_port); 3032 } 3033 EXPORT_SYMBOL(mlxsw_core_port_fini); 3034 3035 int mlxsw_core_cpu_port_init(struct mlxsw_core *mlxsw_core, 3036 void *port_driver_priv, 3037 const unsigned char *switch_id, 3038 unsigned char switch_id_len) 3039 { 3040 struct mlxsw_core_port *mlxsw_core_port = 3041 &mlxsw_core->ports[MLXSW_PORT_CPU_PORT]; 3042 int err; 3043 3044 err = __mlxsw_core_port_init(mlxsw_core, MLXSW_PORT_CPU_PORT, 3045 DEVLINK_PORT_FLAVOUR_CPU, 3046 0, false, 0, false, 0, 3047 switch_id, switch_id_len); 3048 if (err) 3049 return err; 3050 3051 mlxsw_core_port->port_driver_priv = port_driver_priv; 3052 return 0; 3053 } 3054 EXPORT_SYMBOL(mlxsw_core_cpu_port_init); 3055 3056 void mlxsw_core_cpu_port_fini(struct mlxsw_core *mlxsw_core) 3057 { 3058 __mlxsw_core_port_fini(mlxsw_core, MLXSW_PORT_CPU_PORT); 3059 } 3060 EXPORT_SYMBOL(mlxsw_core_cpu_port_fini); 3061 3062 void mlxsw_core_port_eth_set(struct mlxsw_core *mlxsw_core, u16 local_port, 3063 void *port_driver_priv, struct net_device *dev) 3064 { 3065 struct mlxsw_core_port *mlxsw_core_port = 3066 &mlxsw_core->ports[local_port]; 3067 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 3068 3069 mlxsw_core_port->port_driver_priv = port_driver_priv; 3070 devlink_port_type_eth_set(devlink_port, dev); 3071 } 3072 EXPORT_SYMBOL(mlxsw_core_port_eth_set); 3073 3074 void mlxsw_core_port_ib_set(struct mlxsw_core *mlxsw_core, u16 local_port, 3075 void *port_driver_priv) 3076 { 3077 struct mlxsw_core_port *mlxsw_core_port = 3078 &mlxsw_core->ports[local_port]; 3079 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 3080 3081 mlxsw_core_port->port_driver_priv = port_driver_priv; 3082 devlink_port_type_ib_set(devlink_port, NULL); 3083 } 3084 EXPORT_SYMBOL(mlxsw_core_port_ib_set); 3085 3086 void mlxsw_core_port_clear(struct mlxsw_core *mlxsw_core, u16 local_port, 3087 void *port_driver_priv) 3088 { 3089 struct mlxsw_core_port *mlxsw_core_port = 3090 &mlxsw_core->ports[local_port]; 3091 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 3092 3093 mlxsw_core_port->port_driver_priv = port_driver_priv; 3094 devlink_port_type_clear(devlink_port); 3095 } 3096 EXPORT_SYMBOL(mlxsw_core_port_clear); 3097 3098 enum devlink_port_type mlxsw_core_port_type_get(struct mlxsw_core *mlxsw_core, 3099 u16 local_port) 3100 { 3101 struct mlxsw_core_port *mlxsw_core_port = 3102 &mlxsw_core->ports[local_port]; 3103 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 3104 3105 return devlink_port->type; 3106 } 3107 EXPORT_SYMBOL(mlxsw_core_port_type_get); 3108 3109 3110 struct devlink_port * 3111 mlxsw_core_port_devlink_port_get(struct mlxsw_core *mlxsw_core, 3112 u16 local_port) 3113 { 3114 struct mlxsw_core_port *mlxsw_core_port = 3115 &mlxsw_core->ports[local_port]; 3116 struct devlink_port *devlink_port = &mlxsw_core_port->devlink_port; 3117 3118 return devlink_port; 3119 } 3120 EXPORT_SYMBOL(mlxsw_core_port_devlink_port_get); 3121 3122 bool mlxsw_core_port_is_xm(const struct mlxsw_core *mlxsw_core, u16 local_port) 3123 { 3124 const struct mlxsw_bus_info *bus_info = mlxsw_core->bus_info; 3125 int i; 3126 3127 for (i = 0; i < bus_info->xm_local_ports_count; i++) 3128 if (bus_info->xm_local_ports[i] == local_port) 3129 return true; 3130 return false; 3131 } 3132 EXPORT_SYMBOL(mlxsw_core_port_is_xm); 3133 3134 struct mlxsw_env *mlxsw_core_env(const struct mlxsw_core *mlxsw_core) 3135 { 3136 return mlxsw_core->env; 3137 } 3138 3139 static void mlxsw_core_buf_dump_dbg(struct mlxsw_core *mlxsw_core, 3140 const char *buf, size_t size) 3141 { 3142 __be32 *m = (__be32 *) buf; 3143 int i; 3144 int count = size / sizeof(__be32); 3145 3146 for (i = count - 1; i >= 0; i--) 3147 if (m[i]) 3148 break; 3149 i++; 3150 count = i ? i : 1; 3151 for (i = 0; i < count; i += 4) 3152 dev_dbg(mlxsw_core->bus_info->dev, "%04x - %08x %08x %08x %08x\n", 3153 i * 4, be32_to_cpu(m[i]), be32_to_cpu(m[i + 1]), 3154 be32_to_cpu(m[i + 2]), be32_to_cpu(m[i + 3])); 3155 } 3156 3157 int mlxsw_cmd_exec(struct mlxsw_core *mlxsw_core, u16 opcode, u8 opcode_mod, 3158 u32 in_mod, bool out_mbox_direct, bool reset_ok, 3159 char *in_mbox, size_t in_mbox_size, 3160 char *out_mbox, size_t out_mbox_size) 3161 { 3162 u8 status; 3163 int err; 3164 3165 BUG_ON(in_mbox_size % sizeof(u32) || out_mbox_size % sizeof(u32)); 3166 if (!mlxsw_core->bus->cmd_exec) 3167 return -EOPNOTSUPP; 3168 3169 dev_dbg(mlxsw_core->bus_info->dev, "Cmd exec (opcode=%x(%s),opcode_mod=%x,in_mod=%x)\n", 3170 opcode, mlxsw_cmd_opcode_str(opcode), opcode_mod, in_mod); 3171 if (in_mbox) { 3172 dev_dbg(mlxsw_core->bus_info->dev, "Input mailbox:\n"); 3173 mlxsw_core_buf_dump_dbg(mlxsw_core, in_mbox, in_mbox_size); 3174 } 3175 3176 err = mlxsw_core->bus->cmd_exec(mlxsw_core->bus_priv, opcode, 3177 opcode_mod, in_mod, out_mbox_direct, 3178 in_mbox, in_mbox_size, 3179 out_mbox, out_mbox_size, &status); 3180 3181 if (!err && out_mbox) { 3182 dev_dbg(mlxsw_core->bus_info->dev, "Output mailbox:\n"); 3183 mlxsw_core_buf_dump_dbg(mlxsw_core, out_mbox, out_mbox_size); 3184 } 3185 3186 if (reset_ok && err == -EIO && 3187 status == MLXSW_CMD_STATUS_RUNNING_RESET) { 3188 err = 0; 3189 } else if (err == -EIO && status != MLXSW_CMD_STATUS_OK) { 3190 dev_err(mlxsw_core->bus_info->dev, "Cmd exec failed (opcode=%x(%s),opcode_mod=%x,in_mod=%x,status=%x(%s))\n", 3191 opcode, mlxsw_cmd_opcode_str(opcode), opcode_mod, 3192 in_mod, status, mlxsw_cmd_status_str(status)); 3193 } else if (err == -ETIMEDOUT) { 3194 dev_err(mlxsw_core->bus_info->dev, "Cmd exec timed-out (opcode=%x(%s),opcode_mod=%x,in_mod=%x)\n", 3195 opcode, mlxsw_cmd_opcode_str(opcode), opcode_mod, 3196 in_mod); 3197 } 3198 3199 return err; 3200 } 3201 EXPORT_SYMBOL(mlxsw_cmd_exec); 3202 3203 int mlxsw_core_schedule_dw(struct delayed_work *dwork, unsigned long delay) 3204 { 3205 return queue_delayed_work(mlxsw_wq, dwork, delay); 3206 } 3207 EXPORT_SYMBOL(mlxsw_core_schedule_dw); 3208 3209 bool mlxsw_core_schedule_work(struct work_struct *work) 3210 { 3211 return queue_work(mlxsw_owq, work); 3212 } 3213 EXPORT_SYMBOL(mlxsw_core_schedule_work); 3214 3215 void mlxsw_core_flush_owq(void) 3216 { 3217 flush_workqueue(mlxsw_owq); 3218 } 3219 EXPORT_SYMBOL(mlxsw_core_flush_owq); 3220 3221 int mlxsw_core_kvd_sizes_get(struct mlxsw_core *mlxsw_core, 3222 const struct mlxsw_config_profile *profile, 3223 u64 *p_single_size, u64 *p_double_size, 3224 u64 *p_linear_size) 3225 { 3226 struct mlxsw_driver *driver = mlxsw_core->driver; 3227 3228 if (!driver->kvd_sizes_get) 3229 return -EINVAL; 3230 3231 return driver->kvd_sizes_get(mlxsw_core, profile, 3232 p_single_size, p_double_size, 3233 p_linear_size); 3234 } 3235 EXPORT_SYMBOL(mlxsw_core_kvd_sizes_get); 3236 3237 int mlxsw_core_resources_query(struct mlxsw_core *mlxsw_core, char *mbox, 3238 struct mlxsw_res *res) 3239 { 3240 int index, i; 3241 u64 data; 3242 u16 id; 3243 int err; 3244 3245 if (!res) 3246 return 0; 3247 3248 mlxsw_cmd_mbox_zero(mbox); 3249 3250 for (index = 0; index < MLXSW_CMD_QUERY_RESOURCES_MAX_QUERIES; 3251 index++) { 3252 err = mlxsw_cmd_query_resources(mlxsw_core, mbox, index); 3253 if (err) 3254 return err; 3255 3256 for (i = 0; i < MLXSW_CMD_QUERY_RESOURCES_PER_QUERY; i++) { 3257 id = mlxsw_cmd_mbox_query_resource_id_get(mbox, i); 3258 data = mlxsw_cmd_mbox_query_resource_data_get(mbox, i); 3259 3260 if (id == MLXSW_CMD_QUERY_RESOURCES_TABLE_END_ID) 3261 return 0; 3262 3263 mlxsw_res_parse(res, id, data); 3264 } 3265 } 3266 3267 /* If after MLXSW_RESOURCES_QUERY_MAX_QUERIES we still didn't get 3268 * MLXSW_RESOURCES_TABLE_END_ID, something went bad in the FW. 3269 */ 3270 return -EIO; 3271 } 3272 EXPORT_SYMBOL(mlxsw_core_resources_query); 3273 3274 u32 mlxsw_core_read_frc_h(struct mlxsw_core *mlxsw_core) 3275 { 3276 return mlxsw_core->bus->read_frc_h(mlxsw_core->bus_priv); 3277 } 3278 EXPORT_SYMBOL(mlxsw_core_read_frc_h); 3279 3280 u32 mlxsw_core_read_frc_l(struct mlxsw_core *mlxsw_core) 3281 { 3282 return mlxsw_core->bus->read_frc_l(mlxsw_core->bus_priv); 3283 } 3284 EXPORT_SYMBOL(mlxsw_core_read_frc_l); 3285 3286 void mlxsw_core_emad_string_tlv_enable(struct mlxsw_core *mlxsw_core) 3287 { 3288 mlxsw_core->emad.enable_string_tlv = true; 3289 } 3290 EXPORT_SYMBOL(mlxsw_core_emad_string_tlv_enable); 3291 3292 static int __init mlxsw_core_module_init(void) 3293 { 3294 int err; 3295 3296 mlxsw_wq = alloc_workqueue(mlxsw_core_driver_name, 0, 0); 3297 if (!mlxsw_wq) 3298 return -ENOMEM; 3299 mlxsw_owq = alloc_ordered_workqueue("%s_ordered", 0, 3300 mlxsw_core_driver_name); 3301 if (!mlxsw_owq) { 3302 err = -ENOMEM; 3303 goto err_alloc_ordered_workqueue; 3304 } 3305 return 0; 3306 3307 err_alloc_ordered_workqueue: 3308 destroy_workqueue(mlxsw_wq); 3309 return err; 3310 } 3311 3312 static void __exit mlxsw_core_module_exit(void) 3313 { 3314 destroy_workqueue(mlxsw_owq); 3315 destroy_workqueue(mlxsw_wq); 3316 } 3317 3318 module_init(mlxsw_core_module_init); 3319 module_exit(mlxsw_core_module_exit); 3320 3321 MODULE_LICENSE("Dual BSD/GPL"); 3322 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>"); 3323 MODULE_DESCRIPTION("Mellanox switch device core driver"); 3324