1 /* 2 * drivers/net/ethernet/mellanox/mlxsw/cmd.h 3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved. 4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com> 5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the names of the copyright holders nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * Alternatively, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") version 2 as published by the Free 21 * Software Foundation. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #ifndef _MLXSW_CMD_H 37 #define _MLXSW_CMD_H 38 39 #include "item.h" 40 41 #define MLXSW_CMD_MBOX_SIZE 4096 42 43 static inline char *mlxsw_cmd_mbox_alloc(void) 44 { 45 return kzalloc(MLXSW_CMD_MBOX_SIZE, GFP_KERNEL); 46 } 47 48 static inline void mlxsw_cmd_mbox_free(char *mbox) 49 { 50 kfree(mbox); 51 } 52 53 static inline void mlxsw_cmd_mbox_zero(char *mbox) 54 { 55 memset(mbox, 0, MLXSW_CMD_MBOX_SIZE); 56 } 57 58 struct mlxsw_core; 59 60 int mlxsw_cmd_exec(struct mlxsw_core *mlxsw_core, u16 opcode, u8 opcode_mod, 61 u32 in_mod, bool out_mbox_direct, 62 char *in_mbox, size_t in_mbox_size, 63 char *out_mbox, size_t out_mbox_size); 64 65 static inline int mlxsw_cmd_exec_in(struct mlxsw_core *mlxsw_core, u16 opcode, 66 u8 opcode_mod, u32 in_mod, char *in_mbox, 67 size_t in_mbox_size) 68 { 69 return mlxsw_cmd_exec(mlxsw_core, opcode, opcode_mod, in_mod, false, 70 in_mbox, in_mbox_size, NULL, 0); 71 } 72 73 static inline int mlxsw_cmd_exec_out(struct mlxsw_core *mlxsw_core, u16 opcode, 74 u8 opcode_mod, u32 in_mod, 75 bool out_mbox_direct, 76 char *out_mbox, size_t out_mbox_size) 77 { 78 return mlxsw_cmd_exec(mlxsw_core, opcode, opcode_mod, in_mod, 79 out_mbox_direct, NULL, 0, 80 out_mbox, out_mbox_size); 81 } 82 83 static inline int mlxsw_cmd_exec_none(struct mlxsw_core *mlxsw_core, u16 opcode, 84 u8 opcode_mod, u32 in_mod) 85 { 86 return mlxsw_cmd_exec(mlxsw_core, opcode, opcode_mod, in_mod, false, 87 NULL, 0, NULL, 0); 88 } 89 90 enum mlxsw_cmd_opcode { 91 MLXSW_CMD_OPCODE_QUERY_FW = 0x004, 92 MLXSW_CMD_OPCODE_QUERY_BOARDINFO = 0x006, 93 MLXSW_CMD_OPCODE_QUERY_AQ_CAP = 0x003, 94 MLXSW_CMD_OPCODE_MAP_FA = 0xFFF, 95 MLXSW_CMD_OPCODE_UNMAP_FA = 0xFFE, 96 MLXSW_CMD_OPCODE_CONFIG_PROFILE = 0x100, 97 MLXSW_CMD_OPCODE_ACCESS_REG = 0x040, 98 MLXSW_CMD_OPCODE_SW2HW_DQ = 0x201, 99 MLXSW_CMD_OPCODE_HW2SW_DQ = 0x202, 100 MLXSW_CMD_OPCODE_2ERR_DQ = 0x01E, 101 MLXSW_CMD_OPCODE_QUERY_DQ = 0x022, 102 MLXSW_CMD_OPCODE_SW2HW_CQ = 0x016, 103 MLXSW_CMD_OPCODE_HW2SW_CQ = 0x017, 104 MLXSW_CMD_OPCODE_QUERY_CQ = 0x018, 105 MLXSW_CMD_OPCODE_SW2HW_EQ = 0x013, 106 MLXSW_CMD_OPCODE_HW2SW_EQ = 0x014, 107 MLXSW_CMD_OPCODE_QUERY_EQ = 0x015, 108 }; 109 110 static inline const char *mlxsw_cmd_opcode_str(u16 opcode) 111 { 112 switch (opcode) { 113 case MLXSW_CMD_OPCODE_QUERY_FW: 114 return "QUERY_FW"; 115 case MLXSW_CMD_OPCODE_QUERY_BOARDINFO: 116 return "QUERY_BOARDINFO"; 117 case MLXSW_CMD_OPCODE_QUERY_AQ_CAP: 118 return "QUERY_AQ_CAP"; 119 case MLXSW_CMD_OPCODE_MAP_FA: 120 return "MAP_FA"; 121 case MLXSW_CMD_OPCODE_UNMAP_FA: 122 return "UNMAP_FA"; 123 case MLXSW_CMD_OPCODE_CONFIG_PROFILE: 124 return "CONFIG_PROFILE"; 125 case MLXSW_CMD_OPCODE_ACCESS_REG: 126 return "ACCESS_REG"; 127 case MLXSW_CMD_OPCODE_SW2HW_DQ: 128 return "SW2HW_DQ"; 129 case MLXSW_CMD_OPCODE_HW2SW_DQ: 130 return "HW2SW_DQ"; 131 case MLXSW_CMD_OPCODE_2ERR_DQ: 132 return "2ERR_DQ"; 133 case MLXSW_CMD_OPCODE_QUERY_DQ: 134 return "QUERY_DQ"; 135 case MLXSW_CMD_OPCODE_SW2HW_CQ: 136 return "SW2HW_CQ"; 137 case MLXSW_CMD_OPCODE_HW2SW_CQ: 138 return "HW2SW_CQ"; 139 case MLXSW_CMD_OPCODE_QUERY_CQ: 140 return "QUERY_CQ"; 141 case MLXSW_CMD_OPCODE_SW2HW_EQ: 142 return "SW2HW_EQ"; 143 case MLXSW_CMD_OPCODE_HW2SW_EQ: 144 return "HW2SW_EQ"; 145 case MLXSW_CMD_OPCODE_QUERY_EQ: 146 return "QUERY_EQ"; 147 default: 148 return "*UNKNOWN*"; 149 } 150 } 151 152 enum mlxsw_cmd_status { 153 /* Command execution succeeded. */ 154 MLXSW_CMD_STATUS_OK = 0x00, 155 /* Internal error (e.g. bus error) occurred while processing command. */ 156 MLXSW_CMD_STATUS_INTERNAL_ERR = 0x01, 157 /* Operation/command not supported or opcode modifier not supported. */ 158 MLXSW_CMD_STATUS_BAD_OP = 0x02, 159 /* Parameter not supported, parameter out of range. */ 160 MLXSW_CMD_STATUS_BAD_PARAM = 0x03, 161 /* System was not enabled or bad system state. */ 162 MLXSW_CMD_STATUS_BAD_SYS_STATE = 0x04, 163 /* Attempt to access reserved or unallocated resource, or resource in 164 * inappropriate ownership. 165 */ 166 MLXSW_CMD_STATUS_BAD_RESOURCE = 0x05, 167 /* Requested resource is currently executing a command. */ 168 MLXSW_CMD_STATUS_RESOURCE_BUSY = 0x06, 169 /* Required capability exceeds device limits. */ 170 MLXSW_CMD_STATUS_EXCEED_LIM = 0x08, 171 /* Resource is not in the appropriate state or ownership. */ 172 MLXSW_CMD_STATUS_BAD_RES_STATE = 0x09, 173 /* Index out of range (might be beyond table size or attempt to 174 * access a reserved resource). 175 */ 176 MLXSW_CMD_STATUS_BAD_INDEX = 0x0A, 177 /* NVMEM checksum/CRC failed. */ 178 MLXSW_CMD_STATUS_BAD_NVMEM = 0x0B, 179 /* Bad management packet (silently discarded). */ 180 MLXSW_CMD_STATUS_BAD_PKT = 0x30, 181 }; 182 183 static inline const char *mlxsw_cmd_status_str(u8 status) 184 { 185 switch (status) { 186 case MLXSW_CMD_STATUS_OK: 187 return "OK"; 188 case MLXSW_CMD_STATUS_INTERNAL_ERR: 189 return "INTERNAL_ERR"; 190 case MLXSW_CMD_STATUS_BAD_OP: 191 return "BAD_OP"; 192 case MLXSW_CMD_STATUS_BAD_PARAM: 193 return "BAD_PARAM"; 194 case MLXSW_CMD_STATUS_BAD_SYS_STATE: 195 return "BAD_SYS_STATE"; 196 case MLXSW_CMD_STATUS_BAD_RESOURCE: 197 return "BAD_RESOURCE"; 198 case MLXSW_CMD_STATUS_RESOURCE_BUSY: 199 return "RESOURCE_BUSY"; 200 case MLXSW_CMD_STATUS_EXCEED_LIM: 201 return "EXCEED_LIM"; 202 case MLXSW_CMD_STATUS_BAD_RES_STATE: 203 return "BAD_RES_STATE"; 204 case MLXSW_CMD_STATUS_BAD_INDEX: 205 return "BAD_INDEX"; 206 case MLXSW_CMD_STATUS_BAD_NVMEM: 207 return "BAD_NVMEM"; 208 case MLXSW_CMD_STATUS_BAD_PKT: 209 return "BAD_PKT"; 210 default: 211 return "*UNKNOWN*"; 212 } 213 } 214 215 /* QUERY_FW - Query Firmware 216 * ------------------------- 217 * OpMod == 0, INMmod == 0 218 * ----------------------- 219 * The QUERY_FW command retrieves information related to firmware, command 220 * interface version and the amount of resources that should be allocated to 221 * the firmware. 222 */ 223 224 static inline int mlxsw_cmd_query_fw(struct mlxsw_core *mlxsw_core, 225 char *out_mbox) 226 { 227 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_FW, 228 0, 0, false, out_mbox, MLXSW_CMD_MBOX_SIZE); 229 } 230 231 /* cmd_mbox_query_fw_fw_pages 232 * Amount of physical memory to be allocatedfor firmware usage in 4KB pages. 233 */ 234 MLXSW_ITEM32(cmd_mbox, query_fw, fw_pages, 0x00, 16, 16); 235 236 /* cmd_mbox_query_fw_fw_rev_major 237 * Firmware Revision - Major 238 */ 239 MLXSW_ITEM32(cmd_mbox, query_fw, fw_rev_major, 0x00, 0, 16); 240 241 /* cmd_mbox_query_fw_fw_rev_subminor 242 * Firmware Sub-minor version (Patch level) 243 */ 244 MLXSW_ITEM32(cmd_mbox, query_fw, fw_rev_subminor, 0x04, 16, 16); 245 246 /* cmd_mbox_query_fw_fw_rev_minor 247 * Firmware Revision - Minor 248 */ 249 MLXSW_ITEM32(cmd_mbox, query_fw, fw_rev_minor, 0x04, 0, 16); 250 251 /* cmd_mbox_query_fw_core_clk 252 * Internal Clock Frequency (in MHz) 253 */ 254 MLXSW_ITEM32(cmd_mbox, query_fw, core_clk, 0x08, 16, 16); 255 256 /* cmd_mbox_query_fw_cmd_interface_rev 257 * Command Interface Interpreter Revision ID. This number is bumped up 258 * every time a non-backward-compatible change is done for the command 259 * interface. The current cmd_interface_rev is 1. 260 */ 261 MLXSW_ITEM32(cmd_mbox, query_fw, cmd_interface_rev, 0x08, 0, 16); 262 263 /* cmd_mbox_query_fw_dt 264 * If set, Debug Trace is supported 265 */ 266 MLXSW_ITEM32(cmd_mbox, query_fw, dt, 0x0C, 31, 1); 267 268 /* cmd_mbox_query_fw_api_version 269 * Indicates the version of the API, to enable software querying 270 * for compatibility. The current api_version is 1. 271 */ 272 MLXSW_ITEM32(cmd_mbox, query_fw, api_version, 0x0C, 0, 16); 273 274 /* cmd_mbox_query_fw_fw_hour 275 * Firmware timestamp - hour 276 */ 277 MLXSW_ITEM32(cmd_mbox, query_fw, fw_hour, 0x10, 24, 8); 278 279 /* cmd_mbox_query_fw_fw_minutes 280 * Firmware timestamp - minutes 281 */ 282 MLXSW_ITEM32(cmd_mbox, query_fw, fw_minutes, 0x10, 16, 8); 283 284 /* cmd_mbox_query_fw_fw_seconds 285 * Firmware timestamp - seconds 286 */ 287 MLXSW_ITEM32(cmd_mbox, query_fw, fw_seconds, 0x10, 8, 8); 288 289 /* cmd_mbox_query_fw_fw_year 290 * Firmware timestamp - year 291 */ 292 MLXSW_ITEM32(cmd_mbox, query_fw, fw_year, 0x14, 16, 16); 293 294 /* cmd_mbox_query_fw_fw_month 295 * Firmware timestamp - month 296 */ 297 MLXSW_ITEM32(cmd_mbox, query_fw, fw_month, 0x14, 8, 8); 298 299 /* cmd_mbox_query_fw_fw_day 300 * Firmware timestamp - day 301 */ 302 MLXSW_ITEM32(cmd_mbox, query_fw, fw_day, 0x14, 0, 8); 303 304 /* cmd_mbox_query_fw_clr_int_base_offset 305 * Clear Interrupt register's offset from clr_int_bar register 306 * in PCI address space. 307 */ 308 MLXSW_ITEM64(cmd_mbox, query_fw, clr_int_base_offset, 0x20, 0, 64); 309 310 /* cmd_mbox_query_fw_clr_int_bar 311 * PCI base address register (BAR) where clr_int register is located. 312 * 00 - BAR 0-1 (64 bit BAR) 313 */ 314 MLXSW_ITEM32(cmd_mbox, query_fw, clr_int_bar, 0x28, 30, 2); 315 316 /* cmd_mbox_query_fw_error_buf_offset 317 * Read Only buffer for internal error reports of offset 318 * from error_buf_bar register in PCI address space). 319 */ 320 MLXSW_ITEM64(cmd_mbox, query_fw, error_buf_offset, 0x30, 0, 64); 321 322 /* cmd_mbox_query_fw_error_buf_size 323 * Internal error buffer size in DWORDs 324 */ 325 MLXSW_ITEM32(cmd_mbox, query_fw, error_buf_size, 0x38, 0, 32); 326 327 /* cmd_mbox_query_fw_error_int_bar 328 * PCI base address register (BAR) where error buffer 329 * register is located. 330 * 00 - BAR 0-1 (64 bit BAR) 331 */ 332 MLXSW_ITEM32(cmd_mbox, query_fw, error_int_bar, 0x3C, 30, 2); 333 334 /* cmd_mbox_query_fw_doorbell_page_offset 335 * Offset of the doorbell page 336 */ 337 MLXSW_ITEM64(cmd_mbox, query_fw, doorbell_page_offset, 0x40, 0, 64); 338 339 /* cmd_mbox_query_fw_doorbell_page_bar 340 * PCI base address register (BAR) of the doorbell page 341 * 00 - BAR 0-1 (64 bit BAR) 342 */ 343 MLXSW_ITEM32(cmd_mbox, query_fw, doorbell_page_bar, 0x48, 30, 2); 344 345 /* QUERY_BOARDINFO - Query Board Information 346 * ----------------------------------------- 347 * OpMod == 0 (N/A), INMmod == 0 (N/A) 348 * ----------------------------------- 349 * The QUERY_BOARDINFO command retrieves adapter specific parameters. 350 */ 351 352 static inline int mlxsw_cmd_boardinfo(struct mlxsw_core *mlxsw_core, 353 char *out_mbox) 354 { 355 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_BOARDINFO, 356 0, 0, false, out_mbox, MLXSW_CMD_MBOX_SIZE); 357 } 358 359 /* cmd_mbox_boardinfo_intapin 360 * When PCIe interrupt messages are being used, this value is used for clearing 361 * an interrupt. When using MSI-X, this register is not used. 362 */ 363 MLXSW_ITEM32(cmd_mbox, boardinfo, intapin, 0x10, 24, 8); 364 365 /* cmd_mbox_boardinfo_vsd_vendor_id 366 * PCISIG Vendor ID (www.pcisig.com/membership/vid_search) of the vendor 367 * specifying/formatting the VSD. The vsd_vendor_id identifies the management 368 * domain of the VSD/PSID data. Different vendors may choose different VSD/PSID 369 * format and encoding as long as they use their assigned vsd_vendor_id. 370 */ 371 MLXSW_ITEM32(cmd_mbox, boardinfo, vsd_vendor_id, 0x1C, 0, 16); 372 373 /* cmd_mbox_boardinfo_vsd 374 * Vendor Specific Data. The VSD string that is burnt to the Flash 375 * with the firmware. 376 */ 377 #define MLXSW_CMD_BOARDINFO_VSD_LEN 208 378 MLXSW_ITEM_BUF(cmd_mbox, boardinfo, vsd, 0x20, MLXSW_CMD_BOARDINFO_VSD_LEN); 379 380 /* cmd_mbox_boardinfo_psid 381 * The PSID field is a 16-ascii (byte) character string which acts as 382 * the board ID. The PSID format is used in conjunction with 383 * Mellanox vsd_vendor_id (15B3h). 384 */ 385 #define MLXSW_CMD_BOARDINFO_PSID_LEN 16 386 MLXSW_ITEM_BUF(cmd_mbox, boardinfo, psid, 0xF0, MLXSW_CMD_BOARDINFO_PSID_LEN); 387 388 /* QUERY_AQ_CAP - Query Asynchronous Queues Capabilities 389 * ----------------------------------------------------- 390 * OpMod == 0 (N/A), INMmod == 0 (N/A) 391 * ----------------------------------- 392 * The QUERY_AQ_CAP command returns the device asynchronous queues 393 * capabilities supported. 394 */ 395 396 static inline int mlxsw_cmd_query_aq_cap(struct mlxsw_core *mlxsw_core, 397 char *out_mbox) 398 { 399 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_AQ_CAP, 400 0, 0, false, out_mbox, MLXSW_CMD_MBOX_SIZE); 401 } 402 403 /* cmd_mbox_query_aq_cap_log_max_sdq_sz 404 * Log (base 2) of max WQEs allowed on SDQ. 405 */ 406 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_sdq_sz, 0x00, 24, 8); 407 408 /* cmd_mbox_query_aq_cap_max_num_sdqs 409 * Maximum number of SDQs. 410 */ 411 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_sdqs, 0x00, 0, 8); 412 413 /* cmd_mbox_query_aq_cap_log_max_rdq_sz 414 * Log (base 2) of max WQEs allowed on RDQ. 415 */ 416 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_rdq_sz, 0x04, 24, 8); 417 418 /* cmd_mbox_query_aq_cap_max_num_rdqs 419 * Maximum number of RDQs. 420 */ 421 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_rdqs, 0x04, 0, 8); 422 423 /* cmd_mbox_query_aq_cap_log_max_cq_sz 424 * Log (base 2) of max CQEs allowed on CQ. 425 */ 426 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_cq_sz, 0x08, 24, 8); 427 428 /* cmd_mbox_query_aq_cap_max_num_cqs 429 * Maximum number of CQs. 430 */ 431 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_cqs, 0x08, 0, 8); 432 433 /* cmd_mbox_query_aq_cap_log_max_eq_sz 434 * Log (base 2) of max EQEs allowed on EQ. 435 */ 436 MLXSW_ITEM32(cmd_mbox, query_aq_cap, log_max_eq_sz, 0x0C, 24, 8); 437 438 /* cmd_mbox_query_aq_cap_max_num_eqs 439 * Maximum number of EQs. 440 */ 441 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_num_eqs, 0x0C, 0, 8); 442 443 /* cmd_mbox_query_aq_cap_max_sg_sq 444 * The maximum S/G list elements in an DSQ. DSQ must not contain 445 * more S/G entries than indicated here. 446 */ 447 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_sg_sq, 0x10, 8, 8); 448 449 /* cmd_mbox_query_aq_cap_ 450 * The maximum S/G list elements in an DRQ. DRQ must not contain 451 * more S/G entries than indicated here. 452 */ 453 MLXSW_ITEM32(cmd_mbox, query_aq_cap, max_sg_rq, 0x10, 0, 8); 454 455 /* MAP_FA - Map Firmware Area 456 * -------------------------- 457 * OpMod == 0 (N/A), INMmod == Number of VPM entries 458 * ------------------------------------------------- 459 * The MAP_FA command passes physical pages to the switch. These pages 460 * are used to store the device firmware. MAP_FA can be executed multiple 461 * times until all the firmware area is mapped (the size that should be 462 * mapped is retrieved through the QUERY_FW command). All required pages 463 * must be mapped to finish the initialization phase. Physical memory 464 * passed in this command must be pinned. 465 */ 466 467 #define MLXSW_CMD_MAP_FA_VPM_ENTRIES_MAX 32 468 469 static inline int mlxsw_cmd_map_fa(struct mlxsw_core *mlxsw_core, 470 char *in_mbox, u32 vpm_entries_count) 471 { 472 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_MAP_FA, 473 0, vpm_entries_count, 474 in_mbox, MLXSW_CMD_MBOX_SIZE); 475 } 476 477 /* cmd_mbox_map_fa_pa 478 * Physical Address. 479 */ 480 MLXSW_ITEM64_INDEXED(cmd_mbox, map_fa, pa, 0x00, 12, 52, 0x08, 0x00, true); 481 482 /* cmd_mbox_map_fa_log2size 483 * Log (base 2) of the size in 4KB pages of the physical and contiguous memory 484 * that starts at PA_L/H. 485 */ 486 MLXSW_ITEM32_INDEXED(cmd_mbox, map_fa, log2size, 0x00, 0, 5, 0x08, 0x04, false); 487 488 /* UNMAP_FA - Unmap Firmware Area 489 * ------------------------------ 490 * OpMod == 0 (N/A), INMmod == 0 (N/A) 491 * ----------------------------------- 492 * The UNMAP_FA command unload the firmware and unmaps all the 493 * firmware area. After this command is completed the device will not access 494 * the pages that were mapped to the firmware area. After executing UNMAP_FA 495 * command, software reset must be done prior to execution of MAP_FW command. 496 */ 497 498 static inline int mlxsw_cmd_unmap_fa(struct mlxsw_core *mlxsw_core) 499 { 500 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_UNMAP_FA, 0, 0); 501 } 502 503 /* CONFIG_PROFILE (Set) - Configure Switch Profile 504 * ------------------------------ 505 * OpMod == 1 (Set), INMmod == 0 (N/A) 506 * ----------------------------------- 507 * The CONFIG_PROFILE command sets the switch profile. The command can be 508 * executed on the device only once at startup in order to allocate and 509 * configure all switch resources and prepare it for operational mode. 510 * It is not possible to change the device profile after the chip is 511 * in operational mode. 512 * Failure of the CONFIG_PROFILE command leaves the hardware in an indeterminate 513 * state therefore it is required to perform software reset to the device 514 * following an unsuccessful completion of the command. It is required 515 * to perform software reset to the device to change an existing profile. 516 */ 517 518 static inline int mlxsw_cmd_config_profile_set(struct mlxsw_core *mlxsw_core, 519 char *in_mbox) 520 { 521 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_CONFIG_PROFILE, 522 1, 0, in_mbox, MLXSW_CMD_MBOX_SIZE); 523 } 524 525 /* cmd_mbox_config_profile_set_max_vepa_channels 526 * Capability bit. Setting a bit to 1 configures the profile 527 * according to the mailbox contents. 528 */ 529 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_vepa_channels, 0x0C, 0, 1); 530 531 /* cmd_mbox_config_profile_set_max_lag 532 * Capability bit. Setting a bit to 1 configures the profile 533 * according to the mailbox contents. 534 */ 535 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_lag, 0x0C, 1, 1); 536 537 /* cmd_mbox_config_profile_set_max_port_per_lag 538 * Capability bit. Setting a bit to 1 configures the profile 539 * according to the mailbox contents. 540 */ 541 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_port_per_lag, 0x0C, 2, 1); 542 543 /* cmd_mbox_config_profile_set_max_mid 544 * Capability bit. Setting a bit to 1 configures the profile 545 * according to the mailbox contents. 546 */ 547 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_mid, 0x0C, 3, 1); 548 549 /* cmd_mbox_config_profile_set_max_pgt 550 * Capability bit. Setting a bit to 1 configures the profile 551 * according to the mailbox contents. 552 */ 553 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_pgt, 0x0C, 4, 1); 554 555 /* cmd_mbox_config_profile_set_max_system_port 556 * Capability bit. Setting a bit to 1 configures the profile 557 * according to the mailbox contents. 558 */ 559 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_system_port, 0x0C, 5, 1); 560 561 /* cmd_mbox_config_profile_set_max_vlan_groups 562 * Capability bit. Setting a bit to 1 configures the profile 563 * according to the mailbox contents. 564 */ 565 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_vlan_groups, 0x0C, 6, 1); 566 567 /* cmd_mbox_config_profile_set_max_regions 568 * Capability bit. Setting a bit to 1 configures the profile 569 * according to the mailbox contents. 570 */ 571 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_regions, 0x0C, 7, 1); 572 573 /* cmd_mbox_config_profile_set_flood_mode 574 * Capability bit. Setting a bit to 1 configures the profile 575 * according to the mailbox contents. 576 */ 577 MLXSW_ITEM32(cmd_mbox, config_profile, set_flood_mode, 0x0C, 8, 1); 578 579 /* cmd_mbox_config_profile_set_max_flood_tables 580 * Capability bit. Setting a bit to 1 configures the profile 581 * according to the mailbox contents. 582 */ 583 MLXSW_ITEM32(cmd_mbox, config_profile, set_flood_tables, 0x0C, 9, 1); 584 585 /* cmd_mbox_config_profile_set_max_ib_mc 586 * Capability bit. Setting a bit to 1 configures the profile 587 * according to the mailbox contents. 588 */ 589 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_ib_mc, 0x0C, 12, 1); 590 591 /* cmd_mbox_config_profile_set_max_pkey 592 * Capability bit. Setting a bit to 1 configures the profile 593 * according to the mailbox contents. 594 */ 595 MLXSW_ITEM32(cmd_mbox, config_profile, set_max_pkey, 0x0C, 13, 1); 596 597 /* cmd_mbox_config_profile_set_adaptive_routing_group_cap 598 * Capability bit. Setting a bit to 1 configures the profile 599 * according to the mailbox contents. 600 */ 601 MLXSW_ITEM32(cmd_mbox, config_profile, 602 set_adaptive_routing_group_cap, 0x0C, 14, 1); 603 604 /* cmd_mbox_config_profile_set_ar_sec 605 * Capability bit. Setting a bit to 1 configures the profile 606 * according to the mailbox contents. 607 */ 608 MLXSW_ITEM32(cmd_mbox, config_profile, set_ar_sec, 0x0C, 15, 1); 609 610 /* cmd_mbox_config_profile_max_vepa_channels 611 * Maximum number of VEPA channels per port (0 through 16) 612 * 0 - multi-channel VEPA is disabled 613 */ 614 MLXSW_ITEM32(cmd_mbox, config_profile, max_vepa_channels, 0x10, 0, 8); 615 616 /* cmd_mbox_config_profile_max_lag 617 * Maximum number of LAG IDs requested. 618 */ 619 MLXSW_ITEM32(cmd_mbox, config_profile, max_lag, 0x14, 0, 16); 620 621 /* cmd_mbox_config_profile_max_port_per_lag 622 * Maximum number of ports per LAG requested. 623 */ 624 MLXSW_ITEM32(cmd_mbox, config_profile, max_port_per_lag, 0x18, 0, 16); 625 626 /* cmd_mbox_config_profile_max_mid 627 * Maximum Multicast IDs. 628 * Multicast IDs are allocated from 0 to max_mid-1 629 */ 630 MLXSW_ITEM32(cmd_mbox, config_profile, max_mid, 0x1C, 0, 16); 631 632 /* cmd_mbox_config_profile_max_pgt 633 * Maximum records in the Port Group Table per Switch Partition. 634 * Port Group Table indexes are from 0 to max_pgt-1 635 */ 636 MLXSW_ITEM32(cmd_mbox, config_profile, max_pgt, 0x20, 0, 16); 637 638 /* cmd_mbox_config_profile_max_system_port 639 * The maximum number of system ports that can be allocated. 640 */ 641 MLXSW_ITEM32(cmd_mbox, config_profile, max_system_port, 0x24, 0, 16); 642 643 /* cmd_mbox_config_profile_max_vlan_groups 644 * Maximum number VLAN Groups for VLAN binding. 645 */ 646 MLXSW_ITEM32(cmd_mbox, config_profile, max_vlan_groups, 0x28, 0, 12); 647 648 /* cmd_mbox_config_profile_max_regions 649 * Maximum number of TCAM Regions. 650 */ 651 MLXSW_ITEM32(cmd_mbox, config_profile, max_regions, 0x2C, 0, 16); 652 653 /* cmd_mbox_config_profile_max_flood_tables 654 * Maximum number of single-entry flooding tables. Different flooding tables 655 * can be associated with different packet types. 656 */ 657 MLXSW_ITEM32(cmd_mbox, config_profile, max_flood_tables, 0x30, 16, 4); 658 659 /* cmd_mbox_config_profile_max_vid_flood_tables 660 * Maximum number of per-vid flooding tables. Flooding tables are associated 661 * to the different packet types for the different switch partitions. 662 * Table size is 4K entries covering all VID space. 663 */ 664 MLXSW_ITEM32(cmd_mbox, config_profile, max_vid_flood_tables, 0x30, 8, 4); 665 666 /* cmd_mbox_config_profile_flood_mode 667 * Flooding mode to use. 668 * 0-2 - Backward compatible modes for SwitchX devices. 669 * 3 - Mixed mode, where: 670 * max_flood_tables indicates the number of single-entry tables. 671 * max_vid_flood_tables indicates the number of per-VID tables. 672 * max_fid_offset_flood_tables indicates the number of FID-offset tables. 673 * max_fid_flood_tables indicates the number of per-FID tables. 674 */ 675 MLXSW_ITEM32(cmd_mbox, config_profile, flood_mode, 0x30, 0, 2); 676 677 /* cmd_mbox_config_profile_max_fid_offset_flood_tables 678 * Maximum number of FID-offset flooding tables. 679 */ 680 MLXSW_ITEM32(cmd_mbox, config_profile, 681 max_fid_offset_flood_tables, 0x34, 24, 4); 682 683 /* cmd_mbox_config_profile_fid_offset_flood_table_size 684 * The size (number of entries) of each FID-offset flood table. 685 */ 686 MLXSW_ITEM32(cmd_mbox, config_profile, 687 fid_offset_flood_table_size, 0x34, 0, 16); 688 689 /* cmd_mbox_config_profile_max_fid_flood_tables 690 * Maximum number of per-FID flooding tables. 691 * 692 * Note: This flooding tables cover special FIDs only (vFIDs), starting at 693 * FID value 4K and higher. 694 */ 695 MLXSW_ITEM32(cmd_mbox, config_profile, max_fid_flood_tables, 0x38, 24, 4); 696 697 /* cmd_mbox_config_profile_fid_flood_table_size 698 * The size (number of entries) of each per-FID table. 699 */ 700 MLXSW_ITEM32(cmd_mbox, config_profile, fid_flood_table_size, 0x38, 0, 16); 701 702 /* cmd_mbox_config_profile_max_ib_mc 703 * Maximum number of multicast FDB records for InfiniBand 704 * FDB (in 512 chunks) per InfiniBand switch partition. 705 */ 706 MLXSW_ITEM32(cmd_mbox, config_profile, max_ib_mc, 0x40, 0, 15); 707 708 /* cmd_mbox_config_profile_max_pkey 709 * Maximum per port PKEY table size (for PKEY enforcement) 710 */ 711 MLXSW_ITEM32(cmd_mbox, config_profile, max_pkey, 0x44, 0, 15); 712 713 /* cmd_mbox_config_profile_ar_sec 714 * Primary/secondary capability 715 * Describes the number of adaptive routing sub-groups 716 * 0 - disable primary/secondary (single group) 717 * 1 - enable primary/secondary (2 sub-groups) 718 * 2 - 3 sub-groups: Not supported in SwitchX, SwitchX-2 719 * 3 - 4 sub-groups: Not supported in SwitchX, SwitchX-2 720 */ 721 MLXSW_ITEM32(cmd_mbox, config_profile, ar_sec, 0x4C, 24, 2); 722 723 /* cmd_mbox_config_profile_adaptive_routing_group_cap 724 * Adaptive Routing Group Capability. Indicates the number of AR groups 725 * supported. Note that when Primary/secondary is enabled, each 726 * primary/secondary couple consumes 2 adaptive routing entries. 727 */ 728 MLXSW_ITEM32(cmd_mbox, config_profile, adaptive_routing_group_cap, 0x4C, 0, 16); 729 730 /* cmd_mbox_config_profile_arn 731 * Adaptive Routing Notification Enable 732 * Not supported in SwitchX, SwitchX-2 733 */ 734 MLXSW_ITEM32(cmd_mbox, config_profile, arn, 0x50, 31, 1); 735 736 /* cmd_mbox_config_profile_swid_config_mask 737 * Modify Switch Partition Configuration mask. When set, the configu- 738 * ration value for the Switch Partition are taken from the mailbox. 739 * When clear, the current configuration values are used. 740 * Bit 0 - set type 741 * Bit 1 - properties 742 * Other - reserved 743 */ 744 MLXSW_ITEM32_INDEXED(cmd_mbox, config_profile, swid_config_mask, 745 0x60, 24, 8, 0x08, 0x00, false); 746 747 /* cmd_mbox_config_profile_swid_config_type 748 * Switch Partition type. 749 * 0000 - disabled (Switch Partition does not exist) 750 * 0001 - InfiniBand 751 * 0010 - Ethernet 752 * 1000 - router port (SwitchX-2 only) 753 * Other - reserved 754 */ 755 MLXSW_ITEM32_INDEXED(cmd_mbox, config_profile, swid_config_type, 756 0x60, 20, 4, 0x08, 0x00, false); 757 758 /* cmd_mbox_config_profile_swid_config_properties 759 * Switch Partition properties. 760 */ 761 MLXSW_ITEM32_INDEXED(cmd_mbox, config_profile, swid_config_properties, 762 0x60, 0, 8, 0x08, 0x00, false); 763 764 /* ACCESS_REG - Access EMAD Supported Register 765 * ---------------------------------- 766 * OpMod == 0 (N/A), INMmod == 0 (N/A) 767 * ------------------------------------- 768 * The ACCESS_REG command supports accessing device registers. This access 769 * is mainly used for bootstrapping. 770 */ 771 772 static inline int mlxsw_cmd_access_reg(struct mlxsw_core *mlxsw_core, 773 char *in_mbox, char *out_mbox) 774 { 775 return mlxsw_cmd_exec(mlxsw_core, MLXSW_CMD_OPCODE_ACCESS_REG, 776 0, 0, false, in_mbox, MLXSW_CMD_MBOX_SIZE, 777 out_mbox, MLXSW_CMD_MBOX_SIZE); 778 } 779 780 /* SW2HW_DQ - Software to Hardware DQ 781 * ---------------------------------- 782 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ) 783 * INMmod == DQ number 784 * ---------------------------------------------- 785 * The SW2HW_DQ command transitions a descriptor queue from software to 786 * hardware ownership. The command enables posting WQEs and ringing DoorBells 787 * on the descriptor queue. 788 */ 789 790 static inline int __mlxsw_cmd_sw2hw_dq(struct mlxsw_core *mlxsw_core, 791 char *in_mbox, u32 dq_number, 792 u8 opcode_mod) 793 { 794 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_SW2HW_DQ, 795 opcode_mod, dq_number, 796 in_mbox, MLXSW_CMD_MBOX_SIZE); 797 } 798 799 enum { 800 MLXSW_CMD_OPCODE_MOD_SDQ = 0, 801 MLXSW_CMD_OPCODE_MOD_RDQ = 1, 802 }; 803 804 static inline int mlxsw_cmd_sw2hw_sdq(struct mlxsw_core *mlxsw_core, 805 char *in_mbox, u32 dq_number) 806 { 807 return __mlxsw_cmd_sw2hw_dq(mlxsw_core, in_mbox, dq_number, 808 MLXSW_CMD_OPCODE_MOD_SDQ); 809 } 810 811 static inline int mlxsw_cmd_sw2hw_rdq(struct mlxsw_core *mlxsw_core, 812 char *in_mbox, u32 dq_number) 813 { 814 return __mlxsw_cmd_sw2hw_dq(mlxsw_core, in_mbox, dq_number, 815 MLXSW_CMD_OPCODE_MOD_RDQ); 816 } 817 818 /* cmd_mbox_sw2hw_dq_cq 819 * Number of the CQ that this Descriptor Queue reports completions to. 820 */ 821 MLXSW_ITEM32(cmd_mbox, sw2hw_dq, cq, 0x00, 24, 8); 822 823 /* cmd_mbox_sw2hw_dq_sdq_tclass 824 * SDQ: CPU Egress TClass 825 * RDQ: Reserved 826 */ 827 MLXSW_ITEM32(cmd_mbox, sw2hw_dq, sdq_tclass, 0x00, 16, 6); 828 829 /* cmd_mbox_sw2hw_dq_log2_dq_sz 830 * Log (base 2) of the Descriptor Queue size in 4KB pages. 831 */ 832 MLXSW_ITEM32(cmd_mbox, sw2hw_dq, log2_dq_sz, 0x00, 0, 6); 833 834 /* cmd_mbox_sw2hw_dq_pa 835 * Physical Address. 836 */ 837 MLXSW_ITEM64_INDEXED(cmd_mbox, sw2hw_dq, pa, 0x10, 12, 52, 0x08, 0x00, true); 838 839 /* HW2SW_DQ - Hardware to Software DQ 840 * ---------------------------------- 841 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ) 842 * INMmod == DQ number 843 * ---------------------------------------------- 844 * The HW2SW_DQ command transitions a descriptor queue from hardware to 845 * software ownership. Incoming packets on the DQ are silently discarded, 846 * SW should not post descriptors on nonoperational DQs. 847 */ 848 849 static inline int __mlxsw_cmd_hw2sw_dq(struct mlxsw_core *mlxsw_core, 850 u32 dq_number, u8 opcode_mod) 851 { 852 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_HW2SW_DQ, 853 opcode_mod, dq_number); 854 } 855 856 static inline int mlxsw_cmd_hw2sw_sdq(struct mlxsw_core *mlxsw_core, 857 u32 dq_number) 858 { 859 return __mlxsw_cmd_hw2sw_dq(mlxsw_core, dq_number, 860 MLXSW_CMD_OPCODE_MOD_SDQ); 861 } 862 863 static inline int mlxsw_cmd_hw2sw_rdq(struct mlxsw_core *mlxsw_core, 864 u32 dq_number) 865 { 866 return __mlxsw_cmd_hw2sw_dq(mlxsw_core, dq_number, 867 MLXSW_CMD_OPCODE_MOD_RDQ); 868 } 869 870 /* 2ERR_DQ - To Error DQ 871 * --------------------- 872 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ) 873 * INMmod == DQ number 874 * ---------------------------------------------- 875 * The 2ERR_DQ command transitions the DQ into the error state from the state 876 * in which it has been. While the command is executed, some in-process 877 * descriptors may complete. Once the DQ transitions into the error state, 878 * if there are posted descriptors on the RDQ/SDQ, the hardware writes 879 * a completion with error (flushed) for all descriptors posted in the RDQ/SDQ. 880 * When the command is completed successfully, the DQ is already in 881 * the error state. 882 */ 883 884 static inline int __mlxsw_cmd_2err_dq(struct mlxsw_core *mlxsw_core, 885 u32 dq_number, u8 opcode_mod) 886 { 887 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_2ERR_DQ, 888 opcode_mod, dq_number); 889 } 890 891 static inline int mlxsw_cmd_2err_sdq(struct mlxsw_core *mlxsw_core, 892 u32 dq_number) 893 { 894 return __mlxsw_cmd_2err_dq(mlxsw_core, dq_number, 895 MLXSW_CMD_OPCODE_MOD_SDQ); 896 } 897 898 static inline int mlxsw_cmd_2err_rdq(struct mlxsw_core *mlxsw_core, 899 u32 dq_number) 900 { 901 return __mlxsw_cmd_2err_dq(mlxsw_core, dq_number, 902 MLXSW_CMD_OPCODE_MOD_RDQ); 903 } 904 905 /* QUERY_DQ - Query DQ 906 * --------------------- 907 * OpMod == 0 (send DQ) / OpMod == 1 (receive DQ) 908 * INMmod == DQ number 909 * ---------------------------------------------- 910 * The QUERY_DQ command retrieves a snapshot of DQ parameters from the hardware. 911 * 912 * Note: Output mailbox has the same format as SW2HW_DQ. 913 */ 914 915 static inline int __mlxsw_cmd_query_dq(struct mlxsw_core *mlxsw_core, 916 char *out_mbox, u32 dq_number, 917 u8 opcode_mod) 918 { 919 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_2ERR_DQ, 920 opcode_mod, dq_number, false, 921 out_mbox, MLXSW_CMD_MBOX_SIZE); 922 } 923 924 static inline int mlxsw_cmd_query_sdq(struct mlxsw_core *mlxsw_core, 925 char *out_mbox, u32 dq_number) 926 { 927 return __mlxsw_cmd_query_dq(mlxsw_core, out_mbox, dq_number, 928 MLXSW_CMD_OPCODE_MOD_SDQ); 929 } 930 931 static inline int mlxsw_cmd_query_rdq(struct mlxsw_core *mlxsw_core, 932 char *out_mbox, u32 dq_number) 933 { 934 return __mlxsw_cmd_query_dq(mlxsw_core, out_mbox, dq_number, 935 MLXSW_CMD_OPCODE_MOD_RDQ); 936 } 937 938 /* SW2HW_CQ - Software to Hardware CQ 939 * ---------------------------------- 940 * OpMod == 0 (N/A), INMmod == CQ number 941 * ------------------------------------- 942 * The SW2HW_CQ command transfers ownership of a CQ context entry from software 943 * to hardware. The command takes the CQ context entry from the input mailbox 944 * and stores it in the CQC in the ownership of the hardware. The command fails 945 * if the requested CQC entry is already in the ownership of the hardware. 946 */ 947 948 static inline int mlxsw_cmd_sw2hw_cq(struct mlxsw_core *mlxsw_core, 949 char *in_mbox, u32 cq_number) 950 { 951 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_SW2HW_CQ, 952 0, cq_number, in_mbox, MLXSW_CMD_MBOX_SIZE); 953 } 954 955 /* cmd_mbox_sw2hw_cq_cv 956 * CQE Version. 957 * 0 - CQE Version 0, 1 - CQE Version 1 958 */ 959 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, cv, 0x00, 28, 4); 960 961 /* cmd_mbox_sw2hw_cq_c_eqn 962 * Event Queue this CQ reports completion events to. 963 */ 964 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, c_eqn, 0x00, 24, 1); 965 966 /* cmd_mbox_sw2hw_cq_oi 967 * When set, overrun ignore is enabled. When set, updates of 968 * CQ consumer counter (poll for completion) or Request completion 969 * notifications (Arm CQ) DoorBells should not be rung on that CQ. 970 */ 971 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, oi, 0x00, 12, 1); 972 973 /* cmd_mbox_sw2hw_cq_st 974 * Event delivery state machine 975 * 0x0 - FIRED 976 * 0x1 - ARMED (Request for Notification) 977 */ 978 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, st, 0x00, 8, 1); 979 980 /* cmd_mbox_sw2hw_cq_log_cq_size 981 * Log (base 2) of the CQ size (in entries). 982 */ 983 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, log_cq_size, 0x00, 0, 4); 984 985 /* cmd_mbox_sw2hw_cq_producer_counter 986 * Producer Counter. The counter is incremented for each CQE that is 987 * written by the HW to the CQ. 988 * Maintained by HW (valid for the QUERY_CQ command only) 989 */ 990 MLXSW_ITEM32(cmd_mbox, sw2hw_cq, producer_counter, 0x04, 0, 16); 991 992 /* cmd_mbox_sw2hw_cq_pa 993 * Physical Address. 994 */ 995 MLXSW_ITEM64_INDEXED(cmd_mbox, sw2hw_cq, pa, 0x10, 11, 53, 0x08, 0x00, true); 996 997 /* HW2SW_CQ - Hardware to Software CQ 998 * ---------------------------------- 999 * OpMod == 0 (N/A), INMmod == CQ number 1000 * ------------------------------------- 1001 * The HW2SW_CQ command transfers ownership of a CQ context entry from hardware 1002 * to software. The CQC entry is invalidated as a result of this command. 1003 */ 1004 1005 static inline int mlxsw_cmd_hw2sw_cq(struct mlxsw_core *mlxsw_core, 1006 u32 cq_number) 1007 { 1008 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_HW2SW_CQ, 1009 0, cq_number); 1010 } 1011 1012 /* QUERY_CQ - Query CQ 1013 * ---------------------------------- 1014 * OpMod == 0 (N/A), INMmod == CQ number 1015 * ------------------------------------- 1016 * The QUERY_CQ command retrieves a snapshot of the current CQ context entry. 1017 * The command stores the snapshot in the output mailbox in the software format. 1018 * Note that the CQ context state and values are not affected by the QUERY_CQ 1019 * command. The QUERY_CQ command is for debug purposes only. 1020 * 1021 * Note: Output mailbox has the same format as SW2HW_CQ. 1022 */ 1023 1024 static inline int mlxsw_cmd_query_cq(struct mlxsw_core *mlxsw_core, 1025 char *out_mbox, u32 cq_number) 1026 { 1027 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_CQ, 1028 0, cq_number, false, 1029 out_mbox, MLXSW_CMD_MBOX_SIZE); 1030 } 1031 1032 /* SW2HW_EQ - Software to Hardware EQ 1033 * ---------------------------------- 1034 * OpMod == 0 (N/A), INMmod == EQ number 1035 * ------------------------------------- 1036 * The SW2HW_EQ command transfers ownership of an EQ context entry from software 1037 * to hardware. The command takes the EQ context entry from the input mailbox 1038 * and stores it in the EQC in the ownership of the hardware. The command fails 1039 * if the requested EQC entry is already in the ownership of the hardware. 1040 */ 1041 1042 static inline int mlxsw_cmd_sw2hw_eq(struct mlxsw_core *mlxsw_core, 1043 char *in_mbox, u32 eq_number) 1044 { 1045 return mlxsw_cmd_exec_in(mlxsw_core, MLXSW_CMD_OPCODE_SW2HW_EQ, 1046 0, eq_number, in_mbox, MLXSW_CMD_MBOX_SIZE); 1047 } 1048 1049 /* cmd_mbox_sw2hw_eq_int_msix 1050 * When set, MSI-X cycles will be generated by this EQ. 1051 * When cleared, an interrupt will be generated by this EQ. 1052 */ 1053 MLXSW_ITEM32(cmd_mbox, sw2hw_eq, int_msix, 0x00, 24, 1); 1054 1055 /* cmd_mbox_sw2hw_eq_int_oi 1056 * When set, overrun ignore is enabled. 1057 */ 1058 MLXSW_ITEM32(cmd_mbox, sw2hw_eq, oi, 0x00, 12, 1); 1059 1060 /* cmd_mbox_sw2hw_eq_int_st 1061 * Event delivery state machine 1062 * 0x0 - FIRED 1063 * 0x1 - ARMED (Request for Notification) 1064 * 0x11 - Always ARMED 1065 * other - reserved 1066 */ 1067 MLXSW_ITEM32(cmd_mbox, sw2hw_eq, st, 0x00, 8, 2); 1068 1069 /* cmd_mbox_sw2hw_eq_int_log_eq_size 1070 * Log (base 2) of the EQ size (in entries). 1071 */ 1072 MLXSW_ITEM32(cmd_mbox, sw2hw_eq, log_eq_size, 0x00, 0, 4); 1073 1074 /* cmd_mbox_sw2hw_eq_int_producer_counter 1075 * Producer Counter. The counter is incremented for each EQE that is written 1076 * by the HW to the EQ. 1077 * Maintained by HW (valid for the QUERY_EQ command only) 1078 */ 1079 MLXSW_ITEM32(cmd_mbox, sw2hw_eq, producer_counter, 0x04, 0, 16); 1080 1081 /* cmd_mbox_sw2hw_eq_int_pa 1082 * Physical Address. 1083 */ 1084 MLXSW_ITEM64_INDEXED(cmd_mbox, sw2hw_eq, pa, 0x10, 11, 53, 0x08, 0x00, true); 1085 1086 /* HW2SW_EQ - Hardware to Software EQ 1087 * ---------------------------------- 1088 * OpMod == 0 (N/A), INMmod == EQ number 1089 * ------------------------------------- 1090 */ 1091 1092 static inline int mlxsw_cmd_hw2sw_eq(struct mlxsw_core *mlxsw_core, 1093 u32 eq_number) 1094 { 1095 return mlxsw_cmd_exec_none(mlxsw_core, MLXSW_CMD_OPCODE_HW2SW_EQ, 1096 0, eq_number); 1097 } 1098 1099 /* QUERY_EQ - Query EQ 1100 * ---------------------------------- 1101 * OpMod == 0 (N/A), INMmod == EQ number 1102 * ------------------------------------- 1103 * 1104 * Note: Output mailbox has the same format as SW2HW_EQ. 1105 */ 1106 1107 static inline int mlxsw_cmd_query_eq(struct mlxsw_core *mlxsw_core, 1108 char *out_mbox, u32 eq_number) 1109 { 1110 return mlxsw_cmd_exec_out(mlxsw_core, MLXSW_CMD_OPCODE_QUERY_EQ, 1111 0, eq_number, false, 1112 out_mbox, MLXSW_CMD_MBOX_SIZE); 1113 } 1114 1115 #endif 1116