1 // SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause 2 3 /* Gigabit Ethernet driver for Mellanox BlueField SoC 4 * 5 * Copyright (C) 2020-2021 NVIDIA CORPORATION & AFFILIATES 6 */ 7 8 #include <linux/acpi.h> 9 #include <linux/device.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/etherdevice.h> 12 #include <linux/interrupt.h> 13 #include <linux/iopoll.h> 14 #include <linux/module.h> 15 #include <linux/phy.h> 16 #include <linux/platform_device.h> 17 #include <linux/skbuff.h> 18 19 #include "mlxbf_gige.h" 20 #include "mlxbf_gige_regs.h" 21 22 /* Allocate SKB whose payload pointer aligns with the Bluefield 23 * hardware DMA limitation, i.e. DMA operation can't cross 24 * a 4KB boundary. A maximum packet size of 2KB is assumed in the 25 * alignment formula. The alignment logic overallocates an SKB, 26 * and then adjusts the headroom so that the SKB data pointer is 27 * naturally aligned to a 2KB boundary. 28 */ 29 struct sk_buff *mlxbf_gige_alloc_skb(struct mlxbf_gige *priv, 30 unsigned int map_len, 31 dma_addr_t *buf_dma, 32 enum dma_data_direction dir) 33 { 34 struct sk_buff *skb; 35 u64 addr, offset; 36 37 /* Overallocate the SKB so that any headroom adjustment (to 38 * provide 2KB natural alignment) does not exceed payload area 39 */ 40 skb = netdev_alloc_skb(priv->netdev, MLXBF_GIGE_DEFAULT_BUF_SZ * 2); 41 if (!skb) 42 return NULL; 43 44 /* Adjust the headroom so that skb->data is naturally aligned to 45 * a 2KB boundary, which is the maximum packet size supported. 46 */ 47 addr = (long)skb->data; 48 offset = (addr + MLXBF_GIGE_DEFAULT_BUF_SZ - 1) & 49 ~(MLXBF_GIGE_DEFAULT_BUF_SZ - 1); 50 offset -= addr; 51 if (offset) 52 skb_reserve(skb, offset); 53 54 /* Return streaming DMA mapping to caller */ 55 *buf_dma = dma_map_single(priv->dev, skb->data, map_len, dir); 56 if (dma_mapping_error(priv->dev, *buf_dma)) { 57 dev_kfree_skb(skb); 58 *buf_dma = (dma_addr_t)0; 59 return NULL; 60 } 61 62 return skb; 63 } 64 65 static void mlxbf_gige_initial_mac(struct mlxbf_gige *priv) 66 { 67 u8 mac[ETH_ALEN]; 68 u64 local_mac; 69 70 eth_zero_addr(mac); 71 mlxbf_gige_get_mac_rx_filter(priv, MLXBF_GIGE_LOCAL_MAC_FILTER_IDX, 72 &local_mac); 73 u64_to_ether_addr(local_mac, mac); 74 75 if (is_valid_ether_addr(mac)) { 76 eth_hw_addr_set(priv->netdev, mac); 77 } else { 78 /* Provide a random MAC if for some reason the device has 79 * not been configured with a valid MAC address already. 80 */ 81 eth_hw_addr_random(priv->netdev); 82 } 83 84 local_mac = ether_addr_to_u64(priv->netdev->dev_addr); 85 mlxbf_gige_set_mac_rx_filter(priv, MLXBF_GIGE_LOCAL_MAC_FILTER_IDX, 86 local_mac); 87 } 88 89 static void mlxbf_gige_cache_stats(struct mlxbf_gige *priv) 90 { 91 struct mlxbf_gige_stats *p; 92 93 /* Cache stats that will be cleared by clean port operation */ 94 p = &priv->stats; 95 p->rx_din_dropped_pkts += readq(priv->base + 96 MLXBF_GIGE_RX_DIN_DROP_COUNTER); 97 p->rx_filter_passed_pkts += readq(priv->base + 98 MLXBF_GIGE_RX_PASS_COUNTER_ALL); 99 p->rx_filter_discard_pkts += readq(priv->base + 100 MLXBF_GIGE_RX_DISC_COUNTER_ALL); 101 } 102 103 static int mlxbf_gige_clean_port(struct mlxbf_gige *priv) 104 { 105 u64 control; 106 u64 temp; 107 int err; 108 109 /* Set the CLEAN_PORT_EN bit to trigger SW reset */ 110 control = readq(priv->base + MLXBF_GIGE_CONTROL); 111 control |= MLXBF_GIGE_CONTROL_CLEAN_PORT_EN; 112 writeq(control, priv->base + MLXBF_GIGE_CONTROL); 113 114 /* Ensure completion of "clean port" write before polling status */ 115 mb(); 116 117 err = readq_poll_timeout_atomic(priv->base + MLXBF_GIGE_STATUS, temp, 118 (temp & MLXBF_GIGE_STATUS_READY), 119 100, 100000); 120 121 /* Clear the CLEAN_PORT_EN bit at end of this loop */ 122 control = readq(priv->base + MLXBF_GIGE_CONTROL); 123 control &= ~MLXBF_GIGE_CONTROL_CLEAN_PORT_EN; 124 writeq(control, priv->base + MLXBF_GIGE_CONTROL); 125 126 return err; 127 } 128 129 static int mlxbf_gige_open(struct net_device *netdev) 130 { 131 struct mlxbf_gige *priv = netdev_priv(netdev); 132 struct phy_device *phydev = netdev->phydev; 133 u64 control; 134 u64 int_en; 135 int err; 136 137 /* Perform general init of GigE block */ 138 control = readq(priv->base + MLXBF_GIGE_CONTROL); 139 control |= MLXBF_GIGE_CONTROL_PORT_EN; 140 writeq(control, priv->base + MLXBF_GIGE_CONTROL); 141 142 mlxbf_gige_cache_stats(priv); 143 err = mlxbf_gige_clean_port(priv); 144 if (err) 145 return err; 146 147 /* Clear driver's valid_polarity to match hardware, 148 * since the above call to clean_port() resets the 149 * receive polarity used by hardware. 150 */ 151 priv->valid_polarity = 0; 152 153 phy_start(phydev); 154 155 err = mlxbf_gige_tx_init(priv); 156 if (err) 157 goto phy_deinit; 158 err = mlxbf_gige_rx_init(priv); 159 if (err) 160 goto tx_deinit; 161 162 netif_napi_add(netdev, &priv->napi, mlxbf_gige_poll); 163 napi_enable(&priv->napi); 164 netif_start_queue(netdev); 165 166 err = mlxbf_gige_request_irqs(priv); 167 if (err) 168 goto napi_deinit; 169 170 /* Set bits in INT_EN that we care about */ 171 int_en = MLXBF_GIGE_INT_EN_HW_ACCESS_ERROR | 172 MLXBF_GIGE_INT_EN_TX_CHECKSUM_INPUTS | 173 MLXBF_GIGE_INT_EN_TX_SMALL_FRAME_SIZE | 174 MLXBF_GIGE_INT_EN_TX_PI_CI_EXCEED_WQ_SIZE | 175 MLXBF_GIGE_INT_EN_SW_CONFIG_ERROR | 176 MLXBF_GIGE_INT_EN_SW_ACCESS_ERROR | 177 MLXBF_GIGE_INT_EN_RX_RECEIVE_PACKET; 178 179 /* Ensure completion of all initialization before enabling interrupts */ 180 mb(); 181 182 writeq(int_en, priv->base + MLXBF_GIGE_INT_EN); 183 184 return 0; 185 186 napi_deinit: 187 netif_stop_queue(netdev); 188 napi_disable(&priv->napi); 189 netif_napi_del(&priv->napi); 190 mlxbf_gige_rx_deinit(priv); 191 192 tx_deinit: 193 mlxbf_gige_tx_deinit(priv); 194 195 phy_deinit: 196 phy_stop(phydev); 197 return err; 198 } 199 200 static int mlxbf_gige_stop(struct net_device *netdev) 201 { 202 struct mlxbf_gige *priv = netdev_priv(netdev); 203 204 writeq(0, priv->base + MLXBF_GIGE_INT_EN); 205 netif_stop_queue(netdev); 206 napi_disable(&priv->napi); 207 netif_napi_del(&priv->napi); 208 mlxbf_gige_free_irqs(priv); 209 210 phy_stop(netdev->phydev); 211 212 mlxbf_gige_rx_deinit(priv); 213 mlxbf_gige_tx_deinit(priv); 214 mlxbf_gige_cache_stats(priv); 215 mlxbf_gige_clean_port(priv); 216 217 return 0; 218 } 219 220 static int mlxbf_gige_eth_ioctl(struct net_device *netdev, 221 struct ifreq *ifr, int cmd) 222 { 223 if (!(netif_running(netdev))) 224 return -EINVAL; 225 226 return phy_mii_ioctl(netdev->phydev, ifr, cmd); 227 } 228 229 static void mlxbf_gige_set_rx_mode(struct net_device *netdev) 230 { 231 struct mlxbf_gige *priv = netdev_priv(netdev); 232 bool new_promisc_enabled; 233 234 new_promisc_enabled = netdev->flags & IFF_PROMISC; 235 236 /* Only write to the hardware registers if the new setting 237 * of promiscuous mode is different from the current one. 238 */ 239 if (new_promisc_enabled != priv->promisc_enabled) { 240 priv->promisc_enabled = new_promisc_enabled; 241 242 if (new_promisc_enabled) 243 mlxbf_gige_enable_promisc(priv); 244 else 245 mlxbf_gige_disable_promisc(priv); 246 } 247 } 248 249 static void mlxbf_gige_get_stats64(struct net_device *netdev, 250 struct rtnl_link_stats64 *stats) 251 { 252 struct mlxbf_gige *priv = netdev_priv(netdev); 253 254 netdev_stats_to_stats64(stats, &netdev->stats); 255 256 stats->rx_length_errors = priv->stats.rx_truncate_errors; 257 stats->rx_fifo_errors = priv->stats.rx_din_dropped_pkts + 258 readq(priv->base + MLXBF_GIGE_RX_DIN_DROP_COUNTER); 259 stats->rx_crc_errors = priv->stats.rx_mac_errors; 260 stats->rx_errors = stats->rx_length_errors + 261 stats->rx_fifo_errors + 262 stats->rx_crc_errors; 263 264 stats->tx_fifo_errors = priv->stats.tx_fifo_full; 265 stats->tx_errors = stats->tx_fifo_errors; 266 } 267 268 static const struct net_device_ops mlxbf_gige_netdev_ops = { 269 .ndo_open = mlxbf_gige_open, 270 .ndo_stop = mlxbf_gige_stop, 271 .ndo_start_xmit = mlxbf_gige_start_xmit, 272 .ndo_set_mac_address = eth_mac_addr, 273 .ndo_validate_addr = eth_validate_addr, 274 .ndo_eth_ioctl = mlxbf_gige_eth_ioctl, 275 .ndo_set_rx_mode = mlxbf_gige_set_rx_mode, 276 .ndo_get_stats64 = mlxbf_gige_get_stats64, 277 }; 278 279 static void mlxbf_gige_bf2_adjust_link(struct net_device *netdev) 280 { 281 struct phy_device *phydev = netdev->phydev; 282 283 phy_print_status(phydev); 284 } 285 286 static void mlxbf_gige_bf3_adjust_link(struct net_device *netdev) 287 { 288 struct mlxbf_gige *priv = netdev_priv(netdev); 289 struct phy_device *phydev = netdev->phydev; 290 u8 sgmii_mode; 291 u16 ipg_size; 292 u32 val; 293 294 if (phydev->link && phydev->speed != priv->prev_speed) { 295 switch (phydev->speed) { 296 case 1000: 297 ipg_size = MLXBF_GIGE_1G_IPG_SIZE; 298 sgmii_mode = MLXBF_GIGE_1G_SGMII_MODE; 299 break; 300 case 100: 301 ipg_size = MLXBF_GIGE_100M_IPG_SIZE; 302 sgmii_mode = MLXBF_GIGE_100M_SGMII_MODE; 303 break; 304 case 10: 305 ipg_size = MLXBF_GIGE_10M_IPG_SIZE; 306 sgmii_mode = MLXBF_GIGE_10M_SGMII_MODE; 307 break; 308 default: 309 return; 310 } 311 312 val = readl(priv->plu_base + MLXBF_GIGE_PLU_TX_REG0); 313 val &= ~(MLXBF_GIGE_PLU_TX_IPG_SIZE_MASK | MLXBF_GIGE_PLU_TX_SGMII_MODE_MASK); 314 val |= FIELD_PREP(MLXBF_GIGE_PLU_TX_IPG_SIZE_MASK, ipg_size); 315 val |= FIELD_PREP(MLXBF_GIGE_PLU_TX_SGMII_MODE_MASK, sgmii_mode); 316 writel(val, priv->plu_base + MLXBF_GIGE_PLU_TX_REG0); 317 318 val = readl(priv->plu_base + MLXBF_GIGE_PLU_RX_REG0); 319 val &= ~MLXBF_GIGE_PLU_RX_SGMII_MODE_MASK; 320 val |= FIELD_PREP(MLXBF_GIGE_PLU_RX_SGMII_MODE_MASK, sgmii_mode); 321 writel(val, priv->plu_base + MLXBF_GIGE_PLU_RX_REG0); 322 323 priv->prev_speed = phydev->speed; 324 } 325 326 phy_print_status(phydev); 327 } 328 329 static void mlxbf_gige_bf2_set_phy_link_mode(struct phy_device *phydev) 330 { 331 /* MAC only supports 1000T full duplex mode */ 332 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 333 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Full_BIT); 334 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT); 335 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT); 336 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT); 337 338 /* Only symmetric pause with flow control enabled is supported so no 339 * need to negotiate pause. 340 */ 341 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->advertising); 342 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->advertising); 343 } 344 345 static void mlxbf_gige_bf3_set_phy_link_mode(struct phy_device *phydev) 346 { 347 /* MAC only supports full duplex mode */ 348 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 349 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT); 350 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT); 351 352 /* Only symmetric pause with flow control enabled is supported so no 353 * need to negotiate pause. 354 */ 355 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->advertising); 356 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->advertising); 357 } 358 359 static struct mlxbf_gige_link_cfg mlxbf_gige_link_cfgs[] = { 360 [MLXBF_GIGE_VERSION_BF2] = { 361 .set_phy_link_mode = mlxbf_gige_bf2_set_phy_link_mode, 362 .adjust_link = mlxbf_gige_bf2_adjust_link, 363 .phy_mode = PHY_INTERFACE_MODE_GMII 364 }, 365 [MLXBF_GIGE_VERSION_BF3] = { 366 .set_phy_link_mode = mlxbf_gige_bf3_set_phy_link_mode, 367 .adjust_link = mlxbf_gige_bf3_adjust_link, 368 .phy_mode = PHY_INTERFACE_MODE_SGMII 369 } 370 }; 371 372 static int mlxbf_gige_probe(struct platform_device *pdev) 373 { 374 struct phy_device *phydev; 375 struct net_device *netdev; 376 struct mlxbf_gige *priv; 377 void __iomem *llu_base; 378 void __iomem *plu_base; 379 void __iomem *base; 380 int addr, phy_irq; 381 int err; 382 383 base = devm_platform_ioremap_resource(pdev, MLXBF_GIGE_RES_MAC); 384 if (IS_ERR(base)) 385 return PTR_ERR(base); 386 387 llu_base = devm_platform_ioremap_resource(pdev, MLXBF_GIGE_RES_LLU); 388 if (IS_ERR(llu_base)) 389 return PTR_ERR(llu_base); 390 391 plu_base = devm_platform_ioremap_resource(pdev, MLXBF_GIGE_RES_PLU); 392 if (IS_ERR(plu_base)) 393 return PTR_ERR(plu_base); 394 395 netdev = devm_alloc_etherdev(&pdev->dev, sizeof(*priv)); 396 if (!netdev) 397 return -ENOMEM; 398 399 SET_NETDEV_DEV(netdev, &pdev->dev); 400 netdev->netdev_ops = &mlxbf_gige_netdev_ops; 401 netdev->ethtool_ops = &mlxbf_gige_ethtool_ops; 402 priv = netdev_priv(netdev); 403 priv->netdev = netdev; 404 405 platform_set_drvdata(pdev, priv); 406 priv->dev = &pdev->dev; 407 priv->pdev = pdev; 408 409 spin_lock_init(&priv->lock); 410 411 priv->hw_version = readq(base + MLXBF_GIGE_VERSION); 412 413 /* Attach MDIO device */ 414 err = mlxbf_gige_mdio_probe(pdev, priv); 415 if (err) 416 return err; 417 418 priv->base = base; 419 priv->llu_base = llu_base; 420 priv->plu_base = plu_base; 421 422 priv->rx_q_entries = MLXBF_GIGE_DEFAULT_RXQ_SZ; 423 priv->tx_q_entries = MLXBF_GIGE_DEFAULT_TXQ_SZ; 424 425 /* Write initial MAC address to hardware */ 426 mlxbf_gige_initial_mac(priv); 427 428 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 429 if (err) { 430 dev_err(&pdev->dev, "DMA configuration failed: 0x%x\n", err); 431 goto out; 432 } 433 434 priv->error_irq = platform_get_irq(pdev, MLXBF_GIGE_ERROR_INTR_IDX); 435 priv->rx_irq = platform_get_irq(pdev, MLXBF_GIGE_RECEIVE_PKT_INTR_IDX); 436 priv->llu_plu_irq = platform_get_irq(pdev, MLXBF_GIGE_LLU_PLU_INTR_IDX); 437 438 phy_irq = acpi_dev_gpio_irq_get_by(ACPI_COMPANION(&pdev->dev), "phy-gpios", 0); 439 if (phy_irq < 0) { 440 dev_err(&pdev->dev, "Error getting PHY irq. Use polling instead"); 441 phy_irq = PHY_POLL; 442 } 443 444 phydev = phy_find_first(priv->mdiobus); 445 if (!phydev) { 446 err = -ENODEV; 447 goto out; 448 } 449 450 addr = phydev->mdio.addr; 451 priv->mdiobus->irq[addr] = phy_irq; 452 phydev->irq = phy_irq; 453 454 err = phy_connect_direct(netdev, phydev, 455 mlxbf_gige_link_cfgs[priv->hw_version].adjust_link, 456 mlxbf_gige_link_cfgs[priv->hw_version].phy_mode); 457 if (err) { 458 dev_err(&pdev->dev, "Could not attach to PHY\n"); 459 goto out; 460 } 461 462 mlxbf_gige_link_cfgs[priv->hw_version].set_phy_link_mode(phydev); 463 464 /* Display information about attached PHY device */ 465 phy_attached_info(phydev); 466 467 err = register_netdev(netdev); 468 if (err) { 469 dev_err(&pdev->dev, "Failed to register netdev\n"); 470 phy_disconnect(phydev); 471 goto out; 472 } 473 474 return 0; 475 476 out: 477 mlxbf_gige_mdio_remove(priv); 478 return err; 479 } 480 481 static void mlxbf_gige_remove(struct platform_device *pdev) 482 { 483 struct mlxbf_gige *priv = platform_get_drvdata(pdev); 484 485 unregister_netdev(priv->netdev); 486 phy_disconnect(priv->netdev->phydev); 487 mlxbf_gige_mdio_remove(priv); 488 platform_set_drvdata(pdev, NULL); 489 } 490 491 static void mlxbf_gige_shutdown(struct platform_device *pdev) 492 { 493 struct mlxbf_gige *priv = platform_get_drvdata(pdev); 494 495 writeq(0, priv->base + MLXBF_GIGE_INT_EN); 496 mlxbf_gige_clean_port(priv); 497 } 498 499 static const struct acpi_device_id __maybe_unused mlxbf_gige_acpi_match[] = { 500 { "MLNXBF17", 0 }, 501 {}, 502 }; 503 MODULE_DEVICE_TABLE(acpi, mlxbf_gige_acpi_match); 504 505 static struct platform_driver mlxbf_gige_driver = { 506 .probe = mlxbf_gige_probe, 507 .remove_new = mlxbf_gige_remove, 508 .shutdown = mlxbf_gige_shutdown, 509 .driver = { 510 .name = KBUILD_MODNAME, 511 .acpi_match_table = ACPI_PTR(mlxbf_gige_acpi_match), 512 }, 513 }; 514 515 module_platform_driver(mlxbf_gige_driver); 516 517 MODULE_DESCRIPTION("Mellanox BlueField SoC Gigabit Ethernet Driver"); 518 MODULE_AUTHOR("David Thompson <davthompson@nvidia.com>"); 519 MODULE_AUTHOR("Asmaa Mnebhi <asmaa@nvidia.com>"); 520 MODULE_LICENSE("Dual BSD/GPL"); 521