1f92e1869SDavid Thompson /* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */ 2f92e1869SDavid Thompson 3f92e1869SDavid Thompson /* Header file for Gigabit Ethernet driver for Mellanox BlueField SoC 4f92e1869SDavid Thompson * - this file contains software data structures and any chip-specific 5f92e1869SDavid Thompson * data structures (e.g. TX WQE format) that are memory resident. 6f92e1869SDavid Thompson * 7f92e1869SDavid Thompson * Copyright (C) 2020-2021 NVIDIA CORPORATION & AFFILIATES 8f92e1869SDavid Thompson */ 9f92e1869SDavid Thompson 10f92e1869SDavid Thompson #ifndef __MLXBF_GIGE_H__ 11f92e1869SDavid Thompson #define __MLXBF_GIGE_H__ 12f92e1869SDavid Thompson 13f92e1869SDavid Thompson #include <linux/io-64-nonatomic-lo-hi.h> 14f92e1869SDavid Thompson #include <linux/irqreturn.h> 15f92e1869SDavid Thompson #include <linux/netdevice.h> 16f92e1869SDavid Thompson #include <linux/irq.h> 1720d03d4dSDavid Thompson #include <linux/phy.h> 18f92e1869SDavid Thompson 19f92e1869SDavid Thompson /* The silicon design supports a maximum RX ring size of 20f92e1869SDavid Thompson * 32K entries. Based on current testing this maximum size 21f92e1869SDavid Thompson * is not required to be supported. Instead the RX ring 22f92e1869SDavid Thompson * will be capped at a realistic value of 1024 entries. 23f92e1869SDavid Thompson */ 24f92e1869SDavid Thompson #define MLXBF_GIGE_MIN_RXQ_SZ 32 25f92e1869SDavid Thompson #define MLXBF_GIGE_MAX_RXQ_SZ 1024 26f92e1869SDavid Thompson #define MLXBF_GIGE_DEFAULT_RXQ_SZ 128 27f92e1869SDavid Thompson 28f92e1869SDavid Thompson #define MLXBF_GIGE_MIN_TXQ_SZ 4 29f92e1869SDavid Thompson #define MLXBF_GIGE_MAX_TXQ_SZ 256 30f92e1869SDavid Thompson #define MLXBF_GIGE_DEFAULT_TXQ_SZ 128 31f92e1869SDavid Thompson 32f92e1869SDavid Thompson #define MLXBF_GIGE_DEFAULT_BUF_SZ 2048 33f92e1869SDavid Thompson 34f92e1869SDavid Thompson #define MLXBF_GIGE_DMA_PAGE_SZ 4096 35f92e1869SDavid Thompson #define MLXBF_GIGE_DMA_PAGE_SHIFT 12 36f92e1869SDavid Thompson 37f92e1869SDavid Thompson /* There are four individual MAC RX filters. Currently 38f92e1869SDavid Thompson * two of them are being used: one for the broadcast MAC 39f92e1869SDavid Thompson * (index 0) and one for local MAC (index 1) 40f92e1869SDavid Thompson */ 41f92e1869SDavid Thompson #define MLXBF_GIGE_BCAST_MAC_FILTER_IDX 0 42f92e1869SDavid Thompson #define MLXBF_GIGE_LOCAL_MAC_FILTER_IDX 1 43*df934abbSDavid Thompson #define MLXBF_GIGE_MAX_FILTER_IDX 3 44f92e1869SDavid Thompson 45f92e1869SDavid Thompson /* Define for broadcast MAC literal */ 46f92e1869SDavid Thompson #define BCAST_MAC_ADDR 0xFFFFFFFFFFFF 47f92e1869SDavid Thompson 48f92e1869SDavid Thompson /* There are three individual interrupts: 49f92e1869SDavid Thompson * 1) Errors, "OOB" interrupt line 50f92e1869SDavid Thompson * 2) Receive Packet, "OOB_LLU" interrupt line 51f92e1869SDavid Thompson * 3) LLU and PLU Events, "OOB_PLU" interrupt line 52f92e1869SDavid Thompson */ 53f92e1869SDavid Thompson #define MLXBF_GIGE_ERROR_INTR_IDX 0 54f92e1869SDavid Thompson #define MLXBF_GIGE_RECEIVE_PKT_INTR_IDX 1 55f92e1869SDavid Thompson #define MLXBF_GIGE_LLU_PLU_INTR_IDX 2 56f92e1869SDavid Thompson 57f92e1869SDavid Thompson struct mlxbf_gige_stats { 58f92e1869SDavid Thompson u64 hw_access_errors; 59f92e1869SDavid Thompson u64 tx_invalid_checksums; 60f92e1869SDavid Thompson u64 tx_small_frames; 61f92e1869SDavid Thompson u64 tx_index_errors; 62f92e1869SDavid Thompson u64 sw_config_errors; 63f92e1869SDavid Thompson u64 sw_access_errors; 64f92e1869SDavid Thompson u64 rx_truncate_errors; 65f92e1869SDavid Thompson u64 rx_mac_errors; 66f92e1869SDavid Thompson u64 rx_din_dropped_pkts; 67f92e1869SDavid Thompson u64 tx_fifo_full; 68f92e1869SDavid Thompson u64 rx_filter_passed_pkts; 69f92e1869SDavid Thompson u64 rx_filter_discard_pkts; 70f92e1869SDavid Thompson }; 71f92e1869SDavid Thompson 722321d69fSDavid Thompson struct mlxbf_gige_reg_param { 732321d69fSDavid Thompson u32 mask; 742321d69fSDavid Thompson u32 shift; 752321d69fSDavid Thompson }; 762321d69fSDavid Thompson 772321d69fSDavid Thompson struct mlxbf_gige_mdio_gw { 782321d69fSDavid Thompson u32 gw_address; 792321d69fSDavid Thompson u32 read_data_address; 802321d69fSDavid Thompson struct mlxbf_gige_reg_param busy; 812321d69fSDavid Thompson struct mlxbf_gige_reg_param write_data; 822321d69fSDavid Thompson struct mlxbf_gige_reg_param read_data; 832321d69fSDavid Thompson struct mlxbf_gige_reg_param devad; 842321d69fSDavid Thompson struct mlxbf_gige_reg_param partad; 852321d69fSDavid Thompson struct mlxbf_gige_reg_param opcode; 862321d69fSDavid Thompson struct mlxbf_gige_reg_param st1; 872321d69fSDavid Thompson }; 882321d69fSDavid Thompson 8920d03d4dSDavid Thompson struct mlxbf_gige_link_cfg { 9020d03d4dSDavid Thompson void (*set_phy_link_mode)(struct phy_device *phydev); 9120d03d4dSDavid Thompson void (*adjust_link)(struct net_device *netdev); 9220d03d4dSDavid Thompson phy_interface_t phy_mode; 9320d03d4dSDavid Thompson }; 9420d03d4dSDavid Thompson 95f92e1869SDavid Thompson struct mlxbf_gige { 96f92e1869SDavid Thompson void __iomem *base; 97f92e1869SDavid Thompson void __iomem *llu_base; 98f92e1869SDavid Thompson void __iomem *plu_base; 99f92e1869SDavid Thompson struct device *dev; 100f92e1869SDavid Thompson struct net_device *netdev; 101f92e1869SDavid Thompson struct platform_device *pdev; 102f92e1869SDavid Thompson void __iomem *mdio_io; 1033a1a274eSDavid Thompson void __iomem *clk_io; 104f92e1869SDavid Thompson struct mii_bus *mdiobus; 105f92e1869SDavid Thompson spinlock_t lock; /* for packet processing indices */ 106f92e1869SDavid Thompson u16 rx_q_entries; 107f92e1869SDavid Thompson u16 tx_q_entries; 108f92e1869SDavid Thompson u64 *tx_wqe_base; 109f92e1869SDavid Thompson dma_addr_t tx_wqe_base_dma; 110f92e1869SDavid Thompson u64 *tx_wqe_next; 111f92e1869SDavid Thompson u64 *tx_cc; 112f92e1869SDavid Thompson dma_addr_t tx_cc_dma; 113f92e1869SDavid Thompson dma_addr_t *rx_wqe_base; 114f92e1869SDavid Thompson dma_addr_t rx_wqe_base_dma; 115f92e1869SDavid Thompson u64 *rx_cqe_base; 116f92e1869SDavid Thompson dma_addr_t rx_cqe_base_dma; 117f92e1869SDavid Thompson u16 tx_pi; 118f92e1869SDavid Thompson u16 prev_tx_ci; 119f92e1869SDavid Thompson struct sk_buff *rx_skb[MLXBF_GIGE_MAX_RXQ_SZ]; 120f92e1869SDavid Thompson struct sk_buff *tx_skb[MLXBF_GIGE_MAX_TXQ_SZ]; 121f92e1869SDavid Thompson int error_irq; 122f92e1869SDavid Thompson int rx_irq; 123f92e1869SDavid Thompson int llu_plu_irq; 124f92e1869SDavid Thompson int phy_irq; 125f92e1869SDavid Thompson int hw_phy_irq; 126f92e1869SDavid Thompson bool promisc_enabled; 127f92e1869SDavid Thompson u8 valid_polarity; 128f92e1869SDavid Thompson struct napi_struct napi; 129f92e1869SDavid Thompson struct mlxbf_gige_stats stats; 1302321d69fSDavid Thompson u8 hw_version; 1312321d69fSDavid Thompson struct mlxbf_gige_mdio_gw *mdio_gw; 13220d03d4dSDavid Thompson int prev_speed; 133f92e1869SDavid Thompson }; 134f92e1869SDavid Thompson 135f92e1869SDavid Thompson /* Rx Work Queue Element definitions */ 136f92e1869SDavid Thompson #define MLXBF_GIGE_RX_WQE_SZ 8 137f92e1869SDavid Thompson 138f92e1869SDavid Thompson /* Rx Completion Queue Element definitions */ 139f92e1869SDavid Thompson #define MLXBF_GIGE_RX_CQE_SZ 8 140f92e1869SDavid Thompson #define MLXBF_GIGE_RX_CQE_PKT_LEN_MASK GENMASK(10, 0) 141f92e1869SDavid Thompson #define MLXBF_GIGE_RX_CQE_VALID_MASK GENMASK(11, 11) 142f92e1869SDavid Thompson #define MLXBF_GIGE_RX_CQE_PKT_STATUS_MASK GENMASK(15, 12) 143f92e1869SDavid Thompson #define MLXBF_GIGE_RX_CQE_PKT_STATUS_MAC_ERR GENMASK(12, 12) 144f92e1869SDavid Thompson #define MLXBF_GIGE_RX_CQE_PKT_STATUS_TRUNCATED GENMASK(13, 13) 145f92e1869SDavid Thompson #define MLXBF_GIGE_RX_CQE_CHKSUM_MASK GENMASK(31, 16) 146f92e1869SDavid Thompson 147f92e1869SDavid Thompson /* Tx Work Queue Element definitions */ 148f92e1869SDavid Thompson #define MLXBF_GIGE_TX_WQE_SZ_QWORDS 2 149f92e1869SDavid Thompson #define MLXBF_GIGE_TX_WQE_SZ 16 150f92e1869SDavid Thompson #define MLXBF_GIGE_TX_WQE_PKT_LEN_MASK GENMASK(10, 0) 151f92e1869SDavid Thompson #define MLXBF_GIGE_TX_WQE_UPDATE_MASK GENMASK(31, 31) 152f92e1869SDavid Thompson #define MLXBF_GIGE_TX_WQE_CHKSUM_LEN_MASK GENMASK(42, 32) 153f92e1869SDavid Thompson #define MLXBF_GIGE_TX_WQE_CHKSUM_START_MASK GENMASK(55, 48) 154f92e1869SDavid Thompson #define MLXBF_GIGE_TX_WQE_CHKSUM_OFFSET_MASK GENMASK(63, 56) 155f92e1869SDavid Thompson 156f92e1869SDavid Thompson /* Macro to return packet length of specified TX WQE */ 157f92e1869SDavid Thompson #define MLXBF_GIGE_TX_WQE_PKT_LEN(tx_wqe_addr) \ 158f92e1869SDavid Thompson (*((tx_wqe_addr) + 1) & MLXBF_GIGE_TX_WQE_PKT_LEN_MASK) 159f92e1869SDavid Thompson 160f92e1869SDavid Thompson /* Tx Completion Count */ 161f92e1869SDavid Thompson #define MLXBF_GIGE_TX_CC_SZ 8 162f92e1869SDavid Thompson 163f92e1869SDavid Thompson /* List of resources in ACPI table */ 164f92e1869SDavid Thompson enum mlxbf_gige_res { 165f92e1869SDavid Thompson MLXBF_GIGE_RES_MAC, 166f92e1869SDavid Thompson MLXBF_GIGE_RES_MDIO9, 167f92e1869SDavid Thompson MLXBF_GIGE_RES_GPIO0, 168f92e1869SDavid Thompson MLXBF_GIGE_RES_LLU, 1693a1a274eSDavid Thompson MLXBF_GIGE_RES_PLU, 1703a1a274eSDavid Thompson MLXBF_GIGE_RES_CLK 171f92e1869SDavid Thompson }; 172f92e1869SDavid Thompson 173f92e1869SDavid Thompson /* Version of register data returned by mlxbf_gige_get_regs() */ 174f92e1869SDavid Thompson #define MLXBF_GIGE_REGS_VERSION 1 175f92e1869SDavid Thompson 176f92e1869SDavid Thompson int mlxbf_gige_mdio_probe(struct platform_device *pdev, 177f92e1869SDavid Thompson struct mlxbf_gige *priv); 178f92e1869SDavid Thompson void mlxbf_gige_mdio_remove(struct mlxbf_gige *priv); 179*df934abbSDavid Thompson 180*df934abbSDavid Thompson void mlxbf_gige_enable_multicast_rx(struct mlxbf_gige *priv); 181*df934abbSDavid Thompson void mlxbf_gige_disable_multicast_rx(struct mlxbf_gige *priv); 182*df934abbSDavid Thompson void mlxbf_gige_enable_mac_rx_filter(struct mlxbf_gige *priv, 183*df934abbSDavid Thompson unsigned int index); 184*df934abbSDavid Thompson void mlxbf_gige_disable_mac_rx_filter(struct mlxbf_gige *priv, 185*df934abbSDavid Thompson unsigned int index); 186f92e1869SDavid Thompson void mlxbf_gige_set_mac_rx_filter(struct mlxbf_gige *priv, 187f92e1869SDavid Thompson unsigned int index, u64 dmac); 188f92e1869SDavid Thompson void mlxbf_gige_get_mac_rx_filter(struct mlxbf_gige *priv, 189f92e1869SDavid Thompson unsigned int index, u64 *dmac); 190f92e1869SDavid Thompson void mlxbf_gige_enable_promisc(struct mlxbf_gige *priv); 191f92e1869SDavid Thompson void mlxbf_gige_disable_promisc(struct mlxbf_gige *priv); 192f92e1869SDavid Thompson int mlxbf_gige_rx_init(struct mlxbf_gige *priv); 193f92e1869SDavid Thompson void mlxbf_gige_rx_deinit(struct mlxbf_gige *priv); 194f92e1869SDavid Thompson int mlxbf_gige_tx_init(struct mlxbf_gige *priv); 195f92e1869SDavid Thompson void mlxbf_gige_tx_deinit(struct mlxbf_gige *priv); 196f92e1869SDavid Thompson bool mlxbf_gige_handle_tx_complete(struct mlxbf_gige *priv); 197f92e1869SDavid Thompson netdev_tx_t mlxbf_gige_start_xmit(struct sk_buff *skb, 198f92e1869SDavid Thompson struct net_device *netdev); 199f92e1869SDavid Thompson struct sk_buff *mlxbf_gige_alloc_skb(struct mlxbf_gige *priv, 200f92e1869SDavid Thompson unsigned int map_len, 201f92e1869SDavid Thompson dma_addr_t *buf_dma, 202f92e1869SDavid Thompson enum dma_data_direction dir); 203f92e1869SDavid Thompson int mlxbf_gige_request_irqs(struct mlxbf_gige *priv); 204f92e1869SDavid Thompson void mlxbf_gige_free_irqs(struct mlxbf_gige *priv); 205f92e1869SDavid Thompson int mlxbf_gige_poll(struct napi_struct *napi, int budget); 206f92e1869SDavid Thompson extern const struct ethtool_ops mlxbf_gige_ethtool_ops; 207f92e1869SDavid Thompson void mlxbf_gige_update_tx_wqe_next(struct mlxbf_gige *priv); 208f92e1869SDavid Thompson 209f92e1869SDavid Thompson #endif /* !defined(__MLXBF_GIGE_H__) */ 210