1 /* 2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34 #ifndef _MLX4_EN_H_ 35 #define _MLX4_EN_H_ 36 37 #include <linux/bitops.h> 38 #include <linux/compiler.h> 39 #include <linux/list.h> 40 #include <linux/mutex.h> 41 #include <linux/netdevice.h> 42 #include <linux/if_vlan.h> 43 44 #include <linux/mlx4/device.h> 45 #include <linux/mlx4/qp.h> 46 #include <linux/mlx4/cq.h> 47 #include <linux/mlx4/srq.h> 48 #include <linux/mlx4/doorbell.h> 49 #include <linux/mlx4/cmd.h> 50 51 #include "en_port.h" 52 53 #define DRV_NAME "mlx4_en" 54 #define DRV_VERSION "1.5.4.2" 55 #define DRV_RELDATE "October 2011" 56 57 #define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN) 58 59 /* 60 * Device constants 61 */ 62 63 64 #define MLX4_EN_PAGE_SHIFT 12 65 #define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT) 66 #define MAX_RX_RINGS 16 67 #define MIN_RX_RINGS 4 68 #define TXBB_SIZE 64 69 #define HEADROOM (2048 / TXBB_SIZE + 1) 70 #define STAMP_STRIDE 64 71 #define STAMP_DWORDS (STAMP_STRIDE / 4) 72 #define STAMP_SHIFT 31 73 #define STAMP_VAL 0x7fffffff 74 #define STATS_DELAY (HZ / 4) 75 76 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */ 77 #define MAX_DESC_SIZE 512 78 #define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE) 79 80 /* 81 * OS related constants and tunables 82 */ 83 84 #define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ) 85 86 #define MLX4_EN_ALLOC_ORDER 2 87 #define MLX4_EN_ALLOC_SIZE (PAGE_SIZE << MLX4_EN_ALLOC_ORDER) 88 89 #define MLX4_EN_MAX_LRO_DESCRIPTORS 32 90 91 /* Receive fragment sizes; we use at most 4 fragments (for 9600 byte MTU 92 * and 4K allocations) */ 93 enum { 94 FRAG_SZ0 = 512 - NET_IP_ALIGN, 95 FRAG_SZ1 = 1024, 96 FRAG_SZ2 = 4096, 97 FRAG_SZ3 = MLX4_EN_ALLOC_SIZE 98 }; 99 #define MLX4_EN_MAX_RX_FRAGS 4 100 101 /* Maximum ring sizes */ 102 #define MLX4_EN_MAX_TX_SIZE 8192 103 #define MLX4_EN_MAX_RX_SIZE 8192 104 105 /* Minimum ring size for our page-allocation sceme to work */ 106 #define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES) 107 #define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE) 108 109 #define MLX4_EN_SMALL_PKT_SIZE 64 110 #define MLX4_EN_NUM_TX_RINGS 8 111 #define MLX4_EN_NUM_PPP_RINGS 8 112 #define MAX_TX_RINGS (MLX4_EN_NUM_TX_RINGS + MLX4_EN_NUM_PPP_RINGS) 113 #define MLX4_EN_DEF_TX_RING_SIZE 512 114 #define MLX4_EN_DEF_RX_RING_SIZE 1024 115 116 /* Target number of packets to coalesce with interrupt moderation */ 117 #define MLX4_EN_RX_COAL_TARGET 44 118 #define MLX4_EN_RX_COAL_TIME 0x10 119 120 #define MLX4_EN_TX_COAL_PKTS 5 121 #define MLX4_EN_TX_COAL_TIME 0x80 122 123 #define MLX4_EN_RX_RATE_LOW 400000 124 #define MLX4_EN_RX_COAL_TIME_LOW 0 125 #define MLX4_EN_RX_RATE_HIGH 450000 126 #define MLX4_EN_RX_COAL_TIME_HIGH 128 127 #define MLX4_EN_RX_SIZE_THRESH 1024 128 #define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH) 129 #define MLX4_EN_SAMPLE_INTERVAL 0 130 #define MLX4_EN_AVG_PKT_SMALL 256 131 132 #define MLX4_EN_AUTO_CONF 0xffff 133 134 #define MLX4_EN_DEF_RX_PAUSE 1 135 #define MLX4_EN_DEF_TX_PAUSE 1 136 137 /* Interval between successive polls in the Tx routine when polling is used 138 instead of interrupts (in per-core Tx rings) - should be power of 2 */ 139 #define MLX4_EN_TX_POLL_MODER 16 140 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4) 141 142 #define ETH_LLC_SNAP_SIZE 8 143 144 #define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN) 145 #define HEADER_COPY_SIZE (128 - NET_IP_ALIGN) 146 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN) 147 148 #define MLX4_EN_MIN_MTU 46 149 #define ETH_BCAST 0xffffffffffffULL 150 151 #define MLX4_EN_LOOPBACK_RETRIES 5 152 #define MLX4_EN_LOOPBACK_TIMEOUT 100 153 154 #ifdef MLX4_EN_PERF_STAT 155 /* Number of samples to 'average' */ 156 #define AVG_SIZE 128 157 #define AVG_FACTOR 1024 158 #define NUM_PERF_STATS NUM_PERF_COUNTERS 159 160 #define INC_PERF_COUNTER(cnt) (++(cnt)) 161 #define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add)) 162 #define AVG_PERF_COUNTER(cnt, sample) \ 163 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE) 164 #define GET_PERF_COUNTER(cnt) (cnt) 165 #define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR) 166 167 #else 168 169 #define NUM_PERF_STATS 0 170 #define INC_PERF_COUNTER(cnt) do {} while (0) 171 #define ADD_PERF_COUNTER(cnt, add) do {} while (0) 172 #define AVG_PERF_COUNTER(cnt, sample) do {} while (0) 173 #define GET_PERF_COUNTER(cnt) (0) 174 #define GET_AVG_PERF_COUNTER(cnt) (0) 175 #endif /* MLX4_EN_PERF_STAT */ 176 177 /* 178 * Configurables 179 */ 180 181 enum cq_type { 182 RX = 0, 183 TX = 1, 184 }; 185 186 187 /* 188 * Useful macros 189 */ 190 #define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x)) 191 #define XNOR(x, y) (!(x) == !(y)) 192 #define ILLEGAL_MAC(addr) (addr == 0xffffffffffffULL || addr == 0x0) 193 194 195 struct mlx4_en_tx_info { 196 struct sk_buff *skb; 197 u32 nr_txbb; 198 u8 linear; 199 u8 data_offset; 200 u8 inl; 201 }; 202 203 204 #define MLX4_EN_BIT_DESC_OWN 0x80000000 205 #define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg) 206 #define MLX4_EN_MEMTYPE_PAD 0x100 207 #define DS_SIZE sizeof(struct mlx4_wqe_data_seg) 208 209 210 struct mlx4_en_tx_desc { 211 struct mlx4_wqe_ctrl_seg ctrl; 212 union { 213 struct mlx4_wqe_data_seg data; /* at least one data segment */ 214 struct mlx4_wqe_lso_seg lso; 215 struct mlx4_wqe_inline_seg inl; 216 }; 217 }; 218 219 #define MLX4_EN_USE_SRQ 0x01000000 220 221 #define MLX4_EN_CX3_LOW_ID 0x1000 222 #define MLX4_EN_CX3_HIGH_ID 0x1005 223 224 struct mlx4_en_rx_alloc { 225 struct page *page; 226 u16 offset; 227 }; 228 229 struct mlx4_en_tx_ring { 230 struct mlx4_hwq_resources wqres; 231 u32 size ; /* number of TXBBs */ 232 u32 size_mask; 233 u16 stride; 234 u16 cqn; /* index of port CQ associated with this ring */ 235 u32 prod; 236 u32 cons; 237 u32 buf_size; 238 u32 doorbell_qpn; 239 void *buf; 240 u16 poll_cnt; 241 int blocked; 242 struct mlx4_en_tx_info *tx_info; 243 u8 *bounce_buf; 244 u32 last_nr_txbb; 245 struct mlx4_qp qp; 246 struct mlx4_qp_context context; 247 int qpn; 248 enum mlx4_qp_state qp_state; 249 struct mlx4_srq dummy; 250 unsigned long bytes; 251 unsigned long packets; 252 unsigned long tx_csum; 253 spinlock_t comp_lock; 254 struct mlx4_bf bf; 255 bool bf_enabled; 256 }; 257 258 struct mlx4_en_rx_desc { 259 /* actual number of entries depends on rx ring stride */ 260 struct mlx4_wqe_data_seg data[0]; 261 }; 262 263 struct mlx4_en_rx_ring { 264 struct mlx4_hwq_resources wqres; 265 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS]; 266 u32 size ; /* number of Rx descs*/ 267 u32 actual_size; 268 u32 size_mask; 269 u16 stride; 270 u16 log_stride; 271 u16 cqn; /* index of port CQ associated with this ring */ 272 u32 prod; 273 u32 cons; 274 u32 buf_size; 275 void *buf; 276 void *rx_info; 277 unsigned long bytes; 278 unsigned long packets; 279 unsigned long csum_ok; 280 unsigned long csum_none; 281 }; 282 283 284 static inline int mlx4_en_can_lro(__be16 status) 285 { 286 return (status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 | 287 MLX4_CQE_STATUS_IPV4F | 288 MLX4_CQE_STATUS_IPV6 | 289 MLX4_CQE_STATUS_IPV4OPT | 290 MLX4_CQE_STATUS_TCP | 291 MLX4_CQE_STATUS_UDP | 292 MLX4_CQE_STATUS_IPOK)) == 293 cpu_to_be16(MLX4_CQE_STATUS_IPV4 | 294 MLX4_CQE_STATUS_IPOK | 295 MLX4_CQE_STATUS_TCP); 296 } 297 298 struct mlx4_en_cq { 299 struct mlx4_cq mcq; 300 struct mlx4_hwq_resources wqres; 301 int ring; 302 spinlock_t lock; 303 struct net_device *dev; 304 struct napi_struct napi; 305 /* Per-core Tx cq processing support */ 306 struct timer_list timer; 307 int size; 308 int buf_size; 309 unsigned vector; 310 enum cq_type is_tx; 311 u16 moder_time; 312 u16 moder_cnt; 313 struct mlx4_cqe *buf; 314 #define MLX4_EN_OPCODE_ERROR 0x1e 315 }; 316 317 struct mlx4_en_port_profile { 318 u32 flags; 319 u32 tx_ring_num; 320 u32 rx_ring_num; 321 u32 tx_ring_size; 322 u32 rx_ring_size; 323 u8 rx_pause; 324 u8 rx_ppp; 325 u8 tx_pause; 326 u8 tx_ppp; 327 }; 328 329 struct mlx4_en_profile { 330 int rss_xor; 331 int tcp_rss; 332 int udp_rss; 333 u8 rss_mask; 334 u32 active_ports; 335 u32 small_pkt_int; 336 u8 no_reset; 337 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1]; 338 }; 339 340 struct mlx4_en_dev { 341 struct mlx4_dev *dev; 342 struct pci_dev *pdev; 343 struct mutex state_lock; 344 struct net_device *pndev[MLX4_MAX_PORTS + 1]; 345 u32 port_cnt; 346 bool device_up; 347 struct mlx4_en_profile profile; 348 u32 LSO_support; 349 struct workqueue_struct *workqueue; 350 struct device *dma_device; 351 void __iomem *uar_map; 352 struct mlx4_uar priv_uar; 353 struct mlx4_mr mr; 354 u32 priv_pdn; 355 spinlock_t uar_lock; 356 u8 mac_removed[MLX4_MAX_PORTS + 1]; 357 }; 358 359 360 struct mlx4_en_rss_map { 361 int base_qpn; 362 struct mlx4_qp qps[MAX_RX_RINGS]; 363 enum mlx4_qp_state state[MAX_RX_RINGS]; 364 struct mlx4_qp indir_qp; 365 enum mlx4_qp_state indir_state; 366 }; 367 368 struct mlx4_en_rss_context { 369 __be32 base_qpn; 370 __be32 default_qpn; 371 u16 reserved; 372 u8 hash_fn; 373 u8 flags; 374 __be32 rss_key[10]; 375 __be32 base_qpn_udp; 376 }; 377 378 struct mlx4_en_port_state { 379 int link_state; 380 int link_speed; 381 int transciver; 382 }; 383 384 struct mlx4_en_pkt_stats { 385 unsigned long broadcast; 386 unsigned long rx_prio[8]; 387 unsigned long tx_prio[8]; 388 #define NUM_PKT_STATS 17 389 }; 390 391 struct mlx4_en_port_stats { 392 unsigned long tso_packets; 393 unsigned long queue_stopped; 394 unsigned long wake_queue; 395 unsigned long tx_timeout; 396 unsigned long rx_alloc_failed; 397 unsigned long rx_chksum_good; 398 unsigned long rx_chksum_none; 399 unsigned long tx_chksum_offload; 400 #define NUM_PORT_STATS 8 401 }; 402 403 struct mlx4_en_perf_stats { 404 u32 tx_poll; 405 u64 tx_pktsz_avg; 406 u32 inflight_avg; 407 u16 tx_coal_avg; 408 u16 rx_coal_avg; 409 u32 napi_quota; 410 #define NUM_PERF_COUNTERS 6 411 }; 412 413 struct mlx4_en_frag_info { 414 u16 frag_size; 415 u16 frag_prefix_size; 416 u16 frag_stride; 417 u16 frag_align; 418 u16 last_offset; 419 420 }; 421 422 struct mlx4_en_priv { 423 struct mlx4_en_dev *mdev; 424 struct mlx4_en_port_profile *prof; 425 struct net_device *dev; 426 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 427 struct net_device_stats stats; 428 struct net_device_stats ret_stats; 429 struct mlx4_en_port_state port_state; 430 spinlock_t stats_lock; 431 432 unsigned long last_moder_packets[MAX_RX_RINGS]; 433 unsigned long last_moder_tx_packets; 434 unsigned long last_moder_bytes[MAX_RX_RINGS]; 435 unsigned long last_moder_jiffies; 436 int last_moder_time[MAX_RX_RINGS]; 437 u16 rx_usecs; 438 u16 rx_frames; 439 u16 tx_usecs; 440 u16 tx_frames; 441 u32 pkt_rate_low; 442 u16 rx_usecs_low; 443 u32 pkt_rate_high; 444 u16 rx_usecs_high; 445 u16 sample_interval; 446 u16 adaptive_rx_coal; 447 u32 msg_enable; 448 u32 loopback_ok; 449 u32 validate_loopback; 450 451 struct mlx4_hwq_resources res; 452 int link_state; 453 int last_link_state; 454 bool port_up; 455 int port; 456 int registered; 457 int allocated; 458 int stride; 459 u64 mac; 460 int mac_index; 461 unsigned max_mtu; 462 int base_qpn; 463 464 struct mlx4_en_rss_map rss_map; 465 u32 flags; 466 #define MLX4_EN_FLAG_PROMISC 0x1 467 #define MLX4_EN_FLAG_MC_PROMISC 0x2 468 u32 tx_ring_num; 469 u32 rx_ring_num; 470 u32 rx_skb_size; 471 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS]; 472 u16 num_frags; 473 u16 log_rx_info; 474 475 struct mlx4_en_tx_ring tx_ring[MAX_TX_RINGS]; 476 struct mlx4_en_rx_ring rx_ring[MAX_RX_RINGS]; 477 struct mlx4_en_cq tx_cq[MAX_TX_RINGS]; 478 struct mlx4_en_cq rx_cq[MAX_RX_RINGS]; 479 struct work_struct mcast_task; 480 struct work_struct mac_task; 481 struct work_struct watchdog_task; 482 struct work_struct linkstate_task; 483 struct delayed_work stats_task; 484 struct mlx4_en_perf_stats pstats; 485 struct mlx4_en_pkt_stats pkstats; 486 struct mlx4_en_port_stats port_stats; 487 char *mc_addrs; 488 int mc_addrs_cnt; 489 struct mlx4_en_stat_out_mbox hw_stats; 490 int vids[128]; 491 bool wol; 492 }; 493 494 enum mlx4_en_wol { 495 MLX4_EN_WOL_MAGIC = (1ULL << 61), 496 MLX4_EN_WOL_ENABLED = (1ULL << 62), 497 MLX4_EN_WOL_DO_MODIFY = (1ULL << 63), 498 }; 499 500 501 void mlx4_en_destroy_netdev(struct net_device *dev); 502 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port, 503 struct mlx4_en_port_profile *prof); 504 505 int mlx4_en_start_port(struct net_device *dev); 506 void mlx4_en_stop_port(struct net_device *dev); 507 508 void mlx4_en_free_resources(struct mlx4_en_priv *priv); 509 int mlx4_en_alloc_resources(struct mlx4_en_priv *priv); 510 511 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq, 512 int entries, int ring, enum cq_type mode); 513 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 514 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq, 515 int cq_idx); 516 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 517 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 518 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 519 520 void mlx4_en_poll_tx_cq(unsigned long data); 521 void mlx4_en_tx_irq(struct mlx4_cq *mcq); 522 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb); 523 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev); 524 525 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring, 526 int qpn, u32 size, u16 stride); 527 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring); 528 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, 529 struct mlx4_en_tx_ring *ring, 530 int cq); 531 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, 532 struct mlx4_en_tx_ring *ring); 533 534 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, 535 struct mlx4_en_rx_ring *ring, 536 u32 size, u16 stride); 537 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, 538 struct mlx4_en_rx_ring *ring); 539 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv); 540 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, 541 struct mlx4_en_rx_ring *ring); 542 int mlx4_en_process_rx_cq(struct net_device *dev, 543 struct mlx4_en_cq *cq, 544 int budget); 545 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget); 546 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride, 547 int is_tx, int rss, int qpn, int cqn, 548 struct mlx4_qp_context *context); 549 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event); 550 int mlx4_en_map_buffer(struct mlx4_buf *buf); 551 void mlx4_en_unmap_buffer(struct mlx4_buf *buf); 552 553 void mlx4_en_calc_rx_buf(struct net_device *dev); 554 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv); 555 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv); 556 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring); 557 void mlx4_en_rx_irq(struct mlx4_cq *mcq); 558 559 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); 560 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv); 561 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu, 562 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx); 563 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn, 564 u8 promisc); 565 566 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset); 567 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port); 568 569 #define MLX4_EN_NUM_SELF_TEST 5 570 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf); 571 u64 mlx4_en_mac_to_u64(u8 *addr); 572 573 /* 574 * Globals 575 */ 576 extern const struct ethtool_ops mlx4_en_ethtool_ops; 577 578 579 580 /* 581 * printk / logging functions 582 */ 583 584 __printf(3, 4) 585 int en_print(const char *level, const struct mlx4_en_priv *priv, 586 const char *format, ...); 587 588 #define en_dbg(mlevel, priv, format, arg...) \ 589 do { \ 590 if (NETIF_MSG_##mlevel & priv->msg_enable) \ 591 en_print(KERN_DEBUG, priv, format, ##arg); \ 592 } while (0) 593 #define en_warn(priv, format, arg...) \ 594 en_print(KERN_WARNING, priv, format, ##arg) 595 #define en_err(priv, format, arg...) \ 596 en_print(KERN_ERR, priv, format, ##arg) 597 #define en_info(priv, format, arg...) \ 598 en_print(KERN_INFO, priv, format, ## arg) 599 600 #define mlx4_err(mdev, format, arg...) \ 601 pr_err("%s %s: " format, DRV_NAME, \ 602 dev_name(&mdev->pdev->dev), ##arg) 603 #define mlx4_info(mdev, format, arg...) \ 604 pr_info("%s %s: " format, DRV_NAME, \ 605 dev_name(&mdev->pdev->dev), ##arg) 606 #define mlx4_warn(mdev, format, arg...) \ 607 pr_warning("%s %s: " format, DRV_NAME, \ 608 dev_name(&mdev->pdev->dev), ##arg) 609 610 #endif 611