1 /* 2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34 #ifndef _MLX4_EN_H_ 35 #define _MLX4_EN_H_ 36 37 #include <linux/bitops.h> 38 #include <linux/compiler.h> 39 #include <linux/list.h> 40 #include <linux/mutex.h> 41 #include <linux/netdevice.h> 42 #include <linux/if_vlan.h> 43 #include <linux/net_tstamp.h> 44 #ifdef CONFIG_MLX4_EN_DCB 45 #include <linux/dcbnl.h> 46 #endif 47 #include <linux/cpu_rmap.h> 48 #include <linux/ptp_clock_kernel.h> 49 50 #include <linux/mlx4/device.h> 51 #include <linux/mlx4/qp.h> 52 #include <linux/mlx4/cq.h> 53 #include <linux/mlx4/srq.h> 54 #include <linux/mlx4/doorbell.h> 55 #include <linux/mlx4/cmd.h> 56 57 #include "en_port.h" 58 #include "mlx4_stats.h" 59 60 #define DRV_NAME "mlx4_en" 61 #define DRV_VERSION "4.0-0" 62 63 #define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN) 64 65 /* 66 * Device constants 67 */ 68 69 70 #define MLX4_EN_PAGE_SHIFT 12 71 #define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT) 72 #define DEF_RX_RINGS 16 73 #define MAX_RX_RINGS 128 74 #define MIN_RX_RINGS 4 75 #define LOG_TXBB_SIZE 6 76 #define TXBB_SIZE BIT(LOG_TXBB_SIZE) 77 #define HEADROOM (2048 / TXBB_SIZE + 1) 78 #define STAMP_STRIDE 64 79 #define STAMP_DWORDS (STAMP_STRIDE / 4) 80 #define STAMP_SHIFT 31 81 #define STAMP_VAL 0x7fffffff 82 #define STATS_DELAY (HZ / 4) 83 #define SERVICE_TASK_DELAY (HZ / 4) 84 #define MAX_NUM_OF_FS_RULES 256 85 86 #define MLX4_EN_FILTER_HASH_SHIFT 4 87 #define MLX4_EN_FILTER_EXPIRY_QUOTA 60 88 89 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */ 90 #define MAX_DESC_SIZE 512 91 #define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE) 92 93 /* 94 * OS related constants and tunables 95 */ 96 97 #define MLX4_EN_PRIV_FLAGS_BLUEFLAME 1 98 #define MLX4_EN_PRIV_FLAGS_PHV 2 99 100 #define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ) 101 102 /* Use the maximum between 16384 and a single page */ 103 #define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(16384) 104 105 #define MLX4_EN_MAX_RX_FRAGS 4 106 107 /* Maximum ring sizes */ 108 #define MLX4_EN_MAX_TX_SIZE 8192 109 #define MLX4_EN_MAX_RX_SIZE 8192 110 111 /* Minimum ring size for our page-allocation scheme to work */ 112 #define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES) 113 #define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE) 114 115 #define MLX4_EN_SMALL_PKT_SIZE 64 116 #define MLX4_EN_MIN_TX_RING_P_UP 1 117 #define MLX4_EN_MAX_TX_RING_P_UP 32 118 #define MLX4_EN_NUM_UP_LOW 1 119 #define MLX4_EN_NUM_UP_HIGH 8 120 #define MLX4_EN_DEF_RX_RING_SIZE 1024 121 #define MLX4_EN_DEF_TX_RING_SIZE MLX4_EN_DEF_RX_RING_SIZE 122 #define MAX_TX_RINGS (MLX4_EN_MAX_TX_RING_P_UP * \ 123 MLX4_EN_NUM_UP_HIGH) 124 125 #define MLX4_EN_DEFAULT_TX_WORK 256 126 127 /* Target number of packets to coalesce with interrupt moderation */ 128 #define MLX4_EN_RX_COAL_TARGET 44 129 #define MLX4_EN_RX_COAL_TIME 0x10 130 131 #define MLX4_EN_TX_COAL_PKTS 16 132 #define MLX4_EN_TX_COAL_TIME 0x10 133 134 #define MLX4_EN_RX_RATE_LOW 400000 135 #define MLX4_EN_RX_COAL_TIME_LOW 0 136 #define MLX4_EN_RX_RATE_HIGH 450000 137 #define MLX4_EN_RX_COAL_TIME_HIGH 128 138 #define MLX4_EN_RX_SIZE_THRESH 1024 139 #define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH) 140 #define MLX4_EN_SAMPLE_INTERVAL 0 141 #define MLX4_EN_AVG_PKT_SMALL 256 142 143 #define MLX4_EN_AUTO_CONF 0xffff 144 145 #define MLX4_EN_DEF_RX_PAUSE 1 146 #define MLX4_EN_DEF_TX_PAUSE 1 147 148 /* Interval between successive polls in the Tx routine when polling is used 149 instead of interrupts (in per-core Tx rings) - should be power of 2 */ 150 #define MLX4_EN_TX_POLL_MODER 16 151 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4) 152 153 #define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN) 154 #define HEADER_COPY_SIZE (128 - NET_IP_ALIGN) 155 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN) 156 #define PREAMBLE_LEN 8 157 #define MLX4_SELFTEST_LB_MIN_MTU (MLX4_LOOPBACK_TEST_PAYLOAD + NET_IP_ALIGN + \ 158 ETH_HLEN + PREAMBLE_LEN) 159 160 #define MLX4_EN_MIN_MTU 46 161 /* VLAN_HLEN is added twice,to support skb vlan tagged with multiple 162 * headers. (For example: ETH_P_8021Q and ETH_P_8021AD). 163 */ 164 #define MLX4_EN_EFF_MTU(mtu) ((mtu) + ETH_HLEN + (2 * VLAN_HLEN)) 165 #define ETH_BCAST 0xffffffffffffULL 166 167 #define MLX4_EN_LOOPBACK_RETRIES 5 168 #define MLX4_EN_LOOPBACK_TIMEOUT 100 169 170 #ifdef MLX4_EN_PERF_STAT 171 /* Number of samples to 'average' */ 172 #define AVG_SIZE 128 173 #define AVG_FACTOR 1024 174 175 #define INC_PERF_COUNTER(cnt) (++(cnt)) 176 #define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add)) 177 #define AVG_PERF_COUNTER(cnt, sample) \ 178 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE) 179 #define GET_PERF_COUNTER(cnt) (cnt) 180 #define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR) 181 182 #else 183 184 #define INC_PERF_COUNTER(cnt) do {} while (0) 185 #define ADD_PERF_COUNTER(cnt, add) do {} while (0) 186 #define AVG_PERF_COUNTER(cnt, sample) do {} while (0) 187 #define GET_PERF_COUNTER(cnt) (0) 188 #define GET_AVG_PERF_COUNTER(cnt) (0) 189 #endif /* MLX4_EN_PERF_STAT */ 190 191 /* Constants for TX flow */ 192 enum { 193 MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */ 194 MAX_BF = 256, 195 MIN_PKT_LEN = 17, 196 }; 197 198 /* 199 * Configurables 200 */ 201 202 enum cq_type { 203 /* keep tx types first */ 204 TX, 205 TX_XDP, 206 #define MLX4_EN_NUM_TX_TYPES (TX_XDP + 1) 207 RX, 208 }; 209 210 211 /* 212 * Useful macros 213 */ 214 #define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x)) 215 #define XNOR(x, y) (!(x) == !(y)) 216 217 218 struct mlx4_en_tx_info { 219 union { 220 struct sk_buff *skb; 221 struct page *page; 222 }; 223 dma_addr_t map0_dma; 224 u32 map0_byte_count; 225 u32 nr_txbb; 226 u32 nr_bytes; 227 u8 linear; 228 u8 data_offset; 229 u8 inl; 230 u8 ts_requested; 231 u8 nr_maps; 232 } ____cacheline_aligned_in_smp; 233 234 235 #define MLX4_EN_BIT_DESC_OWN 0x80000000 236 #define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg) 237 #define MLX4_EN_MEMTYPE_PAD 0x100 238 #define DS_SIZE sizeof(struct mlx4_wqe_data_seg) 239 240 241 struct mlx4_en_tx_desc { 242 struct mlx4_wqe_ctrl_seg ctrl; 243 union { 244 struct mlx4_wqe_data_seg data; /* at least one data segment */ 245 struct mlx4_wqe_lso_seg lso; 246 struct mlx4_wqe_inline_seg inl; 247 }; 248 }; 249 250 #define MLX4_EN_USE_SRQ 0x01000000 251 252 #define MLX4_EN_CX3_LOW_ID 0x1000 253 #define MLX4_EN_CX3_HIGH_ID 0x1005 254 255 struct mlx4_en_rx_alloc { 256 struct page *page; 257 dma_addr_t dma; 258 u32 page_offset; 259 }; 260 261 #define MLX4_EN_CACHE_SIZE (2 * NAPI_POLL_WEIGHT) 262 263 struct mlx4_en_page_cache { 264 u32 index; 265 struct { 266 struct page *page; 267 dma_addr_t dma; 268 } buf[MLX4_EN_CACHE_SIZE]; 269 }; 270 271 struct mlx4_en_priv; 272 273 struct mlx4_en_tx_ring { 274 /* cache line used and dirtied in tx completion 275 * (mlx4_en_free_tx_buf()) 276 */ 277 u32 last_nr_txbb; 278 u32 cons; 279 unsigned long wake_queue; 280 struct netdev_queue *tx_queue; 281 u32 (*free_tx_desc)(struct mlx4_en_priv *priv, 282 struct mlx4_en_tx_ring *ring, 283 int index, 284 u64 timestamp, int napi_mode); 285 struct mlx4_en_rx_ring *recycle_ring; 286 287 /* cache line used and dirtied in mlx4_en_xmit() */ 288 u32 prod ____cacheline_aligned_in_smp; 289 unsigned int tx_dropped; 290 unsigned long bytes; 291 unsigned long packets; 292 unsigned long tx_csum; 293 unsigned long tso_packets; 294 unsigned long xmit_more; 295 struct mlx4_bf bf; 296 297 /* Following part should be mostly read */ 298 __be32 doorbell_qpn; 299 __be32 mr_key; 300 u32 size; /* number of TXBBs */ 301 u32 size_mask; 302 u32 full_size; 303 u32 buf_size; 304 void *buf; 305 struct mlx4_en_tx_info *tx_info; 306 int qpn; 307 u8 queue_index; 308 bool bf_enabled; 309 bool bf_alloced; 310 u8 hwtstamp_tx_type; 311 u8 *bounce_buf; 312 313 /* Not used in fast path 314 * Only queue_stopped might be used if BQL is not properly working. 315 */ 316 unsigned long queue_stopped; 317 struct mlx4_hwq_resources sp_wqres; 318 struct mlx4_qp sp_qp; 319 struct mlx4_qp_context sp_context; 320 cpumask_t sp_affinity_mask; 321 enum mlx4_qp_state sp_qp_state; 322 u16 sp_stride; 323 u16 sp_cqn; /* index of port CQ associated with this ring */ 324 } ____cacheline_aligned_in_smp; 325 326 struct mlx4_en_rx_desc { 327 /* actual number of entries depends on rx ring stride */ 328 struct mlx4_wqe_data_seg data[0]; 329 }; 330 331 struct mlx4_en_rx_ring { 332 struct mlx4_hwq_resources wqres; 333 u32 size ; /* number of Rx descs*/ 334 u32 actual_size; 335 u32 size_mask; 336 u16 stride; 337 u16 log_stride; 338 u16 cqn; /* index of port CQ associated with this ring */ 339 u32 prod; 340 u32 cons; 341 u32 buf_size; 342 u8 fcs_del; 343 void *buf; 344 void *rx_info; 345 struct bpf_prog __rcu *xdp_prog; 346 struct mlx4_en_page_cache page_cache; 347 unsigned long bytes; 348 unsigned long packets; 349 unsigned long csum_ok; 350 unsigned long csum_none; 351 unsigned long csum_complete; 352 unsigned long rx_alloc_pages; 353 unsigned long xdp_drop; 354 unsigned long xdp_tx; 355 unsigned long xdp_tx_full; 356 unsigned long dropped; 357 int hwtstamp_rx_filter; 358 cpumask_var_t affinity_mask; 359 }; 360 361 struct mlx4_en_cq { 362 struct mlx4_cq mcq; 363 struct mlx4_hwq_resources wqres; 364 int ring; 365 struct net_device *dev; 366 union { 367 struct napi_struct napi; 368 bool xdp_busy; 369 }; 370 int size; 371 int buf_size; 372 int vector; 373 enum cq_type type; 374 u16 moder_time; 375 u16 moder_cnt; 376 struct mlx4_cqe *buf; 377 #define MLX4_EN_OPCODE_ERROR 0x1e 378 379 struct irq_desc *irq_desc; 380 }; 381 382 struct mlx4_en_port_profile { 383 u32 flags; 384 u32 tx_ring_num[MLX4_EN_NUM_TX_TYPES]; 385 u32 rx_ring_num; 386 u32 tx_ring_size; 387 u32 rx_ring_size; 388 u8 num_tx_rings_p_up; 389 u8 rx_pause; 390 u8 rx_ppp; 391 u8 tx_pause; 392 u8 tx_ppp; 393 u8 num_up; 394 int rss_rings; 395 int inline_thold; 396 struct hwtstamp_config hwtstamp_config; 397 }; 398 399 struct mlx4_en_profile { 400 int udp_rss; 401 u8 rss_mask; 402 u32 active_ports; 403 u32 small_pkt_int; 404 u8 no_reset; 405 u8 max_num_tx_rings_p_up; 406 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1]; 407 }; 408 409 struct mlx4_en_dev { 410 struct mlx4_dev *dev; 411 struct pci_dev *pdev; 412 struct mutex state_lock; 413 struct net_device *pndev[MLX4_MAX_PORTS + 1]; 414 struct net_device *upper[MLX4_MAX_PORTS + 1]; 415 u32 port_cnt; 416 bool device_up; 417 struct mlx4_en_profile profile; 418 u32 LSO_support; 419 struct workqueue_struct *workqueue; 420 struct device *dma_device; 421 void __iomem *uar_map; 422 struct mlx4_uar priv_uar; 423 struct mlx4_mr mr; 424 u32 priv_pdn; 425 spinlock_t uar_lock; 426 u8 mac_removed[MLX4_MAX_PORTS + 1]; 427 u32 nominal_c_mult; 428 struct cyclecounter cycles; 429 seqlock_t clock_lock; 430 struct timecounter clock; 431 unsigned long last_overflow_check; 432 struct ptp_clock *ptp_clock; 433 struct ptp_clock_info ptp_clock_info; 434 struct notifier_block nb; 435 }; 436 437 438 struct mlx4_en_rss_map { 439 int base_qpn; 440 struct mlx4_qp qps[MAX_RX_RINGS]; 441 enum mlx4_qp_state state[MAX_RX_RINGS]; 442 struct mlx4_qp *indir_qp; 443 enum mlx4_qp_state indir_state; 444 }; 445 446 enum mlx4_en_port_flag { 447 MLX4_EN_PORT_ANC = 1<<0, /* Auto-negotiation complete */ 448 MLX4_EN_PORT_ANE = 1<<1, /* Auto-negotiation enabled */ 449 }; 450 451 struct mlx4_en_port_state { 452 int link_state; 453 int link_speed; 454 int transceiver; 455 u32 flags; 456 }; 457 458 enum mlx4_en_mclist_act { 459 MCLIST_NONE, 460 MCLIST_REM, 461 MCLIST_ADD, 462 }; 463 464 struct mlx4_en_mc_list { 465 struct list_head list; 466 enum mlx4_en_mclist_act action; 467 u8 addr[ETH_ALEN]; 468 u64 reg_id; 469 u64 tunnel_reg_id; 470 }; 471 472 struct mlx4_en_frag_info { 473 u16 frag_size; 474 u32 frag_stride; 475 }; 476 477 #ifdef CONFIG_MLX4_EN_DCB 478 /* Minimal TC BW - setting to 0 will block traffic */ 479 #define MLX4_EN_BW_MIN 1 480 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */ 481 482 #define MLX4_EN_TC_VENDOR 0 483 #define MLX4_EN_TC_ETS 7 484 485 enum dcb_pfc_type { 486 pfc_disabled = 0, 487 pfc_enabled_full, 488 pfc_enabled_tx, 489 pfc_enabled_rx 490 }; 491 492 struct mlx4_en_cee_config { 493 bool pfc_state; 494 enum dcb_pfc_type dcb_pfc[MLX4_EN_NUM_UP_HIGH]; 495 }; 496 #endif 497 498 struct ethtool_flow_id { 499 struct list_head list; 500 struct ethtool_rx_flow_spec flow_spec; 501 u64 id; 502 }; 503 504 enum { 505 MLX4_EN_FLAG_PROMISC = (1 << 0), 506 MLX4_EN_FLAG_MC_PROMISC = (1 << 1), 507 /* whether we need to enable hardware loopback by putting dmac 508 * in Tx WQE 509 */ 510 MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2), 511 /* whether we need to drop packets that hardware loopback-ed */ 512 MLX4_EN_FLAG_RX_FILTER_NEEDED = (1 << 3), 513 MLX4_EN_FLAG_FORCE_PROMISC = (1 << 4), 514 MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP = (1 << 5), 515 #ifdef CONFIG_MLX4_EN_DCB 516 MLX4_EN_FLAG_DCB_ENABLED = (1 << 6), 517 #endif 518 }; 519 520 #define PORT_BEACON_MAX_LIMIT (65535) 521 #define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE) 522 #define MLX4_EN_MAC_HASH_IDX 5 523 524 struct mlx4_en_stats_bitmap { 525 DECLARE_BITMAP(bitmap, NUM_ALL_STATS); 526 struct mutex mutex; /* for mutual access to stats bitmap */ 527 }; 528 529 struct mlx4_en_priv { 530 struct mlx4_en_dev *mdev; 531 struct mlx4_en_port_profile *prof; 532 struct net_device *dev; 533 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 534 struct mlx4_en_port_state port_state; 535 spinlock_t stats_lock; 536 struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES]; 537 /* To allow rules removal while port is going down */ 538 struct list_head ethtool_list; 539 540 unsigned long last_moder_packets[MAX_RX_RINGS]; 541 unsigned long last_moder_tx_packets; 542 unsigned long last_moder_bytes[MAX_RX_RINGS]; 543 unsigned long last_moder_jiffies; 544 int last_moder_time[MAX_RX_RINGS]; 545 u16 rx_usecs; 546 u16 rx_frames; 547 u16 tx_usecs; 548 u16 tx_frames; 549 u32 pkt_rate_low; 550 u16 rx_usecs_low; 551 u32 pkt_rate_high; 552 u16 rx_usecs_high; 553 u16 sample_interval; 554 u16 adaptive_rx_coal; 555 u32 msg_enable; 556 u32 loopback_ok; 557 u32 validate_loopback; 558 559 struct mlx4_hwq_resources res; 560 int link_state; 561 int last_link_state; 562 bool port_up; 563 int port; 564 int registered; 565 int allocated; 566 int stride; 567 unsigned char current_mac[ETH_ALEN + 2]; 568 int mac_index; 569 unsigned max_mtu; 570 int base_qpn; 571 int cqe_factor; 572 int cqe_size; 573 574 struct mlx4_en_rss_map rss_map; 575 __be32 ctrl_flags; 576 u32 flags; 577 u8 num_tx_rings_p_up; 578 u32 tx_work_limit; 579 u32 tx_ring_num[MLX4_EN_NUM_TX_TYPES]; 580 u32 rx_ring_num; 581 u32 rx_skb_size; 582 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS]; 583 u8 num_frags; 584 u8 log_rx_info; 585 u8 dma_dir; 586 u16 rx_headroom; 587 588 struct mlx4_en_tx_ring **tx_ring[MLX4_EN_NUM_TX_TYPES]; 589 struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS]; 590 struct mlx4_en_cq **tx_cq[MLX4_EN_NUM_TX_TYPES]; 591 struct mlx4_en_cq *rx_cq[MAX_RX_RINGS]; 592 struct mlx4_qp drop_qp; 593 struct work_struct rx_mode_task; 594 struct work_struct watchdog_task; 595 struct work_struct linkstate_task; 596 struct delayed_work stats_task; 597 struct delayed_work service_task; 598 struct work_struct vxlan_add_task; 599 struct work_struct vxlan_del_task; 600 struct mlx4_en_perf_stats pstats; 601 struct mlx4_en_pkt_stats pkstats; 602 struct mlx4_en_counter_stats pf_stats; 603 struct mlx4_en_flow_stats_rx rx_priority_flowstats[MLX4_NUM_PRIORITIES]; 604 struct mlx4_en_flow_stats_tx tx_priority_flowstats[MLX4_NUM_PRIORITIES]; 605 struct mlx4_en_flow_stats_rx rx_flowstats; 606 struct mlx4_en_flow_stats_tx tx_flowstats; 607 struct mlx4_en_port_stats port_stats; 608 struct mlx4_en_xdp_stats xdp_stats; 609 struct mlx4_en_stats_bitmap stats_bitmap; 610 struct list_head mc_list; 611 struct list_head curr_list; 612 u64 broadcast_id; 613 struct mlx4_en_stat_out_mbox hw_stats; 614 int vids[128]; 615 bool wol; 616 struct device *ddev; 617 struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE]; 618 struct hwtstamp_config hwtstamp_config; 619 u32 counter_index; 620 621 #ifdef CONFIG_MLX4_EN_DCB 622 #define MLX4_EN_DCB_ENABLED 0x3 623 struct ieee_ets ets; 624 u16 maxrate[IEEE_8021QAZ_MAX_TCS]; 625 enum dcbnl_cndd_states cndd_state[IEEE_8021QAZ_MAX_TCS]; 626 struct mlx4_en_cee_config cee_config; 627 u8 dcbx_cap; 628 #endif 629 #ifdef CONFIG_RFS_ACCEL 630 spinlock_t filters_lock; 631 int last_filter_id; 632 struct list_head filters; 633 struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT]; 634 #endif 635 u64 tunnel_reg_id; 636 __be16 vxlan_port; 637 638 u32 pflags; 639 u8 rss_key[MLX4_EN_RSS_KEY_SIZE]; 640 u8 rss_hash_fn; 641 }; 642 643 enum mlx4_en_wol { 644 MLX4_EN_WOL_MAGIC = (1ULL << 61), 645 MLX4_EN_WOL_ENABLED = (1ULL << 62), 646 }; 647 648 struct mlx4_mac_entry { 649 struct hlist_node hlist; 650 unsigned char mac[ETH_ALEN + 2]; 651 u64 reg_id; 652 struct rcu_head rcu; 653 }; 654 655 static inline struct mlx4_cqe *mlx4_en_get_cqe(void *buf, int idx, int cqe_sz) 656 { 657 return buf + idx * cqe_sz; 658 } 659 660 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63) 661 662 void mlx4_en_init_ptys2ethtool_map(void); 663 void mlx4_en_update_loopback_state(struct net_device *dev, 664 netdev_features_t features); 665 666 void mlx4_en_destroy_netdev(struct net_device *dev); 667 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port, 668 struct mlx4_en_port_profile *prof); 669 670 int mlx4_en_start_port(struct net_device *dev); 671 void mlx4_en_stop_port(struct net_device *dev, int detach); 672 673 void mlx4_en_set_stats_bitmap(struct mlx4_dev *dev, 674 struct mlx4_en_stats_bitmap *stats_bitmap, 675 u8 rx_ppp, u8 rx_pause, 676 u8 tx_ppp, u8 tx_pause); 677 678 int mlx4_en_try_alloc_resources(struct mlx4_en_priv *priv, 679 struct mlx4_en_priv *tmp, 680 struct mlx4_en_port_profile *prof, 681 bool carry_xdp_prog); 682 void mlx4_en_safe_replace_resources(struct mlx4_en_priv *priv, 683 struct mlx4_en_priv *tmp); 684 685 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq, 686 int entries, int ring, enum cq_type mode, int node); 687 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq); 688 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq, 689 int cq_idx); 690 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 691 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 692 void mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 693 694 void mlx4_en_tx_irq(struct mlx4_cq *mcq); 695 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb, 696 void *accel_priv, select_queue_fallback_t fallback); 697 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev); 698 netdev_tx_t mlx4_en_xmit_frame(struct mlx4_en_rx_ring *rx_ring, 699 struct mlx4_en_rx_alloc *frame, 700 struct mlx4_en_priv *priv, unsigned int length, 701 int tx_ind, bool *doorbell_pending); 702 void mlx4_en_xmit_doorbell(struct mlx4_en_tx_ring *ring); 703 bool mlx4_en_rx_recycle(struct mlx4_en_rx_ring *ring, 704 struct mlx4_en_rx_alloc *frame); 705 706 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, 707 struct mlx4_en_tx_ring **pring, 708 u32 size, u16 stride, 709 int node, int queue_index); 710 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, 711 struct mlx4_en_tx_ring **pring); 712 void mlx4_en_init_tx_xdp_ring_descs(struct mlx4_en_priv *priv, 713 struct mlx4_en_tx_ring *ring); 714 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, 715 struct mlx4_en_tx_ring *ring, 716 int cq, int user_prio); 717 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, 718 struct mlx4_en_tx_ring *ring); 719 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev); 720 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv); 721 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, 722 struct mlx4_en_rx_ring **pring, 723 u32 size, u16 stride, int node); 724 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, 725 struct mlx4_en_rx_ring **pring, 726 u32 size, u16 stride); 727 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv); 728 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, 729 struct mlx4_en_rx_ring *ring); 730 int mlx4_en_process_rx_cq(struct net_device *dev, 731 struct mlx4_en_cq *cq, 732 int budget); 733 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget); 734 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget); 735 bool mlx4_en_process_tx_cq(struct net_device *dev, 736 struct mlx4_en_cq *cq, int napi_budget); 737 u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv, 738 struct mlx4_en_tx_ring *ring, 739 int index, u64 timestamp, 740 int napi_mode); 741 u32 mlx4_en_recycle_tx_desc(struct mlx4_en_priv *priv, 742 struct mlx4_en_tx_ring *ring, 743 int index, u64 timestamp, 744 int napi_mode); 745 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride, 746 int is_tx, int rss, int qpn, int cqn, int user_prio, 747 struct mlx4_qp_context *context); 748 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event); 749 int mlx4_en_change_mcast_lb(struct mlx4_en_priv *priv, struct mlx4_qp *qp, 750 int loopback); 751 void mlx4_en_calc_rx_buf(struct net_device *dev); 752 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv); 753 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv); 754 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv); 755 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv); 756 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring); 757 void mlx4_en_rx_irq(struct mlx4_cq *mcq); 758 759 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); 760 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv); 761 762 void mlx4_en_fold_software_stats(struct net_device *dev); 763 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset); 764 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port); 765 766 #ifdef CONFIG_MLX4_EN_DCB 767 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops; 768 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops; 769 #endif 770 771 int mlx4_en_setup_tc(struct net_device *dev, u8 up); 772 int mlx4_en_alloc_tx_queue_per_tc(struct net_device *dev, u8 tc); 773 774 #ifdef CONFIG_RFS_ACCEL 775 void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv); 776 #endif 777 778 #define MLX4_EN_NUM_SELF_TEST 5 779 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf); 780 void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev); 781 782 #define DEV_FEATURE_CHANGED(dev, new_features, feature) \ 783 ((dev->features & feature) ^ (new_features & feature)) 784 785 int mlx4_en_reset_config(struct net_device *dev, 786 struct hwtstamp_config ts_config, 787 netdev_features_t new_features); 788 void mlx4_en_update_pfc_stats_bitmap(struct mlx4_dev *dev, 789 struct mlx4_en_stats_bitmap *stats_bitmap, 790 u8 rx_ppp, u8 rx_pause, 791 u8 tx_ppp, u8 tx_pause); 792 int mlx4_en_netdev_event(struct notifier_block *this, 793 unsigned long event, void *ptr); 794 795 /* 796 * Functions for time stamping 797 */ 798 u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe); 799 void mlx4_en_fill_hwtstamps(struct mlx4_en_dev *mdev, 800 struct skb_shared_hwtstamps *hwts, 801 u64 timestamp); 802 void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev); 803 void mlx4_en_remove_timestamp(struct mlx4_en_dev *mdev); 804 805 /* Globals 806 */ 807 extern const struct ethtool_ops mlx4_en_ethtool_ops; 808 809 810 811 /* 812 * printk / logging functions 813 */ 814 815 __printf(3, 4) 816 void en_print(const char *level, const struct mlx4_en_priv *priv, 817 const char *format, ...); 818 819 #define en_dbg(mlevel, priv, format, ...) \ 820 do { \ 821 if (NETIF_MSG_##mlevel & (priv)->msg_enable) \ 822 en_print(KERN_DEBUG, priv, format, ##__VA_ARGS__); \ 823 } while (0) 824 #define en_warn(priv, format, ...) \ 825 en_print(KERN_WARNING, priv, format, ##__VA_ARGS__) 826 #define en_err(priv, format, ...) \ 827 en_print(KERN_ERR, priv, format, ##__VA_ARGS__) 828 #define en_info(priv, format, ...) \ 829 en_print(KERN_INFO, priv, format, ##__VA_ARGS__) 830 831 #define mlx4_err(mdev, format, ...) \ 832 pr_err(DRV_NAME " %s: " format, \ 833 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__) 834 #define mlx4_info(mdev, format, ...) \ 835 pr_info(DRV_NAME " %s: " format, \ 836 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__) 837 #define mlx4_warn(mdev, format, ...) \ 838 pr_warn(DRV_NAME " %s: " format, \ 839 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__) 840 841 #endif 842