1 /* 2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34 #ifndef _MLX4_EN_H_ 35 #define _MLX4_EN_H_ 36 37 #include <linux/bitops.h> 38 #include <linux/compiler.h> 39 #include <linux/list.h> 40 #include <linux/mutex.h> 41 #include <linux/netdevice.h> 42 #include <linux/if_vlan.h> 43 #include <linux/net_tstamp.h> 44 #ifdef CONFIG_MLX4_EN_DCB 45 #include <linux/dcbnl.h> 46 #endif 47 #include <linux/cpu_rmap.h> 48 #include <linux/ptp_clock_kernel.h> 49 50 #include <linux/mlx4/device.h> 51 #include <linux/mlx4/qp.h> 52 #include <linux/mlx4/cq.h> 53 #include <linux/mlx4/srq.h> 54 #include <linux/mlx4/doorbell.h> 55 #include <linux/mlx4/cmd.h> 56 57 #include "en_port.h" 58 #include "mlx4_stats.h" 59 60 #define DRV_NAME "mlx4_en" 61 #define DRV_VERSION "2.2-1" 62 #define DRV_RELDATE "Feb 2014" 63 64 #define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN) 65 66 /* 67 * Device constants 68 */ 69 70 71 #define MLX4_EN_PAGE_SHIFT 12 72 #define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT) 73 #define DEF_RX_RINGS 16 74 #define MAX_RX_RINGS 128 75 #define MIN_RX_RINGS 4 76 #define TXBB_SIZE 64 77 #define HEADROOM (2048 / TXBB_SIZE + 1) 78 #define STAMP_STRIDE 64 79 #define STAMP_DWORDS (STAMP_STRIDE / 4) 80 #define STAMP_SHIFT 31 81 #define STAMP_VAL 0x7fffffff 82 #define STATS_DELAY (HZ / 4) 83 #define SERVICE_TASK_DELAY (HZ / 4) 84 #define MAX_NUM_OF_FS_RULES 256 85 86 #define MLX4_EN_FILTER_HASH_SHIFT 4 87 #define MLX4_EN_FILTER_EXPIRY_QUOTA 60 88 89 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */ 90 #define MAX_DESC_SIZE 512 91 #define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE) 92 93 /* 94 * OS related constants and tunables 95 */ 96 97 #define MLX4_EN_PRIV_FLAGS_BLUEFLAME 1 98 #define MLX4_EN_PRIV_FLAGS_PHV 2 99 100 #define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ) 101 102 /* Use the maximum between 16384 and a single page */ 103 #define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(16384) 104 105 #define MLX4_EN_ALLOC_PREFER_ORDER PAGE_ALLOC_COSTLY_ORDER 106 107 /* Receive fragment sizes; we use at most 3 fragments (for 9600 byte MTU 108 * and 4K allocations) */ 109 enum { 110 FRAG_SZ0 = 1536 - NET_IP_ALIGN, 111 FRAG_SZ1 = 4096, 112 FRAG_SZ2 = 4096, 113 FRAG_SZ3 = MLX4_EN_ALLOC_SIZE 114 }; 115 #define MLX4_EN_MAX_RX_FRAGS 4 116 117 /* Maximum ring sizes */ 118 #define MLX4_EN_MAX_TX_SIZE 8192 119 #define MLX4_EN_MAX_RX_SIZE 8192 120 121 /* Minimum ring size for our page-allocation scheme to work */ 122 #define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES) 123 #define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE) 124 125 #define MLX4_EN_SMALL_PKT_SIZE 64 126 #define MLX4_EN_MIN_TX_RING_P_UP 1 127 #define MLX4_EN_MAX_TX_RING_P_UP 32 128 #define MLX4_EN_NUM_UP 8 129 #define MLX4_EN_DEF_TX_RING_SIZE 512 130 #define MLX4_EN_DEF_RX_RING_SIZE 1024 131 #define MAX_TX_RINGS (MLX4_EN_MAX_TX_RING_P_UP * \ 132 MLX4_EN_NUM_UP) 133 134 #define MLX4_EN_DEFAULT_TX_WORK 256 135 136 /* Target number of packets to coalesce with interrupt moderation */ 137 #define MLX4_EN_RX_COAL_TARGET 44 138 #define MLX4_EN_RX_COAL_TIME 0x10 139 140 #define MLX4_EN_TX_COAL_PKTS 16 141 #define MLX4_EN_TX_COAL_TIME 0x10 142 143 #define MLX4_EN_RX_RATE_LOW 400000 144 #define MLX4_EN_RX_COAL_TIME_LOW 0 145 #define MLX4_EN_RX_RATE_HIGH 450000 146 #define MLX4_EN_RX_COAL_TIME_HIGH 128 147 #define MLX4_EN_RX_SIZE_THRESH 1024 148 #define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH) 149 #define MLX4_EN_SAMPLE_INTERVAL 0 150 #define MLX4_EN_AVG_PKT_SMALL 256 151 152 #define MLX4_EN_AUTO_CONF 0xffff 153 154 #define MLX4_EN_DEF_RX_PAUSE 1 155 #define MLX4_EN_DEF_TX_PAUSE 1 156 157 /* Interval between successive polls in the Tx routine when polling is used 158 instead of interrupts (in per-core Tx rings) - should be power of 2 */ 159 #define MLX4_EN_TX_POLL_MODER 16 160 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4) 161 162 #define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN) 163 #define HEADER_COPY_SIZE (128 - NET_IP_ALIGN) 164 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN) 165 166 #define MLX4_EN_MIN_MTU 46 167 #define ETH_BCAST 0xffffffffffffULL 168 169 #define MLX4_EN_LOOPBACK_RETRIES 5 170 #define MLX4_EN_LOOPBACK_TIMEOUT 100 171 172 #ifdef MLX4_EN_PERF_STAT 173 /* Number of samples to 'average' */ 174 #define AVG_SIZE 128 175 #define AVG_FACTOR 1024 176 177 #define INC_PERF_COUNTER(cnt) (++(cnt)) 178 #define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add)) 179 #define AVG_PERF_COUNTER(cnt, sample) \ 180 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE) 181 #define GET_PERF_COUNTER(cnt) (cnt) 182 #define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR) 183 184 #else 185 186 #define INC_PERF_COUNTER(cnt) do {} while (0) 187 #define ADD_PERF_COUNTER(cnt, add) do {} while (0) 188 #define AVG_PERF_COUNTER(cnt, sample) do {} while (0) 189 #define GET_PERF_COUNTER(cnt) (0) 190 #define GET_AVG_PERF_COUNTER(cnt) (0) 191 #endif /* MLX4_EN_PERF_STAT */ 192 193 /* Constants for TX flow */ 194 enum { 195 MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */ 196 MAX_BF = 256, 197 MIN_PKT_LEN = 17, 198 }; 199 200 /* 201 * Configurables 202 */ 203 204 enum cq_type { 205 RX = 0, 206 TX = 1, 207 }; 208 209 210 /* 211 * Useful macros 212 */ 213 #define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x)) 214 #define XNOR(x, y) (!(x) == !(y)) 215 216 217 struct mlx4_en_tx_info { 218 struct sk_buff *skb; 219 dma_addr_t map0_dma; 220 u32 map0_byte_count; 221 u32 nr_txbb; 222 u32 nr_bytes; 223 u8 linear; 224 u8 data_offset; 225 u8 inl; 226 u8 ts_requested; 227 u8 nr_maps; 228 } ____cacheline_aligned_in_smp; 229 230 231 #define MLX4_EN_BIT_DESC_OWN 0x80000000 232 #define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg) 233 #define MLX4_EN_MEMTYPE_PAD 0x100 234 #define DS_SIZE sizeof(struct mlx4_wqe_data_seg) 235 236 237 struct mlx4_en_tx_desc { 238 struct mlx4_wqe_ctrl_seg ctrl; 239 union { 240 struct mlx4_wqe_data_seg data; /* at least one data segment */ 241 struct mlx4_wqe_lso_seg lso; 242 struct mlx4_wqe_inline_seg inl; 243 }; 244 }; 245 246 #define MLX4_EN_USE_SRQ 0x01000000 247 248 #define MLX4_EN_CX3_LOW_ID 0x1000 249 #define MLX4_EN_CX3_HIGH_ID 0x1005 250 251 struct mlx4_en_rx_alloc { 252 struct page *page; 253 dma_addr_t dma; 254 u32 page_offset; 255 u32 page_size; 256 }; 257 258 struct mlx4_en_tx_ring { 259 /* cache line used and dirtied in tx completion 260 * (mlx4_en_free_tx_buf()) 261 */ 262 u32 last_nr_txbb; 263 u32 cons; 264 unsigned long wake_queue; 265 266 /* cache line used and dirtied in mlx4_en_xmit() */ 267 u32 prod ____cacheline_aligned_in_smp; 268 unsigned long bytes; 269 unsigned long packets; 270 unsigned long tx_csum; 271 unsigned long tso_packets; 272 unsigned long xmit_more; 273 struct mlx4_bf bf; 274 unsigned long queue_stopped; 275 276 /* Following part should be mostly read */ 277 cpumask_t affinity_mask; 278 struct mlx4_qp qp; 279 struct mlx4_hwq_resources wqres; 280 u32 size; /* number of TXBBs */ 281 u32 size_mask; 282 u16 stride; 283 u32 full_size; 284 u16 cqn; /* index of port CQ associated with this ring */ 285 u32 buf_size; 286 __be32 doorbell_qpn; 287 __be32 mr_key; 288 void *buf; 289 struct mlx4_en_tx_info *tx_info; 290 u8 *bounce_buf; 291 struct mlx4_qp_context context; 292 int qpn; 293 enum mlx4_qp_state qp_state; 294 u8 queue_index; 295 bool bf_enabled; 296 bool bf_alloced; 297 struct netdev_queue *tx_queue; 298 int hwtstamp_tx_type; 299 } ____cacheline_aligned_in_smp; 300 301 struct mlx4_en_rx_desc { 302 /* actual number of entries depends on rx ring stride */ 303 struct mlx4_wqe_data_seg data[0]; 304 }; 305 306 struct mlx4_en_rx_ring { 307 struct mlx4_hwq_resources wqres; 308 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS]; 309 u32 size ; /* number of Rx descs*/ 310 u32 actual_size; 311 u32 size_mask; 312 u16 stride; 313 u16 log_stride; 314 u16 cqn; /* index of port CQ associated with this ring */ 315 u32 prod; 316 u32 cons; 317 u32 buf_size; 318 u8 fcs_del; 319 void *buf; 320 void *rx_info; 321 unsigned long bytes; 322 unsigned long packets; 323 unsigned long csum_ok; 324 unsigned long csum_none; 325 unsigned long csum_complete; 326 int hwtstamp_rx_filter; 327 cpumask_var_t affinity_mask; 328 }; 329 330 struct mlx4_en_cq { 331 struct mlx4_cq mcq; 332 struct mlx4_hwq_resources wqres; 333 int ring; 334 struct net_device *dev; 335 struct napi_struct napi; 336 int size; 337 int buf_size; 338 int vector; 339 enum cq_type is_tx; 340 u16 moder_time; 341 u16 moder_cnt; 342 struct mlx4_cqe *buf; 343 #define MLX4_EN_OPCODE_ERROR 0x1e 344 345 struct irq_desc *irq_desc; 346 }; 347 348 struct mlx4_en_port_profile { 349 u32 flags; 350 u32 tx_ring_num; 351 u32 rx_ring_num; 352 u32 tx_ring_size; 353 u32 rx_ring_size; 354 u8 rx_pause; 355 u8 rx_ppp; 356 u8 tx_pause; 357 u8 tx_ppp; 358 int rss_rings; 359 int inline_thold; 360 }; 361 362 struct mlx4_en_profile { 363 int udp_rss; 364 u8 rss_mask; 365 u32 active_ports; 366 u32 small_pkt_int; 367 u8 no_reset; 368 u8 num_tx_rings_p_up; 369 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1]; 370 }; 371 372 struct mlx4_en_dev { 373 struct mlx4_dev *dev; 374 struct pci_dev *pdev; 375 struct mutex state_lock; 376 struct net_device *pndev[MLX4_MAX_PORTS + 1]; 377 struct net_device *upper[MLX4_MAX_PORTS + 1]; 378 u32 port_cnt; 379 bool device_up; 380 struct mlx4_en_profile profile; 381 u32 LSO_support; 382 struct workqueue_struct *workqueue; 383 struct device *dma_device; 384 void __iomem *uar_map; 385 struct mlx4_uar priv_uar; 386 struct mlx4_mr mr; 387 u32 priv_pdn; 388 spinlock_t uar_lock; 389 u8 mac_removed[MLX4_MAX_PORTS + 1]; 390 rwlock_t clock_lock; 391 u32 nominal_c_mult; 392 struct cyclecounter cycles; 393 struct timecounter clock; 394 unsigned long last_overflow_check; 395 unsigned long overflow_period; 396 struct ptp_clock *ptp_clock; 397 struct ptp_clock_info ptp_clock_info; 398 struct notifier_block nb; 399 }; 400 401 402 struct mlx4_en_rss_map { 403 int base_qpn; 404 struct mlx4_qp qps[MAX_RX_RINGS]; 405 enum mlx4_qp_state state[MAX_RX_RINGS]; 406 struct mlx4_qp indir_qp; 407 enum mlx4_qp_state indir_state; 408 }; 409 410 enum mlx4_en_port_flag { 411 MLX4_EN_PORT_ANC = 1<<0, /* Auto-negotiation complete */ 412 MLX4_EN_PORT_ANE = 1<<1, /* Auto-negotiation enabled */ 413 }; 414 415 struct mlx4_en_port_state { 416 int link_state; 417 int link_speed; 418 int transceiver; 419 u32 flags; 420 }; 421 422 enum mlx4_en_mclist_act { 423 MCLIST_NONE, 424 MCLIST_REM, 425 MCLIST_ADD, 426 }; 427 428 struct mlx4_en_mc_list { 429 struct list_head list; 430 enum mlx4_en_mclist_act action; 431 u8 addr[ETH_ALEN]; 432 u64 reg_id; 433 u64 tunnel_reg_id; 434 }; 435 436 struct mlx4_en_frag_info { 437 u16 frag_size; 438 u16 frag_prefix_size; 439 u16 frag_stride; 440 }; 441 442 #ifdef CONFIG_MLX4_EN_DCB 443 /* Minimal TC BW - setting to 0 will block traffic */ 444 #define MLX4_EN_BW_MIN 1 445 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */ 446 447 #define MLX4_EN_TC_ETS 7 448 449 #endif 450 451 struct ethtool_flow_id { 452 struct list_head list; 453 struct ethtool_rx_flow_spec flow_spec; 454 u64 id; 455 }; 456 457 enum { 458 MLX4_EN_FLAG_PROMISC = (1 << 0), 459 MLX4_EN_FLAG_MC_PROMISC = (1 << 1), 460 /* whether we need to enable hardware loopback by putting dmac 461 * in Tx WQE 462 */ 463 MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2), 464 /* whether we need to drop packets that hardware loopback-ed */ 465 MLX4_EN_FLAG_RX_FILTER_NEEDED = (1 << 3), 466 MLX4_EN_FLAG_FORCE_PROMISC = (1 << 4), 467 MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP = (1 << 5), 468 }; 469 470 #define PORT_BEACON_MAX_LIMIT (65535) 471 #define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE) 472 #define MLX4_EN_MAC_HASH_IDX 5 473 474 struct mlx4_en_stats_bitmap { 475 DECLARE_BITMAP(bitmap, NUM_ALL_STATS); 476 struct mutex mutex; /* for mutual access to stats bitmap */ 477 }; 478 479 struct mlx4_en_priv { 480 struct mlx4_en_dev *mdev; 481 struct mlx4_en_port_profile *prof; 482 struct net_device *dev; 483 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 484 struct net_device_stats stats; 485 struct net_device_stats ret_stats; 486 struct mlx4_en_port_state port_state; 487 spinlock_t stats_lock; 488 struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES]; 489 /* To allow rules removal while port is going down */ 490 struct list_head ethtool_list; 491 492 unsigned long last_moder_packets[MAX_RX_RINGS]; 493 unsigned long last_moder_tx_packets; 494 unsigned long last_moder_bytes[MAX_RX_RINGS]; 495 unsigned long last_moder_jiffies; 496 int last_moder_time[MAX_RX_RINGS]; 497 u16 rx_usecs; 498 u16 rx_frames; 499 u16 tx_usecs; 500 u16 tx_frames; 501 u32 pkt_rate_low; 502 u16 rx_usecs_low; 503 u32 pkt_rate_high; 504 u16 rx_usecs_high; 505 u16 sample_interval; 506 u16 adaptive_rx_coal; 507 u32 msg_enable; 508 u32 loopback_ok; 509 u32 validate_loopback; 510 511 struct mlx4_hwq_resources res; 512 int link_state; 513 int last_link_state; 514 bool port_up; 515 int port; 516 int registered; 517 int allocated; 518 int stride; 519 unsigned char current_mac[ETH_ALEN + 2]; 520 int mac_index; 521 unsigned max_mtu; 522 int base_qpn; 523 int cqe_factor; 524 int cqe_size; 525 526 struct mlx4_en_rss_map rss_map; 527 __be32 ctrl_flags; 528 u32 flags; 529 u8 num_tx_rings_p_up; 530 u32 tx_work_limit; 531 u32 tx_ring_num; 532 u32 rx_ring_num; 533 u32 rx_skb_size; 534 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS]; 535 u16 num_frags; 536 u16 log_rx_info; 537 538 struct mlx4_en_tx_ring **tx_ring; 539 struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS]; 540 struct mlx4_en_cq **tx_cq; 541 struct mlx4_en_cq *rx_cq[MAX_RX_RINGS]; 542 struct mlx4_qp drop_qp; 543 struct work_struct rx_mode_task; 544 struct work_struct watchdog_task; 545 struct work_struct linkstate_task; 546 struct delayed_work stats_task; 547 struct delayed_work service_task; 548 #ifdef CONFIG_MLX4_EN_VXLAN 549 struct work_struct vxlan_add_task; 550 struct work_struct vxlan_del_task; 551 #endif 552 struct mlx4_en_perf_stats pstats; 553 struct mlx4_en_pkt_stats pkstats; 554 struct mlx4_en_counter_stats pf_stats; 555 struct mlx4_en_flow_stats_rx rx_priority_flowstats[MLX4_NUM_PRIORITIES]; 556 struct mlx4_en_flow_stats_tx tx_priority_flowstats[MLX4_NUM_PRIORITIES]; 557 struct mlx4_en_flow_stats_rx rx_flowstats; 558 struct mlx4_en_flow_stats_tx tx_flowstats; 559 struct mlx4_en_port_stats port_stats; 560 struct mlx4_en_stats_bitmap stats_bitmap; 561 struct list_head mc_list; 562 struct list_head curr_list; 563 u64 broadcast_id; 564 struct mlx4_en_stat_out_mbox hw_stats; 565 int vids[128]; 566 bool wol; 567 struct device *ddev; 568 struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE]; 569 struct hwtstamp_config hwtstamp_config; 570 u32 counter_index; 571 572 #ifdef CONFIG_MLX4_EN_DCB 573 struct ieee_ets ets; 574 u16 maxrate[IEEE_8021QAZ_MAX_TCS]; 575 enum dcbnl_cndd_states cndd_state[IEEE_8021QAZ_MAX_TCS]; 576 #endif 577 #ifdef CONFIG_RFS_ACCEL 578 spinlock_t filters_lock; 579 int last_filter_id; 580 struct list_head filters; 581 struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT]; 582 #endif 583 u64 tunnel_reg_id; 584 __be16 vxlan_port; 585 586 u32 pflags; 587 u8 rss_key[MLX4_EN_RSS_KEY_SIZE]; 588 u8 rss_hash_fn; 589 }; 590 591 enum mlx4_en_wol { 592 MLX4_EN_WOL_MAGIC = (1ULL << 61), 593 MLX4_EN_WOL_ENABLED = (1ULL << 62), 594 }; 595 596 struct mlx4_mac_entry { 597 struct hlist_node hlist; 598 unsigned char mac[ETH_ALEN + 2]; 599 u64 reg_id; 600 struct rcu_head rcu; 601 }; 602 603 static inline struct mlx4_cqe *mlx4_en_get_cqe(void *buf, int idx, int cqe_sz) 604 { 605 return buf + idx * cqe_sz; 606 } 607 608 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63) 609 610 void mlx4_en_init_ptys2ethtool_map(void); 611 void mlx4_en_update_loopback_state(struct net_device *dev, 612 netdev_features_t features); 613 614 void mlx4_en_destroy_netdev(struct net_device *dev); 615 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port, 616 struct mlx4_en_port_profile *prof); 617 618 int mlx4_en_start_port(struct net_device *dev); 619 void mlx4_en_stop_port(struct net_device *dev, int detach); 620 621 void mlx4_en_set_stats_bitmap(struct mlx4_dev *dev, 622 struct mlx4_en_stats_bitmap *stats_bitmap, 623 u8 rx_ppp, u8 rx_pause, 624 u8 tx_ppp, u8 tx_pause); 625 626 void mlx4_en_free_resources(struct mlx4_en_priv *priv); 627 int mlx4_en_alloc_resources(struct mlx4_en_priv *priv); 628 629 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq, 630 int entries, int ring, enum cq_type mode, int node); 631 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq); 632 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq, 633 int cq_idx); 634 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 635 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 636 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 637 638 void mlx4_en_tx_irq(struct mlx4_cq *mcq); 639 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb, 640 void *accel_priv, select_queue_fallback_t fallback); 641 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev); 642 643 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, 644 struct mlx4_en_tx_ring **pring, 645 u32 size, u16 stride, 646 int node, int queue_index); 647 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, 648 struct mlx4_en_tx_ring **pring); 649 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, 650 struct mlx4_en_tx_ring *ring, 651 int cq, int user_prio); 652 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, 653 struct mlx4_en_tx_ring *ring); 654 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev); 655 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv); 656 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, 657 struct mlx4_en_rx_ring **pring, 658 u32 size, u16 stride, int node); 659 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, 660 struct mlx4_en_rx_ring **pring, 661 u32 size, u16 stride); 662 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv); 663 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, 664 struct mlx4_en_rx_ring *ring); 665 int mlx4_en_process_rx_cq(struct net_device *dev, 666 struct mlx4_en_cq *cq, 667 int budget); 668 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget); 669 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget); 670 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride, 671 int is_tx, int rss, int qpn, int cqn, int user_prio, 672 struct mlx4_qp_context *context); 673 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event); 674 int mlx4_en_map_buffer(struct mlx4_buf *buf); 675 void mlx4_en_unmap_buffer(struct mlx4_buf *buf); 676 int mlx4_en_change_mcast_lb(struct mlx4_en_priv *priv, struct mlx4_qp *qp, 677 int loopback); 678 void mlx4_en_calc_rx_buf(struct net_device *dev); 679 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv); 680 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv); 681 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv); 682 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv); 683 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring); 684 void mlx4_en_rx_irq(struct mlx4_cq *mcq); 685 686 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); 687 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv); 688 689 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset); 690 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port); 691 692 #ifdef CONFIG_MLX4_EN_DCB 693 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops; 694 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops; 695 #endif 696 697 int mlx4_en_setup_tc(struct net_device *dev, u8 up); 698 699 #ifdef CONFIG_RFS_ACCEL 700 void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv); 701 #endif 702 703 #define MLX4_EN_NUM_SELF_TEST 5 704 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf); 705 void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev); 706 707 #define DEV_FEATURE_CHANGED(dev, new_features, feature) \ 708 ((dev->features & feature) ^ (new_features & feature)) 709 710 int mlx4_en_reset_config(struct net_device *dev, 711 struct hwtstamp_config ts_config, 712 netdev_features_t new_features); 713 void mlx4_en_update_pfc_stats_bitmap(struct mlx4_dev *dev, 714 struct mlx4_en_stats_bitmap *stats_bitmap, 715 u8 rx_ppp, u8 rx_pause, 716 u8 tx_ppp, u8 tx_pause); 717 int mlx4_en_netdev_event(struct notifier_block *this, 718 unsigned long event, void *ptr); 719 720 /* 721 * Functions for time stamping 722 */ 723 u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe); 724 void mlx4_en_fill_hwtstamps(struct mlx4_en_dev *mdev, 725 struct skb_shared_hwtstamps *hwts, 726 u64 timestamp); 727 void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev); 728 void mlx4_en_remove_timestamp(struct mlx4_en_dev *mdev); 729 730 /* Globals 731 */ 732 extern const struct ethtool_ops mlx4_en_ethtool_ops; 733 734 735 736 /* 737 * printk / logging functions 738 */ 739 740 __printf(3, 4) 741 void en_print(const char *level, const struct mlx4_en_priv *priv, 742 const char *format, ...); 743 744 #define en_dbg(mlevel, priv, format, ...) \ 745 do { \ 746 if (NETIF_MSG_##mlevel & (priv)->msg_enable) \ 747 en_print(KERN_DEBUG, priv, format, ##__VA_ARGS__); \ 748 } while (0) 749 #define en_warn(priv, format, ...) \ 750 en_print(KERN_WARNING, priv, format, ##__VA_ARGS__) 751 #define en_err(priv, format, ...) \ 752 en_print(KERN_ERR, priv, format, ##__VA_ARGS__) 753 #define en_info(priv, format, ...) \ 754 en_print(KERN_INFO, priv, format, ##__VA_ARGS__) 755 756 #define mlx4_err(mdev, format, ...) \ 757 pr_err(DRV_NAME " %s: " format, \ 758 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__) 759 #define mlx4_info(mdev, format, ...) \ 760 pr_info(DRV_NAME " %s: " format, \ 761 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__) 762 #define mlx4_warn(mdev, format, ...) \ 763 pr_warn(DRV_NAME " %s: " format, \ 764 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__) 765 766 #endif 767