1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved. 5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved. 7 * 8 * This software is available to you under a choice of one of two 9 * licenses. You may choose to be licensed under the terms of the GNU 10 * General Public License (GPL) Version 2, available from the file 11 * COPYING in the main directory of this source tree, or the 12 * OpenIB.org BSD license below: 13 * 14 * Redistribution and use in source and binary forms, with or 15 * without modification, are permitted provided that the following 16 * conditions are met: 17 * 18 * - Redistributions of source code must retain the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer. 21 * 22 * - Redistributions in binary form must reproduce the above 23 * copyright notice, this list of conditions and the following 24 * disclaimer in the documentation and/or other materials 25 * provided with the distribution. 26 * 27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 34 * SOFTWARE. 35 */ 36 37 #ifndef MLX4_H 38 #define MLX4_H 39 40 #include <linux/mutex.h> 41 #include <linux/radix-tree.h> 42 #include <linux/rbtree.h> 43 #include <linux/timer.h> 44 #include <linux/semaphore.h> 45 #include <linux/workqueue.h> 46 47 #include <linux/mlx4/device.h> 48 #include <linux/mlx4/driver.h> 49 #include <linux/mlx4/doorbell.h> 50 #include <linux/mlx4/cmd.h> 51 52 #define DRV_NAME "mlx4_core" 53 #define PFX DRV_NAME ": " 54 #define DRV_VERSION "1.1" 55 #define DRV_RELDATE "Dec, 2011" 56 57 #define MLX4_FS_UDP_UC_EN (1 << 1) 58 #define MLX4_FS_TCP_UC_EN (1 << 2) 59 #define MLX4_FS_NUM_OF_L2_ADDR 8 60 #define MLX4_FS_MGM_LOG_ENTRY_SIZE 7 61 #define MLX4_FS_NUM_MCG (1 << 17) 62 63 enum { 64 MLX4_FS_L2_HASH = 0, 65 MLX4_FS_L2_L3_L4_HASH, 66 }; 67 68 #define MLX4_NUM_UP 8 69 #define MLX4_NUM_TC 8 70 #define MLX4_RATELIMIT_UNITS 3 /* 100 Mbps */ 71 #define MLX4_RATELIMIT_DEFAULT 0xffff 72 73 struct mlx4_set_port_prio2tc_context { 74 u8 prio2tc[4]; 75 }; 76 77 struct mlx4_port_scheduler_tc_cfg_be { 78 __be16 pg; 79 __be16 bw_precentage; 80 __be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */ 81 __be16 max_bw_value; 82 }; 83 84 struct mlx4_set_port_scheduler_context { 85 struct mlx4_port_scheduler_tc_cfg_be tc[MLX4_NUM_TC]; 86 }; 87 88 enum { 89 MLX4_HCR_BASE = 0x80680, 90 MLX4_HCR_SIZE = 0x0001c, 91 MLX4_CLR_INT_SIZE = 0x00008, 92 MLX4_SLAVE_COMM_BASE = 0x0, 93 MLX4_COMM_PAGESIZE = 0x1000 94 }; 95 96 enum { 97 MLX4_MAX_MGM_ENTRY_SIZE = 0x1000, 98 MLX4_MAX_QP_PER_MGM = 4 * (MLX4_MAX_MGM_ENTRY_SIZE / 16 - 2), 99 MLX4_MTT_ENTRY_PER_SEG = 8, 100 }; 101 102 enum { 103 MLX4_NUM_PDS = 1 << 15 104 }; 105 106 enum { 107 MLX4_CMPT_TYPE_QP = 0, 108 MLX4_CMPT_TYPE_SRQ = 1, 109 MLX4_CMPT_TYPE_CQ = 2, 110 MLX4_CMPT_TYPE_EQ = 3, 111 MLX4_CMPT_NUM_TYPE 112 }; 113 114 enum { 115 MLX4_CMPT_SHIFT = 24, 116 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT 117 }; 118 119 enum mlx4_mr_state { 120 MLX4_MR_DISABLED = 0, 121 MLX4_MR_EN_HW, 122 MLX4_MR_EN_SW 123 }; 124 125 #define MLX4_COMM_TIME 10000 126 enum { 127 MLX4_COMM_CMD_RESET, 128 MLX4_COMM_CMD_VHCR0, 129 MLX4_COMM_CMD_VHCR1, 130 MLX4_COMM_CMD_VHCR2, 131 MLX4_COMM_CMD_VHCR_EN, 132 MLX4_COMM_CMD_VHCR_POST, 133 MLX4_COMM_CMD_FLR = 254 134 }; 135 136 /*The flag indicates that the slave should delay the RESET cmd*/ 137 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb 138 /*indicates how many retries will be done if we are in the middle of FLR*/ 139 #define NUM_OF_RESET_RETRIES 10 140 #define SLEEP_TIME_IN_RESET (2 * 1000) 141 enum mlx4_resource { 142 RES_QP, 143 RES_CQ, 144 RES_SRQ, 145 RES_XRCD, 146 RES_MPT, 147 RES_MTT, 148 RES_MAC, 149 RES_VLAN, 150 RES_EQ, 151 RES_COUNTER, 152 RES_FS_RULE, 153 MLX4_NUM_OF_RESOURCE_TYPE 154 }; 155 156 enum mlx4_alloc_mode { 157 RES_OP_RESERVE, 158 RES_OP_RESERVE_AND_MAP, 159 RES_OP_MAP_ICM, 160 }; 161 162 enum mlx4_res_tracker_free_type { 163 RES_TR_FREE_ALL, 164 RES_TR_FREE_SLAVES_ONLY, 165 RES_TR_FREE_STRUCTS_ONLY, 166 }; 167 168 /* 169 *Virtual HCR structures. 170 * mlx4_vhcr is the sw representation, in machine endianess 171 * 172 * mlx4_vhcr_cmd is the formalized structure, the one that is passed 173 * to FW to go through communication channel. 174 * It is big endian, and has the same structure as the physical HCR 175 * used by command interface 176 */ 177 struct mlx4_vhcr { 178 u64 in_param; 179 u64 out_param; 180 u32 in_modifier; 181 u32 errno; 182 u16 op; 183 u16 token; 184 u8 op_modifier; 185 u8 e_bit; 186 }; 187 188 struct mlx4_vhcr_cmd { 189 __be64 in_param; 190 __be32 in_modifier; 191 __be64 out_param; 192 __be16 token; 193 u16 reserved; 194 u8 status; 195 u8 flags; 196 __be16 opcode; 197 }; 198 199 struct mlx4_cmd_info { 200 u16 opcode; 201 bool has_inbox; 202 bool has_outbox; 203 bool out_is_imm; 204 bool encode_slave_id; 205 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr, 206 struct mlx4_cmd_mailbox *inbox); 207 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr, 208 struct mlx4_cmd_mailbox *inbox, 209 struct mlx4_cmd_mailbox *outbox, 210 struct mlx4_cmd_info *cmd); 211 }; 212 213 #ifdef CONFIG_MLX4_DEBUG 214 extern int mlx4_debug_level; 215 #else /* CONFIG_MLX4_DEBUG */ 216 #define mlx4_debug_level (0) 217 #endif /* CONFIG_MLX4_DEBUG */ 218 219 #define mlx4_dbg(mdev, format, arg...) \ 220 do { \ 221 if (mlx4_debug_level) \ 222 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \ 223 } while (0) 224 225 #define mlx4_err(mdev, format, arg...) \ 226 dev_err(&mdev->pdev->dev, format, ##arg) 227 #define mlx4_info(mdev, format, arg...) \ 228 dev_info(&mdev->pdev->dev, format, ##arg) 229 #define mlx4_warn(mdev, format, arg...) \ 230 dev_warn(&mdev->pdev->dev, format, ##arg) 231 232 extern int mlx4_log_num_mgm_entry_size; 233 extern int log_mtts_per_seg; 234 235 #define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF) 236 #define ALL_SLAVES 0xff 237 238 struct mlx4_bitmap { 239 u32 last; 240 u32 top; 241 u32 max; 242 u32 reserved_top; 243 u32 mask; 244 u32 avail; 245 spinlock_t lock; 246 unsigned long *table; 247 }; 248 249 struct mlx4_buddy { 250 unsigned long **bits; 251 unsigned int *num_free; 252 u32 max_order; 253 spinlock_t lock; 254 }; 255 256 struct mlx4_icm; 257 258 struct mlx4_icm_table { 259 u64 virt; 260 int num_icm; 261 u32 num_obj; 262 int obj_size; 263 int lowmem; 264 int coherent; 265 struct mutex mutex; 266 struct mlx4_icm **icm; 267 }; 268 269 /* 270 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits. 271 */ 272 struct mlx4_mpt_entry { 273 __be32 flags; 274 __be32 qpn; 275 __be32 key; 276 __be32 pd_flags; 277 __be64 start; 278 __be64 length; 279 __be32 lkey; 280 __be32 win_cnt; 281 u8 reserved1[3]; 282 u8 mtt_rep; 283 __be64 mtt_addr; 284 __be32 mtt_sz; 285 __be32 entity_size; 286 __be32 first_byte_offset; 287 } __packed; 288 289 /* 290 * Must be packed because start is 64 bits but only aligned to 32 bits. 291 */ 292 struct mlx4_eq_context { 293 __be32 flags; 294 u16 reserved1[3]; 295 __be16 page_offset; 296 u8 log_eq_size; 297 u8 reserved2[4]; 298 u8 eq_period; 299 u8 reserved3; 300 u8 eq_max_count; 301 u8 reserved4[3]; 302 u8 intr; 303 u8 log_page_size; 304 u8 reserved5[2]; 305 u8 mtt_base_addr_h; 306 __be32 mtt_base_addr_l; 307 u32 reserved6[2]; 308 __be32 consumer_index; 309 __be32 producer_index; 310 u32 reserved7[4]; 311 }; 312 313 struct mlx4_cq_context { 314 __be32 flags; 315 u16 reserved1[3]; 316 __be16 page_offset; 317 __be32 logsize_usrpage; 318 __be16 cq_period; 319 __be16 cq_max_count; 320 u8 reserved2[3]; 321 u8 comp_eqn; 322 u8 log_page_size; 323 u8 reserved3[2]; 324 u8 mtt_base_addr_h; 325 __be32 mtt_base_addr_l; 326 __be32 last_notified_index; 327 __be32 solicit_producer_index; 328 __be32 consumer_index; 329 __be32 producer_index; 330 u32 reserved4[2]; 331 __be64 db_rec_addr; 332 }; 333 334 struct mlx4_srq_context { 335 __be32 state_logsize_srqn; 336 u8 logstride; 337 u8 reserved1; 338 __be16 xrcd; 339 __be32 pg_offset_cqn; 340 u32 reserved2; 341 u8 log_page_size; 342 u8 reserved3[2]; 343 u8 mtt_base_addr_h; 344 __be32 mtt_base_addr_l; 345 __be32 pd; 346 __be16 limit_watermark; 347 __be16 wqe_cnt; 348 u16 reserved4; 349 __be16 wqe_counter; 350 u32 reserved5; 351 __be64 db_rec_addr; 352 }; 353 354 struct mlx4_eq { 355 struct mlx4_dev *dev; 356 void __iomem *doorbell; 357 int eqn; 358 u32 cons_index; 359 u16 irq; 360 u16 have_irq; 361 int nent; 362 struct mlx4_buf_list *page_list; 363 struct mlx4_mtt mtt; 364 }; 365 366 struct mlx4_slave_eqe { 367 u8 type; 368 u8 port; 369 u32 param; 370 }; 371 372 struct mlx4_slave_event_eq_info { 373 int eqn; 374 u16 token; 375 }; 376 377 struct mlx4_profile { 378 int num_qp; 379 int rdmarc_per_qp; 380 int num_srq; 381 int num_cq; 382 int num_mcg; 383 int num_mpt; 384 unsigned num_mtt; 385 }; 386 387 struct mlx4_fw { 388 u64 clr_int_base; 389 u64 catas_offset; 390 u64 comm_base; 391 struct mlx4_icm *fw_icm; 392 struct mlx4_icm *aux_icm; 393 u32 catas_size; 394 u16 fw_pages; 395 u8 clr_int_bar; 396 u8 catas_bar; 397 u8 comm_bar; 398 }; 399 400 struct mlx4_comm { 401 u32 slave_write; 402 u32 slave_read; 403 }; 404 405 enum { 406 MLX4_MCAST_CONFIG = 0, 407 MLX4_MCAST_DISABLE = 1, 408 MLX4_MCAST_ENABLE = 2, 409 }; 410 411 #define VLAN_FLTR_SIZE 128 412 413 struct mlx4_vlan_fltr { 414 __be32 entry[VLAN_FLTR_SIZE]; 415 }; 416 417 struct mlx4_mcast_entry { 418 struct list_head list; 419 u64 addr; 420 }; 421 422 struct mlx4_promisc_qp { 423 struct list_head list; 424 u32 qpn; 425 }; 426 427 struct mlx4_steer_index { 428 struct list_head list; 429 unsigned int index; 430 struct list_head duplicates; 431 }; 432 433 #define MLX4_EVENT_TYPES_NUM 64 434 435 struct mlx4_slave_state { 436 u8 comm_toggle; 437 u8 last_cmd; 438 u8 init_port_mask; 439 bool active; 440 u8 function; 441 dma_addr_t vhcr_dma; 442 u16 mtu[MLX4_MAX_PORTS + 1]; 443 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1]; 444 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES]; 445 struct list_head mcast_filters[MLX4_MAX_PORTS + 1]; 446 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1]; 447 /* event type to eq number lookup */ 448 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM]; 449 u16 eq_pi; 450 u16 eq_ci; 451 spinlock_t lock; 452 /*initialized via the kzalloc*/ 453 u8 is_slave_going_down; 454 u32 cookie; 455 enum slave_port_state port_state[MLX4_MAX_PORTS + 1]; 456 }; 457 458 struct slave_list { 459 struct mutex mutex; 460 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE]; 461 }; 462 463 struct mlx4_resource_tracker { 464 spinlock_t lock; 465 /* tree for each resources */ 466 struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE]; 467 /* num_of_slave's lists, one per slave */ 468 struct slave_list *slave_list; 469 }; 470 471 #define SLAVE_EVENT_EQ_SIZE 128 472 struct mlx4_slave_event_eq { 473 u32 eqn; 474 u32 cons; 475 u32 prod; 476 spinlock_t event_lock; 477 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE]; 478 }; 479 480 struct mlx4_master_qp0_state { 481 int proxy_qp0_active; 482 int qp0_active; 483 int port_active; 484 }; 485 486 struct mlx4_mfunc_master_ctx { 487 struct mlx4_slave_state *slave_state; 488 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1]; 489 int init_port_ref[MLX4_MAX_PORTS + 1]; 490 u16 max_mtu[MLX4_MAX_PORTS + 1]; 491 int disable_mcast_ref[MLX4_MAX_PORTS + 1]; 492 struct mlx4_resource_tracker res_tracker; 493 struct workqueue_struct *comm_wq; 494 struct work_struct comm_work; 495 struct work_struct slave_event_work; 496 struct work_struct slave_flr_event_work; 497 spinlock_t slave_state_lock; 498 __be32 comm_arm_bit_vector[4]; 499 struct mlx4_eqe cmd_eqe; 500 struct mlx4_slave_event_eq slave_eq; 501 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX]; 502 }; 503 504 struct mlx4_mfunc { 505 struct mlx4_comm __iomem *comm; 506 struct mlx4_vhcr_cmd *vhcr; 507 dma_addr_t vhcr_dma; 508 509 struct mlx4_mfunc_master_ctx master; 510 }; 511 512 struct mlx4_cmd { 513 struct pci_pool *pool; 514 void __iomem *hcr; 515 struct mutex hcr_mutex; 516 struct mutex slave_cmd_mutex; 517 struct semaphore poll_sem; 518 struct semaphore event_sem; 519 int max_cmds; 520 spinlock_t context_lock; 521 int free_head; 522 struct mlx4_cmd_context *context; 523 u16 token_mask; 524 u8 use_events; 525 u8 toggle; 526 u8 comm_toggle; 527 }; 528 529 struct mlx4_uar_table { 530 struct mlx4_bitmap bitmap; 531 }; 532 533 struct mlx4_mr_table { 534 struct mlx4_bitmap mpt_bitmap; 535 struct mlx4_buddy mtt_buddy; 536 u64 mtt_base; 537 u64 mpt_base; 538 struct mlx4_icm_table mtt_table; 539 struct mlx4_icm_table dmpt_table; 540 }; 541 542 struct mlx4_cq_table { 543 struct mlx4_bitmap bitmap; 544 spinlock_t lock; 545 struct radix_tree_root tree; 546 struct mlx4_icm_table table; 547 struct mlx4_icm_table cmpt_table; 548 }; 549 550 struct mlx4_eq_table { 551 struct mlx4_bitmap bitmap; 552 char *irq_names; 553 void __iomem *clr_int; 554 void __iomem **uar_map; 555 u32 clr_mask; 556 struct mlx4_eq *eq; 557 struct mlx4_icm_table table; 558 struct mlx4_icm_table cmpt_table; 559 int have_irq; 560 u8 inta_pin; 561 }; 562 563 struct mlx4_srq_table { 564 struct mlx4_bitmap bitmap; 565 spinlock_t lock; 566 struct radix_tree_root tree; 567 struct mlx4_icm_table table; 568 struct mlx4_icm_table cmpt_table; 569 }; 570 571 struct mlx4_qp_table { 572 struct mlx4_bitmap bitmap; 573 u32 rdmarc_base; 574 int rdmarc_shift; 575 spinlock_t lock; 576 struct mlx4_icm_table qp_table; 577 struct mlx4_icm_table auxc_table; 578 struct mlx4_icm_table altc_table; 579 struct mlx4_icm_table rdmarc_table; 580 struct mlx4_icm_table cmpt_table; 581 }; 582 583 struct mlx4_mcg_table { 584 struct mutex mutex; 585 struct mlx4_bitmap bitmap; 586 struct mlx4_icm_table table; 587 }; 588 589 struct mlx4_catas_err { 590 u32 __iomem *map; 591 struct timer_list timer; 592 struct list_head list; 593 }; 594 595 #define MLX4_MAX_MAC_NUM 128 596 #define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3) 597 598 struct mlx4_mac_table { 599 __be64 entries[MLX4_MAX_MAC_NUM]; 600 int refs[MLX4_MAX_MAC_NUM]; 601 struct mutex mutex; 602 int total; 603 int max; 604 }; 605 606 #define MLX4_MAX_VLAN_NUM 128 607 #define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2) 608 609 struct mlx4_vlan_table { 610 __be32 entries[MLX4_MAX_VLAN_NUM]; 611 int refs[MLX4_MAX_VLAN_NUM]; 612 struct mutex mutex; 613 int total; 614 int max; 615 }; 616 617 #define SET_PORT_GEN_ALL_VALID 0x7 618 #define SET_PORT_PROMISC_SHIFT 31 619 #define SET_PORT_MC_PROMISC_SHIFT 30 620 621 enum { 622 MCAST_DIRECT_ONLY = 0, 623 MCAST_DIRECT = 1, 624 MCAST_DEFAULT = 2 625 }; 626 627 628 struct mlx4_set_port_general_context { 629 u8 reserved[3]; 630 u8 flags; 631 u16 reserved2; 632 __be16 mtu; 633 u8 pptx; 634 u8 pfctx; 635 u16 reserved3; 636 u8 pprx; 637 u8 pfcrx; 638 u16 reserved4; 639 }; 640 641 struct mlx4_set_port_rqp_calc_context { 642 __be32 base_qpn; 643 u8 rererved; 644 u8 n_mac; 645 u8 n_vlan; 646 u8 n_prio; 647 u8 reserved2[3]; 648 u8 mac_miss; 649 u8 intra_no_vlan; 650 u8 no_vlan; 651 u8 intra_vlan_miss; 652 u8 vlan_miss; 653 u8 reserved3[3]; 654 u8 no_vlan_prio; 655 __be32 promisc; 656 __be32 mcast; 657 }; 658 659 struct mlx4_mac_entry { 660 u64 mac; 661 u64 reg_id; 662 }; 663 664 struct mlx4_port_info { 665 struct mlx4_dev *dev; 666 int port; 667 char dev_name[16]; 668 struct device_attribute port_attr; 669 enum mlx4_port_type tmp_type; 670 char dev_mtu_name[16]; 671 struct device_attribute port_mtu_attr; 672 struct mlx4_mac_table mac_table; 673 struct radix_tree_root mac_tree; 674 struct mlx4_vlan_table vlan_table; 675 int base_qpn; 676 }; 677 678 struct mlx4_sense { 679 struct mlx4_dev *dev; 680 u8 do_sense_port[MLX4_MAX_PORTS + 1]; 681 u8 sense_allowed[MLX4_MAX_PORTS + 1]; 682 struct delayed_work sense_poll; 683 }; 684 685 struct mlx4_msix_ctl { 686 u64 pool_bm; 687 struct mutex pool_lock; 688 }; 689 690 struct mlx4_steer { 691 struct list_head promisc_qps[MLX4_NUM_STEERS]; 692 struct list_head steer_entries[MLX4_NUM_STEERS]; 693 }; 694 695 struct mlx4_net_trans_rule_hw_ctrl { 696 __be32 ctrl; 697 __be32 vf_vep_port; 698 __be32 qpn; 699 __be32 reserved; 700 }; 701 702 struct mlx4_net_trans_rule_hw_ib { 703 u8 size; 704 u8 rsvd1; 705 __be16 id; 706 u32 rsvd2; 707 __be32 qpn; 708 __be32 qpn_mask; 709 u8 dst_gid[16]; 710 u8 dst_gid_msk[16]; 711 } __packed; 712 713 struct mlx4_net_trans_rule_hw_eth { 714 u8 size; 715 u8 rsvd; 716 __be16 id; 717 u8 rsvd1[6]; 718 u8 dst_mac[6]; 719 u16 rsvd2; 720 u8 dst_mac_msk[6]; 721 u16 rsvd3; 722 u8 src_mac[6]; 723 u16 rsvd4; 724 u8 src_mac_msk[6]; 725 u8 rsvd5; 726 u8 ether_type_enable; 727 __be16 ether_type; 728 __be16 vlan_id_msk; 729 __be16 vlan_id; 730 } __packed; 731 732 struct mlx4_net_trans_rule_hw_tcp_udp { 733 u8 size; 734 u8 rsvd; 735 __be16 id; 736 __be16 rsvd1[3]; 737 __be16 dst_port; 738 __be16 rsvd2; 739 __be16 dst_port_msk; 740 __be16 rsvd3; 741 __be16 src_port; 742 __be16 rsvd4; 743 __be16 src_port_msk; 744 } __packed; 745 746 struct mlx4_net_trans_rule_hw_ipv4 { 747 u8 size; 748 u8 rsvd; 749 __be16 id; 750 __be32 rsvd1; 751 __be32 dst_ip; 752 __be32 dst_ip_msk; 753 __be32 src_ip; 754 __be32 src_ip_msk; 755 } __packed; 756 757 struct _rule_hw { 758 union { 759 struct { 760 u8 size; 761 u8 rsvd; 762 __be16 id; 763 }; 764 struct mlx4_net_trans_rule_hw_eth eth; 765 struct mlx4_net_trans_rule_hw_ib ib; 766 struct mlx4_net_trans_rule_hw_ipv4 ipv4; 767 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp; 768 }; 769 }; 770 771 enum { 772 MLX4_PCI_DEV_IS_VF = 1 << 0, 773 MLX4_PCI_DEV_FORCE_SENSE_PORT = 1 << 1, 774 }; 775 776 struct mlx4_priv { 777 struct mlx4_dev dev; 778 779 struct list_head dev_list; 780 struct list_head ctx_list; 781 spinlock_t ctx_lock; 782 783 int pci_dev_data; 784 785 struct list_head pgdir_list; 786 struct mutex pgdir_mutex; 787 788 struct mlx4_fw fw; 789 struct mlx4_cmd cmd; 790 struct mlx4_mfunc mfunc; 791 792 struct mlx4_bitmap pd_bitmap; 793 struct mlx4_bitmap xrcd_bitmap; 794 struct mlx4_uar_table uar_table; 795 struct mlx4_mr_table mr_table; 796 struct mlx4_cq_table cq_table; 797 struct mlx4_eq_table eq_table; 798 struct mlx4_srq_table srq_table; 799 struct mlx4_qp_table qp_table; 800 struct mlx4_mcg_table mcg_table; 801 struct mlx4_bitmap counters_bitmap; 802 803 struct mlx4_catas_err catas_err; 804 805 void __iomem *clr_base; 806 807 struct mlx4_uar driver_uar; 808 void __iomem *kar; 809 struct mlx4_port_info port[MLX4_MAX_PORTS + 1]; 810 struct mlx4_sense sense; 811 struct mutex port_mutex; 812 struct mlx4_msix_ctl msix_ctl; 813 struct mlx4_steer *steer; 814 struct list_head bf_list; 815 struct mutex bf_mutex; 816 struct io_mapping *bf_mapping; 817 int reserved_mtts; 818 int fs_hash_mode; 819 u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS]; 820 __be64 slave_node_guids[MLX4_MFUNC_MAX]; 821 822 }; 823 824 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev) 825 { 826 return container_of(dev, struct mlx4_priv, dev); 827 } 828 829 #define MLX4_SENSE_RANGE (HZ * 3) 830 831 extern struct workqueue_struct *mlx4_wq; 832 833 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap); 834 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj); 835 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align); 836 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt); 837 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap); 838 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask, 839 u32 reserved_bot, u32 resetrved_top); 840 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap); 841 842 int mlx4_reset(struct mlx4_dev *dev); 843 844 int mlx4_alloc_eq_table(struct mlx4_dev *dev); 845 void mlx4_free_eq_table(struct mlx4_dev *dev); 846 847 int mlx4_init_pd_table(struct mlx4_dev *dev); 848 int mlx4_init_xrcd_table(struct mlx4_dev *dev); 849 int mlx4_init_uar_table(struct mlx4_dev *dev); 850 int mlx4_init_mr_table(struct mlx4_dev *dev); 851 int mlx4_init_eq_table(struct mlx4_dev *dev); 852 int mlx4_init_cq_table(struct mlx4_dev *dev); 853 int mlx4_init_qp_table(struct mlx4_dev *dev); 854 int mlx4_init_srq_table(struct mlx4_dev *dev); 855 int mlx4_init_mcg_table(struct mlx4_dev *dev); 856 857 void mlx4_cleanup_pd_table(struct mlx4_dev *dev); 858 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev); 859 void mlx4_cleanup_uar_table(struct mlx4_dev *dev); 860 void mlx4_cleanup_mr_table(struct mlx4_dev *dev); 861 void mlx4_cleanup_eq_table(struct mlx4_dev *dev); 862 void mlx4_cleanup_cq_table(struct mlx4_dev *dev); 863 void mlx4_cleanup_qp_table(struct mlx4_dev *dev); 864 void mlx4_cleanup_srq_table(struct mlx4_dev *dev); 865 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev); 866 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn); 867 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn); 868 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn); 869 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn); 870 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn); 871 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn); 872 int __mlx4_mr_reserve(struct mlx4_dev *dev); 873 void __mlx4_mr_release(struct mlx4_dev *dev, u32 index); 874 int __mlx4_mr_alloc_icm(struct mlx4_dev *dev, u32 index); 875 void __mlx4_mr_free_icm(struct mlx4_dev *dev, u32 index); 876 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order); 877 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order); 878 879 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave, 880 struct mlx4_vhcr *vhcr, 881 struct mlx4_cmd_mailbox *inbox, 882 struct mlx4_cmd_mailbox *outbox, 883 struct mlx4_cmd_info *cmd); 884 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave, 885 struct mlx4_vhcr *vhcr, 886 struct mlx4_cmd_mailbox *inbox, 887 struct mlx4_cmd_mailbox *outbox, 888 struct mlx4_cmd_info *cmd); 889 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave, 890 struct mlx4_vhcr *vhcr, 891 struct mlx4_cmd_mailbox *inbox, 892 struct mlx4_cmd_mailbox *outbox, 893 struct mlx4_cmd_info *cmd); 894 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave, 895 struct mlx4_vhcr *vhcr, 896 struct mlx4_cmd_mailbox *inbox, 897 struct mlx4_cmd_mailbox *outbox, 898 struct mlx4_cmd_info *cmd); 899 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave, 900 struct mlx4_vhcr *vhcr, 901 struct mlx4_cmd_mailbox *inbox, 902 struct mlx4_cmd_mailbox *outbox, 903 struct mlx4_cmd_info *cmd); 904 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave, 905 struct mlx4_vhcr *vhcr, 906 struct mlx4_cmd_mailbox *inbox, 907 struct mlx4_cmd_mailbox *outbox, 908 struct mlx4_cmd_info *cmd); 909 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave, 910 struct mlx4_vhcr *vhcr, 911 struct mlx4_cmd_mailbox *inbox, 912 struct mlx4_cmd_mailbox *outbox, 913 struct mlx4_cmd_info *cmd); 914 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, 915 int *base); 916 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); 917 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); 918 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); 919 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac); 920 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 921 int start_index, int npages, u64 *page_list); 922 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx); 923 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx); 924 int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); 925 void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); 926 927 void mlx4_start_catas_poll(struct mlx4_dev *dev); 928 void mlx4_stop_catas_poll(struct mlx4_dev *dev); 929 void mlx4_catas_init(void); 930 int mlx4_restart_one(struct pci_dev *pdev); 931 int mlx4_register_device(struct mlx4_dev *dev); 932 void mlx4_unregister_device(struct mlx4_dev *dev); 933 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type, 934 unsigned long param); 935 936 struct mlx4_dev_cap; 937 struct mlx4_init_hca_param; 938 939 u64 mlx4_make_profile(struct mlx4_dev *dev, 940 struct mlx4_profile *request, 941 struct mlx4_dev_cap *dev_cap, 942 struct mlx4_init_hca_param *init_hca); 943 void mlx4_master_comm_channel(struct work_struct *work); 944 void mlx4_gen_slave_eqe(struct work_struct *work); 945 void mlx4_master_handle_slave_flr(struct work_struct *work); 946 947 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave, 948 struct mlx4_vhcr *vhcr, 949 struct mlx4_cmd_mailbox *inbox, 950 struct mlx4_cmd_mailbox *outbox, 951 struct mlx4_cmd_info *cmd); 952 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave, 953 struct mlx4_vhcr *vhcr, 954 struct mlx4_cmd_mailbox *inbox, 955 struct mlx4_cmd_mailbox *outbox, 956 struct mlx4_cmd_info *cmd); 957 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave, 958 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox, 959 struct mlx4_cmd_mailbox *outbox, 960 struct mlx4_cmd_info *cmd); 961 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave, 962 struct mlx4_vhcr *vhcr, 963 struct mlx4_cmd_mailbox *inbox, 964 struct mlx4_cmd_mailbox *outbox, 965 struct mlx4_cmd_info *cmd); 966 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave, 967 struct mlx4_vhcr *vhcr, 968 struct mlx4_cmd_mailbox *inbox, 969 struct mlx4_cmd_mailbox *outbox, 970 struct mlx4_cmd_info *cmd); 971 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave, 972 struct mlx4_vhcr *vhcr, 973 struct mlx4_cmd_mailbox *inbox, 974 struct mlx4_cmd_mailbox *outbox, 975 struct mlx4_cmd_info *cmd); 976 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave, 977 struct mlx4_vhcr *vhcr, 978 struct mlx4_cmd_mailbox *inbox, 979 struct mlx4_cmd_mailbox *outbox, 980 struct mlx4_cmd_info *cmd); 981 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave, 982 struct mlx4_vhcr *vhcr, 983 struct mlx4_cmd_mailbox *inbox, 984 struct mlx4_cmd_mailbox *outbox, 985 struct mlx4_cmd_info *cmd); 986 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave, 987 struct mlx4_vhcr *vhcr, 988 struct mlx4_cmd_mailbox *inbox, 989 struct mlx4_cmd_mailbox *outbox, 990 struct mlx4_cmd_info *cmd); 991 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave, 992 struct mlx4_vhcr *vhcr, 993 struct mlx4_cmd_mailbox *inbox, 994 struct mlx4_cmd_mailbox *outbox, 995 struct mlx4_cmd_info *cmd); 996 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave, 997 struct mlx4_vhcr *vhcr, 998 struct mlx4_cmd_mailbox *inbox, 999 struct mlx4_cmd_mailbox *outbox, 1000 struct mlx4_cmd_info *cmd); 1001 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave, 1002 struct mlx4_vhcr *vhcr, 1003 struct mlx4_cmd_mailbox *inbox, 1004 struct mlx4_cmd_mailbox *outbox, 1005 struct mlx4_cmd_info *cmd); 1006 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave, 1007 struct mlx4_vhcr *vhcr, 1008 struct mlx4_cmd_mailbox *inbox, 1009 struct mlx4_cmd_mailbox *outbox, 1010 struct mlx4_cmd_info *cmd); 1011 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave, 1012 struct mlx4_vhcr *vhcr, 1013 struct mlx4_cmd_mailbox *inbox, 1014 struct mlx4_cmd_mailbox *outbox, 1015 struct mlx4_cmd_info *cmd); 1016 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave, 1017 struct mlx4_vhcr *vhcr, 1018 struct mlx4_cmd_mailbox *inbox, 1019 struct mlx4_cmd_mailbox *outbox, 1020 struct mlx4_cmd_info *cmd); 1021 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave, 1022 struct mlx4_vhcr *vhcr, 1023 struct mlx4_cmd_mailbox *inbox, 1024 struct mlx4_cmd_mailbox *outbox, 1025 struct mlx4_cmd_info *cmd); 1026 int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave, 1027 struct mlx4_vhcr *vhcr, 1028 struct mlx4_cmd_mailbox *inbox, 1029 struct mlx4_cmd_mailbox *outbox, 1030 struct mlx4_cmd_info *cmd); 1031 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave, 1032 struct mlx4_vhcr *vhcr, 1033 struct mlx4_cmd_mailbox *inbox, 1034 struct mlx4_cmd_mailbox *outbox, 1035 struct mlx4_cmd_info *cmd); 1036 int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1037 struct mlx4_vhcr *vhcr, 1038 struct mlx4_cmd_mailbox *inbox, 1039 struct mlx4_cmd_mailbox *outbox, 1040 struct mlx4_cmd_info *cmd); 1041 int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1042 struct mlx4_vhcr *vhcr, 1043 struct mlx4_cmd_mailbox *inbox, 1044 struct mlx4_cmd_mailbox *outbox, 1045 struct mlx4_cmd_info *cmd); 1046 int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1047 struct mlx4_vhcr *vhcr, 1048 struct mlx4_cmd_mailbox *inbox, 1049 struct mlx4_cmd_mailbox *outbox, 1050 struct mlx4_cmd_info *cmd); 1051 int mlx4_2ERR_QP_wrapper(struct mlx4_dev *dev, int slave, 1052 struct mlx4_vhcr *vhcr, 1053 struct mlx4_cmd_mailbox *inbox, 1054 struct mlx4_cmd_mailbox *outbox, 1055 struct mlx4_cmd_info *cmd); 1056 int mlx4_RTS2SQD_QP_wrapper(struct mlx4_dev *dev, int slave, 1057 struct mlx4_vhcr *vhcr, 1058 struct mlx4_cmd_mailbox *inbox, 1059 struct mlx4_cmd_mailbox *outbox, 1060 struct mlx4_cmd_info *cmd); 1061 int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave, 1062 struct mlx4_vhcr *vhcr, 1063 struct mlx4_cmd_mailbox *inbox, 1064 struct mlx4_cmd_mailbox *outbox, 1065 struct mlx4_cmd_info *cmd); 1066 int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1067 struct mlx4_vhcr *vhcr, 1068 struct mlx4_cmd_mailbox *inbox, 1069 struct mlx4_cmd_mailbox *outbox, 1070 struct mlx4_cmd_info *cmd); 1071 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave, 1072 struct mlx4_vhcr *vhcr, 1073 struct mlx4_cmd_mailbox *inbox, 1074 struct mlx4_cmd_mailbox *outbox, 1075 struct mlx4_cmd_info *cmd); 1076 int mlx4_QUERY_QP_wrapper(struct mlx4_dev *dev, int slave, 1077 struct mlx4_vhcr *vhcr, 1078 struct mlx4_cmd_mailbox *inbox, 1079 struct mlx4_cmd_mailbox *outbox, 1080 struct mlx4_cmd_info *cmd); 1081 1082 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe); 1083 1084 int mlx4_cmd_init(struct mlx4_dev *dev); 1085 void mlx4_cmd_cleanup(struct mlx4_dev *dev); 1086 int mlx4_multi_func_init(struct mlx4_dev *dev); 1087 void mlx4_multi_func_cleanup(struct mlx4_dev *dev); 1088 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param); 1089 int mlx4_cmd_use_events(struct mlx4_dev *dev); 1090 void mlx4_cmd_use_polling(struct mlx4_dev *dev); 1091 1092 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param, 1093 unsigned long timeout); 1094 1095 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn); 1096 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type); 1097 1098 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type); 1099 1100 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type); 1101 1102 void mlx4_handle_catas_err(struct mlx4_dev *dev); 1103 1104 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port, 1105 enum mlx4_port_type *type); 1106 void mlx4_do_sense_ports(struct mlx4_dev *dev, 1107 enum mlx4_port_type *stype, 1108 enum mlx4_port_type *defaults); 1109 void mlx4_start_sense(struct mlx4_dev *dev); 1110 void mlx4_stop_sense(struct mlx4_dev *dev); 1111 void mlx4_sense_init(struct mlx4_dev *dev); 1112 int mlx4_check_port_params(struct mlx4_dev *dev, 1113 enum mlx4_port_type *port_type); 1114 int mlx4_change_port_types(struct mlx4_dev *dev, 1115 enum mlx4_port_type *port_types); 1116 1117 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table); 1118 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table); 1119 1120 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz); 1121 /* resource tracker functions*/ 1122 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev, 1123 enum mlx4_resource resource_type, 1124 u64 resource_id, int *slave); 1125 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id); 1126 int mlx4_init_resource_tracker(struct mlx4_dev *dev); 1127 1128 void mlx4_free_resource_tracker(struct mlx4_dev *dev, 1129 enum mlx4_res_tracker_free_type type); 1130 1131 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave, 1132 struct mlx4_vhcr *vhcr, 1133 struct mlx4_cmd_mailbox *inbox, 1134 struct mlx4_cmd_mailbox *outbox, 1135 struct mlx4_cmd_info *cmd); 1136 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave, 1137 struct mlx4_vhcr *vhcr, 1138 struct mlx4_cmd_mailbox *inbox, 1139 struct mlx4_cmd_mailbox *outbox, 1140 struct mlx4_cmd_info *cmd); 1141 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave, 1142 struct mlx4_vhcr *vhcr, 1143 struct mlx4_cmd_mailbox *inbox, 1144 struct mlx4_cmd_mailbox *outbox, 1145 struct mlx4_cmd_info *cmd); 1146 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave, 1147 struct mlx4_vhcr *vhcr, 1148 struct mlx4_cmd_mailbox *inbox, 1149 struct mlx4_cmd_mailbox *outbox, 1150 struct mlx4_cmd_info *cmd); 1151 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave, 1152 struct mlx4_vhcr *vhcr, 1153 struct mlx4_cmd_mailbox *inbox, 1154 struct mlx4_cmd_mailbox *outbox, 1155 struct mlx4_cmd_info *cmd); 1156 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave, 1157 struct mlx4_vhcr *vhcr, 1158 struct mlx4_cmd_mailbox *inbox, 1159 struct mlx4_cmd_mailbox *outbox, 1160 struct mlx4_cmd_info *cmd); 1161 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps); 1162 1163 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port, 1164 int *gid_tbl_len, int *pkey_tbl_len); 1165 1166 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave, 1167 struct mlx4_vhcr *vhcr, 1168 struct mlx4_cmd_mailbox *inbox, 1169 struct mlx4_cmd_mailbox *outbox, 1170 struct mlx4_cmd_info *cmd); 1171 1172 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave, 1173 struct mlx4_vhcr *vhcr, 1174 struct mlx4_cmd_mailbox *inbox, 1175 struct mlx4_cmd_mailbox *outbox, 1176 struct mlx4_cmd_info *cmd); 1177 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1178 enum mlx4_protocol prot, enum mlx4_steer_type steer); 1179 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1180 int block_mcast_loopback, enum mlx4_protocol prot, 1181 enum mlx4_steer_type steer); 1182 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave, 1183 struct mlx4_vhcr *vhcr, 1184 struct mlx4_cmd_mailbox *inbox, 1185 struct mlx4_cmd_mailbox *outbox, 1186 struct mlx4_cmd_info *cmd); 1187 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave, 1188 struct mlx4_vhcr *vhcr, 1189 struct mlx4_cmd_mailbox *inbox, 1190 struct mlx4_cmd_mailbox *outbox, 1191 struct mlx4_cmd_info *cmd); 1192 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function, 1193 int port, void *buf); 1194 int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod, 1195 struct mlx4_cmd_mailbox *outbox); 1196 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave, 1197 struct mlx4_vhcr *vhcr, 1198 struct mlx4_cmd_mailbox *inbox, 1199 struct mlx4_cmd_mailbox *outbox, 1200 struct mlx4_cmd_info *cmd); 1201 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave, 1202 struct mlx4_vhcr *vhcr, 1203 struct mlx4_cmd_mailbox *inbox, 1204 struct mlx4_cmd_mailbox *outbox, 1205 struct mlx4_cmd_info *cmd); 1206 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave, 1207 struct mlx4_vhcr *vhcr, 1208 struct mlx4_cmd_mailbox *inbox, 1209 struct mlx4_cmd_mailbox *outbox, 1210 struct mlx4_cmd_info *cmd); 1211 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave, 1212 struct mlx4_vhcr *vhcr, 1213 struct mlx4_cmd_mailbox *inbox, 1214 struct mlx4_cmd_mailbox *outbox, 1215 struct mlx4_cmd_info *cmd); 1216 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave, 1217 struct mlx4_vhcr *vhcr, 1218 struct mlx4_cmd_mailbox *inbox, 1219 struct mlx4_cmd_mailbox *outbox, 1220 struct mlx4_cmd_info *cmd); 1221 1222 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev); 1223 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev); 1224 1225 static inline void set_param_l(u64 *arg, u32 val) 1226 { 1227 *((u32 *)arg) = val; 1228 } 1229 1230 static inline void set_param_h(u64 *arg, u32 val) 1231 { 1232 *arg = (*arg & 0xffffffff) | ((u64) val << 32); 1233 } 1234 1235 static inline u32 get_param_l(u64 *arg) 1236 { 1237 return (u32) (*arg & 0xffffffff); 1238 } 1239 1240 static inline u32 get_param_h(u64 *arg) 1241 { 1242 return (u32)(*arg >> 32); 1243 } 1244 1245 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev) 1246 { 1247 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock; 1248 } 1249 1250 #define NOT_MASKED_PD_BITS 17 1251 1252 #endif /* MLX4_H */ 1253