1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved. 5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved. 7 * 8 * This software is available to you under a choice of one of two 9 * licenses. You may choose to be licensed under the terms of the GNU 10 * General Public License (GPL) Version 2, available from the file 11 * COPYING in the main directory of this source tree, or the 12 * OpenIB.org BSD license below: 13 * 14 * Redistribution and use in source and binary forms, with or 15 * without modification, are permitted provided that the following 16 * conditions are met: 17 * 18 * - Redistributions of source code must retain the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer. 21 * 22 * - Redistributions in binary form must reproduce the above 23 * copyright notice, this list of conditions and the following 24 * disclaimer in the documentation and/or other materials 25 * provided with the distribution. 26 * 27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 34 * SOFTWARE. 35 */ 36 37 #ifndef MLX4_H 38 #define MLX4_H 39 40 #include <linux/mutex.h> 41 #include <linux/radix-tree.h> 42 #include <linux/timer.h> 43 #include <linux/semaphore.h> 44 #include <linux/workqueue.h> 45 46 #include <linux/mlx4/device.h> 47 #include <linux/mlx4/driver.h> 48 #include <linux/mlx4/doorbell.h> 49 #include <linux/mlx4/cmd.h> 50 51 #define DRV_NAME "mlx4_core" 52 #define PFX DRV_NAME ": " 53 #define DRV_VERSION "1.1" 54 #define DRV_RELDATE "Dec, 2011" 55 56 enum { 57 MLX4_HCR_BASE = 0x80680, 58 MLX4_HCR_SIZE = 0x0001c, 59 MLX4_CLR_INT_SIZE = 0x00008, 60 MLX4_SLAVE_COMM_BASE = 0x0, 61 MLX4_COMM_PAGESIZE = 0x1000 62 }; 63 64 enum { 65 MLX4_MAX_MGM_ENTRY_SIZE = 0x1000, 66 MLX4_MAX_QP_PER_MGM = 4 * (MLX4_MAX_MGM_ENTRY_SIZE / 16 - 2), 67 MLX4_MTT_ENTRY_PER_SEG = 8, 68 }; 69 70 enum { 71 MLX4_NUM_PDS = 1 << 15 72 }; 73 74 enum { 75 MLX4_CMPT_TYPE_QP = 0, 76 MLX4_CMPT_TYPE_SRQ = 1, 77 MLX4_CMPT_TYPE_CQ = 2, 78 MLX4_CMPT_TYPE_EQ = 3, 79 MLX4_CMPT_NUM_TYPE 80 }; 81 82 enum { 83 MLX4_CMPT_SHIFT = 24, 84 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT 85 }; 86 87 enum mlx4_mr_state { 88 MLX4_MR_DISABLED = 0, 89 MLX4_MR_EN_HW, 90 MLX4_MR_EN_SW 91 }; 92 93 #define MLX4_COMM_TIME 10000 94 enum { 95 MLX4_COMM_CMD_RESET, 96 MLX4_COMM_CMD_VHCR0, 97 MLX4_COMM_CMD_VHCR1, 98 MLX4_COMM_CMD_VHCR2, 99 MLX4_COMM_CMD_VHCR_EN, 100 MLX4_COMM_CMD_VHCR_POST, 101 MLX4_COMM_CMD_FLR = 254 102 }; 103 104 /*The flag indicates that the slave should delay the RESET cmd*/ 105 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb 106 /*indicates how many retries will be done if we are in the middle of FLR*/ 107 #define NUM_OF_RESET_RETRIES 10 108 #define SLEEP_TIME_IN_RESET (2 * 1000) 109 enum mlx4_resource { 110 RES_QP, 111 RES_CQ, 112 RES_SRQ, 113 RES_XRCD, 114 RES_MPT, 115 RES_MTT, 116 RES_MAC, 117 RES_VLAN, 118 RES_EQ, 119 RES_COUNTER, 120 MLX4_NUM_OF_RESOURCE_TYPE 121 }; 122 123 enum mlx4_alloc_mode { 124 RES_OP_RESERVE, 125 RES_OP_RESERVE_AND_MAP, 126 RES_OP_MAP_ICM, 127 }; 128 129 130 /* 131 *Virtual HCR structures. 132 * mlx4_vhcr is the sw representation, in machine endianess 133 * 134 * mlx4_vhcr_cmd is the formalized structure, the one that is passed 135 * to FW to go through communication channel. 136 * It is big endian, and has the same structure as the physical HCR 137 * used by command interface 138 */ 139 struct mlx4_vhcr { 140 u64 in_param; 141 u64 out_param; 142 u32 in_modifier; 143 u32 errno; 144 u16 op; 145 u16 token; 146 u8 op_modifier; 147 u8 e_bit; 148 }; 149 150 struct mlx4_vhcr_cmd { 151 __be64 in_param; 152 __be32 in_modifier; 153 __be64 out_param; 154 __be16 token; 155 u16 reserved; 156 u8 status; 157 u8 flags; 158 __be16 opcode; 159 }; 160 161 struct mlx4_cmd_info { 162 u16 opcode; 163 bool has_inbox; 164 bool has_outbox; 165 bool out_is_imm; 166 bool encode_slave_id; 167 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr, 168 struct mlx4_cmd_mailbox *inbox); 169 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr, 170 struct mlx4_cmd_mailbox *inbox, 171 struct mlx4_cmd_mailbox *outbox, 172 struct mlx4_cmd_info *cmd); 173 }; 174 175 #ifdef CONFIG_MLX4_DEBUG 176 extern int mlx4_debug_level; 177 #else /* CONFIG_MLX4_DEBUG */ 178 #define mlx4_debug_level (0) 179 #endif /* CONFIG_MLX4_DEBUG */ 180 181 #define mlx4_dbg(mdev, format, arg...) \ 182 do { \ 183 if (mlx4_debug_level) \ 184 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \ 185 } while (0) 186 187 #define mlx4_err(mdev, format, arg...) \ 188 dev_err(&mdev->pdev->dev, format, ##arg) 189 #define mlx4_info(mdev, format, arg...) \ 190 dev_info(&mdev->pdev->dev, format, ##arg) 191 #define mlx4_warn(mdev, format, arg...) \ 192 dev_warn(&mdev->pdev->dev, format, ##arg) 193 194 extern int mlx4_log_num_mgm_entry_size; 195 extern int log_mtts_per_seg; 196 197 #define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF) 198 #define ALL_SLAVES 0xff 199 200 struct mlx4_bitmap { 201 u32 last; 202 u32 top; 203 u32 max; 204 u32 reserved_top; 205 u32 mask; 206 u32 avail; 207 spinlock_t lock; 208 unsigned long *table; 209 }; 210 211 struct mlx4_buddy { 212 unsigned long **bits; 213 unsigned int *num_free; 214 int max_order; 215 spinlock_t lock; 216 }; 217 218 struct mlx4_icm; 219 220 struct mlx4_icm_table { 221 u64 virt; 222 int num_icm; 223 int num_obj; 224 int obj_size; 225 int lowmem; 226 int coherent; 227 struct mutex mutex; 228 struct mlx4_icm **icm; 229 }; 230 231 /* 232 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits. 233 */ 234 struct mlx4_mpt_entry { 235 __be32 flags; 236 __be32 qpn; 237 __be32 key; 238 __be32 pd_flags; 239 __be64 start; 240 __be64 length; 241 __be32 lkey; 242 __be32 win_cnt; 243 u8 reserved1[3]; 244 u8 mtt_rep; 245 __be64 mtt_addr; 246 __be32 mtt_sz; 247 __be32 entity_size; 248 __be32 first_byte_offset; 249 } __packed; 250 251 /* 252 * Must be packed because start is 64 bits but only aligned to 32 bits. 253 */ 254 struct mlx4_eq_context { 255 __be32 flags; 256 u16 reserved1[3]; 257 __be16 page_offset; 258 u8 log_eq_size; 259 u8 reserved2[4]; 260 u8 eq_period; 261 u8 reserved3; 262 u8 eq_max_count; 263 u8 reserved4[3]; 264 u8 intr; 265 u8 log_page_size; 266 u8 reserved5[2]; 267 u8 mtt_base_addr_h; 268 __be32 mtt_base_addr_l; 269 u32 reserved6[2]; 270 __be32 consumer_index; 271 __be32 producer_index; 272 u32 reserved7[4]; 273 }; 274 275 struct mlx4_cq_context { 276 __be32 flags; 277 u16 reserved1[3]; 278 __be16 page_offset; 279 __be32 logsize_usrpage; 280 __be16 cq_period; 281 __be16 cq_max_count; 282 u8 reserved2[3]; 283 u8 comp_eqn; 284 u8 log_page_size; 285 u8 reserved3[2]; 286 u8 mtt_base_addr_h; 287 __be32 mtt_base_addr_l; 288 __be32 last_notified_index; 289 __be32 solicit_producer_index; 290 __be32 consumer_index; 291 __be32 producer_index; 292 u32 reserved4[2]; 293 __be64 db_rec_addr; 294 }; 295 296 struct mlx4_srq_context { 297 __be32 state_logsize_srqn; 298 u8 logstride; 299 u8 reserved1; 300 __be16 xrcd; 301 __be32 pg_offset_cqn; 302 u32 reserved2; 303 u8 log_page_size; 304 u8 reserved3[2]; 305 u8 mtt_base_addr_h; 306 __be32 mtt_base_addr_l; 307 __be32 pd; 308 __be16 limit_watermark; 309 __be16 wqe_cnt; 310 u16 reserved4; 311 __be16 wqe_counter; 312 u32 reserved5; 313 __be64 db_rec_addr; 314 }; 315 316 struct mlx4_eqe { 317 u8 reserved1; 318 u8 type; 319 u8 reserved2; 320 u8 subtype; 321 union { 322 u32 raw[6]; 323 struct { 324 __be32 cqn; 325 } __packed comp; 326 struct { 327 u16 reserved1; 328 __be16 token; 329 u32 reserved2; 330 u8 reserved3[3]; 331 u8 status; 332 __be64 out_param; 333 } __packed cmd; 334 struct { 335 __be32 qpn; 336 } __packed qp; 337 struct { 338 __be32 srqn; 339 } __packed srq; 340 struct { 341 __be32 cqn; 342 u32 reserved1; 343 u8 reserved2[3]; 344 u8 syndrome; 345 } __packed cq_err; 346 struct { 347 u32 reserved1[2]; 348 __be32 port; 349 } __packed port_change; 350 struct { 351 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4 352 u32 reserved; 353 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE]; 354 } __packed comm_channel_arm; 355 struct { 356 u8 port; 357 u8 reserved[3]; 358 __be64 mac; 359 } __packed mac_update; 360 struct { 361 u8 port; 362 } __packed sw_event; 363 struct { 364 __be32 slave_id; 365 } __packed flr_event; 366 } event; 367 u8 slave_id; 368 u8 reserved3[2]; 369 u8 owner; 370 } __packed; 371 372 struct mlx4_eq { 373 struct mlx4_dev *dev; 374 void __iomem *doorbell; 375 int eqn; 376 u32 cons_index; 377 u16 irq; 378 u16 have_irq; 379 int nent; 380 struct mlx4_buf_list *page_list; 381 struct mlx4_mtt mtt; 382 }; 383 384 struct mlx4_slave_eqe { 385 u8 type; 386 u8 port; 387 u32 param; 388 }; 389 390 struct mlx4_slave_event_eq_info { 391 int eqn; 392 u16 token; 393 }; 394 395 struct mlx4_profile { 396 int num_qp; 397 int rdmarc_per_qp; 398 int num_srq; 399 int num_cq; 400 int num_mcg; 401 int num_mpt; 402 int num_mtt; 403 }; 404 405 struct mlx4_fw { 406 u64 clr_int_base; 407 u64 catas_offset; 408 u64 comm_base; 409 struct mlx4_icm *fw_icm; 410 struct mlx4_icm *aux_icm; 411 u32 catas_size; 412 u16 fw_pages; 413 u8 clr_int_bar; 414 u8 catas_bar; 415 u8 comm_bar; 416 }; 417 418 struct mlx4_comm { 419 u32 slave_write; 420 u32 slave_read; 421 }; 422 423 enum { 424 MLX4_MCAST_CONFIG = 0, 425 MLX4_MCAST_DISABLE = 1, 426 MLX4_MCAST_ENABLE = 2, 427 }; 428 429 #define VLAN_FLTR_SIZE 128 430 431 struct mlx4_vlan_fltr { 432 __be32 entry[VLAN_FLTR_SIZE]; 433 }; 434 435 struct mlx4_mcast_entry { 436 struct list_head list; 437 u64 addr; 438 }; 439 440 struct mlx4_promisc_qp { 441 struct list_head list; 442 u32 qpn; 443 }; 444 445 struct mlx4_steer_index { 446 struct list_head list; 447 unsigned int index; 448 struct list_head duplicates; 449 }; 450 451 #define MLX4_EVENT_TYPES_NUM 64 452 453 struct mlx4_slave_state { 454 u8 comm_toggle; 455 u8 last_cmd; 456 u8 init_port_mask; 457 bool active; 458 u8 function; 459 dma_addr_t vhcr_dma; 460 u16 mtu[MLX4_MAX_PORTS + 1]; 461 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1]; 462 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES]; 463 struct list_head mcast_filters[MLX4_MAX_PORTS + 1]; 464 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1]; 465 /* event type to eq number lookup */ 466 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM]; 467 u16 eq_pi; 468 u16 eq_ci; 469 spinlock_t lock; 470 /*initialized via the kzalloc*/ 471 u8 is_slave_going_down; 472 u32 cookie; 473 }; 474 475 struct slave_list { 476 struct mutex mutex; 477 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE]; 478 }; 479 480 struct mlx4_resource_tracker { 481 spinlock_t lock; 482 /* tree for each resources */ 483 struct radix_tree_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE]; 484 /* num_of_slave's lists, one per slave */ 485 struct slave_list *slave_list; 486 }; 487 488 #define SLAVE_EVENT_EQ_SIZE 128 489 struct mlx4_slave_event_eq { 490 u32 eqn; 491 u32 cons; 492 u32 prod; 493 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE]; 494 }; 495 496 struct mlx4_master_qp0_state { 497 int proxy_qp0_active; 498 int qp0_active; 499 int port_active; 500 }; 501 502 struct mlx4_mfunc_master_ctx { 503 struct mlx4_slave_state *slave_state; 504 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1]; 505 int init_port_ref[MLX4_MAX_PORTS + 1]; 506 u16 max_mtu[MLX4_MAX_PORTS + 1]; 507 int disable_mcast_ref[MLX4_MAX_PORTS + 1]; 508 struct mlx4_resource_tracker res_tracker; 509 struct workqueue_struct *comm_wq; 510 struct work_struct comm_work; 511 struct work_struct slave_event_work; 512 struct work_struct slave_flr_event_work; 513 spinlock_t slave_state_lock; 514 __be32 comm_arm_bit_vector[4]; 515 struct mlx4_eqe cmd_eqe; 516 struct mlx4_slave_event_eq slave_eq; 517 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX]; 518 }; 519 520 struct mlx4_mfunc { 521 struct mlx4_comm __iomem *comm; 522 struct mlx4_vhcr_cmd *vhcr; 523 dma_addr_t vhcr_dma; 524 525 struct mlx4_mfunc_master_ctx master; 526 }; 527 528 struct mlx4_cmd { 529 struct pci_pool *pool; 530 void __iomem *hcr; 531 struct mutex hcr_mutex; 532 struct semaphore poll_sem; 533 struct semaphore event_sem; 534 struct semaphore slave_sem; 535 int max_cmds; 536 spinlock_t context_lock; 537 int free_head; 538 struct mlx4_cmd_context *context; 539 u16 token_mask; 540 u8 use_events; 541 u8 toggle; 542 u8 comm_toggle; 543 }; 544 545 struct mlx4_uar_table { 546 struct mlx4_bitmap bitmap; 547 }; 548 549 struct mlx4_mr_table { 550 struct mlx4_bitmap mpt_bitmap; 551 struct mlx4_buddy mtt_buddy; 552 u64 mtt_base; 553 u64 mpt_base; 554 struct mlx4_icm_table mtt_table; 555 struct mlx4_icm_table dmpt_table; 556 }; 557 558 struct mlx4_cq_table { 559 struct mlx4_bitmap bitmap; 560 spinlock_t lock; 561 struct radix_tree_root tree; 562 struct mlx4_icm_table table; 563 struct mlx4_icm_table cmpt_table; 564 }; 565 566 struct mlx4_eq_table { 567 struct mlx4_bitmap bitmap; 568 char *irq_names; 569 void __iomem *clr_int; 570 void __iomem **uar_map; 571 u32 clr_mask; 572 struct mlx4_eq *eq; 573 struct mlx4_icm_table table; 574 struct mlx4_icm_table cmpt_table; 575 int have_irq; 576 u8 inta_pin; 577 }; 578 579 struct mlx4_srq_table { 580 struct mlx4_bitmap bitmap; 581 spinlock_t lock; 582 struct radix_tree_root tree; 583 struct mlx4_icm_table table; 584 struct mlx4_icm_table cmpt_table; 585 }; 586 587 struct mlx4_qp_table { 588 struct mlx4_bitmap bitmap; 589 u32 rdmarc_base; 590 int rdmarc_shift; 591 spinlock_t lock; 592 struct mlx4_icm_table qp_table; 593 struct mlx4_icm_table auxc_table; 594 struct mlx4_icm_table altc_table; 595 struct mlx4_icm_table rdmarc_table; 596 struct mlx4_icm_table cmpt_table; 597 }; 598 599 struct mlx4_mcg_table { 600 struct mutex mutex; 601 struct mlx4_bitmap bitmap; 602 struct mlx4_icm_table table; 603 }; 604 605 struct mlx4_catas_err { 606 u32 __iomem *map; 607 struct timer_list timer; 608 struct list_head list; 609 }; 610 611 #define MLX4_MAX_MAC_NUM 128 612 #define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3) 613 614 struct mlx4_mac_table { 615 __be64 entries[MLX4_MAX_MAC_NUM]; 616 int refs[MLX4_MAX_MAC_NUM]; 617 struct mutex mutex; 618 int total; 619 int max; 620 }; 621 622 #define MLX4_MAX_VLAN_NUM 128 623 #define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2) 624 625 struct mlx4_vlan_table { 626 __be32 entries[MLX4_MAX_VLAN_NUM]; 627 int refs[MLX4_MAX_VLAN_NUM]; 628 struct mutex mutex; 629 int total; 630 int max; 631 }; 632 633 #define SET_PORT_GEN_ALL_VALID 0x7 634 #define SET_PORT_PROMISC_SHIFT 31 635 #define SET_PORT_MC_PROMISC_SHIFT 30 636 637 enum { 638 MCAST_DIRECT_ONLY = 0, 639 MCAST_DIRECT = 1, 640 MCAST_DEFAULT = 2 641 }; 642 643 644 struct mlx4_set_port_general_context { 645 u8 reserved[3]; 646 u8 flags; 647 u16 reserved2; 648 __be16 mtu; 649 u8 pptx; 650 u8 pfctx; 651 u16 reserved3; 652 u8 pprx; 653 u8 pfcrx; 654 u16 reserved4; 655 }; 656 657 struct mlx4_set_port_rqp_calc_context { 658 __be32 base_qpn; 659 u8 rererved; 660 u8 n_mac; 661 u8 n_vlan; 662 u8 n_prio; 663 u8 reserved2[3]; 664 u8 mac_miss; 665 u8 intra_no_vlan; 666 u8 no_vlan; 667 u8 intra_vlan_miss; 668 u8 vlan_miss; 669 u8 reserved3[3]; 670 u8 no_vlan_prio; 671 __be32 promisc; 672 __be32 mcast; 673 }; 674 675 struct mlx4_mac_entry { 676 u64 mac; 677 }; 678 679 struct mlx4_port_info { 680 struct mlx4_dev *dev; 681 int port; 682 char dev_name[16]; 683 struct device_attribute port_attr; 684 enum mlx4_port_type tmp_type; 685 struct mlx4_mac_table mac_table; 686 struct radix_tree_root mac_tree; 687 struct mlx4_vlan_table vlan_table; 688 int base_qpn; 689 }; 690 691 struct mlx4_sense { 692 struct mlx4_dev *dev; 693 u8 do_sense_port[MLX4_MAX_PORTS + 1]; 694 u8 sense_allowed[MLX4_MAX_PORTS + 1]; 695 struct delayed_work sense_poll; 696 }; 697 698 struct mlx4_msix_ctl { 699 u64 pool_bm; 700 struct mutex pool_lock; 701 }; 702 703 struct mlx4_steer { 704 struct list_head promisc_qps[MLX4_NUM_STEERS]; 705 struct list_head steer_entries[MLX4_NUM_STEERS]; 706 struct list_head high_prios; 707 }; 708 709 struct mlx4_priv { 710 struct mlx4_dev dev; 711 712 struct list_head dev_list; 713 struct list_head ctx_list; 714 spinlock_t ctx_lock; 715 716 struct list_head pgdir_list; 717 struct mutex pgdir_mutex; 718 719 struct mlx4_fw fw; 720 struct mlx4_cmd cmd; 721 struct mlx4_mfunc mfunc; 722 723 struct mlx4_bitmap pd_bitmap; 724 struct mlx4_bitmap xrcd_bitmap; 725 struct mlx4_uar_table uar_table; 726 struct mlx4_mr_table mr_table; 727 struct mlx4_cq_table cq_table; 728 struct mlx4_eq_table eq_table; 729 struct mlx4_srq_table srq_table; 730 struct mlx4_qp_table qp_table; 731 struct mlx4_mcg_table mcg_table; 732 struct mlx4_bitmap counters_bitmap; 733 734 struct mlx4_catas_err catas_err; 735 736 void __iomem *clr_base; 737 738 struct mlx4_uar driver_uar; 739 void __iomem *kar; 740 struct mlx4_port_info port[MLX4_MAX_PORTS + 1]; 741 struct mlx4_sense sense; 742 struct mutex port_mutex; 743 struct mlx4_msix_ctl msix_ctl; 744 struct mlx4_steer *steer; 745 struct list_head bf_list; 746 struct mutex bf_mutex; 747 struct io_mapping *bf_mapping; 748 int reserved_mtts; 749 }; 750 751 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev) 752 { 753 return container_of(dev, struct mlx4_priv, dev); 754 } 755 756 #define MLX4_SENSE_RANGE (HZ * 3) 757 758 extern struct workqueue_struct *mlx4_wq; 759 760 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap); 761 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj); 762 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align); 763 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt); 764 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap); 765 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask, 766 u32 reserved_bot, u32 resetrved_top); 767 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap); 768 769 int mlx4_reset(struct mlx4_dev *dev); 770 771 int mlx4_alloc_eq_table(struct mlx4_dev *dev); 772 void mlx4_free_eq_table(struct mlx4_dev *dev); 773 774 int mlx4_init_pd_table(struct mlx4_dev *dev); 775 int mlx4_init_xrcd_table(struct mlx4_dev *dev); 776 int mlx4_init_uar_table(struct mlx4_dev *dev); 777 int mlx4_init_mr_table(struct mlx4_dev *dev); 778 int mlx4_init_eq_table(struct mlx4_dev *dev); 779 int mlx4_init_cq_table(struct mlx4_dev *dev); 780 int mlx4_init_qp_table(struct mlx4_dev *dev); 781 int mlx4_init_srq_table(struct mlx4_dev *dev); 782 int mlx4_init_mcg_table(struct mlx4_dev *dev); 783 784 void mlx4_cleanup_pd_table(struct mlx4_dev *dev); 785 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev); 786 void mlx4_cleanup_uar_table(struct mlx4_dev *dev); 787 void mlx4_cleanup_mr_table(struct mlx4_dev *dev); 788 void mlx4_cleanup_eq_table(struct mlx4_dev *dev); 789 void mlx4_cleanup_cq_table(struct mlx4_dev *dev); 790 void mlx4_cleanup_qp_table(struct mlx4_dev *dev); 791 void mlx4_cleanup_srq_table(struct mlx4_dev *dev); 792 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev); 793 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn); 794 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn); 795 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn); 796 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn); 797 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn); 798 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn); 799 int __mlx4_mr_reserve(struct mlx4_dev *dev); 800 void __mlx4_mr_release(struct mlx4_dev *dev, u32 index); 801 int __mlx4_mr_alloc_icm(struct mlx4_dev *dev, u32 index); 802 void __mlx4_mr_free_icm(struct mlx4_dev *dev, u32 index); 803 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order); 804 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order); 805 806 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave, 807 struct mlx4_vhcr *vhcr, 808 struct mlx4_cmd_mailbox *inbox, 809 struct mlx4_cmd_mailbox *outbox, 810 struct mlx4_cmd_info *cmd); 811 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave, 812 struct mlx4_vhcr *vhcr, 813 struct mlx4_cmd_mailbox *inbox, 814 struct mlx4_cmd_mailbox *outbox, 815 struct mlx4_cmd_info *cmd); 816 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave, 817 struct mlx4_vhcr *vhcr, 818 struct mlx4_cmd_mailbox *inbox, 819 struct mlx4_cmd_mailbox *outbox, 820 struct mlx4_cmd_info *cmd); 821 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave, 822 struct mlx4_vhcr *vhcr, 823 struct mlx4_cmd_mailbox *inbox, 824 struct mlx4_cmd_mailbox *outbox, 825 struct mlx4_cmd_info *cmd); 826 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave, 827 struct mlx4_vhcr *vhcr, 828 struct mlx4_cmd_mailbox *inbox, 829 struct mlx4_cmd_mailbox *outbox, 830 struct mlx4_cmd_info *cmd); 831 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave, 832 struct mlx4_vhcr *vhcr, 833 struct mlx4_cmd_mailbox *inbox, 834 struct mlx4_cmd_mailbox *outbox, 835 struct mlx4_cmd_info *cmd); 836 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave, 837 struct mlx4_vhcr *vhcr, 838 struct mlx4_cmd_mailbox *inbox, 839 struct mlx4_cmd_mailbox *outbox, 840 struct mlx4_cmd_info *cmd); 841 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, 842 int *base); 843 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); 844 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); 845 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); 846 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac); 847 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 848 int start_index, int npages, u64 *page_list); 849 850 void mlx4_start_catas_poll(struct mlx4_dev *dev); 851 void mlx4_stop_catas_poll(struct mlx4_dev *dev); 852 void mlx4_catas_init(void); 853 int mlx4_restart_one(struct pci_dev *pdev); 854 int mlx4_register_device(struct mlx4_dev *dev); 855 void mlx4_unregister_device(struct mlx4_dev *dev); 856 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type, int port); 857 858 struct mlx4_dev_cap; 859 struct mlx4_init_hca_param; 860 861 u64 mlx4_make_profile(struct mlx4_dev *dev, 862 struct mlx4_profile *request, 863 struct mlx4_dev_cap *dev_cap, 864 struct mlx4_init_hca_param *init_hca); 865 void mlx4_master_comm_channel(struct work_struct *work); 866 void mlx4_gen_slave_eqe(struct work_struct *work); 867 void mlx4_master_handle_slave_flr(struct work_struct *work); 868 869 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave, 870 struct mlx4_vhcr *vhcr, 871 struct mlx4_cmd_mailbox *inbox, 872 struct mlx4_cmd_mailbox *outbox, 873 struct mlx4_cmd_info *cmd); 874 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave, 875 struct mlx4_vhcr *vhcr, 876 struct mlx4_cmd_mailbox *inbox, 877 struct mlx4_cmd_mailbox *outbox, 878 struct mlx4_cmd_info *cmd); 879 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave, 880 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox, 881 struct mlx4_cmd_mailbox *outbox, 882 struct mlx4_cmd_info *cmd); 883 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave, 884 struct mlx4_vhcr *vhcr, 885 struct mlx4_cmd_mailbox *inbox, 886 struct mlx4_cmd_mailbox *outbox, 887 struct mlx4_cmd_info *cmd); 888 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave, 889 struct mlx4_vhcr *vhcr, 890 struct mlx4_cmd_mailbox *inbox, 891 struct mlx4_cmd_mailbox *outbox, 892 struct mlx4_cmd_info *cmd); 893 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave, 894 struct mlx4_vhcr *vhcr, 895 struct mlx4_cmd_mailbox *inbox, 896 struct mlx4_cmd_mailbox *outbox, 897 struct mlx4_cmd_info *cmd); 898 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave, 899 struct mlx4_vhcr *vhcr, 900 struct mlx4_cmd_mailbox *inbox, 901 struct mlx4_cmd_mailbox *outbox, 902 struct mlx4_cmd_info *cmd); 903 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave, 904 struct mlx4_vhcr *vhcr, 905 struct mlx4_cmd_mailbox *inbox, 906 struct mlx4_cmd_mailbox *outbox, 907 struct mlx4_cmd_info *cmd); 908 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave, 909 struct mlx4_vhcr *vhcr, 910 struct mlx4_cmd_mailbox *inbox, 911 struct mlx4_cmd_mailbox *outbox, 912 struct mlx4_cmd_info *cmd); 913 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave, 914 struct mlx4_vhcr *vhcr, 915 struct mlx4_cmd_mailbox *inbox, 916 struct mlx4_cmd_mailbox *outbox, 917 struct mlx4_cmd_info *cmd); 918 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave, 919 struct mlx4_vhcr *vhcr, 920 struct mlx4_cmd_mailbox *inbox, 921 struct mlx4_cmd_mailbox *outbox, 922 struct mlx4_cmd_info *cmd); 923 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave, 924 struct mlx4_vhcr *vhcr, 925 struct mlx4_cmd_mailbox *inbox, 926 struct mlx4_cmd_mailbox *outbox, 927 struct mlx4_cmd_info *cmd); 928 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave, 929 struct mlx4_vhcr *vhcr, 930 struct mlx4_cmd_mailbox *inbox, 931 struct mlx4_cmd_mailbox *outbox, 932 struct mlx4_cmd_info *cmd); 933 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave, 934 struct mlx4_vhcr *vhcr, 935 struct mlx4_cmd_mailbox *inbox, 936 struct mlx4_cmd_mailbox *outbox, 937 struct mlx4_cmd_info *cmd); 938 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave, 939 struct mlx4_vhcr *vhcr, 940 struct mlx4_cmd_mailbox *inbox, 941 struct mlx4_cmd_mailbox *outbox, 942 struct mlx4_cmd_info *cmd); 943 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave, 944 struct mlx4_vhcr *vhcr, 945 struct mlx4_cmd_mailbox *inbox, 946 struct mlx4_cmd_mailbox *outbox, 947 struct mlx4_cmd_info *cmd); 948 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave, 949 struct mlx4_vhcr *vhcr, 950 struct mlx4_cmd_mailbox *inbox, 951 struct mlx4_cmd_mailbox *outbox, 952 struct mlx4_cmd_info *cmd); 953 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave, 954 struct mlx4_vhcr *vhcr, 955 struct mlx4_cmd_mailbox *inbox, 956 struct mlx4_cmd_mailbox *outbox, 957 struct mlx4_cmd_info *cmd); 958 959 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe); 960 961 int mlx4_cmd_init(struct mlx4_dev *dev); 962 void mlx4_cmd_cleanup(struct mlx4_dev *dev); 963 int mlx4_multi_func_init(struct mlx4_dev *dev); 964 void mlx4_multi_func_cleanup(struct mlx4_dev *dev); 965 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param); 966 int mlx4_cmd_use_events(struct mlx4_dev *dev); 967 void mlx4_cmd_use_polling(struct mlx4_dev *dev); 968 969 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param, 970 unsigned long timeout); 971 972 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn); 973 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type); 974 975 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type); 976 977 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type); 978 979 void mlx4_handle_catas_err(struct mlx4_dev *dev); 980 981 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port, 982 enum mlx4_port_type *type); 983 void mlx4_do_sense_ports(struct mlx4_dev *dev, 984 enum mlx4_port_type *stype, 985 enum mlx4_port_type *defaults); 986 void mlx4_start_sense(struct mlx4_dev *dev); 987 void mlx4_stop_sense(struct mlx4_dev *dev); 988 void mlx4_sense_init(struct mlx4_dev *dev); 989 int mlx4_check_port_params(struct mlx4_dev *dev, 990 enum mlx4_port_type *port_type); 991 int mlx4_change_port_types(struct mlx4_dev *dev, 992 enum mlx4_port_type *port_types); 993 994 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table); 995 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table); 996 997 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port); 998 /* resource tracker functions*/ 999 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev, 1000 enum mlx4_resource resource_type, 1001 int resource_id, int *slave); 1002 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id); 1003 int mlx4_init_resource_tracker(struct mlx4_dev *dev); 1004 1005 void mlx4_free_resource_tracker(struct mlx4_dev *dev); 1006 1007 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave, 1008 struct mlx4_vhcr *vhcr, 1009 struct mlx4_cmd_mailbox *inbox, 1010 struct mlx4_cmd_mailbox *outbox, 1011 struct mlx4_cmd_info *cmd); 1012 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave, 1013 struct mlx4_vhcr *vhcr, 1014 struct mlx4_cmd_mailbox *inbox, 1015 struct mlx4_cmd_mailbox *outbox, 1016 struct mlx4_cmd_info *cmd); 1017 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave, 1018 struct mlx4_vhcr *vhcr, 1019 struct mlx4_cmd_mailbox *inbox, 1020 struct mlx4_cmd_mailbox *outbox, 1021 struct mlx4_cmd_info *cmd); 1022 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave, 1023 struct mlx4_vhcr *vhcr, 1024 struct mlx4_cmd_mailbox *inbox, 1025 struct mlx4_cmd_mailbox *outbox, 1026 struct mlx4_cmd_info *cmd); 1027 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps); 1028 int mlx4_check_ext_port_caps(struct mlx4_dev *dev, u8 port); 1029 1030 1031 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave, 1032 struct mlx4_vhcr *vhcr, 1033 struct mlx4_cmd_mailbox *inbox, 1034 struct mlx4_cmd_mailbox *outbox, 1035 struct mlx4_cmd_info *cmd); 1036 1037 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave, 1038 struct mlx4_vhcr *vhcr, 1039 struct mlx4_cmd_mailbox *inbox, 1040 struct mlx4_cmd_mailbox *outbox, 1041 struct mlx4_cmd_info *cmd); 1042 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1043 enum mlx4_protocol prot, enum mlx4_steer_type steer); 1044 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1045 int block_mcast_loopback, enum mlx4_protocol prot, 1046 enum mlx4_steer_type steer); 1047 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave, 1048 struct mlx4_vhcr *vhcr, 1049 struct mlx4_cmd_mailbox *inbox, 1050 struct mlx4_cmd_mailbox *outbox, 1051 struct mlx4_cmd_info *cmd); 1052 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave, 1053 struct mlx4_vhcr *vhcr, 1054 struct mlx4_cmd_mailbox *inbox, 1055 struct mlx4_cmd_mailbox *outbox, 1056 struct mlx4_cmd_info *cmd); 1057 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function, 1058 int port, void *buf); 1059 int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod, 1060 struct mlx4_cmd_mailbox *outbox); 1061 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave, 1062 struct mlx4_vhcr *vhcr, 1063 struct mlx4_cmd_mailbox *inbox, 1064 struct mlx4_cmd_mailbox *outbox, 1065 struct mlx4_cmd_info *cmd); 1066 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave, 1067 struct mlx4_vhcr *vhcr, 1068 struct mlx4_cmd_mailbox *inbox, 1069 struct mlx4_cmd_mailbox *outbox, 1070 struct mlx4_cmd_info *cmd); 1071 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave, 1072 struct mlx4_vhcr *vhcr, 1073 struct mlx4_cmd_mailbox *inbox, 1074 struct mlx4_cmd_mailbox *outbox, 1075 struct mlx4_cmd_info *cmd); 1076 1077 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev); 1078 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev); 1079 1080 static inline void set_param_l(u64 *arg, u32 val) 1081 { 1082 *((u32 *)arg) = val; 1083 } 1084 1085 static inline void set_param_h(u64 *arg, u32 val) 1086 { 1087 *arg = (*arg & 0xffffffff) | ((u64) val << 32); 1088 } 1089 1090 static inline u32 get_param_l(u64 *arg) 1091 { 1092 return (u32) (*arg & 0xffffffff); 1093 } 1094 1095 static inline u32 get_param_h(u64 *arg) 1096 { 1097 return (u32)(*arg >> 32); 1098 } 1099 1100 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev) 1101 { 1102 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock; 1103 } 1104 1105 #define NOT_MASKED_PD_BITS 17 1106 1107 #endif /* MLX4_H */ 1108