1 /* 2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #include <linux/string.h> 35 #include <linux/etherdevice.h> 36 37 #include <linux/mlx4/cmd.h> 38 #include <linux/export.h> 39 40 #include "mlx4.h" 41 42 static const u8 zero_gid[16]; /* automatically initialized to 0 */ 43 44 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev) 45 { 46 return 1 << dev->oper_log_mgm_entry_size; 47 } 48 49 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev) 50 { 51 return 4 * (mlx4_get_mgm_entry_size(dev) / 16 - 2); 52 } 53 54 static int mlx4_QP_FLOW_STEERING_ATTACH(struct mlx4_dev *dev, 55 struct mlx4_cmd_mailbox *mailbox, 56 u32 size, 57 u64 *reg_id) 58 { 59 u64 imm; 60 int err = 0; 61 62 err = mlx4_cmd_imm(dev, mailbox->dma, &imm, size, 0, 63 MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A, 64 MLX4_CMD_NATIVE); 65 if (err) 66 return err; 67 *reg_id = imm; 68 69 return err; 70 } 71 72 static int mlx4_QP_FLOW_STEERING_DETACH(struct mlx4_dev *dev, u64 regid) 73 { 74 int err = 0; 75 76 err = mlx4_cmd(dev, regid, 0, 0, 77 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A, 78 MLX4_CMD_NATIVE); 79 80 return err; 81 } 82 83 static int mlx4_READ_ENTRY(struct mlx4_dev *dev, int index, 84 struct mlx4_cmd_mailbox *mailbox) 85 { 86 return mlx4_cmd_box(dev, 0, mailbox->dma, index, 0, MLX4_CMD_READ_MCG, 87 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 88 } 89 90 static int mlx4_WRITE_ENTRY(struct mlx4_dev *dev, int index, 91 struct mlx4_cmd_mailbox *mailbox) 92 { 93 return mlx4_cmd(dev, mailbox->dma, index, 0, MLX4_CMD_WRITE_MCG, 94 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 95 } 96 97 static int mlx4_WRITE_PROMISC(struct mlx4_dev *dev, u8 port, u8 steer, 98 struct mlx4_cmd_mailbox *mailbox) 99 { 100 u32 in_mod; 101 102 in_mod = (u32) port << 16 | steer << 1; 103 return mlx4_cmd(dev, mailbox->dma, in_mod, 0x1, 104 MLX4_CMD_WRITE_MCG, MLX4_CMD_TIME_CLASS_A, 105 MLX4_CMD_NATIVE); 106 } 107 108 static int mlx4_GID_HASH(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, 109 u16 *hash, u8 op_mod) 110 { 111 u64 imm; 112 int err; 113 114 err = mlx4_cmd_imm(dev, mailbox->dma, &imm, 0, op_mod, 115 MLX4_CMD_MGID_HASH, MLX4_CMD_TIME_CLASS_A, 116 MLX4_CMD_NATIVE); 117 118 if (!err) 119 *hash = imm; 120 121 return err; 122 } 123 124 static struct mlx4_promisc_qp *get_promisc_qp(struct mlx4_dev *dev, u8 port, 125 enum mlx4_steer_type steer, 126 u32 qpn) 127 { 128 struct mlx4_steer *s_steer = &mlx4_priv(dev)->steer[port - 1]; 129 struct mlx4_promisc_qp *pqp; 130 131 list_for_each_entry(pqp, &s_steer->promisc_qps[steer], list) { 132 if (pqp->qpn == qpn) 133 return pqp; 134 } 135 /* not found */ 136 return NULL; 137 } 138 139 /* 140 * Add new entry to steering data structure. 141 * All promisc QPs should be added as well 142 */ 143 static int new_steering_entry(struct mlx4_dev *dev, u8 port, 144 enum mlx4_steer_type steer, 145 unsigned int index, u32 qpn) 146 { 147 struct mlx4_steer *s_steer; 148 struct mlx4_cmd_mailbox *mailbox; 149 struct mlx4_mgm *mgm; 150 u32 members_count; 151 struct mlx4_steer_index *new_entry; 152 struct mlx4_promisc_qp *pqp; 153 struct mlx4_promisc_qp *dqp = NULL; 154 u32 prot; 155 int err; 156 157 s_steer = &mlx4_priv(dev)->steer[port - 1]; 158 new_entry = kzalloc(sizeof *new_entry, GFP_KERNEL); 159 if (!new_entry) 160 return -ENOMEM; 161 162 INIT_LIST_HEAD(&new_entry->duplicates); 163 new_entry->index = index; 164 list_add_tail(&new_entry->list, &s_steer->steer_entries[steer]); 165 166 /* If the given qpn is also a promisc qp, 167 * it should be inserted to duplicates list 168 */ 169 pqp = get_promisc_qp(dev, port, steer, qpn); 170 if (pqp) { 171 dqp = kmalloc(sizeof *dqp, GFP_KERNEL); 172 if (!dqp) { 173 err = -ENOMEM; 174 goto out_alloc; 175 } 176 dqp->qpn = qpn; 177 list_add_tail(&dqp->list, &new_entry->duplicates); 178 } 179 180 /* if no promisc qps for this vep, we are done */ 181 if (list_empty(&s_steer->promisc_qps[steer])) 182 return 0; 183 184 /* now need to add all the promisc qps to the new 185 * steering entry, as they should also receive the packets 186 * destined to this address */ 187 mailbox = mlx4_alloc_cmd_mailbox(dev); 188 if (IS_ERR(mailbox)) { 189 err = -ENOMEM; 190 goto out_alloc; 191 } 192 mgm = mailbox->buf; 193 194 err = mlx4_READ_ENTRY(dev, index, mailbox); 195 if (err) 196 goto out_mailbox; 197 198 members_count = be32_to_cpu(mgm->members_count) & 0xffffff; 199 prot = be32_to_cpu(mgm->members_count) >> 30; 200 list_for_each_entry(pqp, &s_steer->promisc_qps[steer], list) { 201 /* don't add already existing qpn */ 202 if (pqp->qpn == qpn) 203 continue; 204 if (members_count == dev->caps.num_qp_per_mgm) { 205 /* out of space */ 206 err = -ENOMEM; 207 goto out_mailbox; 208 } 209 210 /* add the qpn */ 211 mgm->qp[members_count++] = cpu_to_be32(pqp->qpn & MGM_QPN_MASK); 212 } 213 /* update the qps count and update the entry with all the promisc qps*/ 214 mgm->members_count = cpu_to_be32(members_count | (prot << 30)); 215 err = mlx4_WRITE_ENTRY(dev, index, mailbox); 216 217 out_mailbox: 218 mlx4_free_cmd_mailbox(dev, mailbox); 219 if (!err) 220 return 0; 221 out_alloc: 222 if (dqp) { 223 list_del(&dqp->list); 224 kfree(dqp); 225 } 226 list_del(&new_entry->list); 227 kfree(new_entry); 228 return err; 229 } 230 231 /* update the data structures with existing steering entry */ 232 static int existing_steering_entry(struct mlx4_dev *dev, u8 port, 233 enum mlx4_steer_type steer, 234 unsigned int index, u32 qpn) 235 { 236 struct mlx4_steer *s_steer; 237 struct mlx4_steer_index *tmp_entry, *entry = NULL; 238 struct mlx4_promisc_qp *pqp; 239 struct mlx4_promisc_qp *dqp; 240 241 s_steer = &mlx4_priv(dev)->steer[port - 1]; 242 243 pqp = get_promisc_qp(dev, port, steer, qpn); 244 if (!pqp) 245 return 0; /* nothing to do */ 246 247 list_for_each_entry(tmp_entry, &s_steer->steer_entries[steer], list) { 248 if (tmp_entry->index == index) { 249 entry = tmp_entry; 250 break; 251 } 252 } 253 if (unlikely(!entry)) { 254 mlx4_warn(dev, "Steering entry at index %x is not registered\n", index); 255 return -EINVAL; 256 } 257 258 /* the given qpn is listed as a promisc qpn 259 * we need to add it as a duplicate to this entry 260 * for future references */ 261 list_for_each_entry(dqp, &entry->duplicates, list) { 262 if (qpn == pqp->qpn) 263 return 0; /* qp is already duplicated */ 264 } 265 266 /* add the qp as a duplicate on this index */ 267 dqp = kmalloc(sizeof *dqp, GFP_KERNEL); 268 if (!dqp) 269 return -ENOMEM; 270 dqp->qpn = qpn; 271 list_add_tail(&dqp->list, &entry->duplicates); 272 273 return 0; 274 } 275 276 /* Check whether a qpn is a duplicate on steering entry 277 * If so, it should not be removed from mgm */ 278 static bool check_duplicate_entry(struct mlx4_dev *dev, u8 port, 279 enum mlx4_steer_type steer, 280 unsigned int index, u32 qpn) 281 { 282 struct mlx4_steer *s_steer; 283 struct mlx4_steer_index *tmp_entry, *entry = NULL; 284 struct mlx4_promisc_qp *dqp, *tmp_dqp; 285 286 s_steer = &mlx4_priv(dev)->steer[port - 1]; 287 288 /* if qp is not promisc, it cannot be duplicated */ 289 if (!get_promisc_qp(dev, port, steer, qpn)) 290 return false; 291 292 /* The qp is promisc qp so it is a duplicate on this index 293 * Find the index entry, and remove the duplicate */ 294 list_for_each_entry(tmp_entry, &s_steer->steer_entries[steer], list) { 295 if (tmp_entry->index == index) { 296 entry = tmp_entry; 297 break; 298 } 299 } 300 if (unlikely(!entry)) { 301 mlx4_warn(dev, "Steering entry for index %x is not registered\n", index); 302 return false; 303 } 304 list_for_each_entry_safe(dqp, tmp_dqp, &entry->duplicates, list) { 305 if (dqp->qpn == qpn) { 306 list_del(&dqp->list); 307 kfree(dqp); 308 } 309 } 310 return true; 311 } 312 313 /* I a steering entry contains only promisc QPs, it can be removed. */ 314 static bool can_remove_steering_entry(struct mlx4_dev *dev, u8 port, 315 enum mlx4_steer_type steer, 316 unsigned int index, u32 tqpn) 317 { 318 struct mlx4_steer *s_steer; 319 struct mlx4_cmd_mailbox *mailbox; 320 struct mlx4_mgm *mgm; 321 struct mlx4_steer_index *entry = NULL, *tmp_entry; 322 u32 qpn; 323 u32 members_count; 324 bool ret = false; 325 int i; 326 327 s_steer = &mlx4_priv(dev)->steer[port - 1]; 328 329 mailbox = mlx4_alloc_cmd_mailbox(dev); 330 if (IS_ERR(mailbox)) 331 return false; 332 mgm = mailbox->buf; 333 334 if (mlx4_READ_ENTRY(dev, index, mailbox)) 335 goto out; 336 members_count = be32_to_cpu(mgm->members_count) & 0xffffff; 337 for (i = 0; i < members_count; i++) { 338 qpn = be32_to_cpu(mgm->qp[i]) & MGM_QPN_MASK; 339 if (!get_promisc_qp(dev, port, steer, qpn) && qpn != tqpn) { 340 /* the qp is not promisc, the entry can't be removed */ 341 goto out; 342 } 343 } 344 /* All the qps currently registered for this entry are promiscuous, 345 * Checking for duplicates */ 346 ret = true; 347 list_for_each_entry_safe(entry, tmp_entry, &s_steer->steer_entries[steer], list) { 348 if (entry->index == index) { 349 if (list_empty(&entry->duplicates)) { 350 list_del(&entry->list); 351 kfree(entry); 352 } else { 353 /* This entry contains duplicates so it shouldn't be removed */ 354 ret = false; 355 goto out; 356 } 357 } 358 } 359 360 out: 361 mlx4_free_cmd_mailbox(dev, mailbox); 362 return ret; 363 } 364 365 static int add_promisc_qp(struct mlx4_dev *dev, u8 port, 366 enum mlx4_steer_type steer, u32 qpn) 367 { 368 struct mlx4_steer *s_steer; 369 struct mlx4_cmd_mailbox *mailbox; 370 struct mlx4_mgm *mgm; 371 struct mlx4_steer_index *entry; 372 struct mlx4_promisc_qp *pqp; 373 struct mlx4_promisc_qp *dqp; 374 u32 members_count; 375 u32 prot; 376 int i; 377 bool found; 378 int err; 379 struct mlx4_priv *priv = mlx4_priv(dev); 380 381 s_steer = &mlx4_priv(dev)->steer[port - 1]; 382 383 mutex_lock(&priv->mcg_table.mutex); 384 385 if (get_promisc_qp(dev, port, steer, qpn)) { 386 err = 0; /* Noting to do, already exists */ 387 goto out_mutex; 388 } 389 390 pqp = kmalloc(sizeof *pqp, GFP_KERNEL); 391 if (!pqp) { 392 err = -ENOMEM; 393 goto out_mutex; 394 } 395 pqp->qpn = qpn; 396 397 mailbox = mlx4_alloc_cmd_mailbox(dev); 398 if (IS_ERR(mailbox)) { 399 err = -ENOMEM; 400 goto out_alloc; 401 } 402 mgm = mailbox->buf; 403 404 /* the promisc qp needs to be added for each one of the steering 405 * entries, if it already exists, needs to be added as a duplicate 406 * for this entry */ 407 list_for_each_entry(entry, &s_steer->steer_entries[steer], list) { 408 err = mlx4_READ_ENTRY(dev, entry->index, mailbox); 409 if (err) 410 goto out_mailbox; 411 412 members_count = be32_to_cpu(mgm->members_count) & 0xffffff; 413 prot = be32_to_cpu(mgm->members_count) >> 30; 414 found = false; 415 for (i = 0; i < members_count; i++) { 416 if ((be32_to_cpu(mgm->qp[i]) & MGM_QPN_MASK) == qpn) { 417 /* Entry already exists, add to duplicates */ 418 dqp = kmalloc(sizeof *dqp, GFP_KERNEL); 419 if (!dqp) { 420 err = -ENOMEM; 421 goto out_mailbox; 422 } 423 dqp->qpn = qpn; 424 list_add_tail(&dqp->list, &entry->duplicates); 425 found = true; 426 } 427 } 428 if (!found) { 429 /* Need to add the qpn to mgm */ 430 if (members_count == dev->caps.num_qp_per_mgm) { 431 /* entry is full */ 432 err = -ENOMEM; 433 goto out_mailbox; 434 } 435 mgm->qp[members_count++] = cpu_to_be32(qpn & MGM_QPN_MASK); 436 mgm->members_count = cpu_to_be32(members_count | (prot << 30)); 437 err = mlx4_WRITE_ENTRY(dev, entry->index, mailbox); 438 if (err) 439 goto out_mailbox; 440 } 441 } 442 443 /* add the new qpn to list of promisc qps */ 444 list_add_tail(&pqp->list, &s_steer->promisc_qps[steer]); 445 /* now need to add all the promisc qps to default entry */ 446 memset(mgm, 0, sizeof *mgm); 447 members_count = 0; 448 list_for_each_entry(dqp, &s_steer->promisc_qps[steer], list) 449 mgm->qp[members_count++] = cpu_to_be32(dqp->qpn & MGM_QPN_MASK); 450 mgm->members_count = cpu_to_be32(members_count | MLX4_PROT_ETH << 30); 451 452 err = mlx4_WRITE_PROMISC(dev, port, steer, mailbox); 453 if (err) 454 goto out_list; 455 456 mlx4_free_cmd_mailbox(dev, mailbox); 457 mutex_unlock(&priv->mcg_table.mutex); 458 return 0; 459 460 out_list: 461 list_del(&pqp->list); 462 out_mailbox: 463 mlx4_free_cmd_mailbox(dev, mailbox); 464 out_alloc: 465 kfree(pqp); 466 out_mutex: 467 mutex_unlock(&priv->mcg_table.mutex); 468 return err; 469 } 470 471 static int remove_promisc_qp(struct mlx4_dev *dev, u8 port, 472 enum mlx4_steer_type steer, u32 qpn) 473 { 474 struct mlx4_priv *priv = mlx4_priv(dev); 475 struct mlx4_steer *s_steer; 476 struct mlx4_cmd_mailbox *mailbox; 477 struct mlx4_mgm *mgm; 478 struct mlx4_steer_index *entry; 479 struct mlx4_promisc_qp *pqp; 480 struct mlx4_promisc_qp *dqp; 481 u32 members_count; 482 bool found; 483 bool back_to_list = false; 484 int loc, i; 485 int err; 486 487 s_steer = &mlx4_priv(dev)->steer[port - 1]; 488 mutex_lock(&priv->mcg_table.mutex); 489 490 pqp = get_promisc_qp(dev, port, steer, qpn); 491 if (unlikely(!pqp)) { 492 mlx4_warn(dev, "QP %x is not promiscuous QP\n", qpn); 493 /* nothing to do */ 494 err = 0; 495 goto out_mutex; 496 } 497 498 /*remove from list of promisc qps */ 499 list_del(&pqp->list); 500 501 /* set the default entry not to include the removed one */ 502 mailbox = mlx4_alloc_cmd_mailbox(dev); 503 if (IS_ERR(mailbox)) { 504 err = -ENOMEM; 505 back_to_list = true; 506 goto out_list; 507 } 508 mgm = mailbox->buf; 509 members_count = 0; 510 list_for_each_entry(dqp, &s_steer->promisc_qps[steer], list) 511 mgm->qp[members_count++] = cpu_to_be32(dqp->qpn & MGM_QPN_MASK); 512 mgm->members_count = cpu_to_be32(members_count | MLX4_PROT_ETH << 30); 513 514 err = mlx4_WRITE_PROMISC(dev, port, steer, mailbox); 515 if (err) 516 goto out_mailbox; 517 518 /* remove the qp from all the steering entries*/ 519 list_for_each_entry(entry, &s_steer->steer_entries[steer], list) { 520 found = false; 521 list_for_each_entry(dqp, &entry->duplicates, list) { 522 if (dqp->qpn == qpn) { 523 found = true; 524 break; 525 } 526 } 527 if (found) { 528 /* a duplicate, no need to change the mgm, 529 * only update the duplicates list */ 530 list_del(&dqp->list); 531 kfree(dqp); 532 } else { 533 err = mlx4_READ_ENTRY(dev, entry->index, mailbox); 534 if (err) 535 goto out_mailbox; 536 members_count = be32_to_cpu(mgm->members_count) & 0xffffff; 537 for (loc = -1, i = 0; i < members_count; ++i) 538 if ((be32_to_cpu(mgm->qp[i]) & MGM_QPN_MASK) == qpn) 539 loc = i; 540 541 mgm->members_count = cpu_to_be32(--members_count | 542 (MLX4_PROT_ETH << 30)); 543 mgm->qp[loc] = mgm->qp[i - 1]; 544 mgm->qp[i - 1] = 0; 545 546 err = mlx4_WRITE_ENTRY(dev, entry->index, mailbox); 547 if (err) 548 goto out_mailbox; 549 } 550 551 } 552 553 out_mailbox: 554 mlx4_free_cmd_mailbox(dev, mailbox); 555 out_list: 556 if (back_to_list) 557 list_add_tail(&pqp->list, &s_steer->promisc_qps[steer]); 558 else 559 kfree(pqp); 560 out_mutex: 561 mutex_unlock(&priv->mcg_table.mutex); 562 return err; 563 } 564 565 /* 566 * Caller must hold MCG table semaphore. gid and mgm parameters must 567 * be properly aligned for command interface. 568 * 569 * Returns 0 unless a firmware command error occurs. 570 * 571 * If GID is found in MGM or MGM is empty, *index = *hash, *prev = -1 572 * and *mgm holds MGM entry. 573 * 574 * if GID is found in AMGM, *index = index in AMGM, *prev = index of 575 * previous entry in hash chain and *mgm holds AMGM entry. 576 * 577 * If no AMGM exists for given gid, *index = -1, *prev = index of last 578 * entry in hash chain and *mgm holds end of hash chain. 579 */ 580 static int find_entry(struct mlx4_dev *dev, u8 port, 581 u8 *gid, enum mlx4_protocol prot, 582 struct mlx4_cmd_mailbox *mgm_mailbox, 583 int *prev, int *index) 584 { 585 struct mlx4_cmd_mailbox *mailbox; 586 struct mlx4_mgm *mgm = mgm_mailbox->buf; 587 u8 *mgid; 588 int err; 589 u16 hash; 590 u8 op_mod = (prot == MLX4_PROT_ETH) ? 591 !!(dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) : 0; 592 593 mailbox = mlx4_alloc_cmd_mailbox(dev); 594 if (IS_ERR(mailbox)) 595 return -ENOMEM; 596 mgid = mailbox->buf; 597 598 memcpy(mgid, gid, 16); 599 600 err = mlx4_GID_HASH(dev, mailbox, &hash, op_mod); 601 mlx4_free_cmd_mailbox(dev, mailbox); 602 if (err) 603 return err; 604 605 if (0) 606 mlx4_dbg(dev, "Hash for %pI6 is %04x\n", gid, hash); 607 608 *index = hash; 609 *prev = -1; 610 611 do { 612 err = mlx4_READ_ENTRY(dev, *index, mgm_mailbox); 613 if (err) 614 return err; 615 616 if (!(be32_to_cpu(mgm->members_count) & 0xffffff)) { 617 if (*index != hash) { 618 mlx4_err(dev, "Found zero MGID in AMGM.\n"); 619 err = -EINVAL; 620 } 621 return err; 622 } 623 624 if (!memcmp(mgm->gid, gid, 16) && 625 be32_to_cpu(mgm->members_count) >> 30 == prot) 626 return err; 627 628 *prev = *index; 629 *index = be32_to_cpu(mgm->next_gid_index) >> 6; 630 } while (*index); 631 632 *index = -1; 633 return err; 634 } 635 636 static const u8 __promisc_mode[] = { 637 [MLX4_FS_REGULAR] = 0x0, 638 [MLX4_FS_ALL_DEFAULT] = 0x1, 639 [MLX4_FS_MC_DEFAULT] = 0x3, 640 [MLX4_FS_UC_SNIFFER] = 0x4, 641 [MLX4_FS_MC_SNIFFER] = 0x5, 642 }; 643 644 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev, 645 enum mlx4_net_trans_promisc_mode flow_type) 646 { 647 if (flow_type >= MLX4_FS_MODE_NUM) { 648 mlx4_err(dev, "Invalid flow type. type = %d\n", flow_type); 649 return -EINVAL; 650 } 651 return __promisc_mode[flow_type]; 652 } 653 EXPORT_SYMBOL_GPL(mlx4_map_sw_to_hw_steering_mode); 654 655 static void trans_rule_ctrl_to_hw(struct mlx4_net_trans_rule *ctrl, 656 struct mlx4_net_trans_rule_hw_ctrl *hw) 657 { 658 u8 flags = 0; 659 660 flags = ctrl->queue_mode == MLX4_NET_TRANS_Q_LIFO ? 1 : 0; 661 flags |= ctrl->exclusive ? (1 << 2) : 0; 662 flags |= ctrl->allow_loopback ? (1 << 3) : 0; 663 664 hw->flags = flags; 665 hw->type = __promisc_mode[ctrl->promisc_mode]; 666 hw->prio = cpu_to_be16(ctrl->priority); 667 hw->port = ctrl->port; 668 hw->qpn = cpu_to_be32(ctrl->qpn); 669 } 670 671 const u16 __sw_id_hw[] = { 672 [MLX4_NET_TRANS_RULE_ID_ETH] = 0xE001, 673 [MLX4_NET_TRANS_RULE_ID_IB] = 0xE005, 674 [MLX4_NET_TRANS_RULE_ID_IPV6] = 0xE003, 675 [MLX4_NET_TRANS_RULE_ID_IPV4] = 0xE002, 676 [MLX4_NET_TRANS_RULE_ID_TCP] = 0xE004, 677 [MLX4_NET_TRANS_RULE_ID_UDP] = 0xE006 678 }; 679 680 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev, 681 enum mlx4_net_trans_rule_id id) 682 { 683 if (id >= MLX4_NET_TRANS_RULE_NUM) { 684 mlx4_err(dev, "Invalid network rule id. id = %d\n", id); 685 return -EINVAL; 686 } 687 return __sw_id_hw[id]; 688 } 689 EXPORT_SYMBOL_GPL(mlx4_map_sw_to_hw_steering_id); 690 691 static const int __rule_hw_sz[] = { 692 [MLX4_NET_TRANS_RULE_ID_ETH] = 693 sizeof(struct mlx4_net_trans_rule_hw_eth), 694 [MLX4_NET_TRANS_RULE_ID_IB] = 695 sizeof(struct mlx4_net_trans_rule_hw_ib), 696 [MLX4_NET_TRANS_RULE_ID_IPV6] = 0, 697 [MLX4_NET_TRANS_RULE_ID_IPV4] = 698 sizeof(struct mlx4_net_trans_rule_hw_ipv4), 699 [MLX4_NET_TRANS_RULE_ID_TCP] = 700 sizeof(struct mlx4_net_trans_rule_hw_tcp_udp), 701 [MLX4_NET_TRANS_RULE_ID_UDP] = 702 sizeof(struct mlx4_net_trans_rule_hw_tcp_udp) 703 }; 704 705 int mlx4_hw_rule_sz(struct mlx4_dev *dev, 706 enum mlx4_net_trans_rule_id id) 707 { 708 if (id >= MLX4_NET_TRANS_RULE_NUM) { 709 mlx4_err(dev, "Invalid network rule id. id = %d\n", id); 710 return -EINVAL; 711 } 712 713 return __rule_hw_sz[id]; 714 } 715 EXPORT_SYMBOL_GPL(mlx4_hw_rule_sz); 716 717 static int parse_trans_rule(struct mlx4_dev *dev, struct mlx4_spec_list *spec, 718 struct _rule_hw *rule_hw) 719 { 720 if (mlx4_hw_rule_sz(dev, spec->id) < 0) 721 return -EINVAL; 722 memset(rule_hw, 0, mlx4_hw_rule_sz(dev, spec->id)); 723 rule_hw->id = cpu_to_be16(__sw_id_hw[spec->id]); 724 rule_hw->size = mlx4_hw_rule_sz(dev, spec->id) >> 2; 725 726 switch (spec->id) { 727 case MLX4_NET_TRANS_RULE_ID_ETH: 728 memcpy(rule_hw->eth.dst_mac, spec->eth.dst_mac, ETH_ALEN); 729 memcpy(rule_hw->eth.dst_mac_msk, spec->eth.dst_mac_msk, 730 ETH_ALEN); 731 memcpy(rule_hw->eth.src_mac, spec->eth.src_mac, ETH_ALEN); 732 memcpy(rule_hw->eth.src_mac_msk, spec->eth.src_mac_msk, 733 ETH_ALEN); 734 if (spec->eth.ether_type_enable) { 735 rule_hw->eth.ether_type_enable = 1; 736 rule_hw->eth.ether_type = spec->eth.ether_type; 737 } 738 rule_hw->eth.vlan_tag = spec->eth.vlan_id; 739 rule_hw->eth.vlan_tag_msk = spec->eth.vlan_id_msk; 740 break; 741 742 case MLX4_NET_TRANS_RULE_ID_IB: 743 rule_hw->ib.l3_qpn = spec->ib.l3_qpn; 744 rule_hw->ib.qpn_mask = spec->ib.qpn_msk; 745 memcpy(&rule_hw->ib.dst_gid, &spec->ib.dst_gid, 16); 746 memcpy(&rule_hw->ib.dst_gid_msk, &spec->ib.dst_gid_msk, 16); 747 break; 748 749 case MLX4_NET_TRANS_RULE_ID_IPV6: 750 return -EOPNOTSUPP; 751 752 case MLX4_NET_TRANS_RULE_ID_IPV4: 753 rule_hw->ipv4.src_ip = spec->ipv4.src_ip; 754 rule_hw->ipv4.src_ip_msk = spec->ipv4.src_ip_msk; 755 rule_hw->ipv4.dst_ip = spec->ipv4.dst_ip; 756 rule_hw->ipv4.dst_ip_msk = spec->ipv4.dst_ip_msk; 757 break; 758 759 case MLX4_NET_TRANS_RULE_ID_TCP: 760 case MLX4_NET_TRANS_RULE_ID_UDP: 761 rule_hw->tcp_udp.dst_port = spec->tcp_udp.dst_port; 762 rule_hw->tcp_udp.dst_port_msk = spec->tcp_udp.dst_port_msk; 763 rule_hw->tcp_udp.src_port = spec->tcp_udp.src_port; 764 rule_hw->tcp_udp.src_port_msk = spec->tcp_udp.src_port_msk; 765 break; 766 767 default: 768 return -EINVAL; 769 } 770 771 return __rule_hw_sz[spec->id]; 772 } 773 774 static void mlx4_err_rule(struct mlx4_dev *dev, char *str, 775 struct mlx4_net_trans_rule *rule) 776 { 777 #define BUF_SIZE 256 778 struct mlx4_spec_list *cur; 779 char buf[BUF_SIZE]; 780 int len = 0; 781 782 mlx4_err(dev, "%s", str); 783 len += snprintf(buf + len, BUF_SIZE - len, 784 "port = %d prio = 0x%x qp = 0x%x ", 785 rule->port, rule->priority, rule->qpn); 786 787 list_for_each_entry(cur, &rule->list, list) { 788 switch (cur->id) { 789 case MLX4_NET_TRANS_RULE_ID_ETH: 790 len += snprintf(buf + len, BUF_SIZE - len, 791 "dmac = %pM ", &cur->eth.dst_mac); 792 if (cur->eth.ether_type) 793 len += snprintf(buf + len, BUF_SIZE - len, 794 "ethertype = 0x%x ", 795 be16_to_cpu(cur->eth.ether_type)); 796 if (cur->eth.vlan_id) 797 len += snprintf(buf + len, BUF_SIZE - len, 798 "vlan-id = %d ", 799 be16_to_cpu(cur->eth.vlan_id)); 800 break; 801 802 case MLX4_NET_TRANS_RULE_ID_IPV4: 803 if (cur->ipv4.src_ip) 804 len += snprintf(buf + len, BUF_SIZE - len, 805 "src-ip = %pI4 ", 806 &cur->ipv4.src_ip); 807 if (cur->ipv4.dst_ip) 808 len += snprintf(buf + len, BUF_SIZE - len, 809 "dst-ip = %pI4 ", 810 &cur->ipv4.dst_ip); 811 break; 812 813 case MLX4_NET_TRANS_RULE_ID_TCP: 814 case MLX4_NET_TRANS_RULE_ID_UDP: 815 if (cur->tcp_udp.src_port) 816 len += snprintf(buf + len, BUF_SIZE - len, 817 "src-port = %d ", 818 be16_to_cpu(cur->tcp_udp.src_port)); 819 if (cur->tcp_udp.dst_port) 820 len += snprintf(buf + len, BUF_SIZE - len, 821 "dst-port = %d ", 822 be16_to_cpu(cur->tcp_udp.dst_port)); 823 break; 824 825 case MLX4_NET_TRANS_RULE_ID_IB: 826 len += snprintf(buf + len, BUF_SIZE - len, 827 "dst-gid = %pI6\n", cur->ib.dst_gid); 828 len += snprintf(buf + len, BUF_SIZE - len, 829 "dst-gid-mask = %pI6\n", 830 cur->ib.dst_gid_msk); 831 break; 832 833 case MLX4_NET_TRANS_RULE_ID_IPV6: 834 break; 835 836 default: 837 break; 838 } 839 } 840 len += snprintf(buf + len, BUF_SIZE - len, "\n"); 841 mlx4_err(dev, "%s", buf); 842 843 if (len >= BUF_SIZE) 844 mlx4_err(dev, "Network rule error message was truncated, print buffer is too small.\n"); 845 } 846 847 int mlx4_flow_attach(struct mlx4_dev *dev, 848 struct mlx4_net_trans_rule *rule, u64 *reg_id) 849 { 850 struct mlx4_cmd_mailbox *mailbox; 851 struct mlx4_spec_list *cur; 852 u32 size = 0; 853 int ret; 854 855 mailbox = mlx4_alloc_cmd_mailbox(dev); 856 if (IS_ERR(mailbox)) 857 return PTR_ERR(mailbox); 858 859 trans_rule_ctrl_to_hw(rule, mailbox->buf); 860 861 size += sizeof(struct mlx4_net_trans_rule_hw_ctrl); 862 863 list_for_each_entry(cur, &rule->list, list) { 864 ret = parse_trans_rule(dev, cur, mailbox->buf + size); 865 if (ret < 0) { 866 mlx4_free_cmd_mailbox(dev, mailbox); 867 return -EINVAL; 868 } 869 size += ret; 870 } 871 872 ret = mlx4_QP_FLOW_STEERING_ATTACH(dev, mailbox, size >> 2, reg_id); 873 if (ret == -ENOMEM) 874 mlx4_err_rule(dev, 875 "mcg table is full. Fail to register network rule.\n", 876 rule); 877 else if (ret) 878 mlx4_err_rule(dev, "Fail to register network rule.\n", rule); 879 880 mlx4_free_cmd_mailbox(dev, mailbox); 881 882 return ret; 883 } 884 EXPORT_SYMBOL_GPL(mlx4_flow_attach); 885 886 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id) 887 { 888 int err; 889 890 err = mlx4_QP_FLOW_STEERING_DETACH(dev, reg_id); 891 if (err) 892 mlx4_err(dev, "Fail to detach network rule. registration id = 0x%llx\n", 893 reg_id); 894 return err; 895 } 896 EXPORT_SYMBOL_GPL(mlx4_flow_detach); 897 898 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 899 int block_mcast_loopback, enum mlx4_protocol prot, 900 enum mlx4_steer_type steer) 901 { 902 struct mlx4_priv *priv = mlx4_priv(dev); 903 struct mlx4_cmd_mailbox *mailbox; 904 struct mlx4_mgm *mgm; 905 u32 members_count; 906 int index, prev; 907 int link = 0; 908 int i; 909 int err; 910 u8 port = gid[5]; 911 u8 new_entry = 0; 912 913 mailbox = mlx4_alloc_cmd_mailbox(dev); 914 if (IS_ERR(mailbox)) 915 return PTR_ERR(mailbox); 916 mgm = mailbox->buf; 917 918 mutex_lock(&priv->mcg_table.mutex); 919 err = find_entry(dev, port, gid, prot, 920 mailbox, &prev, &index); 921 if (err) 922 goto out; 923 924 if (index != -1) { 925 if (!(be32_to_cpu(mgm->members_count) & 0xffffff)) { 926 new_entry = 1; 927 memcpy(mgm->gid, gid, 16); 928 } 929 } else { 930 link = 1; 931 932 index = mlx4_bitmap_alloc(&priv->mcg_table.bitmap); 933 if (index == -1) { 934 mlx4_err(dev, "No AMGM entries left\n"); 935 err = -ENOMEM; 936 goto out; 937 } 938 index += dev->caps.num_mgms; 939 940 new_entry = 1; 941 memset(mgm, 0, sizeof *mgm); 942 memcpy(mgm->gid, gid, 16); 943 } 944 945 members_count = be32_to_cpu(mgm->members_count) & 0xffffff; 946 if (members_count == dev->caps.num_qp_per_mgm) { 947 mlx4_err(dev, "MGM at index %x is full.\n", index); 948 err = -ENOMEM; 949 goto out; 950 } 951 952 for (i = 0; i < members_count; ++i) 953 if ((be32_to_cpu(mgm->qp[i]) & MGM_QPN_MASK) == qp->qpn) { 954 mlx4_dbg(dev, "QP %06x already a member of MGM\n", qp->qpn); 955 err = 0; 956 goto out; 957 } 958 959 if (block_mcast_loopback) 960 mgm->qp[members_count++] = cpu_to_be32((qp->qpn & MGM_QPN_MASK) | 961 (1U << MGM_BLCK_LB_BIT)); 962 else 963 mgm->qp[members_count++] = cpu_to_be32(qp->qpn & MGM_QPN_MASK); 964 965 mgm->members_count = cpu_to_be32(members_count | (u32) prot << 30); 966 967 err = mlx4_WRITE_ENTRY(dev, index, mailbox); 968 if (err) 969 goto out; 970 971 if (!link) 972 goto out; 973 974 err = mlx4_READ_ENTRY(dev, prev, mailbox); 975 if (err) 976 goto out; 977 978 mgm->next_gid_index = cpu_to_be32(index << 6); 979 980 err = mlx4_WRITE_ENTRY(dev, prev, mailbox); 981 if (err) 982 goto out; 983 984 out: 985 if (prot == MLX4_PROT_ETH) { 986 /* manage the steering entry for promisc mode */ 987 if (new_entry) 988 new_steering_entry(dev, port, steer, index, qp->qpn); 989 else 990 existing_steering_entry(dev, port, steer, 991 index, qp->qpn); 992 } 993 if (err && link && index != -1) { 994 if (index < dev->caps.num_mgms) 995 mlx4_warn(dev, "Got AMGM index %d < %d", 996 index, dev->caps.num_mgms); 997 else 998 mlx4_bitmap_free(&priv->mcg_table.bitmap, 999 index - dev->caps.num_mgms); 1000 } 1001 mutex_unlock(&priv->mcg_table.mutex); 1002 1003 mlx4_free_cmd_mailbox(dev, mailbox); 1004 return err; 1005 } 1006 1007 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1008 enum mlx4_protocol prot, enum mlx4_steer_type steer) 1009 { 1010 struct mlx4_priv *priv = mlx4_priv(dev); 1011 struct mlx4_cmd_mailbox *mailbox; 1012 struct mlx4_mgm *mgm; 1013 u32 members_count; 1014 int prev, index; 1015 int i, loc; 1016 int err; 1017 u8 port = gid[5]; 1018 bool removed_entry = false; 1019 1020 mailbox = mlx4_alloc_cmd_mailbox(dev); 1021 if (IS_ERR(mailbox)) 1022 return PTR_ERR(mailbox); 1023 mgm = mailbox->buf; 1024 1025 mutex_lock(&priv->mcg_table.mutex); 1026 1027 err = find_entry(dev, port, gid, prot, 1028 mailbox, &prev, &index); 1029 if (err) 1030 goto out; 1031 1032 if (index == -1) { 1033 mlx4_err(dev, "MGID %pI6 not found\n", gid); 1034 err = -EINVAL; 1035 goto out; 1036 } 1037 1038 /* if this pq is also a promisc qp, it shouldn't be removed */ 1039 if (prot == MLX4_PROT_ETH && 1040 check_duplicate_entry(dev, port, steer, index, qp->qpn)) 1041 goto out; 1042 1043 members_count = be32_to_cpu(mgm->members_count) & 0xffffff; 1044 for (loc = -1, i = 0; i < members_count; ++i) 1045 if ((be32_to_cpu(mgm->qp[i]) & MGM_QPN_MASK) == qp->qpn) 1046 loc = i; 1047 1048 if (loc == -1) { 1049 mlx4_err(dev, "QP %06x not found in MGM\n", qp->qpn); 1050 err = -EINVAL; 1051 goto out; 1052 } 1053 1054 1055 mgm->members_count = cpu_to_be32(--members_count | (u32) prot << 30); 1056 mgm->qp[loc] = mgm->qp[i - 1]; 1057 mgm->qp[i - 1] = 0; 1058 1059 if (prot == MLX4_PROT_ETH) 1060 removed_entry = can_remove_steering_entry(dev, port, steer, 1061 index, qp->qpn); 1062 if (i != 1 && (prot != MLX4_PROT_ETH || !removed_entry)) { 1063 err = mlx4_WRITE_ENTRY(dev, index, mailbox); 1064 goto out; 1065 } 1066 1067 /* We are going to delete the entry, members count should be 0 */ 1068 mgm->members_count = cpu_to_be32((u32) prot << 30); 1069 1070 if (prev == -1) { 1071 /* Remove entry from MGM */ 1072 int amgm_index = be32_to_cpu(mgm->next_gid_index) >> 6; 1073 if (amgm_index) { 1074 err = mlx4_READ_ENTRY(dev, amgm_index, mailbox); 1075 if (err) 1076 goto out; 1077 } else 1078 memset(mgm->gid, 0, 16); 1079 1080 err = mlx4_WRITE_ENTRY(dev, index, mailbox); 1081 if (err) 1082 goto out; 1083 1084 if (amgm_index) { 1085 if (amgm_index < dev->caps.num_mgms) 1086 mlx4_warn(dev, "MGM entry %d had AMGM index %d < %d", 1087 index, amgm_index, dev->caps.num_mgms); 1088 else 1089 mlx4_bitmap_free(&priv->mcg_table.bitmap, 1090 amgm_index - dev->caps.num_mgms); 1091 } 1092 } else { 1093 /* Remove entry from AMGM */ 1094 int cur_next_index = be32_to_cpu(mgm->next_gid_index) >> 6; 1095 err = mlx4_READ_ENTRY(dev, prev, mailbox); 1096 if (err) 1097 goto out; 1098 1099 mgm->next_gid_index = cpu_to_be32(cur_next_index << 6); 1100 1101 err = mlx4_WRITE_ENTRY(dev, prev, mailbox); 1102 if (err) 1103 goto out; 1104 1105 if (index < dev->caps.num_mgms) 1106 mlx4_warn(dev, "entry %d had next AMGM index %d < %d", 1107 prev, index, dev->caps.num_mgms); 1108 else 1109 mlx4_bitmap_free(&priv->mcg_table.bitmap, 1110 index - dev->caps.num_mgms); 1111 } 1112 1113 out: 1114 mutex_unlock(&priv->mcg_table.mutex); 1115 1116 mlx4_free_cmd_mailbox(dev, mailbox); 1117 return err; 1118 } 1119 1120 static int mlx4_QP_ATTACH(struct mlx4_dev *dev, struct mlx4_qp *qp, 1121 u8 gid[16], u8 attach, u8 block_loopback, 1122 enum mlx4_protocol prot) 1123 { 1124 struct mlx4_cmd_mailbox *mailbox; 1125 int err = 0; 1126 int qpn; 1127 1128 if (!mlx4_is_mfunc(dev)) 1129 return -EBADF; 1130 1131 mailbox = mlx4_alloc_cmd_mailbox(dev); 1132 if (IS_ERR(mailbox)) 1133 return PTR_ERR(mailbox); 1134 1135 memcpy(mailbox->buf, gid, 16); 1136 qpn = qp->qpn; 1137 qpn |= (prot << 28); 1138 if (attach && block_loopback) 1139 qpn |= (1 << 31); 1140 1141 err = mlx4_cmd(dev, mailbox->dma, qpn, attach, 1142 MLX4_CMD_QP_ATTACH, MLX4_CMD_TIME_CLASS_A, 1143 MLX4_CMD_WRAPPED); 1144 1145 mlx4_free_cmd_mailbox(dev, mailbox); 1146 return err; 1147 } 1148 1149 int mlx4_trans_to_dmfs_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, 1150 u8 gid[16], u8 port, 1151 int block_mcast_loopback, 1152 enum mlx4_protocol prot, u64 *reg_id) 1153 { 1154 struct mlx4_spec_list spec = { {NULL} }; 1155 __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16); 1156 1157 struct mlx4_net_trans_rule rule = { 1158 .queue_mode = MLX4_NET_TRANS_Q_FIFO, 1159 .exclusive = 0, 1160 .promisc_mode = MLX4_FS_REGULAR, 1161 .priority = MLX4_DOMAIN_NIC, 1162 }; 1163 1164 rule.allow_loopback = !block_mcast_loopback; 1165 rule.port = port; 1166 rule.qpn = qp->qpn; 1167 INIT_LIST_HEAD(&rule.list); 1168 1169 switch (prot) { 1170 case MLX4_PROT_ETH: 1171 spec.id = MLX4_NET_TRANS_RULE_ID_ETH; 1172 memcpy(spec.eth.dst_mac, &gid[10], ETH_ALEN); 1173 memcpy(spec.eth.dst_mac_msk, &mac_mask, ETH_ALEN); 1174 break; 1175 1176 case MLX4_PROT_IB_IPV6: 1177 spec.id = MLX4_NET_TRANS_RULE_ID_IB; 1178 memcpy(spec.ib.dst_gid, gid, 16); 1179 memset(&spec.ib.dst_gid_msk, 0xff, 16); 1180 break; 1181 default: 1182 return -EINVAL; 1183 } 1184 list_add_tail(&spec.list, &rule.list); 1185 1186 return mlx4_flow_attach(dev, &rule, reg_id); 1187 } 1188 1189 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1190 u8 port, int block_mcast_loopback, 1191 enum mlx4_protocol prot, u64 *reg_id) 1192 { 1193 switch (dev->caps.steering_mode) { 1194 case MLX4_STEERING_MODE_A0: 1195 if (prot == MLX4_PROT_ETH) 1196 return 0; 1197 1198 case MLX4_STEERING_MODE_B0: 1199 if (prot == MLX4_PROT_ETH) 1200 gid[7] |= (MLX4_MC_STEER << 1); 1201 1202 if (mlx4_is_mfunc(dev)) 1203 return mlx4_QP_ATTACH(dev, qp, gid, 1, 1204 block_mcast_loopback, prot); 1205 return mlx4_qp_attach_common(dev, qp, gid, 1206 block_mcast_loopback, prot, 1207 MLX4_MC_STEER); 1208 1209 case MLX4_STEERING_MODE_DEVICE_MANAGED: 1210 return mlx4_trans_to_dmfs_attach(dev, qp, gid, port, 1211 block_mcast_loopback, 1212 prot, reg_id); 1213 default: 1214 return -EINVAL; 1215 } 1216 } 1217 EXPORT_SYMBOL_GPL(mlx4_multicast_attach); 1218 1219 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1220 enum mlx4_protocol prot, u64 reg_id) 1221 { 1222 switch (dev->caps.steering_mode) { 1223 case MLX4_STEERING_MODE_A0: 1224 if (prot == MLX4_PROT_ETH) 1225 return 0; 1226 1227 case MLX4_STEERING_MODE_B0: 1228 if (prot == MLX4_PROT_ETH) 1229 gid[7] |= (MLX4_MC_STEER << 1); 1230 1231 if (mlx4_is_mfunc(dev)) 1232 return mlx4_QP_ATTACH(dev, qp, gid, 0, 0, prot); 1233 1234 return mlx4_qp_detach_common(dev, qp, gid, prot, 1235 MLX4_MC_STEER); 1236 1237 case MLX4_STEERING_MODE_DEVICE_MANAGED: 1238 return mlx4_flow_detach(dev, reg_id); 1239 1240 default: 1241 return -EINVAL; 1242 } 1243 } 1244 EXPORT_SYMBOL_GPL(mlx4_multicast_detach); 1245 1246 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, 1247 u32 qpn, enum mlx4_net_trans_promisc_mode mode) 1248 { 1249 struct mlx4_net_trans_rule rule; 1250 u64 *regid_p; 1251 1252 switch (mode) { 1253 case MLX4_FS_ALL_DEFAULT: 1254 regid_p = &dev->regid_promisc_array[port]; 1255 break; 1256 case MLX4_FS_MC_DEFAULT: 1257 regid_p = &dev->regid_allmulti_array[port]; 1258 break; 1259 default: 1260 return -1; 1261 } 1262 1263 if (*regid_p != 0) 1264 return -1; 1265 1266 rule.promisc_mode = mode; 1267 rule.port = port; 1268 rule.qpn = qpn; 1269 INIT_LIST_HEAD(&rule.list); 1270 mlx4_err(dev, "going promisc on %x\n", port); 1271 1272 return mlx4_flow_attach(dev, &rule, regid_p); 1273 } 1274 EXPORT_SYMBOL_GPL(mlx4_flow_steer_promisc_add); 1275 1276 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port, 1277 enum mlx4_net_trans_promisc_mode mode) 1278 { 1279 int ret; 1280 u64 *regid_p; 1281 1282 switch (mode) { 1283 case MLX4_FS_ALL_DEFAULT: 1284 regid_p = &dev->regid_promisc_array[port]; 1285 break; 1286 case MLX4_FS_MC_DEFAULT: 1287 regid_p = &dev->regid_allmulti_array[port]; 1288 break; 1289 default: 1290 return -1; 1291 } 1292 1293 if (*regid_p == 0) 1294 return -1; 1295 1296 ret = mlx4_flow_detach(dev, *regid_p); 1297 if (ret == 0) 1298 *regid_p = 0; 1299 1300 return ret; 1301 } 1302 EXPORT_SYMBOL_GPL(mlx4_flow_steer_promisc_remove); 1303 1304 int mlx4_unicast_attach(struct mlx4_dev *dev, 1305 struct mlx4_qp *qp, u8 gid[16], 1306 int block_mcast_loopback, enum mlx4_protocol prot) 1307 { 1308 if (prot == MLX4_PROT_ETH) 1309 gid[7] |= (MLX4_UC_STEER << 1); 1310 1311 if (mlx4_is_mfunc(dev)) 1312 return mlx4_QP_ATTACH(dev, qp, gid, 1, 1313 block_mcast_loopback, prot); 1314 1315 return mlx4_qp_attach_common(dev, qp, gid, block_mcast_loopback, 1316 prot, MLX4_UC_STEER); 1317 } 1318 EXPORT_SYMBOL_GPL(mlx4_unicast_attach); 1319 1320 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, 1321 u8 gid[16], enum mlx4_protocol prot) 1322 { 1323 if (prot == MLX4_PROT_ETH) 1324 gid[7] |= (MLX4_UC_STEER << 1); 1325 1326 if (mlx4_is_mfunc(dev)) 1327 return mlx4_QP_ATTACH(dev, qp, gid, 0, 0, prot); 1328 1329 return mlx4_qp_detach_common(dev, qp, gid, prot, MLX4_UC_STEER); 1330 } 1331 EXPORT_SYMBOL_GPL(mlx4_unicast_detach); 1332 1333 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave, 1334 struct mlx4_vhcr *vhcr, 1335 struct mlx4_cmd_mailbox *inbox, 1336 struct mlx4_cmd_mailbox *outbox, 1337 struct mlx4_cmd_info *cmd) 1338 { 1339 u32 qpn = (u32) vhcr->in_param & 0xffffffff; 1340 u8 port = vhcr->in_param >> 62; 1341 enum mlx4_steer_type steer = vhcr->in_modifier; 1342 1343 /* Promiscuous unicast is not allowed in mfunc */ 1344 if (mlx4_is_mfunc(dev) && steer == MLX4_UC_STEER) 1345 return 0; 1346 1347 if (vhcr->op_modifier) 1348 return add_promisc_qp(dev, port, steer, qpn); 1349 else 1350 return remove_promisc_qp(dev, port, steer, qpn); 1351 } 1352 1353 static int mlx4_PROMISC(struct mlx4_dev *dev, u32 qpn, 1354 enum mlx4_steer_type steer, u8 add, u8 port) 1355 { 1356 return mlx4_cmd(dev, (u64) qpn | (u64) port << 62, (u32) steer, add, 1357 MLX4_CMD_PROMISC, MLX4_CMD_TIME_CLASS_A, 1358 MLX4_CMD_WRAPPED); 1359 } 1360 1361 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port) 1362 { 1363 if (mlx4_is_mfunc(dev)) 1364 return mlx4_PROMISC(dev, qpn, MLX4_MC_STEER, 1, port); 1365 1366 return add_promisc_qp(dev, port, MLX4_MC_STEER, qpn); 1367 } 1368 EXPORT_SYMBOL_GPL(mlx4_multicast_promisc_add); 1369 1370 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port) 1371 { 1372 if (mlx4_is_mfunc(dev)) 1373 return mlx4_PROMISC(dev, qpn, MLX4_MC_STEER, 0, port); 1374 1375 return remove_promisc_qp(dev, port, MLX4_MC_STEER, qpn); 1376 } 1377 EXPORT_SYMBOL_GPL(mlx4_multicast_promisc_remove); 1378 1379 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port) 1380 { 1381 if (mlx4_is_mfunc(dev)) 1382 return mlx4_PROMISC(dev, qpn, MLX4_UC_STEER, 1, port); 1383 1384 return add_promisc_qp(dev, port, MLX4_UC_STEER, qpn); 1385 } 1386 EXPORT_SYMBOL_GPL(mlx4_unicast_promisc_add); 1387 1388 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port) 1389 { 1390 if (mlx4_is_mfunc(dev)) 1391 return mlx4_PROMISC(dev, qpn, MLX4_UC_STEER, 0, port); 1392 1393 return remove_promisc_qp(dev, port, MLX4_UC_STEER, qpn); 1394 } 1395 EXPORT_SYMBOL_GPL(mlx4_unicast_promisc_remove); 1396 1397 int mlx4_init_mcg_table(struct mlx4_dev *dev) 1398 { 1399 struct mlx4_priv *priv = mlx4_priv(dev); 1400 int err; 1401 1402 /* No need for mcg_table when fw managed the mcg table*/ 1403 if (dev->caps.steering_mode == 1404 MLX4_STEERING_MODE_DEVICE_MANAGED) 1405 return 0; 1406 err = mlx4_bitmap_init(&priv->mcg_table.bitmap, dev->caps.num_amgms, 1407 dev->caps.num_amgms - 1, 0, 0); 1408 if (err) 1409 return err; 1410 1411 mutex_init(&priv->mcg_table.mutex); 1412 1413 return 0; 1414 } 1415 1416 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev) 1417 { 1418 if (dev->caps.steering_mode != 1419 MLX4_STEERING_MODE_DEVICE_MANAGED) 1420 mlx4_bitmap_cleanup(&mlx4_priv(dev)->mcg_table.bitmap); 1421 } 1422