1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * OpenIB.org BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or 14 * without modification, are permitted provided that the following 15 * conditions are met: 16 * 17 * - Redistributions of source code must retain the above 18 * copyright notice, this list of conditions and the following 19 * disclaimer. 20 * 21 * - Redistributions in binary form must reproduce the above 22 * copyright notice, this list of conditions and the following 23 * disclaimer in the documentation and/or other materials 24 * provided with the distribution. 25 * 26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 33 * SOFTWARE. 34 */ 35 36 #include <linux/module.h> 37 #include <linux/kernel.h> 38 #include <linux/init.h> 39 #include <linux/errno.h> 40 #include <linux/pci.h> 41 #include <linux/dma-mapping.h> 42 #include <linux/slab.h> 43 #include <linux/io-mapping.h> 44 #include <linux/delay.h> 45 #include <linux/etherdevice.h> 46 #include <net/devlink.h> 47 48 #include <uapi/rdma/mlx4-abi.h> 49 #include <linux/mlx4/device.h> 50 #include <linux/mlx4/doorbell.h> 51 52 #include "mlx4.h" 53 #include "fw.h" 54 #include "icm.h" 55 56 MODULE_AUTHOR("Roland Dreier"); 57 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver"); 58 MODULE_LICENSE("Dual BSD/GPL"); 59 MODULE_VERSION(DRV_VERSION); 60 61 struct workqueue_struct *mlx4_wq; 62 63 #ifdef CONFIG_MLX4_DEBUG 64 65 int mlx4_debug_level; /* 0 by default */ 66 module_param_named(debug_level, mlx4_debug_level, int, 0644); 67 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0"); 68 69 #endif /* CONFIG_MLX4_DEBUG */ 70 71 #ifdef CONFIG_PCI_MSI 72 73 static int msi_x = 1; 74 module_param(msi_x, int, 0444); 75 MODULE_PARM_DESC(msi_x, "0 - don't use MSI-X, 1 - use MSI-X, >1 - limit number of MSI-X irqs to msi_x"); 76 77 #else /* CONFIG_PCI_MSI */ 78 79 #define msi_x (0) 80 81 #endif /* CONFIG_PCI_MSI */ 82 83 static uint8_t num_vfs[3] = {0, 0, 0}; 84 static int num_vfs_argc; 85 module_param_array(num_vfs, byte, &num_vfs_argc, 0444); 86 MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0\n" 87 "num_vfs=port1,port2,port1+2"); 88 89 static uint8_t probe_vf[3] = {0, 0, 0}; 90 static int probe_vfs_argc; 91 module_param_array(probe_vf, byte, &probe_vfs_argc, 0444); 92 MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)\n" 93 "probe_vf=port1,port2,port1+2"); 94 95 static int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE; 96 module_param_named(log_num_mgm_entry_size, 97 mlx4_log_num_mgm_entry_size, int, 0444); 98 MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num" 99 " of qp per mcg, for example:" 100 " 10 gives 248.range: 7 <=" 101 " log_num_mgm_entry_size <= 12." 102 " To activate device managed" 103 " flow steering when available, set to -1"); 104 105 static bool enable_64b_cqe_eqe = true; 106 module_param(enable_64b_cqe_eqe, bool, 0444); 107 MODULE_PARM_DESC(enable_64b_cqe_eqe, 108 "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)"); 109 110 static bool enable_4k_uar; 111 module_param(enable_4k_uar, bool, 0444); 112 MODULE_PARM_DESC(enable_4k_uar, 113 "Enable using 4K UAR. Should not be enabled if have VFs which do not support 4K UARs (default: false)"); 114 115 #define PF_CONTEXT_BEHAVIOUR_MASK (MLX4_FUNC_CAP_64B_EQE_CQE | \ 116 MLX4_FUNC_CAP_EQE_CQE_STRIDE | \ 117 MLX4_FUNC_CAP_DMFS_A0_STATIC) 118 119 #define RESET_PERSIST_MASK_FLAGS (MLX4_FLAG_SRIOV) 120 121 static char mlx4_version[] = 122 DRV_NAME ": Mellanox ConnectX core driver v" 123 DRV_VERSION "\n"; 124 125 static const struct mlx4_profile default_profile = { 126 .num_qp = 1 << 18, 127 .num_srq = 1 << 16, 128 .rdmarc_per_qp = 1 << 4, 129 .num_cq = 1 << 16, 130 .num_mcg = 1 << 13, 131 .num_mpt = 1 << 19, 132 .num_mtt = 1 << 20, /* It is really num mtt segments */ 133 }; 134 135 static const struct mlx4_profile low_mem_profile = { 136 .num_qp = 1 << 17, 137 .num_srq = 1 << 6, 138 .rdmarc_per_qp = 1 << 4, 139 .num_cq = 1 << 8, 140 .num_mcg = 1 << 8, 141 .num_mpt = 1 << 9, 142 .num_mtt = 1 << 7, 143 }; 144 145 static int log_num_mac = 7; 146 module_param_named(log_num_mac, log_num_mac, int, 0444); 147 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)"); 148 149 static int log_num_vlan; 150 module_param_named(log_num_vlan, log_num_vlan, int, 0444); 151 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)"); 152 /* Log2 max number of VLANs per ETH port (0-7) */ 153 #define MLX4_LOG_NUM_VLANS 7 154 #define MLX4_MIN_LOG_NUM_VLANS 0 155 #define MLX4_MIN_LOG_NUM_MAC 1 156 157 static bool use_prio; 158 module_param_named(use_prio, use_prio, bool, 0444); 159 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports (deprecated)"); 160 161 int log_mtts_per_seg = ilog2(1); 162 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444); 163 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment " 164 "(0-7) (default: 0)"); 165 166 static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE}; 167 static int arr_argc = 2; 168 module_param_array(port_type_array, int, &arr_argc, 0444); 169 MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default " 170 "1 for IB, 2 for Ethernet"); 171 172 struct mlx4_port_config { 173 struct list_head list; 174 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; 175 struct pci_dev *pdev; 176 }; 177 178 static atomic_t pf_loading = ATOMIC_INIT(0); 179 180 static int mlx4_devlink_ierr_reset_get(struct devlink *devlink, u32 id, 181 struct devlink_param_gset_ctx *ctx) 182 { 183 ctx->val.vbool = !!mlx4_internal_err_reset; 184 return 0; 185 } 186 187 static int mlx4_devlink_ierr_reset_set(struct devlink *devlink, u32 id, 188 struct devlink_param_gset_ctx *ctx, 189 struct netlink_ext_ack *extack) 190 { 191 mlx4_internal_err_reset = ctx->val.vbool; 192 return 0; 193 } 194 195 static int mlx4_devlink_crdump_snapshot_get(struct devlink *devlink, u32 id, 196 struct devlink_param_gset_ctx *ctx) 197 { 198 struct mlx4_priv *priv = devlink_priv(devlink); 199 struct mlx4_dev *dev = &priv->dev; 200 201 ctx->val.vbool = dev->persist->crdump.snapshot_enable; 202 return 0; 203 } 204 205 static int mlx4_devlink_crdump_snapshot_set(struct devlink *devlink, u32 id, 206 struct devlink_param_gset_ctx *ctx, 207 struct netlink_ext_ack *extack) 208 { 209 struct mlx4_priv *priv = devlink_priv(devlink); 210 struct mlx4_dev *dev = &priv->dev; 211 212 dev->persist->crdump.snapshot_enable = ctx->val.vbool; 213 return 0; 214 } 215 216 static int 217 mlx4_devlink_max_macs_validate(struct devlink *devlink, u32 id, 218 union devlink_param_value val, 219 struct netlink_ext_ack *extack) 220 { 221 u32 value = val.vu32; 222 223 if (value < 1 || value > 128) 224 return -ERANGE; 225 226 if (!is_power_of_2(value)) { 227 NL_SET_ERR_MSG_MOD(extack, "max_macs supported must be power of 2"); 228 return -EINVAL; 229 } 230 231 return 0; 232 } 233 234 enum mlx4_devlink_param_id { 235 MLX4_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX, 236 MLX4_DEVLINK_PARAM_ID_ENABLE_64B_CQE_EQE, 237 MLX4_DEVLINK_PARAM_ID_ENABLE_4K_UAR, 238 }; 239 240 static const struct devlink_param mlx4_devlink_params[] = { 241 DEVLINK_PARAM_GENERIC(INT_ERR_RESET, 242 BIT(DEVLINK_PARAM_CMODE_RUNTIME) | 243 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), 244 mlx4_devlink_ierr_reset_get, 245 mlx4_devlink_ierr_reset_set, NULL), 246 DEVLINK_PARAM_GENERIC(MAX_MACS, 247 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), 248 NULL, NULL, mlx4_devlink_max_macs_validate), 249 DEVLINK_PARAM_GENERIC(REGION_SNAPSHOT, 250 BIT(DEVLINK_PARAM_CMODE_RUNTIME) | 251 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), 252 mlx4_devlink_crdump_snapshot_get, 253 mlx4_devlink_crdump_snapshot_set, NULL), 254 DEVLINK_PARAM_DRIVER(MLX4_DEVLINK_PARAM_ID_ENABLE_64B_CQE_EQE, 255 "enable_64b_cqe_eqe", DEVLINK_PARAM_TYPE_BOOL, 256 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), 257 NULL, NULL, NULL), 258 DEVLINK_PARAM_DRIVER(MLX4_DEVLINK_PARAM_ID_ENABLE_4K_UAR, 259 "enable_4k_uar", DEVLINK_PARAM_TYPE_BOOL, 260 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT), 261 NULL, NULL, NULL), 262 }; 263 264 static void mlx4_devlink_set_params_init_values(struct devlink *devlink) 265 { 266 union devlink_param_value value; 267 268 value.vbool = !!mlx4_internal_err_reset; 269 devl_param_driverinit_value_set(devlink, 270 DEVLINK_PARAM_GENERIC_ID_INT_ERR_RESET, 271 value); 272 273 value.vu32 = 1UL << log_num_mac; 274 devl_param_driverinit_value_set(devlink, 275 DEVLINK_PARAM_GENERIC_ID_MAX_MACS, 276 value); 277 278 value.vbool = enable_64b_cqe_eqe; 279 devl_param_driverinit_value_set(devlink, 280 MLX4_DEVLINK_PARAM_ID_ENABLE_64B_CQE_EQE, 281 value); 282 283 value.vbool = enable_4k_uar; 284 devl_param_driverinit_value_set(devlink, 285 MLX4_DEVLINK_PARAM_ID_ENABLE_4K_UAR, 286 value); 287 288 value.vbool = false; 289 devl_param_driverinit_value_set(devlink, 290 DEVLINK_PARAM_GENERIC_ID_REGION_SNAPSHOT, 291 value); 292 } 293 294 static inline void mlx4_set_num_reserved_uars(struct mlx4_dev *dev, 295 struct mlx4_dev_cap *dev_cap) 296 { 297 /* The reserved_uars is calculated by system page size unit. 298 * Therefore, adjustment is added when the uar page size is less 299 * than the system page size 300 */ 301 dev->caps.reserved_uars = 302 max_t(int, 303 mlx4_get_num_reserved_uar(dev), 304 dev_cap->reserved_uars / 305 (1 << (PAGE_SHIFT - dev->uar_page_shift))); 306 } 307 308 int mlx4_check_port_params(struct mlx4_dev *dev, 309 enum mlx4_port_type *port_type) 310 { 311 int i; 312 313 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) { 314 for (i = 0; i < dev->caps.num_ports - 1; i++) { 315 if (port_type[i] != port_type[i + 1]) { 316 mlx4_err(dev, "Only same port types supported on this HCA, aborting\n"); 317 return -EOPNOTSUPP; 318 } 319 } 320 } 321 322 for (i = 0; i < dev->caps.num_ports; i++) { 323 if (!(port_type[i] & dev->caps.supported_type[i+1])) { 324 mlx4_err(dev, "Requested port type for port %d is not supported on this HCA\n", 325 i + 1); 326 return -EOPNOTSUPP; 327 } 328 } 329 return 0; 330 } 331 332 static void mlx4_set_port_mask(struct mlx4_dev *dev) 333 { 334 int i; 335 336 for (i = 1; i <= dev->caps.num_ports; ++i) 337 dev->caps.port_mask[i] = dev->caps.port_type[i]; 338 } 339 340 enum { 341 MLX4_QUERY_FUNC_NUM_SYS_EQS = 1 << 0, 342 }; 343 344 static int mlx4_query_func(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 345 { 346 int err = 0; 347 struct mlx4_func func; 348 349 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) { 350 err = mlx4_QUERY_FUNC(dev, &func, 0); 351 if (err) { 352 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 353 return err; 354 } 355 dev_cap->max_eqs = func.max_eq; 356 dev_cap->reserved_eqs = func.rsvd_eqs; 357 dev_cap->reserved_uars = func.rsvd_uars; 358 err |= MLX4_QUERY_FUNC_NUM_SYS_EQS; 359 } 360 return err; 361 } 362 363 static void mlx4_enable_cqe_eqe_stride(struct mlx4_dev *dev) 364 { 365 struct mlx4_caps *dev_cap = &dev->caps; 366 367 /* FW not supporting or cancelled by user */ 368 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) || 369 !(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE)) 370 return; 371 372 /* Must have 64B CQE_EQE enabled by FW to use bigger stride 373 * When FW has NCSI it may decide not to report 64B CQE/EQEs 374 */ 375 if (!(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_EQE) || 376 !(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_CQE)) { 377 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE; 378 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE; 379 return; 380 } 381 382 if (cache_line_size() == 128 || cache_line_size() == 256) { 383 mlx4_dbg(dev, "Enabling CQE stride cacheLine supported\n"); 384 /* Changing the real data inside CQE size to 32B */ 385 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE; 386 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE; 387 388 if (mlx4_is_master(dev)) 389 dev_cap->function_caps |= MLX4_FUNC_CAP_EQE_CQE_STRIDE; 390 } else { 391 if (cache_line_size() != 32 && cache_line_size() != 64) 392 mlx4_dbg(dev, "Disabling CQE stride, cacheLine size unsupported\n"); 393 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE; 394 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE; 395 } 396 } 397 398 static int _mlx4_dev_port(struct mlx4_dev *dev, int port, 399 struct mlx4_port_cap *port_cap) 400 { 401 dev->caps.vl_cap[port] = port_cap->max_vl; 402 dev->caps.ib_mtu_cap[port] = port_cap->ib_mtu; 403 dev->phys_caps.gid_phys_table_len[port] = port_cap->max_gids; 404 dev->phys_caps.pkey_phys_table_len[port] = port_cap->max_pkeys; 405 /* set gid and pkey table operating lengths by default 406 * to non-sriov values 407 */ 408 dev->caps.gid_table_len[port] = port_cap->max_gids; 409 dev->caps.pkey_table_len[port] = port_cap->max_pkeys; 410 dev->caps.port_width_cap[port] = port_cap->max_port_width; 411 dev->caps.eth_mtu_cap[port] = port_cap->eth_mtu; 412 dev->caps.max_tc_eth = port_cap->max_tc_eth; 413 dev->caps.def_mac[port] = port_cap->def_mac; 414 dev->caps.supported_type[port] = port_cap->supported_port_types; 415 dev->caps.suggested_type[port] = port_cap->suggested_type; 416 dev->caps.default_sense[port] = port_cap->default_sense; 417 dev->caps.trans_type[port] = port_cap->trans_type; 418 dev->caps.vendor_oui[port] = port_cap->vendor_oui; 419 dev->caps.wavelength[port] = port_cap->wavelength; 420 dev->caps.trans_code[port] = port_cap->trans_code; 421 422 return 0; 423 } 424 425 static int mlx4_dev_port(struct mlx4_dev *dev, int port, 426 struct mlx4_port_cap *port_cap) 427 { 428 int err = 0; 429 430 err = mlx4_QUERY_PORT(dev, port, port_cap); 431 432 if (err) 433 mlx4_err(dev, "QUERY_PORT command failed.\n"); 434 435 return err; 436 } 437 438 static inline void mlx4_enable_ignore_fcs(struct mlx4_dev *dev) 439 { 440 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_IGNORE_FCS)) 441 return; 442 443 if (mlx4_is_mfunc(dev)) { 444 mlx4_dbg(dev, "SRIOV mode - Disabling Ignore FCS"); 445 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS; 446 return; 447 } 448 449 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)) { 450 mlx4_dbg(dev, 451 "Keep FCS is not supported - Disabling Ignore FCS"); 452 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS; 453 return; 454 } 455 } 456 457 #define MLX4_A0_STEERING_TABLE_SIZE 256 458 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 459 { 460 int err; 461 int i; 462 463 err = mlx4_QUERY_DEV_CAP(dev, dev_cap); 464 if (err) { 465 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n"); 466 return err; 467 } 468 mlx4_dev_cap_dump(dev, dev_cap); 469 470 if (dev_cap->min_page_sz > PAGE_SIZE) { 471 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n", 472 dev_cap->min_page_sz, PAGE_SIZE); 473 return -ENODEV; 474 } 475 if (dev_cap->num_ports > MLX4_MAX_PORTS) { 476 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n", 477 dev_cap->num_ports, MLX4_MAX_PORTS); 478 return -ENODEV; 479 } 480 481 if (dev_cap->uar_size > pci_resource_len(dev->persist->pdev, 2)) { 482 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n", 483 dev_cap->uar_size, 484 (unsigned long long) 485 pci_resource_len(dev->persist->pdev, 2)); 486 return -ENODEV; 487 } 488 489 dev->caps.num_ports = dev_cap->num_ports; 490 dev->caps.num_sys_eqs = dev_cap->num_sys_eqs; 491 dev->phys_caps.num_phys_eqs = dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS ? 492 dev->caps.num_sys_eqs : 493 MLX4_MAX_EQ_NUM; 494 for (i = 1; i <= dev->caps.num_ports; ++i) { 495 err = _mlx4_dev_port(dev, i, dev_cap->port_cap + i); 496 if (err) { 497 mlx4_err(dev, "QUERY_PORT command failed, aborting\n"); 498 return err; 499 } 500 } 501 502 dev->caps.map_clock_to_user = dev_cap->map_clock_to_user; 503 dev->caps.uar_page_size = PAGE_SIZE; 504 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE; 505 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay; 506 dev->caps.bf_reg_size = dev_cap->bf_reg_size; 507 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page; 508 dev->caps.max_sq_sg = dev_cap->max_sq_sg; 509 dev->caps.max_rq_sg = dev_cap->max_rq_sg; 510 dev->caps.max_wqes = dev_cap->max_qp_sz; 511 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp; 512 dev->caps.max_srq_wqes = dev_cap->max_srq_sz; 513 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1; 514 dev->caps.reserved_srqs = dev_cap->reserved_srqs; 515 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz; 516 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz; 517 /* 518 * Subtract 1 from the limit because we need to allocate a 519 * spare CQE to enable resizing the CQ. 520 */ 521 dev->caps.max_cqes = dev_cap->max_cq_sz - 1; 522 dev->caps.reserved_cqs = dev_cap->reserved_cqs; 523 dev->caps.reserved_eqs = dev_cap->reserved_eqs; 524 dev->caps.reserved_mtts = dev_cap->reserved_mtts; 525 dev->caps.reserved_mrws = dev_cap->reserved_mrws; 526 527 dev->caps.reserved_pds = dev_cap->reserved_pds; 528 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? 529 dev_cap->reserved_xrcds : 0; 530 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? 531 dev_cap->max_xrcds : 0; 532 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz; 533 534 dev->caps.max_msg_sz = dev_cap->max_msg_sz; 535 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1); 536 dev->caps.flags = dev_cap->flags; 537 dev->caps.flags2 = dev_cap->flags2; 538 dev->caps.bmme_flags = dev_cap->bmme_flags; 539 dev->caps.reserved_lkey = dev_cap->reserved_lkey; 540 dev->caps.stat_rate_support = dev_cap->stat_rate_support; 541 dev->caps.max_gso_sz = dev_cap->max_gso_sz; 542 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz; 543 dev->caps.wol_port[1] = dev_cap->wol_port[1]; 544 dev->caps.wol_port[2] = dev_cap->wol_port[2]; 545 dev->caps.health_buffer_addrs = dev_cap->health_buffer_addrs; 546 547 /* Save uar page shift */ 548 if (!mlx4_is_slave(dev)) { 549 /* Virtual PCI function needs to determine UAR page size from 550 * firmware. Only master PCI function can set the uar page size 551 */ 552 if (enable_4k_uar || !dev->persist->num_vfs) 553 dev->uar_page_shift = DEFAULT_UAR_PAGE_SHIFT; 554 else 555 dev->uar_page_shift = PAGE_SHIFT; 556 557 mlx4_set_num_reserved_uars(dev, dev_cap); 558 } 559 560 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN) { 561 struct mlx4_init_hca_param hca_param; 562 563 memset(&hca_param, 0, sizeof(hca_param)); 564 err = mlx4_QUERY_HCA(dev, &hca_param); 565 /* Turn off PHV_EN flag in case phv_check_en is set. 566 * phv_check_en is a HW check that parse the packet and verify 567 * phv bit was reported correctly in the wqe. To allow QinQ 568 * PHV_EN flag should be set and phv_check_en must be cleared 569 * otherwise QinQ packets will be drop by the HW. 570 */ 571 if (err || hca_param.phv_check_en) 572 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_PHV_EN; 573 } 574 575 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */ 576 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT) 577 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; 578 /* Don't do sense port on multifunction devices (for now at least) */ 579 if (mlx4_is_mfunc(dev)) 580 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; 581 582 if (mlx4_low_memory_profile()) { 583 dev->caps.log_num_macs = MLX4_MIN_LOG_NUM_MAC; 584 dev->caps.log_num_vlans = MLX4_MIN_LOG_NUM_VLANS; 585 } else { 586 dev->caps.log_num_macs = log_num_mac; 587 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS; 588 } 589 590 for (i = 1; i <= dev->caps.num_ports; ++i) { 591 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE; 592 if (dev->caps.supported_type[i]) { 593 /* if only ETH is supported - assign ETH */ 594 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH) 595 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH; 596 /* if only IB is supported, assign IB */ 597 else if (dev->caps.supported_type[i] == 598 MLX4_PORT_TYPE_IB) 599 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB; 600 else { 601 /* if IB and ETH are supported, we set the port 602 * type according to user selection of port type; 603 * if user selected none, take the FW hint */ 604 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE) 605 dev->caps.port_type[i] = dev->caps.suggested_type[i] ? 606 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB; 607 else 608 dev->caps.port_type[i] = port_type_array[i - 1]; 609 } 610 } 611 /* 612 * Link sensing is allowed on the port if 3 conditions are true: 613 * 1. Both protocols are supported on the port. 614 * 2. Different types are supported on the port 615 * 3. FW declared that it supports link sensing 616 */ 617 mlx4_priv(dev)->sense.sense_allowed[i] = 618 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) && 619 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && 620 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)); 621 622 /* 623 * If "default_sense" bit is set, we move the port to "AUTO" mode 624 * and perform sense_port FW command to try and set the correct 625 * port type from beginning 626 */ 627 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) { 628 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE; 629 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO; 630 mlx4_SENSE_PORT(dev, i, &sensed_port); 631 if (sensed_port != MLX4_PORT_TYPE_NONE) 632 dev->caps.port_type[i] = sensed_port; 633 } else { 634 dev->caps.possible_type[i] = dev->caps.port_type[i]; 635 } 636 637 if (dev->caps.log_num_macs > dev_cap->port_cap[i].log_max_macs) { 638 dev->caps.log_num_macs = dev_cap->port_cap[i].log_max_macs; 639 mlx4_warn(dev, "Requested number of MACs is too much for port %d, reducing to %d\n", 640 i, 1 << dev->caps.log_num_macs); 641 } 642 if (dev->caps.log_num_vlans > dev_cap->port_cap[i].log_max_vlans) { 643 dev->caps.log_num_vlans = dev_cap->port_cap[i].log_max_vlans; 644 mlx4_warn(dev, "Requested number of VLANs is too much for port %d, reducing to %d\n", 645 i, 1 << dev->caps.log_num_vlans); 646 } 647 } 648 649 if (mlx4_is_master(dev) && (dev->caps.num_ports == 2) && 650 (port_type_array[0] == MLX4_PORT_TYPE_IB) && 651 (port_type_array[1] == MLX4_PORT_TYPE_ETH)) { 652 mlx4_warn(dev, 653 "Granular QoS per VF not supported with IB/Eth configuration\n"); 654 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_QOS_VPP; 655 } 656 657 dev->caps.max_counters = dev_cap->max_counters; 658 659 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps; 660 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] = 661 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] = 662 (1 << dev->caps.log_num_macs) * 663 (1 << dev->caps.log_num_vlans) * 664 dev->caps.num_ports; 665 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH; 666 667 if (dev_cap->dmfs_high_rate_qpn_base > 0 && 668 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) 669 dev->caps.dmfs_high_rate_qpn_base = dev_cap->dmfs_high_rate_qpn_base; 670 else 671 dev->caps.dmfs_high_rate_qpn_base = 672 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]; 673 674 if (dev_cap->dmfs_high_rate_qpn_range > 0 && 675 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) { 676 dev->caps.dmfs_high_rate_qpn_range = dev_cap->dmfs_high_rate_qpn_range; 677 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DEFAULT; 678 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_FS_A0; 679 } else { 680 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_NOT_SUPPORTED; 681 dev->caps.dmfs_high_rate_qpn_base = 682 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]; 683 dev->caps.dmfs_high_rate_qpn_range = MLX4_A0_STEERING_TABLE_SIZE; 684 } 685 686 dev->caps.rl_caps = dev_cap->rl_caps; 687 688 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_RSS_RAW_ETH] = 689 dev->caps.dmfs_high_rate_qpn_range; 690 691 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] + 692 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] + 693 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] + 694 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH]; 695 696 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0; 697 698 if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) { 699 if (dev_cap->flags & 700 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) { 701 mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n"); 702 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE; 703 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE; 704 } 705 706 if (dev_cap->flags2 & 707 (MLX4_DEV_CAP_FLAG2_CQE_STRIDE | 708 MLX4_DEV_CAP_FLAG2_EQE_STRIDE)) { 709 mlx4_warn(dev, "Disabling EQE/CQE stride per user request\n"); 710 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE; 711 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE; 712 } 713 } 714 715 if ((dev->caps.flags & 716 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) && 717 mlx4_is_master(dev)) 718 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE; 719 720 if (!mlx4_is_slave(dev)) { 721 mlx4_enable_cqe_eqe_stride(dev); 722 dev->caps.alloc_res_qp_mask = 723 (dev->caps.bf_reg_size ? MLX4_RESERVE_ETH_BF_QP : 0) | 724 MLX4_RESERVE_A0_QP; 725 726 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG) && 727 dev->caps.flags & MLX4_DEV_CAP_FLAG_SET_ETH_SCHED) { 728 mlx4_warn(dev, "Old device ETS support detected\n"); 729 mlx4_warn(dev, "Consider upgrading device FW.\n"); 730 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG; 731 } 732 733 } else { 734 dev->caps.alloc_res_qp_mask = 0; 735 } 736 737 mlx4_enable_ignore_fcs(dev); 738 739 return 0; 740 } 741 742 /*The function checks if there are live vf, return the num of them*/ 743 static int mlx4_how_many_lives_vf(struct mlx4_dev *dev) 744 { 745 struct mlx4_priv *priv = mlx4_priv(dev); 746 struct mlx4_slave_state *s_state; 747 int i; 748 int ret = 0; 749 750 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) { 751 s_state = &priv->mfunc.master.slave_state[i]; 752 if (s_state->active && s_state->last_cmd != 753 MLX4_COMM_CMD_RESET) { 754 mlx4_warn(dev, "%s: slave: %d is still active\n", 755 __func__, i); 756 ret++; 757 } 758 } 759 return ret; 760 } 761 762 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey) 763 { 764 u32 qk = MLX4_RESERVED_QKEY_BASE; 765 766 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX || 767 qpn < dev->phys_caps.base_proxy_sqpn) 768 return -EINVAL; 769 770 if (qpn >= dev->phys_caps.base_tunnel_sqpn) 771 /* tunnel qp */ 772 qk += qpn - dev->phys_caps.base_tunnel_sqpn; 773 else 774 qk += qpn - dev->phys_caps.base_proxy_sqpn; 775 *qkey = qk; 776 return 0; 777 } 778 EXPORT_SYMBOL(mlx4_get_parav_qkey); 779 780 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val) 781 { 782 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 783 784 if (!mlx4_is_master(dev)) 785 return; 786 787 priv->virt2phys_pkey[slave][port - 1][i] = val; 788 } 789 EXPORT_SYMBOL(mlx4_sync_pkey_table); 790 791 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid) 792 { 793 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 794 795 if (!mlx4_is_master(dev)) 796 return; 797 798 priv->slave_node_guids[slave] = guid; 799 } 800 EXPORT_SYMBOL(mlx4_put_slave_node_guid); 801 802 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave) 803 { 804 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 805 806 if (!mlx4_is_master(dev)) 807 return 0; 808 809 return priv->slave_node_guids[slave]; 810 } 811 EXPORT_SYMBOL(mlx4_get_slave_node_guid); 812 813 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave) 814 { 815 struct mlx4_priv *priv = mlx4_priv(dev); 816 struct mlx4_slave_state *s_slave; 817 818 if (!mlx4_is_master(dev)) 819 return 0; 820 821 s_slave = &priv->mfunc.master.slave_state[slave]; 822 return !!s_slave->active; 823 } 824 EXPORT_SYMBOL(mlx4_is_slave_active); 825 826 void mlx4_handle_eth_header_mcast_prio(struct mlx4_net_trans_rule_hw_ctrl *ctrl, 827 struct _rule_hw *eth_header) 828 { 829 if (is_multicast_ether_addr(eth_header->eth.dst_mac) || 830 is_broadcast_ether_addr(eth_header->eth.dst_mac)) { 831 struct mlx4_net_trans_rule_hw_eth *eth = 832 (struct mlx4_net_trans_rule_hw_eth *)eth_header; 833 struct _rule_hw *next_rule = (struct _rule_hw *)(eth + 1); 834 bool last_rule = next_rule->size == 0 && next_rule->id == 0 && 835 next_rule->rsvd == 0; 836 837 if (last_rule) 838 ctrl->prio = cpu_to_be16(MLX4_DOMAIN_NIC); 839 } 840 } 841 EXPORT_SYMBOL(mlx4_handle_eth_header_mcast_prio); 842 843 static void slave_adjust_steering_mode(struct mlx4_dev *dev, 844 struct mlx4_dev_cap *dev_cap, 845 struct mlx4_init_hca_param *hca_param) 846 { 847 dev->caps.steering_mode = hca_param->steering_mode; 848 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) { 849 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry; 850 dev->caps.fs_log_max_ucast_qp_range_size = 851 dev_cap->fs_log_max_ucast_qp_range_size; 852 } else 853 dev->caps.num_qp_per_mgm = 854 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2); 855 856 mlx4_dbg(dev, "Steering mode is: %s\n", 857 mlx4_steering_mode_str(dev->caps.steering_mode)); 858 } 859 860 static void mlx4_slave_destroy_special_qp_cap(struct mlx4_dev *dev) 861 { 862 kfree(dev->caps.spec_qps); 863 dev->caps.spec_qps = NULL; 864 } 865 866 static int mlx4_slave_special_qp_cap(struct mlx4_dev *dev) 867 { 868 struct mlx4_func_cap *func_cap; 869 struct mlx4_caps *caps = &dev->caps; 870 int i, err = 0; 871 872 func_cap = kzalloc(sizeof(*func_cap), GFP_KERNEL); 873 caps->spec_qps = kcalloc(caps->num_ports, sizeof(*caps->spec_qps), GFP_KERNEL); 874 875 if (!func_cap || !caps->spec_qps) { 876 mlx4_err(dev, "Failed to allocate memory for special qps cap\n"); 877 err = -ENOMEM; 878 goto err_mem; 879 } 880 881 for (i = 1; i <= caps->num_ports; ++i) { 882 err = mlx4_QUERY_FUNC_CAP(dev, i, func_cap); 883 if (err) { 884 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for port %d, aborting (%d)\n", 885 i, err); 886 goto err_mem; 887 } 888 caps->spec_qps[i - 1] = func_cap->spec_qps; 889 caps->port_mask[i] = caps->port_type[i]; 890 caps->phys_port_id[i] = func_cap->phys_port_id; 891 err = mlx4_get_slave_pkey_gid_tbl_len(dev, i, 892 &caps->gid_table_len[i], 893 &caps->pkey_table_len[i]); 894 if (err) { 895 mlx4_err(dev, "QUERY_PORT command failed for port %d, aborting (%d)\n", 896 i, err); 897 goto err_mem; 898 } 899 } 900 901 err_mem: 902 if (err) 903 mlx4_slave_destroy_special_qp_cap(dev); 904 kfree(func_cap); 905 return err; 906 } 907 908 static int mlx4_slave_cap(struct mlx4_dev *dev) 909 { 910 int err; 911 u32 page_size; 912 struct mlx4_dev_cap *dev_cap; 913 struct mlx4_func_cap *func_cap; 914 struct mlx4_init_hca_param *hca_param; 915 916 hca_param = kzalloc(sizeof(*hca_param), GFP_KERNEL); 917 func_cap = kzalloc(sizeof(*func_cap), GFP_KERNEL); 918 dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL); 919 if (!hca_param || !func_cap || !dev_cap) { 920 mlx4_err(dev, "Failed to allocate memory for slave_cap\n"); 921 err = -ENOMEM; 922 goto free_mem; 923 } 924 925 err = mlx4_QUERY_HCA(dev, hca_param); 926 if (err) { 927 mlx4_err(dev, "QUERY_HCA command failed, aborting\n"); 928 goto free_mem; 929 } 930 931 /* fail if the hca has an unknown global capability 932 * at this time global_caps should be always zeroed 933 */ 934 if (hca_param->global_caps) { 935 mlx4_err(dev, "Unknown hca global capabilities\n"); 936 err = -EINVAL; 937 goto free_mem; 938 } 939 940 dev->caps.hca_core_clock = hca_param->hca_core_clock; 941 942 dev->caps.max_qp_dest_rdma = 1 << hca_param->log_rd_per_qp; 943 err = mlx4_dev_cap(dev, dev_cap); 944 if (err) { 945 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n"); 946 goto free_mem; 947 } 948 949 err = mlx4_QUERY_FW(dev); 950 if (err) 951 mlx4_err(dev, "QUERY_FW command failed: could not get FW version\n"); 952 953 page_size = ~dev->caps.page_size_cap + 1; 954 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size); 955 if (page_size > PAGE_SIZE) { 956 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n", 957 page_size, PAGE_SIZE); 958 err = -ENODEV; 959 goto free_mem; 960 } 961 962 /* Set uar_page_shift for VF */ 963 dev->uar_page_shift = hca_param->uar_page_sz + 12; 964 965 /* Make sure the master uar page size is valid */ 966 if (dev->uar_page_shift > PAGE_SHIFT) { 967 mlx4_err(dev, 968 "Invalid configuration: uar page size is larger than system page size\n"); 969 err = -ENODEV; 970 goto free_mem; 971 } 972 973 /* Set reserved_uars based on the uar_page_shift */ 974 mlx4_set_num_reserved_uars(dev, dev_cap); 975 976 /* Although uar page size in FW differs from system page size, 977 * upper software layers (mlx4_ib, mlx4_en and part of mlx4_core) 978 * still works with assumption that uar page size == system page size 979 */ 980 dev->caps.uar_page_size = PAGE_SIZE; 981 982 err = mlx4_QUERY_FUNC_CAP(dev, 0, func_cap); 983 if (err) { 984 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d)\n", 985 err); 986 goto free_mem; 987 } 988 989 if ((func_cap->pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) != 990 PF_CONTEXT_BEHAVIOUR_MASK) { 991 mlx4_err(dev, "Unknown pf context behaviour %x known flags %x\n", 992 func_cap->pf_context_behaviour, 993 PF_CONTEXT_BEHAVIOUR_MASK); 994 err = -EINVAL; 995 goto free_mem; 996 } 997 998 dev->caps.num_ports = func_cap->num_ports; 999 dev->quotas.qp = func_cap->qp_quota; 1000 dev->quotas.srq = func_cap->srq_quota; 1001 dev->quotas.cq = func_cap->cq_quota; 1002 dev->quotas.mpt = func_cap->mpt_quota; 1003 dev->quotas.mtt = func_cap->mtt_quota; 1004 dev->caps.num_qps = 1 << hca_param->log_num_qps; 1005 dev->caps.num_srqs = 1 << hca_param->log_num_srqs; 1006 dev->caps.num_cqs = 1 << hca_param->log_num_cqs; 1007 dev->caps.num_mpts = 1 << hca_param->log_mpt_sz; 1008 dev->caps.num_eqs = func_cap->max_eq; 1009 dev->caps.reserved_eqs = func_cap->reserved_eq; 1010 dev->caps.reserved_lkey = func_cap->reserved_lkey; 1011 dev->caps.num_pds = MLX4_NUM_PDS; 1012 dev->caps.num_mgms = 0; 1013 dev->caps.num_amgms = 0; 1014 1015 if (dev->caps.num_ports > MLX4_MAX_PORTS) { 1016 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n", 1017 dev->caps.num_ports, MLX4_MAX_PORTS); 1018 err = -ENODEV; 1019 goto free_mem; 1020 } 1021 1022 mlx4_replace_zero_macs(dev); 1023 1024 err = mlx4_slave_special_qp_cap(dev); 1025 if (err) { 1026 mlx4_err(dev, "Set special QP caps failed. aborting\n"); 1027 goto free_mem; 1028 } 1029 1030 if (dev->caps.uar_page_size * (dev->caps.num_uars - 1031 dev->caps.reserved_uars) > 1032 pci_resource_len(dev->persist->pdev, 1033 2)) { 1034 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n", 1035 dev->caps.uar_page_size * dev->caps.num_uars, 1036 (unsigned long long) 1037 pci_resource_len(dev->persist->pdev, 2)); 1038 err = -ENOMEM; 1039 goto err_mem; 1040 } 1041 1042 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) { 1043 dev->caps.eqe_size = 64; 1044 dev->caps.eqe_factor = 1; 1045 } else { 1046 dev->caps.eqe_size = 32; 1047 dev->caps.eqe_factor = 0; 1048 } 1049 1050 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) { 1051 dev->caps.cqe_size = 64; 1052 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; 1053 } else { 1054 dev->caps.cqe_size = 32; 1055 } 1056 1057 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_EQE_STRIDE_ENABLED) { 1058 dev->caps.eqe_size = hca_param->eqe_size; 1059 dev->caps.eqe_factor = 0; 1060 } 1061 1062 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_CQE_STRIDE_ENABLED) { 1063 dev->caps.cqe_size = hca_param->cqe_size; 1064 /* User still need to know when CQE > 32B */ 1065 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; 1066 } 1067 1068 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 1069 mlx4_warn(dev, "Timestamping is not supported in slave mode\n"); 1070 1071 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_USER_MAC_EN; 1072 mlx4_dbg(dev, "User MAC FW update is not supported in slave mode\n"); 1073 1074 slave_adjust_steering_mode(dev, dev_cap, hca_param); 1075 mlx4_dbg(dev, "RSS support for IP fragments is %s\n", 1076 hca_param->rss_ip_frags ? "on" : "off"); 1077 1078 if (func_cap->extra_flags & MLX4_QUERY_FUNC_FLAGS_BF_RES_QP && 1079 dev->caps.bf_reg_size) 1080 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_ETH_BF_QP; 1081 1082 if (func_cap->extra_flags & MLX4_QUERY_FUNC_FLAGS_A0_RES_QP) 1083 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_A0_QP; 1084 1085 err_mem: 1086 if (err) 1087 mlx4_slave_destroy_special_qp_cap(dev); 1088 free_mem: 1089 kfree(hca_param); 1090 kfree(func_cap); 1091 kfree(dev_cap); 1092 return err; 1093 } 1094 1095 /* 1096 * Change the port configuration of the device. 1097 * Every user of this function must hold the port mutex. 1098 */ 1099 int mlx4_change_port_types(struct mlx4_dev *dev, 1100 enum mlx4_port_type *port_types) 1101 { 1102 int err = 0; 1103 int change = 0; 1104 int port; 1105 1106 for (port = 0; port < dev->caps.num_ports; port++) { 1107 /* Change the port type only if the new type is different 1108 * from the current, and not set to Auto */ 1109 if (port_types[port] != dev->caps.port_type[port + 1]) 1110 change = 1; 1111 } 1112 if (change) { 1113 mlx4_unregister_device(dev); 1114 for (port = 1; port <= dev->caps.num_ports; port++) { 1115 mlx4_CLOSE_PORT(dev, port); 1116 dev->caps.port_type[port] = port_types[port - 1]; 1117 err = mlx4_SET_PORT(dev, port, -1); 1118 if (err) { 1119 mlx4_err(dev, "Failed to set port %d, aborting\n", 1120 port); 1121 goto out; 1122 } 1123 } 1124 mlx4_set_port_mask(dev); 1125 err = mlx4_register_device(dev); 1126 if (err) { 1127 mlx4_err(dev, "Failed to register device\n"); 1128 goto out; 1129 } 1130 } 1131 1132 out: 1133 return err; 1134 } 1135 1136 static ssize_t show_port_type(struct device *dev, 1137 struct device_attribute *attr, 1138 char *buf) 1139 { 1140 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1141 port_attr); 1142 struct mlx4_dev *mdev = info->dev; 1143 char type[8]; 1144 1145 sprintf(type, "%s", 1146 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ? 1147 "ib" : "eth"); 1148 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO) 1149 sprintf(buf, "auto (%s)\n", type); 1150 else 1151 sprintf(buf, "%s\n", type); 1152 1153 return strlen(buf); 1154 } 1155 1156 static int __set_port_type(struct mlx4_port_info *info, 1157 enum mlx4_port_type port_type) 1158 { 1159 struct mlx4_dev *mdev = info->dev; 1160 struct mlx4_priv *priv = mlx4_priv(mdev); 1161 enum mlx4_port_type types[MLX4_MAX_PORTS]; 1162 enum mlx4_port_type new_types[MLX4_MAX_PORTS]; 1163 int i; 1164 int err = 0; 1165 1166 if ((port_type & mdev->caps.supported_type[info->port]) != port_type) { 1167 mlx4_err(mdev, 1168 "Requested port type for port %d is not supported on this HCA\n", 1169 info->port); 1170 return -EOPNOTSUPP; 1171 } 1172 1173 mlx4_stop_sense(mdev); 1174 mutex_lock(&priv->port_mutex); 1175 info->tmp_type = port_type; 1176 1177 /* Possible type is always the one that was delivered */ 1178 mdev->caps.possible_type[info->port] = info->tmp_type; 1179 1180 for (i = 0; i < mdev->caps.num_ports; i++) { 1181 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type : 1182 mdev->caps.possible_type[i+1]; 1183 if (types[i] == MLX4_PORT_TYPE_AUTO) 1184 types[i] = mdev->caps.port_type[i+1]; 1185 } 1186 1187 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && 1188 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) { 1189 for (i = 1; i <= mdev->caps.num_ports; i++) { 1190 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) { 1191 mdev->caps.possible_type[i] = mdev->caps.port_type[i]; 1192 err = -EOPNOTSUPP; 1193 } 1194 } 1195 } 1196 if (err) { 1197 mlx4_err(mdev, "Auto sensing is not supported on this HCA. Set only 'eth' or 'ib' for both ports (should be the same)\n"); 1198 goto out; 1199 } 1200 1201 mlx4_do_sense_ports(mdev, new_types, types); 1202 1203 err = mlx4_check_port_params(mdev, new_types); 1204 if (err) 1205 goto out; 1206 1207 /* We are about to apply the changes after the configuration 1208 * was verified, no need to remember the temporary types 1209 * any more */ 1210 for (i = 0; i < mdev->caps.num_ports; i++) 1211 priv->port[i + 1].tmp_type = 0; 1212 1213 err = mlx4_change_port_types(mdev, new_types); 1214 1215 out: 1216 mlx4_start_sense(mdev); 1217 mutex_unlock(&priv->port_mutex); 1218 1219 return err; 1220 } 1221 1222 static ssize_t set_port_type(struct device *dev, 1223 struct device_attribute *attr, 1224 const char *buf, size_t count) 1225 { 1226 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1227 port_attr); 1228 struct mlx4_dev *mdev = info->dev; 1229 enum mlx4_port_type port_type; 1230 static DEFINE_MUTEX(set_port_type_mutex); 1231 int err; 1232 1233 mutex_lock(&set_port_type_mutex); 1234 1235 if (!strcmp(buf, "ib\n")) { 1236 port_type = MLX4_PORT_TYPE_IB; 1237 } else if (!strcmp(buf, "eth\n")) { 1238 port_type = MLX4_PORT_TYPE_ETH; 1239 } else if (!strcmp(buf, "auto\n")) { 1240 port_type = MLX4_PORT_TYPE_AUTO; 1241 } else { 1242 mlx4_err(mdev, "%s is not supported port type\n", buf); 1243 err = -EINVAL; 1244 goto err_out; 1245 } 1246 1247 err = __set_port_type(info, port_type); 1248 1249 err_out: 1250 mutex_unlock(&set_port_type_mutex); 1251 1252 return err ? err : count; 1253 } 1254 1255 enum ibta_mtu { 1256 IB_MTU_256 = 1, 1257 IB_MTU_512 = 2, 1258 IB_MTU_1024 = 3, 1259 IB_MTU_2048 = 4, 1260 IB_MTU_4096 = 5 1261 }; 1262 1263 static inline int int_to_ibta_mtu(int mtu) 1264 { 1265 switch (mtu) { 1266 case 256: return IB_MTU_256; 1267 case 512: return IB_MTU_512; 1268 case 1024: return IB_MTU_1024; 1269 case 2048: return IB_MTU_2048; 1270 case 4096: return IB_MTU_4096; 1271 default: return -1; 1272 } 1273 } 1274 1275 static inline int ibta_mtu_to_int(enum ibta_mtu mtu) 1276 { 1277 switch (mtu) { 1278 case IB_MTU_256: return 256; 1279 case IB_MTU_512: return 512; 1280 case IB_MTU_1024: return 1024; 1281 case IB_MTU_2048: return 2048; 1282 case IB_MTU_4096: return 4096; 1283 default: return -1; 1284 } 1285 } 1286 1287 static ssize_t show_port_ib_mtu(struct device *dev, 1288 struct device_attribute *attr, 1289 char *buf) 1290 { 1291 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1292 port_mtu_attr); 1293 struct mlx4_dev *mdev = info->dev; 1294 1295 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) 1296 mlx4_warn(mdev, "port level mtu is only used for IB ports\n"); 1297 1298 sprintf(buf, "%d\n", 1299 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port])); 1300 return strlen(buf); 1301 } 1302 1303 static ssize_t set_port_ib_mtu(struct device *dev, 1304 struct device_attribute *attr, 1305 const char *buf, size_t count) 1306 { 1307 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, 1308 port_mtu_attr); 1309 struct mlx4_dev *mdev = info->dev; 1310 struct mlx4_priv *priv = mlx4_priv(mdev); 1311 int err, port, mtu, ibta_mtu = -1; 1312 1313 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) { 1314 mlx4_warn(mdev, "port level mtu is only used for IB ports\n"); 1315 return -EINVAL; 1316 } 1317 1318 err = kstrtoint(buf, 0, &mtu); 1319 if (!err) 1320 ibta_mtu = int_to_ibta_mtu(mtu); 1321 1322 if (err || ibta_mtu < 0) { 1323 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf); 1324 return -EINVAL; 1325 } 1326 1327 mdev->caps.port_ib_mtu[info->port] = ibta_mtu; 1328 1329 mlx4_stop_sense(mdev); 1330 mutex_lock(&priv->port_mutex); 1331 mlx4_unregister_device(mdev); 1332 for (port = 1; port <= mdev->caps.num_ports; port++) { 1333 mlx4_CLOSE_PORT(mdev, port); 1334 err = mlx4_SET_PORT(mdev, port, -1); 1335 if (err) { 1336 mlx4_err(mdev, "Failed to set port %d, aborting\n", 1337 port); 1338 goto err_set_port; 1339 } 1340 } 1341 err = mlx4_register_device(mdev); 1342 err_set_port: 1343 mutex_unlock(&priv->port_mutex); 1344 mlx4_start_sense(mdev); 1345 return err ? err : count; 1346 } 1347 1348 /* bond for multi-function device */ 1349 #define MAX_MF_BOND_ALLOWED_SLAVES 63 1350 static int mlx4_mf_bond(struct mlx4_dev *dev) 1351 { 1352 int err = 0; 1353 int nvfs; 1354 struct mlx4_slaves_pport slaves_port1; 1355 struct mlx4_slaves_pport slaves_port2; 1356 1357 slaves_port1 = mlx4_phys_to_slaves_pport(dev, 1); 1358 slaves_port2 = mlx4_phys_to_slaves_pport(dev, 2); 1359 1360 /* only single port vfs are allowed */ 1361 if (bitmap_weight_and(slaves_port1.slaves, slaves_port2.slaves, 1362 dev->persist->num_vfs + 1) > 1) { 1363 mlx4_warn(dev, "HA mode unsupported for dual ported VFs\n"); 1364 return -EINVAL; 1365 } 1366 1367 /* number of virtual functions is number of total functions minus one 1368 * physical function for each port. 1369 */ 1370 nvfs = bitmap_weight(slaves_port1.slaves, dev->persist->num_vfs + 1) + 1371 bitmap_weight(slaves_port2.slaves, dev->persist->num_vfs + 1) - 2; 1372 1373 /* limit on maximum allowed VFs */ 1374 if (nvfs > MAX_MF_BOND_ALLOWED_SLAVES) { 1375 mlx4_warn(dev, "HA mode is not supported for %d VFs (max %d are allowed)\n", 1376 nvfs, MAX_MF_BOND_ALLOWED_SLAVES); 1377 return -EINVAL; 1378 } 1379 1380 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) { 1381 mlx4_warn(dev, "HA mode unsupported for NON DMFS steering\n"); 1382 return -EINVAL; 1383 } 1384 1385 err = mlx4_bond_mac_table(dev); 1386 if (err) 1387 return err; 1388 err = mlx4_bond_vlan_table(dev); 1389 if (err) 1390 goto err1; 1391 err = mlx4_bond_fs_rules(dev); 1392 if (err) 1393 goto err2; 1394 1395 return 0; 1396 err2: 1397 (void)mlx4_unbond_vlan_table(dev); 1398 err1: 1399 (void)mlx4_unbond_mac_table(dev); 1400 return err; 1401 } 1402 1403 static int mlx4_mf_unbond(struct mlx4_dev *dev) 1404 { 1405 int ret, ret1; 1406 1407 ret = mlx4_unbond_fs_rules(dev); 1408 if (ret) 1409 mlx4_warn(dev, "multifunction unbond for flow rules failed (%d)\n", ret); 1410 ret1 = mlx4_unbond_mac_table(dev); 1411 if (ret1) { 1412 mlx4_warn(dev, "multifunction unbond for MAC table failed (%d)\n", ret1); 1413 ret = ret1; 1414 } 1415 ret1 = mlx4_unbond_vlan_table(dev); 1416 if (ret1) { 1417 mlx4_warn(dev, "multifunction unbond for VLAN table failed (%d)\n", ret1); 1418 ret = ret1; 1419 } 1420 return ret; 1421 } 1422 1423 static int mlx4_bond(struct mlx4_dev *dev) 1424 { 1425 int ret = 0; 1426 struct mlx4_priv *priv = mlx4_priv(dev); 1427 1428 mutex_lock(&priv->bond_mutex); 1429 1430 if (!mlx4_is_bonded(dev)) { 1431 ret = mlx4_do_bond(dev, true); 1432 if (ret) 1433 mlx4_err(dev, "Failed to bond device: %d\n", ret); 1434 if (!ret && mlx4_is_master(dev)) { 1435 ret = mlx4_mf_bond(dev); 1436 if (ret) { 1437 mlx4_err(dev, "bond for multifunction failed\n"); 1438 mlx4_do_bond(dev, false); 1439 } 1440 } 1441 } 1442 1443 mutex_unlock(&priv->bond_mutex); 1444 if (!ret) 1445 mlx4_dbg(dev, "Device is bonded\n"); 1446 1447 return ret; 1448 } 1449 1450 static int mlx4_unbond(struct mlx4_dev *dev) 1451 { 1452 int ret = 0; 1453 struct mlx4_priv *priv = mlx4_priv(dev); 1454 1455 mutex_lock(&priv->bond_mutex); 1456 1457 if (mlx4_is_bonded(dev)) { 1458 int ret2 = 0; 1459 1460 ret = mlx4_do_bond(dev, false); 1461 if (ret) 1462 mlx4_err(dev, "Failed to unbond device: %d\n", ret); 1463 if (mlx4_is_master(dev)) 1464 ret2 = mlx4_mf_unbond(dev); 1465 if (ret2) { 1466 mlx4_warn(dev, "Failed to unbond device for multifunction (%d)\n", ret2); 1467 ret = ret2; 1468 } 1469 } 1470 1471 mutex_unlock(&priv->bond_mutex); 1472 if (!ret) 1473 mlx4_dbg(dev, "Device is unbonded\n"); 1474 1475 return ret; 1476 } 1477 1478 static int mlx4_port_map_set(struct mlx4_dev *dev, struct mlx4_port_map *v2p) 1479 { 1480 u8 port1 = v2p->port1; 1481 u8 port2 = v2p->port2; 1482 struct mlx4_priv *priv = mlx4_priv(dev); 1483 int err; 1484 1485 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_REMAP)) 1486 return -EOPNOTSUPP; 1487 1488 mutex_lock(&priv->bond_mutex); 1489 1490 /* zero means keep current mapping for this port */ 1491 if (port1 == 0) 1492 port1 = priv->v2p.port1; 1493 if (port2 == 0) 1494 port2 = priv->v2p.port2; 1495 1496 if ((port1 < 1) || (port1 > MLX4_MAX_PORTS) || 1497 (port2 < 1) || (port2 > MLX4_MAX_PORTS) || 1498 (port1 == 2 && port2 == 1)) { 1499 /* besides boundary checks cross mapping makes 1500 * no sense and therefore not allowed */ 1501 err = -EINVAL; 1502 } else if ((port1 == priv->v2p.port1) && 1503 (port2 == priv->v2p.port2)) { 1504 err = 0; 1505 } else { 1506 err = mlx4_virt2phy_port_map(dev, port1, port2); 1507 if (!err) { 1508 mlx4_dbg(dev, "port map changed: [%d][%d]\n", 1509 port1, port2); 1510 priv->v2p.port1 = port1; 1511 priv->v2p.port2 = port2; 1512 } else { 1513 mlx4_err(dev, "Failed to change port map: %d\n", err); 1514 } 1515 } 1516 1517 mutex_unlock(&priv->bond_mutex); 1518 return err; 1519 } 1520 1521 struct mlx4_bond { 1522 struct work_struct work; 1523 struct mlx4_dev *dev; 1524 int is_bonded; 1525 struct mlx4_port_map port_map; 1526 }; 1527 1528 static void mlx4_bond_work(struct work_struct *work) 1529 { 1530 struct mlx4_bond *bond = container_of(work, struct mlx4_bond, work); 1531 int err = 0; 1532 1533 if (bond->is_bonded) { 1534 if (!mlx4_is_bonded(bond->dev)) { 1535 err = mlx4_bond(bond->dev); 1536 if (err) 1537 mlx4_err(bond->dev, "Fail to bond device\n"); 1538 } 1539 if (!err) { 1540 err = mlx4_port_map_set(bond->dev, &bond->port_map); 1541 if (err) 1542 mlx4_err(bond->dev, 1543 "Fail to set port map [%d][%d]: %d\n", 1544 bond->port_map.port1, 1545 bond->port_map.port2, err); 1546 } 1547 } else if (mlx4_is_bonded(bond->dev)) { 1548 err = mlx4_unbond(bond->dev); 1549 if (err) 1550 mlx4_err(bond->dev, "Fail to unbond device\n"); 1551 } 1552 put_device(&bond->dev->persist->pdev->dev); 1553 kfree(bond); 1554 } 1555 1556 int mlx4_queue_bond_work(struct mlx4_dev *dev, int is_bonded, u8 v2p_p1, 1557 u8 v2p_p2) 1558 { 1559 struct mlx4_bond *bond; 1560 1561 bond = kzalloc(sizeof(*bond), GFP_ATOMIC); 1562 if (!bond) 1563 return -ENOMEM; 1564 1565 INIT_WORK(&bond->work, mlx4_bond_work); 1566 get_device(&dev->persist->pdev->dev); 1567 bond->dev = dev; 1568 bond->is_bonded = is_bonded; 1569 bond->port_map.port1 = v2p_p1; 1570 bond->port_map.port2 = v2p_p2; 1571 queue_work(mlx4_wq, &bond->work); 1572 return 0; 1573 } 1574 EXPORT_SYMBOL(mlx4_queue_bond_work); 1575 1576 static int mlx4_load_fw(struct mlx4_dev *dev) 1577 { 1578 struct mlx4_priv *priv = mlx4_priv(dev); 1579 int err; 1580 1581 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages, 1582 GFP_HIGHUSER | __GFP_NOWARN, 0); 1583 if (!priv->fw.fw_icm) { 1584 mlx4_err(dev, "Couldn't allocate FW area, aborting\n"); 1585 return -ENOMEM; 1586 } 1587 1588 err = mlx4_MAP_FA(dev, priv->fw.fw_icm); 1589 if (err) { 1590 mlx4_err(dev, "MAP_FA command failed, aborting\n"); 1591 goto err_free; 1592 } 1593 1594 err = mlx4_RUN_FW(dev); 1595 if (err) { 1596 mlx4_err(dev, "RUN_FW command failed, aborting\n"); 1597 goto err_unmap_fa; 1598 } 1599 1600 return 0; 1601 1602 err_unmap_fa: 1603 mlx4_UNMAP_FA(dev); 1604 1605 err_free: 1606 mlx4_free_icm(dev, priv->fw.fw_icm, 0); 1607 return err; 1608 } 1609 1610 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base, 1611 int cmpt_entry_sz) 1612 { 1613 struct mlx4_priv *priv = mlx4_priv(dev); 1614 int err; 1615 int num_eqs; 1616 1617 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table, 1618 cmpt_base + 1619 ((u64) (MLX4_CMPT_TYPE_QP * 1620 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1621 cmpt_entry_sz, dev->caps.num_qps, 1622 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1623 0, 0); 1624 if (err) 1625 goto err; 1626 1627 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table, 1628 cmpt_base + 1629 ((u64) (MLX4_CMPT_TYPE_SRQ * 1630 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1631 cmpt_entry_sz, dev->caps.num_srqs, 1632 dev->caps.reserved_srqs, 0, 0); 1633 if (err) 1634 goto err_qp; 1635 1636 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table, 1637 cmpt_base + 1638 ((u64) (MLX4_CMPT_TYPE_CQ * 1639 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1640 cmpt_entry_sz, dev->caps.num_cqs, 1641 dev->caps.reserved_cqs, 0, 0); 1642 if (err) 1643 goto err_srq; 1644 1645 num_eqs = dev->phys_caps.num_phys_eqs; 1646 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table, 1647 cmpt_base + 1648 ((u64) (MLX4_CMPT_TYPE_EQ * 1649 cmpt_entry_sz) << MLX4_CMPT_SHIFT), 1650 cmpt_entry_sz, num_eqs, num_eqs, 0, 0); 1651 if (err) 1652 goto err_cq; 1653 1654 return 0; 1655 1656 err_cq: 1657 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1658 1659 err_srq: 1660 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1661 1662 err_qp: 1663 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1664 1665 err: 1666 return err; 1667 } 1668 1669 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap, 1670 struct mlx4_init_hca_param *init_hca, u64 icm_size) 1671 { 1672 struct mlx4_priv *priv = mlx4_priv(dev); 1673 u64 aux_pages; 1674 int num_eqs; 1675 int err; 1676 1677 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages); 1678 if (err) { 1679 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting\n"); 1680 return err; 1681 } 1682 1683 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory\n", 1684 (unsigned long long) icm_size >> 10, 1685 (unsigned long long) aux_pages << 2); 1686 1687 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages, 1688 GFP_HIGHUSER | __GFP_NOWARN, 0); 1689 if (!priv->fw.aux_icm) { 1690 mlx4_err(dev, "Couldn't allocate aux memory, aborting\n"); 1691 return -ENOMEM; 1692 } 1693 1694 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm); 1695 if (err) { 1696 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting\n"); 1697 goto err_free_aux; 1698 } 1699 1700 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz); 1701 if (err) { 1702 mlx4_err(dev, "Failed to map cMPT context memory, aborting\n"); 1703 goto err_unmap_aux; 1704 } 1705 1706 1707 num_eqs = dev->phys_caps.num_phys_eqs; 1708 err = mlx4_init_icm_table(dev, &priv->eq_table.table, 1709 init_hca->eqc_base, dev_cap->eqc_entry_sz, 1710 num_eqs, num_eqs, 0, 0); 1711 if (err) { 1712 mlx4_err(dev, "Failed to map EQ context memory, aborting\n"); 1713 goto err_unmap_cmpt; 1714 } 1715 1716 /* 1717 * Reserved MTT entries must be aligned up to a cacheline 1718 * boundary, since the FW will write to them, while the driver 1719 * writes to all other MTT entries. (The variable 1720 * dev->caps.mtt_entry_sz below is really the MTT segment 1721 * size, not the raw entry size) 1722 */ 1723 dev->caps.reserved_mtts = 1724 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz, 1725 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz; 1726 1727 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table, 1728 init_hca->mtt_base, 1729 dev->caps.mtt_entry_sz, 1730 dev->caps.num_mtts, 1731 dev->caps.reserved_mtts, 1, 0); 1732 if (err) { 1733 mlx4_err(dev, "Failed to map MTT context memory, aborting\n"); 1734 goto err_unmap_eq; 1735 } 1736 1737 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table, 1738 init_hca->dmpt_base, 1739 dev_cap->dmpt_entry_sz, 1740 dev->caps.num_mpts, 1741 dev->caps.reserved_mrws, 1, 1); 1742 if (err) { 1743 mlx4_err(dev, "Failed to map dMPT context memory, aborting\n"); 1744 goto err_unmap_mtt; 1745 } 1746 1747 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table, 1748 init_hca->qpc_base, 1749 dev_cap->qpc_entry_sz, 1750 dev->caps.num_qps, 1751 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1752 0, 0); 1753 if (err) { 1754 mlx4_err(dev, "Failed to map QP context memory, aborting\n"); 1755 goto err_unmap_dmpt; 1756 } 1757 1758 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table, 1759 init_hca->auxc_base, 1760 dev_cap->aux_entry_sz, 1761 dev->caps.num_qps, 1762 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1763 0, 0); 1764 if (err) { 1765 mlx4_err(dev, "Failed to map AUXC context memory, aborting\n"); 1766 goto err_unmap_qp; 1767 } 1768 1769 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table, 1770 init_hca->altc_base, 1771 dev_cap->altc_entry_sz, 1772 dev->caps.num_qps, 1773 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1774 0, 0); 1775 if (err) { 1776 mlx4_err(dev, "Failed to map ALTC context memory, aborting\n"); 1777 goto err_unmap_auxc; 1778 } 1779 1780 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table, 1781 init_hca->rdmarc_base, 1782 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift, 1783 dev->caps.num_qps, 1784 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 1785 0, 0); 1786 if (err) { 1787 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n"); 1788 goto err_unmap_altc; 1789 } 1790 1791 err = mlx4_init_icm_table(dev, &priv->cq_table.table, 1792 init_hca->cqc_base, 1793 dev_cap->cqc_entry_sz, 1794 dev->caps.num_cqs, 1795 dev->caps.reserved_cqs, 0, 0); 1796 if (err) { 1797 mlx4_err(dev, "Failed to map CQ context memory, aborting\n"); 1798 goto err_unmap_rdmarc; 1799 } 1800 1801 err = mlx4_init_icm_table(dev, &priv->srq_table.table, 1802 init_hca->srqc_base, 1803 dev_cap->srq_entry_sz, 1804 dev->caps.num_srqs, 1805 dev->caps.reserved_srqs, 0, 0); 1806 if (err) { 1807 mlx4_err(dev, "Failed to map SRQ context memory, aborting\n"); 1808 goto err_unmap_cq; 1809 } 1810 1811 /* 1812 * For flow steering device managed mode it is required to use 1813 * mlx4_init_icm_table. For B0 steering mode it's not strictly 1814 * required, but for simplicity just map the whole multicast 1815 * group table now. The table isn't very big and it's a lot 1816 * easier than trying to track ref counts. 1817 */ 1818 err = mlx4_init_icm_table(dev, &priv->mcg_table.table, 1819 init_hca->mc_base, 1820 mlx4_get_mgm_entry_size(dev), 1821 dev->caps.num_mgms + dev->caps.num_amgms, 1822 dev->caps.num_mgms + dev->caps.num_amgms, 1823 0, 0); 1824 if (err) { 1825 mlx4_err(dev, "Failed to map MCG context memory, aborting\n"); 1826 goto err_unmap_srq; 1827 } 1828 1829 return 0; 1830 1831 err_unmap_srq: 1832 mlx4_cleanup_icm_table(dev, &priv->srq_table.table); 1833 1834 err_unmap_cq: 1835 mlx4_cleanup_icm_table(dev, &priv->cq_table.table); 1836 1837 err_unmap_rdmarc: 1838 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); 1839 1840 err_unmap_altc: 1841 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); 1842 1843 err_unmap_auxc: 1844 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); 1845 1846 err_unmap_qp: 1847 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); 1848 1849 err_unmap_dmpt: 1850 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); 1851 1852 err_unmap_mtt: 1853 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); 1854 1855 err_unmap_eq: 1856 mlx4_cleanup_icm_table(dev, &priv->eq_table.table); 1857 1858 err_unmap_cmpt: 1859 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); 1860 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1861 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1862 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1863 1864 err_unmap_aux: 1865 mlx4_UNMAP_ICM_AUX(dev); 1866 1867 err_free_aux: 1868 mlx4_free_icm(dev, priv->fw.aux_icm, 0); 1869 1870 return err; 1871 } 1872 1873 static void mlx4_free_icms(struct mlx4_dev *dev) 1874 { 1875 struct mlx4_priv *priv = mlx4_priv(dev); 1876 1877 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table); 1878 mlx4_cleanup_icm_table(dev, &priv->srq_table.table); 1879 mlx4_cleanup_icm_table(dev, &priv->cq_table.table); 1880 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); 1881 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); 1882 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); 1883 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); 1884 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); 1885 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); 1886 mlx4_cleanup_icm_table(dev, &priv->eq_table.table); 1887 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); 1888 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); 1889 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); 1890 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); 1891 1892 mlx4_UNMAP_ICM_AUX(dev); 1893 mlx4_free_icm(dev, priv->fw.aux_icm, 0); 1894 } 1895 1896 static void mlx4_slave_exit(struct mlx4_dev *dev) 1897 { 1898 struct mlx4_priv *priv = mlx4_priv(dev); 1899 1900 mutex_lock(&priv->cmd.slave_cmd_mutex); 1901 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP, 1902 MLX4_COMM_TIME)) 1903 mlx4_warn(dev, "Failed to close slave function\n"); 1904 mutex_unlock(&priv->cmd.slave_cmd_mutex); 1905 } 1906 1907 static int map_bf_area(struct mlx4_dev *dev) 1908 { 1909 struct mlx4_priv *priv = mlx4_priv(dev); 1910 resource_size_t bf_start; 1911 resource_size_t bf_len; 1912 int err = 0; 1913 1914 if (!dev->caps.bf_reg_size) 1915 return -ENXIO; 1916 1917 bf_start = pci_resource_start(dev->persist->pdev, 2) + 1918 (dev->caps.num_uars << PAGE_SHIFT); 1919 bf_len = pci_resource_len(dev->persist->pdev, 2) - 1920 (dev->caps.num_uars << PAGE_SHIFT); 1921 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len); 1922 if (!priv->bf_mapping) 1923 err = -ENOMEM; 1924 1925 return err; 1926 } 1927 1928 static void unmap_bf_area(struct mlx4_dev *dev) 1929 { 1930 if (mlx4_priv(dev)->bf_mapping) 1931 io_mapping_free(mlx4_priv(dev)->bf_mapping); 1932 } 1933 1934 u64 mlx4_read_clock(struct mlx4_dev *dev) 1935 { 1936 u32 clockhi, clocklo, clockhi1; 1937 u64 cycles; 1938 int i; 1939 struct mlx4_priv *priv = mlx4_priv(dev); 1940 1941 for (i = 0; i < 10; i++) { 1942 clockhi = swab32(readl(priv->clock_mapping)); 1943 clocklo = swab32(readl(priv->clock_mapping + 4)); 1944 clockhi1 = swab32(readl(priv->clock_mapping)); 1945 if (clockhi == clockhi1) 1946 break; 1947 } 1948 1949 cycles = (u64) clockhi << 32 | (u64) clocklo; 1950 1951 return cycles; 1952 } 1953 EXPORT_SYMBOL_GPL(mlx4_read_clock); 1954 1955 1956 static int map_internal_clock(struct mlx4_dev *dev) 1957 { 1958 struct mlx4_priv *priv = mlx4_priv(dev); 1959 1960 priv->clock_mapping = 1961 ioremap(pci_resource_start(dev->persist->pdev, 1962 priv->fw.clock_bar) + 1963 priv->fw.clock_offset, MLX4_CLOCK_SIZE); 1964 1965 if (!priv->clock_mapping) 1966 return -ENOMEM; 1967 1968 return 0; 1969 } 1970 1971 int mlx4_get_internal_clock_params(struct mlx4_dev *dev, 1972 struct mlx4_clock_params *params) 1973 { 1974 struct mlx4_priv *priv = mlx4_priv(dev); 1975 1976 if (mlx4_is_slave(dev)) 1977 return -EOPNOTSUPP; 1978 1979 if (!dev->caps.map_clock_to_user) { 1980 mlx4_dbg(dev, "Map clock to user is not supported.\n"); 1981 return -EOPNOTSUPP; 1982 } 1983 1984 if (!params) 1985 return -EINVAL; 1986 1987 params->bar = priv->fw.clock_bar; 1988 params->offset = priv->fw.clock_offset; 1989 params->size = MLX4_CLOCK_SIZE; 1990 1991 return 0; 1992 } 1993 EXPORT_SYMBOL_GPL(mlx4_get_internal_clock_params); 1994 1995 static void unmap_internal_clock(struct mlx4_dev *dev) 1996 { 1997 struct mlx4_priv *priv = mlx4_priv(dev); 1998 1999 if (priv->clock_mapping) 2000 iounmap(priv->clock_mapping); 2001 } 2002 2003 static void mlx4_close_hca(struct mlx4_dev *dev) 2004 { 2005 unmap_internal_clock(dev); 2006 unmap_bf_area(dev); 2007 if (mlx4_is_slave(dev)) 2008 mlx4_slave_exit(dev); 2009 else { 2010 mlx4_CLOSE_HCA(dev, 0); 2011 mlx4_free_icms(dev); 2012 } 2013 } 2014 2015 static void mlx4_close_fw(struct mlx4_dev *dev) 2016 { 2017 if (!mlx4_is_slave(dev)) { 2018 mlx4_UNMAP_FA(dev); 2019 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0); 2020 } 2021 } 2022 2023 static int mlx4_comm_check_offline(struct mlx4_dev *dev) 2024 { 2025 #define COMM_CHAN_OFFLINE_OFFSET 0x09 2026 2027 u32 comm_flags; 2028 u32 offline_bit; 2029 unsigned long end; 2030 struct mlx4_priv *priv = mlx4_priv(dev); 2031 2032 end = msecs_to_jiffies(MLX4_COMM_OFFLINE_TIME_OUT) + jiffies; 2033 while (time_before(jiffies, end)) { 2034 comm_flags = swab32(readl((__iomem char *)priv->mfunc.comm + 2035 MLX4_COMM_CHAN_FLAGS)); 2036 offline_bit = (comm_flags & 2037 (u32)(1 << COMM_CHAN_OFFLINE_OFFSET)); 2038 if (!offline_bit) 2039 return 0; 2040 2041 /* If device removal has been requested, 2042 * do not continue retrying. 2043 */ 2044 if (dev->persist->interface_state & 2045 MLX4_INTERFACE_STATE_NOWAIT) 2046 break; 2047 2048 /* There are cases as part of AER/Reset flow that PF needs 2049 * around 100 msec to load. We therefore sleep for 100 msec 2050 * to allow other tasks to make use of that CPU during this 2051 * time interval. 2052 */ 2053 msleep(100); 2054 } 2055 mlx4_err(dev, "Communication channel is offline.\n"); 2056 return -EIO; 2057 } 2058 2059 static void mlx4_reset_vf_support(struct mlx4_dev *dev) 2060 { 2061 #define COMM_CHAN_RST_OFFSET 0x1e 2062 2063 struct mlx4_priv *priv = mlx4_priv(dev); 2064 u32 comm_rst; 2065 u32 comm_caps; 2066 2067 comm_caps = swab32(readl((__iomem char *)priv->mfunc.comm + 2068 MLX4_COMM_CHAN_CAPS)); 2069 comm_rst = (comm_caps & (u32)(1 << COMM_CHAN_RST_OFFSET)); 2070 2071 if (comm_rst) 2072 dev->caps.vf_caps |= MLX4_VF_CAP_FLAG_RESET; 2073 } 2074 2075 static int mlx4_init_slave(struct mlx4_dev *dev) 2076 { 2077 struct mlx4_priv *priv = mlx4_priv(dev); 2078 u64 dma = (u64) priv->mfunc.vhcr_dma; 2079 int ret_from_reset = 0; 2080 u32 slave_read; 2081 u32 cmd_channel_ver; 2082 2083 if (atomic_read(&pf_loading)) { 2084 mlx4_warn(dev, "PF is not ready - Deferring probe\n"); 2085 return -EPROBE_DEFER; 2086 } 2087 2088 mutex_lock(&priv->cmd.slave_cmd_mutex); 2089 priv->cmd.max_cmds = 1; 2090 if (mlx4_comm_check_offline(dev)) { 2091 mlx4_err(dev, "PF is not responsive, skipping initialization\n"); 2092 goto err_offline; 2093 } 2094 2095 mlx4_reset_vf_support(dev); 2096 mlx4_warn(dev, "Sending reset\n"); 2097 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 2098 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME); 2099 /* if we are in the middle of flr the slave will try 2100 * NUM_OF_RESET_RETRIES times before leaving.*/ 2101 if (ret_from_reset) { 2102 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) { 2103 mlx4_warn(dev, "slave is currently in the middle of FLR - Deferring probe\n"); 2104 mutex_unlock(&priv->cmd.slave_cmd_mutex); 2105 return -EPROBE_DEFER; 2106 } else 2107 goto err; 2108 } 2109 2110 /* check the driver version - the slave I/F revision 2111 * must match the master's */ 2112 slave_read = swab32(readl(&priv->mfunc.comm->slave_read)); 2113 cmd_channel_ver = mlx4_comm_get_version(); 2114 2115 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) != 2116 MLX4_COMM_GET_IF_REV(slave_read)) { 2117 mlx4_err(dev, "slave driver version is not supported by the master\n"); 2118 goto err; 2119 } 2120 2121 mlx4_warn(dev, "Sending vhcr0\n"); 2122 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48, 2123 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME)) 2124 goto err; 2125 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32, 2126 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME)) 2127 goto err; 2128 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16, 2129 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME)) 2130 goto err; 2131 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, 2132 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME)) 2133 goto err; 2134 2135 mutex_unlock(&priv->cmd.slave_cmd_mutex); 2136 return 0; 2137 2138 err: 2139 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP, 0); 2140 err_offline: 2141 mutex_unlock(&priv->cmd.slave_cmd_mutex); 2142 return -EIO; 2143 } 2144 2145 static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev) 2146 { 2147 int i; 2148 2149 for (i = 1; i <= dev->caps.num_ports; i++) { 2150 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH) 2151 dev->caps.gid_table_len[i] = 2152 mlx4_get_slave_num_gids(dev, 0, i); 2153 else 2154 dev->caps.gid_table_len[i] = 1; 2155 dev->caps.pkey_table_len[i] = 2156 dev->phys_caps.pkey_phys_table_len[i] - 1; 2157 } 2158 } 2159 2160 static int choose_log_fs_mgm_entry_size(int qp_per_entry) 2161 { 2162 int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; 2163 2164 for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE; 2165 i++) { 2166 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2)) 2167 break; 2168 } 2169 2170 return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1; 2171 } 2172 2173 static const char *dmfs_high_rate_steering_mode_str(int dmfs_high_steer_mode) 2174 { 2175 switch (dmfs_high_steer_mode) { 2176 case MLX4_STEERING_DMFS_A0_DEFAULT: 2177 return "default performance"; 2178 2179 case MLX4_STEERING_DMFS_A0_DYNAMIC: 2180 return "dynamic hybrid mode"; 2181 2182 case MLX4_STEERING_DMFS_A0_STATIC: 2183 return "performance optimized for limited rule configuration (static)"; 2184 2185 case MLX4_STEERING_DMFS_A0_DISABLE: 2186 return "disabled performance optimized steering"; 2187 2188 case MLX4_STEERING_DMFS_A0_NOT_SUPPORTED: 2189 return "performance optimized steering not supported"; 2190 2191 default: 2192 return "Unrecognized mode"; 2193 } 2194 } 2195 2196 #define MLX4_DMFS_A0_STEERING (1UL << 2) 2197 2198 static void choose_steering_mode(struct mlx4_dev *dev, 2199 struct mlx4_dev_cap *dev_cap) 2200 { 2201 if (mlx4_log_num_mgm_entry_size <= 0) { 2202 if ((-mlx4_log_num_mgm_entry_size) & MLX4_DMFS_A0_STEERING) { 2203 if (dev->caps.dmfs_high_steer_mode == 2204 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) 2205 mlx4_err(dev, "DMFS high rate mode not supported\n"); 2206 else 2207 dev->caps.dmfs_high_steer_mode = 2208 MLX4_STEERING_DMFS_A0_STATIC; 2209 } 2210 } 2211 2212 if (mlx4_log_num_mgm_entry_size <= 0 && 2213 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN && 2214 (!mlx4_is_mfunc(dev) || 2215 (dev_cap->fs_max_num_qp_per_entry >= 2216 (dev->persist->num_vfs + 1))) && 2217 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >= 2218 MLX4_MIN_MGM_LOG_ENTRY_SIZE) { 2219 dev->oper_log_mgm_entry_size = 2220 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry); 2221 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED; 2222 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry; 2223 dev->caps.fs_log_max_ucast_qp_range_size = 2224 dev_cap->fs_log_max_ucast_qp_range_size; 2225 } else { 2226 if (dev->caps.dmfs_high_steer_mode != 2227 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) 2228 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DISABLE; 2229 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER && 2230 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) 2231 dev->caps.steering_mode = MLX4_STEERING_MODE_B0; 2232 else { 2233 dev->caps.steering_mode = MLX4_STEERING_MODE_A0; 2234 2235 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER || 2236 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) 2237 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back to A0 steering mode\n"); 2238 } 2239 dev->oper_log_mgm_entry_size = 2240 mlx4_log_num_mgm_entry_size > 0 ? 2241 mlx4_log_num_mgm_entry_size : 2242 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE; 2243 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev); 2244 } 2245 mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, modparam log_num_mgm_entry_size = %d\n", 2246 mlx4_steering_mode_str(dev->caps.steering_mode), 2247 dev->oper_log_mgm_entry_size, 2248 mlx4_log_num_mgm_entry_size); 2249 } 2250 2251 static void choose_tunnel_offload_mode(struct mlx4_dev *dev, 2252 struct mlx4_dev_cap *dev_cap) 2253 { 2254 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED && 2255 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) 2256 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN; 2257 else 2258 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE; 2259 2260 mlx4_dbg(dev, "Tunneling offload mode is: %s\n", (dev->caps.tunnel_offload_mode 2261 == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none"); 2262 } 2263 2264 static int mlx4_validate_optimized_steering(struct mlx4_dev *dev) 2265 { 2266 int i; 2267 struct mlx4_port_cap port_cap; 2268 2269 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) 2270 return -EINVAL; 2271 2272 for (i = 1; i <= dev->caps.num_ports; i++) { 2273 if (mlx4_dev_port(dev, i, &port_cap)) { 2274 mlx4_err(dev, 2275 "QUERY_DEV_CAP command failed, can't verify DMFS high rate steering.\n"); 2276 } else if ((dev->caps.dmfs_high_steer_mode != 2277 MLX4_STEERING_DMFS_A0_DEFAULT) && 2278 (port_cap.dmfs_optimized_state == 2279 !!(dev->caps.dmfs_high_steer_mode == 2280 MLX4_STEERING_DMFS_A0_DISABLE))) { 2281 mlx4_err(dev, 2282 "DMFS high rate steer mode differ, driver requested %s but %s in FW.\n", 2283 dmfs_high_rate_steering_mode_str( 2284 dev->caps.dmfs_high_steer_mode), 2285 (port_cap.dmfs_optimized_state ? 2286 "enabled" : "disabled")); 2287 } 2288 } 2289 2290 return 0; 2291 } 2292 2293 static int mlx4_init_fw(struct mlx4_dev *dev) 2294 { 2295 struct mlx4_mod_stat_cfg mlx4_cfg; 2296 int err = 0; 2297 2298 if (!mlx4_is_slave(dev)) { 2299 err = mlx4_QUERY_FW(dev); 2300 if (err) { 2301 if (err == -EACCES) 2302 mlx4_info(dev, "non-primary physical function, skipping\n"); 2303 else 2304 mlx4_err(dev, "QUERY_FW command failed, aborting\n"); 2305 return err; 2306 } 2307 2308 err = mlx4_load_fw(dev); 2309 if (err) { 2310 mlx4_err(dev, "Failed to start FW, aborting\n"); 2311 return err; 2312 } 2313 2314 mlx4_cfg.log_pg_sz_m = 1; 2315 mlx4_cfg.log_pg_sz = 0; 2316 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg); 2317 if (err) 2318 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n"); 2319 } 2320 2321 return err; 2322 } 2323 2324 static int mlx4_init_hca(struct mlx4_dev *dev) 2325 { 2326 struct mlx4_priv *priv = mlx4_priv(dev); 2327 struct mlx4_init_hca_param *init_hca = NULL; 2328 struct mlx4_dev_cap *dev_cap = NULL; 2329 struct mlx4_adapter adapter; 2330 struct mlx4_profile profile; 2331 u64 icm_size; 2332 struct mlx4_config_dev_params params; 2333 int err; 2334 2335 if (!mlx4_is_slave(dev)) { 2336 dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL); 2337 init_hca = kzalloc(sizeof(*init_hca), GFP_KERNEL); 2338 2339 if (!dev_cap || !init_hca) { 2340 err = -ENOMEM; 2341 goto out_free; 2342 } 2343 2344 err = mlx4_dev_cap(dev, dev_cap); 2345 if (err) { 2346 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n"); 2347 goto out_free; 2348 } 2349 2350 choose_steering_mode(dev, dev_cap); 2351 choose_tunnel_offload_mode(dev, dev_cap); 2352 2353 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC && 2354 mlx4_is_master(dev)) 2355 dev->caps.function_caps |= MLX4_FUNC_CAP_DMFS_A0_STATIC; 2356 2357 err = mlx4_get_phys_port_id(dev); 2358 if (err) 2359 mlx4_err(dev, "Fail to get physical port id\n"); 2360 2361 if (mlx4_is_master(dev)) 2362 mlx4_parav_master_pf_caps(dev); 2363 2364 if (mlx4_low_memory_profile()) { 2365 mlx4_info(dev, "Running from within kdump kernel. Using low memory profile\n"); 2366 profile = low_mem_profile; 2367 } else { 2368 profile = default_profile; 2369 } 2370 if (dev->caps.steering_mode == 2371 MLX4_STEERING_MODE_DEVICE_MANAGED) 2372 profile.num_mcg = MLX4_FS_NUM_MCG; 2373 2374 icm_size = mlx4_make_profile(dev, &profile, dev_cap, 2375 init_hca); 2376 if ((long long) icm_size < 0) { 2377 err = icm_size; 2378 goto out_free; 2379 } 2380 2381 if (enable_4k_uar || !dev->persist->num_vfs) { 2382 init_hca->log_uar_sz = ilog2(dev->caps.num_uars) + 2383 PAGE_SHIFT - DEFAULT_UAR_PAGE_SHIFT; 2384 init_hca->uar_page_sz = DEFAULT_UAR_PAGE_SHIFT - 12; 2385 } else { 2386 init_hca->log_uar_sz = ilog2(dev->caps.num_uars); 2387 init_hca->uar_page_sz = PAGE_SHIFT - 12; 2388 } 2389 2390 init_hca->mw_enabled = 0; 2391 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW || 2392 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) 2393 init_hca->mw_enabled = INIT_HCA_TPT_MW_ENABLE; 2394 2395 err = mlx4_init_icm(dev, dev_cap, init_hca, icm_size); 2396 if (err) 2397 goto out_free; 2398 2399 err = mlx4_INIT_HCA(dev, init_hca); 2400 if (err) { 2401 mlx4_err(dev, "INIT_HCA command failed, aborting\n"); 2402 goto err_free_icm; 2403 } 2404 2405 if (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) { 2406 err = mlx4_query_func(dev, dev_cap); 2407 if (err < 0) { 2408 mlx4_err(dev, "QUERY_FUNC command failed, aborting.\n"); 2409 goto err_close; 2410 } else if (err & MLX4_QUERY_FUNC_NUM_SYS_EQS) { 2411 dev->caps.num_eqs = dev_cap->max_eqs; 2412 dev->caps.reserved_eqs = dev_cap->reserved_eqs; 2413 dev->caps.reserved_uars = dev_cap->reserved_uars; 2414 } 2415 } 2416 2417 /* 2418 * If TS is supported by FW 2419 * read HCA frequency by QUERY_HCA command 2420 */ 2421 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) { 2422 err = mlx4_QUERY_HCA(dev, init_hca); 2423 if (err) { 2424 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp\n"); 2425 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 2426 } else { 2427 dev->caps.hca_core_clock = 2428 init_hca->hca_core_clock; 2429 } 2430 2431 /* In case we got HCA frequency 0 - disable timestamping 2432 * to avoid dividing by zero 2433 */ 2434 if (!dev->caps.hca_core_clock) { 2435 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 2436 mlx4_err(dev, 2437 "HCA frequency is 0 - timestamping is not supported\n"); 2438 } else if (map_internal_clock(dev)) { 2439 /* 2440 * Map internal clock, 2441 * in case of failure disable timestamping 2442 */ 2443 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; 2444 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported\n"); 2445 } 2446 } 2447 2448 if (dev->caps.dmfs_high_steer_mode != 2449 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) { 2450 if (mlx4_validate_optimized_steering(dev)) 2451 mlx4_warn(dev, "Optimized steering validation failed\n"); 2452 2453 if (dev->caps.dmfs_high_steer_mode == 2454 MLX4_STEERING_DMFS_A0_DISABLE) { 2455 dev->caps.dmfs_high_rate_qpn_base = 2456 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]; 2457 dev->caps.dmfs_high_rate_qpn_range = 2458 MLX4_A0_STEERING_TABLE_SIZE; 2459 } 2460 2461 mlx4_info(dev, "DMFS high rate steer mode is: %s\n", 2462 dmfs_high_rate_steering_mode_str( 2463 dev->caps.dmfs_high_steer_mode)); 2464 } 2465 } else { 2466 err = mlx4_init_slave(dev); 2467 if (err) { 2468 if (err != -EPROBE_DEFER) 2469 mlx4_err(dev, "Failed to initialize slave\n"); 2470 return err; 2471 } 2472 2473 err = mlx4_slave_cap(dev); 2474 if (err) { 2475 mlx4_err(dev, "Failed to obtain slave caps\n"); 2476 goto err_close; 2477 } 2478 } 2479 2480 if (map_bf_area(dev)) 2481 mlx4_dbg(dev, "Failed to map blue flame area\n"); 2482 2483 /*Only the master set the ports, all the rest got it from it.*/ 2484 if (!mlx4_is_slave(dev)) 2485 mlx4_set_port_mask(dev); 2486 2487 err = mlx4_QUERY_ADAPTER(dev, &adapter); 2488 if (err) { 2489 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting\n"); 2490 goto unmap_bf; 2491 } 2492 2493 /* Query CONFIG_DEV parameters */ 2494 err = mlx4_config_dev_retrieval(dev, ¶ms); 2495 if (err && err != -EOPNOTSUPP) { 2496 mlx4_err(dev, "Failed to query CONFIG_DEV parameters\n"); 2497 } else if (!err) { 2498 dev->caps.rx_checksum_flags_port[1] = params.rx_csum_flags_port_1; 2499 dev->caps.rx_checksum_flags_port[2] = params.rx_csum_flags_port_2; 2500 } 2501 priv->eq_table.inta_pin = adapter.inta_pin; 2502 memcpy(dev->board_id, adapter.board_id, sizeof(dev->board_id)); 2503 2504 err = 0; 2505 goto out_free; 2506 2507 unmap_bf: 2508 unmap_internal_clock(dev); 2509 unmap_bf_area(dev); 2510 2511 if (mlx4_is_slave(dev)) 2512 mlx4_slave_destroy_special_qp_cap(dev); 2513 2514 err_close: 2515 if (mlx4_is_slave(dev)) 2516 mlx4_slave_exit(dev); 2517 else 2518 mlx4_CLOSE_HCA(dev, 0); 2519 2520 err_free_icm: 2521 if (!mlx4_is_slave(dev)) 2522 mlx4_free_icms(dev); 2523 2524 out_free: 2525 kfree(dev_cap); 2526 kfree(init_hca); 2527 2528 return err; 2529 } 2530 2531 static int mlx4_init_counters_table(struct mlx4_dev *dev) 2532 { 2533 struct mlx4_priv *priv = mlx4_priv(dev); 2534 int nent_pow2; 2535 2536 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 2537 return -ENOENT; 2538 2539 if (!dev->caps.max_counters) 2540 return -ENOSPC; 2541 2542 nent_pow2 = roundup_pow_of_two(dev->caps.max_counters); 2543 /* reserve last counter index for sink counter */ 2544 return mlx4_bitmap_init(&priv->counters_bitmap, nent_pow2, 2545 nent_pow2 - 1, 0, 2546 nent_pow2 - dev->caps.max_counters + 1); 2547 } 2548 2549 static void mlx4_cleanup_counters_table(struct mlx4_dev *dev) 2550 { 2551 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 2552 return; 2553 2554 if (!dev->caps.max_counters) 2555 return; 2556 2557 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap); 2558 } 2559 2560 static void mlx4_cleanup_default_counters(struct mlx4_dev *dev) 2561 { 2562 struct mlx4_priv *priv = mlx4_priv(dev); 2563 int port; 2564 2565 for (port = 0; port < dev->caps.num_ports; port++) 2566 if (priv->def_counter[port] != -1) 2567 mlx4_counter_free(dev, priv->def_counter[port]); 2568 } 2569 2570 static int mlx4_allocate_default_counters(struct mlx4_dev *dev) 2571 { 2572 struct mlx4_priv *priv = mlx4_priv(dev); 2573 int port, err = 0; 2574 u32 idx; 2575 2576 for (port = 0; port < dev->caps.num_ports; port++) 2577 priv->def_counter[port] = -1; 2578 2579 for (port = 0; port < dev->caps.num_ports; port++) { 2580 err = mlx4_counter_alloc(dev, &idx, MLX4_RES_USAGE_DRIVER); 2581 2582 if (!err || err == -ENOSPC) { 2583 priv->def_counter[port] = idx; 2584 err = 0; 2585 } else if (err == -ENOENT) { 2586 err = 0; 2587 continue; 2588 } else if (mlx4_is_slave(dev) && err == -EINVAL) { 2589 priv->def_counter[port] = MLX4_SINK_COUNTER_INDEX(dev); 2590 mlx4_warn(dev, "can't allocate counter from old PF driver, using index %d\n", 2591 MLX4_SINK_COUNTER_INDEX(dev)); 2592 err = 0; 2593 } else { 2594 mlx4_err(dev, "%s: failed to allocate default counter port %d err %d\n", 2595 __func__, port + 1, err); 2596 mlx4_cleanup_default_counters(dev); 2597 return err; 2598 } 2599 2600 mlx4_dbg(dev, "%s: default counter index %d for port %d\n", 2601 __func__, priv->def_counter[port], port + 1); 2602 } 2603 2604 return err; 2605 } 2606 2607 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx) 2608 { 2609 struct mlx4_priv *priv = mlx4_priv(dev); 2610 2611 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 2612 return -ENOENT; 2613 2614 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap); 2615 if (*idx == -1) { 2616 *idx = MLX4_SINK_COUNTER_INDEX(dev); 2617 return -ENOSPC; 2618 } 2619 2620 return 0; 2621 } 2622 2623 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx, u8 usage) 2624 { 2625 u32 in_modifier = RES_COUNTER | (((u32)usage & 3) << 30); 2626 u64 out_param; 2627 int err; 2628 2629 if (mlx4_is_mfunc(dev)) { 2630 err = mlx4_cmd_imm(dev, 0, &out_param, in_modifier, 2631 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES, 2632 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 2633 if (!err) 2634 *idx = get_param_l(&out_param); 2635 if (WARN_ON(err == -ENOSPC)) 2636 err = -EINVAL; 2637 return err; 2638 } 2639 return __mlx4_counter_alloc(dev, idx); 2640 } 2641 EXPORT_SYMBOL_GPL(mlx4_counter_alloc); 2642 2643 static int __mlx4_clear_if_stat(struct mlx4_dev *dev, 2644 u8 counter_index) 2645 { 2646 struct mlx4_cmd_mailbox *if_stat_mailbox; 2647 int err; 2648 u32 if_stat_in_mod = (counter_index & 0xff) | MLX4_QUERY_IF_STAT_RESET; 2649 2650 if_stat_mailbox = mlx4_alloc_cmd_mailbox(dev); 2651 if (IS_ERR(if_stat_mailbox)) 2652 return PTR_ERR(if_stat_mailbox); 2653 2654 err = mlx4_cmd_box(dev, 0, if_stat_mailbox->dma, if_stat_in_mod, 0, 2655 MLX4_CMD_QUERY_IF_STAT, MLX4_CMD_TIME_CLASS_C, 2656 MLX4_CMD_NATIVE); 2657 2658 mlx4_free_cmd_mailbox(dev, if_stat_mailbox); 2659 return err; 2660 } 2661 2662 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx) 2663 { 2664 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) 2665 return; 2666 2667 if (idx == MLX4_SINK_COUNTER_INDEX(dev)) 2668 return; 2669 2670 __mlx4_clear_if_stat(dev, idx); 2671 2672 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR); 2673 return; 2674 } 2675 2676 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx) 2677 { 2678 u64 in_param = 0; 2679 2680 if (mlx4_is_mfunc(dev)) { 2681 set_param_l(&in_param, idx); 2682 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE, 2683 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A, 2684 MLX4_CMD_WRAPPED); 2685 return; 2686 } 2687 __mlx4_counter_free(dev, idx); 2688 } 2689 EXPORT_SYMBOL_GPL(mlx4_counter_free); 2690 2691 int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port) 2692 { 2693 struct mlx4_priv *priv = mlx4_priv(dev); 2694 2695 return priv->def_counter[port - 1]; 2696 } 2697 EXPORT_SYMBOL_GPL(mlx4_get_default_counter_index); 2698 2699 void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry, int port) 2700 { 2701 struct mlx4_priv *priv = mlx4_priv(dev); 2702 2703 priv->mfunc.master.vf_admin[entry].vport[port].guid = guid; 2704 } 2705 EXPORT_SYMBOL_GPL(mlx4_set_admin_guid); 2706 2707 __be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port) 2708 { 2709 struct mlx4_priv *priv = mlx4_priv(dev); 2710 2711 return priv->mfunc.master.vf_admin[entry].vport[port].guid; 2712 } 2713 EXPORT_SYMBOL_GPL(mlx4_get_admin_guid); 2714 2715 void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port) 2716 { 2717 struct mlx4_priv *priv = mlx4_priv(dev); 2718 __be64 guid; 2719 2720 /* hw GUID */ 2721 if (entry == 0) 2722 return; 2723 2724 get_random_bytes((char *)&guid, sizeof(guid)); 2725 guid &= ~(cpu_to_be64(1ULL << 56)); 2726 guid |= cpu_to_be64(1ULL << 57); 2727 priv->mfunc.master.vf_admin[entry].vport[port].guid = guid; 2728 } 2729 2730 static int mlx4_setup_hca(struct mlx4_dev *dev) 2731 { 2732 struct mlx4_priv *priv = mlx4_priv(dev); 2733 int err; 2734 int port; 2735 __be32 ib_port_default_caps; 2736 2737 err = mlx4_init_uar_table(dev); 2738 if (err) { 2739 mlx4_err(dev, "Failed to initialize user access region table, aborting\n"); 2740 return err; 2741 } 2742 2743 err = mlx4_uar_alloc(dev, &priv->driver_uar); 2744 if (err) { 2745 mlx4_err(dev, "Failed to allocate driver access region, aborting\n"); 2746 goto err_uar_table_free; 2747 } 2748 2749 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE); 2750 if (!priv->kar) { 2751 mlx4_err(dev, "Couldn't map kernel access region, aborting\n"); 2752 err = -ENOMEM; 2753 goto err_uar_free; 2754 } 2755 2756 err = mlx4_init_pd_table(dev); 2757 if (err) { 2758 mlx4_err(dev, "Failed to initialize protection domain table, aborting\n"); 2759 goto err_kar_unmap; 2760 } 2761 2762 err = mlx4_init_xrcd_table(dev); 2763 if (err) { 2764 mlx4_err(dev, "Failed to initialize reliable connection domain table, aborting\n"); 2765 goto err_pd_table_free; 2766 } 2767 2768 err = mlx4_init_mr_table(dev); 2769 if (err) { 2770 mlx4_err(dev, "Failed to initialize memory region table, aborting\n"); 2771 goto err_xrcd_table_free; 2772 } 2773 2774 if (!mlx4_is_slave(dev)) { 2775 err = mlx4_init_mcg_table(dev); 2776 if (err) { 2777 mlx4_err(dev, "Failed to initialize multicast group table, aborting\n"); 2778 goto err_mr_table_free; 2779 } 2780 err = mlx4_config_mad_demux(dev); 2781 if (err) { 2782 mlx4_err(dev, "Failed in config_mad_demux, aborting\n"); 2783 goto err_mcg_table_free; 2784 } 2785 } 2786 2787 err = mlx4_init_eq_table(dev); 2788 if (err) { 2789 mlx4_err(dev, "Failed to initialize event queue table, aborting\n"); 2790 goto err_mcg_table_free; 2791 } 2792 2793 err = mlx4_cmd_use_events(dev); 2794 if (err) { 2795 mlx4_err(dev, "Failed to switch to event-driven firmware commands, aborting\n"); 2796 goto err_eq_table_free; 2797 } 2798 2799 err = mlx4_NOP(dev); 2800 if (err) { 2801 if (dev->flags & MLX4_FLAG_MSI_X) { 2802 mlx4_warn(dev, "NOP command failed to generate MSI-X interrupt IRQ %d)\n", 2803 priv->eq_table.eq[MLX4_EQ_ASYNC].irq); 2804 mlx4_warn(dev, "Trying again without MSI-X\n"); 2805 } else { 2806 mlx4_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting\n", 2807 priv->eq_table.eq[MLX4_EQ_ASYNC].irq); 2808 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n"); 2809 } 2810 2811 goto err_cmd_poll; 2812 } 2813 2814 mlx4_dbg(dev, "NOP command IRQ test passed\n"); 2815 2816 err = mlx4_init_cq_table(dev); 2817 if (err) { 2818 mlx4_err(dev, "Failed to initialize completion queue table, aborting\n"); 2819 goto err_cmd_poll; 2820 } 2821 2822 err = mlx4_init_srq_table(dev); 2823 if (err) { 2824 mlx4_err(dev, "Failed to initialize shared receive queue table, aborting\n"); 2825 goto err_cq_table_free; 2826 } 2827 2828 err = mlx4_init_qp_table(dev); 2829 if (err) { 2830 mlx4_err(dev, "Failed to initialize queue pair table, aborting\n"); 2831 goto err_srq_table_free; 2832 } 2833 2834 if (!mlx4_is_slave(dev)) { 2835 err = mlx4_init_counters_table(dev); 2836 if (err && err != -ENOENT) { 2837 mlx4_err(dev, "Failed to initialize counters table, aborting\n"); 2838 goto err_qp_table_free; 2839 } 2840 } 2841 2842 err = mlx4_allocate_default_counters(dev); 2843 if (err) { 2844 mlx4_err(dev, "Failed to allocate default counters, aborting\n"); 2845 goto err_counters_table_free; 2846 } 2847 2848 if (!mlx4_is_slave(dev)) { 2849 for (port = 1; port <= dev->caps.num_ports; port++) { 2850 ib_port_default_caps = 0; 2851 err = mlx4_get_port_ib_caps(dev, port, 2852 &ib_port_default_caps); 2853 if (err) 2854 mlx4_warn(dev, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n", 2855 port, err); 2856 dev->caps.ib_port_def_cap[port] = ib_port_default_caps; 2857 2858 /* initialize per-slave default ib port capabilities */ 2859 if (mlx4_is_master(dev)) { 2860 int i; 2861 for (i = 0; i < dev->num_slaves; i++) { 2862 if (i == mlx4_master_func_num(dev)) 2863 continue; 2864 priv->mfunc.master.slave_state[i].ib_cap_mask[port] = 2865 ib_port_default_caps; 2866 } 2867 } 2868 2869 if (mlx4_is_mfunc(dev)) 2870 dev->caps.port_ib_mtu[port] = IB_MTU_2048; 2871 else 2872 dev->caps.port_ib_mtu[port] = IB_MTU_4096; 2873 2874 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ? 2875 dev->caps.pkey_table_len[port] : -1); 2876 if (err) { 2877 mlx4_err(dev, "Failed to set port %d, aborting\n", 2878 port); 2879 goto err_default_countes_free; 2880 } 2881 } 2882 } 2883 2884 return 0; 2885 2886 err_default_countes_free: 2887 mlx4_cleanup_default_counters(dev); 2888 2889 err_counters_table_free: 2890 if (!mlx4_is_slave(dev)) 2891 mlx4_cleanup_counters_table(dev); 2892 2893 err_qp_table_free: 2894 mlx4_cleanup_qp_table(dev); 2895 2896 err_srq_table_free: 2897 mlx4_cleanup_srq_table(dev); 2898 2899 err_cq_table_free: 2900 mlx4_cleanup_cq_table(dev); 2901 2902 err_cmd_poll: 2903 mlx4_cmd_use_polling(dev); 2904 2905 err_eq_table_free: 2906 mlx4_cleanup_eq_table(dev); 2907 2908 err_mcg_table_free: 2909 if (!mlx4_is_slave(dev)) 2910 mlx4_cleanup_mcg_table(dev); 2911 2912 err_mr_table_free: 2913 mlx4_cleanup_mr_table(dev); 2914 2915 err_xrcd_table_free: 2916 mlx4_cleanup_xrcd_table(dev); 2917 2918 err_pd_table_free: 2919 mlx4_cleanup_pd_table(dev); 2920 2921 err_kar_unmap: 2922 iounmap(priv->kar); 2923 2924 err_uar_free: 2925 mlx4_uar_free(dev, &priv->driver_uar); 2926 2927 err_uar_table_free: 2928 mlx4_cleanup_uar_table(dev); 2929 return err; 2930 } 2931 2932 static int mlx4_init_affinity_hint(struct mlx4_dev *dev, int port, int eqn) 2933 { 2934 int requested_cpu = 0; 2935 struct mlx4_priv *priv = mlx4_priv(dev); 2936 struct mlx4_eq *eq; 2937 int off = 0; 2938 int i; 2939 2940 if (eqn > dev->caps.num_comp_vectors) 2941 return -EINVAL; 2942 2943 for (i = 1; i < port; i++) 2944 off += mlx4_get_eqs_per_port(dev, i); 2945 2946 requested_cpu = eqn - off - !!(eqn > MLX4_EQ_ASYNC); 2947 2948 /* Meaning EQs are shared, and this call comes from the second port */ 2949 if (requested_cpu < 0) 2950 return 0; 2951 2952 eq = &priv->eq_table.eq[eqn]; 2953 2954 if (!zalloc_cpumask_var(&eq->affinity_mask, GFP_KERNEL)) 2955 return -ENOMEM; 2956 2957 cpumask_set_cpu(requested_cpu, eq->affinity_mask); 2958 2959 return 0; 2960 } 2961 2962 static void mlx4_enable_msi_x(struct mlx4_dev *dev) 2963 { 2964 struct mlx4_priv *priv = mlx4_priv(dev); 2965 struct msix_entry *entries; 2966 int i; 2967 int port = 0; 2968 2969 if (msi_x) { 2970 int nreq = min3(dev->caps.num_ports * 2971 (int)num_online_cpus() + 1, 2972 dev->caps.num_eqs - dev->caps.reserved_eqs, 2973 MAX_MSIX); 2974 2975 if (msi_x > 1) 2976 nreq = min_t(int, nreq, msi_x); 2977 2978 entries = kcalloc(nreq, sizeof(*entries), GFP_KERNEL); 2979 if (!entries) 2980 goto no_msi; 2981 2982 for (i = 0; i < nreq; ++i) 2983 entries[i].entry = i; 2984 2985 nreq = pci_enable_msix_range(dev->persist->pdev, entries, 2, 2986 nreq); 2987 2988 if (nreq < 0 || nreq < MLX4_EQ_ASYNC) { 2989 kfree(entries); 2990 goto no_msi; 2991 } 2992 /* 1 is reserved for events (asyncrounous EQ) */ 2993 dev->caps.num_comp_vectors = nreq - 1; 2994 2995 priv->eq_table.eq[MLX4_EQ_ASYNC].irq = entries[0].vector; 2996 bitmap_zero(priv->eq_table.eq[MLX4_EQ_ASYNC].actv_ports.ports, 2997 dev->caps.num_ports); 2998 2999 for (i = 0; i < dev->caps.num_comp_vectors + 1; i++) { 3000 if (i == MLX4_EQ_ASYNC) 3001 continue; 3002 3003 priv->eq_table.eq[i].irq = 3004 entries[i + 1 - !!(i > MLX4_EQ_ASYNC)].vector; 3005 3006 if (MLX4_IS_LEGACY_EQ_MODE(dev->caps)) { 3007 bitmap_fill(priv->eq_table.eq[i].actv_ports.ports, 3008 dev->caps.num_ports); 3009 /* We don't set affinity hint when there 3010 * aren't enough EQs 3011 */ 3012 } else { 3013 set_bit(port, 3014 priv->eq_table.eq[i].actv_ports.ports); 3015 if (mlx4_init_affinity_hint(dev, port + 1, i)) 3016 mlx4_warn(dev, "Couldn't init hint cpumask for EQ %d\n", 3017 i); 3018 } 3019 /* We divide the Eqs evenly between the two ports. 3020 * (dev->caps.num_comp_vectors / dev->caps.num_ports) 3021 * refers to the number of Eqs per port 3022 * (i.e eqs_per_port). Theoretically, we would like to 3023 * write something like (i + 1) % eqs_per_port == 0. 3024 * However, since there's an asynchronous Eq, we have 3025 * to skip over it by comparing this condition to 3026 * !!((i + 1) > MLX4_EQ_ASYNC). 3027 */ 3028 if ((dev->caps.num_comp_vectors > dev->caps.num_ports) && 3029 ((i + 1) % 3030 (dev->caps.num_comp_vectors / dev->caps.num_ports)) == 3031 !!((i + 1) > MLX4_EQ_ASYNC)) 3032 /* If dev->caps.num_comp_vectors < dev->caps.num_ports, 3033 * everything is shared anyway. 3034 */ 3035 port++; 3036 } 3037 3038 dev->flags |= MLX4_FLAG_MSI_X; 3039 3040 kfree(entries); 3041 return; 3042 } 3043 3044 no_msi: 3045 dev->caps.num_comp_vectors = 1; 3046 3047 BUG_ON(MLX4_EQ_ASYNC >= 2); 3048 for (i = 0; i < 2; ++i) { 3049 priv->eq_table.eq[i].irq = dev->persist->pdev->irq; 3050 if (i != MLX4_EQ_ASYNC) { 3051 bitmap_fill(priv->eq_table.eq[i].actv_ports.ports, 3052 dev->caps.num_ports); 3053 } 3054 } 3055 } 3056 3057 static int mlx4_devlink_port_type_set(struct devlink_port *devlink_port, 3058 enum devlink_port_type port_type) 3059 { 3060 struct mlx4_port_info *info = container_of(devlink_port, 3061 struct mlx4_port_info, 3062 devlink_port); 3063 enum mlx4_port_type mlx4_port_type; 3064 3065 switch (port_type) { 3066 case DEVLINK_PORT_TYPE_AUTO: 3067 mlx4_port_type = MLX4_PORT_TYPE_AUTO; 3068 break; 3069 case DEVLINK_PORT_TYPE_ETH: 3070 mlx4_port_type = MLX4_PORT_TYPE_ETH; 3071 break; 3072 case DEVLINK_PORT_TYPE_IB: 3073 mlx4_port_type = MLX4_PORT_TYPE_IB; 3074 break; 3075 default: 3076 return -EOPNOTSUPP; 3077 } 3078 3079 return __set_port_type(info, mlx4_port_type); 3080 } 3081 3082 static const struct devlink_port_ops mlx4_devlink_port_ops = { 3083 .port_type_set = mlx4_devlink_port_type_set, 3084 }; 3085 3086 static int mlx4_init_port_info(struct mlx4_dev *dev, int port) 3087 { 3088 struct devlink *devlink = priv_to_devlink(mlx4_priv(dev)); 3089 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port]; 3090 int err; 3091 3092 err = devl_port_register_with_ops(devlink, &info->devlink_port, port, 3093 &mlx4_devlink_port_ops); 3094 if (err) 3095 return err; 3096 3097 /* Ethernet and IB drivers will normally set the port type, 3098 * but if they are not built set the type now to prevent 3099 * devlink_port_type_warn() from firing. 3100 */ 3101 if (!IS_ENABLED(CONFIG_MLX4_EN) && 3102 dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) 3103 devlink_port_type_eth_set(&info->devlink_port); 3104 else if (!IS_ENABLED(CONFIG_MLX4_INFINIBAND) && 3105 dev->caps.port_type[port] == MLX4_PORT_TYPE_IB) 3106 devlink_port_type_ib_set(&info->devlink_port, NULL); 3107 3108 info->dev = dev; 3109 info->port = port; 3110 if (!mlx4_is_slave(dev)) { 3111 mlx4_init_mac_table(dev, &info->mac_table); 3112 mlx4_init_vlan_table(dev, &info->vlan_table); 3113 mlx4_init_roce_gid_table(dev, &info->gid_table); 3114 info->base_qpn = mlx4_get_base_qpn(dev, port); 3115 } 3116 3117 sprintf(info->dev_name, "mlx4_port%d", port); 3118 info->port_attr.attr.name = info->dev_name; 3119 if (mlx4_is_mfunc(dev)) { 3120 info->port_attr.attr.mode = 0444; 3121 } else { 3122 info->port_attr.attr.mode = 0644; 3123 info->port_attr.store = set_port_type; 3124 } 3125 info->port_attr.show = show_port_type; 3126 sysfs_attr_init(&info->port_attr.attr); 3127 3128 err = device_create_file(&dev->persist->pdev->dev, &info->port_attr); 3129 if (err) { 3130 mlx4_err(dev, "Failed to create file for port %d\n", port); 3131 devlink_port_type_clear(&info->devlink_port); 3132 devl_port_unregister(&info->devlink_port); 3133 info->port = -1; 3134 return err; 3135 } 3136 3137 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port); 3138 info->port_mtu_attr.attr.name = info->dev_mtu_name; 3139 if (mlx4_is_mfunc(dev)) { 3140 info->port_mtu_attr.attr.mode = 0444; 3141 } else { 3142 info->port_mtu_attr.attr.mode = 0644; 3143 info->port_mtu_attr.store = set_port_ib_mtu; 3144 } 3145 info->port_mtu_attr.show = show_port_ib_mtu; 3146 sysfs_attr_init(&info->port_mtu_attr.attr); 3147 3148 err = device_create_file(&dev->persist->pdev->dev, 3149 &info->port_mtu_attr); 3150 if (err) { 3151 mlx4_err(dev, "Failed to create mtu file for port %d\n", port); 3152 device_remove_file(&info->dev->persist->pdev->dev, 3153 &info->port_attr); 3154 devlink_port_type_clear(&info->devlink_port); 3155 devl_port_unregister(&info->devlink_port); 3156 info->port = -1; 3157 return err; 3158 } 3159 3160 return 0; 3161 } 3162 3163 static void mlx4_cleanup_port_info(struct mlx4_port_info *info) 3164 { 3165 if (info->port < 0) 3166 return; 3167 3168 device_remove_file(&info->dev->persist->pdev->dev, &info->port_attr); 3169 device_remove_file(&info->dev->persist->pdev->dev, 3170 &info->port_mtu_attr); 3171 devlink_port_type_clear(&info->devlink_port); 3172 devl_port_unregister(&info->devlink_port); 3173 3174 #ifdef CONFIG_RFS_ACCEL 3175 free_irq_cpu_rmap(info->rmap); 3176 info->rmap = NULL; 3177 #endif 3178 } 3179 3180 static int mlx4_init_steering(struct mlx4_dev *dev) 3181 { 3182 struct mlx4_priv *priv = mlx4_priv(dev); 3183 int num_entries = dev->caps.num_ports; 3184 int i, j; 3185 3186 priv->steer = kcalloc(num_entries, sizeof(struct mlx4_steer), 3187 GFP_KERNEL); 3188 if (!priv->steer) 3189 return -ENOMEM; 3190 3191 for (i = 0; i < num_entries; i++) 3192 for (j = 0; j < MLX4_NUM_STEERS; j++) { 3193 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]); 3194 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]); 3195 } 3196 return 0; 3197 } 3198 3199 static void mlx4_clear_steering(struct mlx4_dev *dev) 3200 { 3201 struct mlx4_priv *priv = mlx4_priv(dev); 3202 struct mlx4_steer_index *entry, *tmp_entry; 3203 struct mlx4_promisc_qp *pqp, *tmp_pqp; 3204 int num_entries = dev->caps.num_ports; 3205 int i, j; 3206 3207 for (i = 0; i < num_entries; i++) { 3208 for (j = 0; j < MLX4_NUM_STEERS; j++) { 3209 list_for_each_entry_safe(pqp, tmp_pqp, 3210 &priv->steer[i].promisc_qps[j], 3211 list) { 3212 list_del(&pqp->list); 3213 kfree(pqp); 3214 } 3215 list_for_each_entry_safe(entry, tmp_entry, 3216 &priv->steer[i].steer_entries[j], 3217 list) { 3218 list_del(&entry->list); 3219 list_for_each_entry_safe(pqp, tmp_pqp, 3220 &entry->duplicates, 3221 list) { 3222 list_del(&pqp->list); 3223 kfree(pqp); 3224 } 3225 kfree(entry); 3226 } 3227 } 3228 } 3229 kfree(priv->steer); 3230 } 3231 3232 static int extended_func_num(struct pci_dev *pdev) 3233 { 3234 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn); 3235 } 3236 3237 #define MLX4_OWNER_BASE 0x8069c 3238 #define MLX4_OWNER_SIZE 4 3239 3240 static int mlx4_get_ownership(struct mlx4_dev *dev) 3241 { 3242 void __iomem *owner; 3243 u32 ret; 3244 3245 if (pci_channel_offline(dev->persist->pdev)) 3246 return -EIO; 3247 3248 owner = ioremap(pci_resource_start(dev->persist->pdev, 0) + 3249 MLX4_OWNER_BASE, 3250 MLX4_OWNER_SIZE); 3251 if (!owner) { 3252 mlx4_err(dev, "Failed to obtain ownership bit\n"); 3253 return -ENOMEM; 3254 } 3255 3256 ret = readl(owner); 3257 iounmap(owner); 3258 return (int) !!ret; 3259 } 3260 3261 static void mlx4_free_ownership(struct mlx4_dev *dev) 3262 { 3263 void __iomem *owner; 3264 3265 if (pci_channel_offline(dev->persist->pdev)) 3266 return; 3267 3268 owner = ioremap(pci_resource_start(dev->persist->pdev, 0) + 3269 MLX4_OWNER_BASE, 3270 MLX4_OWNER_SIZE); 3271 if (!owner) { 3272 mlx4_err(dev, "Failed to obtain ownership bit\n"); 3273 return; 3274 } 3275 writel(0, owner); 3276 msleep(1000); 3277 iounmap(owner); 3278 } 3279 3280 #define SRIOV_VALID_STATE(flags) (!!((flags) & MLX4_FLAG_SRIOV) ==\ 3281 !!((flags) & MLX4_FLAG_MASTER)) 3282 3283 static u64 mlx4_enable_sriov(struct mlx4_dev *dev, struct pci_dev *pdev, 3284 u8 total_vfs, int existing_vfs, int reset_flow) 3285 { 3286 u64 dev_flags = dev->flags; 3287 int err = 0; 3288 int fw_enabled_sriov_vfs = min(pci_sriov_get_totalvfs(pdev), 3289 MLX4_MAX_NUM_VF); 3290 3291 if (reset_flow) { 3292 dev->dev_vfs = kcalloc(total_vfs, sizeof(*dev->dev_vfs), 3293 GFP_KERNEL); 3294 if (!dev->dev_vfs) 3295 goto free_mem; 3296 return dev_flags; 3297 } 3298 3299 atomic_inc(&pf_loading); 3300 if (dev->flags & MLX4_FLAG_SRIOV) { 3301 if (existing_vfs != total_vfs) { 3302 mlx4_err(dev, "SR-IOV was already enabled, but with num_vfs (%d) different than requested (%d)\n", 3303 existing_vfs, total_vfs); 3304 total_vfs = existing_vfs; 3305 } 3306 } 3307 3308 dev->dev_vfs = kcalloc(total_vfs, sizeof(*dev->dev_vfs), GFP_KERNEL); 3309 if (NULL == dev->dev_vfs) { 3310 mlx4_err(dev, "Failed to allocate memory for VFs\n"); 3311 goto disable_sriov; 3312 } 3313 3314 if (!(dev->flags & MLX4_FLAG_SRIOV)) { 3315 if (total_vfs > fw_enabled_sriov_vfs) { 3316 mlx4_err(dev, "requested vfs (%d) > available vfs (%d). Continuing without SR_IOV\n", 3317 total_vfs, fw_enabled_sriov_vfs); 3318 err = -ENOMEM; 3319 goto disable_sriov; 3320 } 3321 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", total_vfs); 3322 err = pci_enable_sriov(pdev, total_vfs); 3323 } 3324 if (err) { 3325 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n", 3326 err); 3327 goto disable_sriov; 3328 } else { 3329 mlx4_warn(dev, "Running in master mode\n"); 3330 dev_flags |= MLX4_FLAG_SRIOV | 3331 MLX4_FLAG_MASTER; 3332 dev_flags &= ~MLX4_FLAG_SLAVE; 3333 dev->persist->num_vfs = total_vfs; 3334 } 3335 return dev_flags; 3336 3337 disable_sriov: 3338 atomic_dec(&pf_loading); 3339 free_mem: 3340 dev->persist->num_vfs = 0; 3341 kfree(dev->dev_vfs); 3342 dev->dev_vfs = NULL; 3343 return dev_flags & ~MLX4_FLAG_MASTER; 3344 } 3345 3346 enum { 3347 MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64 = -1, 3348 }; 3349 3350 static int mlx4_check_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap, 3351 int *nvfs) 3352 { 3353 int requested_vfs = nvfs[0] + nvfs[1] + nvfs[2]; 3354 /* Checking for 64 VFs as a limitation of CX2 */ 3355 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_80_VFS) && 3356 requested_vfs >= 64) { 3357 mlx4_err(dev, "Requested %d VFs, but FW does not support more than 64\n", 3358 requested_vfs); 3359 return MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64; 3360 } 3361 return 0; 3362 } 3363 3364 static int mlx4_pci_enable_device(struct mlx4_dev *dev) 3365 { 3366 struct pci_dev *pdev = dev->persist->pdev; 3367 int err = 0; 3368 3369 mutex_lock(&dev->persist->pci_status_mutex); 3370 if (dev->persist->pci_status == MLX4_PCI_STATUS_DISABLED) { 3371 err = pci_enable_device(pdev); 3372 if (!err) 3373 dev->persist->pci_status = MLX4_PCI_STATUS_ENABLED; 3374 } 3375 mutex_unlock(&dev->persist->pci_status_mutex); 3376 3377 return err; 3378 } 3379 3380 static void mlx4_pci_disable_device(struct mlx4_dev *dev) 3381 { 3382 struct pci_dev *pdev = dev->persist->pdev; 3383 3384 mutex_lock(&dev->persist->pci_status_mutex); 3385 if (dev->persist->pci_status == MLX4_PCI_STATUS_ENABLED) { 3386 pci_disable_device(pdev); 3387 dev->persist->pci_status = MLX4_PCI_STATUS_DISABLED; 3388 } 3389 mutex_unlock(&dev->persist->pci_status_mutex); 3390 } 3391 3392 static int mlx4_load_one(struct pci_dev *pdev, int pci_dev_data, 3393 int total_vfs, int *nvfs, struct mlx4_priv *priv, 3394 int reset_flow) 3395 { 3396 struct devlink *devlink = priv_to_devlink(priv); 3397 struct mlx4_dev *dev; 3398 unsigned sum = 0; 3399 int err; 3400 int port; 3401 int i; 3402 struct mlx4_dev_cap *dev_cap = NULL; 3403 int existing_vfs = 0; 3404 3405 devl_assert_locked(devlink); 3406 dev = &priv->dev; 3407 3408 err = mlx4_adev_init(dev); 3409 if (err) 3410 return err; 3411 3412 ATOMIC_INIT_NOTIFIER_HEAD(&priv->event_nh); 3413 3414 mutex_init(&priv->port_mutex); 3415 mutex_init(&priv->bond_mutex); 3416 3417 INIT_LIST_HEAD(&priv->pgdir_list); 3418 mutex_init(&priv->pgdir_mutex); 3419 spin_lock_init(&priv->cmd.context_lock); 3420 3421 INIT_LIST_HEAD(&priv->bf_list); 3422 mutex_init(&priv->bf_mutex); 3423 3424 dev->rev_id = pdev->revision; 3425 dev->numa_node = dev_to_node(&pdev->dev); 3426 3427 /* Detect if this device is a virtual function */ 3428 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) { 3429 mlx4_warn(dev, "Detected virtual function - running in slave mode\n"); 3430 dev->flags |= MLX4_FLAG_SLAVE; 3431 } else { 3432 /* We reset the device and enable SRIOV only for physical 3433 * devices. Try to claim ownership on the device; 3434 * if already taken, skip -- do not allow multiple PFs */ 3435 err = mlx4_get_ownership(dev); 3436 if (err) { 3437 if (err < 0) 3438 goto err_adev; 3439 else { 3440 mlx4_warn(dev, "Multiple PFs not yet supported - Skipping PF\n"); 3441 err = -EINVAL; 3442 goto err_adev; 3443 } 3444 } 3445 3446 atomic_set(&priv->opreq_count, 0); 3447 INIT_WORK(&priv->opreq_task, mlx4_opreq_action); 3448 3449 /* 3450 * Now reset the HCA before we touch the PCI capabilities or 3451 * attempt a firmware command, since a boot ROM may have left 3452 * the HCA in an undefined state. 3453 */ 3454 err = mlx4_reset(dev); 3455 if (err) { 3456 mlx4_err(dev, "Failed to reset HCA, aborting\n"); 3457 goto err_sriov; 3458 } 3459 3460 if (total_vfs) { 3461 dev->flags = MLX4_FLAG_MASTER; 3462 existing_vfs = pci_num_vf(pdev); 3463 if (existing_vfs) 3464 dev->flags |= MLX4_FLAG_SRIOV; 3465 dev->persist->num_vfs = total_vfs; 3466 } 3467 } 3468 3469 /* on load remove any previous indication of internal error, 3470 * device is up. 3471 */ 3472 dev->persist->state = MLX4_DEVICE_STATE_UP; 3473 3474 slave_start: 3475 err = mlx4_cmd_init(dev); 3476 if (err) { 3477 mlx4_err(dev, "Failed to init command interface, aborting\n"); 3478 goto err_sriov; 3479 } 3480 3481 /* In slave functions, the communication channel must be initialized 3482 * before posting commands. Also, init num_slaves before calling 3483 * mlx4_init_hca */ 3484 if (mlx4_is_mfunc(dev)) { 3485 if (mlx4_is_master(dev)) { 3486 dev->num_slaves = MLX4_MAX_NUM_SLAVES; 3487 3488 } else { 3489 dev->num_slaves = 0; 3490 err = mlx4_multi_func_init(dev); 3491 if (err) { 3492 mlx4_err(dev, "Failed to init slave mfunc interface, aborting\n"); 3493 goto err_cmd; 3494 } 3495 } 3496 } 3497 3498 err = mlx4_init_fw(dev); 3499 if (err) { 3500 mlx4_err(dev, "Failed to init fw, aborting.\n"); 3501 goto err_mfunc; 3502 } 3503 3504 if (mlx4_is_master(dev)) { 3505 /* when we hit the goto slave_start below, dev_cap already initialized */ 3506 if (!dev_cap) { 3507 dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL); 3508 3509 if (!dev_cap) { 3510 err = -ENOMEM; 3511 goto err_fw; 3512 } 3513 3514 err = mlx4_QUERY_DEV_CAP(dev, dev_cap); 3515 if (err) { 3516 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 3517 goto err_fw; 3518 } 3519 3520 if (mlx4_check_dev_cap(dev, dev_cap, nvfs)) 3521 goto err_fw; 3522 3523 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) { 3524 u64 dev_flags = mlx4_enable_sriov(dev, pdev, 3525 total_vfs, 3526 existing_vfs, 3527 reset_flow); 3528 3529 mlx4_close_fw(dev); 3530 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); 3531 dev->flags = dev_flags; 3532 if (!SRIOV_VALID_STATE(dev->flags)) { 3533 mlx4_err(dev, "Invalid SRIOV state\n"); 3534 goto err_sriov; 3535 } 3536 err = mlx4_reset(dev); 3537 if (err) { 3538 mlx4_err(dev, "Failed to reset HCA, aborting.\n"); 3539 goto err_sriov; 3540 } 3541 goto slave_start; 3542 } 3543 } else { 3544 /* Legacy mode FW requires SRIOV to be enabled before 3545 * doing QUERY_DEV_CAP, since max_eq's value is different if 3546 * SRIOV is enabled. 3547 */ 3548 memset(dev_cap, 0, sizeof(*dev_cap)); 3549 err = mlx4_QUERY_DEV_CAP(dev, dev_cap); 3550 if (err) { 3551 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); 3552 goto err_fw; 3553 } 3554 3555 if (mlx4_check_dev_cap(dev, dev_cap, nvfs)) 3556 goto err_fw; 3557 } 3558 } 3559 3560 err = mlx4_init_hca(dev); 3561 if (err) { 3562 if (err == -EACCES) { 3563 /* Not primary Physical function 3564 * Running in slave mode */ 3565 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); 3566 /* We're not a PF */ 3567 if (dev->flags & MLX4_FLAG_SRIOV) { 3568 if (!existing_vfs) 3569 pci_disable_sriov(pdev); 3570 if (mlx4_is_master(dev) && !reset_flow) 3571 atomic_dec(&pf_loading); 3572 dev->flags &= ~MLX4_FLAG_SRIOV; 3573 } 3574 if (!mlx4_is_slave(dev)) 3575 mlx4_free_ownership(dev); 3576 dev->flags |= MLX4_FLAG_SLAVE; 3577 dev->flags &= ~MLX4_FLAG_MASTER; 3578 goto slave_start; 3579 } else 3580 goto err_fw; 3581 } 3582 3583 if (mlx4_is_master(dev) && (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) { 3584 u64 dev_flags = mlx4_enable_sriov(dev, pdev, total_vfs, 3585 existing_vfs, reset_flow); 3586 3587 if ((dev->flags ^ dev_flags) & (MLX4_FLAG_MASTER | MLX4_FLAG_SLAVE)) { 3588 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_VHCR); 3589 dev->flags = dev_flags; 3590 err = mlx4_cmd_init(dev); 3591 if (err) { 3592 /* Only VHCR is cleaned up, so could still 3593 * send FW commands 3594 */ 3595 mlx4_err(dev, "Failed to init VHCR command interface, aborting\n"); 3596 goto err_close; 3597 } 3598 } else { 3599 dev->flags = dev_flags; 3600 } 3601 3602 if (!SRIOV_VALID_STATE(dev->flags)) { 3603 mlx4_err(dev, "Invalid SRIOV state\n"); 3604 err = -EINVAL; 3605 goto err_close; 3606 } 3607 } 3608 3609 /* check if the device is functioning at its maximum possible speed. 3610 * No return code for this call, just warn the user in case of PCI 3611 * express device capabilities are under-satisfied by the bus. 3612 */ 3613 if (!mlx4_is_slave(dev)) 3614 pcie_print_link_status(dev->persist->pdev); 3615 3616 /* In master functions, the communication channel must be initialized 3617 * after obtaining its address from fw */ 3618 if (mlx4_is_master(dev)) { 3619 if (dev->caps.num_ports < 2 && 3620 num_vfs_argc > 1) { 3621 err = -EINVAL; 3622 mlx4_err(dev, 3623 "Error: Trying to configure VFs on port 2, but HCA has only %d physical ports\n", 3624 dev->caps.num_ports); 3625 goto err_close; 3626 } 3627 memcpy(dev->persist->nvfs, nvfs, sizeof(dev->persist->nvfs)); 3628 3629 for (i = 0; 3630 i < sizeof(dev->persist->nvfs)/ 3631 sizeof(dev->persist->nvfs[0]); i++) { 3632 unsigned j; 3633 3634 for (j = 0; j < dev->persist->nvfs[i]; ++sum, ++j) { 3635 dev->dev_vfs[sum].min_port = i < 2 ? i + 1 : 1; 3636 dev->dev_vfs[sum].n_ports = i < 2 ? 1 : 3637 dev->caps.num_ports; 3638 } 3639 } 3640 3641 /* In master functions, the communication channel 3642 * must be initialized after obtaining its address from fw 3643 */ 3644 err = mlx4_multi_func_init(dev); 3645 if (err) { 3646 mlx4_err(dev, "Failed to init master mfunc interface, aborting.\n"); 3647 goto err_close; 3648 } 3649 } 3650 3651 err = mlx4_alloc_eq_table(dev); 3652 if (err) 3653 goto err_master_mfunc; 3654 3655 bitmap_zero(priv->msix_ctl.pool_bm, MAX_MSIX); 3656 mutex_init(&priv->msix_ctl.pool_lock); 3657 3658 mlx4_enable_msi_x(dev); 3659 if ((mlx4_is_mfunc(dev)) && 3660 !(dev->flags & MLX4_FLAG_MSI_X)) { 3661 err = -EOPNOTSUPP; 3662 mlx4_err(dev, "INTx is not supported in multi-function mode, aborting\n"); 3663 goto err_free_eq; 3664 } 3665 3666 if (!mlx4_is_slave(dev)) { 3667 err = mlx4_init_steering(dev); 3668 if (err) 3669 goto err_disable_msix; 3670 } 3671 3672 mlx4_init_quotas(dev); 3673 3674 err = mlx4_setup_hca(dev); 3675 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) && 3676 !mlx4_is_mfunc(dev)) { 3677 dev->flags &= ~MLX4_FLAG_MSI_X; 3678 dev->caps.num_comp_vectors = 1; 3679 pci_disable_msix(pdev); 3680 err = mlx4_setup_hca(dev); 3681 } 3682 3683 if (err) 3684 goto err_steer; 3685 3686 /* When PF resources are ready arm its comm channel to enable 3687 * getting commands 3688 */ 3689 if (mlx4_is_master(dev)) { 3690 err = mlx4_ARM_COMM_CHANNEL(dev); 3691 if (err) { 3692 mlx4_err(dev, " Failed to arm comm channel eq: %x\n", 3693 err); 3694 goto err_steer; 3695 } 3696 } 3697 3698 for (port = 1; port <= dev->caps.num_ports; port++) { 3699 err = mlx4_init_port_info(dev, port); 3700 if (err) 3701 goto err_port; 3702 } 3703 3704 priv->v2p.port1 = 1; 3705 priv->v2p.port2 = 2; 3706 3707 err = mlx4_register_device(dev); 3708 if (err) 3709 goto err_port; 3710 3711 mlx4_sense_init(dev); 3712 mlx4_start_sense(dev); 3713 3714 priv->removed = 0; 3715 3716 if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow) 3717 atomic_dec(&pf_loading); 3718 3719 kfree(dev_cap); 3720 return 0; 3721 3722 err_port: 3723 for (--port; port >= 1; --port) 3724 mlx4_cleanup_port_info(&priv->port[port]); 3725 3726 mlx4_cleanup_default_counters(dev); 3727 if (!mlx4_is_slave(dev)) 3728 mlx4_cleanup_counters_table(dev); 3729 mlx4_cleanup_qp_table(dev); 3730 mlx4_cleanup_srq_table(dev); 3731 mlx4_cleanup_cq_table(dev); 3732 mlx4_cmd_use_polling(dev); 3733 mlx4_cleanup_eq_table(dev); 3734 mlx4_cleanup_mcg_table(dev); 3735 mlx4_cleanup_mr_table(dev); 3736 mlx4_cleanup_xrcd_table(dev); 3737 mlx4_cleanup_pd_table(dev); 3738 mlx4_cleanup_uar_table(dev); 3739 3740 err_steer: 3741 if (!mlx4_is_slave(dev)) 3742 mlx4_clear_steering(dev); 3743 3744 err_disable_msix: 3745 if (dev->flags & MLX4_FLAG_MSI_X) 3746 pci_disable_msix(pdev); 3747 3748 err_free_eq: 3749 mlx4_free_eq_table(dev); 3750 3751 err_master_mfunc: 3752 if (mlx4_is_master(dev)) { 3753 mlx4_free_resource_tracker(dev, RES_TR_FREE_STRUCTS_ONLY); 3754 mlx4_multi_func_cleanup(dev); 3755 } 3756 3757 if (mlx4_is_slave(dev)) 3758 mlx4_slave_destroy_special_qp_cap(dev); 3759 3760 err_close: 3761 mlx4_close_hca(dev); 3762 3763 err_fw: 3764 mlx4_close_fw(dev); 3765 3766 err_mfunc: 3767 if (mlx4_is_slave(dev)) 3768 mlx4_multi_func_cleanup(dev); 3769 3770 err_cmd: 3771 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); 3772 3773 err_sriov: 3774 if (dev->flags & MLX4_FLAG_SRIOV && !existing_vfs) { 3775 pci_disable_sriov(pdev); 3776 dev->flags &= ~MLX4_FLAG_SRIOV; 3777 } 3778 3779 if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow) 3780 atomic_dec(&pf_loading); 3781 3782 kfree(priv->dev.dev_vfs); 3783 3784 if (!mlx4_is_slave(dev)) 3785 mlx4_free_ownership(dev); 3786 3787 kfree(dev_cap); 3788 3789 err_adev: 3790 mlx4_adev_cleanup(dev); 3791 return err; 3792 } 3793 3794 static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data, 3795 struct mlx4_priv *priv) 3796 { 3797 int err; 3798 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 3799 int prb_vf[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 3800 const int param_map[MLX4_MAX_PORTS + 1][MLX4_MAX_PORTS + 1] = { 3801 {2, 0, 0}, {0, 1, 2}, {0, 1, 2} }; 3802 unsigned total_vfs = 0; 3803 unsigned int i; 3804 3805 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev)); 3806 3807 err = mlx4_pci_enable_device(&priv->dev); 3808 if (err) { 3809 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); 3810 return err; 3811 } 3812 3813 /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS 3814 * per port, we must limit the number of VFs to 63 (since their are 3815 * 128 MACs) 3816 */ 3817 for (i = 0; i < ARRAY_SIZE(nvfs) && i < num_vfs_argc; 3818 total_vfs += nvfs[param_map[num_vfs_argc - 1][i]], i++) { 3819 nvfs[param_map[num_vfs_argc - 1][i]] = num_vfs[i]; 3820 if (nvfs[i] < 0) { 3821 dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n"); 3822 err = -EINVAL; 3823 goto err_disable_pdev; 3824 } 3825 } 3826 for (i = 0; i < ARRAY_SIZE(prb_vf) && i < probe_vfs_argc; 3827 i++) { 3828 prb_vf[param_map[probe_vfs_argc - 1][i]] = probe_vf[i]; 3829 if (prb_vf[i] < 0 || prb_vf[i] > nvfs[i]) { 3830 dev_err(&pdev->dev, "probe_vf module parameter cannot be negative or greater than num_vfs\n"); 3831 err = -EINVAL; 3832 goto err_disable_pdev; 3833 } 3834 } 3835 if (total_vfs > MLX4_MAX_NUM_VF) { 3836 dev_err(&pdev->dev, 3837 "Requested more VF's (%d) than allowed by hw (%d)\n", 3838 total_vfs, MLX4_MAX_NUM_VF); 3839 err = -EINVAL; 3840 goto err_disable_pdev; 3841 } 3842 3843 for (i = 0; i < MLX4_MAX_PORTS; i++) { 3844 if (nvfs[i] + nvfs[2] > MLX4_MAX_NUM_VF_P_PORT) { 3845 dev_err(&pdev->dev, 3846 "Requested more VF's (%d) for port (%d) than allowed by driver (%d)\n", 3847 nvfs[i] + nvfs[2], i + 1, 3848 MLX4_MAX_NUM_VF_P_PORT); 3849 err = -EINVAL; 3850 goto err_disable_pdev; 3851 } 3852 } 3853 3854 /* Check for BARs. */ 3855 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) && 3856 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 3857 dev_err(&pdev->dev, "Missing DCS, aborting (driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n", 3858 pci_dev_data, pci_resource_flags(pdev, 0)); 3859 err = -ENODEV; 3860 goto err_disable_pdev; 3861 } 3862 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 3863 dev_err(&pdev->dev, "Missing UAR, aborting\n"); 3864 err = -ENODEV; 3865 goto err_disable_pdev; 3866 } 3867 3868 err = pci_request_regions(pdev, DRV_NAME); 3869 if (err) { 3870 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); 3871 goto err_disable_pdev; 3872 } 3873 3874 pci_set_master(pdev); 3875 3876 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 3877 if (err) { 3878 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); 3879 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 3880 if (err) { 3881 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); 3882 goto err_release_regions; 3883 } 3884 } 3885 3886 /* Allow large DMA segments, up to the firmware limit of 1 GB */ 3887 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024); 3888 /* Detect if this device is a virtual function */ 3889 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) { 3890 /* When acting as pf, we normally skip vfs unless explicitly 3891 * requested to probe them. 3892 */ 3893 if (total_vfs) { 3894 unsigned vfs_offset = 0; 3895 3896 for (i = 0; i < ARRAY_SIZE(nvfs) && 3897 vfs_offset + nvfs[i] < extended_func_num(pdev); 3898 vfs_offset += nvfs[i], i++) 3899 ; 3900 if (i == ARRAY_SIZE(nvfs)) { 3901 err = -ENODEV; 3902 goto err_release_regions; 3903 } 3904 if ((extended_func_num(pdev) - vfs_offset) 3905 > prb_vf[i]) { 3906 dev_warn(&pdev->dev, "Skipping virtual function:%d\n", 3907 extended_func_num(pdev)); 3908 err = -ENODEV; 3909 goto err_release_regions; 3910 } 3911 } 3912 } 3913 3914 err = mlx4_crdump_init(&priv->dev); 3915 if (err) 3916 goto err_release_regions; 3917 3918 err = mlx4_catas_init(&priv->dev); 3919 if (err) 3920 goto err_crdump; 3921 3922 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 0); 3923 if (err) 3924 goto err_catas; 3925 3926 return 0; 3927 3928 err_catas: 3929 mlx4_catas_end(&priv->dev); 3930 3931 err_crdump: 3932 mlx4_crdump_end(&priv->dev); 3933 3934 err_release_regions: 3935 pci_release_regions(pdev); 3936 3937 err_disable_pdev: 3938 mlx4_pci_disable_device(&priv->dev); 3939 return err; 3940 } 3941 3942 static void mlx4_devlink_param_load_driverinit_values(struct devlink *devlink) 3943 { 3944 struct mlx4_priv *priv = devlink_priv(devlink); 3945 struct mlx4_dev *dev = &priv->dev; 3946 struct mlx4_fw_crdump *crdump = &dev->persist->crdump; 3947 union devlink_param_value saved_value; 3948 int err; 3949 3950 err = devl_param_driverinit_value_get(devlink, 3951 DEVLINK_PARAM_GENERIC_ID_INT_ERR_RESET, 3952 &saved_value); 3953 if (!err && mlx4_internal_err_reset != saved_value.vbool) { 3954 mlx4_internal_err_reset = saved_value.vbool; 3955 /* Notify on value changed on runtime configuration mode */ 3956 devl_param_value_changed(devlink, 3957 DEVLINK_PARAM_GENERIC_ID_INT_ERR_RESET); 3958 } 3959 err = devl_param_driverinit_value_get(devlink, 3960 DEVLINK_PARAM_GENERIC_ID_MAX_MACS, 3961 &saved_value); 3962 if (!err) 3963 log_num_mac = order_base_2(saved_value.vu32); 3964 err = devl_param_driverinit_value_get(devlink, 3965 MLX4_DEVLINK_PARAM_ID_ENABLE_64B_CQE_EQE, 3966 &saved_value); 3967 if (!err) 3968 enable_64b_cqe_eqe = saved_value.vbool; 3969 err = devl_param_driverinit_value_get(devlink, 3970 MLX4_DEVLINK_PARAM_ID_ENABLE_4K_UAR, 3971 &saved_value); 3972 if (!err) 3973 enable_4k_uar = saved_value.vbool; 3974 err = devl_param_driverinit_value_get(devlink, 3975 DEVLINK_PARAM_GENERIC_ID_REGION_SNAPSHOT, 3976 &saved_value); 3977 if (!err && crdump->snapshot_enable != saved_value.vbool) { 3978 crdump->snapshot_enable = saved_value.vbool; 3979 devl_param_value_changed(devlink, 3980 DEVLINK_PARAM_GENERIC_ID_REGION_SNAPSHOT); 3981 } 3982 } 3983 3984 static void mlx4_restart_one_down(struct pci_dev *pdev); 3985 static int mlx4_restart_one_up(struct pci_dev *pdev, bool reload, 3986 struct devlink *devlink); 3987 3988 static int mlx4_devlink_reload_down(struct devlink *devlink, bool netns_change, 3989 enum devlink_reload_action action, 3990 enum devlink_reload_limit limit, 3991 struct netlink_ext_ack *extack) 3992 { 3993 struct mlx4_priv *priv = devlink_priv(devlink); 3994 struct mlx4_dev *dev = &priv->dev; 3995 struct mlx4_dev_persistent *persist = dev->persist; 3996 3997 if (netns_change) { 3998 NL_SET_ERR_MSG_MOD(extack, "Namespace change is not supported"); 3999 return -EOPNOTSUPP; 4000 } 4001 if (persist->num_vfs) 4002 mlx4_warn(persist->dev, "Reload performed on PF, will cause reset on operating Virtual Functions\n"); 4003 mlx4_restart_one_down(persist->pdev); 4004 return 0; 4005 } 4006 4007 static int mlx4_devlink_reload_up(struct devlink *devlink, enum devlink_reload_action action, 4008 enum devlink_reload_limit limit, u32 *actions_performed, 4009 struct netlink_ext_ack *extack) 4010 { 4011 struct mlx4_priv *priv = devlink_priv(devlink); 4012 struct mlx4_dev *dev = &priv->dev; 4013 struct mlx4_dev_persistent *persist = dev->persist; 4014 int err; 4015 4016 *actions_performed = BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT); 4017 err = mlx4_restart_one_up(persist->pdev, true, devlink); 4018 if (err) 4019 mlx4_err(persist->dev, "mlx4_restart_one_up failed, ret=%d\n", 4020 err); 4021 4022 return err; 4023 } 4024 4025 static const struct devlink_ops mlx4_devlink_ops = { 4026 .reload_actions = BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT), 4027 .reload_down = mlx4_devlink_reload_down, 4028 .reload_up = mlx4_devlink_reload_up, 4029 }; 4030 4031 static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 4032 { 4033 struct devlink *devlink; 4034 struct mlx4_priv *priv; 4035 struct mlx4_dev *dev; 4036 int ret; 4037 4038 printk_once(KERN_INFO "%s", mlx4_version); 4039 4040 devlink = devlink_alloc(&mlx4_devlink_ops, sizeof(*priv), &pdev->dev); 4041 if (!devlink) 4042 return -ENOMEM; 4043 devl_lock(devlink); 4044 priv = devlink_priv(devlink); 4045 4046 dev = &priv->dev; 4047 dev->persist = kzalloc(sizeof(*dev->persist), GFP_KERNEL); 4048 if (!dev->persist) { 4049 ret = -ENOMEM; 4050 goto err_devlink_free; 4051 } 4052 dev->persist->pdev = pdev; 4053 dev->persist->dev = dev; 4054 pci_set_drvdata(pdev, dev->persist); 4055 priv->pci_dev_data = id->driver_data; 4056 mutex_init(&dev->persist->device_state_mutex); 4057 mutex_init(&dev->persist->interface_state_mutex); 4058 mutex_init(&dev->persist->pci_status_mutex); 4059 4060 ret = devl_params_register(devlink, mlx4_devlink_params, 4061 ARRAY_SIZE(mlx4_devlink_params)); 4062 if (ret) 4063 goto err_devlink_unregister; 4064 mlx4_devlink_set_params_init_values(devlink); 4065 ret = __mlx4_init_one(pdev, id->driver_data, priv); 4066 if (ret) 4067 goto err_params_unregister; 4068 4069 pci_save_state(pdev); 4070 devl_unlock(devlink); 4071 devlink_register(devlink); 4072 return 0; 4073 4074 err_params_unregister: 4075 devl_params_unregister(devlink, mlx4_devlink_params, 4076 ARRAY_SIZE(mlx4_devlink_params)); 4077 err_devlink_unregister: 4078 kfree(dev->persist); 4079 err_devlink_free: 4080 devl_unlock(devlink); 4081 devlink_free(devlink); 4082 return ret; 4083 } 4084 4085 static void mlx4_clean_dev(struct mlx4_dev *dev) 4086 { 4087 struct mlx4_dev_persistent *persist = dev->persist; 4088 struct mlx4_priv *priv = mlx4_priv(dev); 4089 unsigned long flags = (dev->flags & RESET_PERSIST_MASK_FLAGS); 4090 4091 memset(priv, 0, sizeof(*priv)); 4092 priv->dev.persist = persist; 4093 priv->dev.flags = flags; 4094 } 4095 4096 static void mlx4_unload_one(struct pci_dev *pdev) 4097 { 4098 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4099 struct mlx4_dev *dev = persist->dev; 4100 struct mlx4_priv *priv = mlx4_priv(dev); 4101 int pci_dev_data; 4102 struct devlink *devlink; 4103 int p, i; 4104 4105 devlink = priv_to_devlink(priv); 4106 devl_assert_locked(devlink); 4107 if (priv->removed) 4108 return; 4109 4110 /* saving current ports type for further use */ 4111 for (i = 0; i < dev->caps.num_ports; i++) { 4112 dev->persist->curr_port_type[i] = dev->caps.port_type[i + 1]; 4113 dev->persist->curr_port_poss_type[i] = dev->caps. 4114 possible_type[i + 1]; 4115 } 4116 4117 pci_dev_data = priv->pci_dev_data; 4118 4119 mlx4_stop_sense(dev); 4120 mlx4_unregister_device(dev); 4121 4122 for (p = 1; p <= dev->caps.num_ports; p++) { 4123 mlx4_cleanup_port_info(&priv->port[p]); 4124 mlx4_CLOSE_PORT(dev, p); 4125 } 4126 4127 if (mlx4_is_master(dev)) 4128 mlx4_free_resource_tracker(dev, 4129 RES_TR_FREE_SLAVES_ONLY); 4130 4131 mlx4_cleanup_default_counters(dev); 4132 if (!mlx4_is_slave(dev)) 4133 mlx4_cleanup_counters_table(dev); 4134 mlx4_cleanup_qp_table(dev); 4135 mlx4_cleanup_srq_table(dev); 4136 mlx4_cleanup_cq_table(dev); 4137 mlx4_cmd_use_polling(dev); 4138 mlx4_cleanup_eq_table(dev); 4139 mlx4_cleanup_mcg_table(dev); 4140 mlx4_cleanup_mr_table(dev); 4141 mlx4_cleanup_xrcd_table(dev); 4142 mlx4_cleanup_pd_table(dev); 4143 4144 if (mlx4_is_master(dev)) 4145 mlx4_free_resource_tracker(dev, 4146 RES_TR_FREE_STRUCTS_ONLY); 4147 4148 iounmap(priv->kar); 4149 mlx4_uar_free(dev, &priv->driver_uar); 4150 mlx4_cleanup_uar_table(dev); 4151 if (!mlx4_is_slave(dev)) 4152 mlx4_clear_steering(dev); 4153 mlx4_free_eq_table(dev); 4154 if (mlx4_is_master(dev)) 4155 mlx4_multi_func_cleanup(dev); 4156 mlx4_close_hca(dev); 4157 mlx4_close_fw(dev); 4158 if (mlx4_is_slave(dev)) 4159 mlx4_multi_func_cleanup(dev); 4160 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL); 4161 4162 if (dev->flags & MLX4_FLAG_MSI_X) 4163 pci_disable_msix(pdev); 4164 4165 if (!mlx4_is_slave(dev)) 4166 mlx4_free_ownership(dev); 4167 4168 mlx4_slave_destroy_special_qp_cap(dev); 4169 kfree(dev->dev_vfs); 4170 4171 mlx4_adev_cleanup(dev); 4172 4173 mlx4_clean_dev(dev); 4174 priv->pci_dev_data = pci_dev_data; 4175 priv->removed = 1; 4176 } 4177 4178 static void mlx4_remove_one(struct pci_dev *pdev) 4179 { 4180 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4181 struct mlx4_dev *dev = persist->dev; 4182 struct mlx4_priv *priv = mlx4_priv(dev); 4183 struct devlink *devlink = priv_to_devlink(priv); 4184 int active_vfs = 0; 4185 4186 devlink_unregister(devlink); 4187 4188 devl_lock(devlink); 4189 if (mlx4_is_slave(dev)) 4190 persist->interface_state |= MLX4_INTERFACE_STATE_NOWAIT; 4191 4192 mutex_lock(&persist->interface_state_mutex); 4193 persist->interface_state |= MLX4_INTERFACE_STATE_DELETION; 4194 mutex_unlock(&persist->interface_state_mutex); 4195 4196 /* Disabling SR-IOV is not allowed while there are active vf's */ 4197 if (mlx4_is_master(dev) && dev->flags & MLX4_FLAG_SRIOV) { 4198 active_vfs = mlx4_how_many_lives_vf(dev); 4199 if (active_vfs) { 4200 pr_warn("Removing PF when there are active VF's !!\n"); 4201 pr_warn("Will not disable SR-IOV.\n"); 4202 } 4203 } 4204 4205 /* device marked to be under deletion running now without the lock 4206 * letting other tasks to be terminated 4207 */ 4208 if (persist->interface_state & MLX4_INTERFACE_STATE_UP) 4209 mlx4_unload_one(pdev); 4210 else 4211 mlx4_info(dev, "%s: interface is down\n", __func__); 4212 mlx4_catas_end(dev); 4213 mlx4_crdump_end(dev); 4214 if (dev->flags & MLX4_FLAG_SRIOV && !active_vfs) { 4215 mlx4_warn(dev, "Disabling SR-IOV\n"); 4216 pci_disable_sriov(pdev); 4217 } 4218 4219 pci_release_regions(pdev); 4220 mlx4_pci_disable_device(dev); 4221 devl_params_unregister(devlink, mlx4_devlink_params, 4222 ARRAY_SIZE(mlx4_devlink_params)); 4223 kfree(dev->persist); 4224 devl_unlock(devlink); 4225 devlink_free(devlink); 4226 } 4227 4228 static int restore_current_port_types(struct mlx4_dev *dev, 4229 enum mlx4_port_type *types, 4230 enum mlx4_port_type *poss_types) 4231 { 4232 struct mlx4_priv *priv = mlx4_priv(dev); 4233 int err, i; 4234 4235 mlx4_stop_sense(dev); 4236 4237 mutex_lock(&priv->port_mutex); 4238 for (i = 0; i < dev->caps.num_ports; i++) 4239 dev->caps.possible_type[i + 1] = poss_types[i]; 4240 err = mlx4_change_port_types(dev, types); 4241 mlx4_start_sense(dev); 4242 mutex_unlock(&priv->port_mutex); 4243 4244 return err; 4245 } 4246 4247 static void mlx4_restart_one_down(struct pci_dev *pdev) 4248 { 4249 mlx4_unload_one(pdev); 4250 } 4251 4252 static int mlx4_restart_one_up(struct pci_dev *pdev, bool reload, 4253 struct devlink *devlink) 4254 { 4255 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4256 struct mlx4_dev *dev = persist->dev; 4257 struct mlx4_priv *priv = mlx4_priv(dev); 4258 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 4259 int pci_dev_data, err, total_vfs; 4260 4261 pci_dev_data = priv->pci_dev_data; 4262 total_vfs = dev->persist->num_vfs; 4263 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs)); 4264 4265 if (reload) 4266 mlx4_devlink_param_load_driverinit_values(devlink); 4267 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 1); 4268 if (err) { 4269 mlx4_err(dev, "%s: ERROR: mlx4_load_one failed, pci_name=%s, err=%d\n", 4270 __func__, pci_name(pdev), err); 4271 return err; 4272 } 4273 4274 err = restore_current_port_types(dev, dev->persist->curr_port_type, 4275 dev->persist->curr_port_poss_type); 4276 if (err) 4277 mlx4_err(dev, "could not restore original port types (%d)\n", 4278 err); 4279 4280 return err; 4281 } 4282 4283 int mlx4_restart_one(struct pci_dev *pdev) 4284 { 4285 mlx4_restart_one_down(pdev); 4286 return mlx4_restart_one_up(pdev, false, NULL); 4287 } 4288 4289 #define MLX_SP(id) { PCI_VDEVICE(MELLANOX, id), MLX4_PCI_DEV_FORCE_SENSE_PORT } 4290 #define MLX_VF(id) { PCI_VDEVICE(MELLANOX, id), MLX4_PCI_DEV_IS_VF } 4291 #define MLX_GN(id) { PCI_VDEVICE(MELLANOX, id), 0 } 4292 4293 static const struct pci_device_id mlx4_pci_table[] = { 4294 #ifdef CONFIG_MLX4_CORE_GEN2 4295 /* MT25408 "Hermon" */ 4296 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_SDR), /* SDR */ 4297 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_DDR), /* DDR */ 4298 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_QDR), /* QDR */ 4299 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2), /* DDR Gen2 */ 4300 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2), /* QDR Gen2 */ 4301 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_EN), /* EN 10GigE */ 4302 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2), /* EN 10GigE Gen2 */ 4303 /* MT25458 ConnectX EN 10GBASE-T */ 4304 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN), 4305 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2), /* Gen2 */ 4306 /* MT26468 ConnectX EN 10GigE PCIe Gen2*/ 4307 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2), 4308 /* MT26438 ConnectX EN 40GigE PCIe Gen2 5GT/s */ 4309 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2), 4310 /* MT26478 ConnectX2 40GigE PCIe Gen2 */ 4311 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX2), 4312 /* MT25400 Family [ConnectX-2] */ 4313 MLX_VF(0x1002), /* Virtual Function */ 4314 #endif /* CONFIG_MLX4_CORE_GEN2 */ 4315 /* MT27500 Family [ConnectX-3] */ 4316 MLX_GN(PCI_DEVICE_ID_MELLANOX_CONNECTX3), 4317 MLX_VF(0x1004), /* Virtual Function */ 4318 MLX_GN(0x1005), /* MT27510 Family */ 4319 MLX_GN(0x1006), /* MT27511 Family */ 4320 MLX_GN(PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO), /* MT27520 Family */ 4321 MLX_GN(0x1008), /* MT27521 Family */ 4322 MLX_GN(0x1009), /* MT27530 Family */ 4323 MLX_GN(0x100a), /* MT27531 Family */ 4324 MLX_GN(0x100b), /* MT27540 Family */ 4325 MLX_GN(0x100c), /* MT27541 Family */ 4326 MLX_GN(0x100d), /* MT27550 Family */ 4327 MLX_GN(0x100e), /* MT27551 Family */ 4328 MLX_GN(0x100f), /* MT27560 Family */ 4329 MLX_GN(0x1010), /* MT27561 Family */ 4330 4331 /* 4332 * See the mellanox_check_broken_intx_masking() quirk when 4333 * adding devices 4334 */ 4335 4336 { 0, } 4337 }; 4338 4339 MODULE_DEVICE_TABLE(pci, mlx4_pci_table); 4340 4341 static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev, 4342 pci_channel_state_t state) 4343 { 4344 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4345 struct mlx4_dev *dev = persist->dev; 4346 struct devlink *devlink; 4347 4348 mlx4_err(persist->dev, "mlx4_pci_err_detected was called\n"); 4349 mlx4_enter_error_state(persist); 4350 4351 devlink = priv_to_devlink(mlx4_priv(dev)); 4352 devl_lock(devlink); 4353 mutex_lock(&persist->interface_state_mutex); 4354 if (persist->interface_state & MLX4_INTERFACE_STATE_UP) 4355 mlx4_unload_one(pdev); 4356 4357 mutex_unlock(&persist->interface_state_mutex); 4358 devl_unlock(devlink); 4359 if (state == pci_channel_io_perm_failure) 4360 return PCI_ERS_RESULT_DISCONNECT; 4361 4362 mlx4_pci_disable_device(persist->dev); 4363 return PCI_ERS_RESULT_NEED_RESET; 4364 } 4365 4366 static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev) 4367 { 4368 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4369 struct mlx4_dev *dev = persist->dev; 4370 int err; 4371 4372 mlx4_err(dev, "mlx4_pci_slot_reset was called\n"); 4373 err = mlx4_pci_enable_device(dev); 4374 if (err) { 4375 mlx4_err(dev, "Can not re-enable device, err=%d\n", err); 4376 return PCI_ERS_RESULT_DISCONNECT; 4377 } 4378 4379 pci_set_master(pdev); 4380 pci_restore_state(pdev); 4381 pci_save_state(pdev); 4382 return PCI_ERS_RESULT_RECOVERED; 4383 } 4384 4385 static void mlx4_pci_resume(struct pci_dev *pdev) 4386 { 4387 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4388 struct mlx4_dev *dev = persist->dev; 4389 struct mlx4_priv *priv = mlx4_priv(dev); 4390 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 4391 struct devlink *devlink; 4392 int total_vfs; 4393 int err; 4394 4395 mlx4_err(dev, "%s was called\n", __func__); 4396 total_vfs = dev->persist->num_vfs; 4397 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs)); 4398 4399 devlink = priv_to_devlink(priv); 4400 devl_lock(devlink); 4401 mutex_lock(&persist->interface_state_mutex); 4402 if (!(persist->interface_state & MLX4_INTERFACE_STATE_UP)) { 4403 err = mlx4_load_one(pdev, priv->pci_dev_data, total_vfs, nvfs, 4404 priv, 1); 4405 if (err) { 4406 mlx4_err(dev, "%s: mlx4_load_one failed, err=%d\n", 4407 __func__, err); 4408 goto end; 4409 } 4410 4411 err = restore_current_port_types(dev, dev->persist-> 4412 curr_port_type, dev->persist-> 4413 curr_port_poss_type); 4414 if (err) 4415 mlx4_err(dev, "could not restore original port types (%d)\n", err); 4416 } 4417 end: 4418 mutex_unlock(&persist->interface_state_mutex); 4419 devl_unlock(devlink); 4420 } 4421 4422 static void mlx4_shutdown(struct pci_dev *pdev) 4423 { 4424 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4425 struct mlx4_dev *dev = persist->dev; 4426 struct devlink *devlink; 4427 4428 mlx4_info(persist->dev, "mlx4_shutdown was called\n"); 4429 devlink = priv_to_devlink(mlx4_priv(dev)); 4430 devl_lock(devlink); 4431 mutex_lock(&persist->interface_state_mutex); 4432 if (persist->interface_state & MLX4_INTERFACE_STATE_UP) 4433 mlx4_unload_one(pdev); 4434 mutex_unlock(&persist->interface_state_mutex); 4435 devl_unlock(devlink); 4436 mlx4_pci_disable_device(dev); 4437 } 4438 4439 static const struct pci_error_handlers mlx4_err_handler = { 4440 .error_detected = mlx4_pci_err_detected, 4441 .slot_reset = mlx4_pci_slot_reset, 4442 .resume = mlx4_pci_resume, 4443 }; 4444 4445 static int __maybe_unused mlx4_suspend(struct device *dev_d) 4446 { 4447 struct pci_dev *pdev = to_pci_dev(dev_d); 4448 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4449 struct mlx4_dev *dev = persist->dev; 4450 struct devlink *devlink; 4451 4452 mlx4_err(dev, "suspend was called\n"); 4453 devlink = priv_to_devlink(mlx4_priv(dev)); 4454 devl_lock(devlink); 4455 mutex_lock(&persist->interface_state_mutex); 4456 if (persist->interface_state & MLX4_INTERFACE_STATE_UP) 4457 mlx4_unload_one(pdev); 4458 mutex_unlock(&persist->interface_state_mutex); 4459 devl_unlock(devlink); 4460 4461 return 0; 4462 } 4463 4464 static int __maybe_unused mlx4_resume(struct device *dev_d) 4465 { 4466 struct pci_dev *pdev = to_pci_dev(dev_d); 4467 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev); 4468 struct mlx4_dev *dev = persist->dev; 4469 struct mlx4_priv *priv = mlx4_priv(dev); 4470 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0}; 4471 struct devlink *devlink; 4472 int total_vfs; 4473 int ret = 0; 4474 4475 mlx4_err(dev, "resume was called\n"); 4476 total_vfs = dev->persist->num_vfs; 4477 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs)); 4478 4479 devlink = priv_to_devlink(priv); 4480 devl_lock(devlink); 4481 mutex_lock(&persist->interface_state_mutex); 4482 if (!(persist->interface_state & MLX4_INTERFACE_STATE_UP)) { 4483 ret = mlx4_load_one(pdev, priv->pci_dev_data, total_vfs, 4484 nvfs, priv, 1); 4485 if (!ret) { 4486 ret = restore_current_port_types(dev, 4487 dev->persist->curr_port_type, 4488 dev->persist->curr_port_poss_type); 4489 if (ret) 4490 mlx4_err(dev, "resume: could not restore original port types (%d)\n", ret); 4491 } 4492 } 4493 mutex_unlock(&persist->interface_state_mutex); 4494 devl_unlock(devlink); 4495 4496 return ret; 4497 } 4498 4499 static SIMPLE_DEV_PM_OPS(mlx4_pm_ops, mlx4_suspend, mlx4_resume); 4500 4501 static struct pci_driver mlx4_driver = { 4502 .name = DRV_NAME, 4503 .id_table = mlx4_pci_table, 4504 .probe = mlx4_init_one, 4505 .shutdown = mlx4_shutdown, 4506 .remove = mlx4_remove_one, 4507 .driver.pm = &mlx4_pm_ops, 4508 .err_handler = &mlx4_err_handler, 4509 }; 4510 4511 static int __init mlx4_verify_params(void) 4512 { 4513 if (msi_x < 0) { 4514 pr_warn("mlx4_core: bad msi_x: %d\n", msi_x); 4515 return -1; 4516 } 4517 4518 if ((log_num_mac < 0) || (log_num_mac > 7)) { 4519 pr_warn("mlx4_core: bad num_mac: %d\n", log_num_mac); 4520 return -1; 4521 } 4522 4523 if (log_num_vlan != 0) 4524 pr_warn("mlx4_core: log_num_vlan - obsolete module param, using %d\n", 4525 MLX4_LOG_NUM_VLANS); 4526 4527 if (use_prio != 0) 4528 pr_warn("mlx4_core: use_prio - obsolete module param, ignored\n"); 4529 4530 if ((log_mtts_per_seg < 0) || (log_mtts_per_seg > 7)) { 4531 pr_warn("mlx4_core: bad log_mtts_per_seg: %d\n", 4532 log_mtts_per_seg); 4533 return -1; 4534 } 4535 4536 /* Check if module param for ports type has legal combination */ 4537 if (port_type_array[0] == false && port_type_array[1] == true) { 4538 pr_warn("Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n"); 4539 port_type_array[0] = true; 4540 } 4541 4542 if (mlx4_log_num_mgm_entry_size < -7 || 4543 (mlx4_log_num_mgm_entry_size > 0 && 4544 (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE || 4545 mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE))) { 4546 pr_warn("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not in legal range (-7..0 or %d..%d)\n", 4547 mlx4_log_num_mgm_entry_size, 4548 MLX4_MIN_MGM_LOG_ENTRY_SIZE, 4549 MLX4_MAX_MGM_LOG_ENTRY_SIZE); 4550 return -1; 4551 } 4552 4553 return 0; 4554 } 4555 4556 static int __init mlx4_init(void) 4557 { 4558 int ret; 4559 4560 WARN_ONCE(strcmp(MLX4_ADEV_NAME, KBUILD_MODNAME), 4561 "mlx4_core name not in sync with kernel module name"); 4562 4563 if (mlx4_verify_params()) 4564 return -EINVAL; 4565 4566 4567 mlx4_wq = create_singlethread_workqueue("mlx4"); 4568 if (!mlx4_wq) 4569 return -ENOMEM; 4570 4571 ret = pci_register_driver(&mlx4_driver); 4572 if (ret < 0) 4573 destroy_workqueue(mlx4_wq); 4574 return ret < 0 ? ret : 0; 4575 } 4576 4577 static void __exit mlx4_cleanup(void) 4578 { 4579 pci_unregister_driver(&mlx4_driver); 4580 destroy_workqueue(mlx4_wq); 4581 } 4582 4583 module_init(mlx4_init); 4584 module_exit(mlx4_cleanup); 4585