1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #include <linux/etherdevice.h> 36 #include <linux/mlx4/cmd.h> 37 #include <linux/module.h> 38 #include <linux/cache.h> 39 40 #include "fw.h" 41 #include "icm.h" 42 43 enum { 44 MLX4_COMMAND_INTERFACE_MIN_REV = 2, 45 MLX4_COMMAND_INTERFACE_MAX_REV = 3, 46 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3, 47 }; 48 49 extern void __buggy_use_of_MLX4_GET(void); 50 extern void __buggy_use_of_MLX4_PUT(void); 51 52 static bool enable_qos = true; 53 module_param(enable_qos, bool, 0444); 54 MODULE_PARM_DESC(enable_qos, "Enable Enhanced QoS support (default: on)"); 55 56 #define MLX4_GET(dest, source, offset) \ 57 do { \ 58 void *__p = (char *) (source) + (offset); \ 59 u64 val; \ 60 switch (sizeof (dest)) { \ 61 case 1: (dest) = *(u8 *) __p; break; \ 62 case 2: (dest) = be16_to_cpup(__p); break; \ 63 case 4: (dest) = be32_to_cpup(__p); break; \ 64 case 8: val = get_unaligned((u64 *)__p); \ 65 (dest) = be64_to_cpu(val); break; \ 66 default: __buggy_use_of_MLX4_GET(); \ 67 } \ 68 } while (0) 69 70 #define MLX4_PUT(dest, source, offset) \ 71 do { \ 72 void *__d = ((char *) (dest) + (offset)); \ 73 switch (sizeof(source)) { \ 74 case 1: *(u8 *) __d = (source); break; \ 75 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \ 76 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \ 77 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \ 78 default: __buggy_use_of_MLX4_PUT(); \ 79 } \ 80 } while (0) 81 82 static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags) 83 { 84 static const char *fname[] = { 85 [ 0] = "RC transport", 86 [ 1] = "UC transport", 87 [ 2] = "UD transport", 88 [ 3] = "XRC transport", 89 [ 6] = "SRQ support", 90 [ 7] = "IPoIB checksum offload", 91 [ 8] = "P_Key violation counter", 92 [ 9] = "Q_Key violation counter", 93 [12] = "Dual Port Different Protocol (DPDP) support", 94 [15] = "Big LSO headers", 95 [16] = "MW support", 96 [17] = "APM support", 97 [18] = "Atomic ops support", 98 [19] = "Raw multicast support", 99 [20] = "Address vector port checking support", 100 [21] = "UD multicast support", 101 [30] = "IBoE support", 102 [32] = "Unicast loopback support", 103 [34] = "FCS header control", 104 [37] = "Wake On LAN (port1) support", 105 [38] = "Wake On LAN (port2) support", 106 [40] = "UDP RSS support", 107 [41] = "Unicast VEP steering support", 108 [42] = "Multicast VEP steering support", 109 [48] = "Counters support", 110 [52] = "RSS IP fragments support", 111 [53] = "Port ETS Scheduler support", 112 [55] = "Port link type sensing support", 113 [59] = "Port management change event support", 114 [61] = "64 byte EQE support", 115 [62] = "64 byte CQE support", 116 }; 117 int i; 118 119 mlx4_dbg(dev, "DEV_CAP flags:\n"); 120 for (i = 0; i < ARRAY_SIZE(fname); ++i) 121 if (fname[i] && (flags & (1LL << i))) 122 mlx4_dbg(dev, " %s\n", fname[i]); 123 } 124 125 static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags) 126 { 127 static const char * const fname[] = { 128 [0] = "RSS support", 129 [1] = "RSS Toeplitz Hash Function support", 130 [2] = "RSS XOR Hash Function support", 131 [3] = "Device managed flow steering support", 132 [4] = "Automatic MAC reassignment support", 133 [5] = "Time stamping support", 134 [6] = "VST (control vlan insertion/stripping) support", 135 [7] = "FSM (MAC anti-spoofing) support", 136 [8] = "Dynamic QP updates support", 137 [9] = "Device managed flow steering IPoIB support", 138 [10] = "TCP/IP offloads/flow-steering for VXLAN support", 139 [11] = "MAD DEMUX (Secure-Host) support", 140 [12] = "Large cache line (>64B) CQE stride support", 141 [13] = "Large cache line (>64B) EQE stride support", 142 [14] = "Ethernet protocol control support", 143 [15] = "Ethernet Backplane autoneg support", 144 [16] = "CONFIG DEV support", 145 [17] = "Asymmetric EQs support", 146 [18] = "More than 80 VFs support", 147 [19] = "Performance optimized for limited rule configuration flow steering support", 148 [20] = "Recoverable error events support", 149 [21] = "Port Remap support", 150 [22] = "QCN support", 151 [23] = "QP rate limiting support", 152 [24] = "Ethernet Flow control statistics support", 153 [25] = "Granular QoS per VF support", 154 [26] = "Port ETS Scheduler support", 155 [27] = "Port beacon support", 156 [28] = "RX-ALL support", 157 [29] = "802.1ad offload support", 158 }; 159 int i; 160 161 for (i = 0; i < ARRAY_SIZE(fname); ++i) 162 if (fname[i] && (flags & (1LL << i))) 163 mlx4_dbg(dev, " %s\n", fname[i]); 164 } 165 166 int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg) 167 { 168 struct mlx4_cmd_mailbox *mailbox; 169 u32 *inbox; 170 int err = 0; 171 172 #define MOD_STAT_CFG_IN_SIZE 0x100 173 174 #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002 175 #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003 176 177 mailbox = mlx4_alloc_cmd_mailbox(dev); 178 if (IS_ERR(mailbox)) 179 return PTR_ERR(mailbox); 180 inbox = mailbox->buf; 181 182 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET); 183 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET); 184 185 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG, 186 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 187 188 mlx4_free_cmd_mailbox(dev, mailbox); 189 return err; 190 } 191 192 int mlx4_QUERY_FUNC(struct mlx4_dev *dev, struct mlx4_func *func, int slave) 193 { 194 struct mlx4_cmd_mailbox *mailbox; 195 u32 *outbox; 196 u8 in_modifier; 197 u8 field; 198 u16 field16; 199 int err; 200 201 #define QUERY_FUNC_BUS_OFFSET 0x00 202 #define QUERY_FUNC_DEVICE_OFFSET 0x01 203 #define QUERY_FUNC_FUNCTION_OFFSET 0x01 204 #define QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET 0x03 205 #define QUERY_FUNC_RSVD_EQS_OFFSET 0x04 206 #define QUERY_FUNC_MAX_EQ_OFFSET 0x06 207 #define QUERY_FUNC_RSVD_UARS_OFFSET 0x0b 208 209 mailbox = mlx4_alloc_cmd_mailbox(dev); 210 if (IS_ERR(mailbox)) 211 return PTR_ERR(mailbox); 212 outbox = mailbox->buf; 213 214 in_modifier = slave; 215 216 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_modifier, 0, 217 MLX4_CMD_QUERY_FUNC, 218 MLX4_CMD_TIME_CLASS_A, 219 MLX4_CMD_NATIVE); 220 if (err) 221 goto out; 222 223 MLX4_GET(field, outbox, QUERY_FUNC_BUS_OFFSET); 224 func->bus = field & 0xf; 225 MLX4_GET(field, outbox, QUERY_FUNC_DEVICE_OFFSET); 226 func->device = field & 0xf1; 227 MLX4_GET(field, outbox, QUERY_FUNC_FUNCTION_OFFSET); 228 func->function = field & 0x7; 229 MLX4_GET(field, outbox, QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET); 230 func->physical_function = field & 0xf; 231 MLX4_GET(field16, outbox, QUERY_FUNC_RSVD_EQS_OFFSET); 232 func->rsvd_eqs = field16 & 0xffff; 233 MLX4_GET(field16, outbox, QUERY_FUNC_MAX_EQ_OFFSET); 234 func->max_eq = field16 & 0xffff; 235 MLX4_GET(field, outbox, QUERY_FUNC_RSVD_UARS_OFFSET); 236 func->rsvd_uars = field & 0x0f; 237 238 mlx4_dbg(dev, "Bus: %d, Device: %d, Function: %d, Physical function: %d, Max EQs: %d, Reserved EQs: %d, Reserved UARs: %d\n", 239 func->bus, func->device, func->function, func->physical_function, 240 func->max_eq, func->rsvd_eqs, func->rsvd_uars); 241 242 out: 243 mlx4_free_cmd_mailbox(dev, mailbox); 244 return err; 245 } 246 247 int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave, 248 struct mlx4_vhcr *vhcr, 249 struct mlx4_cmd_mailbox *inbox, 250 struct mlx4_cmd_mailbox *outbox, 251 struct mlx4_cmd_info *cmd) 252 { 253 struct mlx4_priv *priv = mlx4_priv(dev); 254 u8 field, port; 255 u32 size, proxy_qp, qkey; 256 int err = 0; 257 struct mlx4_func func; 258 259 #define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0 260 #define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1 261 #define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4 262 #define QUERY_FUNC_CAP_FMR_OFFSET 0x8 263 #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP 0x10 264 #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP 0x14 265 #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP 0x18 266 #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP 0x20 267 #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP 0x24 268 #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP 0x28 269 #define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c 270 #define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30 271 #define QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET 0x48 272 273 #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x50 274 #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x54 275 #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x58 276 #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x60 277 #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x64 278 #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x68 279 280 #define QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET 0x6c 281 282 #define QUERY_FUNC_CAP_FMR_FLAG 0x80 283 #define QUERY_FUNC_CAP_FLAG_RDMA 0x40 284 #define QUERY_FUNC_CAP_FLAG_ETH 0x80 285 #define QUERY_FUNC_CAP_FLAG_QUOTAS 0x10 286 #define QUERY_FUNC_CAP_FLAG_RESD_LKEY 0x08 287 #define QUERY_FUNC_CAP_FLAG_VALID_MAILBOX 0x04 288 289 #define QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG (1UL << 31) 290 #define QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG (1UL << 30) 291 292 /* when opcode modifier = 1 */ 293 #define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3 294 #define QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET 0x4 295 #define QUERY_FUNC_CAP_FLAGS0_OFFSET 0x8 296 #define QUERY_FUNC_CAP_FLAGS1_OFFSET 0xc 297 298 #define QUERY_FUNC_CAP_QP0_TUNNEL 0x10 299 #define QUERY_FUNC_CAP_QP0_PROXY 0x14 300 #define QUERY_FUNC_CAP_QP1_TUNNEL 0x18 301 #define QUERY_FUNC_CAP_QP1_PROXY 0x1c 302 #define QUERY_FUNC_CAP_PHYS_PORT_ID 0x28 303 304 #define QUERY_FUNC_CAP_FLAGS1_FORCE_MAC 0x40 305 #define QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN 0x80 306 #define QUERY_FUNC_CAP_FLAGS1_NIC_INFO 0x10 307 #define QUERY_FUNC_CAP_VF_ENABLE_QP0 0x08 308 309 #define QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID 0x80 310 #define QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS (1 << 31) 311 #define QUERY_FUNC_CAP_PHV_BIT 0x40 312 313 if (vhcr->op_modifier == 1) { 314 struct mlx4_active_ports actv_ports = 315 mlx4_get_active_ports(dev, slave); 316 int converted_port = mlx4_slave_convert_port( 317 dev, slave, vhcr->in_modifier); 318 319 if (converted_port < 0) 320 return -EINVAL; 321 322 vhcr->in_modifier = converted_port; 323 /* phys-port = logical-port */ 324 field = vhcr->in_modifier - 325 find_first_bit(actv_ports.ports, dev->caps.num_ports); 326 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); 327 328 port = vhcr->in_modifier; 329 proxy_qp = dev->phys_caps.base_proxy_sqpn + 8 * slave + port - 1; 330 331 /* Set nic_info bit to mark new fields support */ 332 field = QUERY_FUNC_CAP_FLAGS1_NIC_INFO; 333 334 if (mlx4_vf_smi_enabled(dev, slave, port) && 335 !mlx4_get_parav_qkey(dev, proxy_qp, &qkey)) { 336 field |= QUERY_FUNC_CAP_VF_ENABLE_QP0; 337 MLX4_PUT(outbox->buf, qkey, 338 QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET); 339 } 340 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS1_OFFSET); 341 342 /* size is now the QP number */ 343 size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + port - 1; 344 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL); 345 346 size += 2; 347 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL); 348 349 MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP0_PROXY); 350 proxy_qp += 2; 351 MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP1_PROXY); 352 353 MLX4_PUT(outbox->buf, dev->caps.phys_port_id[vhcr->in_modifier], 354 QUERY_FUNC_CAP_PHYS_PORT_ID); 355 356 if (dev->caps.phv_bit[port]) { 357 field = QUERY_FUNC_CAP_PHV_BIT; 358 MLX4_PUT(outbox->buf, field, 359 QUERY_FUNC_CAP_FLAGS0_OFFSET); 360 } 361 362 } else if (vhcr->op_modifier == 0) { 363 struct mlx4_active_ports actv_ports = 364 mlx4_get_active_ports(dev, slave); 365 /* enable rdma and ethernet interfaces, new quota locations, 366 * and reserved lkey 367 */ 368 field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA | 369 QUERY_FUNC_CAP_FLAG_QUOTAS | QUERY_FUNC_CAP_FLAG_VALID_MAILBOX | 370 QUERY_FUNC_CAP_FLAG_RESD_LKEY); 371 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET); 372 373 field = min( 374 bitmap_weight(actv_ports.ports, dev->caps.num_ports), 375 dev->caps.num_ports); 376 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); 377 378 size = dev->caps.function_caps; /* set PF behaviours */ 379 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET); 380 381 field = 0; /* protected FMR support not available as yet */ 382 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET); 383 384 size = priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[slave]; 385 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET); 386 size = dev->caps.num_qps; 387 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP); 388 389 size = priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[slave]; 390 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET); 391 size = dev->caps.num_srqs; 392 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP); 393 394 size = priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[slave]; 395 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET); 396 size = dev->caps.num_cqs; 397 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP); 398 399 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) || 400 mlx4_QUERY_FUNC(dev, &func, slave)) { 401 size = vhcr->in_modifier & 402 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS ? 403 dev->caps.num_eqs : 404 rounddown_pow_of_two(dev->caps.num_eqs); 405 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET); 406 size = dev->caps.reserved_eqs; 407 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); 408 } else { 409 size = vhcr->in_modifier & 410 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS ? 411 func.max_eq : 412 rounddown_pow_of_two(func.max_eq); 413 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET); 414 size = func.rsvd_eqs; 415 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); 416 } 417 418 size = priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[slave]; 419 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET); 420 size = dev->caps.num_mpts; 421 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP); 422 423 size = priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[slave]; 424 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET); 425 size = dev->caps.num_mtts; 426 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP); 427 428 size = dev->caps.num_mgms + dev->caps.num_amgms; 429 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET); 430 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP); 431 432 size = QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG | 433 QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG; 434 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET); 435 436 size = dev->caps.reserved_lkey + ((slave << 8) & 0xFF00); 437 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET); 438 } else 439 err = -EINVAL; 440 441 return err; 442 } 443 444 int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u8 gen_or_port, 445 struct mlx4_func_cap *func_cap) 446 { 447 struct mlx4_cmd_mailbox *mailbox; 448 u32 *outbox; 449 u8 field, op_modifier; 450 u32 size, qkey; 451 int err = 0, quotas = 0; 452 u32 in_modifier; 453 454 op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */ 455 in_modifier = op_modifier ? gen_or_port : 456 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS; 457 458 mailbox = mlx4_alloc_cmd_mailbox(dev); 459 if (IS_ERR(mailbox)) 460 return PTR_ERR(mailbox); 461 462 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_modifier, op_modifier, 463 MLX4_CMD_QUERY_FUNC_CAP, 464 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 465 if (err) 466 goto out; 467 468 outbox = mailbox->buf; 469 470 if (!op_modifier) { 471 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET); 472 if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) { 473 mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n"); 474 err = -EPROTONOSUPPORT; 475 goto out; 476 } 477 func_cap->flags = field; 478 quotas = !!(func_cap->flags & QUERY_FUNC_CAP_FLAG_QUOTAS); 479 480 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); 481 func_cap->num_ports = field; 482 483 MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET); 484 func_cap->pf_context_behaviour = size; 485 486 if (quotas) { 487 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET); 488 func_cap->qp_quota = size & 0xFFFFFF; 489 490 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET); 491 func_cap->srq_quota = size & 0xFFFFFF; 492 493 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET); 494 func_cap->cq_quota = size & 0xFFFFFF; 495 496 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET); 497 func_cap->mpt_quota = size & 0xFFFFFF; 498 499 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET); 500 func_cap->mtt_quota = size & 0xFFFFFF; 501 502 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET); 503 func_cap->mcg_quota = size & 0xFFFFFF; 504 505 } else { 506 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP); 507 func_cap->qp_quota = size & 0xFFFFFF; 508 509 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP); 510 func_cap->srq_quota = size & 0xFFFFFF; 511 512 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP); 513 func_cap->cq_quota = size & 0xFFFFFF; 514 515 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP); 516 func_cap->mpt_quota = size & 0xFFFFFF; 517 518 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP); 519 func_cap->mtt_quota = size & 0xFFFFFF; 520 521 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP); 522 func_cap->mcg_quota = size & 0xFFFFFF; 523 } 524 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET); 525 func_cap->max_eq = size & 0xFFFFFF; 526 527 MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); 528 func_cap->reserved_eq = size & 0xFFFFFF; 529 530 if (func_cap->flags & QUERY_FUNC_CAP_FLAG_RESD_LKEY) { 531 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET); 532 func_cap->reserved_lkey = size; 533 } else { 534 func_cap->reserved_lkey = 0; 535 } 536 537 func_cap->extra_flags = 0; 538 539 /* Mailbox data from 0x6c and onward should only be treated if 540 * QUERY_FUNC_CAP_FLAG_VALID_MAILBOX is set in func_cap->flags 541 */ 542 if (func_cap->flags & QUERY_FUNC_CAP_FLAG_VALID_MAILBOX) { 543 MLX4_GET(size, outbox, QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET); 544 if (size & QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG) 545 func_cap->extra_flags |= MLX4_QUERY_FUNC_FLAGS_BF_RES_QP; 546 if (size & QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG) 547 func_cap->extra_flags |= MLX4_QUERY_FUNC_FLAGS_A0_RES_QP; 548 } 549 550 goto out; 551 } 552 553 /* logical port query */ 554 if (gen_or_port > dev->caps.num_ports) { 555 err = -EINVAL; 556 goto out; 557 } 558 559 MLX4_GET(func_cap->flags1, outbox, QUERY_FUNC_CAP_FLAGS1_OFFSET); 560 if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) { 561 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN) { 562 mlx4_err(dev, "VLAN is enforced on this port\n"); 563 err = -EPROTONOSUPPORT; 564 goto out; 565 } 566 567 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_MAC) { 568 mlx4_err(dev, "Force mac is enabled on this port\n"); 569 err = -EPROTONOSUPPORT; 570 goto out; 571 } 572 } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) { 573 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET); 574 if (field & QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID) { 575 mlx4_err(dev, "phy_wqe_gid is enforced on this ib port\n"); 576 err = -EPROTONOSUPPORT; 577 goto out; 578 } 579 } 580 581 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); 582 func_cap->physical_port = field; 583 if (func_cap->physical_port != gen_or_port) { 584 err = -ENOSYS; 585 goto out; 586 } 587 588 if (func_cap->flags1 & QUERY_FUNC_CAP_VF_ENABLE_QP0) { 589 MLX4_GET(qkey, outbox, QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET); 590 func_cap->qp0_qkey = qkey; 591 } else { 592 func_cap->qp0_qkey = 0; 593 } 594 595 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL); 596 func_cap->qp0_tunnel_qpn = size & 0xFFFFFF; 597 598 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY); 599 func_cap->qp0_proxy_qpn = size & 0xFFFFFF; 600 601 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL); 602 func_cap->qp1_tunnel_qpn = size & 0xFFFFFF; 603 604 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY); 605 func_cap->qp1_proxy_qpn = size & 0xFFFFFF; 606 607 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_NIC_INFO) 608 MLX4_GET(func_cap->phys_port_id, outbox, 609 QUERY_FUNC_CAP_PHYS_PORT_ID); 610 611 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET); 612 func_cap->flags |= (field & QUERY_FUNC_CAP_PHV_BIT); 613 614 /* All other resources are allocated by the master, but we still report 615 * 'num' and 'reserved' capabilities as follows: 616 * - num remains the maximum resource index 617 * - 'num - reserved' is the total available objects of a resource, but 618 * resource indices may be less than 'reserved' 619 * TODO: set per-resource quotas */ 620 621 out: 622 mlx4_free_cmd_mailbox(dev, mailbox); 623 624 return err; 625 } 626 627 int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 628 { 629 struct mlx4_cmd_mailbox *mailbox; 630 u32 *outbox; 631 u8 field; 632 u32 field32, flags, ext_flags; 633 u16 size; 634 u16 stat_rate; 635 int err; 636 int i; 637 638 #define QUERY_DEV_CAP_OUT_SIZE 0x100 639 #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10 640 #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11 641 #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12 642 #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13 643 #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14 644 #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15 645 #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16 646 #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17 647 #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19 648 #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a 649 #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b 650 #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d 651 #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e 652 #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f 653 #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20 654 #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21 655 #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22 656 #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23 657 #define QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET 0x26 658 #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27 659 #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29 660 #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b 661 #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d 662 #define QUERY_DEV_CAP_RSS_OFFSET 0x2e 663 #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f 664 #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33 665 #define QUERY_DEV_CAP_PORT_BEACON_OFFSET 0x34 666 #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35 667 #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36 668 #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37 669 #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38 670 #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b 671 #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c 672 #define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e 673 #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f 674 #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40 675 #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44 676 #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48 677 #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49 678 #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b 679 #define QUERY_DEV_CAP_BF_OFFSET 0x4c 680 #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d 681 #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e 682 #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f 683 #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51 684 #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52 685 #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55 686 #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56 687 #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61 688 #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62 689 #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63 690 #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64 691 #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65 692 #define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66 693 #define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67 694 #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68 695 #define QUERY_DEV_CAP_PORT_FLOWSTATS_COUNTERS_OFFSET 0x70 696 #define QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET 0x70 697 #define QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET 0x74 698 #define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76 699 #define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77 700 #define QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE 0x7a 701 #define QUERY_DEV_CAP_ECN_QCN_VER_OFFSET 0x7b 702 #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80 703 #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82 704 #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84 705 #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86 706 #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88 707 #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a 708 #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c 709 #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e 710 #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90 711 #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92 712 #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94 713 #define QUERY_DEV_CAP_CONFIG_DEV_OFFSET 0x94 714 #define QUERY_DEV_CAP_PHV_EN_OFFSET 0x96 715 #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98 716 #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0 717 #define QUERY_DEV_CAP_ETH_BACKPL_OFFSET 0x9c 718 #define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d 719 #define QUERY_DEV_CAP_VXLAN 0x9e 720 #define QUERY_DEV_CAP_MAD_DEMUX_OFFSET 0xb0 721 #define QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_BASE_OFFSET 0xa8 722 #define QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_RANGE_OFFSET 0xac 723 #define QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET 0xcc 724 #define QUERY_DEV_CAP_QP_RATE_LIMIT_MAX_OFFSET 0xd0 725 #define QUERY_DEV_CAP_QP_RATE_LIMIT_MIN_OFFSET 0xd2 726 727 728 dev_cap->flags2 = 0; 729 mailbox = mlx4_alloc_cmd_mailbox(dev); 730 if (IS_ERR(mailbox)) 731 return PTR_ERR(mailbox); 732 outbox = mailbox->buf; 733 734 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, 735 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 736 if (err) 737 goto out; 738 739 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET); 740 dev_cap->reserved_qps = 1 << (field & 0xf); 741 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET); 742 dev_cap->max_qps = 1 << (field & 0x1f); 743 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET); 744 dev_cap->reserved_srqs = 1 << (field >> 4); 745 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET); 746 dev_cap->max_srqs = 1 << (field & 0x1f); 747 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET); 748 dev_cap->max_cq_sz = 1 << field; 749 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET); 750 dev_cap->reserved_cqs = 1 << (field & 0xf); 751 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET); 752 dev_cap->max_cqs = 1 << (field & 0x1f); 753 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET); 754 dev_cap->max_mpts = 1 << (field & 0x3f); 755 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET); 756 dev_cap->reserved_eqs = 1 << (field & 0xf); 757 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET); 758 dev_cap->max_eqs = 1 << (field & 0xf); 759 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET); 760 dev_cap->reserved_mtts = 1 << (field >> 4); 761 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET); 762 dev_cap->max_mrw_sz = 1 << field; 763 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET); 764 dev_cap->reserved_mrws = 1 << (field & 0xf); 765 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET); 766 dev_cap->max_mtt_seg = 1 << (field & 0x3f); 767 MLX4_GET(size, outbox, QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET); 768 dev_cap->num_sys_eqs = size & 0xfff; 769 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET); 770 dev_cap->max_requester_per_qp = 1 << (field & 0x3f); 771 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET); 772 dev_cap->max_responder_per_qp = 1 << (field & 0x3f); 773 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET); 774 field &= 0x1f; 775 if (!field) 776 dev_cap->max_gso_sz = 0; 777 else 778 dev_cap->max_gso_sz = 1 << field; 779 780 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET); 781 if (field & 0x20) 782 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR; 783 if (field & 0x10) 784 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP; 785 field &= 0xf; 786 if (field) { 787 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS; 788 dev_cap->max_rss_tbl_sz = 1 << field; 789 } else 790 dev_cap->max_rss_tbl_sz = 0; 791 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET); 792 dev_cap->max_rdma_global = 1 << (field & 0x3f); 793 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET); 794 dev_cap->local_ca_ack_delay = field & 0x1f; 795 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); 796 dev_cap->num_ports = field & 0xf; 797 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET); 798 dev_cap->max_msg_sz = 1 << (field & 0x1f); 799 MLX4_GET(field, outbox, QUERY_DEV_CAP_PORT_FLOWSTATS_COUNTERS_OFFSET); 800 if (field & 0x10) 801 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN; 802 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); 803 if (field & 0x80) 804 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN; 805 dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f; 806 MLX4_GET(field, outbox, QUERY_DEV_CAP_PORT_BEACON_OFFSET); 807 if (field & 0x80) 808 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PORT_BEACON; 809 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); 810 if (field & 0x80) 811 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_IPOIB; 812 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET); 813 dev_cap->fs_max_num_qp_per_entry = field; 814 MLX4_GET(field, outbox, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET); 815 if (field & 0x1) 816 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QCN; 817 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET); 818 dev_cap->stat_rate_support = stat_rate; 819 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); 820 if (field & 0x80) 821 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS; 822 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); 823 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET); 824 dev_cap->flags = flags | (u64)ext_flags << 32; 825 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET); 826 dev_cap->reserved_uars = field >> 4; 827 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET); 828 dev_cap->uar_size = 1 << ((field & 0x3f) + 20); 829 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET); 830 dev_cap->min_page_sz = 1 << field; 831 832 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET); 833 if (field & 0x80) { 834 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET); 835 dev_cap->bf_reg_size = 1 << (field & 0x1f); 836 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET); 837 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size)) 838 field = 3; 839 dev_cap->bf_regs_per_page = 1 << (field & 0x3f); 840 } else { 841 dev_cap->bf_reg_size = 0; 842 } 843 844 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET); 845 dev_cap->max_sq_sg = field; 846 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET); 847 dev_cap->max_sq_desc_sz = size; 848 849 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET); 850 dev_cap->max_qp_per_mcg = 1 << field; 851 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET); 852 dev_cap->reserved_mgms = field & 0xf; 853 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET); 854 dev_cap->max_mcgs = 1 << field; 855 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET); 856 dev_cap->reserved_pds = field >> 4; 857 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET); 858 dev_cap->max_pds = 1 << (field & 0x3f); 859 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET); 860 dev_cap->reserved_xrcds = field >> 4; 861 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET); 862 dev_cap->max_xrcds = 1 << (field & 0x1f); 863 864 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET); 865 dev_cap->rdmarc_entry_sz = size; 866 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET); 867 dev_cap->qpc_entry_sz = size; 868 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET); 869 dev_cap->aux_entry_sz = size; 870 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET); 871 dev_cap->altc_entry_sz = size; 872 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET); 873 dev_cap->eqc_entry_sz = size; 874 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET); 875 dev_cap->cqc_entry_sz = size; 876 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET); 877 dev_cap->srq_entry_sz = size; 878 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET); 879 dev_cap->cmpt_entry_sz = size; 880 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET); 881 dev_cap->mtt_entry_sz = size; 882 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET); 883 dev_cap->dmpt_entry_sz = size; 884 885 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET); 886 dev_cap->max_srq_sz = 1 << field; 887 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET); 888 dev_cap->max_qp_sz = 1 << field; 889 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET); 890 dev_cap->resize_srq = field & 1; 891 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET); 892 dev_cap->max_rq_sg = field; 893 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET); 894 dev_cap->max_rq_desc_sz = size; 895 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE); 896 if (field & (1 << 4)) 897 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QOS_VPP; 898 if (field & (1 << 5)) 899 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL; 900 if (field & (1 << 6)) 901 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CQE_STRIDE; 902 if (field & (1 << 7)) 903 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_EQE_STRIDE; 904 MLX4_GET(dev_cap->bmme_flags, outbox, 905 QUERY_DEV_CAP_BMME_FLAGS_OFFSET); 906 if (dev_cap->bmme_flags & MLX4_FLAG_PORT_REMAP) 907 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PORT_REMAP; 908 MLX4_GET(field, outbox, QUERY_DEV_CAP_CONFIG_DEV_OFFSET); 909 if (field & 0x20) 910 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CONFIG_DEV; 911 if (field & (1 << 2)) 912 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_IGNORE_FCS; 913 MLX4_GET(field, outbox, QUERY_DEV_CAP_PHV_EN_OFFSET); 914 if (field & 0x80) 915 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PHV_EN; 916 if (field & 0x40) 917 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN; 918 919 MLX4_GET(dev_cap->reserved_lkey, outbox, 920 QUERY_DEV_CAP_RSVD_LKEY_OFFSET); 921 MLX4_GET(field32, outbox, QUERY_DEV_CAP_ETH_BACKPL_OFFSET); 922 if (field32 & (1 << 0)) 923 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP; 924 if (field32 & (1 << 7)) 925 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT; 926 MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC); 927 if (field & 1<<6) 928 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN; 929 MLX4_GET(field, outbox, QUERY_DEV_CAP_VXLAN); 930 if (field & 1<<3) 931 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS; 932 if (field & (1 << 5)) 933 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG; 934 MLX4_GET(dev_cap->max_icm_sz, outbox, 935 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET); 936 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS) 937 MLX4_GET(dev_cap->max_counters, outbox, 938 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET); 939 940 MLX4_GET(field32, outbox, 941 QUERY_DEV_CAP_MAD_DEMUX_OFFSET); 942 if (field32 & (1 << 0)) 943 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_MAD_DEMUX; 944 945 MLX4_GET(dev_cap->dmfs_high_rate_qpn_base, outbox, 946 QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_BASE_OFFSET); 947 dev_cap->dmfs_high_rate_qpn_base &= MGM_QPN_MASK; 948 MLX4_GET(dev_cap->dmfs_high_rate_qpn_range, outbox, 949 QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_RANGE_OFFSET); 950 dev_cap->dmfs_high_rate_qpn_range &= MGM_QPN_MASK; 951 952 MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET); 953 dev_cap->rl_caps.num_rates = size; 954 if (dev_cap->rl_caps.num_rates) { 955 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT; 956 MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_MAX_OFFSET); 957 dev_cap->rl_caps.max_val = size & 0xfff; 958 dev_cap->rl_caps.max_unit = size >> 14; 959 MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_MIN_OFFSET); 960 dev_cap->rl_caps.min_val = size & 0xfff; 961 dev_cap->rl_caps.min_unit = size >> 14; 962 } 963 964 MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); 965 if (field32 & (1 << 16)) 966 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP; 967 if (field32 & (1 << 26)) 968 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL; 969 if (field32 & (1 << 20)) 970 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM; 971 if (field32 & (1 << 21)) 972 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_80_VFS; 973 974 for (i = 1; i <= dev_cap->num_ports; i++) { 975 err = mlx4_QUERY_PORT(dev, i, dev_cap->port_cap + i); 976 if (err) 977 goto out; 978 } 979 980 /* 981 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then 982 * we can't use any EQs whose doorbell falls on that page, 983 * even if the EQ itself isn't reserved. 984 */ 985 if (dev_cap->num_sys_eqs == 0) 986 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4, 987 dev_cap->reserved_eqs); 988 else 989 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SYS_EQS; 990 991 out: 992 mlx4_free_cmd_mailbox(dev, mailbox); 993 return err; 994 } 995 996 void mlx4_dev_cap_dump(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 997 { 998 if (dev_cap->bf_reg_size > 0) 999 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n", 1000 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page); 1001 else 1002 mlx4_dbg(dev, "BlueFlame not available\n"); 1003 1004 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n", 1005 dev_cap->bmme_flags, dev_cap->reserved_lkey); 1006 mlx4_dbg(dev, "Max ICM size %lld MB\n", 1007 (unsigned long long) dev_cap->max_icm_sz >> 20); 1008 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n", 1009 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz); 1010 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n", 1011 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz); 1012 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n", 1013 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz); 1014 mlx4_dbg(dev, "Num sys EQs: %d, max EQs: %d, reserved EQs: %d, entry size: %d\n", 1015 dev_cap->num_sys_eqs, dev_cap->max_eqs, dev_cap->reserved_eqs, 1016 dev_cap->eqc_entry_sz); 1017 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n", 1018 dev_cap->reserved_mrws, dev_cap->reserved_mtts); 1019 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n", 1020 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars); 1021 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n", 1022 dev_cap->max_pds, dev_cap->reserved_mgms); 1023 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n", 1024 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz); 1025 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n", 1026 dev_cap->local_ca_ack_delay, 128 << dev_cap->port_cap[1].ib_mtu, 1027 dev_cap->port_cap[1].max_port_width); 1028 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n", 1029 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg); 1030 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n", 1031 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg); 1032 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz); 1033 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters); 1034 mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz); 1035 mlx4_dbg(dev, "DMFS high rate steer QPn base: %d\n", 1036 dev_cap->dmfs_high_rate_qpn_base); 1037 mlx4_dbg(dev, "DMFS high rate steer QPn range: %d\n", 1038 dev_cap->dmfs_high_rate_qpn_range); 1039 1040 if (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT) { 1041 struct mlx4_rate_limit_caps *rl_caps = &dev_cap->rl_caps; 1042 1043 mlx4_dbg(dev, "QP Rate-Limit: #rates %d, unit/val max %d/%d, min %d/%d\n", 1044 rl_caps->num_rates, rl_caps->max_unit, rl_caps->max_val, 1045 rl_caps->min_unit, rl_caps->min_val); 1046 } 1047 1048 dump_dev_cap_flags(dev, dev_cap->flags); 1049 dump_dev_cap_flags2(dev, dev_cap->flags2); 1050 } 1051 1052 int mlx4_QUERY_PORT(struct mlx4_dev *dev, int port, struct mlx4_port_cap *port_cap) 1053 { 1054 struct mlx4_cmd_mailbox *mailbox; 1055 u32 *outbox; 1056 u8 field; 1057 u32 field32; 1058 int err; 1059 1060 mailbox = mlx4_alloc_cmd_mailbox(dev); 1061 if (IS_ERR(mailbox)) 1062 return PTR_ERR(mailbox); 1063 outbox = mailbox->buf; 1064 1065 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { 1066 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, 1067 MLX4_CMD_TIME_CLASS_A, 1068 MLX4_CMD_NATIVE); 1069 1070 if (err) 1071 goto out; 1072 1073 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); 1074 port_cap->max_vl = field >> 4; 1075 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET); 1076 port_cap->ib_mtu = field >> 4; 1077 port_cap->max_port_width = field & 0xf; 1078 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET); 1079 port_cap->max_gids = 1 << (field & 0xf); 1080 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET); 1081 port_cap->max_pkeys = 1 << (field & 0xf); 1082 } else { 1083 #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00 1084 #define QUERY_PORT_MTU_OFFSET 0x01 1085 #define QUERY_PORT_ETH_MTU_OFFSET 0x02 1086 #define QUERY_PORT_WIDTH_OFFSET 0x06 1087 #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07 1088 #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a 1089 #define QUERY_PORT_MAX_VL_OFFSET 0x0b 1090 #define QUERY_PORT_MAC_OFFSET 0x10 1091 #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18 1092 #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c 1093 #define QUERY_PORT_TRANS_CODE_OFFSET 0x20 1094 1095 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0, MLX4_CMD_QUERY_PORT, 1096 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 1097 if (err) 1098 goto out; 1099 1100 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET); 1101 port_cap->supported_port_types = field & 3; 1102 port_cap->suggested_type = (field >> 3) & 1; 1103 port_cap->default_sense = (field >> 4) & 1; 1104 port_cap->dmfs_optimized_state = (field >> 5) & 1; 1105 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET); 1106 port_cap->ib_mtu = field & 0xf; 1107 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET); 1108 port_cap->max_port_width = field & 0xf; 1109 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET); 1110 port_cap->max_gids = 1 << (field >> 4); 1111 port_cap->max_pkeys = 1 << (field & 0xf); 1112 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET); 1113 port_cap->max_vl = field & 0xf; 1114 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET); 1115 port_cap->log_max_macs = field & 0xf; 1116 port_cap->log_max_vlans = field >> 4; 1117 MLX4_GET(port_cap->eth_mtu, outbox, QUERY_PORT_ETH_MTU_OFFSET); 1118 MLX4_GET(port_cap->def_mac, outbox, QUERY_PORT_MAC_OFFSET); 1119 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET); 1120 port_cap->trans_type = field32 >> 24; 1121 port_cap->vendor_oui = field32 & 0xffffff; 1122 MLX4_GET(port_cap->wavelength, outbox, QUERY_PORT_WAVELENGTH_OFFSET); 1123 MLX4_GET(port_cap->trans_code, outbox, QUERY_PORT_TRANS_CODE_OFFSET); 1124 } 1125 1126 out: 1127 mlx4_free_cmd_mailbox(dev, mailbox); 1128 return err; 1129 } 1130 1131 #define DEV_CAP_EXT_2_FLAG_PFC_COUNTERS (1 << 28) 1132 #define DEV_CAP_EXT_2_FLAG_VLAN_CONTROL (1 << 26) 1133 #define DEV_CAP_EXT_2_FLAG_80_VFS (1 << 21) 1134 #define DEV_CAP_EXT_2_FLAG_FSM (1 << 20) 1135 1136 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave, 1137 struct mlx4_vhcr *vhcr, 1138 struct mlx4_cmd_mailbox *inbox, 1139 struct mlx4_cmd_mailbox *outbox, 1140 struct mlx4_cmd_info *cmd) 1141 { 1142 u64 flags; 1143 int err = 0; 1144 u8 field; 1145 u16 field16; 1146 u32 bmme_flags, field32; 1147 int real_port; 1148 int slave_port; 1149 int first_port; 1150 struct mlx4_active_ports actv_ports; 1151 1152 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, 1153 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1154 if (err) 1155 return err; 1156 1157 /* add port mng change event capability and disable mw type 1 1158 * unconditionally to slaves 1159 */ 1160 MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); 1161 flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV; 1162 flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW; 1163 actv_ports = mlx4_get_active_ports(dev, slave); 1164 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports); 1165 for (slave_port = 0, real_port = first_port; 1166 real_port < first_port + 1167 bitmap_weight(actv_ports.ports, dev->caps.num_ports); 1168 ++real_port, ++slave_port) { 1169 if (flags & (MLX4_DEV_CAP_FLAG_WOL_PORT1 << real_port)) 1170 flags |= MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port; 1171 else 1172 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port); 1173 } 1174 for (; slave_port < dev->caps.num_ports; ++slave_port) 1175 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port); 1176 1177 /* Not exposing RSS IP fragments to guests */ 1178 flags &= ~MLX4_DEV_CAP_FLAG_RSS_IP_FRAG; 1179 MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); 1180 1181 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VL_PORT_OFFSET); 1182 field &= ~0x0F; 1183 field |= bitmap_weight(actv_ports.ports, dev->caps.num_ports) & 0x0F; 1184 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VL_PORT_OFFSET); 1185 1186 /* For guests, disable timestamp */ 1187 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); 1188 field &= 0x7f; 1189 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); 1190 1191 /* For guests, disable vxlan tunneling and QoS support */ 1192 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VXLAN); 1193 field &= 0xd7; 1194 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VXLAN); 1195 1196 /* For guests, disable port BEACON */ 1197 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_PORT_BEACON_OFFSET); 1198 field &= 0x7f; 1199 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_PORT_BEACON_OFFSET); 1200 1201 /* For guests, report Blueflame disabled */ 1202 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET); 1203 field &= 0x7f; 1204 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET); 1205 1206 /* For guests, disable mw type 2 and port remap*/ 1207 MLX4_GET(bmme_flags, outbox->buf, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); 1208 bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN; 1209 bmme_flags &= ~MLX4_FLAG_PORT_REMAP; 1210 MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); 1211 1212 /* turn off device-managed steering capability if not enabled */ 1213 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) { 1214 MLX4_GET(field, outbox->buf, 1215 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); 1216 field &= 0x7f; 1217 MLX4_PUT(outbox->buf, field, 1218 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); 1219 } 1220 1221 /* turn off ipoib managed steering for guests */ 1222 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); 1223 field &= ~0x80; 1224 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); 1225 1226 /* turn off host side virt features (VST, FSM, etc) for guests */ 1227 MLX4_GET(field32, outbox->buf, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); 1228 field32 &= ~(DEV_CAP_EXT_2_FLAG_VLAN_CONTROL | DEV_CAP_EXT_2_FLAG_80_VFS | 1229 DEV_CAP_EXT_2_FLAG_FSM | DEV_CAP_EXT_2_FLAG_PFC_COUNTERS); 1230 MLX4_PUT(outbox->buf, field32, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); 1231 1232 /* turn off QCN for guests */ 1233 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET); 1234 field &= 0xfe; 1235 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET); 1236 1237 /* turn off QP max-rate limiting for guests */ 1238 field16 = 0; 1239 MLX4_PUT(outbox->buf, field16, QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET); 1240 1241 /* turn off QoS per VF support for guests */ 1242 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE); 1243 field &= 0xef; 1244 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE); 1245 1246 /* turn off ignore FCS feature for guests */ 1247 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CONFIG_DEV_OFFSET); 1248 field &= 0xfb; 1249 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CONFIG_DEV_OFFSET); 1250 1251 return 0; 1252 } 1253 1254 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave, 1255 struct mlx4_vhcr *vhcr, 1256 struct mlx4_cmd_mailbox *inbox, 1257 struct mlx4_cmd_mailbox *outbox, 1258 struct mlx4_cmd_info *cmd) 1259 { 1260 struct mlx4_priv *priv = mlx4_priv(dev); 1261 u64 def_mac; 1262 u8 port_type; 1263 u16 short_field; 1264 int err; 1265 int admin_link_state; 1266 int port = mlx4_slave_convert_port(dev, slave, 1267 vhcr->in_modifier & 0xFF); 1268 1269 #define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0 1270 #define MLX4_PORT_LINK_UP_MASK 0x80 1271 #define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c 1272 #define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e 1273 1274 if (port < 0) 1275 return -EINVAL; 1276 1277 /* Protect against untrusted guests: enforce that this is the 1278 * QUERY_PORT general query. 1279 */ 1280 if (vhcr->op_modifier || vhcr->in_modifier & ~0xFF) 1281 return -EINVAL; 1282 1283 vhcr->in_modifier = port; 1284 1285 err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0, 1286 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, 1287 MLX4_CMD_NATIVE); 1288 1289 if (!err && dev->caps.function != slave) { 1290 def_mac = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac; 1291 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET); 1292 1293 /* get port type - currently only eth is enabled */ 1294 MLX4_GET(port_type, outbox->buf, 1295 QUERY_PORT_SUPPORTED_TYPE_OFFSET); 1296 1297 /* No link sensing allowed */ 1298 port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK; 1299 /* set port type to currently operating port type */ 1300 port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3); 1301 1302 admin_link_state = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.link_state; 1303 if (IFLA_VF_LINK_STATE_ENABLE == admin_link_state) 1304 port_type |= MLX4_PORT_LINK_UP_MASK; 1305 else if (IFLA_VF_LINK_STATE_DISABLE == admin_link_state) 1306 port_type &= ~MLX4_PORT_LINK_UP_MASK; 1307 1308 MLX4_PUT(outbox->buf, port_type, 1309 QUERY_PORT_SUPPORTED_TYPE_OFFSET); 1310 1311 if (dev->caps.port_type[vhcr->in_modifier] == MLX4_PORT_TYPE_ETH) 1312 short_field = mlx4_get_slave_num_gids(dev, slave, port); 1313 else 1314 short_field = 1; /* slave max gids */ 1315 MLX4_PUT(outbox->buf, short_field, 1316 QUERY_PORT_CUR_MAX_GID_OFFSET); 1317 1318 short_field = dev->caps.pkey_table_len[vhcr->in_modifier]; 1319 MLX4_PUT(outbox->buf, short_field, 1320 QUERY_PORT_CUR_MAX_PKEY_OFFSET); 1321 } 1322 1323 return err; 1324 } 1325 1326 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port, 1327 int *gid_tbl_len, int *pkey_tbl_len) 1328 { 1329 struct mlx4_cmd_mailbox *mailbox; 1330 u32 *outbox; 1331 u16 field; 1332 int err; 1333 1334 mailbox = mlx4_alloc_cmd_mailbox(dev); 1335 if (IS_ERR(mailbox)) 1336 return PTR_ERR(mailbox); 1337 1338 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0, 1339 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, 1340 MLX4_CMD_WRAPPED); 1341 if (err) 1342 goto out; 1343 1344 outbox = mailbox->buf; 1345 1346 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET); 1347 *gid_tbl_len = field; 1348 1349 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET); 1350 *pkey_tbl_len = field; 1351 1352 out: 1353 mlx4_free_cmd_mailbox(dev, mailbox); 1354 return err; 1355 } 1356 EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len); 1357 1358 int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt) 1359 { 1360 struct mlx4_cmd_mailbox *mailbox; 1361 struct mlx4_icm_iter iter; 1362 __be64 *pages; 1363 int lg; 1364 int nent = 0; 1365 int i; 1366 int err = 0; 1367 int ts = 0, tc = 0; 1368 1369 mailbox = mlx4_alloc_cmd_mailbox(dev); 1370 if (IS_ERR(mailbox)) 1371 return PTR_ERR(mailbox); 1372 pages = mailbox->buf; 1373 1374 for (mlx4_icm_first(icm, &iter); 1375 !mlx4_icm_last(&iter); 1376 mlx4_icm_next(&iter)) { 1377 /* 1378 * We have to pass pages that are aligned to their 1379 * size, so find the least significant 1 in the 1380 * address or size and use that as our log2 size. 1381 */ 1382 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1; 1383 if (lg < MLX4_ICM_PAGE_SHIFT) { 1384 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx)\n", 1385 MLX4_ICM_PAGE_SIZE, 1386 (unsigned long long) mlx4_icm_addr(&iter), 1387 mlx4_icm_size(&iter)); 1388 err = -EINVAL; 1389 goto out; 1390 } 1391 1392 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) { 1393 if (virt != -1) { 1394 pages[nent * 2] = cpu_to_be64(virt); 1395 virt += 1 << lg; 1396 } 1397 1398 pages[nent * 2 + 1] = 1399 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) | 1400 (lg - MLX4_ICM_PAGE_SHIFT)); 1401 ts += 1 << (lg - 10); 1402 ++tc; 1403 1404 if (++nent == MLX4_MAILBOX_SIZE / 16) { 1405 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, 1406 MLX4_CMD_TIME_CLASS_B, 1407 MLX4_CMD_NATIVE); 1408 if (err) 1409 goto out; 1410 nent = 0; 1411 } 1412 } 1413 } 1414 1415 if (nent) 1416 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, 1417 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 1418 if (err) 1419 goto out; 1420 1421 switch (op) { 1422 case MLX4_CMD_MAP_FA: 1423 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW\n", tc, ts); 1424 break; 1425 case MLX4_CMD_MAP_ICM_AUX: 1426 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux\n", tc, ts); 1427 break; 1428 case MLX4_CMD_MAP_ICM: 1429 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM\n", 1430 tc, ts, (unsigned long long) virt - (ts << 10)); 1431 break; 1432 } 1433 1434 out: 1435 mlx4_free_cmd_mailbox(dev, mailbox); 1436 return err; 1437 } 1438 1439 int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm) 1440 { 1441 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1); 1442 } 1443 1444 int mlx4_UNMAP_FA(struct mlx4_dev *dev) 1445 { 1446 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA, 1447 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 1448 } 1449 1450 1451 int mlx4_RUN_FW(struct mlx4_dev *dev) 1452 { 1453 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW, 1454 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1455 } 1456 1457 int mlx4_QUERY_FW(struct mlx4_dev *dev) 1458 { 1459 struct mlx4_fw *fw = &mlx4_priv(dev)->fw; 1460 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd; 1461 struct mlx4_cmd_mailbox *mailbox; 1462 u32 *outbox; 1463 int err = 0; 1464 u64 fw_ver; 1465 u16 cmd_if_rev; 1466 u8 lg; 1467 1468 #define QUERY_FW_OUT_SIZE 0x100 1469 #define QUERY_FW_VER_OFFSET 0x00 1470 #define QUERY_FW_PPF_ID 0x09 1471 #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a 1472 #define QUERY_FW_MAX_CMD_OFFSET 0x0f 1473 #define QUERY_FW_ERR_START_OFFSET 0x30 1474 #define QUERY_FW_ERR_SIZE_OFFSET 0x38 1475 #define QUERY_FW_ERR_BAR_OFFSET 0x3c 1476 1477 #define QUERY_FW_SIZE_OFFSET 0x00 1478 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20 1479 #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28 1480 1481 #define QUERY_FW_COMM_BASE_OFFSET 0x40 1482 #define QUERY_FW_COMM_BAR_OFFSET 0x48 1483 1484 #define QUERY_FW_CLOCK_OFFSET 0x50 1485 #define QUERY_FW_CLOCK_BAR 0x58 1486 1487 mailbox = mlx4_alloc_cmd_mailbox(dev); 1488 if (IS_ERR(mailbox)) 1489 return PTR_ERR(mailbox); 1490 outbox = mailbox->buf; 1491 1492 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW, 1493 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1494 if (err) 1495 goto out; 1496 1497 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET); 1498 /* 1499 * FW subminor version is at more significant bits than minor 1500 * version, so swap here. 1501 */ 1502 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) | 1503 ((fw_ver & 0xffff0000ull) >> 16) | 1504 ((fw_ver & 0x0000ffffull) << 16); 1505 1506 MLX4_GET(lg, outbox, QUERY_FW_PPF_ID); 1507 dev->caps.function = lg; 1508 1509 if (mlx4_is_slave(dev)) 1510 goto out; 1511 1512 1513 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET); 1514 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV || 1515 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) { 1516 mlx4_err(dev, "Installed FW has unsupported command interface revision %d\n", 1517 cmd_if_rev); 1518 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n", 1519 (int) (dev->caps.fw_ver >> 32), 1520 (int) (dev->caps.fw_ver >> 16) & 0xffff, 1521 (int) dev->caps.fw_ver & 0xffff); 1522 mlx4_err(dev, "This driver version supports only revisions %d to %d\n", 1523 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV); 1524 err = -ENODEV; 1525 goto out; 1526 } 1527 1528 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS) 1529 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS; 1530 1531 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET); 1532 cmd->max_cmds = 1 << lg; 1533 1534 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n", 1535 (int) (dev->caps.fw_ver >> 32), 1536 (int) (dev->caps.fw_ver >> 16) & 0xffff, 1537 (int) dev->caps.fw_ver & 0xffff, 1538 cmd_if_rev, cmd->max_cmds); 1539 1540 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET); 1541 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET); 1542 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET); 1543 fw->catas_bar = (fw->catas_bar >> 6) * 2; 1544 1545 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n", 1546 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar); 1547 1548 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET); 1549 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET); 1550 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET); 1551 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2; 1552 1553 MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET); 1554 MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET); 1555 fw->comm_bar = (fw->comm_bar >> 6) * 2; 1556 mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n", 1557 fw->comm_bar, fw->comm_base); 1558 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2); 1559 1560 MLX4_GET(fw->clock_offset, outbox, QUERY_FW_CLOCK_OFFSET); 1561 MLX4_GET(fw->clock_bar, outbox, QUERY_FW_CLOCK_BAR); 1562 fw->clock_bar = (fw->clock_bar >> 6) * 2; 1563 mlx4_dbg(dev, "Internal clock bar:%d offset:0x%llx\n", 1564 fw->clock_bar, fw->clock_offset); 1565 1566 /* 1567 * Round up number of system pages needed in case 1568 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. 1569 */ 1570 fw->fw_pages = 1571 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> 1572 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); 1573 1574 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n", 1575 (unsigned long long) fw->clr_int_base, fw->clr_int_bar); 1576 1577 out: 1578 mlx4_free_cmd_mailbox(dev, mailbox); 1579 return err; 1580 } 1581 1582 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave, 1583 struct mlx4_vhcr *vhcr, 1584 struct mlx4_cmd_mailbox *inbox, 1585 struct mlx4_cmd_mailbox *outbox, 1586 struct mlx4_cmd_info *cmd) 1587 { 1588 u8 *outbuf; 1589 int err; 1590 1591 outbuf = outbox->buf; 1592 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW, 1593 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1594 if (err) 1595 return err; 1596 1597 /* for slaves, set pci PPF ID to invalid and zero out everything 1598 * else except FW version */ 1599 outbuf[0] = outbuf[1] = 0; 1600 memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8); 1601 outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID; 1602 1603 return 0; 1604 } 1605 1606 static void get_board_id(void *vsd, char *board_id) 1607 { 1608 int i; 1609 1610 #define VSD_OFFSET_SIG1 0x00 1611 #define VSD_OFFSET_SIG2 0xde 1612 #define VSD_OFFSET_MLX_BOARD_ID 0xd0 1613 #define VSD_OFFSET_TS_BOARD_ID 0x20 1614 1615 #define VSD_SIGNATURE_TOPSPIN 0x5ad 1616 1617 memset(board_id, 0, MLX4_BOARD_ID_LEN); 1618 1619 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN && 1620 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) { 1621 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN); 1622 } else { 1623 /* 1624 * The board ID is a string but the firmware byte 1625 * swaps each 4-byte word before passing it back to 1626 * us. Therefore we need to swab it before printing. 1627 */ 1628 u32 *bid_u32 = (u32 *)board_id; 1629 1630 for (i = 0; i < 4; ++i) { 1631 u32 *addr; 1632 u32 val; 1633 1634 addr = (u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4); 1635 val = get_unaligned(addr); 1636 val = swab32(val); 1637 put_unaligned(val, &bid_u32[i]); 1638 } 1639 } 1640 } 1641 1642 int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter) 1643 { 1644 struct mlx4_cmd_mailbox *mailbox; 1645 u32 *outbox; 1646 int err; 1647 1648 #define QUERY_ADAPTER_OUT_SIZE 0x100 1649 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10 1650 #define QUERY_ADAPTER_VSD_OFFSET 0x20 1651 1652 mailbox = mlx4_alloc_cmd_mailbox(dev); 1653 if (IS_ERR(mailbox)) 1654 return PTR_ERR(mailbox); 1655 outbox = mailbox->buf; 1656 1657 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER, 1658 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1659 if (err) 1660 goto out; 1661 1662 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET); 1663 1664 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4, 1665 adapter->board_id); 1666 1667 out: 1668 mlx4_free_cmd_mailbox(dev, mailbox); 1669 return err; 1670 } 1671 1672 int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param) 1673 { 1674 struct mlx4_cmd_mailbox *mailbox; 1675 __be32 *inbox; 1676 int err; 1677 static const u8 a0_dmfs_hw_steering[] = { 1678 [MLX4_STEERING_DMFS_A0_DEFAULT] = 0, 1679 [MLX4_STEERING_DMFS_A0_DYNAMIC] = 1, 1680 [MLX4_STEERING_DMFS_A0_STATIC] = 2, 1681 [MLX4_STEERING_DMFS_A0_DISABLE] = 3 1682 }; 1683 1684 #define INIT_HCA_IN_SIZE 0x200 1685 #define INIT_HCA_VERSION_OFFSET 0x000 1686 #define INIT_HCA_VERSION 2 1687 #define INIT_HCA_VXLAN_OFFSET 0x0c 1688 #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e 1689 #define INIT_HCA_FLAGS_OFFSET 0x014 1690 #define INIT_HCA_RECOVERABLE_ERROR_EVENT_OFFSET 0x018 1691 #define INIT_HCA_QPC_OFFSET 0x020 1692 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10) 1693 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17) 1694 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28) 1695 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f) 1696 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30) 1697 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37) 1698 #define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38) 1699 #define INIT_HCA_EQE_CQE_STRIDE_OFFSET (INIT_HCA_QPC_OFFSET + 0x3b) 1700 #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40) 1701 #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50) 1702 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60) 1703 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67) 1704 #define INIT_HCA_NUM_SYS_EQS_OFFSET (INIT_HCA_QPC_OFFSET + 0x6a) 1705 #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70) 1706 #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77) 1707 #define INIT_HCA_MCAST_OFFSET 0x0c0 1708 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00) 1709 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12) 1710 #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16) 1711 #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18) 1712 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b) 1713 #define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6 1714 #define INIT_HCA_FS_PARAM_OFFSET 0x1d0 1715 #define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00) 1716 #define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12) 1717 #define INIT_HCA_FS_A0_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x18) 1718 #define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b) 1719 #define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21) 1720 #define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22) 1721 #define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25) 1722 #define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26) 1723 #define INIT_HCA_TPT_OFFSET 0x0f0 1724 #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00) 1725 #define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08) 1726 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b) 1727 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10) 1728 #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18) 1729 #define INIT_HCA_UAR_OFFSET 0x120 1730 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a) 1731 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b) 1732 1733 mailbox = mlx4_alloc_cmd_mailbox(dev); 1734 if (IS_ERR(mailbox)) 1735 return PTR_ERR(mailbox); 1736 inbox = mailbox->buf; 1737 1738 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION; 1739 1740 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) = 1741 (ilog2(cache_line_size()) - 4) << 5; 1742 1743 #if defined(__LITTLE_ENDIAN) 1744 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1); 1745 #elif defined(__BIG_ENDIAN) 1746 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1); 1747 #else 1748 #error Host endianness not defined 1749 #endif 1750 /* Check port for UD address vector: */ 1751 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1); 1752 1753 /* Enable IPoIB checksumming if we can: */ 1754 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM) 1755 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3); 1756 1757 /* Enable QoS support if module parameter set */ 1758 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG && enable_qos) 1759 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2); 1760 1761 /* enable counters */ 1762 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS) 1763 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4); 1764 1765 /* Enable RSS spread to fragmented IP packets when supported */ 1766 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_RSS_IP_FRAG) 1767 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 13); 1768 1769 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */ 1770 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) { 1771 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29); 1772 dev->caps.eqe_size = 64; 1773 dev->caps.eqe_factor = 1; 1774 } else { 1775 dev->caps.eqe_size = 32; 1776 dev->caps.eqe_factor = 0; 1777 } 1778 1779 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) { 1780 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30); 1781 dev->caps.cqe_size = 64; 1782 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; 1783 } else { 1784 dev->caps.cqe_size = 32; 1785 } 1786 1787 /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */ 1788 if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) && 1789 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE)) { 1790 dev->caps.eqe_size = cache_line_size(); 1791 dev->caps.cqe_size = cache_line_size(); 1792 dev->caps.eqe_factor = 0; 1793 MLX4_PUT(inbox, (u8)((ilog2(dev->caps.eqe_size) - 5) << 4 | 1794 (ilog2(dev->caps.eqe_size) - 5)), 1795 INIT_HCA_EQE_CQE_STRIDE_OFFSET); 1796 1797 /* User still need to know to support CQE > 32B */ 1798 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; 1799 } 1800 1801 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT) 1802 *(inbox + INIT_HCA_RECOVERABLE_ERROR_EVENT_OFFSET / 4) |= cpu_to_be32(1 << 31); 1803 1804 /* QPC/EEC/CQC/EQC/RDMARC attributes */ 1805 1806 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET); 1807 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET); 1808 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET); 1809 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET); 1810 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET); 1811 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET); 1812 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET); 1813 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET); 1814 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET); 1815 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET); 1816 MLX4_PUT(inbox, param->num_sys_eqs, INIT_HCA_NUM_SYS_EQS_OFFSET); 1817 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET); 1818 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET); 1819 1820 /* steering attributes */ 1821 if (dev->caps.steering_mode == 1822 MLX4_STEERING_MODE_DEVICE_MANAGED) { 1823 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= 1824 cpu_to_be32(1 << 1825 INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN); 1826 1827 MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET); 1828 MLX4_PUT(inbox, param->log_mc_entry_sz, 1829 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET); 1830 MLX4_PUT(inbox, param->log_mc_table_sz, 1831 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET); 1832 /* Enable Ethernet flow steering 1833 * with udp unicast and tcp unicast 1834 */ 1835 if (dev->caps.dmfs_high_steer_mode != 1836 MLX4_STEERING_DMFS_A0_STATIC) 1837 MLX4_PUT(inbox, 1838 (u8)(MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN), 1839 INIT_HCA_FS_ETH_BITS_OFFSET); 1840 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR, 1841 INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET); 1842 /* Enable IPoIB flow steering 1843 * with udp unicast and tcp unicast 1844 */ 1845 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN), 1846 INIT_HCA_FS_IB_BITS_OFFSET); 1847 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR, 1848 INIT_HCA_FS_IB_NUM_ADDRS_OFFSET); 1849 1850 if (dev->caps.dmfs_high_steer_mode != 1851 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) 1852 MLX4_PUT(inbox, 1853 ((u8)(a0_dmfs_hw_steering[dev->caps.dmfs_high_steer_mode] 1854 << 6)), 1855 INIT_HCA_FS_A0_OFFSET); 1856 } else { 1857 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET); 1858 MLX4_PUT(inbox, param->log_mc_entry_sz, 1859 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); 1860 MLX4_PUT(inbox, param->log_mc_hash_sz, 1861 INIT_HCA_LOG_MC_HASH_SZ_OFFSET); 1862 MLX4_PUT(inbox, param->log_mc_table_sz, 1863 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); 1864 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0) 1865 MLX4_PUT(inbox, (u8) (1 << 3), 1866 INIT_HCA_UC_STEERING_OFFSET); 1867 } 1868 1869 /* TPT attributes */ 1870 1871 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET); 1872 MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET); 1873 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET); 1874 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET); 1875 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET); 1876 1877 /* UAR attributes */ 1878 1879 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET); 1880 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET); 1881 1882 /* set parser VXLAN attributes */ 1883 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) { 1884 u8 parser_params = 0; 1885 MLX4_PUT(inbox, parser_params, INIT_HCA_VXLAN_OFFSET); 1886 } 1887 1888 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 1889 MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE); 1890 1891 if (err) 1892 mlx4_err(dev, "INIT_HCA returns %d\n", err); 1893 1894 mlx4_free_cmd_mailbox(dev, mailbox); 1895 return err; 1896 } 1897 1898 int mlx4_QUERY_HCA(struct mlx4_dev *dev, 1899 struct mlx4_init_hca_param *param) 1900 { 1901 struct mlx4_cmd_mailbox *mailbox; 1902 __be32 *outbox; 1903 u32 dword_field; 1904 int err; 1905 u8 byte_field; 1906 static const u8 a0_dmfs_query_hw_steering[] = { 1907 [0] = MLX4_STEERING_DMFS_A0_DEFAULT, 1908 [1] = MLX4_STEERING_DMFS_A0_DYNAMIC, 1909 [2] = MLX4_STEERING_DMFS_A0_STATIC, 1910 [3] = MLX4_STEERING_DMFS_A0_DISABLE 1911 }; 1912 1913 #define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04 1914 #define QUERY_HCA_CORE_CLOCK_OFFSET 0x0c 1915 1916 mailbox = mlx4_alloc_cmd_mailbox(dev); 1917 if (IS_ERR(mailbox)) 1918 return PTR_ERR(mailbox); 1919 outbox = mailbox->buf; 1920 1921 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, 1922 MLX4_CMD_QUERY_HCA, 1923 MLX4_CMD_TIME_CLASS_B, 1924 !mlx4_is_slave(dev)); 1925 if (err) 1926 goto out; 1927 1928 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET); 1929 MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET); 1930 1931 /* QPC/EEC/CQC/EQC/RDMARC attributes */ 1932 1933 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET); 1934 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET); 1935 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET); 1936 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET); 1937 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET); 1938 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET); 1939 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET); 1940 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET); 1941 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET); 1942 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET); 1943 MLX4_GET(param->num_sys_eqs, outbox, INIT_HCA_NUM_SYS_EQS_OFFSET); 1944 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET); 1945 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET); 1946 1947 MLX4_GET(dword_field, outbox, INIT_HCA_FLAGS_OFFSET); 1948 if (dword_field & (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN)) { 1949 param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED; 1950 } else { 1951 MLX4_GET(byte_field, outbox, INIT_HCA_UC_STEERING_OFFSET); 1952 if (byte_field & 0x8) 1953 param->steering_mode = MLX4_STEERING_MODE_B0; 1954 else 1955 param->steering_mode = MLX4_STEERING_MODE_A0; 1956 } 1957 1958 if (dword_field & (1 << 13)) 1959 param->rss_ip_frags = 1; 1960 1961 /* steering attributes */ 1962 if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) { 1963 MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET); 1964 MLX4_GET(param->log_mc_entry_sz, outbox, 1965 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET); 1966 MLX4_GET(param->log_mc_table_sz, outbox, 1967 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET); 1968 MLX4_GET(byte_field, outbox, 1969 INIT_HCA_FS_A0_OFFSET); 1970 param->dmfs_high_steer_mode = 1971 a0_dmfs_query_hw_steering[(byte_field >> 6) & 3]; 1972 } else { 1973 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET); 1974 MLX4_GET(param->log_mc_entry_sz, outbox, 1975 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); 1976 MLX4_GET(param->log_mc_hash_sz, outbox, 1977 INIT_HCA_LOG_MC_HASH_SZ_OFFSET); 1978 MLX4_GET(param->log_mc_table_sz, outbox, 1979 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); 1980 } 1981 1982 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */ 1983 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS); 1984 if (byte_field & 0x20) /* 64-bytes eqe enabled */ 1985 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED; 1986 if (byte_field & 0x40) /* 64-bytes cqe enabled */ 1987 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED; 1988 1989 /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */ 1990 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_STRIDE_OFFSET); 1991 if (byte_field) { 1992 param->dev_cap_enabled |= MLX4_DEV_CAP_EQE_STRIDE_ENABLED; 1993 param->dev_cap_enabled |= MLX4_DEV_CAP_CQE_STRIDE_ENABLED; 1994 param->cqe_size = 1 << ((byte_field & 1995 MLX4_CQE_SIZE_MASK_STRIDE) + 5); 1996 param->eqe_size = 1 << (((byte_field & 1997 MLX4_EQE_SIZE_MASK_STRIDE) >> 4) + 5); 1998 } 1999 2000 /* TPT attributes */ 2001 2002 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET); 2003 MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET); 2004 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET); 2005 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET); 2006 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET); 2007 2008 /* UAR attributes */ 2009 2010 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET); 2011 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET); 2012 2013 /* phv_check enable */ 2014 MLX4_GET(byte_field, outbox, INIT_HCA_CACHELINE_SZ_OFFSET); 2015 if (byte_field & 0x2) 2016 param->phv_check_en = 1; 2017 out: 2018 mlx4_free_cmd_mailbox(dev, mailbox); 2019 2020 return err; 2021 } 2022 2023 static int mlx4_hca_core_clock_update(struct mlx4_dev *dev) 2024 { 2025 struct mlx4_cmd_mailbox *mailbox; 2026 __be32 *outbox; 2027 int err; 2028 2029 mailbox = mlx4_alloc_cmd_mailbox(dev); 2030 if (IS_ERR(mailbox)) { 2031 mlx4_warn(dev, "hca_core_clock mailbox allocation failed\n"); 2032 return PTR_ERR(mailbox); 2033 } 2034 outbox = mailbox->buf; 2035 2036 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, 2037 MLX4_CMD_QUERY_HCA, 2038 MLX4_CMD_TIME_CLASS_B, 2039 !mlx4_is_slave(dev)); 2040 if (err) { 2041 mlx4_warn(dev, "hca_core_clock update failed\n"); 2042 goto out; 2043 } 2044 2045 MLX4_GET(dev->caps.hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET); 2046 2047 out: 2048 mlx4_free_cmd_mailbox(dev, mailbox); 2049 2050 return err; 2051 } 2052 2053 /* for IB-type ports only in SRIOV mode. Checks that both proxy QP0 2054 * and real QP0 are active, so that the paravirtualized QP0 is ready 2055 * to operate */ 2056 static int check_qp0_state(struct mlx4_dev *dev, int function, int port) 2057 { 2058 struct mlx4_priv *priv = mlx4_priv(dev); 2059 /* irrelevant if not infiniband */ 2060 if (priv->mfunc.master.qp0_state[port].proxy_qp0_active && 2061 priv->mfunc.master.qp0_state[port].qp0_active) 2062 return 1; 2063 return 0; 2064 } 2065 2066 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave, 2067 struct mlx4_vhcr *vhcr, 2068 struct mlx4_cmd_mailbox *inbox, 2069 struct mlx4_cmd_mailbox *outbox, 2070 struct mlx4_cmd_info *cmd) 2071 { 2072 struct mlx4_priv *priv = mlx4_priv(dev); 2073 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier); 2074 int err; 2075 2076 if (port < 0) 2077 return -EINVAL; 2078 2079 if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port)) 2080 return 0; 2081 2082 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) { 2083 /* Enable port only if it was previously disabled */ 2084 if (!priv->mfunc.master.init_port_ref[port]) { 2085 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, 2086 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2087 if (err) 2088 return err; 2089 } 2090 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); 2091 } else { 2092 if (slave == mlx4_master_func_num(dev)) { 2093 if (check_qp0_state(dev, slave, port) && 2094 !priv->mfunc.master.qp0_state[port].port_active) { 2095 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, 2096 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2097 if (err) 2098 return err; 2099 priv->mfunc.master.qp0_state[port].port_active = 1; 2100 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); 2101 } 2102 } else 2103 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); 2104 } 2105 ++priv->mfunc.master.init_port_ref[port]; 2106 return 0; 2107 } 2108 2109 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port) 2110 { 2111 struct mlx4_cmd_mailbox *mailbox; 2112 u32 *inbox; 2113 int err; 2114 u32 flags; 2115 u16 field; 2116 2117 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { 2118 #define INIT_PORT_IN_SIZE 256 2119 #define INIT_PORT_FLAGS_OFFSET 0x00 2120 #define INIT_PORT_FLAG_SIG (1 << 18) 2121 #define INIT_PORT_FLAG_NG (1 << 17) 2122 #define INIT_PORT_FLAG_G0 (1 << 16) 2123 #define INIT_PORT_VL_SHIFT 4 2124 #define INIT_PORT_PORT_WIDTH_SHIFT 8 2125 #define INIT_PORT_MTU_OFFSET 0x04 2126 #define INIT_PORT_MAX_GID_OFFSET 0x06 2127 #define INIT_PORT_MAX_PKEY_OFFSET 0x0a 2128 #define INIT_PORT_GUID0_OFFSET 0x10 2129 #define INIT_PORT_NODE_GUID_OFFSET 0x18 2130 #define INIT_PORT_SI_GUID_OFFSET 0x20 2131 2132 mailbox = mlx4_alloc_cmd_mailbox(dev); 2133 if (IS_ERR(mailbox)) 2134 return PTR_ERR(mailbox); 2135 inbox = mailbox->buf; 2136 2137 flags = 0; 2138 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT; 2139 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT; 2140 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET); 2141 2142 field = 128 << dev->caps.ib_mtu_cap[port]; 2143 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET); 2144 field = dev->caps.gid_table_len[port]; 2145 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET); 2146 field = dev->caps.pkey_table_len[port]; 2147 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET); 2148 2149 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT, 2150 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2151 2152 mlx4_free_cmd_mailbox(dev, mailbox); 2153 } else 2154 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, 2155 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 2156 2157 if (!err) 2158 mlx4_hca_core_clock_update(dev); 2159 2160 return err; 2161 } 2162 EXPORT_SYMBOL_GPL(mlx4_INIT_PORT); 2163 2164 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave, 2165 struct mlx4_vhcr *vhcr, 2166 struct mlx4_cmd_mailbox *inbox, 2167 struct mlx4_cmd_mailbox *outbox, 2168 struct mlx4_cmd_info *cmd) 2169 { 2170 struct mlx4_priv *priv = mlx4_priv(dev); 2171 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier); 2172 int err; 2173 2174 if (port < 0) 2175 return -EINVAL; 2176 2177 if (!(priv->mfunc.master.slave_state[slave].init_port_mask & 2178 (1 << port))) 2179 return 0; 2180 2181 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) { 2182 if (priv->mfunc.master.init_port_ref[port] == 1) { 2183 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 2184 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2185 if (err) 2186 return err; 2187 } 2188 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); 2189 } else { 2190 /* infiniband port */ 2191 if (slave == mlx4_master_func_num(dev)) { 2192 if (!priv->mfunc.master.qp0_state[port].qp0_active && 2193 priv->mfunc.master.qp0_state[port].port_active) { 2194 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 2195 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2196 if (err) 2197 return err; 2198 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); 2199 priv->mfunc.master.qp0_state[port].port_active = 0; 2200 } 2201 } else 2202 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); 2203 } 2204 --priv->mfunc.master.init_port_ref[port]; 2205 return 0; 2206 } 2207 2208 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port) 2209 { 2210 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 2211 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 2212 } 2213 EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT); 2214 2215 int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic) 2216 { 2217 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 2218 MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE); 2219 } 2220 2221 struct mlx4_config_dev { 2222 __be32 update_flags; 2223 __be32 rsvd1[3]; 2224 __be16 vxlan_udp_dport; 2225 __be16 rsvd2; 2226 __be32 rsvd3; 2227 __be32 roce_flags; 2228 __be32 rsvd4[25]; 2229 __be16 rsvd5; 2230 u8 rsvd6; 2231 u8 rx_checksum_val; 2232 }; 2233 2234 #define MLX4_VXLAN_UDP_DPORT (1 << 0) 2235 #define MLX4_DISABLE_RX_PORT BIT(18) 2236 2237 static int mlx4_CONFIG_DEV_set(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev) 2238 { 2239 int err; 2240 struct mlx4_cmd_mailbox *mailbox; 2241 2242 mailbox = mlx4_alloc_cmd_mailbox(dev); 2243 if (IS_ERR(mailbox)) 2244 return PTR_ERR(mailbox); 2245 2246 memcpy(mailbox->buf, config_dev, sizeof(*config_dev)); 2247 2248 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_CONFIG_DEV, 2249 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 2250 2251 mlx4_free_cmd_mailbox(dev, mailbox); 2252 return err; 2253 } 2254 2255 static int mlx4_CONFIG_DEV_get(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev) 2256 { 2257 int err; 2258 struct mlx4_cmd_mailbox *mailbox; 2259 2260 mailbox = mlx4_alloc_cmd_mailbox(dev); 2261 if (IS_ERR(mailbox)) 2262 return PTR_ERR(mailbox); 2263 2264 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 1, MLX4_CMD_CONFIG_DEV, 2265 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2266 2267 if (!err) 2268 memcpy(config_dev, mailbox->buf, sizeof(*config_dev)); 2269 2270 mlx4_free_cmd_mailbox(dev, mailbox); 2271 return err; 2272 } 2273 2274 /* Conversion between the HW values and the actual functionality. 2275 * The value represented by the array index, 2276 * and the functionality determined by the flags. 2277 */ 2278 static const u8 config_dev_csum_flags[] = { 2279 [0] = 0, 2280 [1] = MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP, 2281 [2] = MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP | 2282 MLX4_RX_CSUM_MODE_L4, 2283 [3] = MLX4_RX_CSUM_MODE_L4 | 2284 MLX4_RX_CSUM_MODE_IP_OK_IP_NON_TCP_UDP | 2285 MLX4_RX_CSUM_MODE_MULTI_VLAN 2286 }; 2287 2288 int mlx4_config_dev_retrieval(struct mlx4_dev *dev, 2289 struct mlx4_config_dev_params *params) 2290 { 2291 struct mlx4_config_dev config_dev = {0}; 2292 int err; 2293 u8 csum_mask; 2294 2295 #define CONFIG_DEV_RX_CSUM_MODE_MASK 0x7 2296 #define CONFIG_DEV_RX_CSUM_MODE_PORT1_BIT_OFFSET 0 2297 #define CONFIG_DEV_RX_CSUM_MODE_PORT2_BIT_OFFSET 4 2298 2299 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CONFIG_DEV)) 2300 return -ENOTSUPP; 2301 2302 err = mlx4_CONFIG_DEV_get(dev, &config_dev); 2303 if (err) 2304 return err; 2305 2306 csum_mask = (config_dev.rx_checksum_val >> CONFIG_DEV_RX_CSUM_MODE_PORT1_BIT_OFFSET) & 2307 CONFIG_DEV_RX_CSUM_MODE_MASK; 2308 2309 if (csum_mask >= sizeof(config_dev_csum_flags)/sizeof(config_dev_csum_flags[0])) 2310 return -EINVAL; 2311 params->rx_csum_flags_port_1 = config_dev_csum_flags[csum_mask]; 2312 2313 csum_mask = (config_dev.rx_checksum_val >> CONFIG_DEV_RX_CSUM_MODE_PORT2_BIT_OFFSET) & 2314 CONFIG_DEV_RX_CSUM_MODE_MASK; 2315 2316 if (csum_mask >= sizeof(config_dev_csum_flags)/sizeof(config_dev_csum_flags[0])) 2317 return -EINVAL; 2318 params->rx_csum_flags_port_2 = config_dev_csum_flags[csum_mask]; 2319 2320 params->vxlan_udp_dport = be16_to_cpu(config_dev.vxlan_udp_dport); 2321 2322 return 0; 2323 } 2324 EXPORT_SYMBOL_GPL(mlx4_config_dev_retrieval); 2325 2326 int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port) 2327 { 2328 struct mlx4_config_dev config_dev; 2329 2330 memset(&config_dev, 0, sizeof(config_dev)); 2331 config_dev.update_flags = cpu_to_be32(MLX4_VXLAN_UDP_DPORT); 2332 config_dev.vxlan_udp_dport = udp_port; 2333 2334 return mlx4_CONFIG_DEV_set(dev, &config_dev); 2335 } 2336 EXPORT_SYMBOL_GPL(mlx4_config_vxlan_port); 2337 2338 #define CONFIG_DISABLE_RX_PORT BIT(15) 2339 int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis) 2340 { 2341 struct mlx4_config_dev config_dev; 2342 2343 memset(&config_dev, 0, sizeof(config_dev)); 2344 config_dev.update_flags = cpu_to_be32(MLX4_DISABLE_RX_PORT); 2345 if (dis) 2346 config_dev.roce_flags = 2347 cpu_to_be32(CONFIG_DISABLE_RX_PORT); 2348 2349 return mlx4_CONFIG_DEV_set(dev, &config_dev); 2350 } 2351 2352 int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2) 2353 { 2354 struct mlx4_cmd_mailbox *mailbox; 2355 struct { 2356 __be32 v_port1; 2357 __be32 v_port2; 2358 } *v2p; 2359 int err; 2360 2361 mailbox = mlx4_alloc_cmd_mailbox(dev); 2362 if (IS_ERR(mailbox)) 2363 return -ENOMEM; 2364 2365 v2p = mailbox->buf; 2366 v2p->v_port1 = cpu_to_be32(port1); 2367 v2p->v_port2 = cpu_to_be32(port2); 2368 2369 err = mlx4_cmd(dev, mailbox->dma, 0, 2370 MLX4_SET_PORT_VIRT2PHY, MLX4_CMD_VIRT_PORT_MAP, 2371 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 2372 2373 mlx4_free_cmd_mailbox(dev, mailbox); 2374 return err; 2375 } 2376 2377 2378 int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages) 2379 { 2380 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0, 2381 MLX4_CMD_SET_ICM_SIZE, 2382 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2383 if (ret) 2384 return ret; 2385 2386 /* 2387 * Round up number of system pages needed in case 2388 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. 2389 */ 2390 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> 2391 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); 2392 2393 return 0; 2394 } 2395 2396 int mlx4_NOP(struct mlx4_dev *dev) 2397 { 2398 /* Input modifier of 0x1f means "finish as soon as possible." */ 2399 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, MLX4_CMD_TIME_CLASS_A, 2400 MLX4_CMD_NATIVE); 2401 } 2402 2403 int mlx4_get_phys_port_id(struct mlx4_dev *dev) 2404 { 2405 u8 port; 2406 u32 *outbox; 2407 struct mlx4_cmd_mailbox *mailbox; 2408 u32 in_mod; 2409 u32 guid_hi, guid_lo; 2410 int err, ret = 0; 2411 #define MOD_STAT_CFG_PORT_OFFSET 8 2412 #define MOD_STAT_CFG_GUID_H 0X14 2413 #define MOD_STAT_CFG_GUID_L 0X1c 2414 2415 mailbox = mlx4_alloc_cmd_mailbox(dev); 2416 if (IS_ERR(mailbox)) 2417 return PTR_ERR(mailbox); 2418 outbox = mailbox->buf; 2419 2420 for (port = 1; port <= dev->caps.num_ports; port++) { 2421 in_mod = port << MOD_STAT_CFG_PORT_OFFSET; 2422 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_mod, 0x2, 2423 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A, 2424 MLX4_CMD_NATIVE); 2425 if (err) { 2426 mlx4_err(dev, "Fail to get port %d uplink guid\n", 2427 port); 2428 ret = err; 2429 } else { 2430 MLX4_GET(guid_hi, outbox, MOD_STAT_CFG_GUID_H); 2431 MLX4_GET(guid_lo, outbox, MOD_STAT_CFG_GUID_L); 2432 dev->caps.phys_port_id[port] = (u64)guid_lo | 2433 (u64)guid_hi << 32; 2434 } 2435 } 2436 mlx4_free_cmd_mailbox(dev, mailbox); 2437 return ret; 2438 } 2439 2440 #define MLX4_WOL_SETUP_MODE (5 << 28) 2441 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port) 2442 { 2443 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8; 2444 2445 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3, 2446 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A, 2447 MLX4_CMD_NATIVE); 2448 } 2449 EXPORT_SYMBOL_GPL(mlx4_wol_read); 2450 2451 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port) 2452 { 2453 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8; 2454 2455 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG, 2456 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2457 } 2458 EXPORT_SYMBOL_GPL(mlx4_wol_write); 2459 2460 enum { 2461 ADD_TO_MCG = 0x26, 2462 }; 2463 2464 2465 void mlx4_opreq_action(struct work_struct *work) 2466 { 2467 struct mlx4_priv *priv = container_of(work, struct mlx4_priv, 2468 opreq_task); 2469 struct mlx4_dev *dev = &priv->dev; 2470 int num_tasks = atomic_read(&priv->opreq_count); 2471 struct mlx4_cmd_mailbox *mailbox; 2472 struct mlx4_mgm *mgm; 2473 u32 *outbox; 2474 u32 modifier; 2475 u16 token; 2476 u16 type; 2477 int err; 2478 u32 num_qps; 2479 struct mlx4_qp qp; 2480 int i; 2481 u8 rem_mcg; 2482 u8 prot; 2483 2484 #define GET_OP_REQ_MODIFIER_OFFSET 0x08 2485 #define GET_OP_REQ_TOKEN_OFFSET 0x14 2486 #define GET_OP_REQ_TYPE_OFFSET 0x1a 2487 #define GET_OP_REQ_DATA_OFFSET 0x20 2488 2489 mailbox = mlx4_alloc_cmd_mailbox(dev); 2490 if (IS_ERR(mailbox)) { 2491 mlx4_err(dev, "Failed to allocate mailbox for GET_OP_REQ\n"); 2492 return; 2493 } 2494 outbox = mailbox->buf; 2495 2496 while (num_tasks) { 2497 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, 2498 MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A, 2499 MLX4_CMD_NATIVE); 2500 if (err) { 2501 mlx4_err(dev, "Failed to retrieve required operation: %d\n", 2502 err); 2503 return; 2504 } 2505 MLX4_GET(modifier, outbox, GET_OP_REQ_MODIFIER_OFFSET); 2506 MLX4_GET(token, outbox, GET_OP_REQ_TOKEN_OFFSET); 2507 MLX4_GET(type, outbox, GET_OP_REQ_TYPE_OFFSET); 2508 type &= 0xfff; 2509 2510 switch (type) { 2511 case ADD_TO_MCG: 2512 if (dev->caps.steering_mode == 2513 MLX4_STEERING_MODE_DEVICE_MANAGED) { 2514 mlx4_warn(dev, "ADD MCG operation is not supported in DEVICE_MANAGED steering mode\n"); 2515 err = EPERM; 2516 break; 2517 } 2518 mgm = (struct mlx4_mgm *)((u8 *)(outbox) + 2519 GET_OP_REQ_DATA_OFFSET); 2520 num_qps = be32_to_cpu(mgm->members_count) & 2521 MGM_QPN_MASK; 2522 rem_mcg = ((u8 *)(&mgm->members_count))[0] & 1; 2523 prot = ((u8 *)(&mgm->members_count))[0] >> 6; 2524 2525 for (i = 0; i < num_qps; i++) { 2526 qp.qpn = be32_to_cpu(mgm->qp[i]); 2527 if (rem_mcg) 2528 err = mlx4_multicast_detach(dev, &qp, 2529 mgm->gid, 2530 prot, 0); 2531 else 2532 err = mlx4_multicast_attach(dev, &qp, 2533 mgm->gid, 2534 mgm->gid[5] 2535 , 0, prot, 2536 NULL); 2537 if (err) 2538 break; 2539 } 2540 break; 2541 default: 2542 mlx4_warn(dev, "Bad type for required operation\n"); 2543 err = EINVAL; 2544 break; 2545 } 2546 err = mlx4_cmd(dev, 0, ((u32) err | 2547 (__force u32)cpu_to_be32(token) << 16), 2548 1, MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A, 2549 MLX4_CMD_NATIVE); 2550 if (err) { 2551 mlx4_err(dev, "Failed to acknowledge required request: %d\n", 2552 err); 2553 goto out; 2554 } 2555 memset(outbox, 0, 0xffc); 2556 num_tasks = atomic_dec_return(&priv->opreq_count); 2557 } 2558 2559 out: 2560 mlx4_free_cmd_mailbox(dev, mailbox); 2561 } 2562 2563 static int mlx4_check_smp_firewall_active(struct mlx4_dev *dev, 2564 struct mlx4_cmd_mailbox *mailbox) 2565 { 2566 #define MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET 0x10 2567 #define MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET 0x20 2568 #define MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET 0x40 2569 #define MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET 0x70 2570 2571 u32 set_attr_mask, getresp_attr_mask; 2572 u32 trap_attr_mask, traprepress_attr_mask; 2573 2574 MLX4_GET(set_attr_mask, mailbox->buf, 2575 MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET); 2576 mlx4_dbg(dev, "SMP firewall set_attribute_mask = 0x%x\n", 2577 set_attr_mask); 2578 2579 MLX4_GET(getresp_attr_mask, mailbox->buf, 2580 MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET); 2581 mlx4_dbg(dev, "SMP firewall getresp_attribute_mask = 0x%x\n", 2582 getresp_attr_mask); 2583 2584 MLX4_GET(trap_attr_mask, mailbox->buf, 2585 MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET); 2586 mlx4_dbg(dev, "SMP firewall trap_attribute_mask = 0x%x\n", 2587 trap_attr_mask); 2588 2589 MLX4_GET(traprepress_attr_mask, mailbox->buf, 2590 MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET); 2591 mlx4_dbg(dev, "SMP firewall traprepress_attribute_mask = 0x%x\n", 2592 traprepress_attr_mask); 2593 2594 if (set_attr_mask && getresp_attr_mask && trap_attr_mask && 2595 traprepress_attr_mask) 2596 return 1; 2597 2598 return 0; 2599 } 2600 2601 int mlx4_config_mad_demux(struct mlx4_dev *dev) 2602 { 2603 struct mlx4_cmd_mailbox *mailbox; 2604 int secure_host_active; 2605 int err; 2606 2607 /* Check if mad_demux is supported */ 2608 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_MAD_DEMUX)) 2609 return 0; 2610 2611 mailbox = mlx4_alloc_cmd_mailbox(dev); 2612 if (IS_ERR(mailbox)) { 2613 mlx4_warn(dev, "Failed to allocate mailbox for cmd MAD_DEMUX"); 2614 return -ENOMEM; 2615 } 2616 2617 /* Query mad_demux to find out which MADs are handled by internal sma */ 2618 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0x01 /* subn mgmt class */, 2619 MLX4_CMD_MAD_DEMUX_QUERY_RESTR, MLX4_CMD_MAD_DEMUX, 2620 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 2621 if (err) { 2622 mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: query restrictions failed (%d)\n", 2623 err); 2624 goto out; 2625 } 2626 2627 secure_host_active = mlx4_check_smp_firewall_active(dev, mailbox); 2628 2629 /* Config mad_demux to handle all MADs returned by the query above */ 2630 err = mlx4_cmd(dev, mailbox->dma, 0x01 /* subn mgmt class */, 2631 MLX4_CMD_MAD_DEMUX_CONFIG, MLX4_CMD_MAD_DEMUX, 2632 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 2633 if (err) { 2634 mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: configure failed (%d)\n", err); 2635 goto out; 2636 } 2637 2638 if (secure_host_active) 2639 mlx4_warn(dev, "HCA operating in secure-host mode. SMP firewall activated.\n"); 2640 out: 2641 mlx4_free_cmd_mailbox(dev, mailbox); 2642 return err; 2643 } 2644 2645 /* Access Reg commands */ 2646 enum mlx4_access_reg_masks { 2647 MLX4_ACCESS_REG_STATUS_MASK = 0x7f, 2648 MLX4_ACCESS_REG_METHOD_MASK = 0x7f, 2649 MLX4_ACCESS_REG_LEN_MASK = 0x7ff 2650 }; 2651 2652 struct mlx4_access_reg { 2653 __be16 constant1; 2654 u8 status; 2655 u8 resrvd1; 2656 __be16 reg_id; 2657 u8 method; 2658 u8 constant2; 2659 __be32 resrvd2[2]; 2660 __be16 len_const; 2661 __be16 resrvd3; 2662 #define MLX4_ACCESS_REG_HEADER_SIZE (20) 2663 u8 reg_data[MLX4_MAILBOX_SIZE-MLX4_ACCESS_REG_HEADER_SIZE]; 2664 } __attribute__((__packed__)); 2665 2666 /** 2667 * mlx4_ACCESS_REG - Generic access reg command. 2668 * @dev: mlx4_dev. 2669 * @reg_id: register ID to access. 2670 * @method: Access method Read/Write. 2671 * @reg_len: register length to Read/Write in bytes. 2672 * @reg_data: reg_data pointer to Read/Write From/To. 2673 * 2674 * Access ConnectX registers FW command. 2675 * Returns 0 on success and copies outbox mlx4_access_reg data 2676 * field into reg_data or a negative error code. 2677 */ 2678 static int mlx4_ACCESS_REG(struct mlx4_dev *dev, u16 reg_id, 2679 enum mlx4_access_reg_method method, 2680 u16 reg_len, void *reg_data) 2681 { 2682 struct mlx4_cmd_mailbox *inbox, *outbox; 2683 struct mlx4_access_reg *inbuf, *outbuf; 2684 int err; 2685 2686 inbox = mlx4_alloc_cmd_mailbox(dev); 2687 if (IS_ERR(inbox)) 2688 return PTR_ERR(inbox); 2689 2690 outbox = mlx4_alloc_cmd_mailbox(dev); 2691 if (IS_ERR(outbox)) { 2692 mlx4_free_cmd_mailbox(dev, inbox); 2693 return PTR_ERR(outbox); 2694 } 2695 2696 inbuf = inbox->buf; 2697 outbuf = outbox->buf; 2698 2699 inbuf->constant1 = cpu_to_be16(0x1<<11 | 0x4); 2700 inbuf->constant2 = 0x1; 2701 inbuf->reg_id = cpu_to_be16(reg_id); 2702 inbuf->method = method & MLX4_ACCESS_REG_METHOD_MASK; 2703 2704 reg_len = min(reg_len, (u16)(sizeof(inbuf->reg_data))); 2705 inbuf->len_const = 2706 cpu_to_be16(((reg_len/4 + 1) & MLX4_ACCESS_REG_LEN_MASK) | 2707 ((0x3) << 12)); 2708 2709 memcpy(inbuf->reg_data, reg_data, reg_len); 2710 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, 0, 0, 2711 MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C, 2712 MLX4_CMD_WRAPPED); 2713 if (err) 2714 goto out; 2715 2716 if (outbuf->status & MLX4_ACCESS_REG_STATUS_MASK) { 2717 err = outbuf->status & MLX4_ACCESS_REG_STATUS_MASK; 2718 mlx4_err(dev, 2719 "MLX4_CMD_ACCESS_REG(%x) returned REG status (%x)\n", 2720 reg_id, err); 2721 goto out; 2722 } 2723 2724 memcpy(reg_data, outbuf->reg_data, reg_len); 2725 out: 2726 mlx4_free_cmd_mailbox(dev, inbox); 2727 mlx4_free_cmd_mailbox(dev, outbox); 2728 return err; 2729 } 2730 2731 /* ConnectX registers IDs */ 2732 enum mlx4_reg_id { 2733 MLX4_REG_ID_PTYS = 0x5004, 2734 }; 2735 2736 /** 2737 * mlx4_ACCESS_PTYS_REG - Access PTYs (Port Type and Speed) 2738 * register 2739 * @dev: mlx4_dev. 2740 * @method: Access method Read/Write. 2741 * @ptys_reg: PTYS register data pointer. 2742 * 2743 * Access ConnectX PTYS register, to Read/Write Port Type/Speed 2744 * configuration 2745 * Returns 0 on success or a negative error code. 2746 */ 2747 int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev, 2748 enum mlx4_access_reg_method method, 2749 struct mlx4_ptys_reg *ptys_reg) 2750 { 2751 return mlx4_ACCESS_REG(dev, MLX4_REG_ID_PTYS, 2752 method, sizeof(*ptys_reg), ptys_reg); 2753 } 2754 EXPORT_SYMBOL_GPL(mlx4_ACCESS_PTYS_REG); 2755 2756 int mlx4_ACCESS_REG_wrapper(struct mlx4_dev *dev, int slave, 2757 struct mlx4_vhcr *vhcr, 2758 struct mlx4_cmd_mailbox *inbox, 2759 struct mlx4_cmd_mailbox *outbox, 2760 struct mlx4_cmd_info *cmd) 2761 { 2762 struct mlx4_access_reg *inbuf = inbox->buf; 2763 u8 method = inbuf->method & MLX4_ACCESS_REG_METHOD_MASK; 2764 u16 reg_id = be16_to_cpu(inbuf->reg_id); 2765 2766 if (slave != mlx4_master_func_num(dev) && 2767 method == MLX4_ACCESS_REG_WRITE) 2768 return -EPERM; 2769 2770 if (reg_id == MLX4_REG_ID_PTYS) { 2771 struct mlx4_ptys_reg *ptys_reg = 2772 (struct mlx4_ptys_reg *)inbuf->reg_data; 2773 2774 ptys_reg->local_port = 2775 mlx4_slave_convert_port(dev, slave, 2776 ptys_reg->local_port); 2777 } 2778 2779 return mlx4_cmd_box(dev, inbox->dma, outbox->dma, vhcr->in_modifier, 2780 0, MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C, 2781 MLX4_CMD_NATIVE); 2782 } 2783 2784 static int mlx4_SET_PORT_phv_bit(struct mlx4_dev *dev, u8 port, u8 phv_bit) 2785 { 2786 #define SET_PORT_GEN_PHV_VALID 0x10 2787 #define SET_PORT_GEN_PHV_EN 0x80 2788 2789 struct mlx4_cmd_mailbox *mailbox; 2790 struct mlx4_set_port_general_context *context; 2791 u32 in_mod; 2792 int err; 2793 2794 mailbox = mlx4_alloc_cmd_mailbox(dev); 2795 if (IS_ERR(mailbox)) 2796 return PTR_ERR(mailbox); 2797 context = mailbox->buf; 2798 2799 context->v_ignore_fcs |= SET_PORT_GEN_PHV_VALID; 2800 if (phv_bit) 2801 context->phv_en |= SET_PORT_GEN_PHV_EN; 2802 2803 in_mod = MLX4_SET_PORT_GENERAL << 8 | port; 2804 err = mlx4_cmd(dev, mailbox->dma, in_mod, MLX4_SET_PORT_ETH_OPCODE, 2805 MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, 2806 MLX4_CMD_NATIVE); 2807 2808 mlx4_free_cmd_mailbox(dev, mailbox); 2809 return err; 2810 } 2811 2812 int get_phv_bit(struct mlx4_dev *dev, u8 port, int *phv) 2813 { 2814 int err; 2815 struct mlx4_func_cap func_cap; 2816 2817 memset(&func_cap, 0, sizeof(func_cap)); 2818 err = mlx4_QUERY_FUNC_CAP(dev, port, &func_cap); 2819 if (!err) 2820 *phv = func_cap.flags & QUERY_FUNC_CAP_PHV_BIT; 2821 return err; 2822 } 2823 EXPORT_SYMBOL(get_phv_bit); 2824 2825 int set_phv_bit(struct mlx4_dev *dev, u8 port, int new_val) 2826 { 2827 int ret; 2828 2829 if (mlx4_is_slave(dev)) 2830 return -EPERM; 2831 2832 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN && 2833 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN)) { 2834 ret = mlx4_SET_PORT_phv_bit(dev, port, new_val); 2835 if (!ret) 2836 dev->caps.phv_bit[port] = new_val; 2837 return ret; 2838 } 2839 2840 return -EOPNOTSUPP; 2841 } 2842 EXPORT_SYMBOL(set_phv_bit); 2843