1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #include <linux/etherdevice.h> 36 #include <linux/mlx4/cmd.h> 37 #include <linux/module.h> 38 #include <linux/cache.h> 39 40 #include "fw.h" 41 #include "icm.h" 42 43 enum { 44 MLX4_COMMAND_INTERFACE_MIN_REV = 2, 45 MLX4_COMMAND_INTERFACE_MAX_REV = 3, 46 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3, 47 }; 48 49 extern void __buggy_use_of_MLX4_GET(void); 50 extern void __buggy_use_of_MLX4_PUT(void); 51 52 static bool enable_qos; 53 module_param(enable_qos, bool, 0444); 54 MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)"); 55 56 #define MLX4_GET(dest, source, offset) \ 57 do { \ 58 void *__p = (char *) (source) + (offset); \ 59 switch (sizeof (dest)) { \ 60 case 1: (dest) = *(u8 *) __p; break; \ 61 case 2: (dest) = be16_to_cpup(__p); break; \ 62 case 4: (dest) = be32_to_cpup(__p); break; \ 63 case 8: (dest) = be64_to_cpup(__p); break; \ 64 default: __buggy_use_of_MLX4_GET(); \ 65 } \ 66 } while (0) 67 68 #define MLX4_PUT(dest, source, offset) \ 69 do { \ 70 void *__d = ((char *) (dest) + (offset)); \ 71 switch (sizeof(source)) { \ 72 case 1: *(u8 *) __d = (source); break; \ 73 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \ 74 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \ 75 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \ 76 default: __buggy_use_of_MLX4_PUT(); \ 77 } \ 78 } while (0) 79 80 static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags) 81 { 82 static const char *fname[] = { 83 [ 0] = "RC transport", 84 [ 1] = "UC transport", 85 [ 2] = "UD transport", 86 [ 3] = "XRC transport", 87 [ 4] = "reliable multicast", 88 [ 5] = "FCoIB support", 89 [ 6] = "SRQ support", 90 [ 7] = "IPoIB checksum offload", 91 [ 8] = "P_Key violation counter", 92 [ 9] = "Q_Key violation counter", 93 [10] = "VMM", 94 [12] = "DPDP", 95 [15] = "Big LSO headers", 96 [16] = "MW support", 97 [17] = "APM support", 98 [18] = "Atomic ops support", 99 [19] = "Raw multicast support", 100 [20] = "Address vector port checking support", 101 [21] = "UD multicast support", 102 [24] = "Demand paging support", 103 [25] = "Router support", 104 [30] = "IBoE support", 105 [32] = "Unicast loopback support", 106 [34] = "FCS header control", 107 [38] = "Wake On LAN support", 108 [40] = "UDP RSS support", 109 [41] = "Unicast VEP steering support", 110 [42] = "Multicast VEP steering support", 111 [48] = "Counters support", 112 }; 113 int i; 114 115 mlx4_dbg(dev, "DEV_CAP flags:\n"); 116 for (i = 0; i < ARRAY_SIZE(fname); ++i) 117 if (fname[i] && (flags & (1LL << i))) 118 mlx4_dbg(dev, " %s\n", fname[i]); 119 } 120 121 int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg) 122 { 123 struct mlx4_cmd_mailbox *mailbox; 124 u32 *inbox; 125 int err = 0; 126 127 #define MOD_STAT_CFG_IN_SIZE 0x100 128 129 #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002 130 #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003 131 132 mailbox = mlx4_alloc_cmd_mailbox(dev); 133 if (IS_ERR(mailbox)) 134 return PTR_ERR(mailbox); 135 inbox = mailbox->buf; 136 137 memset(inbox, 0, MOD_STAT_CFG_IN_SIZE); 138 139 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET); 140 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET); 141 142 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG, 143 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 144 145 mlx4_free_cmd_mailbox(dev, mailbox); 146 return err; 147 } 148 149 int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave, 150 struct mlx4_vhcr *vhcr, 151 struct mlx4_cmd_mailbox *inbox, 152 struct mlx4_cmd_mailbox *outbox, 153 struct mlx4_cmd_info *cmd) 154 { 155 u8 field; 156 u32 size; 157 int err = 0; 158 159 #define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0 160 #define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1 161 #define QUERY_FUNC_CAP_FUNCTION_OFFSET 0x3 162 #define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4 163 #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x10 164 #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x14 165 #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x18 166 #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x20 167 #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x24 168 #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x28 169 #define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c 170 #define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0X30 171 172 #define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3 173 #define QUERY_FUNC_CAP_ETH_PROPS_OFFSET 0xc 174 175 if (vhcr->op_modifier == 1) { 176 field = vhcr->in_modifier; 177 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); 178 179 field = 0; /* ensure fvl bit is not set */ 180 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_ETH_PROPS_OFFSET); 181 } else if (vhcr->op_modifier == 0) { 182 field = 1 << 7; /* enable only ethernet interface */ 183 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET); 184 185 field = slave; 186 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FUNCTION_OFFSET); 187 188 field = dev->caps.num_ports; 189 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); 190 191 size = 0; /* no PF behavious is set for now */ 192 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET); 193 194 size = dev->caps.num_qps; 195 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET); 196 197 size = dev->caps.num_srqs; 198 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET); 199 200 size = dev->caps.num_cqs; 201 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET); 202 203 size = dev->caps.num_eqs; 204 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET); 205 206 size = dev->caps.reserved_eqs; 207 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); 208 209 size = dev->caps.num_mpts; 210 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET); 211 212 size = dev->caps.num_mtts; 213 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET); 214 215 size = dev->caps.num_mgms + dev->caps.num_amgms; 216 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET); 217 218 } else 219 err = -EINVAL; 220 221 return err; 222 } 223 224 int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, struct mlx4_func_cap *func_cap) 225 { 226 struct mlx4_cmd_mailbox *mailbox; 227 u32 *outbox; 228 u8 field; 229 u32 size; 230 int i; 231 int err = 0; 232 233 234 mailbox = mlx4_alloc_cmd_mailbox(dev); 235 if (IS_ERR(mailbox)) 236 return PTR_ERR(mailbox); 237 238 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FUNC_CAP, 239 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 240 if (err) 241 goto out; 242 243 outbox = mailbox->buf; 244 245 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET); 246 if (!(field & (1 << 7))) { 247 mlx4_err(dev, "The host doesn't support eth interface\n"); 248 err = -EPROTONOSUPPORT; 249 goto out; 250 } 251 252 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FUNCTION_OFFSET); 253 func_cap->function = field; 254 255 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); 256 func_cap->num_ports = field; 257 258 MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET); 259 func_cap->pf_context_behaviour = size; 260 261 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET); 262 func_cap->qp_quota = size & 0xFFFFFF; 263 264 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET); 265 func_cap->srq_quota = size & 0xFFFFFF; 266 267 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET); 268 func_cap->cq_quota = size & 0xFFFFFF; 269 270 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET); 271 func_cap->max_eq = size & 0xFFFFFF; 272 273 MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); 274 func_cap->reserved_eq = size & 0xFFFFFF; 275 276 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET); 277 func_cap->mpt_quota = size & 0xFFFFFF; 278 279 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET); 280 func_cap->mtt_quota = size & 0xFFFFFF; 281 282 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET); 283 func_cap->mcg_quota = size & 0xFFFFFF; 284 285 for (i = 1; i <= func_cap->num_ports; ++i) { 286 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 1, 287 MLX4_CMD_QUERY_FUNC_CAP, 288 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 289 if (err) 290 goto out; 291 292 MLX4_GET(field, outbox, QUERY_FUNC_CAP_ETH_PROPS_OFFSET); 293 if (field & (1 << 7)) { 294 mlx4_err(dev, "VLAN is enforced on this port\n"); 295 err = -EPROTONOSUPPORT; 296 goto out; 297 } 298 299 if (field & (1 << 6)) { 300 mlx4_err(dev, "Force mac is enabled on this port\n"); 301 err = -EPROTONOSUPPORT; 302 goto out; 303 } 304 305 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); 306 func_cap->physical_port[i] = field; 307 } 308 309 /* All other resources are allocated by the master, but we still report 310 * 'num' and 'reserved' capabilities as follows: 311 * - num remains the maximum resource index 312 * - 'num - reserved' is the total available objects of a resource, but 313 * resource indices may be less than 'reserved' 314 * TODO: set per-resource quotas */ 315 316 out: 317 mlx4_free_cmd_mailbox(dev, mailbox); 318 319 return err; 320 } 321 322 int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 323 { 324 struct mlx4_cmd_mailbox *mailbox; 325 u32 *outbox; 326 u8 field; 327 u32 field32, flags, ext_flags; 328 u16 size; 329 u16 stat_rate; 330 int err; 331 int i; 332 333 #define QUERY_DEV_CAP_OUT_SIZE 0x100 334 #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10 335 #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11 336 #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12 337 #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13 338 #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14 339 #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15 340 #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16 341 #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17 342 #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19 343 #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a 344 #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b 345 #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d 346 #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e 347 #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f 348 #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20 349 #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21 350 #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22 351 #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23 352 #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27 353 #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29 354 #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b 355 #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d 356 #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f 357 #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33 358 #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35 359 #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36 360 #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37 361 #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38 362 #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b 363 #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c 364 #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f 365 #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40 366 #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44 367 #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48 368 #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49 369 #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b 370 #define QUERY_DEV_CAP_BF_OFFSET 0x4c 371 #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d 372 #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e 373 #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f 374 #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51 375 #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52 376 #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55 377 #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56 378 #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61 379 #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62 380 #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63 381 #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64 382 #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65 383 #define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66 384 #define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67 385 #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68 386 #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80 387 #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82 388 #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84 389 #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86 390 #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88 391 #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a 392 #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c 393 #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e 394 #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90 395 #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92 396 #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94 397 #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98 398 #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0 399 400 mailbox = mlx4_alloc_cmd_mailbox(dev); 401 if (IS_ERR(mailbox)) 402 return PTR_ERR(mailbox); 403 outbox = mailbox->buf; 404 405 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, 406 MLX4_CMD_TIME_CLASS_A, !mlx4_is_slave(dev)); 407 if (err) 408 goto out; 409 410 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET); 411 dev_cap->reserved_qps = 1 << (field & 0xf); 412 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET); 413 dev_cap->max_qps = 1 << (field & 0x1f); 414 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET); 415 dev_cap->reserved_srqs = 1 << (field >> 4); 416 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET); 417 dev_cap->max_srqs = 1 << (field & 0x1f); 418 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET); 419 dev_cap->max_cq_sz = 1 << field; 420 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET); 421 dev_cap->reserved_cqs = 1 << (field & 0xf); 422 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET); 423 dev_cap->max_cqs = 1 << (field & 0x1f); 424 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET); 425 dev_cap->max_mpts = 1 << (field & 0x3f); 426 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET); 427 dev_cap->reserved_eqs = field & 0xf; 428 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET); 429 dev_cap->max_eqs = 1 << (field & 0xf); 430 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET); 431 dev_cap->reserved_mtts = 1 << (field >> 4); 432 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET); 433 dev_cap->max_mrw_sz = 1 << field; 434 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET); 435 dev_cap->reserved_mrws = 1 << (field & 0xf); 436 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET); 437 dev_cap->max_mtt_seg = 1 << (field & 0x3f); 438 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET); 439 dev_cap->max_requester_per_qp = 1 << (field & 0x3f); 440 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET); 441 dev_cap->max_responder_per_qp = 1 << (field & 0x3f); 442 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET); 443 field &= 0x1f; 444 if (!field) 445 dev_cap->max_gso_sz = 0; 446 else 447 dev_cap->max_gso_sz = 1 << field; 448 449 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET); 450 dev_cap->max_rdma_global = 1 << (field & 0x3f); 451 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET); 452 dev_cap->local_ca_ack_delay = field & 0x1f; 453 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); 454 dev_cap->num_ports = field & 0xf; 455 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET); 456 dev_cap->max_msg_sz = 1 << (field & 0x1f); 457 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET); 458 dev_cap->stat_rate_support = stat_rate; 459 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); 460 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET); 461 dev_cap->flags = flags | (u64)ext_flags << 32; 462 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET); 463 dev_cap->reserved_uars = field >> 4; 464 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET); 465 dev_cap->uar_size = 1 << ((field & 0x3f) + 20); 466 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET); 467 dev_cap->min_page_sz = 1 << field; 468 469 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET); 470 if (field & 0x80) { 471 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET); 472 dev_cap->bf_reg_size = 1 << (field & 0x1f); 473 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET); 474 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size)) 475 field = 3; 476 dev_cap->bf_regs_per_page = 1 << (field & 0x3f); 477 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n", 478 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page); 479 } else { 480 dev_cap->bf_reg_size = 0; 481 mlx4_dbg(dev, "BlueFlame not available\n"); 482 } 483 484 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET); 485 dev_cap->max_sq_sg = field; 486 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET); 487 dev_cap->max_sq_desc_sz = size; 488 489 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET); 490 dev_cap->max_qp_per_mcg = 1 << field; 491 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET); 492 dev_cap->reserved_mgms = field & 0xf; 493 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET); 494 dev_cap->max_mcgs = 1 << field; 495 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET); 496 dev_cap->reserved_pds = field >> 4; 497 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET); 498 dev_cap->max_pds = 1 << (field & 0x3f); 499 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET); 500 dev_cap->reserved_xrcds = field >> 4; 501 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET); 502 dev_cap->max_xrcds = 1 << (field & 0x1f); 503 504 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET); 505 dev_cap->rdmarc_entry_sz = size; 506 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET); 507 dev_cap->qpc_entry_sz = size; 508 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET); 509 dev_cap->aux_entry_sz = size; 510 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET); 511 dev_cap->altc_entry_sz = size; 512 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET); 513 dev_cap->eqc_entry_sz = size; 514 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET); 515 dev_cap->cqc_entry_sz = size; 516 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET); 517 dev_cap->srq_entry_sz = size; 518 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET); 519 dev_cap->cmpt_entry_sz = size; 520 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET); 521 dev_cap->mtt_entry_sz = size; 522 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET); 523 dev_cap->dmpt_entry_sz = size; 524 525 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET); 526 dev_cap->max_srq_sz = 1 << field; 527 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET); 528 dev_cap->max_qp_sz = 1 << field; 529 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET); 530 dev_cap->resize_srq = field & 1; 531 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET); 532 dev_cap->max_rq_sg = field; 533 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET); 534 dev_cap->max_rq_desc_sz = size; 535 536 MLX4_GET(dev_cap->bmme_flags, outbox, 537 QUERY_DEV_CAP_BMME_FLAGS_OFFSET); 538 MLX4_GET(dev_cap->reserved_lkey, outbox, 539 QUERY_DEV_CAP_RSVD_LKEY_OFFSET); 540 MLX4_GET(dev_cap->max_icm_sz, outbox, 541 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET); 542 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS) 543 MLX4_GET(dev_cap->max_counters, outbox, 544 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET); 545 546 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { 547 for (i = 1; i <= dev_cap->num_ports; ++i) { 548 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); 549 dev_cap->max_vl[i] = field >> 4; 550 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET); 551 dev_cap->ib_mtu[i] = field >> 4; 552 dev_cap->max_port_width[i] = field & 0xf; 553 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET); 554 dev_cap->max_gids[i] = 1 << (field & 0xf); 555 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET); 556 dev_cap->max_pkeys[i] = 1 << (field & 0xf); 557 } 558 } else { 559 #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00 560 #define QUERY_PORT_MTU_OFFSET 0x01 561 #define QUERY_PORT_ETH_MTU_OFFSET 0x02 562 #define QUERY_PORT_WIDTH_OFFSET 0x06 563 #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07 564 #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a 565 #define QUERY_PORT_MAX_VL_OFFSET 0x0b 566 #define QUERY_PORT_MAC_OFFSET 0x10 567 #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18 568 #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c 569 #define QUERY_PORT_TRANS_CODE_OFFSET 0x20 570 571 for (i = 1; i <= dev_cap->num_ports; ++i) { 572 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT, 573 MLX4_CMD_TIME_CLASS_B, 574 !mlx4_is_slave(dev)); 575 if (err) 576 goto out; 577 578 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET); 579 dev_cap->supported_port_types[i] = field & 3; 580 dev_cap->suggested_type[i] = (field >> 3) & 1; 581 dev_cap->default_sense[i] = (field >> 4) & 1; 582 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET); 583 dev_cap->ib_mtu[i] = field & 0xf; 584 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET); 585 dev_cap->max_port_width[i] = field & 0xf; 586 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET); 587 dev_cap->max_gids[i] = 1 << (field >> 4); 588 dev_cap->max_pkeys[i] = 1 << (field & 0xf); 589 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET); 590 dev_cap->max_vl[i] = field & 0xf; 591 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET); 592 dev_cap->log_max_macs[i] = field & 0xf; 593 dev_cap->log_max_vlans[i] = field >> 4; 594 MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET); 595 MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET); 596 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET); 597 dev_cap->trans_type[i] = field32 >> 24; 598 dev_cap->vendor_oui[i] = field32 & 0xffffff; 599 MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET); 600 MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET); 601 } 602 } 603 604 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n", 605 dev_cap->bmme_flags, dev_cap->reserved_lkey); 606 607 /* 608 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then 609 * we can't use any EQs whose doorbell falls on that page, 610 * even if the EQ itself isn't reserved. 611 */ 612 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4, 613 dev_cap->reserved_eqs); 614 615 mlx4_dbg(dev, "Max ICM size %lld MB\n", 616 (unsigned long long) dev_cap->max_icm_sz >> 20); 617 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n", 618 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz); 619 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n", 620 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz); 621 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n", 622 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz); 623 mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n", 624 dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz); 625 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n", 626 dev_cap->reserved_mrws, dev_cap->reserved_mtts); 627 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n", 628 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars); 629 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n", 630 dev_cap->max_pds, dev_cap->reserved_mgms); 631 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n", 632 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz); 633 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n", 634 dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1], 635 dev_cap->max_port_width[1]); 636 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n", 637 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg); 638 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n", 639 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg); 640 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz); 641 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters); 642 643 dump_dev_cap_flags(dev, dev_cap->flags); 644 645 out: 646 mlx4_free_cmd_mailbox(dev, mailbox); 647 return err; 648 } 649 650 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave, 651 struct mlx4_vhcr *vhcr, 652 struct mlx4_cmd_mailbox *inbox, 653 struct mlx4_cmd_mailbox *outbox, 654 struct mlx4_cmd_info *cmd) 655 { 656 u64 def_mac; 657 u8 port_type; 658 int err; 659 660 #define MLX4_PORT_SUPPORT_IB (1 << 0) 661 #define MLX4_PORT_SUGGEST_TYPE (1 << 3) 662 #define MLX4_PORT_DEFAULT_SENSE (1 << 4) 663 #define MLX4_VF_PORT_ETH_ONLY_MASK (0xff & ~MLX4_PORT_SUPPORT_IB & \ 664 ~MLX4_PORT_SUGGEST_TYPE & \ 665 ~MLX4_PORT_DEFAULT_SENSE) 666 667 err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0, 668 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, 669 MLX4_CMD_NATIVE); 670 671 if (!err && dev->caps.function != slave) { 672 /* set slave default_mac address */ 673 MLX4_GET(def_mac, outbox->buf, QUERY_PORT_MAC_OFFSET); 674 def_mac += slave << 8; 675 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET); 676 677 /* get port type - currently only eth is enabled */ 678 MLX4_GET(port_type, outbox->buf, 679 QUERY_PORT_SUPPORTED_TYPE_OFFSET); 680 681 /* Allow only Eth port, no link sensing allowed */ 682 port_type &= MLX4_VF_PORT_ETH_ONLY_MASK; 683 684 /* check eth is enabled for this port */ 685 if (!(port_type & 2)) 686 mlx4_dbg(dev, "QUERY PORT: eth not supported by host"); 687 688 MLX4_PUT(outbox->buf, port_type, 689 QUERY_PORT_SUPPORTED_TYPE_OFFSET); 690 } 691 692 return err; 693 } 694 695 static int mlx4_QUERY_PORT(struct mlx4_dev *dev, void *ptr, u8 port) 696 { 697 struct mlx4_cmd_mailbox *outbox = ptr; 698 699 return mlx4_cmd_box(dev, 0, outbox->dma, port, 0, 700 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, 701 MLX4_CMD_WRAPPED); 702 } 703 EXPORT_SYMBOL_GPL(mlx4_QUERY_PORT); 704 705 int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt) 706 { 707 struct mlx4_cmd_mailbox *mailbox; 708 struct mlx4_icm_iter iter; 709 __be64 *pages; 710 int lg; 711 int nent = 0; 712 int i; 713 int err = 0; 714 int ts = 0, tc = 0; 715 716 mailbox = mlx4_alloc_cmd_mailbox(dev); 717 if (IS_ERR(mailbox)) 718 return PTR_ERR(mailbox); 719 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE); 720 pages = mailbox->buf; 721 722 for (mlx4_icm_first(icm, &iter); 723 !mlx4_icm_last(&iter); 724 mlx4_icm_next(&iter)) { 725 /* 726 * We have to pass pages that are aligned to their 727 * size, so find the least significant 1 in the 728 * address or size and use that as our log2 size. 729 */ 730 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1; 731 if (lg < MLX4_ICM_PAGE_SHIFT) { 732 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n", 733 MLX4_ICM_PAGE_SIZE, 734 (unsigned long long) mlx4_icm_addr(&iter), 735 mlx4_icm_size(&iter)); 736 err = -EINVAL; 737 goto out; 738 } 739 740 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) { 741 if (virt != -1) { 742 pages[nent * 2] = cpu_to_be64(virt); 743 virt += 1 << lg; 744 } 745 746 pages[nent * 2 + 1] = 747 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) | 748 (lg - MLX4_ICM_PAGE_SHIFT)); 749 ts += 1 << (lg - 10); 750 ++tc; 751 752 if (++nent == MLX4_MAILBOX_SIZE / 16) { 753 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, 754 MLX4_CMD_TIME_CLASS_B, 755 MLX4_CMD_NATIVE); 756 if (err) 757 goto out; 758 nent = 0; 759 } 760 } 761 } 762 763 if (nent) 764 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, 765 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 766 if (err) 767 goto out; 768 769 switch (op) { 770 case MLX4_CMD_MAP_FA: 771 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts); 772 break; 773 case MLX4_CMD_MAP_ICM_AUX: 774 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts); 775 break; 776 case MLX4_CMD_MAP_ICM: 777 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n", 778 tc, ts, (unsigned long long) virt - (ts << 10)); 779 break; 780 } 781 782 out: 783 mlx4_free_cmd_mailbox(dev, mailbox); 784 return err; 785 } 786 787 int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm) 788 { 789 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1); 790 } 791 792 int mlx4_UNMAP_FA(struct mlx4_dev *dev) 793 { 794 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA, 795 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 796 } 797 798 799 int mlx4_RUN_FW(struct mlx4_dev *dev) 800 { 801 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW, 802 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 803 } 804 805 int mlx4_QUERY_FW(struct mlx4_dev *dev) 806 { 807 struct mlx4_fw *fw = &mlx4_priv(dev)->fw; 808 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd; 809 struct mlx4_cmd_mailbox *mailbox; 810 u32 *outbox; 811 int err = 0; 812 u64 fw_ver; 813 u16 cmd_if_rev; 814 u8 lg; 815 816 #define QUERY_FW_OUT_SIZE 0x100 817 #define QUERY_FW_VER_OFFSET 0x00 818 #define QUERY_FW_PPF_ID 0x09 819 #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a 820 #define QUERY_FW_MAX_CMD_OFFSET 0x0f 821 #define QUERY_FW_ERR_START_OFFSET 0x30 822 #define QUERY_FW_ERR_SIZE_OFFSET 0x38 823 #define QUERY_FW_ERR_BAR_OFFSET 0x3c 824 825 #define QUERY_FW_SIZE_OFFSET 0x00 826 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20 827 #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28 828 829 #define QUERY_FW_COMM_BASE_OFFSET 0x40 830 #define QUERY_FW_COMM_BAR_OFFSET 0x48 831 832 mailbox = mlx4_alloc_cmd_mailbox(dev); 833 if (IS_ERR(mailbox)) 834 return PTR_ERR(mailbox); 835 outbox = mailbox->buf; 836 837 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW, 838 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 839 if (err) 840 goto out; 841 842 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET); 843 /* 844 * FW subminor version is at more significant bits than minor 845 * version, so swap here. 846 */ 847 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) | 848 ((fw_ver & 0xffff0000ull) >> 16) | 849 ((fw_ver & 0x0000ffffull) << 16); 850 851 MLX4_GET(lg, outbox, QUERY_FW_PPF_ID); 852 dev->caps.function = lg; 853 854 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET); 855 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV || 856 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) { 857 mlx4_err(dev, "Installed FW has unsupported " 858 "command interface revision %d.\n", 859 cmd_if_rev); 860 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n", 861 (int) (dev->caps.fw_ver >> 32), 862 (int) (dev->caps.fw_ver >> 16) & 0xffff, 863 (int) dev->caps.fw_ver & 0xffff); 864 mlx4_err(dev, "This driver version supports only revisions %d to %d.\n", 865 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV); 866 err = -ENODEV; 867 goto out; 868 } 869 870 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS) 871 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS; 872 873 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET); 874 cmd->max_cmds = 1 << lg; 875 876 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n", 877 (int) (dev->caps.fw_ver >> 32), 878 (int) (dev->caps.fw_ver >> 16) & 0xffff, 879 (int) dev->caps.fw_ver & 0xffff, 880 cmd_if_rev, cmd->max_cmds); 881 882 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET); 883 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET); 884 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET); 885 fw->catas_bar = (fw->catas_bar >> 6) * 2; 886 887 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n", 888 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar); 889 890 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET); 891 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET); 892 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET); 893 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2; 894 895 MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET); 896 MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET); 897 fw->comm_bar = (fw->comm_bar >> 6) * 2; 898 mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n", 899 fw->comm_bar, fw->comm_base); 900 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2); 901 902 /* 903 * Round up number of system pages needed in case 904 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. 905 */ 906 fw->fw_pages = 907 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> 908 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); 909 910 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n", 911 (unsigned long long) fw->clr_int_base, fw->clr_int_bar); 912 913 out: 914 mlx4_free_cmd_mailbox(dev, mailbox); 915 return err; 916 } 917 918 static void get_board_id(void *vsd, char *board_id) 919 { 920 int i; 921 922 #define VSD_OFFSET_SIG1 0x00 923 #define VSD_OFFSET_SIG2 0xde 924 #define VSD_OFFSET_MLX_BOARD_ID 0xd0 925 #define VSD_OFFSET_TS_BOARD_ID 0x20 926 927 #define VSD_SIGNATURE_TOPSPIN 0x5ad 928 929 memset(board_id, 0, MLX4_BOARD_ID_LEN); 930 931 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN && 932 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) { 933 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN); 934 } else { 935 /* 936 * The board ID is a string but the firmware byte 937 * swaps each 4-byte word before passing it back to 938 * us. Therefore we need to swab it before printing. 939 */ 940 for (i = 0; i < 4; ++i) 941 ((u32 *) board_id)[i] = 942 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4)); 943 } 944 } 945 946 int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter) 947 { 948 struct mlx4_cmd_mailbox *mailbox; 949 u32 *outbox; 950 int err; 951 952 #define QUERY_ADAPTER_OUT_SIZE 0x100 953 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10 954 #define QUERY_ADAPTER_VSD_OFFSET 0x20 955 956 mailbox = mlx4_alloc_cmd_mailbox(dev); 957 if (IS_ERR(mailbox)) 958 return PTR_ERR(mailbox); 959 outbox = mailbox->buf; 960 961 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER, 962 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 963 if (err) 964 goto out; 965 966 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET); 967 968 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4, 969 adapter->board_id); 970 971 out: 972 mlx4_free_cmd_mailbox(dev, mailbox); 973 return err; 974 } 975 976 int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param) 977 { 978 struct mlx4_cmd_mailbox *mailbox; 979 __be32 *inbox; 980 int err; 981 982 #define INIT_HCA_IN_SIZE 0x200 983 #define INIT_HCA_VERSION_OFFSET 0x000 984 #define INIT_HCA_VERSION 2 985 #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e 986 #define INIT_HCA_FLAGS_OFFSET 0x014 987 #define INIT_HCA_QPC_OFFSET 0x020 988 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10) 989 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17) 990 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28) 991 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f) 992 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30) 993 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37) 994 #define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38) 995 #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40) 996 #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50) 997 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60) 998 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67) 999 #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70) 1000 #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77) 1001 #define INIT_HCA_MCAST_OFFSET 0x0c0 1002 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00) 1003 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12) 1004 #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16) 1005 #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18) 1006 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b) 1007 #define INIT_HCA_TPT_OFFSET 0x0f0 1008 #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00) 1009 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b) 1010 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10) 1011 #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18) 1012 #define INIT_HCA_UAR_OFFSET 0x120 1013 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a) 1014 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b) 1015 1016 mailbox = mlx4_alloc_cmd_mailbox(dev); 1017 if (IS_ERR(mailbox)) 1018 return PTR_ERR(mailbox); 1019 inbox = mailbox->buf; 1020 1021 memset(inbox, 0, INIT_HCA_IN_SIZE); 1022 1023 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION; 1024 1025 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) = 1026 (ilog2(cache_line_size()) - 4) << 5; 1027 1028 #if defined(__LITTLE_ENDIAN) 1029 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1); 1030 #elif defined(__BIG_ENDIAN) 1031 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1); 1032 #else 1033 #error Host endianness not defined 1034 #endif 1035 /* Check port for UD address vector: */ 1036 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1); 1037 1038 /* Enable IPoIB checksumming if we can: */ 1039 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM) 1040 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3); 1041 1042 /* Enable QoS support if module parameter set */ 1043 if (enable_qos) 1044 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2); 1045 1046 /* enable counters */ 1047 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS) 1048 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4); 1049 1050 /* QPC/EEC/CQC/EQC/RDMARC attributes */ 1051 1052 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET); 1053 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET); 1054 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET); 1055 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET); 1056 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET); 1057 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET); 1058 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET); 1059 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET); 1060 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET); 1061 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET); 1062 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET); 1063 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET); 1064 1065 /* multicast attributes */ 1066 1067 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET); 1068 MLX4_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); 1069 MLX4_PUT(inbox, param->log_mc_hash_sz, INIT_HCA_LOG_MC_HASH_SZ_OFFSET); 1070 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) 1071 MLX4_PUT(inbox, (u8) (1 << 3), INIT_HCA_UC_STEERING_OFFSET); 1072 MLX4_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); 1073 1074 /* TPT attributes */ 1075 1076 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET); 1077 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET); 1078 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET); 1079 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET); 1080 1081 /* UAR attributes */ 1082 1083 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET); 1084 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET); 1085 1086 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000, 1087 MLX4_CMD_NATIVE); 1088 1089 if (err) 1090 mlx4_err(dev, "INIT_HCA returns %d\n", err); 1091 1092 mlx4_free_cmd_mailbox(dev, mailbox); 1093 return err; 1094 } 1095 1096 int mlx4_QUERY_HCA(struct mlx4_dev *dev, 1097 struct mlx4_init_hca_param *param) 1098 { 1099 struct mlx4_cmd_mailbox *mailbox; 1100 __be32 *outbox; 1101 int err; 1102 1103 #define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04 1104 1105 mailbox = mlx4_alloc_cmd_mailbox(dev); 1106 if (IS_ERR(mailbox)) 1107 return PTR_ERR(mailbox); 1108 outbox = mailbox->buf; 1109 1110 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, 1111 MLX4_CMD_QUERY_HCA, 1112 MLX4_CMD_TIME_CLASS_B, 1113 !mlx4_is_slave(dev)); 1114 if (err) 1115 goto out; 1116 1117 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET); 1118 1119 /* QPC/EEC/CQC/EQC/RDMARC attributes */ 1120 1121 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET); 1122 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET); 1123 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET); 1124 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET); 1125 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET); 1126 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET); 1127 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET); 1128 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET); 1129 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET); 1130 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET); 1131 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET); 1132 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET); 1133 1134 /* multicast attributes */ 1135 1136 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET); 1137 MLX4_GET(param->log_mc_entry_sz, outbox, 1138 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); 1139 MLX4_GET(param->log_mc_hash_sz, outbox, 1140 INIT_HCA_LOG_MC_HASH_SZ_OFFSET); 1141 MLX4_GET(param->log_mc_table_sz, outbox, 1142 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); 1143 1144 /* TPT attributes */ 1145 1146 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET); 1147 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET); 1148 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET); 1149 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET); 1150 1151 /* UAR attributes */ 1152 1153 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET); 1154 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET); 1155 1156 out: 1157 mlx4_free_cmd_mailbox(dev, mailbox); 1158 1159 return err; 1160 } 1161 1162 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave, 1163 struct mlx4_vhcr *vhcr, 1164 struct mlx4_cmd_mailbox *inbox, 1165 struct mlx4_cmd_mailbox *outbox, 1166 struct mlx4_cmd_info *cmd) 1167 { 1168 struct mlx4_priv *priv = mlx4_priv(dev); 1169 int port = vhcr->in_modifier; 1170 int err; 1171 1172 if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port)) 1173 return 0; 1174 1175 if (dev->caps.port_mask[port] == MLX4_PORT_TYPE_IB) 1176 return -ENODEV; 1177 1178 /* Enable port only if it was previously disabled */ 1179 if (!priv->mfunc.master.init_port_ref[port]) { 1180 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, 1181 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1182 if (err) 1183 return err; 1184 priv->mfunc.master.slave_state[slave].init_port_mask |= 1185 (1 << port); 1186 } 1187 ++priv->mfunc.master.init_port_ref[port]; 1188 return 0; 1189 } 1190 1191 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port) 1192 { 1193 struct mlx4_cmd_mailbox *mailbox; 1194 u32 *inbox; 1195 int err; 1196 u32 flags; 1197 u16 field; 1198 1199 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { 1200 #define INIT_PORT_IN_SIZE 256 1201 #define INIT_PORT_FLAGS_OFFSET 0x00 1202 #define INIT_PORT_FLAG_SIG (1 << 18) 1203 #define INIT_PORT_FLAG_NG (1 << 17) 1204 #define INIT_PORT_FLAG_G0 (1 << 16) 1205 #define INIT_PORT_VL_SHIFT 4 1206 #define INIT_PORT_PORT_WIDTH_SHIFT 8 1207 #define INIT_PORT_MTU_OFFSET 0x04 1208 #define INIT_PORT_MAX_GID_OFFSET 0x06 1209 #define INIT_PORT_MAX_PKEY_OFFSET 0x0a 1210 #define INIT_PORT_GUID0_OFFSET 0x10 1211 #define INIT_PORT_NODE_GUID_OFFSET 0x18 1212 #define INIT_PORT_SI_GUID_OFFSET 0x20 1213 1214 mailbox = mlx4_alloc_cmd_mailbox(dev); 1215 if (IS_ERR(mailbox)) 1216 return PTR_ERR(mailbox); 1217 inbox = mailbox->buf; 1218 1219 memset(inbox, 0, INIT_PORT_IN_SIZE); 1220 1221 flags = 0; 1222 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT; 1223 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT; 1224 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET); 1225 1226 field = 128 << dev->caps.ib_mtu_cap[port]; 1227 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET); 1228 field = dev->caps.gid_table_len[port]; 1229 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET); 1230 field = dev->caps.pkey_table_len[port]; 1231 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET); 1232 1233 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT, 1234 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1235 1236 mlx4_free_cmd_mailbox(dev, mailbox); 1237 } else 1238 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, 1239 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 1240 1241 return err; 1242 } 1243 EXPORT_SYMBOL_GPL(mlx4_INIT_PORT); 1244 1245 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave, 1246 struct mlx4_vhcr *vhcr, 1247 struct mlx4_cmd_mailbox *inbox, 1248 struct mlx4_cmd_mailbox *outbox, 1249 struct mlx4_cmd_info *cmd) 1250 { 1251 struct mlx4_priv *priv = mlx4_priv(dev); 1252 int port = vhcr->in_modifier; 1253 int err; 1254 1255 if (!(priv->mfunc.master.slave_state[slave].init_port_mask & 1256 (1 << port))) 1257 return 0; 1258 1259 if (dev->caps.port_mask[port] == MLX4_PORT_TYPE_IB) 1260 return -ENODEV; 1261 if (priv->mfunc.master.init_port_ref[port] == 1) { 1262 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000, 1263 MLX4_CMD_NATIVE); 1264 if (err) 1265 return err; 1266 } 1267 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); 1268 --priv->mfunc.master.init_port_ref[port]; 1269 return 0; 1270 } 1271 1272 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port) 1273 { 1274 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000, 1275 MLX4_CMD_WRAPPED); 1276 } 1277 EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT); 1278 1279 int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic) 1280 { 1281 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000, 1282 MLX4_CMD_NATIVE); 1283 } 1284 1285 int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages) 1286 { 1287 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0, 1288 MLX4_CMD_SET_ICM_SIZE, 1289 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1290 if (ret) 1291 return ret; 1292 1293 /* 1294 * Round up number of system pages needed in case 1295 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. 1296 */ 1297 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> 1298 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); 1299 1300 return 0; 1301 } 1302 1303 int mlx4_NOP(struct mlx4_dev *dev) 1304 { 1305 /* Input modifier of 0x1f means "finish as soon as possible." */ 1306 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100, MLX4_CMD_NATIVE); 1307 } 1308 1309 #define MLX4_WOL_SETUP_MODE (5 << 28) 1310 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port) 1311 { 1312 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8; 1313 1314 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3, 1315 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A, 1316 MLX4_CMD_NATIVE); 1317 } 1318 EXPORT_SYMBOL_GPL(mlx4_wol_read); 1319 1320 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port) 1321 { 1322 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8; 1323 1324 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG, 1325 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1326 } 1327 EXPORT_SYMBOL_GPL(mlx4_wol_write); 1328