15a2cc190SJeff Kirsher /* 25a2cc190SJeff Kirsher * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 35a2cc190SJeff Kirsher * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 45a2cc190SJeff Kirsher * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved. 55a2cc190SJeff Kirsher * 65a2cc190SJeff Kirsher * This software is available to you under a choice of one of two 75a2cc190SJeff Kirsher * licenses. You may choose to be licensed under the terms of the GNU 85a2cc190SJeff Kirsher * General Public License (GPL) Version 2, available from the file 95a2cc190SJeff Kirsher * COPYING in the main directory of this source tree, or the 105a2cc190SJeff Kirsher * OpenIB.org BSD license below: 115a2cc190SJeff Kirsher * 125a2cc190SJeff Kirsher * Redistribution and use in source and binary forms, with or 135a2cc190SJeff Kirsher * without modification, are permitted provided that the following 145a2cc190SJeff Kirsher * conditions are met: 155a2cc190SJeff Kirsher * 165a2cc190SJeff Kirsher * - Redistributions of source code must retain the above 175a2cc190SJeff Kirsher * copyright notice, this list of conditions and the following 185a2cc190SJeff Kirsher * disclaimer. 195a2cc190SJeff Kirsher * 205a2cc190SJeff Kirsher * - Redistributions in binary form must reproduce the above 215a2cc190SJeff Kirsher * copyright notice, this list of conditions and the following 225a2cc190SJeff Kirsher * disclaimer in the documentation and/or other materials 235a2cc190SJeff Kirsher * provided with the distribution. 245a2cc190SJeff Kirsher * 255a2cc190SJeff Kirsher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 265a2cc190SJeff Kirsher * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 275a2cc190SJeff Kirsher * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 285a2cc190SJeff Kirsher * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 295a2cc190SJeff Kirsher * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 305a2cc190SJeff Kirsher * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 315a2cc190SJeff Kirsher * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 325a2cc190SJeff Kirsher * SOFTWARE. 335a2cc190SJeff Kirsher */ 345a2cc190SJeff Kirsher 355cc914f1SMarcel Apfelbaum #include <linux/etherdevice.h> 365a2cc190SJeff Kirsher #include <linux/mlx4/cmd.h> 379d9779e7SPaul Gortmaker #include <linux/module.h> 385a2cc190SJeff Kirsher #include <linux/cache.h> 395a2cc190SJeff Kirsher 405a2cc190SJeff Kirsher #include "fw.h" 415a2cc190SJeff Kirsher #include "icm.h" 425a2cc190SJeff Kirsher 435a2cc190SJeff Kirsher enum { 445a2cc190SJeff Kirsher MLX4_COMMAND_INTERFACE_MIN_REV = 2, 455a2cc190SJeff Kirsher MLX4_COMMAND_INTERFACE_MAX_REV = 3, 465a2cc190SJeff Kirsher MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3, 475a2cc190SJeff Kirsher }; 485a2cc190SJeff Kirsher 495a2cc190SJeff Kirsher extern void __buggy_use_of_MLX4_GET(void); 505a2cc190SJeff Kirsher extern void __buggy_use_of_MLX4_PUT(void); 515a2cc190SJeff Kirsher 52eb939922SRusty Russell static bool enable_qos; 535a2cc190SJeff Kirsher module_param(enable_qos, bool, 0444); 545a2cc190SJeff Kirsher MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)"); 555a2cc190SJeff Kirsher 565a2cc190SJeff Kirsher #define MLX4_GET(dest, source, offset) \ 575a2cc190SJeff Kirsher do { \ 585a2cc190SJeff Kirsher void *__p = (char *) (source) + (offset); \ 595a2cc190SJeff Kirsher switch (sizeof (dest)) { \ 605a2cc190SJeff Kirsher case 1: (dest) = *(u8 *) __p; break; \ 615a2cc190SJeff Kirsher case 2: (dest) = be16_to_cpup(__p); break; \ 625a2cc190SJeff Kirsher case 4: (dest) = be32_to_cpup(__p); break; \ 635a2cc190SJeff Kirsher case 8: (dest) = be64_to_cpup(__p); break; \ 645a2cc190SJeff Kirsher default: __buggy_use_of_MLX4_GET(); \ 655a2cc190SJeff Kirsher } \ 665a2cc190SJeff Kirsher } while (0) 675a2cc190SJeff Kirsher 685a2cc190SJeff Kirsher #define MLX4_PUT(dest, source, offset) \ 695a2cc190SJeff Kirsher do { \ 705a2cc190SJeff Kirsher void *__d = ((char *) (dest) + (offset)); \ 715a2cc190SJeff Kirsher switch (sizeof(source)) { \ 725a2cc190SJeff Kirsher case 1: *(u8 *) __d = (source); break; \ 735a2cc190SJeff Kirsher case 2: *(__be16 *) __d = cpu_to_be16(source); break; \ 745a2cc190SJeff Kirsher case 4: *(__be32 *) __d = cpu_to_be32(source); break; \ 755a2cc190SJeff Kirsher case 8: *(__be64 *) __d = cpu_to_be64(source); break; \ 765a2cc190SJeff Kirsher default: __buggy_use_of_MLX4_PUT(); \ 775a2cc190SJeff Kirsher } \ 785a2cc190SJeff Kirsher } while (0) 795a2cc190SJeff Kirsher 805a2cc190SJeff Kirsher static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags) 815a2cc190SJeff Kirsher { 825a2cc190SJeff Kirsher static const char *fname[] = { 835a2cc190SJeff Kirsher [ 0] = "RC transport", 845a2cc190SJeff Kirsher [ 1] = "UC transport", 855a2cc190SJeff Kirsher [ 2] = "UD transport", 865a2cc190SJeff Kirsher [ 3] = "XRC transport", 875a2cc190SJeff Kirsher [ 4] = "reliable multicast", 885a2cc190SJeff Kirsher [ 5] = "FCoIB support", 895a2cc190SJeff Kirsher [ 6] = "SRQ support", 905a2cc190SJeff Kirsher [ 7] = "IPoIB checksum offload", 915a2cc190SJeff Kirsher [ 8] = "P_Key violation counter", 925a2cc190SJeff Kirsher [ 9] = "Q_Key violation counter", 935a2cc190SJeff Kirsher [10] = "VMM", 944d531aa8SOr Gerlitz [12] = "Dual Port Different Protocol (DPDP) support", 955a2cc190SJeff Kirsher [15] = "Big LSO headers", 965a2cc190SJeff Kirsher [16] = "MW support", 975a2cc190SJeff Kirsher [17] = "APM support", 985a2cc190SJeff Kirsher [18] = "Atomic ops support", 995a2cc190SJeff Kirsher [19] = "Raw multicast support", 1005a2cc190SJeff Kirsher [20] = "Address vector port checking support", 1015a2cc190SJeff Kirsher [21] = "UD multicast support", 1025a2cc190SJeff Kirsher [24] = "Demand paging support", 1035a2cc190SJeff Kirsher [25] = "Router support", 1045a2cc190SJeff Kirsher [30] = "IBoE support", 1055a2cc190SJeff Kirsher [32] = "Unicast loopback support", 106f3a9d1f2SYevgeny Petrilin [34] = "FCS header control", 1075a2cc190SJeff Kirsher [38] = "Wake On LAN support", 1085a2cc190SJeff Kirsher [40] = "UDP RSS support", 1095a2cc190SJeff Kirsher [41] = "Unicast VEP steering support", 1105a2cc190SJeff Kirsher [42] = "Multicast VEP steering support", 1115a2cc190SJeff Kirsher [48] = "Counters support", 112540b3a39SOr Gerlitz [53] = "Port ETS Scheduler support", 1134d531aa8SOr Gerlitz [55] = "Port link type sensing support", 11400f5ce99SJack Morgenstein [59] = "Port management change event support", 11508ff3235SOr Gerlitz [61] = "64 byte EQE support", 11608ff3235SOr Gerlitz [62] = "64 byte CQE support", 1175a2cc190SJeff Kirsher }; 1185a2cc190SJeff Kirsher int i; 1195a2cc190SJeff Kirsher 1205a2cc190SJeff Kirsher mlx4_dbg(dev, "DEV_CAP flags:\n"); 1215a2cc190SJeff Kirsher for (i = 0; i < ARRAY_SIZE(fname); ++i) 1225a2cc190SJeff Kirsher if (fname[i] && (flags & (1LL << i))) 1235a2cc190SJeff Kirsher mlx4_dbg(dev, " %s\n", fname[i]); 1245a2cc190SJeff Kirsher } 1255a2cc190SJeff Kirsher 126b3416f44SShlomo Pongratz static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags) 127b3416f44SShlomo Pongratz { 128b3416f44SShlomo Pongratz static const char * const fname[] = { 129b3416f44SShlomo Pongratz [0] = "RSS support", 130b3416f44SShlomo Pongratz [1] = "RSS Toeplitz Hash Function support", 1310ff1fb65SHadar Hen Zion [2] = "RSS XOR Hash Function support", 132955154faSMatan Barak [3] = "Device manage flow steering support", 133d998735fSEugenia Emantayev [4] = "Automatic MAC reassignment support", 1344e8cf5b8SOr Gerlitz [5] = "Time stamping support", 1354e8cf5b8SOr Gerlitz [6] = "VST (control vlan insertion/stripping) support", 136b01978caSJack Morgenstein [7] = "FSM (MAC anti-spoofing) support", 137b01978caSJack Morgenstein [8] = "Dynamic QP updates support" 138b3416f44SShlomo Pongratz }; 139b3416f44SShlomo Pongratz int i; 140b3416f44SShlomo Pongratz 141b3416f44SShlomo Pongratz for (i = 0; i < ARRAY_SIZE(fname); ++i) 142b3416f44SShlomo Pongratz if (fname[i] && (flags & (1LL << i))) 143b3416f44SShlomo Pongratz mlx4_dbg(dev, " %s\n", fname[i]); 144b3416f44SShlomo Pongratz } 145b3416f44SShlomo Pongratz 1465a2cc190SJeff Kirsher int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg) 1475a2cc190SJeff Kirsher { 1485a2cc190SJeff Kirsher struct mlx4_cmd_mailbox *mailbox; 1495a2cc190SJeff Kirsher u32 *inbox; 1505a2cc190SJeff Kirsher int err = 0; 1515a2cc190SJeff Kirsher 1525a2cc190SJeff Kirsher #define MOD_STAT_CFG_IN_SIZE 0x100 1535a2cc190SJeff Kirsher 1545a2cc190SJeff Kirsher #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002 1555a2cc190SJeff Kirsher #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003 1565a2cc190SJeff Kirsher 1575a2cc190SJeff Kirsher mailbox = mlx4_alloc_cmd_mailbox(dev); 1585a2cc190SJeff Kirsher if (IS_ERR(mailbox)) 1595a2cc190SJeff Kirsher return PTR_ERR(mailbox); 1605a2cc190SJeff Kirsher inbox = mailbox->buf; 1615a2cc190SJeff Kirsher 1625a2cc190SJeff Kirsher memset(inbox, 0, MOD_STAT_CFG_IN_SIZE); 1635a2cc190SJeff Kirsher 1645a2cc190SJeff Kirsher MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET); 1655a2cc190SJeff Kirsher MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET); 1665a2cc190SJeff Kirsher 1675a2cc190SJeff Kirsher err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG, 168f9baff50SJack Morgenstein MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1695a2cc190SJeff Kirsher 1705a2cc190SJeff Kirsher mlx4_free_cmd_mailbox(dev, mailbox); 1715a2cc190SJeff Kirsher return err; 1725a2cc190SJeff Kirsher } 1735a2cc190SJeff Kirsher 1745cc914f1SMarcel Apfelbaum int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave, 1755cc914f1SMarcel Apfelbaum struct mlx4_vhcr *vhcr, 1765cc914f1SMarcel Apfelbaum struct mlx4_cmd_mailbox *inbox, 1775cc914f1SMarcel Apfelbaum struct mlx4_cmd_mailbox *outbox, 1785cc914f1SMarcel Apfelbaum struct mlx4_cmd_info *cmd) 1795cc914f1SMarcel Apfelbaum { 180*5a0d0a61SJack Morgenstein struct mlx4_priv *priv = mlx4_priv(dev); 1815cc914f1SMarcel Apfelbaum u8 field; 1825cc914f1SMarcel Apfelbaum u32 size; 1835cc914f1SMarcel Apfelbaum int err = 0; 1845cc914f1SMarcel Apfelbaum 1855cc914f1SMarcel Apfelbaum #define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0 1865cc914f1SMarcel Apfelbaum #define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1 1875cc914f1SMarcel Apfelbaum #define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4 188105c320fSJack Morgenstein #define QUERY_FUNC_CAP_FMR_OFFSET 0x8 1895cc914f1SMarcel Apfelbaum #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x10 1905cc914f1SMarcel Apfelbaum #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x14 1915cc914f1SMarcel Apfelbaum #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x18 1925cc914f1SMarcel Apfelbaum #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x20 1935cc914f1SMarcel Apfelbaum #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x24 1945cc914f1SMarcel Apfelbaum #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x28 1955cc914f1SMarcel Apfelbaum #define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c 19669612b9fSRoland Dreier #define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30 1975cc914f1SMarcel Apfelbaum 198105c320fSJack Morgenstein #define QUERY_FUNC_CAP_FMR_FLAG 0x80 199105c320fSJack Morgenstein #define QUERY_FUNC_CAP_FLAG_RDMA 0x40 200105c320fSJack Morgenstein #define QUERY_FUNC_CAP_FLAG_ETH 0x80 201105c320fSJack Morgenstein 202105c320fSJack Morgenstein /* when opcode modifier = 1 */ 2035cc914f1SMarcel Apfelbaum #define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3 204105c320fSJack Morgenstein #define QUERY_FUNC_CAP_RDMA_PROPS_OFFSET 0x8 2055cc914f1SMarcel Apfelbaum #define QUERY_FUNC_CAP_ETH_PROPS_OFFSET 0xc 2065cc914f1SMarcel Apfelbaum 20747605df9SJack Morgenstein #define QUERY_FUNC_CAP_QP0_TUNNEL 0x10 20847605df9SJack Morgenstein #define QUERY_FUNC_CAP_QP0_PROXY 0x14 20947605df9SJack Morgenstein #define QUERY_FUNC_CAP_QP1_TUNNEL 0x18 21047605df9SJack Morgenstein #define QUERY_FUNC_CAP_QP1_PROXY 0x1c 21147605df9SJack Morgenstein 212105c320fSJack Morgenstein #define QUERY_FUNC_CAP_ETH_PROPS_FORCE_MAC 0x40 213105c320fSJack Morgenstein #define QUERY_FUNC_CAP_ETH_PROPS_FORCE_VLAN 0x80 214105c320fSJack Morgenstein 215105c320fSJack Morgenstein #define QUERY_FUNC_CAP_RDMA_PROPS_FORCE_PHY_WQE_GID 0x80 216105c320fSJack Morgenstein 2175cc914f1SMarcel Apfelbaum if (vhcr->op_modifier == 1) { 218105c320fSJack Morgenstein field = 0; 219105c320fSJack Morgenstein /* ensure force vlan and force mac bits are not set */ 2205cc914f1SMarcel Apfelbaum MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_ETH_PROPS_OFFSET); 221105c320fSJack Morgenstein /* ensure that phy_wqe_gid bit is not set */ 222105c320fSJack Morgenstein MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_RDMA_PROPS_OFFSET); 223105c320fSJack Morgenstein 22447605df9SJack Morgenstein field = vhcr->in_modifier; /* phys-port = logical-port */ 22547605df9SJack Morgenstein MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); 22647605df9SJack Morgenstein 22747605df9SJack Morgenstein /* size is now the QP number */ 22847605df9SJack Morgenstein size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + field - 1; 22947605df9SJack Morgenstein MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL); 23047605df9SJack Morgenstein 23147605df9SJack Morgenstein size += 2; 23247605df9SJack Morgenstein MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL); 23347605df9SJack Morgenstein 23447605df9SJack Morgenstein size = dev->phys_caps.base_proxy_sqpn + 8 * slave + field - 1; 23547605df9SJack Morgenstein MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_PROXY); 23647605df9SJack Morgenstein 23747605df9SJack Morgenstein size += 2; 23847605df9SJack Morgenstein MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_PROXY); 23947605df9SJack Morgenstein 2405cc914f1SMarcel Apfelbaum } else if (vhcr->op_modifier == 0) { 241105c320fSJack Morgenstein /* enable rdma and ethernet interfaces */ 242105c320fSJack Morgenstein field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA); 2435cc914f1SMarcel Apfelbaum MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET); 2445cc914f1SMarcel Apfelbaum 2455cc914f1SMarcel Apfelbaum field = dev->caps.num_ports; 2465cc914f1SMarcel Apfelbaum MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); 2475cc914f1SMarcel Apfelbaum 24808ff3235SOr Gerlitz size = dev->caps.function_caps; /* set PF behaviours */ 2495cc914f1SMarcel Apfelbaum MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET); 2505cc914f1SMarcel Apfelbaum 251105c320fSJack Morgenstein field = 0; /* protected FMR support not available as yet */ 252105c320fSJack Morgenstein MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET); 253105c320fSJack Morgenstein 254*5a0d0a61SJack Morgenstein size = priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[slave]; 2555cc914f1SMarcel Apfelbaum MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET); 2565cc914f1SMarcel Apfelbaum 257*5a0d0a61SJack Morgenstein size = priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[slave]; 2585cc914f1SMarcel Apfelbaum MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET); 2595cc914f1SMarcel Apfelbaum 260*5a0d0a61SJack Morgenstein size = priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[slave]; 2615cc914f1SMarcel Apfelbaum MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET); 2625cc914f1SMarcel Apfelbaum 2635cc914f1SMarcel Apfelbaum size = dev->caps.num_eqs; 2645cc914f1SMarcel Apfelbaum MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET); 2655cc914f1SMarcel Apfelbaum 2665cc914f1SMarcel Apfelbaum size = dev->caps.reserved_eqs; 2675cc914f1SMarcel Apfelbaum MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); 2685cc914f1SMarcel Apfelbaum 269*5a0d0a61SJack Morgenstein size = priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[slave]; 2705cc914f1SMarcel Apfelbaum MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET); 2715cc914f1SMarcel Apfelbaum 272*5a0d0a61SJack Morgenstein size = priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[slave]; 2735cc914f1SMarcel Apfelbaum MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET); 2745cc914f1SMarcel Apfelbaum 2755cc914f1SMarcel Apfelbaum size = dev->caps.num_mgms + dev->caps.num_amgms; 2765cc914f1SMarcel Apfelbaum MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET); 2775cc914f1SMarcel Apfelbaum 2785cc914f1SMarcel Apfelbaum } else 2795cc914f1SMarcel Apfelbaum err = -EINVAL; 2805cc914f1SMarcel Apfelbaum 2815cc914f1SMarcel Apfelbaum return err; 2825cc914f1SMarcel Apfelbaum } 2835cc914f1SMarcel Apfelbaum 28447605df9SJack Morgenstein int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u32 gen_or_port, 28547605df9SJack Morgenstein struct mlx4_func_cap *func_cap) 2865cc914f1SMarcel Apfelbaum { 2875cc914f1SMarcel Apfelbaum struct mlx4_cmd_mailbox *mailbox; 2885cc914f1SMarcel Apfelbaum u32 *outbox; 28947605df9SJack Morgenstein u8 field, op_modifier; 2905cc914f1SMarcel Apfelbaum u32 size; 2915cc914f1SMarcel Apfelbaum int err = 0; 2925cc914f1SMarcel Apfelbaum 29347605df9SJack Morgenstein op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */ 2945cc914f1SMarcel Apfelbaum 2955cc914f1SMarcel Apfelbaum mailbox = mlx4_alloc_cmd_mailbox(dev); 2965cc914f1SMarcel Apfelbaum if (IS_ERR(mailbox)) 2975cc914f1SMarcel Apfelbaum return PTR_ERR(mailbox); 2985cc914f1SMarcel Apfelbaum 29947605df9SJack Morgenstein err = mlx4_cmd_box(dev, 0, mailbox->dma, gen_or_port, op_modifier, 30047605df9SJack Morgenstein MLX4_CMD_QUERY_FUNC_CAP, 3015cc914f1SMarcel Apfelbaum MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 3025cc914f1SMarcel Apfelbaum if (err) 3035cc914f1SMarcel Apfelbaum goto out; 3045cc914f1SMarcel Apfelbaum 3055cc914f1SMarcel Apfelbaum outbox = mailbox->buf; 3065cc914f1SMarcel Apfelbaum 30747605df9SJack Morgenstein if (!op_modifier) { 3085cc914f1SMarcel Apfelbaum MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET); 309105c320fSJack Morgenstein if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) { 310105c320fSJack Morgenstein mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n"); 3115cc914f1SMarcel Apfelbaum err = -EPROTONOSUPPORT; 3125cc914f1SMarcel Apfelbaum goto out; 3135cc914f1SMarcel Apfelbaum } 314105c320fSJack Morgenstein func_cap->flags = field; 3155cc914f1SMarcel Apfelbaum 3165cc914f1SMarcel Apfelbaum MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); 3175cc914f1SMarcel Apfelbaum func_cap->num_ports = field; 3185cc914f1SMarcel Apfelbaum 3195cc914f1SMarcel Apfelbaum MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET); 3205cc914f1SMarcel Apfelbaum func_cap->pf_context_behaviour = size; 3215cc914f1SMarcel Apfelbaum 3225cc914f1SMarcel Apfelbaum MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET); 3235cc914f1SMarcel Apfelbaum func_cap->qp_quota = size & 0xFFFFFF; 3245cc914f1SMarcel Apfelbaum 3255cc914f1SMarcel Apfelbaum MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET); 3265cc914f1SMarcel Apfelbaum func_cap->srq_quota = size & 0xFFFFFF; 3275cc914f1SMarcel Apfelbaum 3285cc914f1SMarcel Apfelbaum MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET); 3295cc914f1SMarcel Apfelbaum func_cap->cq_quota = size & 0xFFFFFF; 3305cc914f1SMarcel Apfelbaum 3315cc914f1SMarcel Apfelbaum MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET); 3325cc914f1SMarcel Apfelbaum func_cap->max_eq = size & 0xFFFFFF; 3335cc914f1SMarcel Apfelbaum 3345cc914f1SMarcel Apfelbaum MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); 3355cc914f1SMarcel Apfelbaum func_cap->reserved_eq = size & 0xFFFFFF; 3365cc914f1SMarcel Apfelbaum 3375cc914f1SMarcel Apfelbaum MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET); 3385cc914f1SMarcel Apfelbaum func_cap->mpt_quota = size & 0xFFFFFF; 3395cc914f1SMarcel Apfelbaum 3405cc914f1SMarcel Apfelbaum MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET); 3415cc914f1SMarcel Apfelbaum func_cap->mtt_quota = size & 0xFFFFFF; 3425cc914f1SMarcel Apfelbaum 3435cc914f1SMarcel Apfelbaum MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET); 3445cc914f1SMarcel Apfelbaum func_cap->mcg_quota = size & 0xFFFFFF; 3455cc914f1SMarcel Apfelbaum goto out; 34647605df9SJack Morgenstein } 3475cc914f1SMarcel Apfelbaum 34847605df9SJack Morgenstein /* logical port query */ 34947605df9SJack Morgenstein if (gen_or_port > dev->caps.num_ports) { 35047605df9SJack Morgenstein err = -EINVAL; 35147605df9SJack Morgenstein goto out; 35247605df9SJack Morgenstein } 35347605df9SJack Morgenstein 35447605df9SJack Morgenstein if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) { 3555cc914f1SMarcel Apfelbaum MLX4_GET(field, outbox, QUERY_FUNC_CAP_ETH_PROPS_OFFSET); 356105c320fSJack Morgenstein if (field & QUERY_FUNC_CAP_ETH_PROPS_FORCE_VLAN) { 3575cc914f1SMarcel Apfelbaum mlx4_err(dev, "VLAN is enforced on this port\n"); 3585cc914f1SMarcel Apfelbaum err = -EPROTONOSUPPORT; 3595cc914f1SMarcel Apfelbaum goto out; 3605cc914f1SMarcel Apfelbaum } 3615cc914f1SMarcel Apfelbaum 362105c320fSJack Morgenstein if (field & QUERY_FUNC_CAP_ETH_PROPS_FORCE_MAC) { 3635cc914f1SMarcel Apfelbaum mlx4_err(dev, "Force mac is enabled on this port\n"); 3645cc914f1SMarcel Apfelbaum err = -EPROTONOSUPPORT; 3655cc914f1SMarcel Apfelbaum goto out; 3665cc914f1SMarcel Apfelbaum } 36747605df9SJack Morgenstein } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) { 368105c320fSJack Morgenstein MLX4_GET(field, outbox, QUERY_FUNC_CAP_RDMA_PROPS_OFFSET); 369105c320fSJack Morgenstein if (field & QUERY_FUNC_CAP_RDMA_PROPS_FORCE_PHY_WQE_GID) { 370105c320fSJack Morgenstein mlx4_err(dev, "phy_wqe_gid is " 371105c320fSJack Morgenstein "enforced on this ib port\n"); 372105c320fSJack Morgenstein err = -EPROTONOSUPPORT; 373105c320fSJack Morgenstein goto out; 374105c320fSJack Morgenstein } 375105c320fSJack Morgenstein } 3765cc914f1SMarcel Apfelbaum 3775cc914f1SMarcel Apfelbaum MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); 37847605df9SJack Morgenstein func_cap->physical_port = field; 37947605df9SJack Morgenstein if (func_cap->physical_port != gen_or_port) { 38047605df9SJack Morgenstein err = -ENOSYS; 38147605df9SJack Morgenstein goto out; 3825cc914f1SMarcel Apfelbaum } 3835cc914f1SMarcel Apfelbaum 38447605df9SJack Morgenstein MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL); 38547605df9SJack Morgenstein func_cap->qp0_tunnel_qpn = size & 0xFFFFFF; 38647605df9SJack Morgenstein 38747605df9SJack Morgenstein MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY); 38847605df9SJack Morgenstein func_cap->qp0_proxy_qpn = size & 0xFFFFFF; 38947605df9SJack Morgenstein 39047605df9SJack Morgenstein MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL); 39147605df9SJack Morgenstein func_cap->qp1_tunnel_qpn = size & 0xFFFFFF; 39247605df9SJack Morgenstein 39347605df9SJack Morgenstein MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY); 39447605df9SJack Morgenstein func_cap->qp1_proxy_qpn = size & 0xFFFFFF; 39547605df9SJack Morgenstein 3965cc914f1SMarcel Apfelbaum /* All other resources are allocated by the master, but we still report 3975cc914f1SMarcel Apfelbaum * 'num' and 'reserved' capabilities as follows: 3985cc914f1SMarcel Apfelbaum * - num remains the maximum resource index 3995cc914f1SMarcel Apfelbaum * - 'num - reserved' is the total available objects of a resource, but 4005cc914f1SMarcel Apfelbaum * resource indices may be less than 'reserved' 4015cc914f1SMarcel Apfelbaum * TODO: set per-resource quotas */ 4025cc914f1SMarcel Apfelbaum 4035cc914f1SMarcel Apfelbaum out: 4045cc914f1SMarcel Apfelbaum mlx4_free_cmd_mailbox(dev, mailbox); 4055cc914f1SMarcel Apfelbaum 4065cc914f1SMarcel Apfelbaum return err; 4075cc914f1SMarcel Apfelbaum } 4085cc914f1SMarcel Apfelbaum 4095a2cc190SJeff Kirsher int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 4105a2cc190SJeff Kirsher { 4115a2cc190SJeff Kirsher struct mlx4_cmd_mailbox *mailbox; 4125a2cc190SJeff Kirsher u32 *outbox; 4135a2cc190SJeff Kirsher u8 field; 4145a2cc190SJeff Kirsher u32 field32, flags, ext_flags; 4155a2cc190SJeff Kirsher u16 size; 4165a2cc190SJeff Kirsher u16 stat_rate; 4175a2cc190SJeff Kirsher int err; 4185a2cc190SJeff Kirsher int i; 4195a2cc190SJeff Kirsher 4205a2cc190SJeff Kirsher #define QUERY_DEV_CAP_OUT_SIZE 0x100 4215a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10 4225a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11 4235a2cc190SJeff Kirsher #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12 4245a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13 4255a2cc190SJeff Kirsher #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14 4265a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15 4275a2cc190SJeff Kirsher #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16 4285a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17 4295a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19 4305a2cc190SJeff Kirsher #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a 4315a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b 4325a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d 4335a2cc190SJeff Kirsher #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e 4345a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f 4355a2cc190SJeff Kirsher #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20 4365a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21 4375a2cc190SJeff Kirsher #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22 4385a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23 4395a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27 4405a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29 4415a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b 4425a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d 443b3416f44SShlomo Pongratz #define QUERY_DEV_CAP_RSS_OFFSET 0x2e 4445a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f 4455a2cc190SJeff Kirsher #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33 4465a2cc190SJeff Kirsher #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35 4475a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36 4485a2cc190SJeff Kirsher #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37 4495a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38 4505a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b 4515a2cc190SJeff Kirsher #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c 452d998735fSEugenia Emantayev #define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e 4535a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f 4545a2cc190SJeff Kirsher #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40 4555a2cc190SJeff Kirsher #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44 4565a2cc190SJeff Kirsher #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48 4575a2cc190SJeff Kirsher #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49 4585a2cc190SJeff Kirsher #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b 4595a2cc190SJeff Kirsher #define QUERY_DEV_CAP_BF_OFFSET 0x4c 4605a2cc190SJeff Kirsher #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d 4615a2cc190SJeff Kirsher #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e 4625a2cc190SJeff Kirsher #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f 4635a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51 4645a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52 4655a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55 4665a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56 4675a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61 4685a2cc190SJeff Kirsher #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62 4695a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63 4705a2cc190SJeff Kirsher #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64 4715a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65 472f470f8d4SLinus Torvalds #define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66 473f470f8d4SLinus Torvalds #define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67 4745a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68 4753f7fb021SRony Efraim #define QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET 0x70 4760ff1fb65SHadar Hen Zion #define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76 4770ff1fb65SHadar Hen Zion #define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77 4785a2cc190SJeff Kirsher #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80 4795a2cc190SJeff Kirsher #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82 4805a2cc190SJeff Kirsher #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84 4815a2cc190SJeff Kirsher #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86 4825a2cc190SJeff Kirsher #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88 4835a2cc190SJeff Kirsher #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a 4845a2cc190SJeff Kirsher #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c 4855a2cc190SJeff Kirsher #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e 4865a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90 4875a2cc190SJeff Kirsher #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92 4885a2cc190SJeff Kirsher #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94 4895a2cc190SJeff Kirsher #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98 4905a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0 491955154faSMatan Barak #define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d 4925a2cc190SJeff Kirsher 493b3416f44SShlomo Pongratz dev_cap->flags2 = 0; 4945a2cc190SJeff Kirsher mailbox = mlx4_alloc_cmd_mailbox(dev); 4955a2cc190SJeff Kirsher if (IS_ERR(mailbox)) 4965a2cc190SJeff Kirsher return PTR_ERR(mailbox); 4975a2cc190SJeff Kirsher outbox = mailbox->buf; 4985a2cc190SJeff Kirsher 4995a2cc190SJeff Kirsher err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, 500401453a3SJack Morgenstein MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 5015a2cc190SJeff Kirsher if (err) 5025a2cc190SJeff Kirsher goto out; 5035a2cc190SJeff Kirsher 5045a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET); 5055a2cc190SJeff Kirsher dev_cap->reserved_qps = 1 << (field & 0xf); 5065a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET); 5075a2cc190SJeff Kirsher dev_cap->max_qps = 1 << (field & 0x1f); 5085a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET); 5095a2cc190SJeff Kirsher dev_cap->reserved_srqs = 1 << (field >> 4); 5105a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET); 5115a2cc190SJeff Kirsher dev_cap->max_srqs = 1 << (field & 0x1f); 5125a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET); 5135a2cc190SJeff Kirsher dev_cap->max_cq_sz = 1 << field; 5145a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET); 5155a2cc190SJeff Kirsher dev_cap->reserved_cqs = 1 << (field & 0xf); 5165a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET); 5175a2cc190SJeff Kirsher dev_cap->max_cqs = 1 << (field & 0x1f); 5185a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET); 5195a2cc190SJeff Kirsher dev_cap->max_mpts = 1 << (field & 0x3f); 5205a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET); 5215a2cc190SJeff Kirsher dev_cap->reserved_eqs = field & 0xf; 5225a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET); 5235a2cc190SJeff Kirsher dev_cap->max_eqs = 1 << (field & 0xf); 5245a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET); 5255a2cc190SJeff Kirsher dev_cap->reserved_mtts = 1 << (field >> 4); 5265a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET); 5275a2cc190SJeff Kirsher dev_cap->max_mrw_sz = 1 << field; 5285a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET); 5295a2cc190SJeff Kirsher dev_cap->reserved_mrws = 1 << (field & 0xf); 5305a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET); 5315a2cc190SJeff Kirsher dev_cap->max_mtt_seg = 1 << (field & 0x3f); 5325a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET); 5335a2cc190SJeff Kirsher dev_cap->max_requester_per_qp = 1 << (field & 0x3f); 5345a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET); 5355a2cc190SJeff Kirsher dev_cap->max_responder_per_qp = 1 << (field & 0x3f); 5365a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET); 5375a2cc190SJeff Kirsher field &= 0x1f; 5385a2cc190SJeff Kirsher if (!field) 5395a2cc190SJeff Kirsher dev_cap->max_gso_sz = 0; 5405a2cc190SJeff Kirsher else 5415a2cc190SJeff Kirsher dev_cap->max_gso_sz = 1 << field; 5425a2cc190SJeff Kirsher 543b3416f44SShlomo Pongratz MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET); 544b3416f44SShlomo Pongratz if (field & 0x20) 545b3416f44SShlomo Pongratz dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR; 546b3416f44SShlomo Pongratz if (field & 0x10) 547b3416f44SShlomo Pongratz dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP; 548b3416f44SShlomo Pongratz field &= 0xf; 549b3416f44SShlomo Pongratz if (field) { 550b3416f44SShlomo Pongratz dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS; 551b3416f44SShlomo Pongratz dev_cap->max_rss_tbl_sz = 1 << field; 552b3416f44SShlomo Pongratz } else 553b3416f44SShlomo Pongratz dev_cap->max_rss_tbl_sz = 0; 5545a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET); 5555a2cc190SJeff Kirsher dev_cap->max_rdma_global = 1 << (field & 0x3f); 5565a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET); 5575a2cc190SJeff Kirsher dev_cap->local_ca_ack_delay = field & 0x1f; 5585a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); 5595a2cc190SJeff Kirsher dev_cap->num_ports = field & 0xf; 5605a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET); 5615a2cc190SJeff Kirsher dev_cap->max_msg_sz = 1 << (field & 0x1f); 5620ff1fb65SHadar Hen Zion MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); 5630ff1fb65SHadar Hen Zion if (field & 0x80) 5640ff1fb65SHadar Hen Zion dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN; 5650ff1fb65SHadar Hen Zion dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f; 5660ff1fb65SHadar Hen Zion MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET); 5670ff1fb65SHadar Hen Zion dev_cap->fs_max_num_qp_per_entry = field; 5685a2cc190SJeff Kirsher MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET); 5695a2cc190SJeff Kirsher dev_cap->stat_rate_support = stat_rate; 570d998735fSEugenia Emantayev MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); 571d998735fSEugenia Emantayev if (field & 0x80) 572d998735fSEugenia Emantayev dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS; 5735a2cc190SJeff Kirsher MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); 5745a2cc190SJeff Kirsher MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET); 5755a2cc190SJeff Kirsher dev_cap->flags = flags | (u64)ext_flags << 32; 5765a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET); 5775a2cc190SJeff Kirsher dev_cap->reserved_uars = field >> 4; 5785a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET); 5795a2cc190SJeff Kirsher dev_cap->uar_size = 1 << ((field & 0x3f) + 20); 5805a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET); 5815a2cc190SJeff Kirsher dev_cap->min_page_sz = 1 << field; 5825a2cc190SJeff Kirsher 5835a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET); 5845a2cc190SJeff Kirsher if (field & 0x80) { 5855a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET); 5865a2cc190SJeff Kirsher dev_cap->bf_reg_size = 1 << (field & 0x1f); 5875a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET); 5885a2cc190SJeff Kirsher if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size)) 5895a2cc190SJeff Kirsher field = 3; 5905a2cc190SJeff Kirsher dev_cap->bf_regs_per_page = 1 << (field & 0x3f); 5915a2cc190SJeff Kirsher mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n", 5925a2cc190SJeff Kirsher dev_cap->bf_reg_size, dev_cap->bf_regs_per_page); 5935a2cc190SJeff Kirsher } else { 5945a2cc190SJeff Kirsher dev_cap->bf_reg_size = 0; 5955a2cc190SJeff Kirsher mlx4_dbg(dev, "BlueFlame not available\n"); 5965a2cc190SJeff Kirsher } 5975a2cc190SJeff Kirsher 5985a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET); 5995a2cc190SJeff Kirsher dev_cap->max_sq_sg = field; 6005a2cc190SJeff Kirsher MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET); 6015a2cc190SJeff Kirsher dev_cap->max_sq_desc_sz = size; 6025a2cc190SJeff Kirsher 6035a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET); 6045a2cc190SJeff Kirsher dev_cap->max_qp_per_mcg = 1 << field; 6055a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET); 6065a2cc190SJeff Kirsher dev_cap->reserved_mgms = field & 0xf; 6075a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET); 6085a2cc190SJeff Kirsher dev_cap->max_mcgs = 1 << field; 6095a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET); 6105a2cc190SJeff Kirsher dev_cap->reserved_pds = field >> 4; 6115a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET); 6125a2cc190SJeff Kirsher dev_cap->max_pds = 1 << (field & 0x3f); 613f470f8d4SLinus Torvalds MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET); 614f470f8d4SLinus Torvalds dev_cap->reserved_xrcds = field >> 4; 615426dd00dSDotan Barak MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET); 616f470f8d4SLinus Torvalds dev_cap->max_xrcds = 1 << (field & 0x1f); 6175a2cc190SJeff Kirsher 6185a2cc190SJeff Kirsher MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET); 6195a2cc190SJeff Kirsher dev_cap->rdmarc_entry_sz = size; 6205a2cc190SJeff Kirsher MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET); 6215a2cc190SJeff Kirsher dev_cap->qpc_entry_sz = size; 6225a2cc190SJeff Kirsher MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET); 6235a2cc190SJeff Kirsher dev_cap->aux_entry_sz = size; 6245a2cc190SJeff Kirsher MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET); 6255a2cc190SJeff Kirsher dev_cap->altc_entry_sz = size; 6265a2cc190SJeff Kirsher MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET); 6275a2cc190SJeff Kirsher dev_cap->eqc_entry_sz = size; 6285a2cc190SJeff Kirsher MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET); 6295a2cc190SJeff Kirsher dev_cap->cqc_entry_sz = size; 6305a2cc190SJeff Kirsher MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET); 6315a2cc190SJeff Kirsher dev_cap->srq_entry_sz = size; 6325a2cc190SJeff Kirsher MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET); 6335a2cc190SJeff Kirsher dev_cap->cmpt_entry_sz = size; 6345a2cc190SJeff Kirsher MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET); 6355a2cc190SJeff Kirsher dev_cap->mtt_entry_sz = size; 6365a2cc190SJeff Kirsher MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET); 6375a2cc190SJeff Kirsher dev_cap->dmpt_entry_sz = size; 6385a2cc190SJeff Kirsher 6395a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET); 6405a2cc190SJeff Kirsher dev_cap->max_srq_sz = 1 << field; 6415a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET); 6425a2cc190SJeff Kirsher dev_cap->max_qp_sz = 1 << field; 6435a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET); 6445a2cc190SJeff Kirsher dev_cap->resize_srq = field & 1; 6455a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET); 6465a2cc190SJeff Kirsher dev_cap->max_rq_sg = field; 6475a2cc190SJeff Kirsher MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET); 6485a2cc190SJeff Kirsher dev_cap->max_rq_desc_sz = size; 6495a2cc190SJeff Kirsher 6505a2cc190SJeff Kirsher MLX4_GET(dev_cap->bmme_flags, outbox, 6515a2cc190SJeff Kirsher QUERY_DEV_CAP_BMME_FLAGS_OFFSET); 6525a2cc190SJeff Kirsher MLX4_GET(dev_cap->reserved_lkey, outbox, 6535a2cc190SJeff Kirsher QUERY_DEV_CAP_RSVD_LKEY_OFFSET); 654955154faSMatan Barak MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC); 655955154faSMatan Barak if (field & 1<<6) 6565930e8d0SOr Gerlitz dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN; 6575a2cc190SJeff Kirsher MLX4_GET(dev_cap->max_icm_sz, outbox, 6585a2cc190SJeff Kirsher QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET); 6595a2cc190SJeff Kirsher if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS) 6605a2cc190SJeff Kirsher MLX4_GET(dev_cap->max_counters, outbox, 6615a2cc190SJeff Kirsher QUERY_DEV_CAP_MAX_COUNTERS_OFFSET); 6625a2cc190SJeff Kirsher 6633f7fb021SRony Efraim MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); 664b01978caSJack Morgenstein if (field32 & (1 << 16)) 665b01978caSJack Morgenstein dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP; 6663f7fb021SRony Efraim if (field32 & (1 << 26)) 6673f7fb021SRony Efraim dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL; 668e6b6a231SRony Efraim if (field32 & (1 << 20)) 669e6b6a231SRony Efraim dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM; 6703f7fb021SRony Efraim 6715a2cc190SJeff Kirsher if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { 6725a2cc190SJeff Kirsher for (i = 1; i <= dev_cap->num_ports; ++i) { 6735a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); 6745a2cc190SJeff Kirsher dev_cap->max_vl[i] = field >> 4; 6755a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET); 6765a2cc190SJeff Kirsher dev_cap->ib_mtu[i] = field >> 4; 6775a2cc190SJeff Kirsher dev_cap->max_port_width[i] = field & 0xf; 6785a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET); 6795a2cc190SJeff Kirsher dev_cap->max_gids[i] = 1 << (field & 0xf); 6805a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET); 6815a2cc190SJeff Kirsher dev_cap->max_pkeys[i] = 1 << (field & 0xf); 6825a2cc190SJeff Kirsher } 6835a2cc190SJeff Kirsher } else { 6845a2cc190SJeff Kirsher #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00 6855a2cc190SJeff Kirsher #define QUERY_PORT_MTU_OFFSET 0x01 6865a2cc190SJeff Kirsher #define QUERY_PORT_ETH_MTU_OFFSET 0x02 6875a2cc190SJeff Kirsher #define QUERY_PORT_WIDTH_OFFSET 0x06 6885a2cc190SJeff Kirsher #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07 6895a2cc190SJeff Kirsher #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a 6905a2cc190SJeff Kirsher #define QUERY_PORT_MAX_VL_OFFSET 0x0b 6915a2cc190SJeff Kirsher #define QUERY_PORT_MAC_OFFSET 0x10 6925a2cc190SJeff Kirsher #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18 6935a2cc190SJeff Kirsher #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c 6945a2cc190SJeff Kirsher #define QUERY_PORT_TRANS_CODE_OFFSET 0x20 6955a2cc190SJeff Kirsher 6965a2cc190SJeff Kirsher for (i = 1; i <= dev_cap->num_ports; ++i) { 6975a2cc190SJeff Kirsher err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT, 698401453a3SJack Morgenstein MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 6995a2cc190SJeff Kirsher if (err) 7005a2cc190SJeff Kirsher goto out; 7015a2cc190SJeff Kirsher 7025a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET); 7035a2cc190SJeff Kirsher dev_cap->supported_port_types[i] = field & 3; 7048d0fc7b6SYevgeny Petrilin dev_cap->suggested_type[i] = (field >> 3) & 1; 7058d0fc7b6SYevgeny Petrilin dev_cap->default_sense[i] = (field >> 4) & 1; 7065a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET); 7075a2cc190SJeff Kirsher dev_cap->ib_mtu[i] = field & 0xf; 7085a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET); 7095a2cc190SJeff Kirsher dev_cap->max_port_width[i] = field & 0xf; 7105a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET); 7115a2cc190SJeff Kirsher dev_cap->max_gids[i] = 1 << (field >> 4); 7125a2cc190SJeff Kirsher dev_cap->max_pkeys[i] = 1 << (field & 0xf); 7135a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET); 7145a2cc190SJeff Kirsher dev_cap->max_vl[i] = field & 0xf; 7155a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET); 7165a2cc190SJeff Kirsher dev_cap->log_max_macs[i] = field & 0xf; 7175a2cc190SJeff Kirsher dev_cap->log_max_vlans[i] = field >> 4; 7185a2cc190SJeff Kirsher MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET); 7195a2cc190SJeff Kirsher MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET); 7205a2cc190SJeff Kirsher MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET); 7215a2cc190SJeff Kirsher dev_cap->trans_type[i] = field32 >> 24; 7225a2cc190SJeff Kirsher dev_cap->vendor_oui[i] = field32 & 0xffffff; 7235a2cc190SJeff Kirsher MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET); 7245a2cc190SJeff Kirsher MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET); 7255a2cc190SJeff Kirsher } 7265a2cc190SJeff Kirsher } 7275a2cc190SJeff Kirsher 7285a2cc190SJeff Kirsher mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n", 7295a2cc190SJeff Kirsher dev_cap->bmme_flags, dev_cap->reserved_lkey); 7305a2cc190SJeff Kirsher 7315a2cc190SJeff Kirsher /* 7325a2cc190SJeff Kirsher * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then 7335a2cc190SJeff Kirsher * we can't use any EQs whose doorbell falls on that page, 7345a2cc190SJeff Kirsher * even if the EQ itself isn't reserved. 7355a2cc190SJeff Kirsher */ 7365a2cc190SJeff Kirsher dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4, 7375a2cc190SJeff Kirsher dev_cap->reserved_eqs); 7385a2cc190SJeff Kirsher 7395a2cc190SJeff Kirsher mlx4_dbg(dev, "Max ICM size %lld MB\n", 7405a2cc190SJeff Kirsher (unsigned long long) dev_cap->max_icm_sz >> 20); 7415a2cc190SJeff Kirsher mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n", 7425a2cc190SJeff Kirsher dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz); 7435a2cc190SJeff Kirsher mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n", 7445a2cc190SJeff Kirsher dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz); 7455a2cc190SJeff Kirsher mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n", 7465a2cc190SJeff Kirsher dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz); 7475a2cc190SJeff Kirsher mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n", 7485a2cc190SJeff Kirsher dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz); 7495a2cc190SJeff Kirsher mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n", 7505a2cc190SJeff Kirsher dev_cap->reserved_mrws, dev_cap->reserved_mtts); 7515a2cc190SJeff Kirsher mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n", 7525a2cc190SJeff Kirsher dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars); 7535a2cc190SJeff Kirsher mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n", 7545a2cc190SJeff Kirsher dev_cap->max_pds, dev_cap->reserved_mgms); 7555a2cc190SJeff Kirsher mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n", 7565a2cc190SJeff Kirsher dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz); 7575a2cc190SJeff Kirsher mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n", 7585a2cc190SJeff Kirsher dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1], 7595a2cc190SJeff Kirsher dev_cap->max_port_width[1]); 7605a2cc190SJeff Kirsher mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n", 7615a2cc190SJeff Kirsher dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg); 7625a2cc190SJeff Kirsher mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n", 7635a2cc190SJeff Kirsher dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg); 7645a2cc190SJeff Kirsher mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz); 7655a2cc190SJeff Kirsher mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters); 766b3416f44SShlomo Pongratz mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz); 7675a2cc190SJeff Kirsher 7685a2cc190SJeff Kirsher dump_dev_cap_flags(dev, dev_cap->flags); 769b3416f44SShlomo Pongratz dump_dev_cap_flags2(dev, dev_cap->flags2); 7705a2cc190SJeff Kirsher 7715a2cc190SJeff Kirsher out: 7725a2cc190SJeff Kirsher mlx4_free_cmd_mailbox(dev, mailbox); 7735a2cc190SJeff Kirsher return err; 7745a2cc190SJeff Kirsher } 7755a2cc190SJeff Kirsher 776b91cb3ebSJack Morgenstein int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave, 777b91cb3ebSJack Morgenstein struct mlx4_vhcr *vhcr, 778b91cb3ebSJack Morgenstein struct mlx4_cmd_mailbox *inbox, 779b91cb3ebSJack Morgenstein struct mlx4_cmd_mailbox *outbox, 780b91cb3ebSJack Morgenstein struct mlx4_cmd_info *cmd) 781b91cb3ebSJack Morgenstein { 7822a4fae14SJack Morgenstein u64 flags; 783b91cb3ebSJack Morgenstein int err = 0; 784b91cb3ebSJack Morgenstein u8 field; 785cc1ade94SShani Michaeli u32 bmme_flags; 786b91cb3ebSJack Morgenstein 787b91cb3ebSJack Morgenstein err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, 788b91cb3ebSJack Morgenstein MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 789b91cb3ebSJack Morgenstein if (err) 790b91cb3ebSJack Morgenstein return err; 791b91cb3ebSJack Morgenstein 792cc1ade94SShani Michaeli /* add port mng change event capability and disable mw type 1 793cc1ade94SShani Michaeli * unconditionally to slaves 794cc1ade94SShani Michaeli */ 7952a4fae14SJack Morgenstein MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); 7962a4fae14SJack Morgenstein flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV; 797cc1ade94SShani Michaeli flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW; 7982a4fae14SJack Morgenstein MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); 7992a4fae14SJack Morgenstein 80030b40c31SAmir Vadai /* For guests, disable timestamp */ 80130b40c31SAmir Vadai MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); 80230b40c31SAmir Vadai field &= 0x7f; 80330b40c31SAmir Vadai MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); 80430b40c31SAmir Vadai 805b91cb3ebSJack Morgenstein /* For guests, report Blueflame disabled */ 806b91cb3ebSJack Morgenstein MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET); 807b91cb3ebSJack Morgenstein field &= 0x7f; 808b91cb3ebSJack Morgenstein MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET); 809b91cb3ebSJack Morgenstein 810cc1ade94SShani Michaeli /* For guests, disable mw type 2 */ 811cc1ade94SShani Michaeli MLX4_GET(bmme_flags, outbox, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); 812cc1ade94SShani Michaeli bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN; 813cc1ade94SShani Michaeli MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); 814cc1ade94SShani Michaeli 8150081c8f3SJack Morgenstein /* turn off device-managed steering capability if not enabled */ 8160081c8f3SJack Morgenstein if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) { 8170081c8f3SJack Morgenstein MLX4_GET(field, outbox->buf, 8180081c8f3SJack Morgenstein QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); 8190081c8f3SJack Morgenstein field &= 0x7f; 8200081c8f3SJack Morgenstein MLX4_PUT(outbox->buf, field, 8210081c8f3SJack Morgenstein QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); 8220081c8f3SJack Morgenstein } 823b91cb3ebSJack Morgenstein return 0; 824b91cb3ebSJack Morgenstein } 825b91cb3ebSJack Morgenstein 8265cc914f1SMarcel Apfelbaum int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave, 8275cc914f1SMarcel Apfelbaum struct mlx4_vhcr *vhcr, 8285cc914f1SMarcel Apfelbaum struct mlx4_cmd_mailbox *inbox, 8295cc914f1SMarcel Apfelbaum struct mlx4_cmd_mailbox *outbox, 8305cc914f1SMarcel Apfelbaum struct mlx4_cmd_info *cmd) 8315cc914f1SMarcel Apfelbaum { 8320eb62b93SRony Efraim struct mlx4_priv *priv = mlx4_priv(dev); 8335cc914f1SMarcel Apfelbaum u64 def_mac; 8345cc914f1SMarcel Apfelbaum u8 port_type; 8356634961cSJack Morgenstein u16 short_field; 8365cc914f1SMarcel Apfelbaum int err; 837948e306dSRony Efraim int admin_link_state; 8385cc914f1SMarcel Apfelbaum 839105c320fSJack Morgenstein #define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0 840948e306dSRony Efraim #define MLX4_PORT_LINK_UP_MASK 0x80 8416634961cSJack Morgenstein #define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c 8426634961cSJack Morgenstein #define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e 84395f56e7aSYevgeny Petrilin 8445cc914f1SMarcel Apfelbaum err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0, 8455cc914f1SMarcel Apfelbaum MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, 8465cc914f1SMarcel Apfelbaum MLX4_CMD_NATIVE); 8475cc914f1SMarcel Apfelbaum 8485cc914f1SMarcel Apfelbaum if (!err && dev->caps.function != slave) { 8490eb62b93SRony Efraim def_mac = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac; 8505cc914f1SMarcel Apfelbaum MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET); 8515cc914f1SMarcel Apfelbaum 8525cc914f1SMarcel Apfelbaum /* get port type - currently only eth is enabled */ 8535cc914f1SMarcel Apfelbaum MLX4_GET(port_type, outbox->buf, 8545cc914f1SMarcel Apfelbaum QUERY_PORT_SUPPORTED_TYPE_OFFSET); 8555cc914f1SMarcel Apfelbaum 856105c320fSJack Morgenstein /* No link sensing allowed */ 857105c320fSJack Morgenstein port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK; 858105c320fSJack Morgenstein /* set port type to currently operating port type */ 859105c320fSJack Morgenstein port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3); 8605cc914f1SMarcel Apfelbaum 861948e306dSRony Efraim admin_link_state = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.link_state; 862948e306dSRony Efraim if (IFLA_VF_LINK_STATE_ENABLE == admin_link_state) 863948e306dSRony Efraim port_type |= MLX4_PORT_LINK_UP_MASK; 864948e306dSRony Efraim else if (IFLA_VF_LINK_STATE_DISABLE == admin_link_state) 865948e306dSRony Efraim port_type &= ~MLX4_PORT_LINK_UP_MASK; 866948e306dSRony Efraim 8675cc914f1SMarcel Apfelbaum MLX4_PUT(outbox->buf, port_type, 8685cc914f1SMarcel Apfelbaum QUERY_PORT_SUPPORTED_TYPE_OFFSET); 8696634961cSJack Morgenstein 8706634961cSJack Morgenstein short_field = 1; /* slave max gids */ 8716634961cSJack Morgenstein MLX4_PUT(outbox->buf, short_field, 8726634961cSJack Morgenstein QUERY_PORT_CUR_MAX_GID_OFFSET); 8736634961cSJack Morgenstein 8746634961cSJack Morgenstein short_field = dev->caps.pkey_table_len[vhcr->in_modifier]; 8756634961cSJack Morgenstein MLX4_PUT(outbox->buf, short_field, 8766634961cSJack Morgenstein QUERY_PORT_CUR_MAX_PKEY_OFFSET); 8775cc914f1SMarcel Apfelbaum } 8785cc914f1SMarcel Apfelbaum 8795cc914f1SMarcel Apfelbaum return err; 8805cc914f1SMarcel Apfelbaum } 8815cc914f1SMarcel Apfelbaum 8826634961cSJack Morgenstein int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port, 8836634961cSJack Morgenstein int *gid_tbl_len, int *pkey_tbl_len) 8846634961cSJack Morgenstein { 8856634961cSJack Morgenstein struct mlx4_cmd_mailbox *mailbox; 8866634961cSJack Morgenstein u32 *outbox; 8876634961cSJack Morgenstein u16 field; 8886634961cSJack Morgenstein int err; 8896634961cSJack Morgenstein 8906634961cSJack Morgenstein mailbox = mlx4_alloc_cmd_mailbox(dev); 8916634961cSJack Morgenstein if (IS_ERR(mailbox)) 8926634961cSJack Morgenstein return PTR_ERR(mailbox); 8936634961cSJack Morgenstein 8946634961cSJack Morgenstein err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0, 8956634961cSJack Morgenstein MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, 8966634961cSJack Morgenstein MLX4_CMD_WRAPPED); 8976634961cSJack Morgenstein if (err) 8986634961cSJack Morgenstein goto out; 8996634961cSJack Morgenstein 9006634961cSJack Morgenstein outbox = mailbox->buf; 9016634961cSJack Morgenstein 9026634961cSJack Morgenstein MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET); 9036634961cSJack Morgenstein *gid_tbl_len = field; 9046634961cSJack Morgenstein 9056634961cSJack Morgenstein MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET); 9066634961cSJack Morgenstein *pkey_tbl_len = field; 9076634961cSJack Morgenstein 9086634961cSJack Morgenstein out: 9096634961cSJack Morgenstein mlx4_free_cmd_mailbox(dev, mailbox); 9106634961cSJack Morgenstein return err; 9116634961cSJack Morgenstein } 9126634961cSJack Morgenstein EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len); 9136634961cSJack Morgenstein 9145a2cc190SJeff Kirsher int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt) 9155a2cc190SJeff Kirsher { 9165a2cc190SJeff Kirsher struct mlx4_cmd_mailbox *mailbox; 9175a2cc190SJeff Kirsher struct mlx4_icm_iter iter; 9185a2cc190SJeff Kirsher __be64 *pages; 9195a2cc190SJeff Kirsher int lg; 9205a2cc190SJeff Kirsher int nent = 0; 9215a2cc190SJeff Kirsher int i; 9225a2cc190SJeff Kirsher int err = 0; 9235a2cc190SJeff Kirsher int ts = 0, tc = 0; 9245a2cc190SJeff Kirsher 9255a2cc190SJeff Kirsher mailbox = mlx4_alloc_cmd_mailbox(dev); 9265a2cc190SJeff Kirsher if (IS_ERR(mailbox)) 9275a2cc190SJeff Kirsher return PTR_ERR(mailbox); 9285a2cc190SJeff Kirsher memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE); 9295a2cc190SJeff Kirsher pages = mailbox->buf; 9305a2cc190SJeff Kirsher 9315a2cc190SJeff Kirsher for (mlx4_icm_first(icm, &iter); 9325a2cc190SJeff Kirsher !mlx4_icm_last(&iter); 9335a2cc190SJeff Kirsher mlx4_icm_next(&iter)) { 9345a2cc190SJeff Kirsher /* 9355a2cc190SJeff Kirsher * We have to pass pages that are aligned to their 9365a2cc190SJeff Kirsher * size, so find the least significant 1 in the 9375a2cc190SJeff Kirsher * address or size and use that as our log2 size. 9385a2cc190SJeff Kirsher */ 9395a2cc190SJeff Kirsher lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1; 9405a2cc190SJeff Kirsher if (lg < MLX4_ICM_PAGE_SHIFT) { 9415a2cc190SJeff Kirsher mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n", 9425a2cc190SJeff Kirsher MLX4_ICM_PAGE_SIZE, 9435a2cc190SJeff Kirsher (unsigned long long) mlx4_icm_addr(&iter), 9445a2cc190SJeff Kirsher mlx4_icm_size(&iter)); 9455a2cc190SJeff Kirsher err = -EINVAL; 9465a2cc190SJeff Kirsher goto out; 9475a2cc190SJeff Kirsher } 9485a2cc190SJeff Kirsher 9495a2cc190SJeff Kirsher for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) { 9505a2cc190SJeff Kirsher if (virt != -1) { 9515a2cc190SJeff Kirsher pages[nent * 2] = cpu_to_be64(virt); 9525a2cc190SJeff Kirsher virt += 1 << lg; 9535a2cc190SJeff Kirsher } 9545a2cc190SJeff Kirsher 9555a2cc190SJeff Kirsher pages[nent * 2 + 1] = 9565a2cc190SJeff Kirsher cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) | 9575a2cc190SJeff Kirsher (lg - MLX4_ICM_PAGE_SHIFT)); 9585a2cc190SJeff Kirsher ts += 1 << (lg - 10); 9595a2cc190SJeff Kirsher ++tc; 9605a2cc190SJeff Kirsher 9615a2cc190SJeff Kirsher if (++nent == MLX4_MAILBOX_SIZE / 16) { 9625a2cc190SJeff Kirsher err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, 963f9baff50SJack Morgenstein MLX4_CMD_TIME_CLASS_B, 964f9baff50SJack Morgenstein MLX4_CMD_NATIVE); 9655a2cc190SJeff Kirsher if (err) 9665a2cc190SJeff Kirsher goto out; 9675a2cc190SJeff Kirsher nent = 0; 9685a2cc190SJeff Kirsher } 9695a2cc190SJeff Kirsher } 9705a2cc190SJeff Kirsher } 9715a2cc190SJeff Kirsher 9725a2cc190SJeff Kirsher if (nent) 973f9baff50SJack Morgenstein err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, 974f9baff50SJack Morgenstein MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 9755a2cc190SJeff Kirsher if (err) 9765a2cc190SJeff Kirsher goto out; 9775a2cc190SJeff Kirsher 9785a2cc190SJeff Kirsher switch (op) { 9795a2cc190SJeff Kirsher case MLX4_CMD_MAP_FA: 9805a2cc190SJeff Kirsher mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts); 9815a2cc190SJeff Kirsher break; 9825a2cc190SJeff Kirsher case MLX4_CMD_MAP_ICM_AUX: 9835a2cc190SJeff Kirsher mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts); 9845a2cc190SJeff Kirsher break; 9855a2cc190SJeff Kirsher case MLX4_CMD_MAP_ICM: 9865a2cc190SJeff Kirsher mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n", 9875a2cc190SJeff Kirsher tc, ts, (unsigned long long) virt - (ts << 10)); 9885a2cc190SJeff Kirsher break; 9895a2cc190SJeff Kirsher } 9905a2cc190SJeff Kirsher 9915a2cc190SJeff Kirsher out: 9925a2cc190SJeff Kirsher mlx4_free_cmd_mailbox(dev, mailbox); 9935a2cc190SJeff Kirsher return err; 9945a2cc190SJeff Kirsher } 9955a2cc190SJeff Kirsher 9965a2cc190SJeff Kirsher int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm) 9975a2cc190SJeff Kirsher { 9985a2cc190SJeff Kirsher return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1); 9995a2cc190SJeff Kirsher } 10005a2cc190SJeff Kirsher 10015a2cc190SJeff Kirsher int mlx4_UNMAP_FA(struct mlx4_dev *dev) 10025a2cc190SJeff Kirsher { 1003f9baff50SJack Morgenstein return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA, 1004f9baff50SJack Morgenstein MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 10055a2cc190SJeff Kirsher } 10065a2cc190SJeff Kirsher 10075a2cc190SJeff Kirsher 10085a2cc190SJeff Kirsher int mlx4_RUN_FW(struct mlx4_dev *dev) 10095a2cc190SJeff Kirsher { 1010f9baff50SJack Morgenstein return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW, 1011f9baff50SJack Morgenstein MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 10125a2cc190SJeff Kirsher } 10135a2cc190SJeff Kirsher 10145a2cc190SJeff Kirsher int mlx4_QUERY_FW(struct mlx4_dev *dev) 10155a2cc190SJeff Kirsher { 10165a2cc190SJeff Kirsher struct mlx4_fw *fw = &mlx4_priv(dev)->fw; 10175a2cc190SJeff Kirsher struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd; 10185a2cc190SJeff Kirsher struct mlx4_cmd_mailbox *mailbox; 10195a2cc190SJeff Kirsher u32 *outbox; 10205a2cc190SJeff Kirsher int err = 0; 10215a2cc190SJeff Kirsher u64 fw_ver; 10225a2cc190SJeff Kirsher u16 cmd_if_rev; 10235a2cc190SJeff Kirsher u8 lg; 10245a2cc190SJeff Kirsher 10255a2cc190SJeff Kirsher #define QUERY_FW_OUT_SIZE 0x100 10265a2cc190SJeff Kirsher #define QUERY_FW_VER_OFFSET 0x00 10275cc914f1SMarcel Apfelbaum #define QUERY_FW_PPF_ID 0x09 10285a2cc190SJeff Kirsher #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a 10295a2cc190SJeff Kirsher #define QUERY_FW_MAX_CMD_OFFSET 0x0f 10305a2cc190SJeff Kirsher #define QUERY_FW_ERR_START_OFFSET 0x30 10315a2cc190SJeff Kirsher #define QUERY_FW_ERR_SIZE_OFFSET 0x38 10325a2cc190SJeff Kirsher #define QUERY_FW_ERR_BAR_OFFSET 0x3c 10335a2cc190SJeff Kirsher 10345a2cc190SJeff Kirsher #define QUERY_FW_SIZE_OFFSET 0x00 10355a2cc190SJeff Kirsher #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20 10365a2cc190SJeff Kirsher #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28 10375a2cc190SJeff Kirsher 10385cc914f1SMarcel Apfelbaum #define QUERY_FW_COMM_BASE_OFFSET 0x40 10395cc914f1SMarcel Apfelbaum #define QUERY_FW_COMM_BAR_OFFSET 0x48 10405cc914f1SMarcel Apfelbaum 1041ddd8a6c1SEugenia Emantayev #define QUERY_FW_CLOCK_OFFSET 0x50 1042ddd8a6c1SEugenia Emantayev #define QUERY_FW_CLOCK_BAR 0x58 1043ddd8a6c1SEugenia Emantayev 10445a2cc190SJeff Kirsher mailbox = mlx4_alloc_cmd_mailbox(dev); 10455a2cc190SJeff Kirsher if (IS_ERR(mailbox)) 10465a2cc190SJeff Kirsher return PTR_ERR(mailbox); 10475a2cc190SJeff Kirsher outbox = mailbox->buf; 10485a2cc190SJeff Kirsher 10495a2cc190SJeff Kirsher err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW, 1050f9baff50SJack Morgenstein MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 10515a2cc190SJeff Kirsher if (err) 10525a2cc190SJeff Kirsher goto out; 10535a2cc190SJeff Kirsher 10545a2cc190SJeff Kirsher MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET); 10555a2cc190SJeff Kirsher /* 10565a2cc190SJeff Kirsher * FW subminor version is at more significant bits than minor 10575a2cc190SJeff Kirsher * version, so swap here. 10585a2cc190SJeff Kirsher */ 10595a2cc190SJeff Kirsher dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) | 10605a2cc190SJeff Kirsher ((fw_ver & 0xffff0000ull) >> 16) | 10615a2cc190SJeff Kirsher ((fw_ver & 0x0000ffffull) << 16); 10625a2cc190SJeff Kirsher 1063752a50caSJack Morgenstein MLX4_GET(lg, outbox, QUERY_FW_PPF_ID); 1064752a50caSJack Morgenstein dev->caps.function = lg; 1065752a50caSJack Morgenstein 1066b91cb3ebSJack Morgenstein if (mlx4_is_slave(dev)) 1067b91cb3ebSJack Morgenstein goto out; 1068b91cb3ebSJack Morgenstein 10695cc914f1SMarcel Apfelbaum 10705a2cc190SJeff Kirsher MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET); 10715a2cc190SJeff Kirsher if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV || 10725a2cc190SJeff Kirsher cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) { 10735a2cc190SJeff Kirsher mlx4_err(dev, "Installed FW has unsupported " 10745a2cc190SJeff Kirsher "command interface revision %d.\n", 10755a2cc190SJeff Kirsher cmd_if_rev); 10765a2cc190SJeff Kirsher mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n", 10775a2cc190SJeff Kirsher (int) (dev->caps.fw_ver >> 32), 10785a2cc190SJeff Kirsher (int) (dev->caps.fw_ver >> 16) & 0xffff, 10795a2cc190SJeff Kirsher (int) dev->caps.fw_ver & 0xffff); 10805a2cc190SJeff Kirsher mlx4_err(dev, "This driver version supports only revisions %d to %d.\n", 10815a2cc190SJeff Kirsher MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV); 10825a2cc190SJeff Kirsher err = -ENODEV; 10835a2cc190SJeff Kirsher goto out; 10845a2cc190SJeff Kirsher } 10855a2cc190SJeff Kirsher 10865a2cc190SJeff Kirsher if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS) 10875a2cc190SJeff Kirsher dev->flags |= MLX4_FLAG_OLD_PORT_CMDS; 10885a2cc190SJeff Kirsher 10895a2cc190SJeff Kirsher MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET); 10905a2cc190SJeff Kirsher cmd->max_cmds = 1 << lg; 10915a2cc190SJeff Kirsher 10925a2cc190SJeff Kirsher mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n", 10935a2cc190SJeff Kirsher (int) (dev->caps.fw_ver >> 32), 10945a2cc190SJeff Kirsher (int) (dev->caps.fw_ver >> 16) & 0xffff, 10955a2cc190SJeff Kirsher (int) dev->caps.fw_ver & 0xffff, 10965a2cc190SJeff Kirsher cmd_if_rev, cmd->max_cmds); 10975a2cc190SJeff Kirsher 10985a2cc190SJeff Kirsher MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET); 10995a2cc190SJeff Kirsher MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET); 11005a2cc190SJeff Kirsher MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET); 11015a2cc190SJeff Kirsher fw->catas_bar = (fw->catas_bar >> 6) * 2; 11025a2cc190SJeff Kirsher 11035a2cc190SJeff Kirsher mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n", 11045a2cc190SJeff Kirsher (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar); 11055a2cc190SJeff Kirsher 11065a2cc190SJeff Kirsher MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET); 11075a2cc190SJeff Kirsher MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET); 11085a2cc190SJeff Kirsher MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET); 11095a2cc190SJeff Kirsher fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2; 11105a2cc190SJeff Kirsher 11115cc914f1SMarcel Apfelbaum MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET); 11125cc914f1SMarcel Apfelbaum MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET); 11135cc914f1SMarcel Apfelbaum fw->comm_bar = (fw->comm_bar >> 6) * 2; 11145cc914f1SMarcel Apfelbaum mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n", 11155cc914f1SMarcel Apfelbaum fw->comm_bar, fw->comm_base); 11165a2cc190SJeff Kirsher mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2); 11175a2cc190SJeff Kirsher 1118ddd8a6c1SEugenia Emantayev MLX4_GET(fw->clock_offset, outbox, QUERY_FW_CLOCK_OFFSET); 1119ddd8a6c1SEugenia Emantayev MLX4_GET(fw->clock_bar, outbox, QUERY_FW_CLOCK_BAR); 1120ddd8a6c1SEugenia Emantayev fw->clock_bar = (fw->clock_bar >> 6) * 2; 1121ddd8a6c1SEugenia Emantayev mlx4_dbg(dev, "Internal clock bar:%d offset:0x%llx\n", 1122ddd8a6c1SEugenia Emantayev fw->clock_bar, fw->clock_offset); 1123ddd8a6c1SEugenia Emantayev 11245a2cc190SJeff Kirsher /* 11255a2cc190SJeff Kirsher * Round up number of system pages needed in case 11265a2cc190SJeff Kirsher * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. 11275a2cc190SJeff Kirsher */ 11285a2cc190SJeff Kirsher fw->fw_pages = 11295a2cc190SJeff Kirsher ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> 11305a2cc190SJeff Kirsher (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); 11315a2cc190SJeff Kirsher 11325a2cc190SJeff Kirsher mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n", 11335a2cc190SJeff Kirsher (unsigned long long) fw->clr_int_base, fw->clr_int_bar); 11345a2cc190SJeff Kirsher 11355a2cc190SJeff Kirsher out: 11365a2cc190SJeff Kirsher mlx4_free_cmd_mailbox(dev, mailbox); 11375a2cc190SJeff Kirsher return err; 11385a2cc190SJeff Kirsher } 11395a2cc190SJeff Kirsher 1140b91cb3ebSJack Morgenstein int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave, 1141b91cb3ebSJack Morgenstein struct mlx4_vhcr *vhcr, 1142b91cb3ebSJack Morgenstein struct mlx4_cmd_mailbox *inbox, 1143b91cb3ebSJack Morgenstein struct mlx4_cmd_mailbox *outbox, 1144b91cb3ebSJack Morgenstein struct mlx4_cmd_info *cmd) 1145b91cb3ebSJack Morgenstein { 1146b91cb3ebSJack Morgenstein u8 *outbuf; 1147b91cb3ebSJack Morgenstein int err; 1148b91cb3ebSJack Morgenstein 1149b91cb3ebSJack Morgenstein outbuf = outbox->buf; 1150b91cb3ebSJack Morgenstein err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW, 1151b91cb3ebSJack Morgenstein MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1152b91cb3ebSJack Morgenstein if (err) 1153b91cb3ebSJack Morgenstein return err; 1154b91cb3ebSJack Morgenstein 1155752a50caSJack Morgenstein /* for slaves, set pci PPF ID to invalid and zero out everything 1156752a50caSJack Morgenstein * else except FW version */ 1157b91cb3ebSJack Morgenstein outbuf[0] = outbuf[1] = 0; 1158b91cb3ebSJack Morgenstein memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8); 1159752a50caSJack Morgenstein outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID; 1160752a50caSJack Morgenstein 1161b91cb3ebSJack Morgenstein return 0; 1162b91cb3ebSJack Morgenstein } 1163b91cb3ebSJack Morgenstein 11645a2cc190SJeff Kirsher static void get_board_id(void *vsd, char *board_id) 11655a2cc190SJeff Kirsher { 11665a2cc190SJeff Kirsher int i; 11675a2cc190SJeff Kirsher 11685a2cc190SJeff Kirsher #define VSD_OFFSET_SIG1 0x00 11695a2cc190SJeff Kirsher #define VSD_OFFSET_SIG2 0xde 11705a2cc190SJeff Kirsher #define VSD_OFFSET_MLX_BOARD_ID 0xd0 11715a2cc190SJeff Kirsher #define VSD_OFFSET_TS_BOARD_ID 0x20 11725a2cc190SJeff Kirsher 11735a2cc190SJeff Kirsher #define VSD_SIGNATURE_TOPSPIN 0x5ad 11745a2cc190SJeff Kirsher 11755a2cc190SJeff Kirsher memset(board_id, 0, MLX4_BOARD_ID_LEN); 11765a2cc190SJeff Kirsher 11775a2cc190SJeff Kirsher if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN && 11785a2cc190SJeff Kirsher be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) { 11795a2cc190SJeff Kirsher strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN); 11805a2cc190SJeff Kirsher } else { 11815a2cc190SJeff Kirsher /* 11825a2cc190SJeff Kirsher * The board ID is a string but the firmware byte 11835a2cc190SJeff Kirsher * swaps each 4-byte word before passing it back to 11845a2cc190SJeff Kirsher * us. Therefore we need to swab it before printing. 11855a2cc190SJeff Kirsher */ 11865a2cc190SJeff Kirsher for (i = 0; i < 4; ++i) 11875a2cc190SJeff Kirsher ((u32 *) board_id)[i] = 11885a2cc190SJeff Kirsher swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4)); 11895a2cc190SJeff Kirsher } 11905a2cc190SJeff Kirsher } 11915a2cc190SJeff Kirsher 11925a2cc190SJeff Kirsher int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter) 11935a2cc190SJeff Kirsher { 11945a2cc190SJeff Kirsher struct mlx4_cmd_mailbox *mailbox; 11955a2cc190SJeff Kirsher u32 *outbox; 11965a2cc190SJeff Kirsher int err; 11975a2cc190SJeff Kirsher 11985a2cc190SJeff Kirsher #define QUERY_ADAPTER_OUT_SIZE 0x100 11995a2cc190SJeff Kirsher #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10 12005a2cc190SJeff Kirsher #define QUERY_ADAPTER_VSD_OFFSET 0x20 12015a2cc190SJeff Kirsher 12025a2cc190SJeff Kirsher mailbox = mlx4_alloc_cmd_mailbox(dev); 12035a2cc190SJeff Kirsher if (IS_ERR(mailbox)) 12045a2cc190SJeff Kirsher return PTR_ERR(mailbox); 12055a2cc190SJeff Kirsher outbox = mailbox->buf; 12065a2cc190SJeff Kirsher 12075a2cc190SJeff Kirsher err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER, 1208f9baff50SJack Morgenstein MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 12095a2cc190SJeff Kirsher if (err) 12105a2cc190SJeff Kirsher goto out; 12115a2cc190SJeff Kirsher 12125a2cc190SJeff Kirsher MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET); 12135a2cc190SJeff Kirsher 12145a2cc190SJeff Kirsher get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4, 12155a2cc190SJeff Kirsher adapter->board_id); 12165a2cc190SJeff Kirsher 12175a2cc190SJeff Kirsher out: 12185a2cc190SJeff Kirsher mlx4_free_cmd_mailbox(dev, mailbox); 12195a2cc190SJeff Kirsher return err; 12205a2cc190SJeff Kirsher } 12215a2cc190SJeff Kirsher 12225a2cc190SJeff Kirsher int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param) 12235a2cc190SJeff Kirsher { 12245a2cc190SJeff Kirsher struct mlx4_cmd_mailbox *mailbox; 12255a2cc190SJeff Kirsher __be32 *inbox; 12265a2cc190SJeff Kirsher int err; 12275a2cc190SJeff Kirsher 12285a2cc190SJeff Kirsher #define INIT_HCA_IN_SIZE 0x200 12295a2cc190SJeff Kirsher #define INIT_HCA_VERSION_OFFSET 0x000 12305a2cc190SJeff Kirsher #define INIT_HCA_VERSION 2 12315a2cc190SJeff Kirsher #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e 12325a2cc190SJeff Kirsher #define INIT_HCA_FLAGS_OFFSET 0x014 12335a2cc190SJeff Kirsher #define INIT_HCA_QPC_OFFSET 0x020 12345a2cc190SJeff Kirsher #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10) 12355a2cc190SJeff Kirsher #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17) 12365a2cc190SJeff Kirsher #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28) 12375a2cc190SJeff Kirsher #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f) 12385a2cc190SJeff Kirsher #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30) 12395a2cc190SJeff Kirsher #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37) 12405cc914f1SMarcel Apfelbaum #define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38) 12415a2cc190SJeff Kirsher #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40) 12425a2cc190SJeff Kirsher #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50) 12435a2cc190SJeff Kirsher #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60) 12445a2cc190SJeff Kirsher #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67) 12455a2cc190SJeff Kirsher #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70) 12465a2cc190SJeff Kirsher #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77) 12475a2cc190SJeff Kirsher #define INIT_HCA_MCAST_OFFSET 0x0c0 12485a2cc190SJeff Kirsher #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00) 12495a2cc190SJeff Kirsher #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12) 12505a2cc190SJeff Kirsher #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16) 12515a2cc190SJeff Kirsher #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18) 12525a2cc190SJeff Kirsher #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b) 12530ff1fb65SHadar Hen Zion #define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6 12540ff1fb65SHadar Hen Zion #define INIT_HCA_FS_PARAM_OFFSET 0x1d0 12550ff1fb65SHadar Hen Zion #define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00) 12560ff1fb65SHadar Hen Zion #define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12) 12570ff1fb65SHadar Hen Zion #define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b) 12580ff1fb65SHadar Hen Zion #define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21) 12590ff1fb65SHadar Hen Zion #define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22) 12600ff1fb65SHadar Hen Zion #define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25) 12610ff1fb65SHadar Hen Zion #define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26) 12625a2cc190SJeff Kirsher #define INIT_HCA_TPT_OFFSET 0x0f0 12635a2cc190SJeff Kirsher #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00) 1264e448834eSShani Michaeli #define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08) 12655a2cc190SJeff Kirsher #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b) 12665a2cc190SJeff Kirsher #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10) 12675a2cc190SJeff Kirsher #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18) 12685a2cc190SJeff Kirsher #define INIT_HCA_UAR_OFFSET 0x120 12695a2cc190SJeff Kirsher #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a) 12705a2cc190SJeff Kirsher #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b) 12715a2cc190SJeff Kirsher 12725a2cc190SJeff Kirsher mailbox = mlx4_alloc_cmd_mailbox(dev); 12735a2cc190SJeff Kirsher if (IS_ERR(mailbox)) 12745a2cc190SJeff Kirsher return PTR_ERR(mailbox); 12755a2cc190SJeff Kirsher inbox = mailbox->buf; 12765a2cc190SJeff Kirsher 12775a2cc190SJeff Kirsher memset(inbox, 0, INIT_HCA_IN_SIZE); 12785a2cc190SJeff Kirsher 12795a2cc190SJeff Kirsher *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION; 12805a2cc190SJeff Kirsher 12815a2cc190SJeff Kirsher *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) = 12825a2cc190SJeff Kirsher (ilog2(cache_line_size()) - 4) << 5; 12835a2cc190SJeff Kirsher 12845a2cc190SJeff Kirsher #if defined(__LITTLE_ENDIAN) 12855a2cc190SJeff Kirsher *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1); 12865a2cc190SJeff Kirsher #elif defined(__BIG_ENDIAN) 12875a2cc190SJeff Kirsher *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1); 12885a2cc190SJeff Kirsher #else 12895a2cc190SJeff Kirsher #error Host endianness not defined 12905a2cc190SJeff Kirsher #endif 12915a2cc190SJeff Kirsher /* Check port for UD address vector: */ 12925a2cc190SJeff Kirsher *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1); 12935a2cc190SJeff Kirsher 12945a2cc190SJeff Kirsher /* Enable IPoIB checksumming if we can: */ 12955a2cc190SJeff Kirsher if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM) 12965a2cc190SJeff Kirsher *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3); 12975a2cc190SJeff Kirsher 12985a2cc190SJeff Kirsher /* Enable QoS support if module parameter set */ 12995a2cc190SJeff Kirsher if (enable_qos) 13005a2cc190SJeff Kirsher *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2); 13015a2cc190SJeff Kirsher 13025a2cc190SJeff Kirsher /* enable counters */ 13035a2cc190SJeff Kirsher if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS) 13045a2cc190SJeff Kirsher *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4); 13055a2cc190SJeff Kirsher 130608ff3235SOr Gerlitz /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */ 130708ff3235SOr Gerlitz if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) { 130808ff3235SOr Gerlitz *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29); 130908ff3235SOr Gerlitz dev->caps.eqe_size = 64; 131008ff3235SOr Gerlitz dev->caps.eqe_factor = 1; 131108ff3235SOr Gerlitz } else { 131208ff3235SOr Gerlitz dev->caps.eqe_size = 32; 131308ff3235SOr Gerlitz dev->caps.eqe_factor = 0; 131408ff3235SOr Gerlitz } 131508ff3235SOr Gerlitz 131608ff3235SOr Gerlitz if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) { 131708ff3235SOr Gerlitz *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30); 131808ff3235SOr Gerlitz dev->caps.cqe_size = 64; 131908ff3235SOr Gerlitz dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_64B_CQE; 132008ff3235SOr Gerlitz } else { 132108ff3235SOr Gerlitz dev->caps.cqe_size = 32; 132208ff3235SOr Gerlitz } 132308ff3235SOr Gerlitz 13245a2cc190SJeff Kirsher /* QPC/EEC/CQC/EQC/RDMARC attributes */ 13255a2cc190SJeff Kirsher 13265a2cc190SJeff Kirsher MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET); 13275a2cc190SJeff Kirsher MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET); 13285a2cc190SJeff Kirsher MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET); 13295a2cc190SJeff Kirsher MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET); 13305a2cc190SJeff Kirsher MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET); 13315a2cc190SJeff Kirsher MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET); 13325a2cc190SJeff Kirsher MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET); 13335a2cc190SJeff Kirsher MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET); 13345a2cc190SJeff Kirsher MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET); 13355a2cc190SJeff Kirsher MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET); 13365a2cc190SJeff Kirsher MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET); 13375a2cc190SJeff Kirsher MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET); 13385a2cc190SJeff Kirsher 13390ff1fb65SHadar Hen Zion /* steering attributes */ 13400ff1fb65SHadar Hen Zion if (dev->caps.steering_mode == 13410ff1fb65SHadar Hen Zion MLX4_STEERING_MODE_DEVICE_MANAGED) { 13420ff1fb65SHadar Hen Zion *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= 13430ff1fb65SHadar Hen Zion cpu_to_be32(1 << 13440ff1fb65SHadar Hen Zion INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN); 13455a2cc190SJeff Kirsher 13460ff1fb65SHadar Hen Zion MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET); 13470ff1fb65SHadar Hen Zion MLX4_PUT(inbox, param->log_mc_entry_sz, 13480ff1fb65SHadar Hen Zion INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET); 13490ff1fb65SHadar Hen Zion MLX4_PUT(inbox, param->log_mc_table_sz, 13500ff1fb65SHadar Hen Zion INIT_HCA_FS_LOG_TABLE_SZ_OFFSET); 13510ff1fb65SHadar Hen Zion /* Enable Ethernet flow steering 13520ff1fb65SHadar Hen Zion * with udp unicast and tcp unicast 13530ff1fb65SHadar Hen Zion */ 135423537b73SHadar Hen Zion MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN), 13550ff1fb65SHadar Hen Zion INIT_HCA_FS_ETH_BITS_OFFSET); 13560ff1fb65SHadar Hen Zion MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR, 13570ff1fb65SHadar Hen Zion INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET); 13580ff1fb65SHadar Hen Zion /* Enable IPoIB flow steering 13590ff1fb65SHadar Hen Zion * with udp unicast and tcp unicast 13600ff1fb65SHadar Hen Zion */ 136123537b73SHadar Hen Zion MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN), 13620ff1fb65SHadar Hen Zion INIT_HCA_FS_IB_BITS_OFFSET); 13630ff1fb65SHadar Hen Zion MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR, 13640ff1fb65SHadar Hen Zion INIT_HCA_FS_IB_NUM_ADDRS_OFFSET); 13650ff1fb65SHadar Hen Zion } else { 13665a2cc190SJeff Kirsher MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET); 13670ff1fb65SHadar Hen Zion MLX4_PUT(inbox, param->log_mc_entry_sz, 13680ff1fb65SHadar Hen Zion INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); 13690ff1fb65SHadar Hen Zion MLX4_PUT(inbox, param->log_mc_hash_sz, 13700ff1fb65SHadar Hen Zion INIT_HCA_LOG_MC_HASH_SZ_OFFSET); 13710ff1fb65SHadar Hen Zion MLX4_PUT(inbox, param->log_mc_table_sz, 13720ff1fb65SHadar Hen Zion INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); 1373c96d97f4SHadar Hen Zion if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0) 13740ff1fb65SHadar Hen Zion MLX4_PUT(inbox, (u8) (1 << 3), 13750ff1fb65SHadar Hen Zion INIT_HCA_UC_STEERING_OFFSET); 13760ff1fb65SHadar Hen Zion } 13775a2cc190SJeff Kirsher 13785a2cc190SJeff Kirsher /* TPT attributes */ 13795a2cc190SJeff Kirsher 13805a2cc190SJeff Kirsher MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET); 1381e448834eSShani Michaeli MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET); 13825a2cc190SJeff Kirsher MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET); 13835a2cc190SJeff Kirsher MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET); 13845a2cc190SJeff Kirsher MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET); 13855a2cc190SJeff Kirsher 13865a2cc190SJeff Kirsher /* UAR attributes */ 13875a2cc190SJeff Kirsher 1388ab9c17a0SJack Morgenstein MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET); 13895a2cc190SJeff Kirsher MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET); 13905a2cc190SJeff Kirsher 1391f9baff50SJack Morgenstein err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000, 1392f9baff50SJack Morgenstein MLX4_CMD_NATIVE); 13935a2cc190SJeff Kirsher 13945a2cc190SJeff Kirsher if (err) 13955a2cc190SJeff Kirsher mlx4_err(dev, "INIT_HCA returns %d\n", err); 13965a2cc190SJeff Kirsher 13975a2cc190SJeff Kirsher mlx4_free_cmd_mailbox(dev, mailbox); 13985a2cc190SJeff Kirsher return err; 13995a2cc190SJeff Kirsher } 14005a2cc190SJeff Kirsher 1401ab9c17a0SJack Morgenstein int mlx4_QUERY_HCA(struct mlx4_dev *dev, 1402ab9c17a0SJack Morgenstein struct mlx4_init_hca_param *param) 1403ab9c17a0SJack Morgenstein { 1404ab9c17a0SJack Morgenstein struct mlx4_cmd_mailbox *mailbox; 1405ab9c17a0SJack Morgenstein __be32 *outbox; 14067b8157beSJack Morgenstein u32 dword_field; 1407ab9c17a0SJack Morgenstein int err; 140808ff3235SOr Gerlitz u8 byte_field; 1409ab9c17a0SJack Morgenstein 1410ab9c17a0SJack Morgenstein #define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04 1411ddd8a6c1SEugenia Emantayev #define QUERY_HCA_CORE_CLOCK_OFFSET 0x0c 1412ab9c17a0SJack Morgenstein 1413ab9c17a0SJack Morgenstein mailbox = mlx4_alloc_cmd_mailbox(dev); 1414ab9c17a0SJack Morgenstein if (IS_ERR(mailbox)) 1415ab9c17a0SJack Morgenstein return PTR_ERR(mailbox); 1416ab9c17a0SJack Morgenstein outbox = mailbox->buf; 1417ab9c17a0SJack Morgenstein 1418ab9c17a0SJack Morgenstein err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, 1419ab9c17a0SJack Morgenstein MLX4_CMD_QUERY_HCA, 1420ab9c17a0SJack Morgenstein MLX4_CMD_TIME_CLASS_B, 1421ab9c17a0SJack Morgenstein !mlx4_is_slave(dev)); 1422ab9c17a0SJack Morgenstein if (err) 1423ab9c17a0SJack Morgenstein goto out; 1424ab9c17a0SJack Morgenstein 1425ab9c17a0SJack Morgenstein MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET); 1426ddd8a6c1SEugenia Emantayev MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET); 1427ab9c17a0SJack Morgenstein 1428ab9c17a0SJack Morgenstein /* QPC/EEC/CQC/EQC/RDMARC attributes */ 1429ab9c17a0SJack Morgenstein 1430ab9c17a0SJack Morgenstein MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET); 1431ab9c17a0SJack Morgenstein MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET); 1432ab9c17a0SJack Morgenstein MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET); 1433ab9c17a0SJack Morgenstein MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET); 1434ab9c17a0SJack Morgenstein MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET); 1435ab9c17a0SJack Morgenstein MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET); 1436ab9c17a0SJack Morgenstein MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET); 1437ab9c17a0SJack Morgenstein MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET); 1438ab9c17a0SJack Morgenstein MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET); 1439ab9c17a0SJack Morgenstein MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET); 1440ab9c17a0SJack Morgenstein MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET); 1441ab9c17a0SJack Morgenstein MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET); 1442ab9c17a0SJack Morgenstein 14437b8157beSJack Morgenstein MLX4_GET(dword_field, outbox, INIT_HCA_FLAGS_OFFSET); 14447b8157beSJack Morgenstein if (dword_field & (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN)) { 14457b8157beSJack Morgenstein param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED; 14467b8157beSJack Morgenstein } else { 14477b8157beSJack Morgenstein MLX4_GET(byte_field, outbox, INIT_HCA_UC_STEERING_OFFSET); 14487b8157beSJack Morgenstein if (byte_field & 0x8) 14497b8157beSJack Morgenstein param->steering_mode = MLX4_STEERING_MODE_B0; 14507b8157beSJack Morgenstein else 14517b8157beSJack Morgenstein param->steering_mode = MLX4_STEERING_MODE_A0; 14527b8157beSJack Morgenstein } 14530ff1fb65SHadar Hen Zion /* steering attributes */ 14547b8157beSJack Morgenstein if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) { 14550ff1fb65SHadar Hen Zion MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET); 14560ff1fb65SHadar Hen Zion MLX4_GET(param->log_mc_entry_sz, outbox, 14570ff1fb65SHadar Hen Zion INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET); 14580ff1fb65SHadar Hen Zion MLX4_GET(param->log_mc_table_sz, outbox, 14590ff1fb65SHadar Hen Zion INIT_HCA_FS_LOG_TABLE_SZ_OFFSET); 14600ff1fb65SHadar Hen Zion } else { 1461ab9c17a0SJack Morgenstein MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET); 1462ab9c17a0SJack Morgenstein MLX4_GET(param->log_mc_entry_sz, outbox, 1463ab9c17a0SJack Morgenstein INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); 1464ab9c17a0SJack Morgenstein MLX4_GET(param->log_mc_hash_sz, outbox, 1465ab9c17a0SJack Morgenstein INIT_HCA_LOG_MC_HASH_SZ_OFFSET); 1466ab9c17a0SJack Morgenstein MLX4_GET(param->log_mc_table_sz, outbox, 1467ab9c17a0SJack Morgenstein INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); 14680ff1fb65SHadar Hen Zion } 1469ab9c17a0SJack Morgenstein 147008ff3235SOr Gerlitz /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */ 147108ff3235SOr Gerlitz MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS); 147208ff3235SOr Gerlitz if (byte_field & 0x20) /* 64-bytes eqe enabled */ 147308ff3235SOr Gerlitz param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED; 147408ff3235SOr Gerlitz if (byte_field & 0x40) /* 64-bytes cqe enabled */ 147508ff3235SOr Gerlitz param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED; 147608ff3235SOr Gerlitz 1477ab9c17a0SJack Morgenstein /* TPT attributes */ 1478ab9c17a0SJack Morgenstein 1479ab9c17a0SJack Morgenstein MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET); 1480e448834eSShani Michaeli MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET); 1481ab9c17a0SJack Morgenstein MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET); 1482ab9c17a0SJack Morgenstein MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET); 1483ab9c17a0SJack Morgenstein MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET); 1484ab9c17a0SJack Morgenstein 1485ab9c17a0SJack Morgenstein /* UAR attributes */ 1486ab9c17a0SJack Morgenstein 1487ab9c17a0SJack Morgenstein MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET); 1488ab9c17a0SJack Morgenstein MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET); 1489ab9c17a0SJack Morgenstein 1490ab9c17a0SJack Morgenstein out: 1491ab9c17a0SJack Morgenstein mlx4_free_cmd_mailbox(dev, mailbox); 1492ab9c17a0SJack Morgenstein 1493ab9c17a0SJack Morgenstein return err; 1494ab9c17a0SJack Morgenstein } 1495ab9c17a0SJack Morgenstein 1496980e9001SJack Morgenstein /* for IB-type ports only in SRIOV mode. Checks that both proxy QP0 1497980e9001SJack Morgenstein * and real QP0 are active, so that the paravirtualized QP0 is ready 1498980e9001SJack Morgenstein * to operate */ 1499980e9001SJack Morgenstein static int check_qp0_state(struct mlx4_dev *dev, int function, int port) 1500980e9001SJack Morgenstein { 1501980e9001SJack Morgenstein struct mlx4_priv *priv = mlx4_priv(dev); 1502980e9001SJack Morgenstein /* irrelevant if not infiniband */ 1503980e9001SJack Morgenstein if (priv->mfunc.master.qp0_state[port].proxy_qp0_active && 1504980e9001SJack Morgenstein priv->mfunc.master.qp0_state[port].qp0_active) 1505980e9001SJack Morgenstein return 1; 1506980e9001SJack Morgenstein return 0; 1507980e9001SJack Morgenstein } 1508980e9001SJack Morgenstein 15095cc914f1SMarcel Apfelbaum int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave, 15105cc914f1SMarcel Apfelbaum struct mlx4_vhcr *vhcr, 15115cc914f1SMarcel Apfelbaum struct mlx4_cmd_mailbox *inbox, 15125cc914f1SMarcel Apfelbaum struct mlx4_cmd_mailbox *outbox, 15135cc914f1SMarcel Apfelbaum struct mlx4_cmd_info *cmd) 15145cc914f1SMarcel Apfelbaum { 15155cc914f1SMarcel Apfelbaum struct mlx4_priv *priv = mlx4_priv(dev); 15165cc914f1SMarcel Apfelbaum int port = vhcr->in_modifier; 15175cc914f1SMarcel Apfelbaum int err; 15185cc914f1SMarcel Apfelbaum 15195cc914f1SMarcel Apfelbaum if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port)) 15205cc914f1SMarcel Apfelbaum return 0; 15215cc914f1SMarcel Apfelbaum 1522980e9001SJack Morgenstein if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) { 15235cc914f1SMarcel Apfelbaum /* Enable port only if it was previously disabled */ 15245cc914f1SMarcel Apfelbaum if (!priv->mfunc.master.init_port_ref[port]) { 15255cc914f1SMarcel Apfelbaum err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, 15265cc914f1SMarcel Apfelbaum MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 15275cc914f1SMarcel Apfelbaum if (err) 15285cc914f1SMarcel Apfelbaum return err; 15295cc914f1SMarcel Apfelbaum } 15308bac9edeSJack Morgenstein priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); 1531980e9001SJack Morgenstein } else { 1532980e9001SJack Morgenstein if (slave == mlx4_master_func_num(dev)) { 1533980e9001SJack Morgenstein if (check_qp0_state(dev, slave, port) && 1534980e9001SJack Morgenstein !priv->mfunc.master.qp0_state[port].port_active) { 1535980e9001SJack Morgenstein err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, 1536980e9001SJack Morgenstein MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1537980e9001SJack Morgenstein if (err) 1538980e9001SJack Morgenstein return err; 1539980e9001SJack Morgenstein priv->mfunc.master.qp0_state[port].port_active = 1; 1540980e9001SJack Morgenstein priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); 1541980e9001SJack Morgenstein } 1542980e9001SJack Morgenstein } else 1543980e9001SJack Morgenstein priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); 1544980e9001SJack Morgenstein } 15455cc914f1SMarcel Apfelbaum ++priv->mfunc.master.init_port_ref[port]; 15465cc914f1SMarcel Apfelbaum return 0; 15475cc914f1SMarcel Apfelbaum } 15485cc914f1SMarcel Apfelbaum 15495a2cc190SJeff Kirsher int mlx4_INIT_PORT(struct mlx4_dev *dev, int port) 15505a2cc190SJeff Kirsher { 15515a2cc190SJeff Kirsher struct mlx4_cmd_mailbox *mailbox; 15525a2cc190SJeff Kirsher u32 *inbox; 15535a2cc190SJeff Kirsher int err; 15545a2cc190SJeff Kirsher u32 flags; 15555a2cc190SJeff Kirsher u16 field; 15565a2cc190SJeff Kirsher 15575a2cc190SJeff Kirsher if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { 15585a2cc190SJeff Kirsher #define INIT_PORT_IN_SIZE 256 15595a2cc190SJeff Kirsher #define INIT_PORT_FLAGS_OFFSET 0x00 15605a2cc190SJeff Kirsher #define INIT_PORT_FLAG_SIG (1 << 18) 15615a2cc190SJeff Kirsher #define INIT_PORT_FLAG_NG (1 << 17) 15625a2cc190SJeff Kirsher #define INIT_PORT_FLAG_G0 (1 << 16) 15635a2cc190SJeff Kirsher #define INIT_PORT_VL_SHIFT 4 15645a2cc190SJeff Kirsher #define INIT_PORT_PORT_WIDTH_SHIFT 8 15655a2cc190SJeff Kirsher #define INIT_PORT_MTU_OFFSET 0x04 15665a2cc190SJeff Kirsher #define INIT_PORT_MAX_GID_OFFSET 0x06 15675a2cc190SJeff Kirsher #define INIT_PORT_MAX_PKEY_OFFSET 0x0a 15685a2cc190SJeff Kirsher #define INIT_PORT_GUID0_OFFSET 0x10 15695a2cc190SJeff Kirsher #define INIT_PORT_NODE_GUID_OFFSET 0x18 15705a2cc190SJeff Kirsher #define INIT_PORT_SI_GUID_OFFSET 0x20 15715a2cc190SJeff Kirsher 15725a2cc190SJeff Kirsher mailbox = mlx4_alloc_cmd_mailbox(dev); 15735a2cc190SJeff Kirsher if (IS_ERR(mailbox)) 15745a2cc190SJeff Kirsher return PTR_ERR(mailbox); 15755a2cc190SJeff Kirsher inbox = mailbox->buf; 15765a2cc190SJeff Kirsher 15775a2cc190SJeff Kirsher memset(inbox, 0, INIT_PORT_IN_SIZE); 15785a2cc190SJeff Kirsher 15795a2cc190SJeff Kirsher flags = 0; 15805a2cc190SJeff Kirsher flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT; 15815a2cc190SJeff Kirsher flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT; 15825a2cc190SJeff Kirsher MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET); 15835a2cc190SJeff Kirsher 15845a2cc190SJeff Kirsher field = 128 << dev->caps.ib_mtu_cap[port]; 15855a2cc190SJeff Kirsher MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET); 15865a2cc190SJeff Kirsher field = dev->caps.gid_table_len[port]; 15875a2cc190SJeff Kirsher MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET); 15885a2cc190SJeff Kirsher field = dev->caps.pkey_table_len[port]; 15895a2cc190SJeff Kirsher MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET); 15905a2cc190SJeff Kirsher 15915a2cc190SJeff Kirsher err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT, 1592f9baff50SJack Morgenstein MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 15935a2cc190SJeff Kirsher 15945a2cc190SJeff Kirsher mlx4_free_cmd_mailbox(dev, mailbox); 15955a2cc190SJeff Kirsher } else 15965a2cc190SJeff Kirsher err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, 1597f9baff50SJack Morgenstein MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 15985a2cc190SJeff Kirsher 15995a2cc190SJeff Kirsher return err; 16005a2cc190SJeff Kirsher } 16015a2cc190SJeff Kirsher EXPORT_SYMBOL_GPL(mlx4_INIT_PORT); 16025a2cc190SJeff Kirsher 16035cc914f1SMarcel Apfelbaum int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave, 16045cc914f1SMarcel Apfelbaum struct mlx4_vhcr *vhcr, 16055cc914f1SMarcel Apfelbaum struct mlx4_cmd_mailbox *inbox, 16065cc914f1SMarcel Apfelbaum struct mlx4_cmd_mailbox *outbox, 16075cc914f1SMarcel Apfelbaum struct mlx4_cmd_info *cmd) 16085cc914f1SMarcel Apfelbaum { 16095cc914f1SMarcel Apfelbaum struct mlx4_priv *priv = mlx4_priv(dev); 16105cc914f1SMarcel Apfelbaum int port = vhcr->in_modifier; 16115cc914f1SMarcel Apfelbaum int err; 16125cc914f1SMarcel Apfelbaum 16135cc914f1SMarcel Apfelbaum if (!(priv->mfunc.master.slave_state[slave].init_port_mask & 16145cc914f1SMarcel Apfelbaum (1 << port))) 16155cc914f1SMarcel Apfelbaum return 0; 16165cc914f1SMarcel Apfelbaum 1617980e9001SJack Morgenstein if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) { 16185cc914f1SMarcel Apfelbaum if (priv->mfunc.master.init_port_ref[port] == 1) { 1619980e9001SJack Morgenstein err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1620980e9001SJack Morgenstein 1000, MLX4_CMD_NATIVE); 16215cc914f1SMarcel Apfelbaum if (err) 16225cc914f1SMarcel Apfelbaum return err; 16235cc914f1SMarcel Apfelbaum } 16245cc914f1SMarcel Apfelbaum priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); 1625980e9001SJack Morgenstein } else { 1626980e9001SJack Morgenstein /* infiniband port */ 1627980e9001SJack Morgenstein if (slave == mlx4_master_func_num(dev)) { 1628980e9001SJack Morgenstein if (!priv->mfunc.master.qp0_state[port].qp0_active && 1629980e9001SJack Morgenstein priv->mfunc.master.qp0_state[port].port_active) { 1630980e9001SJack Morgenstein err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1631980e9001SJack Morgenstein 1000, MLX4_CMD_NATIVE); 1632980e9001SJack Morgenstein if (err) 1633980e9001SJack Morgenstein return err; 1634980e9001SJack Morgenstein priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); 1635980e9001SJack Morgenstein priv->mfunc.master.qp0_state[port].port_active = 0; 1636980e9001SJack Morgenstein } 1637980e9001SJack Morgenstein } else 1638980e9001SJack Morgenstein priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); 1639980e9001SJack Morgenstein } 16405cc914f1SMarcel Apfelbaum --priv->mfunc.master.init_port_ref[port]; 16415cc914f1SMarcel Apfelbaum return 0; 16425cc914f1SMarcel Apfelbaum } 16435cc914f1SMarcel Apfelbaum 16445a2cc190SJeff Kirsher int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port) 16455a2cc190SJeff Kirsher { 1646f9baff50SJack Morgenstein return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000, 1647f9baff50SJack Morgenstein MLX4_CMD_WRAPPED); 16485a2cc190SJeff Kirsher } 16495a2cc190SJeff Kirsher EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT); 16505a2cc190SJeff Kirsher 16515a2cc190SJeff Kirsher int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic) 16525a2cc190SJeff Kirsher { 1653f9baff50SJack Morgenstein return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000, 1654f9baff50SJack Morgenstein MLX4_CMD_NATIVE); 16555a2cc190SJeff Kirsher } 16565a2cc190SJeff Kirsher 16575a2cc190SJeff Kirsher int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages) 16585a2cc190SJeff Kirsher { 16595a2cc190SJeff Kirsher int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0, 16605a2cc190SJeff Kirsher MLX4_CMD_SET_ICM_SIZE, 1661f9baff50SJack Morgenstein MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 16625a2cc190SJeff Kirsher if (ret) 16635a2cc190SJeff Kirsher return ret; 16645a2cc190SJeff Kirsher 16655a2cc190SJeff Kirsher /* 16665a2cc190SJeff Kirsher * Round up number of system pages needed in case 16675a2cc190SJeff Kirsher * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. 16685a2cc190SJeff Kirsher */ 16695a2cc190SJeff Kirsher *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> 16705a2cc190SJeff Kirsher (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); 16715a2cc190SJeff Kirsher 16725a2cc190SJeff Kirsher return 0; 16735a2cc190SJeff Kirsher } 16745a2cc190SJeff Kirsher 16755a2cc190SJeff Kirsher int mlx4_NOP(struct mlx4_dev *dev) 16765a2cc190SJeff Kirsher { 16775a2cc190SJeff Kirsher /* Input modifier of 0x1f means "finish as soon as possible." */ 1678f9baff50SJack Morgenstein return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100, MLX4_CMD_NATIVE); 16795a2cc190SJeff Kirsher } 16805a2cc190SJeff Kirsher 16815a2cc190SJeff Kirsher #define MLX4_WOL_SETUP_MODE (5 << 28) 16825a2cc190SJeff Kirsher int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port) 16835a2cc190SJeff Kirsher { 16845a2cc190SJeff Kirsher u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8; 16855a2cc190SJeff Kirsher 16865a2cc190SJeff Kirsher return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3, 1687f9baff50SJack Morgenstein MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A, 1688f9baff50SJack Morgenstein MLX4_CMD_NATIVE); 16895a2cc190SJeff Kirsher } 16905a2cc190SJeff Kirsher EXPORT_SYMBOL_GPL(mlx4_wol_read); 16915a2cc190SJeff Kirsher 16925a2cc190SJeff Kirsher int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port) 16935a2cc190SJeff Kirsher { 16945a2cc190SJeff Kirsher u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8; 16955a2cc190SJeff Kirsher 16965a2cc190SJeff Kirsher return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG, 1697f9baff50SJack Morgenstein MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 16985a2cc190SJeff Kirsher } 16995a2cc190SJeff Kirsher EXPORT_SYMBOL_GPL(mlx4_wol_write); 1700fe6f700dSYevgeny Petrilin 1701fe6f700dSYevgeny Petrilin enum { 1702fe6f700dSYevgeny Petrilin ADD_TO_MCG = 0x26, 1703fe6f700dSYevgeny Petrilin }; 1704fe6f700dSYevgeny Petrilin 1705fe6f700dSYevgeny Petrilin 1706fe6f700dSYevgeny Petrilin void mlx4_opreq_action(struct work_struct *work) 1707fe6f700dSYevgeny Petrilin { 1708fe6f700dSYevgeny Petrilin struct mlx4_priv *priv = container_of(work, struct mlx4_priv, 1709fe6f700dSYevgeny Petrilin opreq_task); 1710fe6f700dSYevgeny Petrilin struct mlx4_dev *dev = &priv->dev; 1711fe6f700dSYevgeny Petrilin int num_tasks = atomic_read(&priv->opreq_count); 1712fe6f700dSYevgeny Petrilin struct mlx4_cmd_mailbox *mailbox; 1713fe6f700dSYevgeny Petrilin struct mlx4_mgm *mgm; 1714fe6f700dSYevgeny Petrilin u32 *outbox; 1715fe6f700dSYevgeny Petrilin u32 modifier; 1716fe6f700dSYevgeny Petrilin u16 token; 1717fe6f700dSYevgeny Petrilin u16 type; 1718fe6f700dSYevgeny Petrilin int err; 1719fe6f700dSYevgeny Petrilin u32 num_qps; 1720fe6f700dSYevgeny Petrilin struct mlx4_qp qp; 1721fe6f700dSYevgeny Petrilin int i; 1722fe6f700dSYevgeny Petrilin u8 rem_mcg; 1723fe6f700dSYevgeny Petrilin u8 prot; 1724fe6f700dSYevgeny Petrilin 1725fe6f700dSYevgeny Petrilin #define GET_OP_REQ_MODIFIER_OFFSET 0x08 1726fe6f700dSYevgeny Petrilin #define GET_OP_REQ_TOKEN_OFFSET 0x14 1727fe6f700dSYevgeny Petrilin #define GET_OP_REQ_TYPE_OFFSET 0x1a 1728fe6f700dSYevgeny Petrilin #define GET_OP_REQ_DATA_OFFSET 0x20 1729fe6f700dSYevgeny Petrilin 1730fe6f700dSYevgeny Petrilin mailbox = mlx4_alloc_cmd_mailbox(dev); 1731fe6f700dSYevgeny Petrilin if (IS_ERR(mailbox)) { 1732fe6f700dSYevgeny Petrilin mlx4_err(dev, "Failed to allocate mailbox for GET_OP_REQ\n"); 1733fe6f700dSYevgeny Petrilin return; 1734fe6f700dSYevgeny Petrilin } 1735fe6f700dSYevgeny Petrilin outbox = mailbox->buf; 1736fe6f700dSYevgeny Petrilin 1737fe6f700dSYevgeny Petrilin while (num_tasks) { 1738fe6f700dSYevgeny Petrilin err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, 1739fe6f700dSYevgeny Petrilin MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A, 1740fe6f700dSYevgeny Petrilin MLX4_CMD_NATIVE); 1741fe6f700dSYevgeny Petrilin if (err) { 1742fe6f700dSYevgeny Petrilin mlx4_err(dev, "Failed to retreive required operation: %d\n", 1743fe6f700dSYevgeny Petrilin err); 1744fe6f700dSYevgeny Petrilin return; 1745fe6f700dSYevgeny Petrilin } 1746fe6f700dSYevgeny Petrilin MLX4_GET(modifier, outbox, GET_OP_REQ_MODIFIER_OFFSET); 1747fe6f700dSYevgeny Petrilin MLX4_GET(token, outbox, GET_OP_REQ_TOKEN_OFFSET); 1748fe6f700dSYevgeny Petrilin MLX4_GET(type, outbox, GET_OP_REQ_TYPE_OFFSET); 1749fe6f700dSYevgeny Petrilin type &= 0xfff; 1750fe6f700dSYevgeny Petrilin 1751fe6f700dSYevgeny Petrilin switch (type) { 1752fe6f700dSYevgeny Petrilin case ADD_TO_MCG: 1753fe6f700dSYevgeny Petrilin if (dev->caps.steering_mode == 1754fe6f700dSYevgeny Petrilin MLX4_STEERING_MODE_DEVICE_MANAGED) { 1755fe6f700dSYevgeny Petrilin mlx4_warn(dev, "ADD MCG operation is not supported in DEVICE_MANAGED steering mode\n"); 1756fe6f700dSYevgeny Petrilin err = EPERM; 1757fe6f700dSYevgeny Petrilin break; 1758fe6f700dSYevgeny Petrilin } 1759fe6f700dSYevgeny Petrilin mgm = (struct mlx4_mgm *)((u8 *)(outbox) + 1760fe6f700dSYevgeny Petrilin GET_OP_REQ_DATA_OFFSET); 1761fe6f700dSYevgeny Petrilin num_qps = be32_to_cpu(mgm->members_count) & 1762fe6f700dSYevgeny Petrilin MGM_QPN_MASK; 1763fe6f700dSYevgeny Petrilin rem_mcg = ((u8 *)(&mgm->members_count))[0] & 1; 1764fe6f700dSYevgeny Petrilin prot = ((u8 *)(&mgm->members_count))[0] >> 6; 1765fe6f700dSYevgeny Petrilin 1766fe6f700dSYevgeny Petrilin for (i = 0; i < num_qps; i++) { 1767fe6f700dSYevgeny Petrilin qp.qpn = be32_to_cpu(mgm->qp[i]); 1768fe6f700dSYevgeny Petrilin if (rem_mcg) 1769fe6f700dSYevgeny Petrilin err = mlx4_multicast_detach(dev, &qp, 1770fe6f700dSYevgeny Petrilin mgm->gid, 1771fe6f700dSYevgeny Petrilin prot, 0); 1772fe6f700dSYevgeny Petrilin else 1773fe6f700dSYevgeny Petrilin err = mlx4_multicast_attach(dev, &qp, 1774fe6f700dSYevgeny Petrilin mgm->gid, 1775fe6f700dSYevgeny Petrilin mgm->gid[5] 1776fe6f700dSYevgeny Petrilin , 0, prot, 1777fe6f700dSYevgeny Petrilin NULL); 1778fe6f700dSYevgeny Petrilin if (err) 1779fe6f700dSYevgeny Petrilin break; 1780fe6f700dSYevgeny Petrilin } 1781fe6f700dSYevgeny Petrilin break; 1782fe6f700dSYevgeny Petrilin default: 1783fe6f700dSYevgeny Petrilin mlx4_warn(dev, "Bad type for required operation\n"); 1784fe6f700dSYevgeny Petrilin err = EINVAL; 1785fe6f700dSYevgeny Petrilin break; 1786fe6f700dSYevgeny Petrilin } 1787fe6f700dSYevgeny Petrilin err = mlx4_cmd(dev, 0, ((u32) err | cpu_to_be32(token) << 16), 1788fe6f700dSYevgeny Petrilin 1, MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A, 1789fe6f700dSYevgeny Petrilin MLX4_CMD_NATIVE); 1790fe6f700dSYevgeny Petrilin if (err) { 1791fe6f700dSYevgeny Petrilin mlx4_err(dev, "Failed to acknowledge required request: %d\n", 1792fe6f700dSYevgeny Petrilin err); 1793fe6f700dSYevgeny Petrilin goto out; 1794fe6f700dSYevgeny Petrilin } 1795fe6f700dSYevgeny Petrilin memset(outbox, 0, 0xffc); 1796fe6f700dSYevgeny Petrilin num_tasks = atomic_dec_return(&priv->opreq_count); 1797fe6f700dSYevgeny Petrilin } 1798fe6f700dSYevgeny Petrilin 1799fe6f700dSYevgeny Petrilin out: 1800fe6f700dSYevgeny Petrilin mlx4_free_cmd_mailbox(dev, mailbox); 1801fe6f700dSYevgeny Petrilin } 1802