15a2cc190SJeff Kirsher /* 25a2cc190SJeff Kirsher * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 35a2cc190SJeff Kirsher * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 45a2cc190SJeff Kirsher * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved. 55a2cc190SJeff Kirsher * 65a2cc190SJeff Kirsher * This software is available to you under a choice of one of two 75a2cc190SJeff Kirsher * licenses. You may choose to be licensed under the terms of the GNU 85a2cc190SJeff Kirsher * General Public License (GPL) Version 2, available from the file 95a2cc190SJeff Kirsher * COPYING in the main directory of this source tree, or the 105a2cc190SJeff Kirsher * OpenIB.org BSD license below: 115a2cc190SJeff Kirsher * 125a2cc190SJeff Kirsher * Redistribution and use in source and binary forms, with or 135a2cc190SJeff Kirsher * without modification, are permitted provided that the following 145a2cc190SJeff Kirsher * conditions are met: 155a2cc190SJeff Kirsher * 165a2cc190SJeff Kirsher * - Redistributions of source code must retain the above 175a2cc190SJeff Kirsher * copyright notice, this list of conditions and the following 185a2cc190SJeff Kirsher * disclaimer. 195a2cc190SJeff Kirsher * 205a2cc190SJeff Kirsher * - Redistributions in binary form must reproduce the above 215a2cc190SJeff Kirsher * copyright notice, this list of conditions and the following 225a2cc190SJeff Kirsher * disclaimer in the documentation and/or other materials 235a2cc190SJeff Kirsher * provided with the distribution. 245a2cc190SJeff Kirsher * 255a2cc190SJeff Kirsher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 265a2cc190SJeff Kirsher * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 275a2cc190SJeff Kirsher * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 285a2cc190SJeff Kirsher * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 295a2cc190SJeff Kirsher * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 305a2cc190SJeff Kirsher * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 315a2cc190SJeff Kirsher * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 325a2cc190SJeff Kirsher * SOFTWARE. 335a2cc190SJeff Kirsher */ 345a2cc190SJeff Kirsher 355cc914f1SMarcel Apfelbaum #include <linux/etherdevice.h> 365a2cc190SJeff Kirsher #include <linux/mlx4/cmd.h> 379d9779e7SPaul Gortmaker #include <linux/module.h> 385a2cc190SJeff Kirsher #include <linux/cache.h> 395a2cc190SJeff Kirsher 405a2cc190SJeff Kirsher #include "fw.h" 415a2cc190SJeff Kirsher #include "icm.h" 425a2cc190SJeff Kirsher 435a2cc190SJeff Kirsher enum { 445a2cc190SJeff Kirsher MLX4_COMMAND_INTERFACE_MIN_REV = 2, 455a2cc190SJeff Kirsher MLX4_COMMAND_INTERFACE_MAX_REV = 3, 465a2cc190SJeff Kirsher MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3, 475a2cc190SJeff Kirsher }; 485a2cc190SJeff Kirsher 495a2cc190SJeff Kirsher extern void __buggy_use_of_MLX4_GET(void); 505a2cc190SJeff Kirsher extern void __buggy_use_of_MLX4_PUT(void); 515a2cc190SJeff Kirsher 5238438f7cSIdo Shamay static bool enable_qos = true; 535a2cc190SJeff Kirsher module_param(enable_qos, bool, 0444); 5438438f7cSIdo Shamay MODULE_PARM_DESC(enable_qos, "Enable Enhanced QoS support (default: on)"); 555a2cc190SJeff Kirsher 565a2cc190SJeff Kirsher #define MLX4_GET(dest, source, offset) \ 575a2cc190SJeff Kirsher do { \ 585a2cc190SJeff Kirsher void *__p = (char *) (source) + (offset); \ 595a2cc190SJeff Kirsher switch (sizeof (dest)) { \ 605a2cc190SJeff Kirsher case 1: (dest) = *(u8 *) __p; break; \ 615a2cc190SJeff Kirsher case 2: (dest) = be16_to_cpup(__p); break; \ 625a2cc190SJeff Kirsher case 4: (dest) = be32_to_cpup(__p); break; \ 635a2cc190SJeff Kirsher case 8: (dest) = be64_to_cpup(__p); break; \ 645a2cc190SJeff Kirsher default: __buggy_use_of_MLX4_GET(); \ 655a2cc190SJeff Kirsher } \ 665a2cc190SJeff Kirsher } while (0) 675a2cc190SJeff Kirsher 685a2cc190SJeff Kirsher #define MLX4_PUT(dest, source, offset) \ 695a2cc190SJeff Kirsher do { \ 705a2cc190SJeff Kirsher void *__d = ((char *) (dest) + (offset)); \ 715a2cc190SJeff Kirsher switch (sizeof(source)) { \ 725a2cc190SJeff Kirsher case 1: *(u8 *) __d = (source); break; \ 735a2cc190SJeff Kirsher case 2: *(__be16 *) __d = cpu_to_be16(source); break; \ 745a2cc190SJeff Kirsher case 4: *(__be32 *) __d = cpu_to_be32(source); break; \ 755a2cc190SJeff Kirsher case 8: *(__be64 *) __d = cpu_to_be64(source); break; \ 765a2cc190SJeff Kirsher default: __buggy_use_of_MLX4_PUT(); \ 775a2cc190SJeff Kirsher } \ 785a2cc190SJeff Kirsher } while (0) 795a2cc190SJeff Kirsher 805a2cc190SJeff Kirsher static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags) 815a2cc190SJeff Kirsher { 825a2cc190SJeff Kirsher static const char *fname[] = { 835a2cc190SJeff Kirsher [ 0] = "RC transport", 845a2cc190SJeff Kirsher [ 1] = "UC transport", 855a2cc190SJeff Kirsher [ 2] = "UD transport", 865a2cc190SJeff Kirsher [ 3] = "XRC transport", 875a2cc190SJeff Kirsher [ 6] = "SRQ support", 885a2cc190SJeff Kirsher [ 7] = "IPoIB checksum offload", 895a2cc190SJeff Kirsher [ 8] = "P_Key violation counter", 905a2cc190SJeff Kirsher [ 9] = "Q_Key violation counter", 914d531aa8SOr Gerlitz [12] = "Dual Port Different Protocol (DPDP) support", 925a2cc190SJeff Kirsher [15] = "Big LSO headers", 935a2cc190SJeff Kirsher [16] = "MW support", 945a2cc190SJeff Kirsher [17] = "APM support", 955a2cc190SJeff Kirsher [18] = "Atomic ops support", 965a2cc190SJeff Kirsher [19] = "Raw multicast support", 975a2cc190SJeff Kirsher [20] = "Address vector port checking support", 985a2cc190SJeff Kirsher [21] = "UD multicast support", 995a2cc190SJeff Kirsher [30] = "IBoE support", 1005a2cc190SJeff Kirsher [32] = "Unicast loopback support", 101f3a9d1f2SYevgeny Petrilin [34] = "FCS header control", 102cb2147a9SOr Gerlitz [37] = "Wake On LAN (port1) support", 103cb2147a9SOr Gerlitz [38] = "Wake On LAN (port2) support", 1045a2cc190SJeff Kirsher [40] = "UDP RSS support", 1055a2cc190SJeff Kirsher [41] = "Unicast VEP steering support", 1065a2cc190SJeff Kirsher [42] = "Multicast VEP steering support", 1075a2cc190SJeff Kirsher [48] = "Counters support", 108802f42a8SIdo Shamay [52] = "RSS IP fragments support", 109540b3a39SOr Gerlitz [53] = "Port ETS Scheduler support", 1104d531aa8SOr Gerlitz [55] = "Port link type sensing support", 11100f5ce99SJack Morgenstein [59] = "Port management change event support", 11208ff3235SOr Gerlitz [61] = "64 byte EQE support", 11308ff3235SOr Gerlitz [62] = "64 byte CQE support", 1145a2cc190SJeff Kirsher }; 1155a2cc190SJeff Kirsher int i; 1165a2cc190SJeff Kirsher 1175a2cc190SJeff Kirsher mlx4_dbg(dev, "DEV_CAP flags:\n"); 1185a2cc190SJeff Kirsher for (i = 0; i < ARRAY_SIZE(fname); ++i) 1195a2cc190SJeff Kirsher if (fname[i] && (flags & (1LL << i))) 1205a2cc190SJeff Kirsher mlx4_dbg(dev, " %s\n", fname[i]); 1215a2cc190SJeff Kirsher } 1225a2cc190SJeff Kirsher 123b3416f44SShlomo Pongratz static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags) 124b3416f44SShlomo Pongratz { 125b3416f44SShlomo Pongratz static const char * const fname[] = { 126b3416f44SShlomo Pongratz [0] = "RSS support", 127b3416f44SShlomo Pongratz [1] = "RSS Toeplitz Hash Function support", 1280ff1fb65SHadar Hen Zion [2] = "RSS XOR Hash Function support", 12956cb4567SOr Gerlitz [3] = "Device managed flow steering support", 130d998735fSEugenia Emantayev [4] = "Automatic MAC reassignment support", 1314e8cf5b8SOr Gerlitz [5] = "Time stamping support", 1324e8cf5b8SOr Gerlitz [6] = "VST (control vlan insertion/stripping) support", 133b01978caSJack Morgenstein [7] = "FSM (MAC anti-spoofing) support", 1347ffdf726SOr Gerlitz [8] = "Dynamic QP updates support", 13556cb4567SOr Gerlitz [9] = "Device managed flow steering IPoIB support", 136114840c3SJack Morgenstein [10] = "TCP/IP offloads/flow-steering for VXLAN support", 13777507aa2SIdo Shamay [11] = "MAD DEMUX (Secure-Host) support", 13877507aa2SIdo Shamay [12] = "Large cache line (>64B) CQE stride support", 139adbc7ac5SSaeed Mahameed [13] = "Large cache line (>64B) EQE stride support", 140a53e3e8cSSaeed Mahameed [14] = "Ethernet protocol control support", 141d475c95bSMatan Barak [15] = "Ethernet Backplane autoneg support", 1427ae0e400SMatan Barak [16] = "CONFIG DEV support", 143de966c59SMatan Barak [17] = "Asymmetric EQs support", 1447d077cd3SMatan Barak [18] = "More than 80 VFs support", 145be6a6b43SJack Morgenstein [19] = "Performance optimized for limited rule configuration flow steering support", 14659e14e32SMoni Shoua [20] = "Recoverable error events support", 147d237baa1SShani Michaeli [21] = "Port Remap support", 148fc31e256SOr Gerlitz [22] = "QCN support", 1490b131561SMatan Barak [23] = "QP rate limiting support", 150d019fcb2SIdo Shamay [24] = "Ethernet Flow control statistics support", 151d019fcb2SIdo Shamay [25] = "Granular QoS per VF support", 1523742cc65SIdo Shamay [26] = "Port ETS Scheduler support", 153*51af33cfSIdo Shamay [27] = "Port beacon support", 154b3416f44SShlomo Pongratz }; 155b3416f44SShlomo Pongratz int i; 156b3416f44SShlomo Pongratz 157b3416f44SShlomo Pongratz for (i = 0; i < ARRAY_SIZE(fname); ++i) 158b3416f44SShlomo Pongratz if (fname[i] && (flags & (1LL << i))) 159b3416f44SShlomo Pongratz mlx4_dbg(dev, " %s\n", fname[i]); 160b3416f44SShlomo Pongratz } 161b3416f44SShlomo Pongratz 1625a2cc190SJeff Kirsher int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg) 1635a2cc190SJeff Kirsher { 1645a2cc190SJeff Kirsher struct mlx4_cmd_mailbox *mailbox; 1655a2cc190SJeff Kirsher u32 *inbox; 1665a2cc190SJeff Kirsher int err = 0; 1675a2cc190SJeff Kirsher 1685a2cc190SJeff Kirsher #define MOD_STAT_CFG_IN_SIZE 0x100 1695a2cc190SJeff Kirsher 1705a2cc190SJeff Kirsher #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002 1715a2cc190SJeff Kirsher #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003 1725a2cc190SJeff Kirsher 1735a2cc190SJeff Kirsher mailbox = mlx4_alloc_cmd_mailbox(dev); 1745a2cc190SJeff Kirsher if (IS_ERR(mailbox)) 1755a2cc190SJeff Kirsher return PTR_ERR(mailbox); 1765a2cc190SJeff Kirsher inbox = mailbox->buf; 1775a2cc190SJeff Kirsher 1785a2cc190SJeff Kirsher MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET); 1795a2cc190SJeff Kirsher MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET); 1805a2cc190SJeff Kirsher 1815a2cc190SJeff Kirsher err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG, 182f9baff50SJack Morgenstein MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1835a2cc190SJeff Kirsher 1845a2cc190SJeff Kirsher mlx4_free_cmd_mailbox(dev, mailbox); 1855a2cc190SJeff Kirsher return err; 1865a2cc190SJeff Kirsher } 1875a2cc190SJeff Kirsher 188e8c4265bSMatan Barak int mlx4_QUERY_FUNC(struct mlx4_dev *dev, struct mlx4_func *func, int slave) 189e8c4265bSMatan Barak { 190e8c4265bSMatan Barak struct mlx4_cmd_mailbox *mailbox; 191e8c4265bSMatan Barak u32 *outbox; 192e8c4265bSMatan Barak u8 in_modifier; 193e8c4265bSMatan Barak u8 field; 194e8c4265bSMatan Barak u16 field16; 195e8c4265bSMatan Barak int err; 196e8c4265bSMatan Barak 197e8c4265bSMatan Barak #define QUERY_FUNC_BUS_OFFSET 0x00 198e8c4265bSMatan Barak #define QUERY_FUNC_DEVICE_OFFSET 0x01 199e8c4265bSMatan Barak #define QUERY_FUNC_FUNCTION_OFFSET 0x01 200e8c4265bSMatan Barak #define QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET 0x03 201e8c4265bSMatan Barak #define QUERY_FUNC_RSVD_EQS_OFFSET 0x04 202e8c4265bSMatan Barak #define QUERY_FUNC_MAX_EQ_OFFSET 0x06 203e8c4265bSMatan Barak #define QUERY_FUNC_RSVD_UARS_OFFSET 0x0b 204e8c4265bSMatan Barak 205e8c4265bSMatan Barak mailbox = mlx4_alloc_cmd_mailbox(dev); 206e8c4265bSMatan Barak if (IS_ERR(mailbox)) 207e8c4265bSMatan Barak return PTR_ERR(mailbox); 208e8c4265bSMatan Barak outbox = mailbox->buf; 209e8c4265bSMatan Barak 210e8c4265bSMatan Barak in_modifier = slave; 211e8c4265bSMatan Barak 212e8c4265bSMatan Barak err = mlx4_cmd_box(dev, 0, mailbox->dma, in_modifier, 0, 213e8c4265bSMatan Barak MLX4_CMD_QUERY_FUNC, 214e8c4265bSMatan Barak MLX4_CMD_TIME_CLASS_A, 215e8c4265bSMatan Barak MLX4_CMD_NATIVE); 216e8c4265bSMatan Barak if (err) 217e8c4265bSMatan Barak goto out; 218e8c4265bSMatan Barak 219e8c4265bSMatan Barak MLX4_GET(field, outbox, QUERY_FUNC_BUS_OFFSET); 220e8c4265bSMatan Barak func->bus = field & 0xf; 221e8c4265bSMatan Barak MLX4_GET(field, outbox, QUERY_FUNC_DEVICE_OFFSET); 222e8c4265bSMatan Barak func->device = field & 0xf1; 223e8c4265bSMatan Barak MLX4_GET(field, outbox, QUERY_FUNC_FUNCTION_OFFSET); 224e8c4265bSMatan Barak func->function = field & 0x7; 225e8c4265bSMatan Barak MLX4_GET(field, outbox, QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET); 226e8c4265bSMatan Barak func->physical_function = field & 0xf; 227e8c4265bSMatan Barak MLX4_GET(field16, outbox, QUERY_FUNC_RSVD_EQS_OFFSET); 228e8c4265bSMatan Barak func->rsvd_eqs = field16 & 0xffff; 229e8c4265bSMatan Barak MLX4_GET(field16, outbox, QUERY_FUNC_MAX_EQ_OFFSET); 230e8c4265bSMatan Barak func->max_eq = field16 & 0xffff; 231e8c4265bSMatan Barak MLX4_GET(field, outbox, QUERY_FUNC_RSVD_UARS_OFFSET); 232e8c4265bSMatan Barak func->rsvd_uars = field & 0x0f; 233e8c4265bSMatan Barak 234e8c4265bSMatan Barak mlx4_dbg(dev, "Bus: %d, Device: %d, Function: %d, Physical function: %d, Max EQs: %d, Reserved EQs: %d, Reserved UARs: %d\n", 235e8c4265bSMatan Barak func->bus, func->device, func->function, func->physical_function, 236e8c4265bSMatan Barak func->max_eq, func->rsvd_eqs, func->rsvd_uars); 237e8c4265bSMatan Barak 238e8c4265bSMatan Barak out: 239e8c4265bSMatan Barak mlx4_free_cmd_mailbox(dev, mailbox); 240e8c4265bSMatan Barak return err; 241e8c4265bSMatan Barak } 242e8c4265bSMatan Barak 2435cc914f1SMarcel Apfelbaum int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave, 2445cc914f1SMarcel Apfelbaum struct mlx4_vhcr *vhcr, 2455cc914f1SMarcel Apfelbaum struct mlx4_cmd_mailbox *inbox, 2465cc914f1SMarcel Apfelbaum struct mlx4_cmd_mailbox *outbox, 2475cc914f1SMarcel Apfelbaum struct mlx4_cmd_info *cmd) 2485cc914f1SMarcel Apfelbaum { 2495a0d0a61SJack Morgenstein struct mlx4_priv *priv = mlx4_priv(dev); 25099ec41d0SJack Morgenstein u8 field, port; 25199ec41d0SJack Morgenstein u32 size, proxy_qp, qkey; 2525cc914f1SMarcel Apfelbaum int err = 0; 2537ae0e400SMatan Barak struct mlx4_func func; 2545cc914f1SMarcel Apfelbaum 2555cc914f1SMarcel Apfelbaum #define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0 2565cc914f1SMarcel Apfelbaum #define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1 2575cc914f1SMarcel Apfelbaum #define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4 258105c320fSJack Morgenstein #define QUERY_FUNC_CAP_FMR_OFFSET 0x8 259eb456a68SJack Morgenstein #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP 0x10 260eb456a68SJack Morgenstein #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP 0x14 261eb456a68SJack Morgenstein #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP 0x18 262eb456a68SJack Morgenstein #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP 0x20 263eb456a68SJack Morgenstein #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP 0x24 264eb456a68SJack Morgenstein #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP 0x28 2655cc914f1SMarcel Apfelbaum #define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c 26669612b9fSRoland Dreier #define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30 267f0ce0615SJack Morgenstein #define QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET 0x48 2685cc914f1SMarcel Apfelbaum 269eb456a68SJack Morgenstein #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x50 270eb456a68SJack Morgenstein #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x54 271eb456a68SJack Morgenstein #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x58 272eb456a68SJack Morgenstein #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x60 273eb456a68SJack Morgenstein #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x64 274eb456a68SJack Morgenstein #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x68 275eb456a68SJack Morgenstein 276ddae0349SEugenia Emantayev #define QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET 0x6c 277ddae0349SEugenia Emantayev 278105c320fSJack Morgenstein #define QUERY_FUNC_CAP_FMR_FLAG 0x80 279105c320fSJack Morgenstein #define QUERY_FUNC_CAP_FLAG_RDMA 0x40 280105c320fSJack Morgenstein #define QUERY_FUNC_CAP_FLAG_ETH 0x80 281eb456a68SJack Morgenstein #define QUERY_FUNC_CAP_FLAG_QUOTAS 0x10 282f0ce0615SJack Morgenstein #define QUERY_FUNC_CAP_FLAG_RESD_LKEY 0x08 283ddae0349SEugenia Emantayev #define QUERY_FUNC_CAP_FLAG_VALID_MAILBOX 0x04 284ddae0349SEugenia Emantayev 285ddae0349SEugenia Emantayev #define QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG (1UL << 31) 286d57febe1SMatan Barak #define QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG (1UL << 30) 287105c320fSJack Morgenstein 288105c320fSJack Morgenstein /* when opcode modifier = 1 */ 2895cc914f1SMarcel Apfelbaum #define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3 29099ec41d0SJack Morgenstein #define QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET 0x4 29173e74ab4SHadar Hen Zion #define QUERY_FUNC_CAP_FLAGS0_OFFSET 0x8 29273e74ab4SHadar Hen Zion #define QUERY_FUNC_CAP_FLAGS1_OFFSET 0xc 2935cc914f1SMarcel Apfelbaum 29447605df9SJack Morgenstein #define QUERY_FUNC_CAP_QP0_TUNNEL 0x10 29547605df9SJack Morgenstein #define QUERY_FUNC_CAP_QP0_PROXY 0x14 29647605df9SJack Morgenstein #define QUERY_FUNC_CAP_QP1_TUNNEL 0x18 29747605df9SJack Morgenstein #define QUERY_FUNC_CAP_QP1_PROXY 0x1c 2988e1a28e8SHadar Hen Zion #define QUERY_FUNC_CAP_PHYS_PORT_ID 0x28 29947605df9SJack Morgenstein 30073e74ab4SHadar Hen Zion #define QUERY_FUNC_CAP_FLAGS1_FORCE_MAC 0x40 30173e74ab4SHadar Hen Zion #define QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN 0x80 302eb17711bSHadar Hen Zion #define QUERY_FUNC_CAP_FLAGS1_NIC_INFO 0x10 30399ec41d0SJack Morgenstein #define QUERY_FUNC_CAP_VF_ENABLE_QP0 0x08 304105c320fSJack Morgenstein 30573e74ab4SHadar Hen Zion #define QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID 0x80 3067ae0e400SMatan Barak #define QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS (1 << 31) 307105c320fSJack Morgenstein 3085cc914f1SMarcel Apfelbaum if (vhcr->op_modifier == 1) { 309449fc488SMatan Barak struct mlx4_active_ports actv_ports = 310449fc488SMatan Barak mlx4_get_active_ports(dev, slave); 311449fc488SMatan Barak int converted_port = mlx4_slave_convert_port( 312449fc488SMatan Barak dev, slave, vhcr->in_modifier); 313449fc488SMatan Barak 314449fc488SMatan Barak if (converted_port < 0) 315449fc488SMatan Barak return -EINVAL; 316449fc488SMatan Barak 317449fc488SMatan Barak vhcr->in_modifier = converted_port; 318449fc488SMatan Barak /* phys-port = logical-port */ 319449fc488SMatan Barak field = vhcr->in_modifier - 320449fc488SMatan Barak find_first_bit(actv_ports.ports, dev->caps.num_ports); 32147605df9SJack Morgenstein MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); 32247605df9SJack Morgenstein 32399ec41d0SJack Morgenstein port = vhcr->in_modifier; 32499ec41d0SJack Morgenstein proxy_qp = dev->phys_caps.base_proxy_sqpn + 8 * slave + port - 1; 32599ec41d0SJack Morgenstein 32699ec41d0SJack Morgenstein /* Set nic_info bit to mark new fields support */ 32799ec41d0SJack Morgenstein field = QUERY_FUNC_CAP_FLAGS1_NIC_INFO; 32899ec41d0SJack Morgenstein 32999ec41d0SJack Morgenstein if (mlx4_vf_smi_enabled(dev, slave, port) && 33099ec41d0SJack Morgenstein !mlx4_get_parav_qkey(dev, proxy_qp, &qkey)) { 33199ec41d0SJack Morgenstein field |= QUERY_FUNC_CAP_VF_ENABLE_QP0; 33299ec41d0SJack Morgenstein MLX4_PUT(outbox->buf, qkey, 33399ec41d0SJack Morgenstein QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET); 33499ec41d0SJack Morgenstein } 33599ec41d0SJack Morgenstein MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS1_OFFSET); 33699ec41d0SJack Morgenstein 33747605df9SJack Morgenstein /* size is now the QP number */ 33899ec41d0SJack Morgenstein size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + port - 1; 33947605df9SJack Morgenstein MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL); 34047605df9SJack Morgenstein 34147605df9SJack Morgenstein size += 2; 34247605df9SJack Morgenstein MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL); 34347605df9SJack Morgenstein 34499ec41d0SJack Morgenstein MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP0_PROXY); 34599ec41d0SJack Morgenstein proxy_qp += 2; 34699ec41d0SJack Morgenstein MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP1_PROXY); 34747605df9SJack Morgenstein 3488e1a28e8SHadar Hen Zion MLX4_PUT(outbox->buf, dev->caps.phys_port_id[vhcr->in_modifier], 3498e1a28e8SHadar Hen Zion QUERY_FUNC_CAP_PHYS_PORT_ID); 3508e1a28e8SHadar Hen Zion 3515cc914f1SMarcel Apfelbaum } else if (vhcr->op_modifier == 0) { 352449fc488SMatan Barak struct mlx4_active_ports actv_ports = 353449fc488SMatan Barak mlx4_get_active_ports(dev, slave); 354f0ce0615SJack Morgenstein /* enable rdma and ethernet interfaces, new quota locations, 355f0ce0615SJack Morgenstein * and reserved lkey 356f0ce0615SJack Morgenstein */ 357eb456a68SJack Morgenstein field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA | 358f0ce0615SJack Morgenstein QUERY_FUNC_CAP_FLAG_QUOTAS | QUERY_FUNC_CAP_FLAG_VALID_MAILBOX | 359f0ce0615SJack Morgenstein QUERY_FUNC_CAP_FLAG_RESD_LKEY); 3605cc914f1SMarcel Apfelbaum MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET); 3615cc914f1SMarcel Apfelbaum 362449fc488SMatan Barak field = min( 363449fc488SMatan Barak bitmap_weight(actv_ports.ports, dev->caps.num_ports), 364449fc488SMatan Barak dev->caps.num_ports); 3655cc914f1SMarcel Apfelbaum MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); 3665cc914f1SMarcel Apfelbaum 36708ff3235SOr Gerlitz size = dev->caps.function_caps; /* set PF behaviours */ 3685cc914f1SMarcel Apfelbaum MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET); 3695cc914f1SMarcel Apfelbaum 370105c320fSJack Morgenstein field = 0; /* protected FMR support not available as yet */ 371105c320fSJack Morgenstein MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET); 372105c320fSJack Morgenstein 3735a0d0a61SJack Morgenstein size = priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[slave]; 3745cc914f1SMarcel Apfelbaum MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET); 375eb456a68SJack Morgenstein size = dev->caps.num_qps; 376eb456a68SJack Morgenstein MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP); 3775cc914f1SMarcel Apfelbaum 3785a0d0a61SJack Morgenstein size = priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[slave]; 3795cc914f1SMarcel Apfelbaum MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET); 380eb456a68SJack Morgenstein size = dev->caps.num_srqs; 381eb456a68SJack Morgenstein MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP); 3825cc914f1SMarcel Apfelbaum 3835a0d0a61SJack Morgenstein size = priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[slave]; 3845cc914f1SMarcel Apfelbaum MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET); 385eb456a68SJack Morgenstein size = dev->caps.num_cqs; 386eb456a68SJack Morgenstein MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP); 3875cc914f1SMarcel Apfelbaum 3887ae0e400SMatan Barak if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) || 3897ae0e400SMatan Barak mlx4_QUERY_FUNC(dev, &func, slave)) { 3907ae0e400SMatan Barak size = vhcr->in_modifier & 3917ae0e400SMatan Barak QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS ? 3927ae0e400SMatan Barak dev->caps.num_eqs : 3937ae0e400SMatan Barak rounddown_pow_of_two(dev->caps.num_eqs); 3945cc914f1SMarcel Apfelbaum MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET); 3955cc914f1SMarcel Apfelbaum size = dev->caps.reserved_eqs; 3965cc914f1SMarcel Apfelbaum MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); 3977ae0e400SMatan Barak } else { 3987ae0e400SMatan Barak size = vhcr->in_modifier & 3997ae0e400SMatan Barak QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS ? 4007ae0e400SMatan Barak func.max_eq : 4017ae0e400SMatan Barak rounddown_pow_of_two(func.max_eq); 4027ae0e400SMatan Barak MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET); 4037ae0e400SMatan Barak size = func.rsvd_eqs; 4047ae0e400SMatan Barak MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); 4057ae0e400SMatan Barak } 4065cc914f1SMarcel Apfelbaum 4075a0d0a61SJack Morgenstein size = priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[slave]; 4085cc914f1SMarcel Apfelbaum MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET); 409eb456a68SJack Morgenstein size = dev->caps.num_mpts; 410eb456a68SJack Morgenstein MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP); 4115cc914f1SMarcel Apfelbaum 4125a0d0a61SJack Morgenstein size = priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[slave]; 4135cc914f1SMarcel Apfelbaum MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET); 414eb456a68SJack Morgenstein size = dev->caps.num_mtts; 415eb456a68SJack Morgenstein MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP); 4165cc914f1SMarcel Apfelbaum 4175cc914f1SMarcel Apfelbaum size = dev->caps.num_mgms + dev->caps.num_amgms; 4185cc914f1SMarcel Apfelbaum MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET); 419eb456a68SJack Morgenstein MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP); 4205cc914f1SMarcel Apfelbaum 421d57febe1SMatan Barak size = QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG | 422d57febe1SMatan Barak QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG; 423ddae0349SEugenia Emantayev MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET); 424f0ce0615SJack Morgenstein 425f0ce0615SJack Morgenstein size = dev->caps.reserved_lkey + ((slave << 8) & 0xFF00); 426f0ce0615SJack Morgenstein MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET); 4275cc914f1SMarcel Apfelbaum } else 4285cc914f1SMarcel Apfelbaum err = -EINVAL; 4295cc914f1SMarcel Apfelbaum 4305cc914f1SMarcel Apfelbaum return err; 4315cc914f1SMarcel Apfelbaum } 4325cc914f1SMarcel Apfelbaum 433225c6c8cSMatan Barak int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u8 gen_or_port, 43447605df9SJack Morgenstein struct mlx4_func_cap *func_cap) 4355cc914f1SMarcel Apfelbaum { 4365cc914f1SMarcel Apfelbaum struct mlx4_cmd_mailbox *mailbox; 4375cc914f1SMarcel Apfelbaum u32 *outbox; 43847605df9SJack Morgenstein u8 field, op_modifier; 43999ec41d0SJack Morgenstein u32 size, qkey; 440eb456a68SJack Morgenstein int err = 0, quotas = 0; 4417ae0e400SMatan Barak u32 in_modifier; 4425cc914f1SMarcel Apfelbaum 44347605df9SJack Morgenstein op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */ 4447ae0e400SMatan Barak in_modifier = op_modifier ? gen_or_port : 4457ae0e400SMatan Barak QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS; 4465cc914f1SMarcel Apfelbaum 4475cc914f1SMarcel Apfelbaum mailbox = mlx4_alloc_cmd_mailbox(dev); 4485cc914f1SMarcel Apfelbaum if (IS_ERR(mailbox)) 4495cc914f1SMarcel Apfelbaum return PTR_ERR(mailbox); 4505cc914f1SMarcel Apfelbaum 4517ae0e400SMatan Barak err = mlx4_cmd_box(dev, 0, mailbox->dma, in_modifier, op_modifier, 45247605df9SJack Morgenstein MLX4_CMD_QUERY_FUNC_CAP, 4535cc914f1SMarcel Apfelbaum MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 4545cc914f1SMarcel Apfelbaum if (err) 4555cc914f1SMarcel Apfelbaum goto out; 4565cc914f1SMarcel Apfelbaum 4575cc914f1SMarcel Apfelbaum outbox = mailbox->buf; 4585cc914f1SMarcel Apfelbaum 45947605df9SJack Morgenstein if (!op_modifier) { 4605cc914f1SMarcel Apfelbaum MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET); 461105c320fSJack Morgenstein if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) { 462105c320fSJack Morgenstein mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n"); 4635cc914f1SMarcel Apfelbaum err = -EPROTONOSUPPORT; 4645cc914f1SMarcel Apfelbaum goto out; 4655cc914f1SMarcel Apfelbaum } 466105c320fSJack Morgenstein func_cap->flags = field; 467eb456a68SJack Morgenstein quotas = !!(func_cap->flags & QUERY_FUNC_CAP_FLAG_QUOTAS); 4685cc914f1SMarcel Apfelbaum 4695cc914f1SMarcel Apfelbaum MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); 4705cc914f1SMarcel Apfelbaum func_cap->num_ports = field; 4715cc914f1SMarcel Apfelbaum 4725cc914f1SMarcel Apfelbaum MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET); 4735cc914f1SMarcel Apfelbaum func_cap->pf_context_behaviour = size; 4745cc914f1SMarcel Apfelbaum 475eb456a68SJack Morgenstein if (quotas) { 4765cc914f1SMarcel Apfelbaum MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET); 4775cc914f1SMarcel Apfelbaum func_cap->qp_quota = size & 0xFFFFFF; 4785cc914f1SMarcel Apfelbaum 4795cc914f1SMarcel Apfelbaum MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET); 4805cc914f1SMarcel Apfelbaum func_cap->srq_quota = size & 0xFFFFFF; 4815cc914f1SMarcel Apfelbaum 4825cc914f1SMarcel Apfelbaum MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET); 4835cc914f1SMarcel Apfelbaum func_cap->cq_quota = size & 0xFFFFFF; 4845cc914f1SMarcel Apfelbaum 4855cc914f1SMarcel Apfelbaum MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET); 4865cc914f1SMarcel Apfelbaum func_cap->mpt_quota = size & 0xFFFFFF; 4875cc914f1SMarcel Apfelbaum 4885cc914f1SMarcel Apfelbaum MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET); 4895cc914f1SMarcel Apfelbaum func_cap->mtt_quota = size & 0xFFFFFF; 4905cc914f1SMarcel Apfelbaum 4915cc914f1SMarcel Apfelbaum MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET); 4925cc914f1SMarcel Apfelbaum func_cap->mcg_quota = size & 0xFFFFFF; 493eb456a68SJack Morgenstein 494eb456a68SJack Morgenstein } else { 495eb456a68SJack Morgenstein MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP); 496eb456a68SJack Morgenstein func_cap->qp_quota = size & 0xFFFFFF; 497eb456a68SJack Morgenstein 498eb456a68SJack Morgenstein MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP); 499eb456a68SJack Morgenstein func_cap->srq_quota = size & 0xFFFFFF; 500eb456a68SJack Morgenstein 501eb456a68SJack Morgenstein MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP); 502eb456a68SJack Morgenstein func_cap->cq_quota = size & 0xFFFFFF; 503eb456a68SJack Morgenstein 504eb456a68SJack Morgenstein MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP); 505eb456a68SJack Morgenstein func_cap->mpt_quota = size & 0xFFFFFF; 506eb456a68SJack Morgenstein 507eb456a68SJack Morgenstein MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP); 508eb456a68SJack Morgenstein func_cap->mtt_quota = size & 0xFFFFFF; 509eb456a68SJack Morgenstein 510eb456a68SJack Morgenstein MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP); 511eb456a68SJack Morgenstein func_cap->mcg_quota = size & 0xFFFFFF; 512eb456a68SJack Morgenstein } 513eb456a68SJack Morgenstein MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET); 514eb456a68SJack Morgenstein func_cap->max_eq = size & 0xFFFFFF; 515eb456a68SJack Morgenstein 516eb456a68SJack Morgenstein MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); 517eb456a68SJack Morgenstein func_cap->reserved_eq = size & 0xFFFFFF; 518eb456a68SJack Morgenstein 519f0ce0615SJack Morgenstein if (func_cap->flags & QUERY_FUNC_CAP_FLAG_RESD_LKEY) { 520f0ce0615SJack Morgenstein MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET); 521f0ce0615SJack Morgenstein func_cap->reserved_lkey = size; 522f0ce0615SJack Morgenstein } else { 523f0ce0615SJack Morgenstein func_cap->reserved_lkey = 0; 524f0ce0615SJack Morgenstein } 525f0ce0615SJack Morgenstein 526ddae0349SEugenia Emantayev func_cap->extra_flags = 0; 527ddae0349SEugenia Emantayev 528ddae0349SEugenia Emantayev /* Mailbox data from 0x6c and onward should only be treated if 529ddae0349SEugenia Emantayev * QUERY_FUNC_CAP_FLAG_VALID_MAILBOX is set in func_cap->flags 530ddae0349SEugenia Emantayev */ 531ddae0349SEugenia Emantayev if (func_cap->flags & QUERY_FUNC_CAP_FLAG_VALID_MAILBOX) { 532ddae0349SEugenia Emantayev MLX4_GET(size, outbox, QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET); 533ddae0349SEugenia Emantayev if (size & QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG) 534ddae0349SEugenia Emantayev func_cap->extra_flags |= MLX4_QUERY_FUNC_FLAGS_BF_RES_QP; 535d57febe1SMatan Barak if (size & QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG) 536d57febe1SMatan Barak func_cap->extra_flags |= MLX4_QUERY_FUNC_FLAGS_A0_RES_QP; 537ddae0349SEugenia Emantayev } 538ddae0349SEugenia Emantayev 5395cc914f1SMarcel Apfelbaum goto out; 54047605df9SJack Morgenstein } 5415cc914f1SMarcel Apfelbaum 54247605df9SJack Morgenstein /* logical port query */ 54347605df9SJack Morgenstein if (gen_or_port > dev->caps.num_ports) { 54447605df9SJack Morgenstein err = -EINVAL; 54547605df9SJack Morgenstein goto out; 54647605df9SJack Morgenstein } 54747605df9SJack Morgenstein 548eb17711bSHadar Hen Zion MLX4_GET(func_cap->flags1, outbox, QUERY_FUNC_CAP_FLAGS1_OFFSET); 54947605df9SJack Morgenstein if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) { 550bc82878bSJack Morgenstein if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN) { 5515cc914f1SMarcel Apfelbaum mlx4_err(dev, "VLAN is enforced on this port\n"); 5525cc914f1SMarcel Apfelbaum err = -EPROTONOSUPPORT; 5535cc914f1SMarcel Apfelbaum goto out; 5545cc914f1SMarcel Apfelbaum } 5555cc914f1SMarcel Apfelbaum 556eb17711bSHadar Hen Zion if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_MAC) { 5575cc914f1SMarcel Apfelbaum mlx4_err(dev, "Force mac is enabled on this port\n"); 5585cc914f1SMarcel Apfelbaum err = -EPROTONOSUPPORT; 5595cc914f1SMarcel Apfelbaum goto out; 5605cc914f1SMarcel Apfelbaum } 56147605df9SJack Morgenstein } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) { 56273e74ab4SHadar Hen Zion MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET); 56373e74ab4SHadar Hen Zion if (field & QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID) { 5641a91de28SJoe Perches mlx4_err(dev, "phy_wqe_gid is enforced on this ib port\n"); 565105c320fSJack Morgenstein err = -EPROTONOSUPPORT; 566105c320fSJack Morgenstein goto out; 567105c320fSJack Morgenstein } 568105c320fSJack Morgenstein } 5695cc914f1SMarcel Apfelbaum 5705cc914f1SMarcel Apfelbaum MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); 57147605df9SJack Morgenstein func_cap->physical_port = field; 57247605df9SJack Morgenstein if (func_cap->physical_port != gen_or_port) { 57347605df9SJack Morgenstein err = -ENOSYS; 57447605df9SJack Morgenstein goto out; 5755cc914f1SMarcel Apfelbaum } 5765cc914f1SMarcel Apfelbaum 57799ec41d0SJack Morgenstein if (func_cap->flags1 & QUERY_FUNC_CAP_VF_ENABLE_QP0) { 57899ec41d0SJack Morgenstein MLX4_GET(qkey, outbox, QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET); 57999ec41d0SJack Morgenstein func_cap->qp0_qkey = qkey; 58099ec41d0SJack Morgenstein } else { 58199ec41d0SJack Morgenstein func_cap->qp0_qkey = 0; 58299ec41d0SJack Morgenstein } 58399ec41d0SJack Morgenstein 58447605df9SJack Morgenstein MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL); 58547605df9SJack Morgenstein func_cap->qp0_tunnel_qpn = size & 0xFFFFFF; 58647605df9SJack Morgenstein 58747605df9SJack Morgenstein MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY); 58847605df9SJack Morgenstein func_cap->qp0_proxy_qpn = size & 0xFFFFFF; 58947605df9SJack Morgenstein 59047605df9SJack Morgenstein MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL); 59147605df9SJack Morgenstein func_cap->qp1_tunnel_qpn = size & 0xFFFFFF; 59247605df9SJack Morgenstein 59347605df9SJack Morgenstein MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY); 59447605df9SJack Morgenstein func_cap->qp1_proxy_qpn = size & 0xFFFFFF; 59547605df9SJack Morgenstein 5968e1a28e8SHadar Hen Zion if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_NIC_INFO) 5978e1a28e8SHadar Hen Zion MLX4_GET(func_cap->phys_port_id, outbox, 5988e1a28e8SHadar Hen Zion QUERY_FUNC_CAP_PHYS_PORT_ID); 5998e1a28e8SHadar Hen Zion 6005cc914f1SMarcel Apfelbaum /* All other resources are allocated by the master, but we still report 6015cc914f1SMarcel Apfelbaum * 'num' and 'reserved' capabilities as follows: 6025cc914f1SMarcel Apfelbaum * - num remains the maximum resource index 6035cc914f1SMarcel Apfelbaum * - 'num - reserved' is the total available objects of a resource, but 6045cc914f1SMarcel Apfelbaum * resource indices may be less than 'reserved' 6055cc914f1SMarcel Apfelbaum * TODO: set per-resource quotas */ 6065cc914f1SMarcel Apfelbaum 6075cc914f1SMarcel Apfelbaum out: 6085cc914f1SMarcel Apfelbaum mlx4_free_cmd_mailbox(dev, mailbox); 6095cc914f1SMarcel Apfelbaum 6105cc914f1SMarcel Apfelbaum return err; 6115cc914f1SMarcel Apfelbaum } 6125cc914f1SMarcel Apfelbaum 6135a2cc190SJeff Kirsher int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 6145a2cc190SJeff Kirsher { 6155a2cc190SJeff Kirsher struct mlx4_cmd_mailbox *mailbox; 6165a2cc190SJeff Kirsher u32 *outbox; 6175a2cc190SJeff Kirsher u8 field; 6185a2cc190SJeff Kirsher u32 field32, flags, ext_flags; 6195a2cc190SJeff Kirsher u16 size; 6205a2cc190SJeff Kirsher u16 stat_rate; 6215a2cc190SJeff Kirsher int err; 6225a2cc190SJeff Kirsher int i; 6235a2cc190SJeff Kirsher 6245a2cc190SJeff Kirsher #define QUERY_DEV_CAP_OUT_SIZE 0x100 6255a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10 6265a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11 6275a2cc190SJeff Kirsher #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12 6285a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13 6295a2cc190SJeff Kirsher #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14 6305a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15 6315a2cc190SJeff Kirsher #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16 6325a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17 6335a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19 6345a2cc190SJeff Kirsher #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a 6355a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b 6365a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d 6375a2cc190SJeff Kirsher #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e 6385a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f 6395a2cc190SJeff Kirsher #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20 6405a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21 6415a2cc190SJeff Kirsher #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22 6425a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23 6437ae0e400SMatan Barak #define QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET 0x26 6445a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27 6455a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29 6465a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b 6475a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d 648b3416f44SShlomo Pongratz #define QUERY_DEV_CAP_RSS_OFFSET 0x2e 6495a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f 6505a2cc190SJeff Kirsher #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33 651*51af33cfSIdo Shamay #define QUERY_DEV_CAP_PORT_BEACON_OFFSET 0x34 6525a2cc190SJeff Kirsher #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35 6535a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36 6545a2cc190SJeff Kirsher #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37 6555a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38 6565a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b 6575a2cc190SJeff Kirsher #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c 658d998735fSEugenia Emantayev #define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e 6595a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f 6605a2cc190SJeff Kirsher #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40 6615a2cc190SJeff Kirsher #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44 6625a2cc190SJeff Kirsher #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48 6635a2cc190SJeff Kirsher #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49 6645a2cc190SJeff Kirsher #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b 6655a2cc190SJeff Kirsher #define QUERY_DEV_CAP_BF_OFFSET 0x4c 6665a2cc190SJeff Kirsher #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d 6675a2cc190SJeff Kirsher #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e 6685a2cc190SJeff Kirsher #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f 6695a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51 6705a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52 6715a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55 6725a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56 6735a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61 6745a2cc190SJeff Kirsher #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62 6755a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63 6765a2cc190SJeff Kirsher #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64 6775a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65 678f470f8d4SLinus Torvalds #define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66 679f470f8d4SLinus Torvalds #define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67 6805a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68 6810b131561SMatan Barak #define QUERY_DEV_CAP_PORT_FLOWSTATS_COUNTERS_OFFSET 0x70 6823f7fb021SRony Efraim #define QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET 0x70 6834de65803SMatan Barak #define QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET 0x74 6840ff1fb65SHadar Hen Zion #define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76 6850ff1fb65SHadar Hen Zion #define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77 68677507aa2SIdo Shamay #define QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE 0x7a 687d237baa1SShani Michaeli #define QUERY_DEV_CAP_ECN_QCN_VER_OFFSET 0x7b 6885a2cc190SJeff Kirsher #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80 6895a2cc190SJeff Kirsher #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82 6905a2cc190SJeff Kirsher #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84 6915a2cc190SJeff Kirsher #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86 6925a2cc190SJeff Kirsher #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88 6935a2cc190SJeff Kirsher #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a 6945a2cc190SJeff Kirsher #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c 6955a2cc190SJeff Kirsher #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e 6965a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90 6975a2cc190SJeff Kirsher #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92 6985a2cc190SJeff Kirsher #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94 699d475c95bSMatan Barak #define QUERY_DEV_CAP_CONFIG_DEV_OFFSET 0x94 7005a2cc190SJeff Kirsher #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98 7015a2cc190SJeff Kirsher #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0 702a53e3e8cSSaeed Mahameed #define QUERY_DEV_CAP_ETH_BACKPL_OFFSET 0x9c 703955154faSMatan Barak #define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d 7047ffdf726SOr Gerlitz #define QUERY_DEV_CAP_VXLAN 0x9e 705114840c3SJack Morgenstein #define QUERY_DEV_CAP_MAD_DEMUX_OFFSET 0xb0 7067d077cd3SMatan Barak #define QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_BASE_OFFSET 0xa8 7077d077cd3SMatan Barak #define QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_RANGE_OFFSET 0xac 708fc31e256SOr Gerlitz #define QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET 0xcc 709fc31e256SOr Gerlitz #define QUERY_DEV_CAP_QP_RATE_LIMIT_MAX_OFFSET 0xd0 710fc31e256SOr Gerlitz #define QUERY_DEV_CAP_QP_RATE_LIMIT_MIN_OFFSET 0xd2 711fc31e256SOr Gerlitz 7125a2cc190SJeff Kirsher 713b3416f44SShlomo Pongratz dev_cap->flags2 = 0; 7145a2cc190SJeff Kirsher mailbox = mlx4_alloc_cmd_mailbox(dev); 7155a2cc190SJeff Kirsher if (IS_ERR(mailbox)) 7165a2cc190SJeff Kirsher return PTR_ERR(mailbox); 7175a2cc190SJeff Kirsher outbox = mailbox->buf; 7185a2cc190SJeff Kirsher 7195a2cc190SJeff Kirsher err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, 720401453a3SJack Morgenstein MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 7215a2cc190SJeff Kirsher if (err) 7225a2cc190SJeff Kirsher goto out; 7235a2cc190SJeff Kirsher 7245a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET); 7255a2cc190SJeff Kirsher dev_cap->reserved_qps = 1 << (field & 0xf); 7265a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET); 7275a2cc190SJeff Kirsher dev_cap->max_qps = 1 << (field & 0x1f); 7285a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET); 7295a2cc190SJeff Kirsher dev_cap->reserved_srqs = 1 << (field >> 4); 7305a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET); 7315a2cc190SJeff Kirsher dev_cap->max_srqs = 1 << (field & 0x1f); 7325a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET); 7335a2cc190SJeff Kirsher dev_cap->max_cq_sz = 1 << field; 7345a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET); 7355a2cc190SJeff Kirsher dev_cap->reserved_cqs = 1 << (field & 0xf); 7365a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET); 7375a2cc190SJeff Kirsher dev_cap->max_cqs = 1 << (field & 0x1f); 7385a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET); 7395a2cc190SJeff Kirsher dev_cap->max_mpts = 1 << (field & 0x3f); 7405a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET); 7417c68dd43SMatan Barak dev_cap->reserved_eqs = 1 << (field & 0xf); 7425a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET); 7435a2cc190SJeff Kirsher dev_cap->max_eqs = 1 << (field & 0xf); 7445a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET); 7455a2cc190SJeff Kirsher dev_cap->reserved_mtts = 1 << (field >> 4); 7465a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET); 7475a2cc190SJeff Kirsher dev_cap->max_mrw_sz = 1 << field; 7485a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET); 7495a2cc190SJeff Kirsher dev_cap->reserved_mrws = 1 << (field & 0xf); 7505a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET); 7515a2cc190SJeff Kirsher dev_cap->max_mtt_seg = 1 << (field & 0x3f); 7527ae0e400SMatan Barak MLX4_GET(size, outbox, QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET); 7537ae0e400SMatan Barak dev_cap->num_sys_eqs = size & 0xfff; 7545a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET); 7555a2cc190SJeff Kirsher dev_cap->max_requester_per_qp = 1 << (field & 0x3f); 7565a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET); 7575a2cc190SJeff Kirsher dev_cap->max_responder_per_qp = 1 << (field & 0x3f); 7585a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET); 7595a2cc190SJeff Kirsher field &= 0x1f; 7605a2cc190SJeff Kirsher if (!field) 7615a2cc190SJeff Kirsher dev_cap->max_gso_sz = 0; 7625a2cc190SJeff Kirsher else 7635a2cc190SJeff Kirsher dev_cap->max_gso_sz = 1 << field; 7645a2cc190SJeff Kirsher 765b3416f44SShlomo Pongratz MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET); 766b3416f44SShlomo Pongratz if (field & 0x20) 767b3416f44SShlomo Pongratz dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR; 768b3416f44SShlomo Pongratz if (field & 0x10) 769b3416f44SShlomo Pongratz dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP; 770b3416f44SShlomo Pongratz field &= 0xf; 771b3416f44SShlomo Pongratz if (field) { 772b3416f44SShlomo Pongratz dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS; 773b3416f44SShlomo Pongratz dev_cap->max_rss_tbl_sz = 1 << field; 774b3416f44SShlomo Pongratz } else 775b3416f44SShlomo Pongratz dev_cap->max_rss_tbl_sz = 0; 7765a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET); 7775a2cc190SJeff Kirsher dev_cap->max_rdma_global = 1 << (field & 0x3f); 7785a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET); 7795a2cc190SJeff Kirsher dev_cap->local_ca_ack_delay = field & 0x1f; 7805a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); 7815a2cc190SJeff Kirsher dev_cap->num_ports = field & 0xf; 7825a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET); 7830b131561SMatan Barak MLX4_GET(field, outbox, QUERY_DEV_CAP_PORT_FLOWSTATS_COUNTERS_OFFSET); 7840b131561SMatan Barak if (field & 0x10) 7850b131561SMatan Barak dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN; 7865a2cc190SJeff Kirsher dev_cap->max_msg_sz = 1 << (field & 0x1f); 7870ff1fb65SHadar Hen Zion MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); 7880ff1fb65SHadar Hen Zion if (field & 0x80) 7890ff1fb65SHadar Hen Zion dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN; 7900ff1fb65SHadar Hen Zion dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f; 791*51af33cfSIdo Shamay MLX4_GET(field, outbox, QUERY_DEV_CAP_PORT_BEACON_OFFSET); 792*51af33cfSIdo Shamay if (field & 0x80) 793*51af33cfSIdo Shamay dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PORT_BEACON; 7944de65803SMatan Barak MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); 7954de65803SMatan Barak if (field & 0x80) 7964de65803SMatan Barak dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_IPOIB; 7970ff1fb65SHadar Hen Zion MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET); 7980ff1fb65SHadar Hen Zion dev_cap->fs_max_num_qp_per_entry = field; 799d237baa1SShani Michaeli MLX4_GET(field, outbox, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET); 800d237baa1SShani Michaeli if (field & 0x1) 801d237baa1SShani Michaeli dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QCN; 8025a2cc190SJeff Kirsher MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET); 8035a2cc190SJeff Kirsher dev_cap->stat_rate_support = stat_rate; 804d998735fSEugenia Emantayev MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); 805d998735fSEugenia Emantayev if (field & 0x80) 806d998735fSEugenia Emantayev dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS; 8075a2cc190SJeff Kirsher MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); 8085a2cc190SJeff Kirsher MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET); 8095a2cc190SJeff Kirsher dev_cap->flags = flags | (u64)ext_flags << 32; 8105a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET); 8115a2cc190SJeff Kirsher dev_cap->reserved_uars = field >> 4; 8125a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET); 8135a2cc190SJeff Kirsher dev_cap->uar_size = 1 << ((field & 0x3f) + 20); 8145a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET); 8155a2cc190SJeff Kirsher dev_cap->min_page_sz = 1 << field; 8165a2cc190SJeff Kirsher 8175a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET); 8185a2cc190SJeff Kirsher if (field & 0x80) { 8195a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET); 8205a2cc190SJeff Kirsher dev_cap->bf_reg_size = 1 << (field & 0x1f); 8215a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET); 8225a2cc190SJeff Kirsher if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size)) 8235a2cc190SJeff Kirsher field = 3; 8245a2cc190SJeff Kirsher dev_cap->bf_regs_per_page = 1 << (field & 0x3f); 8255a2cc190SJeff Kirsher } else { 8265a2cc190SJeff Kirsher dev_cap->bf_reg_size = 0; 8275a2cc190SJeff Kirsher } 8285a2cc190SJeff Kirsher 8295a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET); 8305a2cc190SJeff Kirsher dev_cap->max_sq_sg = field; 8315a2cc190SJeff Kirsher MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET); 8325a2cc190SJeff Kirsher dev_cap->max_sq_desc_sz = size; 8335a2cc190SJeff Kirsher 8345a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET); 8355a2cc190SJeff Kirsher dev_cap->max_qp_per_mcg = 1 << field; 8365a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET); 8375a2cc190SJeff Kirsher dev_cap->reserved_mgms = field & 0xf; 8385a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET); 8395a2cc190SJeff Kirsher dev_cap->max_mcgs = 1 << field; 8405a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET); 8415a2cc190SJeff Kirsher dev_cap->reserved_pds = field >> 4; 8425a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET); 8435a2cc190SJeff Kirsher dev_cap->max_pds = 1 << (field & 0x3f); 844f470f8d4SLinus Torvalds MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET); 845f470f8d4SLinus Torvalds dev_cap->reserved_xrcds = field >> 4; 846426dd00dSDotan Barak MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET); 847f470f8d4SLinus Torvalds dev_cap->max_xrcds = 1 << (field & 0x1f); 8485a2cc190SJeff Kirsher 8495a2cc190SJeff Kirsher MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET); 8505a2cc190SJeff Kirsher dev_cap->rdmarc_entry_sz = size; 8515a2cc190SJeff Kirsher MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET); 8525a2cc190SJeff Kirsher dev_cap->qpc_entry_sz = size; 8535a2cc190SJeff Kirsher MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET); 8545a2cc190SJeff Kirsher dev_cap->aux_entry_sz = size; 8555a2cc190SJeff Kirsher MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET); 8565a2cc190SJeff Kirsher dev_cap->altc_entry_sz = size; 8575a2cc190SJeff Kirsher MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET); 8585a2cc190SJeff Kirsher dev_cap->eqc_entry_sz = size; 8595a2cc190SJeff Kirsher MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET); 8605a2cc190SJeff Kirsher dev_cap->cqc_entry_sz = size; 8615a2cc190SJeff Kirsher MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET); 8625a2cc190SJeff Kirsher dev_cap->srq_entry_sz = size; 8635a2cc190SJeff Kirsher MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET); 8645a2cc190SJeff Kirsher dev_cap->cmpt_entry_sz = size; 8655a2cc190SJeff Kirsher MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET); 8665a2cc190SJeff Kirsher dev_cap->mtt_entry_sz = size; 8675a2cc190SJeff Kirsher MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET); 8685a2cc190SJeff Kirsher dev_cap->dmpt_entry_sz = size; 8695a2cc190SJeff Kirsher 8705a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET); 8715a2cc190SJeff Kirsher dev_cap->max_srq_sz = 1 << field; 8725a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET); 8735a2cc190SJeff Kirsher dev_cap->max_qp_sz = 1 << field; 8745a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET); 8755a2cc190SJeff Kirsher dev_cap->resize_srq = field & 1; 8765a2cc190SJeff Kirsher MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET); 8775a2cc190SJeff Kirsher dev_cap->max_rq_sg = field; 8785a2cc190SJeff Kirsher MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET); 8795a2cc190SJeff Kirsher dev_cap->max_rq_desc_sz = size; 88077507aa2SIdo Shamay MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE); 881d019fcb2SIdo Shamay if (field & (1 << 4)) 882d019fcb2SIdo Shamay dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QOS_VPP; 883adbc7ac5SSaeed Mahameed if (field & (1 << 5)) 884adbc7ac5SSaeed Mahameed dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL; 88577507aa2SIdo Shamay if (field & (1 << 6)) 88677507aa2SIdo Shamay dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CQE_STRIDE; 88777507aa2SIdo Shamay if (field & (1 << 7)) 88877507aa2SIdo Shamay dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_EQE_STRIDE; 8895a2cc190SJeff Kirsher MLX4_GET(dev_cap->bmme_flags, outbox, 8905a2cc190SJeff Kirsher QUERY_DEV_CAP_BMME_FLAGS_OFFSET); 89159e14e32SMoni Shoua if (dev_cap->bmme_flags & MLX4_FLAG_PORT_REMAP) 89259e14e32SMoni Shoua dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PORT_REMAP; 893d475c95bSMatan Barak MLX4_GET(field, outbox, QUERY_DEV_CAP_CONFIG_DEV_OFFSET); 894d475c95bSMatan Barak if (field & 0x20) 895d475c95bSMatan Barak dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CONFIG_DEV; 8965a2cc190SJeff Kirsher MLX4_GET(dev_cap->reserved_lkey, outbox, 8975a2cc190SJeff Kirsher QUERY_DEV_CAP_RSVD_LKEY_OFFSET); 898a53e3e8cSSaeed Mahameed MLX4_GET(field32, outbox, QUERY_DEV_CAP_ETH_BACKPL_OFFSET); 899a53e3e8cSSaeed Mahameed if (field32 & (1 << 0)) 900a53e3e8cSSaeed Mahameed dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP; 901be6a6b43SJack Morgenstein if (field32 & (1 << 7)) 902be6a6b43SJack Morgenstein dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT; 903955154faSMatan Barak MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC); 904955154faSMatan Barak if (field & 1<<6) 9055930e8d0SOr Gerlitz dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN; 9067ffdf726SOr Gerlitz MLX4_GET(field, outbox, QUERY_DEV_CAP_VXLAN); 9077ffdf726SOr Gerlitz if (field & 1<<3) 9087ffdf726SOr Gerlitz dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS; 9093742cc65SIdo Shamay if (field & (1 << 5)) 9103742cc65SIdo Shamay dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG; 9115a2cc190SJeff Kirsher MLX4_GET(dev_cap->max_icm_sz, outbox, 9125a2cc190SJeff Kirsher QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET); 9135a2cc190SJeff Kirsher if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS) 9145a2cc190SJeff Kirsher MLX4_GET(dev_cap->max_counters, outbox, 9155a2cc190SJeff Kirsher QUERY_DEV_CAP_MAX_COUNTERS_OFFSET); 9165a2cc190SJeff Kirsher 917114840c3SJack Morgenstein MLX4_GET(field32, outbox, 918114840c3SJack Morgenstein QUERY_DEV_CAP_MAD_DEMUX_OFFSET); 919114840c3SJack Morgenstein if (field32 & (1 << 0)) 920114840c3SJack Morgenstein dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_MAD_DEMUX; 921114840c3SJack Morgenstein 9227d077cd3SMatan Barak MLX4_GET(dev_cap->dmfs_high_rate_qpn_base, outbox, 9237d077cd3SMatan Barak QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_BASE_OFFSET); 9247d077cd3SMatan Barak dev_cap->dmfs_high_rate_qpn_base &= MGM_QPN_MASK; 9257d077cd3SMatan Barak MLX4_GET(dev_cap->dmfs_high_rate_qpn_range, outbox, 9267d077cd3SMatan Barak QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_RANGE_OFFSET); 9277d077cd3SMatan Barak dev_cap->dmfs_high_rate_qpn_range &= MGM_QPN_MASK; 9287d077cd3SMatan Barak 929fc31e256SOr Gerlitz MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET); 930fc31e256SOr Gerlitz dev_cap->rl_caps.num_rates = size; 931fc31e256SOr Gerlitz if (dev_cap->rl_caps.num_rates) { 932fc31e256SOr Gerlitz dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT; 933fc31e256SOr Gerlitz MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_MAX_OFFSET); 934fc31e256SOr Gerlitz dev_cap->rl_caps.max_val = size & 0xfff; 935fc31e256SOr Gerlitz dev_cap->rl_caps.max_unit = size >> 14; 936fc31e256SOr Gerlitz MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_MIN_OFFSET); 937fc31e256SOr Gerlitz dev_cap->rl_caps.min_val = size & 0xfff; 938fc31e256SOr Gerlitz dev_cap->rl_caps.min_unit = size >> 14; 939fc31e256SOr Gerlitz } 940fc31e256SOr Gerlitz 9413f7fb021SRony Efraim MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); 942b01978caSJack Morgenstein if (field32 & (1 << 16)) 943b01978caSJack Morgenstein dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP; 9443f7fb021SRony Efraim if (field32 & (1 << 26)) 9453f7fb021SRony Efraim dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL; 946e6b6a231SRony Efraim if (field32 & (1 << 20)) 947e6b6a231SRony Efraim dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM; 948de966c59SMatan Barak if (field32 & (1 << 21)) 949de966c59SMatan Barak dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_80_VFS; 9503f7fb021SRony Efraim 951431df8c7SMatan Barak for (i = 1; i <= dev_cap->num_ports; i++) { 952431df8c7SMatan Barak err = mlx4_QUERY_PORT(dev, i, dev_cap->port_cap + i); 9535a2cc190SJeff Kirsher if (err) 9545a2cc190SJeff Kirsher goto out; 9555a2cc190SJeff Kirsher } 9565a2cc190SJeff Kirsher 9575a2cc190SJeff Kirsher /* 9585a2cc190SJeff Kirsher * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then 9595a2cc190SJeff Kirsher * we can't use any EQs whose doorbell falls on that page, 9605a2cc190SJeff Kirsher * even if the EQ itself isn't reserved. 9615a2cc190SJeff Kirsher */ 9627ae0e400SMatan Barak if (dev_cap->num_sys_eqs == 0) 9635a2cc190SJeff Kirsher dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4, 9645a2cc190SJeff Kirsher dev_cap->reserved_eqs); 9657ae0e400SMatan Barak else 9667ae0e400SMatan Barak dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SYS_EQS; 9675a2cc190SJeff Kirsher 968c78e25edSOr Gerlitz out: 969c78e25edSOr Gerlitz mlx4_free_cmd_mailbox(dev, mailbox); 970c78e25edSOr Gerlitz return err; 971c78e25edSOr Gerlitz } 972c78e25edSOr Gerlitz 973c78e25edSOr Gerlitz void mlx4_dev_cap_dump(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) 974c78e25edSOr Gerlitz { 975c78e25edSOr Gerlitz if (dev_cap->bf_reg_size > 0) 976c78e25edSOr Gerlitz mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n", 977c78e25edSOr Gerlitz dev_cap->bf_reg_size, dev_cap->bf_regs_per_page); 978c78e25edSOr Gerlitz else 979c78e25edSOr Gerlitz mlx4_dbg(dev, "BlueFlame not available\n"); 980c78e25edSOr Gerlitz 981c78e25edSOr Gerlitz mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n", 982c78e25edSOr Gerlitz dev_cap->bmme_flags, dev_cap->reserved_lkey); 9835a2cc190SJeff Kirsher mlx4_dbg(dev, "Max ICM size %lld MB\n", 9845a2cc190SJeff Kirsher (unsigned long long) dev_cap->max_icm_sz >> 20); 9855a2cc190SJeff Kirsher mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n", 9865a2cc190SJeff Kirsher dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz); 9875a2cc190SJeff Kirsher mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n", 9885a2cc190SJeff Kirsher dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz); 9895a2cc190SJeff Kirsher mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n", 9905a2cc190SJeff Kirsher dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz); 9917ae0e400SMatan Barak mlx4_dbg(dev, "Num sys EQs: %d, max EQs: %d, reserved EQs: %d, entry size: %d\n", 9927ae0e400SMatan Barak dev_cap->num_sys_eqs, dev_cap->max_eqs, dev_cap->reserved_eqs, 9937ae0e400SMatan Barak dev_cap->eqc_entry_sz); 9945a2cc190SJeff Kirsher mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n", 9955a2cc190SJeff Kirsher dev_cap->reserved_mrws, dev_cap->reserved_mtts); 9965a2cc190SJeff Kirsher mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n", 9975a2cc190SJeff Kirsher dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars); 9985a2cc190SJeff Kirsher mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n", 9995a2cc190SJeff Kirsher dev_cap->max_pds, dev_cap->reserved_mgms); 10005a2cc190SJeff Kirsher mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n", 10015a2cc190SJeff Kirsher dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz); 10025a2cc190SJeff Kirsher mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n", 1003431df8c7SMatan Barak dev_cap->local_ca_ack_delay, 128 << dev_cap->port_cap[1].ib_mtu, 1004431df8c7SMatan Barak dev_cap->port_cap[1].max_port_width); 10055a2cc190SJeff Kirsher mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n", 10065a2cc190SJeff Kirsher dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg); 10075a2cc190SJeff Kirsher mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n", 10085a2cc190SJeff Kirsher dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg); 10095a2cc190SJeff Kirsher mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz); 10105a2cc190SJeff Kirsher mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters); 1011b3416f44SShlomo Pongratz mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz); 10127d077cd3SMatan Barak mlx4_dbg(dev, "DMFS high rate steer QPn base: %d\n", 10137d077cd3SMatan Barak dev_cap->dmfs_high_rate_qpn_base); 10147d077cd3SMatan Barak mlx4_dbg(dev, "DMFS high rate steer QPn range: %d\n", 10157d077cd3SMatan Barak dev_cap->dmfs_high_rate_qpn_range); 1016fc31e256SOr Gerlitz 1017fc31e256SOr Gerlitz if (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT) { 1018fc31e256SOr Gerlitz struct mlx4_rate_limit_caps *rl_caps = &dev_cap->rl_caps; 1019fc31e256SOr Gerlitz 1020fc31e256SOr Gerlitz mlx4_dbg(dev, "QP Rate-Limit: #rates %d, unit/val max %d/%d, min %d/%d\n", 1021fc31e256SOr Gerlitz rl_caps->num_rates, rl_caps->max_unit, rl_caps->max_val, 1022fc31e256SOr Gerlitz rl_caps->min_unit, rl_caps->min_val); 1023fc31e256SOr Gerlitz } 1024fc31e256SOr Gerlitz 10255a2cc190SJeff Kirsher dump_dev_cap_flags(dev, dev_cap->flags); 1026b3416f44SShlomo Pongratz dump_dev_cap_flags2(dev, dev_cap->flags2); 10275a2cc190SJeff Kirsher } 10285a2cc190SJeff Kirsher 1029431df8c7SMatan Barak int mlx4_QUERY_PORT(struct mlx4_dev *dev, int port, struct mlx4_port_cap *port_cap) 1030431df8c7SMatan Barak { 1031431df8c7SMatan Barak struct mlx4_cmd_mailbox *mailbox; 1032431df8c7SMatan Barak u32 *outbox; 1033431df8c7SMatan Barak u8 field; 1034431df8c7SMatan Barak u32 field32; 1035431df8c7SMatan Barak int err; 1036431df8c7SMatan Barak 1037431df8c7SMatan Barak mailbox = mlx4_alloc_cmd_mailbox(dev); 1038431df8c7SMatan Barak if (IS_ERR(mailbox)) 1039431df8c7SMatan Barak return PTR_ERR(mailbox); 1040431df8c7SMatan Barak outbox = mailbox->buf; 1041431df8c7SMatan Barak 1042431df8c7SMatan Barak if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { 1043431df8c7SMatan Barak err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, 1044431df8c7SMatan Barak MLX4_CMD_TIME_CLASS_A, 1045431df8c7SMatan Barak MLX4_CMD_NATIVE); 1046431df8c7SMatan Barak 1047431df8c7SMatan Barak if (err) 1048431df8c7SMatan Barak goto out; 1049431df8c7SMatan Barak 1050431df8c7SMatan Barak MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); 1051431df8c7SMatan Barak port_cap->max_vl = field >> 4; 1052431df8c7SMatan Barak MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET); 1053431df8c7SMatan Barak port_cap->ib_mtu = field >> 4; 1054431df8c7SMatan Barak port_cap->max_port_width = field & 0xf; 1055431df8c7SMatan Barak MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET); 1056431df8c7SMatan Barak port_cap->max_gids = 1 << (field & 0xf); 1057431df8c7SMatan Barak MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET); 1058431df8c7SMatan Barak port_cap->max_pkeys = 1 << (field & 0xf); 1059431df8c7SMatan Barak } else { 1060431df8c7SMatan Barak #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00 1061431df8c7SMatan Barak #define QUERY_PORT_MTU_OFFSET 0x01 1062431df8c7SMatan Barak #define QUERY_PORT_ETH_MTU_OFFSET 0x02 1063431df8c7SMatan Barak #define QUERY_PORT_WIDTH_OFFSET 0x06 1064431df8c7SMatan Barak #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07 1065431df8c7SMatan Barak #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a 1066431df8c7SMatan Barak #define QUERY_PORT_MAX_VL_OFFSET 0x0b 1067431df8c7SMatan Barak #define QUERY_PORT_MAC_OFFSET 0x10 1068431df8c7SMatan Barak #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18 1069431df8c7SMatan Barak #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c 1070431df8c7SMatan Barak #define QUERY_PORT_TRANS_CODE_OFFSET 0x20 1071431df8c7SMatan Barak 1072431df8c7SMatan Barak err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0, MLX4_CMD_QUERY_PORT, 1073431df8c7SMatan Barak MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 1074431df8c7SMatan Barak if (err) 1075431df8c7SMatan Barak goto out; 1076431df8c7SMatan Barak 1077431df8c7SMatan Barak MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET); 1078431df8c7SMatan Barak port_cap->supported_port_types = field & 3; 1079431df8c7SMatan Barak port_cap->suggested_type = (field >> 3) & 1; 1080431df8c7SMatan Barak port_cap->default_sense = (field >> 4) & 1; 10817d077cd3SMatan Barak port_cap->dmfs_optimized_state = (field >> 5) & 1; 1082431df8c7SMatan Barak MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET); 1083431df8c7SMatan Barak port_cap->ib_mtu = field & 0xf; 1084431df8c7SMatan Barak MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET); 1085431df8c7SMatan Barak port_cap->max_port_width = field & 0xf; 1086431df8c7SMatan Barak MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET); 1087431df8c7SMatan Barak port_cap->max_gids = 1 << (field >> 4); 1088431df8c7SMatan Barak port_cap->max_pkeys = 1 << (field & 0xf); 1089431df8c7SMatan Barak MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET); 1090431df8c7SMatan Barak port_cap->max_vl = field & 0xf; 1091431df8c7SMatan Barak MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET); 1092431df8c7SMatan Barak port_cap->log_max_macs = field & 0xf; 1093431df8c7SMatan Barak port_cap->log_max_vlans = field >> 4; 1094431df8c7SMatan Barak MLX4_GET(port_cap->eth_mtu, outbox, QUERY_PORT_ETH_MTU_OFFSET); 1095431df8c7SMatan Barak MLX4_GET(port_cap->def_mac, outbox, QUERY_PORT_MAC_OFFSET); 1096431df8c7SMatan Barak MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET); 1097431df8c7SMatan Barak port_cap->trans_type = field32 >> 24; 1098431df8c7SMatan Barak port_cap->vendor_oui = field32 & 0xffffff; 1099431df8c7SMatan Barak MLX4_GET(port_cap->wavelength, outbox, QUERY_PORT_WAVELENGTH_OFFSET); 1100431df8c7SMatan Barak MLX4_GET(port_cap->trans_code, outbox, QUERY_PORT_TRANS_CODE_OFFSET); 1101431df8c7SMatan Barak } 1102431df8c7SMatan Barak 1103431df8c7SMatan Barak out: 1104431df8c7SMatan Barak mlx4_free_cmd_mailbox(dev, mailbox); 1105431df8c7SMatan Barak return err; 1106431df8c7SMatan Barak } 1107431df8c7SMatan Barak 11080b131561SMatan Barak #define DEV_CAP_EXT_2_FLAG_PFC_COUNTERS (1 << 28) 1109383677daSOr Gerlitz #define DEV_CAP_EXT_2_FLAG_VLAN_CONTROL (1 << 26) 1110383677daSOr Gerlitz #define DEV_CAP_EXT_2_FLAG_80_VFS (1 << 21) 1111383677daSOr Gerlitz #define DEV_CAP_EXT_2_FLAG_FSM (1 << 20) 1112383677daSOr Gerlitz 1113b91cb3ebSJack Morgenstein int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave, 1114b91cb3ebSJack Morgenstein struct mlx4_vhcr *vhcr, 1115b91cb3ebSJack Morgenstein struct mlx4_cmd_mailbox *inbox, 1116b91cb3ebSJack Morgenstein struct mlx4_cmd_mailbox *outbox, 1117b91cb3ebSJack Morgenstein struct mlx4_cmd_info *cmd) 1118b91cb3ebSJack Morgenstein { 11192a4fae14SJack Morgenstein u64 flags; 1120b91cb3ebSJack Morgenstein int err = 0; 1121b91cb3ebSJack Morgenstein u8 field; 1122fc31e256SOr Gerlitz u16 field16; 1123383677daSOr Gerlitz u32 bmme_flags, field32; 1124449fc488SMatan Barak int real_port; 1125449fc488SMatan Barak int slave_port; 1126449fc488SMatan Barak int first_port; 1127449fc488SMatan Barak struct mlx4_active_ports actv_ports; 1128b91cb3ebSJack Morgenstein 1129b91cb3ebSJack Morgenstein err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, 1130b91cb3ebSJack Morgenstein MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1131b91cb3ebSJack Morgenstein if (err) 1132b91cb3ebSJack Morgenstein return err; 1133b91cb3ebSJack Morgenstein 1134cc1ade94SShani Michaeli /* add port mng change event capability and disable mw type 1 1135cc1ade94SShani Michaeli * unconditionally to slaves 1136cc1ade94SShani Michaeli */ 11372a4fae14SJack Morgenstein MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); 11382a4fae14SJack Morgenstein flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV; 1139cc1ade94SShani Michaeli flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW; 1140449fc488SMatan Barak actv_ports = mlx4_get_active_ports(dev, slave); 1141449fc488SMatan Barak first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports); 1142449fc488SMatan Barak for (slave_port = 0, real_port = first_port; 1143449fc488SMatan Barak real_port < first_port + 1144449fc488SMatan Barak bitmap_weight(actv_ports.ports, dev->caps.num_ports); 1145449fc488SMatan Barak ++real_port, ++slave_port) { 1146449fc488SMatan Barak if (flags & (MLX4_DEV_CAP_FLAG_WOL_PORT1 << real_port)) 1147449fc488SMatan Barak flags |= MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port; 1148449fc488SMatan Barak else 1149449fc488SMatan Barak flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port); 1150449fc488SMatan Barak } 1151449fc488SMatan Barak for (; slave_port < dev->caps.num_ports; ++slave_port) 1152449fc488SMatan Barak flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port); 1153802f42a8SIdo Shamay 1154802f42a8SIdo Shamay /* Not exposing RSS IP fragments to guests */ 1155802f42a8SIdo Shamay flags &= ~MLX4_DEV_CAP_FLAG_RSS_IP_FRAG; 11562a4fae14SJack Morgenstein MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); 11572a4fae14SJack Morgenstein 1158449fc488SMatan Barak MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VL_PORT_OFFSET); 1159449fc488SMatan Barak field &= ~0x0F; 1160449fc488SMatan Barak field |= bitmap_weight(actv_ports.ports, dev->caps.num_ports) & 0x0F; 1161449fc488SMatan Barak MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VL_PORT_OFFSET); 1162449fc488SMatan Barak 116330b40c31SAmir Vadai /* For guests, disable timestamp */ 116430b40c31SAmir Vadai MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); 116530b40c31SAmir Vadai field &= 0x7f; 116630b40c31SAmir Vadai MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); 116730b40c31SAmir Vadai 11683742cc65SIdo Shamay /* For guests, disable vxlan tunneling and QoS support */ 116957352ef4SAmir Vadai MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VXLAN); 11703742cc65SIdo Shamay field &= 0xd7; 11717ffdf726SOr Gerlitz MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VXLAN); 11727ffdf726SOr Gerlitz 1173*51af33cfSIdo Shamay /* For guests, disable port BEACON */ 1174*51af33cfSIdo Shamay MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_PORT_BEACON_OFFSET); 1175*51af33cfSIdo Shamay field &= 0x7f; 1176*51af33cfSIdo Shamay MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_PORT_BEACON_OFFSET); 1177*51af33cfSIdo Shamay 1178b91cb3ebSJack Morgenstein /* For guests, report Blueflame disabled */ 1179b91cb3ebSJack Morgenstein MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET); 1180b91cb3ebSJack Morgenstein field &= 0x7f; 1181b91cb3ebSJack Morgenstein MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET); 1182b91cb3ebSJack Morgenstein 118359e14e32SMoni Shoua /* For guests, disable mw type 2 and port remap*/ 118457352ef4SAmir Vadai MLX4_GET(bmme_flags, outbox->buf, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); 1185cc1ade94SShani Michaeli bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN; 118659e14e32SMoni Shoua bmme_flags &= ~MLX4_FLAG_PORT_REMAP; 1187cc1ade94SShani Michaeli MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); 1188cc1ade94SShani Michaeli 11890081c8f3SJack Morgenstein /* turn off device-managed steering capability if not enabled */ 11900081c8f3SJack Morgenstein if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) { 11910081c8f3SJack Morgenstein MLX4_GET(field, outbox->buf, 11920081c8f3SJack Morgenstein QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); 11930081c8f3SJack Morgenstein field &= 0x7f; 11940081c8f3SJack Morgenstein MLX4_PUT(outbox->buf, field, 11950081c8f3SJack Morgenstein QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); 11960081c8f3SJack Morgenstein } 11974de65803SMatan Barak 11984de65803SMatan Barak /* turn off ipoib managed steering for guests */ 119957352ef4SAmir Vadai MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); 12004de65803SMatan Barak field &= ~0x80; 12014de65803SMatan Barak MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); 12024de65803SMatan Barak 1203383677daSOr Gerlitz /* turn off host side virt features (VST, FSM, etc) for guests */ 1204383677daSOr Gerlitz MLX4_GET(field32, outbox->buf, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); 1205383677daSOr Gerlitz field32 &= ~(DEV_CAP_EXT_2_FLAG_VLAN_CONTROL | DEV_CAP_EXT_2_FLAG_80_VFS | 12060b131561SMatan Barak DEV_CAP_EXT_2_FLAG_FSM | DEV_CAP_EXT_2_FLAG_PFC_COUNTERS); 1207383677daSOr Gerlitz MLX4_PUT(outbox->buf, field32, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); 1208383677daSOr Gerlitz 1209d237baa1SShani Michaeli /* turn off QCN for guests */ 1210d237baa1SShani Michaeli MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET); 1211d237baa1SShani Michaeli field &= 0xfe; 1212d237baa1SShani Michaeli MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET); 1213d237baa1SShani Michaeli 1214fc31e256SOr Gerlitz /* turn off QP max-rate limiting for guests */ 1215fc31e256SOr Gerlitz field16 = 0; 1216fc31e256SOr Gerlitz MLX4_PUT(outbox->buf, field16, QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET); 1217fc31e256SOr Gerlitz 1218d019fcb2SIdo Shamay /* turn off QoS per VF support for guests */ 1219d019fcb2SIdo Shamay MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE); 1220d019fcb2SIdo Shamay field &= 0xef; 1221d019fcb2SIdo Shamay MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE); 1222d019fcb2SIdo Shamay 1223b91cb3ebSJack Morgenstein return 0; 1224b91cb3ebSJack Morgenstein } 1225b91cb3ebSJack Morgenstein 12265cc914f1SMarcel Apfelbaum int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave, 12275cc914f1SMarcel Apfelbaum struct mlx4_vhcr *vhcr, 12285cc914f1SMarcel Apfelbaum struct mlx4_cmd_mailbox *inbox, 12295cc914f1SMarcel Apfelbaum struct mlx4_cmd_mailbox *outbox, 12305cc914f1SMarcel Apfelbaum struct mlx4_cmd_info *cmd) 12315cc914f1SMarcel Apfelbaum { 12320eb62b93SRony Efraim struct mlx4_priv *priv = mlx4_priv(dev); 12335cc914f1SMarcel Apfelbaum u64 def_mac; 12345cc914f1SMarcel Apfelbaum u8 port_type; 12356634961cSJack Morgenstein u16 short_field; 12365cc914f1SMarcel Apfelbaum int err; 1237948e306dSRony Efraim int admin_link_state; 1238449fc488SMatan Barak int port = mlx4_slave_convert_port(dev, slave, 1239449fc488SMatan Barak vhcr->in_modifier & 0xFF); 12405cc914f1SMarcel Apfelbaum 1241105c320fSJack Morgenstein #define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0 1242948e306dSRony Efraim #define MLX4_PORT_LINK_UP_MASK 0x80 12436634961cSJack Morgenstein #define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c 12446634961cSJack Morgenstein #define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e 124595f56e7aSYevgeny Petrilin 1246449fc488SMatan Barak if (port < 0) 1247449fc488SMatan Barak return -EINVAL; 1248449fc488SMatan Barak 1249a7401b9cSJack Morgenstein /* Protect against untrusted guests: enforce that this is the 1250a7401b9cSJack Morgenstein * QUERY_PORT general query. 1251a7401b9cSJack Morgenstein */ 1252a7401b9cSJack Morgenstein if (vhcr->op_modifier || vhcr->in_modifier & ~0xFF) 1253a7401b9cSJack Morgenstein return -EINVAL; 1254a7401b9cSJack Morgenstein 1255a7401b9cSJack Morgenstein vhcr->in_modifier = port; 1256449fc488SMatan Barak 12575cc914f1SMarcel Apfelbaum err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0, 12585cc914f1SMarcel Apfelbaum MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, 12595cc914f1SMarcel Apfelbaum MLX4_CMD_NATIVE); 12605cc914f1SMarcel Apfelbaum 12615cc914f1SMarcel Apfelbaum if (!err && dev->caps.function != slave) { 12620eb62b93SRony Efraim def_mac = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac; 12635cc914f1SMarcel Apfelbaum MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET); 12645cc914f1SMarcel Apfelbaum 12655cc914f1SMarcel Apfelbaum /* get port type - currently only eth is enabled */ 12665cc914f1SMarcel Apfelbaum MLX4_GET(port_type, outbox->buf, 12675cc914f1SMarcel Apfelbaum QUERY_PORT_SUPPORTED_TYPE_OFFSET); 12685cc914f1SMarcel Apfelbaum 1269105c320fSJack Morgenstein /* No link sensing allowed */ 1270105c320fSJack Morgenstein port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK; 1271105c320fSJack Morgenstein /* set port type to currently operating port type */ 1272105c320fSJack Morgenstein port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3); 12735cc914f1SMarcel Apfelbaum 1274948e306dSRony Efraim admin_link_state = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.link_state; 1275948e306dSRony Efraim if (IFLA_VF_LINK_STATE_ENABLE == admin_link_state) 1276948e306dSRony Efraim port_type |= MLX4_PORT_LINK_UP_MASK; 1277948e306dSRony Efraim else if (IFLA_VF_LINK_STATE_DISABLE == admin_link_state) 1278948e306dSRony Efraim port_type &= ~MLX4_PORT_LINK_UP_MASK; 1279948e306dSRony Efraim 12805cc914f1SMarcel Apfelbaum MLX4_PUT(outbox->buf, port_type, 12815cc914f1SMarcel Apfelbaum QUERY_PORT_SUPPORTED_TYPE_OFFSET); 12826634961cSJack Morgenstein 1283b6ffaeffSJack Morgenstein if (dev->caps.port_type[vhcr->in_modifier] == MLX4_PORT_TYPE_ETH) 1284449fc488SMatan Barak short_field = mlx4_get_slave_num_gids(dev, slave, port); 1285b6ffaeffSJack Morgenstein else 12866634961cSJack Morgenstein short_field = 1; /* slave max gids */ 12876634961cSJack Morgenstein MLX4_PUT(outbox->buf, short_field, 12886634961cSJack Morgenstein QUERY_PORT_CUR_MAX_GID_OFFSET); 12896634961cSJack Morgenstein 12906634961cSJack Morgenstein short_field = dev->caps.pkey_table_len[vhcr->in_modifier]; 12916634961cSJack Morgenstein MLX4_PUT(outbox->buf, short_field, 12926634961cSJack Morgenstein QUERY_PORT_CUR_MAX_PKEY_OFFSET); 12935cc914f1SMarcel Apfelbaum } 12945cc914f1SMarcel Apfelbaum 12955cc914f1SMarcel Apfelbaum return err; 12965cc914f1SMarcel Apfelbaum } 12975cc914f1SMarcel Apfelbaum 12986634961cSJack Morgenstein int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port, 12996634961cSJack Morgenstein int *gid_tbl_len, int *pkey_tbl_len) 13006634961cSJack Morgenstein { 13016634961cSJack Morgenstein struct mlx4_cmd_mailbox *mailbox; 13026634961cSJack Morgenstein u32 *outbox; 13036634961cSJack Morgenstein u16 field; 13046634961cSJack Morgenstein int err; 13056634961cSJack Morgenstein 13066634961cSJack Morgenstein mailbox = mlx4_alloc_cmd_mailbox(dev); 13076634961cSJack Morgenstein if (IS_ERR(mailbox)) 13086634961cSJack Morgenstein return PTR_ERR(mailbox); 13096634961cSJack Morgenstein 13106634961cSJack Morgenstein err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0, 13116634961cSJack Morgenstein MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, 13126634961cSJack Morgenstein MLX4_CMD_WRAPPED); 13136634961cSJack Morgenstein if (err) 13146634961cSJack Morgenstein goto out; 13156634961cSJack Morgenstein 13166634961cSJack Morgenstein outbox = mailbox->buf; 13176634961cSJack Morgenstein 13186634961cSJack Morgenstein MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET); 13196634961cSJack Morgenstein *gid_tbl_len = field; 13206634961cSJack Morgenstein 13216634961cSJack Morgenstein MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET); 13226634961cSJack Morgenstein *pkey_tbl_len = field; 13236634961cSJack Morgenstein 13246634961cSJack Morgenstein out: 13256634961cSJack Morgenstein mlx4_free_cmd_mailbox(dev, mailbox); 13266634961cSJack Morgenstein return err; 13276634961cSJack Morgenstein } 13286634961cSJack Morgenstein EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len); 13296634961cSJack Morgenstein 13305a2cc190SJeff Kirsher int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt) 13315a2cc190SJeff Kirsher { 13325a2cc190SJeff Kirsher struct mlx4_cmd_mailbox *mailbox; 13335a2cc190SJeff Kirsher struct mlx4_icm_iter iter; 13345a2cc190SJeff Kirsher __be64 *pages; 13355a2cc190SJeff Kirsher int lg; 13365a2cc190SJeff Kirsher int nent = 0; 13375a2cc190SJeff Kirsher int i; 13385a2cc190SJeff Kirsher int err = 0; 13395a2cc190SJeff Kirsher int ts = 0, tc = 0; 13405a2cc190SJeff Kirsher 13415a2cc190SJeff Kirsher mailbox = mlx4_alloc_cmd_mailbox(dev); 13425a2cc190SJeff Kirsher if (IS_ERR(mailbox)) 13435a2cc190SJeff Kirsher return PTR_ERR(mailbox); 13445a2cc190SJeff Kirsher pages = mailbox->buf; 13455a2cc190SJeff Kirsher 13465a2cc190SJeff Kirsher for (mlx4_icm_first(icm, &iter); 13475a2cc190SJeff Kirsher !mlx4_icm_last(&iter); 13485a2cc190SJeff Kirsher mlx4_icm_next(&iter)) { 13495a2cc190SJeff Kirsher /* 13505a2cc190SJeff Kirsher * We have to pass pages that are aligned to their 13515a2cc190SJeff Kirsher * size, so find the least significant 1 in the 13525a2cc190SJeff Kirsher * address or size and use that as our log2 size. 13535a2cc190SJeff Kirsher */ 13545a2cc190SJeff Kirsher lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1; 13555a2cc190SJeff Kirsher if (lg < MLX4_ICM_PAGE_SHIFT) { 13561a91de28SJoe Perches mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx)\n", 13575a2cc190SJeff Kirsher MLX4_ICM_PAGE_SIZE, 13585a2cc190SJeff Kirsher (unsigned long long) mlx4_icm_addr(&iter), 13595a2cc190SJeff Kirsher mlx4_icm_size(&iter)); 13605a2cc190SJeff Kirsher err = -EINVAL; 13615a2cc190SJeff Kirsher goto out; 13625a2cc190SJeff Kirsher } 13635a2cc190SJeff Kirsher 13645a2cc190SJeff Kirsher for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) { 13655a2cc190SJeff Kirsher if (virt != -1) { 13665a2cc190SJeff Kirsher pages[nent * 2] = cpu_to_be64(virt); 13675a2cc190SJeff Kirsher virt += 1 << lg; 13685a2cc190SJeff Kirsher } 13695a2cc190SJeff Kirsher 13705a2cc190SJeff Kirsher pages[nent * 2 + 1] = 13715a2cc190SJeff Kirsher cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) | 13725a2cc190SJeff Kirsher (lg - MLX4_ICM_PAGE_SHIFT)); 13735a2cc190SJeff Kirsher ts += 1 << (lg - 10); 13745a2cc190SJeff Kirsher ++tc; 13755a2cc190SJeff Kirsher 13765a2cc190SJeff Kirsher if (++nent == MLX4_MAILBOX_SIZE / 16) { 13775a2cc190SJeff Kirsher err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, 1378f9baff50SJack Morgenstein MLX4_CMD_TIME_CLASS_B, 1379f9baff50SJack Morgenstein MLX4_CMD_NATIVE); 13805a2cc190SJeff Kirsher if (err) 13815a2cc190SJeff Kirsher goto out; 13825a2cc190SJeff Kirsher nent = 0; 13835a2cc190SJeff Kirsher } 13845a2cc190SJeff Kirsher } 13855a2cc190SJeff Kirsher } 13865a2cc190SJeff Kirsher 13875a2cc190SJeff Kirsher if (nent) 1388f9baff50SJack Morgenstein err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, 1389f9baff50SJack Morgenstein MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 13905a2cc190SJeff Kirsher if (err) 13915a2cc190SJeff Kirsher goto out; 13925a2cc190SJeff Kirsher 13935a2cc190SJeff Kirsher switch (op) { 13945a2cc190SJeff Kirsher case MLX4_CMD_MAP_FA: 13951a91de28SJoe Perches mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW\n", tc, ts); 13965a2cc190SJeff Kirsher break; 13975a2cc190SJeff Kirsher case MLX4_CMD_MAP_ICM_AUX: 13981a91de28SJoe Perches mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux\n", tc, ts); 13995a2cc190SJeff Kirsher break; 14005a2cc190SJeff Kirsher case MLX4_CMD_MAP_ICM: 14011a91de28SJoe Perches mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM\n", 14025a2cc190SJeff Kirsher tc, ts, (unsigned long long) virt - (ts << 10)); 14035a2cc190SJeff Kirsher break; 14045a2cc190SJeff Kirsher } 14055a2cc190SJeff Kirsher 14065a2cc190SJeff Kirsher out: 14075a2cc190SJeff Kirsher mlx4_free_cmd_mailbox(dev, mailbox); 14085a2cc190SJeff Kirsher return err; 14095a2cc190SJeff Kirsher } 14105a2cc190SJeff Kirsher 14115a2cc190SJeff Kirsher int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm) 14125a2cc190SJeff Kirsher { 14135a2cc190SJeff Kirsher return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1); 14145a2cc190SJeff Kirsher } 14155a2cc190SJeff Kirsher 14165a2cc190SJeff Kirsher int mlx4_UNMAP_FA(struct mlx4_dev *dev) 14175a2cc190SJeff Kirsher { 1418f9baff50SJack Morgenstein return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA, 1419f9baff50SJack Morgenstein MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 14205a2cc190SJeff Kirsher } 14215a2cc190SJeff Kirsher 14225a2cc190SJeff Kirsher 14235a2cc190SJeff Kirsher int mlx4_RUN_FW(struct mlx4_dev *dev) 14245a2cc190SJeff Kirsher { 1425f9baff50SJack Morgenstein return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW, 1426f9baff50SJack Morgenstein MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 14275a2cc190SJeff Kirsher } 14285a2cc190SJeff Kirsher 14295a2cc190SJeff Kirsher int mlx4_QUERY_FW(struct mlx4_dev *dev) 14305a2cc190SJeff Kirsher { 14315a2cc190SJeff Kirsher struct mlx4_fw *fw = &mlx4_priv(dev)->fw; 14325a2cc190SJeff Kirsher struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd; 14335a2cc190SJeff Kirsher struct mlx4_cmd_mailbox *mailbox; 14345a2cc190SJeff Kirsher u32 *outbox; 14355a2cc190SJeff Kirsher int err = 0; 14365a2cc190SJeff Kirsher u64 fw_ver; 14375a2cc190SJeff Kirsher u16 cmd_if_rev; 14385a2cc190SJeff Kirsher u8 lg; 14395a2cc190SJeff Kirsher 14405a2cc190SJeff Kirsher #define QUERY_FW_OUT_SIZE 0x100 14415a2cc190SJeff Kirsher #define QUERY_FW_VER_OFFSET 0x00 14425cc914f1SMarcel Apfelbaum #define QUERY_FW_PPF_ID 0x09 14435a2cc190SJeff Kirsher #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a 14445a2cc190SJeff Kirsher #define QUERY_FW_MAX_CMD_OFFSET 0x0f 14455a2cc190SJeff Kirsher #define QUERY_FW_ERR_START_OFFSET 0x30 14465a2cc190SJeff Kirsher #define QUERY_FW_ERR_SIZE_OFFSET 0x38 14475a2cc190SJeff Kirsher #define QUERY_FW_ERR_BAR_OFFSET 0x3c 14485a2cc190SJeff Kirsher 14495a2cc190SJeff Kirsher #define QUERY_FW_SIZE_OFFSET 0x00 14505a2cc190SJeff Kirsher #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20 14515a2cc190SJeff Kirsher #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28 14525a2cc190SJeff Kirsher 14535cc914f1SMarcel Apfelbaum #define QUERY_FW_COMM_BASE_OFFSET 0x40 14545cc914f1SMarcel Apfelbaum #define QUERY_FW_COMM_BAR_OFFSET 0x48 14555cc914f1SMarcel Apfelbaum 1456ddd8a6c1SEugenia Emantayev #define QUERY_FW_CLOCK_OFFSET 0x50 1457ddd8a6c1SEugenia Emantayev #define QUERY_FW_CLOCK_BAR 0x58 1458ddd8a6c1SEugenia Emantayev 14595a2cc190SJeff Kirsher mailbox = mlx4_alloc_cmd_mailbox(dev); 14605a2cc190SJeff Kirsher if (IS_ERR(mailbox)) 14615a2cc190SJeff Kirsher return PTR_ERR(mailbox); 14625a2cc190SJeff Kirsher outbox = mailbox->buf; 14635a2cc190SJeff Kirsher 14645a2cc190SJeff Kirsher err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW, 1465f9baff50SJack Morgenstein MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 14665a2cc190SJeff Kirsher if (err) 14675a2cc190SJeff Kirsher goto out; 14685a2cc190SJeff Kirsher 14695a2cc190SJeff Kirsher MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET); 14705a2cc190SJeff Kirsher /* 14715a2cc190SJeff Kirsher * FW subminor version is at more significant bits than minor 14725a2cc190SJeff Kirsher * version, so swap here. 14735a2cc190SJeff Kirsher */ 14745a2cc190SJeff Kirsher dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) | 14755a2cc190SJeff Kirsher ((fw_ver & 0xffff0000ull) >> 16) | 14765a2cc190SJeff Kirsher ((fw_ver & 0x0000ffffull) << 16); 14775a2cc190SJeff Kirsher 1478752a50caSJack Morgenstein MLX4_GET(lg, outbox, QUERY_FW_PPF_ID); 1479752a50caSJack Morgenstein dev->caps.function = lg; 1480752a50caSJack Morgenstein 1481b91cb3ebSJack Morgenstein if (mlx4_is_slave(dev)) 1482b91cb3ebSJack Morgenstein goto out; 1483b91cb3ebSJack Morgenstein 14845cc914f1SMarcel Apfelbaum 14855a2cc190SJeff Kirsher MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET); 14865a2cc190SJeff Kirsher if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV || 14875a2cc190SJeff Kirsher cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) { 14881a91de28SJoe Perches mlx4_err(dev, "Installed FW has unsupported command interface revision %d\n", 14895a2cc190SJeff Kirsher cmd_if_rev); 14905a2cc190SJeff Kirsher mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n", 14915a2cc190SJeff Kirsher (int) (dev->caps.fw_ver >> 32), 14925a2cc190SJeff Kirsher (int) (dev->caps.fw_ver >> 16) & 0xffff, 14935a2cc190SJeff Kirsher (int) dev->caps.fw_ver & 0xffff); 14941a91de28SJoe Perches mlx4_err(dev, "This driver version supports only revisions %d to %d\n", 14955a2cc190SJeff Kirsher MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV); 14965a2cc190SJeff Kirsher err = -ENODEV; 14975a2cc190SJeff Kirsher goto out; 14985a2cc190SJeff Kirsher } 14995a2cc190SJeff Kirsher 15005a2cc190SJeff Kirsher if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS) 15015a2cc190SJeff Kirsher dev->flags |= MLX4_FLAG_OLD_PORT_CMDS; 15025a2cc190SJeff Kirsher 15035a2cc190SJeff Kirsher MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET); 15045a2cc190SJeff Kirsher cmd->max_cmds = 1 << lg; 15055a2cc190SJeff Kirsher 15065a2cc190SJeff Kirsher mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n", 15075a2cc190SJeff Kirsher (int) (dev->caps.fw_ver >> 32), 15085a2cc190SJeff Kirsher (int) (dev->caps.fw_ver >> 16) & 0xffff, 15095a2cc190SJeff Kirsher (int) dev->caps.fw_ver & 0xffff, 15105a2cc190SJeff Kirsher cmd_if_rev, cmd->max_cmds); 15115a2cc190SJeff Kirsher 15125a2cc190SJeff Kirsher MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET); 15135a2cc190SJeff Kirsher MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET); 15145a2cc190SJeff Kirsher MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET); 15155a2cc190SJeff Kirsher fw->catas_bar = (fw->catas_bar >> 6) * 2; 15165a2cc190SJeff Kirsher 15175a2cc190SJeff Kirsher mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n", 15185a2cc190SJeff Kirsher (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar); 15195a2cc190SJeff Kirsher 15205a2cc190SJeff Kirsher MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET); 15215a2cc190SJeff Kirsher MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET); 15225a2cc190SJeff Kirsher MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET); 15235a2cc190SJeff Kirsher fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2; 15245a2cc190SJeff Kirsher 15255cc914f1SMarcel Apfelbaum MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET); 15265cc914f1SMarcel Apfelbaum MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET); 15275cc914f1SMarcel Apfelbaum fw->comm_bar = (fw->comm_bar >> 6) * 2; 15285cc914f1SMarcel Apfelbaum mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n", 15295cc914f1SMarcel Apfelbaum fw->comm_bar, fw->comm_base); 15305a2cc190SJeff Kirsher mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2); 15315a2cc190SJeff Kirsher 1532ddd8a6c1SEugenia Emantayev MLX4_GET(fw->clock_offset, outbox, QUERY_FW_CLOCK_OFFSET); 1533ddd8a6c1SEugenia Emantayev MLX4_GET(fw->clock_bar, outbox, QUERY_FW_CLOCK_BAR); 1534ddd8a6c1SEugenia Emantayev fw->clock_bar = (fw->clock_bar >> 6) * 2; 1535ddd8a6c1SEugenia Emantayev mlx4_dbg(dev, "Internal clock bar:%d offset:0x%llx\n", 1536ddd8a6c1SEugenia Emantayev fw->clock_bar, fw->clock_offset); 1537ddd8a6c1SEugenia Emantayev 15385a2cc190SJeff Kirsher /* 15395a2cc190SJeff Kirsher * Round up number of system pages needed in case 15405a2cc190SJeff Kirsher * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. 15415a2cc190SJeff Kirsher */ 15425a2cc190SJeff Kirsher fw->fw_pages = 15435a2cc190SJeff Kirsher ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> 15445a2cc190SJeff Kirsher (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); 15455a2cc190SJeff Kirsher 15465a2cc190SJeff Kirsher mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n", 15475a2cc190SJeff Kirsher (unsigned long long) fw->clr_int_base, fw->clr_int_bar); 15485a2cc190SJeff Kirsher 15495a2cc190SJeff Kirsher out: 15505a2cc190SJeff Kirsher mlx4_free_cmd_mailbox(dev, mailbox); 15515a2cc190SJeff Kirsher return err; 15525a2cc190SJeff Kirsher } 15535a2cc190SJeff Kirsher 1554b91cb3ebSJack Morgenstein int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave, 1555b91cb3ebSJack Morgenstein struct mlx4_vhcr *vhcr, 1556b91cb3ebSJack Morgenstein struct mlx4_cmd_mailbox *inbox, 1557b91cb3ebSJack Morgenstein struct mlx4_cmd_mailbox *outbox, 1558b91cb3ebSJack Morgenstein struct mlx4_cmd_info *cmd) 1559b91cb3ebSJack Morgenstein { 1560b91cb3ebSJack Morgenstein u8 *outbuf; 1561b91cb3ebSJack Morgenstein int err; 1562b91cb3ebSJack Morgenstein 1563b91cb3ebSJack Morgenstein outbuf = outbox->buf; 1564b91cb3ebSJack Morgenstein err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW, 1565b91cb3ebSJack Morgenstein MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 1566b91cb3ebSJack Morgenstein if (err) 1567b91cb3ebSJack Morgenstein return err; 1568b91cb3ebSJack Morgenstein 1569752a50caSJack Morgenstein /* for slaves, set pci PPF ID to invalid and zero out everything 1570752a50caSJack Morgenstein * else except FW version */ 1571b91cb3ebSJack Morgenstein outbuf[0] = outbuf[1] = 0; 1572b91cb3ebSJack Morgenstein memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8); 1573752a50caSJack Morgenstein outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID; 1574752a50caSJack Morgenstein 1575b91cb3ebSJack Morgenstein return 0; 1576b91cb3ebSJack Morgenstein } 1577b91cb3ebSJack Morgenstein 15785a2cc190SJeff Kirsher static void get_board_id(void *vsd, char *board_id) 15795a2cc190SJeff Kirsher { 15805a2cc190SJeff Kirsher int i; 15815a2cc190SJeff Kirsher 15825a2cc190SJeff Kirsher #define VSD_OFFSET_SIG1 0x00 15835a2cc190SJeff Kirsher #define VSD_OFFSET_SIG2 0xde 15845a2cc190SJeff Kirsher #define VSD_OFFSET_MLX_BOARD_ID 0xd0 15855a2cc190SJeff Kirsher #define VSD_OFFSET_TS_BOARD_ID 0x20 15865a2cc190SJeff Kirsher 15875a2cc190SJeff Kirsher #define VSD_SIGNATURE_TOPSPIN 0x5ad 15885a2cc190SJeff Kirsher 15895a2cc190SJeff Kirsher memset(board_id, 0, MLX4_BOARD_ID_LEN); 15905a2cc190SJeff Kirsher 15915a2cc190SJeff Kirsher if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN && 15925a2cc190SJeff Kirsher be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) { 15935a2cc190SJeff Kirsher strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN); 15945a2cc190SJeff Kirsher } else { 15955a2cc190SJeff Kirsher /* 15965a2cc190SJeff Kirsher * The board ID is a string but the firmware byte 15975a2cc190SJeff Kirsher * swaps each 4-byte word before passing it back to 15985a2cc190SJeff Kirsher * us. Therefore we need to swab it before printing. 15995a2cc190SJeff Kirsher */ 16005a2cc190SJeff Kirsher for (i = 0; i < 4; ++i) 16015a2cc190SJeff Kirsher ((u32 *) board_id)[i] = 16025a2cc190SJeff Kirsher swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4)); 16035a2cc190SJeff Kirsher } 16045a2cc190SJeff Kirsher } 16055a2cc190SJeff Kirsher 16065a2cc190SJeff Kirsher int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter) 16075a2cc190SJeff Kirsher { 16085a2cc190SJeff Kirsher struct mlx4_cmd_mailbox *mailbox; 16095a2cc190SJeff Kirsher u32 *outbox; 16105a2cc190SJeff Kirsher int err; 16115a2cc190SJeff Kirsher 16125a2cc190SJeff Kirsher #define QUERY_ADAPTER_OUT_SIZE 0x100 16135a2cc190SJeff Kirsher #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10 16145a2cc190SJeff Kirsher #define QUERY_ADAPTER_VSD_OFFSET 0x20 16155a2cc190SJeff Kirsher 16165a2cc190SJeff Kirsher mailbox = mlx4_alloc_cmd_mailbox(dev); 16175a2cc190SJeff Kirsher if (IS_ERR(mailbox)) 16185a2cc190SJeff Kirsher return PTR_ERR(mailbox); 16195a2cc190SJeff Kirsher outbox = mailbox->buf; 16205a2cc190SJeff Kirsher 16215a2cc190SJeff Kirsher err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER, 1622f9baff50SJack Morgenstein MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 16235a2cc190SJeff Kirsher if (err) 16245a2cc190SJeff Kirsher goto out; 16255a2cc190SJeff Kirsher 16265a2cc190SJeff Kirsher MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET); 16275a2cc190SJeff Kirsher 16285a2cc190SJeff Kirsher get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4, 16295a2cc190SJeff Kirsher adapter->board_id); 16305a2cc190SJeff Kirsher 16315a2cc190SJeff Kirsher out: 16325a2cc190SJeff Kirsher mlx4_free_cmd_mailbox(dev, mailbox); 16335a2cc190SJeff Kirsher return err; 16345a2cc190SJeff Kirsher } 16355a2cc190SJeff Kirsher 16365a2cc190SJeff Kirsher int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param) 16375a2cc190SJeff Kirsher { 16385a2cc190SJeff Kirsher struct mlx4_cmd_mailbox *mailbox; 16395a2cc190SJeff Kirsher __be32 *inbox; 16405a2cc190SJeff Kirsher int err; 16417d077cd3SMatan Barak static const u8 a0_dmfs_hw_steering[] = { 16427d077cd3SMatan Barak [MLX4_STEERING_DMFS_A0_DEFAULT] = 0, 16437d077cd3SMatan Barak [MLX4_STEERING_DMFS_A0_DYNAMIC] = 1, 16447d077cd3SMatan Barak [MLX4_STEERING_DMFS_A0_STATIC] = 2, 16457d077cd3SMatan Barak [MLX4_STEERING_DMFS_A0_DISABLE] = 3 16467d077cd3SMatan Barak }; 16475a2cc190SJeff Kirsher 16485a2cc190SJeff Kirsher #define INIT_HCA_IN_SIZE 0x200 16495a2cc190SJeff Kirsher #define INIT_HCA_VERSION_OFFSET 0x000 16505a2cc190SJeff Kirsher #define INIT_HCA_VERSION 2 16517ffdf726SOr Gerlitz #define INIT_HCA_VXLAN_OFFSET 0x0c 16525a2cc190SJeff Kirsher #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e 16535a2cc190SJeff Kirsher #define INIT_HCA_FLAGS_OFFSET 0x014 1654be6a6b43SJack Morgenstein #define INIT_HCA_RECOVERABLE_ERROR_EVENT_OFFSET 0x018 16555a2cc190SJeff Kirsher #define INIT_HCA_QPC_OFFSET 0x020 16565a2cc190SJeff Kirsher #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10) 16575a2cc190SJeff Kirsher #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17) 16585a2cc190SJeff Kirsher #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28) 16595a2cc190SJeff Kirsher #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f) 16605a2cc190SJeff Kirsher #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30) 16615a2cc190SJeff Kirsher #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37) 16625cc914f1SMarcel Apfelbaum #define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38) 166377507aa2SIdo Shamay #define INIT_HCA_EQE_CQE_STRIDE_OFFSET (INIT_HCA_QPC_OFFSET + 0x3b) 16645a2cc190SJeff Kirsher #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40) 16655a2cc190SJeff Kirsher #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50) 16665a2cc190SJeff Kirsher #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60) 16675a2cc190SJeff Kirsher #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67) 16687ae0e400SMatan Barak #define INIT_HCA_NUM_SYS_EQS_OFFSET (INIT_HCA_QPC_OFFSET + 0x6a) 16695a2cc190SJeff Kirsher #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70) 16705a2cc190SJeff Kirsher #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77) 16715a2cc190SJeff Kirsher #define INIT_HCA_MCAST_OFFSET 0x0c0 16725a2cc190SJeff Kirsher #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00) 16735a2cc190SJeff Kirsher #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12) 16745a2cc190SJeff Kirsher #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16) 16755a2cc190SJeff Kirsher #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18) 16765a2cc190SJeff Kirsher #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b) 16770ff1fb65SHadar Hen Zion #define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6 16780ff1fb65SHadar Hen Zion #define INIT_HCA_FS_PARAM_OFFSET 0x1d0 16790ff1fb65SHadar Hen Zion #define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00) 16800ff1fb65SHadar Hen Zion #define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12) 16817d077cd3SMatan Barak #define INIT_HCA_FS_A0_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x18) 16820ff1fb65SHadar Hen Zion #define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b) 16830ff1fb65SHadar Hen Zion #define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21) 16840ff1fb65SHadar Hen Zion #define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22) 16850ff1fb65SHadar Hen Zion #define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25) 16860ff1fb65SHadar Hen Zion #define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26) 16875a2cc190SJeff Kirsher #define INIT_HCA_TPT_OFFSET 0x0f0 16885a2cc190SJeff Kirsher #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00) 1689e448834eSShani Michaeli #define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08) 16905a2cc190SJeff Kirsher #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b) 16915a2cc190SJeff Kirsher #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10) 16925a2cc190SJeff Kirsher #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18) 16935a2cc190SJeff Kirsher #define INIT_HCA_UAR_OFFSET 0x120 16945a2cc190SJeff Kirsher #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a) 16955a2cc190SJeff Kirsher #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b) 16965a2cc190SJeff Kirsher 16975a2cc190SJeff Kirsher mailbox = mlx4_alloc_cmd_mailbox(dev); 16985a2cc190SJeff Kirsher if (IS_ERR(mailbox)) 16995a2cc190SJeff Kirsher return PTR_ERR(mailbox); 17005a2cc190SJeff Kirsher inbox = mailbox->buf; 17015a2cc190SJeff Kirsher 17025a2cc190SJeff Kirsher *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION; 17035a2cc190SJeff Kirsher 17045a2cc190SJeff Kirsher *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) = 17055a2cc190SJeff Kirsher (ilog2(cache_line_size()) - 4) << 5; 17065a2cc190SJeff Kirsher 17075a2cc190SJeff Kirsher #if defined(__LITTLE_ENDIAN) 17085a2cc190SJeff Kirsher *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1); 17095a2cc190SJeff Kirsher #elif defined(__BIG_ENDIAN) 17105a2cc190SJeff Kirsher *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1); 17115a2cc190SJeff Kirsher #else 17125a2cc190SJeff Kirsher #error Host endianness not defined 17135a2cc190SJeff Kirsher #endif 17145a2cc190SJeff Kirsher /* Check port for UD address vector: */ 17155a2cc190SJeff Kirsher *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1); 17165a2cc190SJeff Kirsher 17175a2cc190SJeff Kirsher /* Enable IPoIB checksumming if we can: */ 17185a2cc190SJeff Kirsher if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM) 17195a2cc190SJeff Kirsher *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3); 17205a2cc190SJeff Kirsher 17215a2cc190SJeff Kirsher /* Enable QoS support if module parameter set */ 172238438f7cSIdo Shamay if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG && enable_qos) 17235a2cc190SJeff Kirsher *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2); 17245a2cc190SJeff Kirsher 17255a2cc190SJeff Kirsher /* enable counters */ 17265a2cc190SJeff Kirsher if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS) 17275a2cc190SJeff Kirsher *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4); 17285a2cc190SJeff Kirsher 1729802f42a8SIdo Shamay /* Enable RSS spread to fragmented IP packets when supported */ 1730802f42a8SIdo Shamay if (dev->caps.flags & MLX4_DEV_CAP_FLAG_RSS_IP_FRAG) 1731802f42a8SIdo Shamay *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 13); 1732802f42a8SIdo Shamay 173308ff3235SOr Gerlitz /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */ 173408ff3235SOr Gerlitz if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) { 173508ff3235SOr Gerlitz *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29); 173608ff3235SOr Gerlitz dev->caps.eqe_size = 64; 173708ff3235SOr Gerlitz dev->caps.eqe_factor = 1; 173808ff3235SOr Gerlitz } else { 173908ff3235SOr Gerlitz dev->caps.eqe_size = 32; 174008ff3235SOr Gerlitz dev->caps.eqe_factor = 0; 174108ff3235SOr Gerlitz } 174208ff3235SOr Gerlitz 174308ff3235SOr Gerlitz if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) { 174408ff3235SOr Gerlitz *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30); 174508ff3235SOr Gerlitz dev->caps.cqe_size = 64; 174677507aa2SIdo Shamay dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; 174708ff3235SOr Gerlitz } else { 174808ff3235SOr Gerlitz dev->caps.cqe_size = 32; 174908ff3235SOr Gerlitz } 175008ff3235SOr Gerlitz 175177507aa2SIdo Shamay /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */ 175277507aa2SIdo Shamay if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) && 175377507aa2SIdo Shamay (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE)) { 175477507aa2SIdo Shamay dev->caps.eqe_size = cache_line_size(); 175577507aa2SIdo Shamay dev->caps.cqe_size = cache_line_size(); 175677507aa2SIdo Shamay dev->caps.eqe_factor = 0; 175777507aa2SIdo Shamay MLX4_PUT(inbox, (u8)((ilog2(dev->caps.eqe_size) - 5) << 4 | 175877507aa2SIdo Shamay (ilog2(dev->caps.eqe_size) - 5)), 175977507aa2SIdo Shamay INIT_HCA_EQE_CQE_STRIDE_OFFSET); 176077507aa2SIdo Shamay 176177507aa2SIdo Shamay /* User still need to know to support CQE > 32B */ 176277507aa2SIdo Shamay dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; 176377507aa2SIdo Shamay } 176477507aa2SIdo Shamay 1765be6a6b43SJack Morgenstein if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT) 1766be6a6b43SJack Morgenstein *(inbox + INIT_HCA_RECOVERABLE_ERROR_EVENT_OFFSET / 4) |= cpu_to_be32(1 << 31); 1767be6a6b43SJack Morgenstein 17685a2cc190SJeff Kirsher /* QPC/EEC/CQC/EQC/RDMARC attributes */ 17695a2cc190SJeff Kirsher 17705a2cc190SJeff Kirsher MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET); 17715a2cc190SJeff Kirsher MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET); 17725a2cc190SJeff Kirsher MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET); 17735a2cc190SJeff Kirsher MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET); 17745a2cc190SJeff Kirsher MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET); 17755a2cc190SJeff Kirsher MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET); 17765a2cc190SJeff Kirsher MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET); 17775a2cc190SJeff Kirsher MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET); 17785a2cc190SJeff Kirsher MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET); 17795a2cc190SJeff Kirsher MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET); 17807ae0e400SMatan Barak MLX4_PUT(inbox, param->num_sys_eqs, INIT_HCA_NUM_SYS_EQS_OFFSET); 17815a2cc190SJeff Kirsher MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET); 17825a2cc190SJeff Kirsher MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET); 17835a2cc190SJeff Kirsher 17840ff1fb65SHadar Hen Zion /* steering attributes */ 17850ff1fb65SHadar Hen Zion if (dev->caps.steering_mode == 17860ff1fb65SHadar Hen Zion MLX4_STEERING_MODE_DEVICE_MANAGED) { 17870ff1fb65SHadar Hen Zion *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= 17880ff1fb65SHadar Hen Zion cpu_to_be32(1 << 17890ff1fb65SHadar Hen Zion INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN); 17905a2cc190SJeff Kirsher 17910ff1fb65SHadar Hen Zion MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET); 17920ff1fb65SHadar Hen Zion MLX4_PUT(inbox, param->log_mc_entry_sz, 17930ff1fb65SHadar Hen Zion INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET); 17940ff1fb65SHadar Hen Zion MLX4_PUT(inbox, param->log_mc_table_sz, 17950ff1fb65SHadar Hen Zion INIT_HCA_FS_LOG_TABLE_SZ_OFFSET); 17960ff1fb65SHadar Hen Zion /* Enable Ethernet flow steering 17970ff1fb65SHadar Hen Zion * with udp unicast and tcp unicast 17980ff1fb65SHadar Hen Zion */ 17997d077cd3SMatan Barak if (dev->caps.dmfs_high_steer_mode != 18007d077cd3SMatan Barak MLX4_STEERING_DMFS_A0_STATIC) 18017d077cd3SMatan Barak MLX4_PUT(inbox, 18027d077cd3SMatan Barak (u8)(MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN), 18030ff1fb65SHadar Hen Zion INIT_HCA_FS_ETH_BITS_OFFSET); 18040ff1fb65SHadar Hen Zion MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR, 18050ff1fb65SHadar Hen Zion INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET); 18060ff1fb65SHadar Hen Zion /* Enable IPoIB flow steering 18070ff1fb65SHadar Hen Zion * with udp unicast and tcp unicast 18080ff1fb65SHadar Hen Zion */ 180923537b73SHadar Hen Zion MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN), 18100ff1fb65SHadar Hen Zion INIT_HCA_FS_IB_BITS_OFFSET); 18110ff1fb65SHadar Hen Zion MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR, 18120ff1fb65SHadar Hen Zion INIT_HCA_FS_IB_NUM_ADDRS_OFFSET); 18137d077cd3SMatan Barak 18147d077cd3SMatan Barak if (dev->caps.dmfs_high_steer_mode != 18157d077cd3SMatan Barak MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) 18167d077cd3SMatan Barak MLX4_PUT(inbox, 18177d077cd3SMatan Barak ((u8)(a0_dmfs_hw_steering[dev->caps.dmfs_high_steer_mode] 18187d077cd3SMatan Barak << 6)), 18197d077cd3SMatan Barak INIT_HCA_FS_A0_OFFSET); 18200ff1fb65SHadar Hen Zion } else { 18215a2cc190SJeff Kirsher MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET); 18220ff1fb65SHadar Hen Zion MLX4_PUT(inbox, param->log_mc_entry_sz, 18230ff1fb65SHadar Hen Zion INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); 18240ff1fb65SHadar Hen Zion MLX4_PUT(inbox, param->log_mc_hash_sz, 18250ff1fb65SHadar Hen Zion INIT_HCA_LOG_MC_HASH_SZ_OFFSET); 18260ff1fb65SHadar Hen Zion MLX4_PUT(inbox, param->log_mc_table_sz, 18270ff1fb65SHadar Hen Zion INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); 1828c96d97f4SHadar Hen Zion if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0) 18290ff1fb65SHadar Hen Zion MLX4_PUT(inbox, (u8) (1 << 3), 18300ff1fb65SHadar Hen Zion INIT_HCA_UC_STEERING_OFFSET); 18310ff1fb65SHadar Hen Zion } 18325a2cc190SJeff Kirsher 18335a2cc190SJeff Kirsher /* TPT attributes */ 18345a2cc190SJeff Kirsher 18355a2cc190SJeff Kirsher MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET); 1836e448834eSShani Michaeli MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET); 18375a2cc190SJeff Kirsher MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET); 18385a2cc190SJeff Kirsher MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET); 18395a2cc190SJeff Kirsher MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET); 18405a2cc190SJeff Kirsher 18415a2cc190SJeff Kirsher /* UAR attributes */ 18425a2cc190SJeff Kirsher 1843ab9c17a0SJack Morgenstein MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET); 18445a2cc190SJeff Kirsher MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET); 18455a2cc190SJeff Kirsher 18467ffdf726SOr Gerlitz /* set parser VXLAN attributes */ 18477ffdf726SOr Gerlitz if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) { 18487ffdf726SOr Gerlitz u8 parser_params = 0; 18497ffdf726SOr Gerlitz MLX4_PUT(inbox, parser_params, INIT_HCA_VXLAN_OFFSET); 18507ffdf726SOr Gerlitz } 18517ffdf726SOr Gerlitz 18525a031086SJack Morgenstein err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 18535a031086SJack Morgenstein MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE); 18545a2cc190SJeff Kirsher 18555a2cc190SJeff Kirsher if (err) 18565a2cc190SJeff Kirsher mlx4_err(dev, "INIT_HCA returns %d\n", err); 18575a2cc190SJeff Kirsher 18585a2cc190SJeff Kirsher mlx4_free_cmd_mailbox(dev, mailbox); 18595a2cc190SJeff Kirsher return err; 18605a2cc190SJeff Kirsher } 18615a2cc190SJeff Kirsher 1862ab9c17a0SJack Morgenstein int mlx4_QUERY_HCA(struct mlx4_dev *dev, 1863ab9c17a0SJack Morgenstein struct mlx4_init_hca_param *param) 1864ab9c17a0SJack Morgenstein { 1865ab9c17a0SJack Morgenstein struct mlx4_cmd_mailbox *mailbox; 1866ab9c17a0SJack Morgenstein __be32 *outbox; 18677b8157beSJack Morgenstein u32 dword_field; 1868ab9c17a0SJack Morgenstein int err; 186908ff3235SOr Gerlitz u8 byte_field; 18707d077cd3SMatan Barak static const u8 a0_dmfs_query_hw_steering[] = { 18717d077cd3SMatan Barak [0] = MLX4_STEERING_DMFS_A0_DEFAULT, 18727d077cd3SMatan Barak [1] = MLX4_STEERING_DMFS_A0_DYNAMIC, 18737d077cd3SMatan Barak [2] = MLX4_STEERING_DMFS_A0_STATIC, 18747d077cd3SMatan Barak [3] = MLX4_STEERING_DMFS_A0_DISABLE 18757d077cd3SMatan Barak }; 1876ab9c17a0SJack Morgenstein 1877ab9c17a0SJack Morgenstein #define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04 1878ddd8a6c1SEugenia Emantayev #define QUERY_HCA_CORE_CLOCK_OFFSET 0x0c 1879ab9c17a0SJack Morgenstein 1880ab9c17a0SJack Morgenstein mailbox = mlx4_alloc_cmd_mailbox(dev); 1881ab9c17a0SJack Morgenstein if (IS_ERR(mailbox)) 1882ab9c17a0SJack Morgenstein return PTR_ERR(mailbox); 1883ab9c17a0SJack Morgenstein outbox = mailbox->buf; 1884ab9c17a0SJack Morgenstein 1885ab9c17a0SJack Morgenstein err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, 1886ab9c17a0SJack Morgenstein MLX4_CMD_QUERY_HCA, 1887ab9c17a0SJack Morgenstein MLX4_CMD_TIME_CLASS_B, 1888ab9c17a0SJack Morgenstein !mlx4_is_slave(dev)); 1889ab9c17a0SJack Morgenstein if (err) 1890ab9c17a0SJack Morgenstein goto out; 1891ab9c17a0SJack Morgenstein 1892ab9c17a0SJack Morgenstein MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET); 1893ddd8a6c1SEugenia Emantayev MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET); 1894ab9c17a0SJack Morgenstein 1895ab9c17a0SJack Morgenstein /* QPC/EEC/CQC/EQC/RDMARC attributes */ 1896ab9c17a0SJack Morgenstein 1897ab9c17a0SJack Morgenstein MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET); 1898ab9c17a0SJack Morgenstein MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET); 1899ab9c17a0SJack Morgenstein MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET); 1900ab9c17a0SJack Morgenstein MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET); 1901ab9c17a0SJack Morgenstein MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET); 1902ab9c17a0SJack Morgenstein MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET); 1903ab9c17a0SJack Morgenstein MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET); 1904ab9c17a0SJack Morgenstein MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET); 1905ab9c17a0SJack Morgenstein MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET); 1906ab9c17a0SJack Morgenstein MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET); 19077ae0e400SMatan Barak MLX4_GET(param->num_sys_eqs, outbox, INIT_HCA_NUM_SYS_EQS_OFFSET); 1908ab9c17a0SJack Morgenstein MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET); 1909ab9c17a0SJack Morgenstein MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET); 1910ab9c17a0SJack Morgenstein 19117b8157beSJack Morgenstein MLX4_GET(dword_field, outbox, INIT_HCA_FLAGS_OFFSET); 19127b8157beSJack Morgenstein if (dword_field & (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN)) { 19137b8157beSJack Morgenstein param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED; 19147b8157beSJack Morgenstein } else { 19157b8157beSJack Morgenstein MLX4_GET(byte_field, outbox, INIT_HCA_UC_STEERING_OFFSET); 19167b8157beSJack Morgenstein if (byte_field & 0x8) 19177b8157beSJack Morgenstein param->steering_mode = MLX4_STEERING_MODE_B0; 19187b8157beSJack Morgenstein else 19197b8157beSJack Morgenstein param->steering_mode = MLX4_STEERING_MODE_A0; 19207b8157beSJack Morgenstein } 1921802f42a8SIdo Shamay 1922802f42a8SIdo Shamay if (dword_field & (1 << 13)) 1923802f42a8SIdo Shamay param->rss_ip_frags = 1; 1924802f42a8SIdo Shamay 19250ff1fb65SHadar Hen Zion /* steering attributes */ 19267b8157beSJack Morgenstein if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) { 19270ff1fb65SHadar Hen Zion MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET); 19280ff1fb65SHadar Hen Zion MLX4_GET(param->log_mc_entry_sz, outbox, 19290ff1fb65SHadar Hen Zion INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET); 19300ff1fb65SHadar Hen Zion MLX4_GET(param->log_mc_table_sz, outbox, 19310ff1fb65SHadar Hen Zion INIT_HCA_FS_LOG_TABLE_SZ_OFFSET); 19327d077cd3SMatan Barak MLX4_GET(byte_field, outbox, 19337d077cd3SMatan Barak INIT_HCA_FS_A0_OFFSET); 19347d077cd3SMatan Barak param->dmfs_high_steer_mode = 19357d077cd3SMatan Barak a0_dmfs_query_hw_steering[(byte_field >> 6) & 3]; 19360ff1fb65SHadar Hen Zion } else { 1937ab9c17a0SJack Morgenstein MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET); 1938ab9c17a0SJack Morgenstein MLX4_GET(param->log_mc_entry_sz, outbox, 1939ab9c17a0SJack Morgenstein INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); 1940ab9c17a0SJack Morgenstein MLX4_GET(param->log_mc_hash_sz, outbox, 1941ab9c17a0SJack Morgenstein INIT_HCA_LOG_MC_HASH_SZ_OFFSET); 1942ab9c17a0SJack Morgenstein MLX4_GET(param->log_mc_table_sz, outbox, 1943ab9c17a0SJack Morgenstein INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); 19440ff1fb65SHadar Hen Zion } 1945ab9c17a0SJack Morgenstein 194608ff3235SOr Gerlitz /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */ 194708ff3235SOr Gerlitz MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS); 194808ff3235SOr Gerlitz if (byte_field & 0x20) /* 64-bytes eqe enabled */ 194908ff3235SOr Gerlitz param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED; 195008ff3235SOr Gerlitz if (byte_field & 0x40) /* 64-bytes cqe enabled */ 195108ff3235SOr Gerlitz param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED; 195208ff3235SOr Gerlitz 195377507aa2SIdo Shamay /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */ 195477507aa2SIdo Shamay MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_STRIDE_OFFSET); 195577507aa2SIdo Shamay if (byte_field) { 1956c3f2511fSIdo Shamay param->dev_cap_enabled |= MLX4_DEV_CAP_EQE_STRIDE_ENABLED; 1957c3f2511fSIdo Shamay param->dev_cap_enabled |= MLX4_DEV_CAP_CQE_STRIDE_ENABLED; 195877507aa2SIdo Shamay param->cqe_size = 1 << ((byte_field & 195977507aa2SIdo Shamay MLX4_CQE_SIZE_MASK_STRIDE) + 5); 196077507aa2SIdo Shamay param->eqe_size = 1 << (((byte_field & 196177507aa2SIdo Shamay MLX4_EQE_SIZE_MASK_STRIDE) >> 4) + 5); 196277507aa2SIdo Shamay } 196377507aa2SIdo Shamay 1964ab9c17a0SJack Morgenstein /* TPT attributes */ 1965ab9c17a0SJack Morgenstein 1966ab9c17a0SJack Morgenstein MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET); 1967e448834eSShani Michaeli MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET); 1968ab9c17a0SJack Morgenstein MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET); 1969ab9c17a0SJack Morgenstein MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET); 1970ab9c17a0SJack Morgenstein MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET); 1971ab9c17a0SJack Morgenstein 1972ab9c17a0SJack Morgenstein /* UAR attributes */ 1973ab9c17a0SJack Morgenstein 1974ab9c17a0SJack Morgenstein MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET); 1975ab9c17a0SJack Morgenstein MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET); 1976ab9c17a0SJack Morgenstein 1977ab9c17a0SJack Morgenstein out: 1978ab9c17a0SJack Morgenstein mlx4_free_cmd_mailbox(dev, mailbox); 1979ab9c17a0SJack Morgenstein 1980ab9c17a0SJack Morgenstein return err; 1981ab9c17a0SJack Morgenstein } 1982ab9c17a0SJack Morgenstein 19836d6e996cSMajd Dibbiny static int mlx4_hca_core_clock_update(struct mlx4_dev *dev) 19846d6e996cSMajd Dibbiny { 19856d6e996cSMajd Dibbiny struct mlx4_cmd_mailbox *mailbox; 19866d6e996cSMajd Dibbiny __be32 *outbox; 19876d6e996cSMajd Dibbiny int err; 19886d6e996cSMajd Dibbiny 19896d6e996cSMajd Dibbiny mailbox = mlx4_alloc_cmd_mailbox(dev); 19906d6e996cSMajd Dibbiny if (IS_ERR(mailbox)) { 19916d6e996cSMajd Dibbiny mlx4_warn(dev, "hca_core_clock mailbox allocation failed\n"); 19926d6e996cSMajd Dibbiny return PTR_ERR(mailbox); 19936d6e996cSMajd Dibbiny } 19946d6e996cSMajd Dibbiny outbox = mailbox->buf; 19956d6e996cSMajd Dibbiny 19966d6e996cSMajd Dibbiny err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, 19976d6e996cSMajd Dibbiny MLX4_CMD_QUERY_HCA, 19986d6e996cSMajd Dibbiny MLX4_CMD_TIME_CLASS_B, 19996d6e996cSMajd Dibbiny !mlx4_is_slave(dev)); 20006d6e996cSMajd Dibbiny if (err) { 20016d6e996cSMajd Dibbiny mlx4_warn(dev, "hca_core_clock update failed\n"); 20026d6e996cSMajd Dibbiny goto out; 20036d6e996cSMajd Dibbiny } 20046d6e996cSMajd Dibbiny 20056d6e996cSMajd Dibbiny MLX4_GET(dev->caps.hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET); 20066d6e996cSMajd Dibbiny 20076d6e996cSMajd Dibbiny out: 20086d6e996cSMajd Dibbiny mlx4_free_cmd_mailbox(dev, mailbox); 20096d6e996cSMajd Dibbiny 20106d6e996cSMajd Dibbiny return err; 20116d6e996cSMajd Dibbiny } 20126d6e996cSMajd Dibbiny 2013980e9001SJack Morgenstein /* for IB-type ports only in SRIOV mode. Checks that both proxy QP0 2014980e9001SJack Morgenstein * and real QP0 are active, so that the paravirtualized QP0 is ready 2015980e9001SJack Morgenstein * to operate */ 2016980e9001SJack Morgenstein static int check_qp0_state(struct mlx4_dev *dev, int function, int port) 2017980e9001SJack Morgenstein { 2018980e9001SJack Morgenstein struct mlx4_priv *priv = mlx4_priv(dev); 2019980e9001SJack Morgenstein /* irrelevant if not infiniband */ 2020980e9001SJack Morgenstein if (priv->mfunc.master.qp0_state[port].proxy_qp0_active && 2021980e9001SJack Morgenstein priv->mfunc.master.qp0_state[port].qp0_active) 2022980e9001SJack Morgenstein return 1; 2023980e9001SJack Morgenstein return 0; 2024980e9001SJack Morgenstein } 2025980e9001SJack Morgenstein 20265cc914f1SMarcel Apfelbaum int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave, 20275cc914f1SMarcel Apfelbaum struct mlx4_vhcr *vhcr, 20285cc914f1SMarcel Apfelbaum struct mlx4_cmd_mailbox *inbox, 20295cc914f1SMarcel Apfelbaum struct mlx4_cmd_mailbox *outbox, 20305cc914f1SMarcel Apfelbaum struct mlx4_cmd_info *cmd) 20315cc914f1SMarcel Apfelbaum { 20325cc914f1SMarcel Apfelbaum struct mlx4_priv *priv = mlx4_priv(dev); 2033449fc488SMatan Barak int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier); 20345cc914f1SMarcel Apfelbaum int err; 20355cc914f1SMarcel Apfelbaum 2036449fc488SMatan Barak if (port < 0) 2037449fc488SMatan Barak return -EINVAL; 2038449fc488SMatan Barak 20395cc914f1SMarcel Apfelbaum if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port)) 20405cc914f1SMarcel Apfelbaum return 0; 20415cc914f1SMarcel Apfelbaum 2042980e9001SJack Morgenstein if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) { 20435cc914f1SMarcel Apfelbaum /* Enable port only if it was previously disabled */ 20445cc914f1SMarcel Apfelbaum if (!priv->mfunc.master.init_port_ref[port]) { 20455cc914f1SMarcel Apfelbaum err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, 20465cc914f1SMarcel Apfelbaum MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 20475cc914f1SMarcel Apfelbaum if (err) 20485cc914f1SMarcel Apfelbaum return err; 20495cc914f1SMarcel Apfelbaum } 20508bac9edeSJack Morgenstein priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); 2051980e9001SJack Morgenstein } else { 2052980e9001SJack Morgenstein if (slave == mlx4_master_func_num(dev)) { 2053980e9001SJack Morgenstein if (check_qp0_state(dev, slave, port) && 2054980e9001SJack Morgenstein !priv->mfunc.master.qp0_state[port].port_active) { 2055980e9001SJack Morgenstein err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, 2056980e9001SJack Morgenstein MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2057980e9001SJack Morgenstein if (err) 2058980e9001SJack Morgenstein return err; 2059980e9001SJack Morgenstein priv->mfunc.master.qp0_state[port].port_active = 1; 2060980e9001SJack Morgenstein priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); 2061980e9001SJack Morgenstein } 2062980e9001SJack Morgenstein } else 2063980e9001SJack Morgenstein priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); 2064980e9001SJack Morgenstein } 20655cc914f1SMarcel Apfelbaum ++priv->mfunc.master.init_port_ref[port]; 20665cc914f1SMarcel Apfelbaum return 0; 20675cc914f1SMarcel Apfelbaum } 20685cc914f1SMarcel Apfelbaum 20695a2cc190SJeff Kirsher int mlx4_INIT_PORT(struct mlx4_dev *dev, int port) 20705a2cc190SJeff Kirsher { 20715a2cc190SJeff Kirsher struct mlx4_cmd_mailbox *mailbox; 20725a2cc190SJeff Kirsher u32 *inbox; 20735a2cc190SJeff Kirsher int err; 20745a2cc190SJeff Kirsher u32 flags; 20755a2cc190SJeff Kirsher u16 field; 20765a2cc190SJeff Kirsher 20775a2cc190SJeff Kirsher if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { 20785a2cc190SJeff Kirsher #define INIT_PORT_IN_SIZE 256 20795a2cc190SJeff Kirsher #define INIT_PORT_FLAGS_OFFSET 0x00 20805a2cc190SJeff Kirsher #define INIT_PORT_FLAG_SIG (1 << 18) 20815a2cc190SJeff Kirsher #define INIT_PORT_FLAG_NG (1 << 17) 20825a2cc190SJeff Kirsher #define INIT_PORT_FLAG_G0 (1 << 16) 20835a2cc190SJeff Kirsher #define INIT_PORT_VL_SHIFT 4 20845a2cc190SJeff Kirsher #define INIT_PORT_PORT_WIDTH_SHIFT 8 20855a2cc190SJeff Kirsher #define INIT_PORT_MTU_OFFSET 0x04 20865a2cc190SJeff Kirsher #define INIT_PORT_MAX_GID_OFFSET 0x06 20875a2cc190SJeff Kirsher #define INIT_PORT_MAX_PKEY_OFFSET 0x0a 20885a2cc190SJeff Kirsher #define INIT_PORT_GUID0_OFFSET 0x10 20895a2cc190SJeff Kirsher #define INIT_PORT_NODE_GUID_OFFSET 0x18 20905a2cc190SJeff Kirsher #define INIT_PORT_SI_GUID_OFFSET 0x20 20915a2cc190SJeff Kirsher 20925a2cc190SJeff Kirsher mailbox = mlx4_alloc_cmd_mailbox(dev); 20935a2cc190SJeff Kirsher if (IS_ERR(mailbox)) 20945a2cc190SJeff Kirsher return PTR_ERR(mailbox); 20955a2cc190SJeff Kirsher inbox = mailbox->buf; 20965a2cc190SJeff Kirsher 20975a2cc190SJeff Kirsher flags = 0; 20985a2cc190SJeff Kirsher flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT; 20995a2cc190SJeff Kirsher flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT; 21005a2cc190SJeff Kirsher MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET); 21015a2cc190SJeff Kirsher 21025a2cc190SJeff Kirsher field = 128 << dev->caps.ib_mtu_cap[port]; 21035a2cc190SJeff Kirsher MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET); 21045a2cc190SJeff Kirsher field = dev->caps.gid_table_len[port]; 21055a2cc190SJeff Kirsher MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET); 21065a2cc190SJeff Kirsher field = dev->caps.pkey_table_len[port]; 21075a2cc190SJeff Kirsher MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET); 21085a2cc190SJeff Kirsher 21095a2cc190SJeff Kirsher err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT, 2110f9baff50SJack Morgenstein MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 21115a2cc190SJeff Kirsher 21125a2cc190SJeff Kirsher mlx4_free_cmd_mailbox(dev, mailbox); 21135a2cc190SJeff Kirsher } else 21145a2cc190SJeff Kirsher err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, 2115f9baff50SJack Morgenstein MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 21165a2cc190SJeff Kirsher 21176d6e996cSMajd Dibbiny if (!err) 21186d6e996cSMajd Dibbiny mlx4_hca_core_clock_update(dev); 21196d6e996cSMajd Dibbiny 21205a2cc190SJeff Kirsher return err; 21215a2cc190SJeff Kirsher } 21225a2cc190SJeff Kirsher EXPORT_SYMBOL_GPL(mlx4_INIT_PORT); 21235a2cc190SJeff Kirsher 21245cc914f1SMarcel Apfelbaum int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave, 21255cc914f1SMarcel Apfelbaum struct mlx4_vhcr *vhcr, 21265cc914f1SMarcel Apfelbaum struct mlx4_cmd_mailbox *inbox, 21275cc914f1SMarcel Apfelbaum struct mlx4_cmd_mailbox *outbox, 21285cc914f1SMarcel Apfelbaum struct mlx4_cmd_info *cmd) 21295cc914f1SMarcel Apfelbaum { 21305cc914f1SMarcel Apfelbaum struct mlx4_priv *priv = mlx4_priv(dev); 2131449fc488SMatan Barak int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier); 21325cc914f1SMarcel Apfelbaum int err; 21335cc914f1SMarcel Apfelbaum 2134449fc488SMatan Barak if (port < 0) 2135449fc488SMatan Barak return -EINVAL; 2136449fc488SMatan Barak 21375cc914f1SMarcel Apfelbaum if (!(priv->mfunc.master.slave_state[slave].init_port_mask & 21385cc914f1SMarcel Apfelbaum (1 << port))) 21395cc914f1SMarcel Apfelbaum return 0; 21405cc914f1SMarcel Apfelbaum 2141980e9001SJack Morgenstein if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) { 21425cc914f1SMarcel Apfelbaum if (priv->mfunc.master.init_port_ref[port] == 1) { 2143980e9001SJack Morgenstein err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 21445a031086SJack Morgenstein MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 21455cc914f1SMarcel Apfelbaum if (err) 21465cc914f1SMarcel Apfelbaum return err; 21475cc914f1SMarcel Apfelbaum } 21485cc914f1SMarcel Apfelbaum priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); 2149980e9001SJack Morgenstein } else { 2150980e9001SJack Morgenstein /* infiniband port */ 2151980e9001SJack Morgenstein if (slave == mlx4_master_func_num(dev)) { 2152980e9001SJack Morgenstein if (!priv->mfunc.master.qp0_state[port].qp0_active && 2153980e9001SJack Morgenstein priv->mfunc.master.qp0_state[port].port_active) { 2154980e9001SJack Morgenstein err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 21555a031086SJack Morgenstein MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2156980e9001SJack Morgenstein if (err) 2157980e9001SJack Morgenstein return err; 2158980e9001SJack Morgenstein priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); 2159980e9001SJack Morgenstein priv->mfunc.master.qp0_state[port].port_active = 0; 2160980e9001SJack Morgenstein } 2161980e9001SJack Morgenstein } else 2162980e9001SJack Morgenstein priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); 2163980e9001SJack Morgenstein } 21645cc914f1SMarcel Apfelbaum --priv->mfunc.master.init_port_ref[port]; 21655cc914f1SMarcel Apfelbaum return 0; 21665cc914f1SMarcel Apfelbaum } 21675cc914f1SMarcel Apfelbaum 21685a2cc190SJeff Kirsher int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port) 21695a2cc190SJeff Kirsher { 21705a031086SJack Morgenstein return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 21715a031086SJack Morgenstein MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 21725a2cc190SJeff Kirsher } 21735a2cc190SJeff Kirsher EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT); 21745a2cc190SJeff Kirsher 21755a2cc190SJeff Kirsher int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic) 21765a2cc190SJeff Kirsher { 21775a031086SJack Morgenstein return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 21785a031086SJack Morgenstein MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE); 21795a2cc190SJeff Kirsher } 21805a2cc190SJeff Kirsher 2181d18f141aSOr Gerlitz struct mlx4_config_dev { 2182d18f141aSOr Gerlitz __be32 update_flags; 2183d475c95bSMatan Barak __be32 rsvd1[3]; 2184d18f141aSOr Gerlitz __be16 vxlan_udp_dport; 2185d18f141aSOr Gerlitz __be16 rsvd2; 218659e14e32SMoni Shoua __be32 rsvd3; 218759e14e32SMoni Shoua __be32 roce_flags; 218859e14e32SMoni Shoua __be32 rsvd4[25]; 218959e14e32SMoni Shoua __be16 rsvd5; 219059e14e32SMoni Shoua u8 rsvd6; 2191d475c95bSMatan Barak u8 rx_checksum_val; 2192d18f141aSOr Gerlitz }; 2193d18f141aSOr Gerlitz 2194d18f141aSOr Gerlitz #define MLX4_VXLAN_UDP_DPORT (1 << 0) 219559e14e32SMoni Shoua #define MLX4_DISABLE_RX_PORT BIT(18) 2196d18f141aSOr Gerlitz 2197d475c95bSMatan Barak static int mlx4_CONFIG_DEV_set(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev) 2198d18f141aSOr Gerlitz { 2199d18f141aSOr Gerlitz int err; 2200d18f141aSOr Gerlitz struct mlx4_cmd_mailbox *mailbox; 2201d18f141aSOr Gerlitz 2202d18f141aSOr Gerlitz mailbox = mlx4_alloc_cmd_mailbox(dev); 2203d18f141aSOr Gerlitz if (IS_ERR(mailbox)) 2204d18f141aSOr Gerlitz return PTR_ERR(mailbox); 2205d18f141aSOr Gerlitz 2206d18f141aSOr Gerlitz memcpy(mailbox->buf, config_dev, sizeof(*config_dev)); 2207d18f141aSOr Gerlitz 2208d18f141aSOr Gerlitz err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_CONFIG_DEV, 2209d18f141aSOr Gerlitz MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 2210d18f141aSOr Gerlitz 2211d18f141aSOr Gerlitz mlx4_free_cmd_mailbox(dev, mailbox); 2212d18f141aSOr Gerlitz return err; 2213d18f141aSOr Gerlitz } 2214d18f141aSOr Gerlitz 2215d475c95bSMatan Barak static int mlx4_CONFIG_DEV_get(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev) 2216d475c95bSMatan Barak { 2217d475c95bSMatan Barak int err; 2218d475c95bSMatan Barak struct mlx4_cmd_mailbox *mailbox; 2219d475c95bSMatan Barak 2220d475c95bSMatan Barak mailbox = mlx4_alloc_cmd_mailbox(dev); 2221d475c95bSMatan Barak if (IS_ERR(mailbox)) 2222d475c95bSMatan Barak return PTR_ERR(mailbox); 2223d475c95bSMatan Barak 2224d475c95bSMatan Barak err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 1, MLX4_CMD_CONFIG_DEV, 2225d475c95bSMatan Barak MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 2226d475c95bSMatan Barak 2227d475c95bSMatan Barak if (!err) 2228d475c95bSMatan Barak memcpy(config_dev, mailbox->buf, sizeof(*config_dev)); 2229d475c95bSMatan Barak 2230d475c95bSMatan Barak mlx4_free_cmd_mailbox(dev, mailbox); 2231d475c95bSMatan Barak return err; 2232d475c95bSMatan Barak } 2233d475c95bSMatan Barak 2234d475c95bSMatan Barak /* Conversion between the HW values and the actual functionality. 2235d475c95bSMatan Barak * The value represented by the array index, 2236d475c95bSMatan Barak * and the functionality determined by the flags. 2237d475c95bSMatan Barak */ 2238d475c95bSMatan Barak static const u8 config_dev_csum_flags[] = { 2239d475c95bSMatan Barak [0] = 0, 2240d475c95bSMatan Barak [1] = MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP, 2241d475c95bSMatan Barak [2] = MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP | 2242d475c95bSMatan Barak MLX4_RX_CSUM_MODE_L4, 2243d475c95bSMatan Barak [3] = MLX4_RX_CSUM_MODE_L4 | 2244d475c95bSMatan Barak MLX4_RX_CSUM_MODE_IP_OK_IP_NON_TCP_UDP | 2245d475c95bSMatan Barak MLX4_RX_CSUM_MODE_MULTI_VLAN 2246d475c95bSMatan Barak }; 2247d475c95bSMatan Barak 2248d475c95bSMatan Barak int mlx4_config_dev_retrieval(struct mlx4_dev *dev, 2249d475c95bSMatan Barak struct mlx4_config_dev_params *params) 2250d475c95bSMatan Barak { 22516af0a52fSMaor Gottlieb struct mlx4_config_dev config_dev = {0}; 2252d475c95bSMatan Barak int err; 2253d475c95bSMatan Barak u8 csum_mask; 2254d475c95bSMatan Barak 2255d475c95bSMatan Barak #define CONFIG_DEV_RX_CSUM_MODE_MASK 0x7 2256d475c95bSMatan Barak #define CONFIG_DEV_RX_CSUM_MODE_PORT1_BIT_OFFSET 0 2257d475c95bSMatan Barak #define CONFIG_DEV_RX_CSUM_MODE_PORT2_BIT_OFFSET 4 2258d475c95bSMatan Barak 2259d475c95bSMatan Barak if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CONFIG_DEV)) 2260d475c95bSMatan Barak return -ENOTSUPP; 2261d475c95bSMatan Barak 2262d475c95bSMatan Barak err = mlx4_CONFIG_DEV_get(dev, &config_dev); 2263d475c95bSMatan Barak if (err) 2264d475c95bSMatan Barak return err; 2265d475c95bSMatan Barak 2266d475c95bSMatan Barak csum_mask = (config_dev.rx_checksum_val >> CONFIG_DEV_RX_CSUM_MODE_PORT1_BIT_OFFSET) & 2267d475c95bSMatan Barak CONFIG_DEV_RX_CSUM_MODE_MASK; 2268d475c95bSMatan Barak 2269d475c95bSMatan Barak if (csum_mask >= sizeof(config_dev_csum_flags)/sizeof(config_dev_csum_flags[0])) 2270d475c95bSMatan Barak return -EINVAL; 2271d475c95bSMatan Barak params->rx_csum_flags_port_1 = config_dev_csum_flags[csum_mask]; 2272d475c95bSMatan Barak 2273d475c95bSMatan Barak csum_mask = (config_dev.rx_checksum_val >> CONFIG_DEV_RX_CSUM_MODE_PORT2_BIT_OFFSET) & 2274d475c95bSMatan Barak CONFIG_DEV_RX_CSUM_MODE_MASK; 2275d475c95bSMatan Barak 2276d475c95bSMatan Barak if (csum_mask >= sizeof(config_dev_csum_flags)/sizeof(config_dev_csum_flags[0])) 2277d475c95bSMatan Barak return -EINVAL; 2278d475c95bSMatan Barak params->rx_csum_flags_port_2 = config_dev_csum_flags[csum_mask]; 2279d475c95bSMatan Barak 2280d475c95bSMatan Barak params->vxlan_udp_dport = be16_to_cpu(config_dev.vxlan_udp_dport); 2281d475c95bSMatan Barak 2282d475c95bSMatan Barak return 0; 2283d475c95bSMatan Barak } 2284d475c95bSMatan Barak EXPORT_SYMBOL_GPL(mlx4_config_dev_retrieval); 2285d475c95bSMatan Barak 2286d18f141aSOr Gerlitz int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port) 2287d18f141aSOr Gerlitz { 2288d18f141aSOr Gerlitz struct mlx4_config_dev config_dev; 2289d18f141aSOr Gerlitz 2290d18f141aSOr Gerlitz memset(&config_dev, 0, sizeof(config_dev)); 2291d18f141aSOr Gerlitz config_dev.update_flags = cpu_to_be32(MLX4_VXLAN_UDP_DPORT); 2292d18f141aSOr Gerlitz config_dev.vxlan_udp_dport = udp_port; 2293d18f141aSOr Gerlitz 2294d475c95bSMatan Barak return mlx4_CONFIG_DEV_set(dev, &config_dev); 2295d18f141aSOr Gerlitz } 2296d18f141aSOr Gerlitz EXPORT_SYMBOL_GPL(mlx4_config_vxlan_port); 2297d18f141aSOr Gerlitz 229859e14e32SMoni Shoua #define CONFIG_DISABLE_RX_PORT BIT(15) 229959e14e32SMoni Shoua int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis) 230059e14e32SMoni Shoua { 230159e14e32SMoni Shoua struct mlx4_config_dev config_dev; 230259e14e32SMoni Shoua 230359e14e32SMoni Shoua memset(&config_dev, 0, sizeof(config_dev)); 230459e14e32SMoni Shoua config_dev.update_flags = cpu_to_be32(MLX4_DISABLE_RX_PORT); 230559e14e32SMoni Shoua if (dis) 230659e14e32SMoni Shoua config_dev.roce_flags = 230759e14e32SMoni Shoua cpu_to_be32(CONFIG_DISABLE_RX_PORT); 230859e14e32SMoni Shoua 230959e14e32SMoni Shoua return mlx4_CONFIG_DEV_set(dev, &config_dev); 231059e14e32SMoni Shoua } 231159e14e32SMoni Shoua 231259e14e32SMoni Shoua int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2) 231359e14e32SMoni Shoua { 231459e14e32SMoni Shoua struct mlx4_cmd_mailbox *mailbox; 231559e14e32SMoni Shoua struct { 231659e14e32SMoni Shoua __be32 v_port1; 231759e14e32SMoni Shoua __be32 v_port2; 231859e14e32SMoni Shoua } *v2p; 231959e14e32SMoni Shoua int err; 232059e14e32SMoni Shoua 232159e14e32SMoni Shoua mailbox = mlx4_alloc_cmd_mailbox(dev); 232259e14e32SMoni Shoua if (IS_ERR(mailbox)) 232359e14e32SMoni Shoua return -ENOMEM; 232459e14e32SMoni Shoua 232559e14e32SMoni Shoua v2p = mailbox->buf; 232659e14e32SMoni Shoua v2p->v_port1 = cpu_to_be32(port1); 232759e14e32SMoni Shoua v2p->v_port2 = cpu_to_be32(port2); 232859e14e32SMoni Shoua 232959e14e32SMoni Shoua err = mlx4_cmd(dev, mailbox->dma, 0, 233059e14e32SMoni Shoua MLX4_SET_PORT_VIRT2PHY, MLX4_CMD_VIRT_PORT_MAP, 233159e14e32SMoni Shoua MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 233259e14e32SMoni Shoua 233359e14e32SMoni Shoua mlx4_free_cmd_mailbox(dev, mailbox); 233459e14e32SMoni Shoua return err; 233559e14e32SMoni Shoua } 233659e14e32SMoni Shoua 2337d18f141aSOr Gerlitz 23385a2cc190SJeff Kirsher int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages) 23395a2cc190SJeff Kirsher { 23405a2cc190SJeff Kirsher int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0, 23415a2cc190SJeff Kirsher MLX4_CMD_SET_ICM_SIZE, 2342f9baff50SJack Morgenstein MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 23435a2cc190SJeff Kirsher if (ret) 23445a2cc190SJeff Kirsher return ret; 23455a2cc190SJeff Kirsher 23465a2cc190SJeff Kirsher /* 23475a2cc190SJeff Kirsher * Round up number of system pages needed in case 23485a2cc190SJeff Kirsher * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. 23495a2cc190SJeff Kirsher */ 23505a2cc190SJeff Kirsher *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> 23515a2cc190SJeff Kirsher (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); 23525a2cc190SJeff Kirsher 23535a2cc190SJeff Kirsher return 0; 23545a2cc190SJeff Kirsher } 23555a2cc190SJeff Kirsher 23565a2cc190SJeff Kirsher int mlx4_NOP(struct mlx4_dev *dev) 23575a2cc190SJeff Kirsher { 23585a2cc190SJeff Kirsher /* Input modifier of 0x1f means "finish as soon as possible." */ 23595a031086SJack Morgenstein return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, MLX4_CMD_TIME_CLASS_A, 23605a031086SJack Morgenstein MLX4_CMD_NATIVE); 23615a2cc190SJeff Kirsher } 23625a2cc190SJeff Kirsher 23638e1a28e8SHadar Hen Zion int mlx4_get_phys_port_id(struct mlx4_dev *dev) 23648e1a28e8SHadar Hen Zion { 23658e1a28e8SHadar Hen Zion u8 port; 23668e1a28e8SHadar Hen Zion u32 *outbox; 23678e1a28e8SHadar Hen Zion struct mlx4_cmd_mailbox *mailbox; 23688e1a28e8SHadar Hen Zion u32 in_mod; 23698e1a28e8SHadar Hen Zion u32 guid_hi, guid_lo; 23708e1a28e8SHadar Hen Zion int err, ret = 0; 23718e1a28e8SHadar Hen Zion #define MOD_STAT_CFG_PORT_OFFSET 8 23728e1a28e8SHadar Hen Zion #define MOD_STAT_CFG_GUID_H 0X14 23738e1a28e8SHadar Hen Zion #define MOD_STAT_CFG_GUID_L 0X1c 23748e1a28e8SHadar Hen Zion 23758e1a28e8SHadar Hen Zion mailbox = mlx4_alloc_cmd_mailbox(dev); 23768e1a28e8SHadar Hen Zion if (IS_ERR(mailbox)) 23778e1a28e8SHadar Hen Zion return PTR_ERR(mailbox); 23788e1a28e8SHadar Hen Zion outbox = mailbox->buf; 23798e1a28e8SHadar Hen Zion 23808e1a28e8SHadar Hen Zion for (port = 1; port <= dev->caps.num_ports; port++) { 23818e1a28e8SHadar Hen Zion in_mod = port << MOD_STAT_CFG_PORT_OFFSET; 23828e1a28e8SHadar Hen Zion err = mlx4_cmd_box(dev, 0, mailbox->dma, in_mod, 0x2, 23838e1a28e8SHadar Hen Zion MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A, 23848e1a28e8SHadar Hen Zion MLX4_CMD_NATIVE); 23858e1a28e8SHadar Hen Zion if (err) { 23868e1a28e8SHadar Hen Zion mlx4_err(dev, "Fail to get port %d uplink guid\n", 23878e1a28e8SHadar Hen Zion port); 23888e1a28e8SHadar Hen Zion ret = err; 23898e1a28e8SHadar Hen Zion } else { 23908e1a28e8SHadar Hen Zion MLX4_GET(guid_hi, outbox, MOD_STAT_CFG_GUID_H); 23918e1a28e8SHadar Hen Zion MLX4_GET(guid_lo, outbox, MOD_STAT_CFG_GUID_L); 23928e1a28e8SHadar Hen Zion dev->caps.phys_port_id[port] = (u64)guid_lo | 23938e1a28e8SHadar Hen Zion (u64)guid_hi << 32; 23948e1a28e8SHadar Hen Zion } 23958e1a28e8SHadar Hen Zion } 23968e1a28e8SHadar Hen Zion mlx4_free_cmd_mailbox(dev, mailbox); 23978e1a28e8SHadar Hen Zion return ret; 23988e1a28e8SHadar Hen Zion } 23998e1a28e8SHadar Hen Zion 24005a2cc190SJeff Kirsher #define MLX4_WOL_SETUP_MODE (5 << 28) 24015a2cc190SJeff Kirsher int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port) 24025a2cc190SJeff Kirsher { 24035a2cc190SJeff Kirsher u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8; 24045a2cc190SJeff Kirsher 24055a2cc190SJeff Kirsher return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3, 2406f9baff50SJack Morgenstein MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A, 2407f9baff50SJack Morgenstein MLX4_CMD_NATIVE); 24085a2cc190SJeff Kirsher } 24095a2cc190SJeff Kirsher EXPORT_SYMBOL_GPL(mlx4_wol_read); 24105a2cc190SJeff Kirsher 24115a2cc190SJeff Kirsher int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port) 24125a2cc190SJeff Kirsher { 24135a2cc190SJeff Kirsher u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8; 24145a2cc190SJeff Kirsher 24155a2cc190SJeff Kirsher return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG, 2416f9baff50SJack Morgenstein MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); 24175a2cc190SJeff Kirsher } 24185a2cc190SJeff Kirsher EXPORT_SYMBOL_GPL(mlx4_wol_write); 2419fe6f700dSYevgeny Petrilin 2420fe6f700dSYevgeny Petrilin enum { 2421fe6f700dSYevgeny Petrilin ADD_TO_MCG = 0x26, 2422fe6f700dSYevgeny Petrilin }; 2423fe6f700dSYevgeny Petrilin 2424fe6f700dSYevgeny Petrilin 2425fe6f700dSYevgeny Petrilin void mlx4_opreq_action(struct work_struct *work) 2426fe6f700dSYevgeny Petrilin { 2427fe6f700dSYevgeny Petrilin struct mlx4_priv *priv = container_of(work, struct mlx4_priv, 2428fe6f700dSYevgeny Petrilin opreq_task); 2429fe6f700dSYevgeny Petrilin struct mlx4_dev *dev = &priv->dev; 2430fe6f700dSYevgeny Petrilin int num_tasks = atomic_read(&priv->opreq_count); 2431fe6f700dSYevgeny Petrilin struct mlx4_cmd_mailbox *mailbox; 2432fe6f700dSYevgeny Petrilin struct mlx4_mgm *mgm; 2433fe6f700dSYevgeny Petrilin u32 *outbox; 2434fe6f700dSYevgeny Petrilin u32 modifier; 2435fe6f700dSYevgeny Petrilin u16 token; 2436fe6f700dSYevgeny Petrilin u16 type; 2437fe6f700dSYevgeny Petrilin int err; 2438fe6f700dSYevgeny Petrilin u32 num_qps; 2439fe6f700dSYevgeny Petrilin struct mlx4_qp qp; 2440fe6f700dSYevgeny Petrilin int i; 2441fe6f700dSYevgeny Petrilin u8 rem_mcg; 2442fe6f700dSYevgeny Petrilin u8 prot; 2443fe6f700dSYevgeny Petrilin 2444fe6f700dSYevgeny Petrilin #define GET_OP_REQ_MODIFIER_OFFSET 0x08 2445fe6f700dSYevgeny Petrilin #define GET_OP_REQ_TOKEN_OFFSET 0x14 2446fe6f700dSYevgeny Petrilin #define GET_OP_REQ_TYPE_OFFSET 0x1a 2447fe6f700dSYevgeny Petrilin #define GET_OP_REQ_DATA_OFFSET 0x20 2448fe6f700dSYevgeny Petrilin 2449fe6f700dSYevgeny Petrilin mailbox = mlx4_alloc_cmd_mailbox(dev); 2450fe6f700dSYevgeny Petrilin if (IS_ERR(mailbox)) { 2451fe6f700dSYevgeny Petrilin mlx4_err(dev, "Failed to allocate mailbox for GET_OP_REQ\n"); 2452fe6f700dSYevgeny Petrilin return; 2453fe6f700dSYevgeny Petrilin } 2454fe6f700dSYevgeny Petrilin outbox = mailbox->buf; 2455fe6f700dSYevgeny Petrilin 2456fe6f700dSYevgeny Petrilin while (num_tasks) { 2457fe6f700dSYevgeny Petrilin err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, 2458fe6f700dSYevgeny Petrilin MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A, 2459fe6f700dSYevgeny Petrilin MLX4_CMD_NATIVE); 2460fe6f700dSYevgeny Petrilin if (err) { 24616d3be300SMasanari Iida mlx4_err(dev, "Failed to retrieve required operation: %d\n", 2462fe6f700dSYevgeny Petrilin err); 2463fe6f700dSYevgeny Petrilin return; 2464fe6f700dSYevgeny Petrilin } 2465fe6f700dSYevgeny Petrilin MLX4_GET(modifier, outbox, GET_OP_REQ_MODIFIER_OFFSET); 2466fe6f700dSYevgeny Petrilin MLX4_GET(token, outbox, GET_OP_REQ_TOKEN_OFFSET); 2467fe6f700dSYevgeny Petrilin MLX4_GET(type, outbox, GET_OP_REQ_TYPE_OFFSET); 2468fe6f700dSYevgeny Petrilin type &= 0xfff; 2469fe6f700dSYevgeny Petrilin 2470fe6f700dSYevgeny Petrilin switch (type) { 2471fe6f700dSYevgeny Petrilin case ADD_TO_MCG: 2472fe6f700dSYevgeny Petrilin if (dev->caps.steering_mode == 2473fe6f700dSYevgeny Petrilin MLX4_STEERING_MODE_DEVICE_MANAGED) { 2474fe6f700dSYevgeny Petrilin mlx4_warn(dev, "ADD MCG operation is not supported in DEVICE_MANAGED steering mode\n"); 2475fe6f700dSYevgeny Petrilin err = EPERM; 2476fe6f700dSYevgeny Petrilin break; 2477fe6f700dSYevgeny Petrilin } 2478fe6f700dSYevgeny Petrilin mgm = (struct mlx4_mgm *)((u8 *)(outbox) + 2479fe6f700dSYevgeny Petrilin GET_OP_REQ_DATA_OFFSET); 2480fe6f700dSYevgeny Petrilin num_qps = be32_to_cpu(mgm->members_count) & 2481fe6f700dSYevgeny Petrilin MGM_QPN_MASK; 2482fe6f700dSYevgeny Petrilin rem_mcg = ((u8 *)(&mgm->members_count))[0] & 1; 2483fe6f700dSYevgeny Petrilin prot = ((u8 *)(&mgm->members_count))[0] >> 6; 2484fe6f700dSYevgeny Petrilin 2485fe6f700dSYevgeny Petrilin for (i = 0; i < num_qps; i++) { 2486fe6f700dSYevgeny Petrilin qp.qpn = be32_to_cpu(mgm->qp[i]); 2487fe6f700dSYevgeny Petrilin if (rem_mcg) 2488fe6f700dSYevgeny Petrilin err = mlx4_multicast_detach(dev, &qp, 2489fe6f700dSYevgeny Petrilin mgm->gid, 2490fe6f700dSYevgeny Petrilin prot, 0); 2491fe6f700dSYevgeny Petrilin else 2492fe6f700dSYevgeny Petrilin err = mlx4_multicast_attach(dev, &qp, 2493fe6f700dSYevgeny Petrilin mgm->gid, 2494fe6f700dSYevgeny Petrilin mgm->gid[5] 2495fe6f700dSYevgeny Petrilin , 0, prot, 2496fe6f700dSYevgeny Petrilin NULL); 2497fe6f700dSYevgeny Petrilin if (err) 2498fe6f700dSYevgeny Petrilin break; 2499fe6f700dSYevgeny Petrilin } 2500fe6f700dSYevgeny Petrilin break; 2501fe6f700dSYevgeny Petrilin default: 2502fe6f700dSYevgeny Petrilin mlx4_warn(dev, "Bad type for required operation\n"); 2503fe6f700dSYevgeny Petrilin err = EINVAL; 2504fe6f700dSYevgeny Petrilin break; 2505fe6f700dSYevgeny Petrilin } 250628d222bbSEyal Perry err = mlx4_cmd(dev, 0, ((u32) err | 250728d222bbSEyal Perry (__force u32)cpu_to_be32(token) << 16), 2508fe6f700dSYevgeny Petrilin 1, MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A, 2509fe6f700dSYevgeny Petrilin MLX4_CMD_NATIVE); 2510fe6f700dSYevgeny Petrilin if (err) { 2511fe6f700dSYevgeny Petrilin mlx4_err(dev, "Failed to acknowledge required request: %d\n", 2512fe6f700dSYevgeny Petrilin err); 2513fe6f700dSYevgeny Petrilin goto out; 2514fe6f700dSYevgeny Petrilin } 2515fe6f700dSYevgeny Petrilin memset(outbox, 0, 0xffc); 2516fe6f700dSYevgeny Petrilin num_tasks = atomic_dec_return(&priv->opreq_count); 2517fe6f700dSYevgeny Petrilin } 2518fe6f700dSYevgeny Petrilin 2519fe6f700dSYevgeny Petrilin out: 2520fe6f700dSYevgeny Petrilin mlx4_free_cmd_mailbox(dev, mailbox); 2521fe6f700dSYevgeny Petrilin } 2522114840c3SJack Morgenstein 2523114840c3SJack Morgenstein static int mlx4_check_smp_firewall_active(struct mlx4_dev *dev, 2524114840c3SJack Morgenstein struct mlx4_cmd_mailbox *mailbox) 2525114840c3SJack Morgenstein { 2526114840c3SJack Morgenstein #define MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET 0x10 2527114840c3SJack Morgenstein #define MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET 0x20 2528114840c3SJack Morgenstein #define MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET 0x40 2529114840c3SJack Morgenstein #define MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET 0x70 2530114840c3SJack Morgenstein 2531114840c3SJack Morgenstein u32 set_attr_mask, getresp_attr_mask; 2532114840c3SJack Morgenstein u32 trap_attr_mask, traprepress_attr_mask; 2533114840c3SJack Morgenstein 2534114840c3SJack Morgenstein MLX4_GET(set_attr_mask, mailbox->buf, 2535114840c3SJack Morgenstein MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET); 2536114840c3SJack Morgenstein mlx4_dbg(dev, "SMP firewall set_attribute_mask = 0x%x\n", 2537114840c3SJack Morgenstein set_attr_mask); 2538114840c3SJack Morgenstein 2539114840c3SJack Morgenstein MLX4_GET(getresp_attr_mask, mailbox->buf, 2540114840c3SJack Morgenstein MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET); 2541114840c3SJack Morgenstein mlx4_dbg(dev, "SMP firewall getresp_attribute_mask = 0x%x\n", 2542114840c3SJack Morgenstein getresp_attr_mask); 2543114840c3SJack Morgenstein 2544114840c3SJack Morgenstein MLX4_GET(trap_attr_mask, mailbox->buf, 2545114840c3SJack Morgenstein MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET); 2546114840c3SJack Morgenstein mlx4_dbg(dev, "SMP firewall trap_attribute_mask = 0x%x\n", 2547114840c3SJack Morgenstein trap_attr_mask); 2548114840c3SJack Morgenstein 2549114840c3SJack Morgenstein MLX4_GET(traprepress_attr_mask, mailbox->buf, 2550114840c3SJack Morgenstein MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET); 2551114840c3SJack Morgenstein mlx4_dbg(dev, "SMP firewall traprepress_attribute_mask = 0x%x\n", 2552114840c3SJack Morgenstein traprepress_attr_mask); 2553114840c3SJack Morgenstein 2554114840c3SJack Morgenstein if (set_attr_mask && getresp_attr_mask && trap_attr_mask && 2555114840c3SJack Morgenstein traprepress_attr_mask) 2556114840c3SJack Morgenstein return 1; 2557114840c3SJack Morgenstein 2558114840c3SJack Morgenstein return 0; 2559114840c3SJack Morgenstein } 2560114840c3SJack Morgenstein 2561114840c3SJack Morgenstein int mlx4_config_mad_demux(struct mlx4_dev *dev) 2562114840c3SJack Morgenstein { 2563114840c3SJack Morgenstein struct mlx4_cmd_mailbox *mailbox; 2564114840c3SJack Morgenstein int secure_host_active; 2565114840c3SJack Morgenstein int err; 2566114840c3SJack Morgenstein 2567114840c3SJack Morgenstein /* Check if mad_demux is supported */ 2568114840c3SJack Morgenstein if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_MAD_DEMUX)) 2569114840c3SJack Morgenstein return 0; 2570114840c3SJack Morgenstein 2571114840c3SJack Morgenstein mailbox = mlx4_alloc_cmd_mailbox(dev); 2572114840c3SJack Morgenstein if (IS_ERR(mailbox)) { 2573114840c3SJack Morgenstein mlx4_warn(dev, "Failed to allocate mailbox for cmd MAD_DEMUX"); 2574114840c3SJack Morgenstein return -ENOMEM; 2575114840c3SJack Morgenstein } 2576114840c3SJack Morgenstein 2577114840c3SJack Morgenstein /* Query mad_demux to find out which MADs are handled by internal sma */ 2578114840c3SJack Morgenstein err = mlx4_cmd_box(dev, 0, mailbox->dma, 0x01 /* subn mgmt class */, 2579114840c3SJack Morgenstein MLX4_CMD_MAD_DEMUX_QUERY_RESTR, MLX4_CMD_MAD_DEMUX, 2580114840c3SJack Morgenstein MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 2581114840c3SJack Morgenstein if (err) { 2582114840c3SJack Morgenstein mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: query restrictions failed (%d)\n", 2583114840c3SJack Morgenstein err); 2584114840c3SJack Morgenstein goto out; 2585114840c3SJack Morgenstein } 2586114840c3SJack Morgenstein 2587114840c3SJack Morgenstein secure_host_active = mlx4_check_smp_firewall_active(dev, mailbox); 2588114840c3SJack Morgenstein 2589114840c3SJack Morgenstein /* Config mad_demux to handle all MADs returned by the query above */ 2590114840c3SJack Morgenstein err = mlx4_cmd(dev, mailbox->dma, 0x01 /* subn mgmt class */, 2591114840c3SJack Morgenstein MLX4_CMD_MAD_DEMUX_CONFIG, MLX4_CMD_MAD_DEMUX, 2592114840c3SJack Morgenstein MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 2593114840c3SJack Morgenstein if (err) { 2594114840c3SJack Morgenstein mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: configure failed (%d)\n", err); 2595114840c3SJack Morgenstein goto out; 2596114840c3SJack Morgenstein } 2597114840c3SJack Morgenstein 2598114840c3SJack Morgenstein if (secure_host_active) 2599114840c3SJack Morgenstein mlx4_warn(dev, "HCA operating in secure-host mode. SMP firewall activated.\n"); 2600114840c3SJack Morgenstein out: 2601114840c3SJack Morgenstein mlx4_free_cmd_mailbox(dev, mailbox); 2602114840c3SJack Morgenstein return err; 2603114840c3SJack Morgenstein } 2604adbc7ac5SSaeed Mahameed 2605adbc7ac5SSaeed Mahameed /* Access Reg commands */ 2606adbc7ac5SSaeed Mahameed enum mlx4_access_reg_masks { 2607adbc7ac5SSaeed Mahameed MLX4_ACCESS_REG_STATUS_MASK = 0x7f, 2608adbc7ac5SSaeed Mahameed MLX4_ACCESS_REG_METHOD_MASK = 0x7f, 2609adbc7ac5SSaeed Mahameed MLX4_ACCESS_REG_LEN_MASK = 0x7ff 2610adbc7ac5SSaeed Mahameed }; 2611adbc7ac5SSaeed Mahameed 2612adbc7ac5SSaeed Mahameed struct mlx4_access_reg { 2613adbc7ac5SSaeed Mahameed __be16 constant1; 2614adbc7ac5SSaeed Mahameed u8 status; 2615adbc7ac5SSaeed Mahameed u8 resrvd1; 2616adbc7ac5SSaeed Mahameed __be16 reg_id; 2617adbc7ac5SSaeed Mahameed u8 method; 2618adbc7ac5SSaeed Mahameed u8 constant2; 2619adbc7ac5SSaeed Mahameed __be32 resrvd2[2]; 2620adbc7ac5SSaeed Mahameed __be16 len_const; 2621adbc7ac5SSaeed Mahameed __be16 resrvd3; 2622adbc7ac5SSaeed Mahameed #define MLX4_ACCESS_REG_HEADER_SIZE (20) 2623adbc7ac5SSaeed Mahameed u8 reg_data[MLX4_MAILBOX_SIZE-MLX4_ACCESS_REG_HEADER_SIZE]; 2624adbc7ac5SSaeed Mahameed } __attribute__((__packed__)); 2625adbc7ac5SSaeed Mahameed 2626adbc7ac5SSaeed Mahameed /** 2627adbc7ac5SSaeed Mahameed * mlx4_ACCESS_REG - Generic access reg command. 2628adbc7ac5SSaeed Mahameed * @dev: mlx4_dev. 2629adbc7ac5SSaeed Mahameed * @reg_id: register ID to access. 2630adbc7ac5SSaeed Mahameed * @method: Access method Read/Write. 2631adbc7ac5SSaeed Mahameed * @reg_len: register length to Read/Write in bytes. 2632adbc7ac5SSaeed Mahameed * @reg_data: reg_data pointer to Read/Write From/To. 2633adbc7ac5SSaeed Mahameed * 2634adbc7ac5SSaeed Mahameed * Access ConnectX registers FW command. 2635adbc7ac5SSaeed Mahameed * Returns 0 on success and copies outbox mlx4_access_reg data 2636adbc7ac5SSaeed Mahameed * field into reg_data or a negative error code. 2637adbc7ac5SSaeed Mahameed */ 2638adbc7ac5SSaeed Mahameed static int mlx4_ACCESS_REG(struct mlx4_dev *dev, u16 reg_id, 2639adbc7ac5SSaeed Mahameed enum mlx4_access_reg_method method, 2640adbc7ac5SSaeed Mahameed u16 reg_len, void *reg_data) 2641adbc7ac5SSaeed Mahameed { 2642adbc7ac5SSaeed Mahameed struct mlx4_cmd_mailbox *inbox, *outbox; 2643adbc7ac5SSaeed Mahameed struct mlx4_access_reg *inbuf, *outbuf; 2644adbc7ac5SSaeed Mahameed int err; 2645adbc7ac5SSaeed Mahameed 2646adbc7ac5SSaeed Mahameed inbox = mlx4_alloc_cmd_mailbox(dev); 2647adbc7ac5SSaeed Mahameed if (IS_ERR(inbox)) 2648adbc7ac5SSaeed Mahameed return PTR_ERR(inbox); 2649adbc7ac5SSaeed Mahameed 2650adbc7ac5SSaeed Mahameed outbox = mlx4_alloc_cmd_mailbox(dev); 2651adbc7ac5SSaeed Mahameed if (IS_ERR(outbox)) { 2652adbc7ac5SSaeed Mahameed mlx4_free_cmd_mailbox(dev, inbox); 2653adbc7ac5SSaeed Mahameed return PTR_ERR(outbox); 2654adbc7ac5SSaeed Mahameed } 2655adbc7ac5SSaeed Mahameed 2656adbc7ac5SSaeed Mahameed inbuf = inbox->buf; 2657adbc7ac5SSaeed Mahameed outbuf = outbox->buf; 2658adbc7ac5SSaeed Mahameed 2659adbc7ac5SSaeed Mahameed inbuf->constant1 = cpu_to_be16(0x1<<11 | 0x4); 2660adbc7ac5SSaeed Mahameed inbuf->constant2 = 0x1; 2661adbc7ac5SSaeed Mahameed inbuf->reg_id = cpu_to_be16(reg_id); 2662adbc7ac5SSaeed Mahameed inbuf->method = method & MLX4_ACCESS_REG_METHOD_MASK; 2663adbc7ac5SSaeed Mahameed 2664adbc7ac5SSaeed Mahameed reg_len = min(reg_len, (u16)(sizeof(inbuf->reg_data))); 2665adbc7ac5SSaeed Mahameed inbuf->len_const = 2666adbc7ac5SSaeed Mahameed cpu_to_be16(((reg_len/4 + 1) & MLX4_ACCESS_REG_LEN_MASK) | 2667adbc7ac5SSaeed Mahameed ((0x3) << 12)); 2668adbc7ac5SSaeed Mahameed 2669adbc7ac5SSaeed Mahameed memcpy(inbuf->reg_data, reg_data, reg_len); 2670adbc7ac5SSaeed Mahameed err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, 0, 0, 2671adbc7ac5SSaeed Mahameed MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C, 26726e806699SSaeed Mahameed MLX4_CMD_WRAPPED); 2673adbc7ac5SSaeed Mahameed if (err) 2674adbc7ac5SSaeed Mahameed goto out; 2675adbc7ac5SSaeed Mahameed 2676adbc7ac5SSaeed Mahameed if (outbuf->status & MLX4_ACCESS_REG_STATUS_MASK) { 2677adbc7ac5SSaeed Mahameed err = outbuf->status & MLX4_ACCESS_REG_STATUS_MASK; 2678adbc7ac5SSaeed Mahameed mlx4_err(dev, 2679adbc7ac5SSaeed Mahameed "MLX4_CMD_ACCESS_REG(%x) returned REG status (%x)\n", 2680adbc7ac5SSaeed Mahameed reg_id, err); 2681adbc7ac5SSaeed Mahameed goto out; 2682adbc7ac5SSaeed Mahameed } 2683adbc7ac5SSaeed Mahameed 2684adbc7ac5SSaeed Mahameed memcpy(reg_data, outbuf->reg_data, reg_len); 2685adbc7ac5SSaeed Mahameed out: 2686adbc7ac5SSaeed Mahameed mlx4_free_cmd_mailbox(dev, inbox); 2687adbc7ac5SSaeed Mahameed mlx4_free_cmd_mailbox(dev, outbox); 2688adbc7ac5SSaeed Mahameed return err; 2689adbc7ac5SSaeed Mahameed } 2690adbc7ac5SSaeed Mahameed 2691adbc7ac5SSaeed Mahameed /* ConnectX registers IDs */ 2692adbc7ac5SSaeed Mahameed enum mlx4_reg_id { 2693adbc7ac5SSaeed Mahameed MLX4_REG_ID_PTYS = 0x5004, 2694adbc7ac5SSaeed Mahameed }; 2695adbc7ac5SSaeed Mahameed 2696adbc7ac5SSaeed Mahameed /** 2697adbc7ac5SSaeed Mahameed * mlx4_ACCESS_PTYS_REG - Access PTYs (Port Type and Speed) 2698adbc7ac5SSaeed Mahameed * register 2699adbc7ac5SSaeed Mahameed * @dev: mlx4_dev. 2700adbc7ac5SSaeed Mahameed * @method: Access method Read/Write. 2701adbc7ac5SSaeed Mahameed * @ptys_reg: PTYS register data pointer. 2702adbc7ac5SSaeed Mahameed * 2703adbc7ac5SSaeed Mahameed * Access ConnectX PTYS register, to Read/Write Port Type/Speed 2704adbc7ac5SSaeed Mahameed * configuration 2705adbc7ac5SSaeed Mahameed * Returns 0 on success or a negative error code. 2706adbc7ac5SSaeed Mahameed */ 2707adbc7ac5SSaeed Mahameed int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev, 2708adbc7ac5SSaeed Mahameed enum mlx4_access_reg_method method, 2709adbc7ac5SSaeed Mahameed struct mlx4_ptys_reg *ptys_reg) 2710adbc7ac5SSaeed Mahameed { 2711adbc7ac5SSaeed Mahameed return mlx4_ACCESS_REG(dev, MLX4_REG_ID_PTYS, 2712adbc7ac5SSaeed Mahameed method, sizeof(*ptys_reg), ptys_reg); 2713adbc7ac5SSaeed Mahameed } 2714adbc7ac5SSaeed Mahameed EXPORT_SYMBOL_GPL(mlx4_ACCESS_PTYS_REG); 27156e806699SSaeed Mahameed 27166e806699SSaeed Mahameed int mlx4_ACCESS_REG_wrapper(struct mlx4_dev *dev, int slave, 27176e806699SSaeed Mahameed struct mlx4_vhcr *vhcr, 27186e806699SSaeed Mahameed struct mlx4_cmd_mailbox *inbox, 27196e806699SSaeed Mahameed struct mlx4_cmd_mailbox *outbox, 27206e806699SSaeed Mahameed struct mlx4_cmd_info *cmd) 27216e806699SSaeed Mahameed { 27226e806699SSaeed Mahameed struct mlx4_access_reg *inbuf = inbox->buf; 27236e806699SSaeed Mahameed u8 method = inbuf->method & MLX4_ACCESS_REG_METHOD_MASK; 27246e806699SSaeed Mahameed u16 reg_id = be16_to_cpu(inbuf->reg_id); 27256e806699SSaeed Mahameed 27266e806699SSaeed Mahameed if (slave != mlx4_master_func_num(dev) && 27276e806699SSaeed Mahameed method == MLX4_ACCESS_REG_WRITE) 27286e806699SSaeed Mahameed return -EPERM; 27296e806699SSaeed Mahameed 27306e806699SSaeed Mahameed if (reg_id == MLX4_REG_ID_PTYS) { 27316e806699SSaeed Mahameed struct mlx4_ptys_reg *ptys_reg = 27326e806699SSaeed Mahameed (struct mlx4_ptys_reg *)inbuf->reg_data; 27336e806699SSaeed Mahameed 27346e806699SSaeed Mahameed ptys_reg->local_port = 27356e806699SSaeed Mahameed mlx4_slave_convert_port(dev, slave, 27366e806699SSaeed Mahameed ptys_reg->local_port); 27376e806699SSaeed Mahameed } 27386e806699SSaeed Mahameed 27396e806699SSaeed Mahameed return mlx4_cmd_box(dev, inbox->dma, outbox->dma, vhcr->in_modifier, 27406e806699SSaeed Mahameed 0, MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C, 27416e806699SSaeed Mahameed MLX4_CMD_NATIVE); 27426e806699SSaeed Mahameed } 2743